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-rw-r--r--sound/pci/hda/hda_intel.c366
-rw-r--r--sound/pci/hda/hda_priv.h398
2 files changed, 399 insertions, 365 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index e8a9e87ac074..da717b5223c4 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -63,6 +63,7 @@
63#include <linux/firmware.h> 63#include <linux/firmware.h>
64#include "hda_codec.h" 64#include "hda_codec.h"
65#include "hda_i915.h" 65#include "hda_i915.h"
66#include "hda_priv.h"
66 67
67 68
68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 69static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
@@ -149,10 +150,8 @@ MODULE_PARM_DESC(align_buffer_size,
149static bool hda_snoop = true; 150static bool hda_snoop = true;
150module_param_named(snoop, hda_snoop, bool, 0444); 151module_param_named(snoop, hda_snoop, bool, 0444);
151MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 152MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152#define azx_snoop(chip) (chip)->snoop
153#else 153#else
154#define hda_snoop true 154#define hda_snoop true
155#define azx_snoop(chip) true
156#endif 155#endif
157 156
158 157
@@ -199,238 +198,7 @@ MODULE_DESCRIPTION("Intel HDA driver");
199 198
200 199
201/* 200/*
202 * registers
203 */ 201 */
204#define ICH6_REG_GCAP 0x00
205#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
206#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
207#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
208#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
209#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
210#define ICH6_REG_VMIN 0x02
211#define ICH6_REG_VMAJ 0x03
212#define ICH6_REG_OUTPAY 0x04
213#define ICH6_REG_INPAY 0x06
214#define ICH6_REG_GCTL 0x08
215#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
216#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
217#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
218#define ICH6_REG_WAKEEN 0x0c
219#define ICH6_REG_STATESTS 0x0e
220#define ICH6_REG_GSTS 0x10
221#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
222#define ICH6_REG_INTCTL 0x20
223#define ICH6_REG_INTSTS 0x24
224#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
225#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
226#define ICH6_REG_SSYNC 0x38
227#define ICH6_REG_CORBLBASE 0x40
228#define ICH6_REG_CORBUBASE 0x44
229#define ICH6_REG_CORBWP 0x48
230#define ICH6_REG_CORBRP 0x4a
231#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
232#define ICH6_REG_CORBCTL 0x4c
233#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
234#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
235#define ICH6_REG_CORBSTS 0x4d
236#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
237#define ICH6_REG_CORBSIZE 0x4e
238
239#define ICH6_REG_RIRBLBASE 0x50
240#define ICH6_REG_RIRBUBASE 0x54
241#define ICH6_REG_RIRBWP 0x58
242#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
243#define ICH6_REG_RINTCNT 0x5a
244#define ICH6_REG_RIRBCTL 0x5c
245#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
246#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
247#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
248#define ICH6_REG_RIRBSTS 0x5d
249#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
250#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
251#define ICH6_REG_RIRBSIZE 0x5e
252
253#define ICH6_REG_IC 0x60
254#define ICH6_REG_IR 0x64
255#define ICH6_REG_IRS 0x68
256#define ICH6_IRS_VALID (1<<1)
257#define ICH6_IRS_BUSY (1<<0)
258
259#define ICH6_REG_DPLBASE 0x70
260#define ICH6_REG_DPUBASE 0x74
261#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
262
263/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
264enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
265
266/* stream register offsets from stream base */
267#define ICH6_REG_SD_CTL 0x00
268#define ICH6_REG_SD_STS 0x03
269#define ICH6_REG_SD_LPIB 0x04
270#define ICH6_REG_SD_CBL 0x08
271#define ICH6_REG_SD_LVI 0x0c
272#define ICH6_REG_SD_FIFOW 0x0e
273#define ICH6_REG_SD_FIFOSIZE 0x10
274#define ICH6_REG_SD_FORMAT 0x12
275#define ICH6_REG_SD_BDLPL 0x18
276#define ICH6_REG_SD_BDLPU 0x1c
277
278/* PCI space */
279#define ICH6_PCIREG_TCSEL 0x44
280
281/*
282 * other constants
283 */
284
285/* max number of SDs */
286/* ICH, ATI and VIA have 4 playback and 4 capture */
287#define ICH6_NUM_CAPTURE 4
288#define ICH6_NUM_PLAYBACK 4
289
290/* ULI has 6 playback and 5 capture */
291#define ULI_NUM_CAPTURE 5
292#define ULI_NUM_PLAYBACK 6
293
294/* ATI HDMI may have up to 8 playbacks and 0 capture */
295#define ATIHDMI_NUM_CAPTURE 0
296#define ATIHDMI_NUM_PLAYBACK 8
297
298/* TERA has 4 playback and 3 capture */
299#define TERA_NUM_CAPTURE 3
300#define TERA_NUM_PLAYBACK 4
301
302/* this number is statically defined for simplicity */
303#define MAX_AZX_DEV 16
304
305/* max number of fragments - we may use more if allocating more pages for BDL */
306#define BDL_SIZE 4096
307#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
308#define AZX_MAX_FRAG 32
309/* max buffer size - no h/w limit, you can increase as you like */
310#define AZX_MAX_BUF_SIZE (1024*1024*1024)
311
312/* RIRB int mask: overrun[2], response[0] */
313#define RIRB_INT_RESPONSE 0x01
314#define RIRB_INT_OVERRUN 0x04
315#define RIRB_INT_MASK 0x05
316
317/* STATESTS int mask: S3,SD2,SD1,SD0 */
318#define AZX_MAX_CODECS 8
319#define AZX_DEFAULT_CODECS 4
320#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
321
322/* SD_CTL bits */
323#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
324#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
325#define SD_CTL_STRIPE (3 << 16) /* stripe control */
326#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
327#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
328#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
329#define SD_CTL_STREAM_TAG_SHIFT 20
330
331/* SD_CTL and SD_STS */
332#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
333#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
334#define SD_INT_COMPLETE 0x04 /* completion interrupt */
335#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
336 SD_INT_COMPLETE)
337
338/* SD_STS */
339#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
340
341/* INTCTL and INTSTS */
342#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
343#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
344#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
345
346/* below are so far hardcoded - should read registers in future */
347#define ICH6_MAX_CORB_ENTRIES 256
348#define ICH6_MAX_RIRB_ENTRIES 256
349
350/* position fix mode */
351enum {
352 POS_FIX_AUTO,
353 POS_FIX_LPIB,
354 POS_FIX_POSBUF,
355 POS_FIX_VIACOMBO,
356 POS_FIX_COMBO,
357};
358
359/* Defines for ATI HD Audio support in SB450 south bridge */
360#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
361#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
362
363/* Defines for Nvidia HDA support */
364#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
365#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
366#define NVIDIA_HDA_ISTRM_COH 0x4d
367#define NVIDIA_HDA_OSTRM_COH 0x4c
368#define NVIDIA_HDA_ENABLE_COHBIT 0x01
369
370/* Defines for Intel SCH HDA snoop control */
371#define INTEL_SCH_HDA_DEVC 0x78
372#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
373
374/* Define IN stream 0 FIFO size offset in VIA controller */
375#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
376/* Define VIA HD Audio Device ID*/
377#define VIA_HDAC_DEVICE_ID 0x3288
378
379/* HD Audio class code */
380#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
381
382/*
383 */
384
385struct azx_dev {
386 struct snd_dma_buffer bdl; /* BDL buffer */
387 u32 *posbuf; /* position buffer pointer */
388
389 unsigned int bufsize; /* size of the play buffer in bytes */
390 unsigned int period_bytes; /* size of the period in bytes */
391 unsigned int frags; /* number for period in the play buffer */
392 unsigned int fifo_size; /* FIFO size */
393 unsigned long start_wallclk; /* start + minimum wallclk */
394 unsigned long period_wallclk; /* wallclk for period */
395
396 void __iomem *sd_addr; /* stream descriptor pointer */
397
398 u32 sd_int_sta_mask; /* stream int status mask */
399
400 /* pcm support */
401 struct snd_pcm_substream *substream; /* assigned substream,
402 * set in PCM open
403 */
404 unsigned int format_val; /* format value to be set in the
405 * controller and the codec
406 */
407 unsigned char stream_tag; /* assigned stream */
408 unsigned char index; /* stream index */
409 int assigned_key; /* last device# key assigned to */
410
411 unsigned int opened :1;
412 unsigned int running :1;
413 unsigned int irq_pending :1;
414 unsigned int prepared:1;
415 unsigned int locked:1;
416 /*
417 * For VIA:
418 * A flag to ensure DMA position is 0
419 * when link position is not greater than FIFO size
420 */
421 unsigned int insufficient :1;
422 unsigned int wc_marked:1;
423 unsigned int no_period_wakeup:1;
424
425 struct timecounter azx_tc;
426 struct cyclecounter azx_cc;
427
428 int delay_negative_threshold;
429
430#ifdef CONFIG_SND_HDA_DSP_LOADER
431 struct mutex dsp_mutex;
432#endif
433};
434 202
435/* DSP lock helpers */ 203/* DSP lock helpers */
436#ifdef CONFIG_SND_HDA_DSP_LOADER 204#ifdef CONFIG_SND_HDA_DSP_LOADER
@@ -445,116 +213,6 @@ struct azx_dev {
445#define dsp_is_locked(dev) 0 213#define dsp_is_locked(dev) 0
446#endif 214#endif
447 215
448/* CORB/RIRB */
449struct azx_rb {
450 u32 *buf; /* CORB/RIRB buffer
451 * Each CORB entry is 4byte, RIRB is 8byte
452 */
453 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
454 /* for RIRB */
455 unsigned short rp, wp; /* read/write pointers */
456 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
457 u32 res[AZX_MAX_CODECS]; /* last read value */
458};
459
460struct azx_pcm {
461 struct azx *chip;
462 struct snd_pcm *pcm;
463 struct hda_codec *codec;
464 struct hda_pcm_stream *hinfo[2];
465 struct list_head list;
466};
467
468struct azx {
469 struct snd_card *card;
470 struct pci_dev *pci;
471 int dev_index;
472
473 /* chip type specific */
474 int driver_type;
475 unsigned int driver_caps;
476 int playback_streams;
477 int playback_index_offset;
478 int capture_streams;
479 int capture_index_offset;
480 int num_streams;
481
482 /* pci resources */
483 unsigned long addr;
484 void __iomem *remap_addr;
485 int irq;
486
487 /* locks */
488 spinlock_t reg_lock;
489 struct mutex open_mutex;
490 struct completion probe_wait;
491
492 /* streams (x num_streams) */
493 struct azx_dev *azx_dev;
494
495 /* PCM */
496 struct list_head pcm_list; /* azx_pcm list */
497
498 /* HD codec */
499 unsigned short codec_mask;
500 int codec_probe_mask; /* copied from probe_mask option */
501 struct hda_bus *bus;
502 unsigned int beep_mode;
503
504 /* CORB/RIRB */
505 struct azx_rb corb;
506 struct azx_rb rirb;
507
508 /* CORB/RIRB and position buffers */
509 struct snd_dma_buffer rb;
510 struct snd_dma_buffer posbuf;
511
512#ifdef CONFIG_SND_HDA_PATCH_LOADER
513 const struct firmware *fw;
514#endif
515
516 /* flags */
517 int position_fix[2]; /* for both playback/capture streams */
518 int poll_count;
519 unsigned int running :1;
520 unsigned int initialized :1;
521 unsigned int single_cmd :1;
522 unsigned int polling_mode :1;
523 unsigned int msi :1;
524 unsigned int irq_pending_warned :1;
525 unsigned int probing :1; /* codec probing phase */
526 unsigned int snoop:1;
527 unsigned int align_buffer_size:1;
528 unsigned int region_requested:1;
529
530 /* VGA-switcheroo setup */
531 unsigned int use_vga_switcheroo:1;
532 unsigned int vga_switcheroo_registered:1;
533 unsigned int init_failed:1; /* delayed init failed */
534 unsigned int disabled:1; /* disabled by VGA-switcher */
535
536 /* for debugging */
537 unsigned int last_cmd[AZX_MAX_CODECS];
538
539 /* for pending irqs */
540 struct work_struct irq_pending_work;
541
542 struct work_struct probe_work;
543
544 /* reboot notifier (for mysterious hangup problem at power-down) */
545 struct notifier_block reboot_notifier;
546
547 /* card list (for power_save trigger) */
548 struct list_head list;
549
550#ifdef CONFIG_SND_HDA_DSP_LOADER
551 struct azx_dev saved_azx_dev;
552#endif
553
554 /* secondary power domain for hdmi audio under vga device */
555 struct dev_pm_domain hdmi_pm_domain;
556};
557
558#define CREATE_TRACE_POINTS 216#define CREATE_TRACE_POINTS
559#include "hda_intel_trace.h" 217#include "hda_intel_trace.h"
560 218
@@ -578,28 +236,6 @@ enum {
578 AZX_NUM_DRIVERS, /* keep this as last entry */ 236 AZX_NUM_DRIVERS, /* keep this as last entry */
579}; 237};
580 238
581/* driver quirks (capabilities) */
582/* bits 0-7 are used for indicating driver type */
583#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
584#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
585#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
586#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
587#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
588#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
589#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
590#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
591#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
592#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
593#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
594#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
595#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
596#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
597#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
598#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
599#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
600#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
601#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
602
603/* quirks for Intel PCH */ 239/* quirks for Intel PCH */
604#define AZX_DCAPS_INTEL_PCH_NOPM \ 240#define AZX_DCAPS_INTEL_PCH_NOPM \
605 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ 241 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
diff --git a/sound/pci/hda/hda_priv.h b/sound/pci/hda/hda_priv.h
new file mode 100644
index 000000000000..765649458a20
--- /dev/null
+++ b/sound/pci/hda/hda_priv.h
@@ -0,0 +1,398 @@
1/*
2 * Common defines for the alsa driver code base for HD Audio.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __SOUND_HDA_PRIV_H
16#define __SOUND_HDA_PRIV_H
17
18#include <linux/clocksource.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21
22/*
23 * registers
24 */
25#define ICH6_REG_GCAP 0x00
26#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
27#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
28#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
29#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
30#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
31#define ICH6_REG_VMIN 0x02
32#define ICH6_REG_VMAJ 0x03
33#define ICH6_REG_OUTPAY 0x04
34#define ICH6_REG_INPAY 0x06
35#define ICH6_REG_GCTL 0x08
36#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
37#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
38#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
39#define ICH6_REG_WAKEEN 0x0c
40#define ICH6_REG_STATESTS 0x0e
41#define ICH6_REG_GSTS 0x10
42#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
43#define ICH6_REG_INTCTL 0x20
44#define ICH6_REG_INTSTS 0x24
45#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
46#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
47#define ICH6_REG_SSYNC 0x38
48#define ICH6_REG_CORBLBASE 0x40
49#define ICH6_REG_CORBUBASE 0x44
50#define ICH6_REG_CORBWP 0x48
51#define ICH6_REG_CORBRP 0x4a
52#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
53#define ICH6_REG_CORBCTL 0x4c
54#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
55#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
56#define ICH6_REG_CORBSTS 0x4d
57#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
58#define ICH6_REG_CORBSIZE 0x4e
59
60#define ICH6_REG_RIRBLBASE 0x50
61#define ICH6_REG_RIRBUBASE 0x54
62#define ICH6_REG_RIRBWP 0x58
63#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
64#define ICH6_REG_RINTCNT 0x5a
65#define ICH6_REG_RIRBCTL 0x5c
66#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
67#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
68#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
69#define ICH6_REG_RIRBSTS 0x5d
70#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
71#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
72#define ICH6_REG_RIRBSIZE 0x5e
73
74#define ICH6_REG_IC 0x60
75#define ICH6_REG_IR 0x64
76#define ICH6_REG_IRS 0x68
77#define ICH6_IRS_VALID (1<<1)
78#define ICH6_IRS_BUSY (1<<0)
79
80#define ICH6_REG_DPLBASE 0x70
81#define ICH6_REG_DPUBASE 0x74
82#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
83
84/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
85enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
86
87/* stream register offsets from stream base */
88#define ICH6_REG_SD_CTL 0x00
89#define ICH6_REG_SD_STS 0x03
90#define ICH6_REG_SD_LPIB 0x04
91#define ICH6_REG_SD_CBL 0x08
92#define ICH6_REG_SD_LVI 0x0c
93#define ICH6_REG_SD_FIFOW 0x0e
94#define ICH6_REG_SD_FIFOSIZE 0x10
95#define ICH6_REG_SD_FORMAT 0x12
96#define ICH6_REG_SD_BDLPL 0x18
97#define ICH6_REG_SD_BDLPU 0x1c
98
99/* PCI space */
100#define ICH6_PCIREG_TCSEL 0x44
101
102/*
103 * other constants
104 */
105
106/* max number of SDs */
107/* ICH, ATI and VIA have 4 playback and 4 capture */
108#define ICH6_NUM_CAPTURE 4
109#define ICH6_NUM_PLAYBACK 4
110
111/* ULI has 6 playback and 5 capture */
112#define ULI_NUM_CAPTURE 5
113#define ULI_NUM_PLAYBACK 6
114
115/* ATI HDMI may have up to 8 playbacks and 0 capture */
116#define ATIHDMI_NUM_CAPTURE 0
117#define ATIHDMI_NUM_PLAYBACK 8
118
119/* TERA has 4 playback and 3 capture */
120#define TERA_NUM_CAPTURE 3
121#define TERA_NUM_PLAYBACK 4
122
123/* this number is statically defined for simplicity */
124#define MAX_AZX_DEV 16
125
126/* max number of fragments - we may use more if allocating more pages for BDL */
127#define BDL_SIZE 4096
128#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
129#define AZX_MAX_FRAG 32
130/* max buffer size - no h/w limit, you can increase as you like */
131#define AZX_MAX_BUF_SIZE (1024*1024*1024)
132
133/* RIRB int mask: overrun[2], response[0] */
134#define RIRB_INT_RESPONSE 0x01
135#define RIRB_INT_OVERRUN 0x04
136#define RIRB_INT_MASK 0x05
137
138/* STATESTS int mask: S3,SD2,SD1,SD0 */
139#define AZX_MAX_CODECS 8
140#define AZX_DEFAULT_CODECS 4
141#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
142
143/* SD_CTL bits */
144#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
145#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
146#define SD_CTL_STRIPE (3 << 16) /* stripe control */
147#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
148#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
149#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
150#define SD_CTL_STREAM_TAG_SHIFT 20
151
152/* SD_CTL and SD_STS */
153#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
154#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
155#define SD_INT_COMPLETE 0x04 /* completion interrupt */
156#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
157 SD_INT_COMPLETE)
158
159/* SD_STS */
160#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
161
162/* INTCTL and INTSTS */
163#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
164#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
165#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
166
167/* below are so far hardcoded - should read registers in future */
168#define ICH6_MAX_CORB_ENTRIES 256
169#define ICH6_MAX_RIRB_ENTRIES 256
170
171/* driver quirks (capabilities) */
172/* bits 0-7 are used for indicating driver type */
173#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
174#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
175#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
176#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
177#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
178#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
179#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
180#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
181#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
182#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
183#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
184#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
185#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
186#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
187#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
188#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
189#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
190#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
191#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
192
193/* position fix mode */
194enum {
195 POS_FIX_AUTO,
196 POS_FIX_LPIB,
197 POS_FIX_POSBUF,
198 POS_FIX_VIACOMBO,
199 POS_FIX_COMBO,
200};
201
202/* Defines for ATI HD Audio support in SB450 south bridge */
203#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
204#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
205
206/* Defines for Nvidia HDA support */
207#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
208#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
209#define NVIDIA_HDA_ISTRM_COH 0x4d
210#define NVIDIA_HDA_OSTRM_COH 0x4c
211#define NVIDIA_HDA_ENABLE_COHBIT 0x01
212
213/* Defines for Intel SCH HDA snoop control */
214#define INTEL_SCH_HDA_DEVC 0x78
215#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
216
217/* Define IN stream 0 FIFO size offset in VIA controller */
218#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
219/* Define VIA HD Audio Device ID*/
220#define VIA_HDAC_DEVICE_ID 0x3288
221
222/* HD Audio class code */
223#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
224
225struct azx_dev {
226 struct snd_dma_buffer bdl; /* BDL buffer */
227 u32 *posbuf; /* position buffer pointer */
228
229 unsigned int bufsize; /* size of the play buffer in bytes */
230 unsigned int period_bytes; /* size of the period in bytes */
231 unsigned int frags; /* number for period in the play buffer */
232 unsigned int fifo_size; /* FIFO size */
233 unsigned long start_wallclk; /* start + minimum wallclk */
234 unsigned long period_wallclk; /* wallclk for period */
235
236 void __iomem *sd_addr; /* stream descriptor pointer */
237
238 u32 sd_int_sta_mask; /* stream int status mask */
239
240 /* pcm support */
241 struct snd_pcm_substream *substream; /* assigned substream,
242 * set in PCM open
243 */
244 unsigned int format_val; /* format value to be set in the
245 * controller and the codec
246 */
247 unsigned char stream_tag; /* assigned stream */
248 unsigned char index; /* stream index */
249 int assigned_key; /* last device# key assigned to */
250
251 unsigned int opened:1;
252 unsigned int running:1;
253 unsigned int irq_pending:1;
254 unsigned int prepared:1;
255 unsigned int locked:1;
256 /*
257 * For VIA:
258 * A flag to ensure DMA position is 0
259 * when link position is not greater than FIFO size
260 */
261 unsigned int insufficient:1;
262 unsigned int wc_marked:1;
263 unsigned int no_period_wakeup:1;
264
265 struct timecounter azx_tc;
266 struct cyclecounter azx_cc;
267
268 int delay_negative_threshold;
269
270#ifdef CONFIG_SND_HDA_DSP_LOADER
271 /* Allows dsp load to have sole access to the playback stream. */
272 struct mutex dsp_mutex;
273#endif
274};
275
276/* CORB/RIRB */
277struct azx_rb {
278 u32 *buf; /* CORB/RIRB buffer
279 * Each CORB entry is 4byte, RIRB is 8byte
280 */
281 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
282 /* for RIRB */
283 unsigned short rp, wp; /* read/write pointers */
284 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
285 u32 res[AZX_MAX_CODECS]; /* last read value */
286};
287
288struct azx_pcm {
289 struct azx *chip;
290 struct snd_pcm *pcm;
291 struct hda_codec *codec;
292 struct hda_pcm_stream *hinfo[2];
293 struct list_head list;
294};
295
296struct azx {
297 struct snd_card *card;
298 struct pci_dev *pci;
299 int dev_index;
300
301 /* chip type specific */
302 int driver_type;
303 unsigned int driver_caps;
304 int playback_streams;
305 int playback_index_offset;
306 int capture_streams;
307 int capture_index_offset;
308 int num_streams;
309
310 /* pci resources */
311 unsigned long addr;
312 void __iomem *remap_addr;
313 int irq;
314
315 /* locks */
316 spinlock_t reg_lock;
317 struct mutex open_mutex; /* Prevents concurrent open/close operations */
318 struct completion probe_wait;
319
320 /* streams (x num_streams) */
321 struct azx_dev *azx_dev;
322
323 /* PCM */
324 struct list_head pcm_list; /* azx_pcm list */
325
326 /* HD codec */
327 unsigned short codec_mask;
328 int codec_probe_mask; /* copied from probe_mask option */
329 struct hda_bus *bus;
330 unsigned int beep_mode;
331
332 /* CORB/RIRB */
333 struct azx_rb corb;
334 struct azx_rb rirb;
335
336 /* CORB/RIRB and position buffers */
337 struct snd_dma_buffer rb;
338 struct snd_dma_buffer posbuf;
339
340#ifdef CONFIG_SND_HDA_PATCH_LOADER
341 const struct firmware *fw;
342#endif
343
344 /* flags */
345 int position_fix[2]; /* for both playback/capture streams */
346 int poll_count;
347 unsigned int running:1;
348 unsigned int initialized:1;
349 unsigned int single_cmd:1;
350 unsigned int polling_mode:1;
351 unsigned int msi:1;
352 unsigned int irq_pending_warned:1;
353 unsigned int probing:1; /* codec probing phase */
354 unsigned int snoop:1;
355 unsigned int align_buffer_size:1;
356 unsigned int region_requested:1;
357
358 /* VGA-switcheroo setup */
359 unsigned int use_vga_switcheroo:1;
360 unsigned int vga_switcheroo_registered:1;
361 unsigned int init_failed:1; /* delayed init failed */
362 unsigned int disabled:1; /* disabled by VGA-switcher */
363
364 /* for debugging */
365 unsigned int last_cmd[AZX_MAX_CODECS];
366
367 /* for pending irqs */
368 struct work_struct irq_pending_work;
369
370 struct work_struct probe_work;
371
372 /* reboot notifier (for mysterious hangup problem at power-down) */
373 struct notifier_block reboot_notifier;
374
375 /* card list (for power_save trigger) */
376 struct list_head list;
377
378#ifdef CONFIG_SND_HDA_DSP_LOADER
379 struct azx_dev saved_azx_dev;
380#endif
381
382 /* secondary power domain for hdmi audio under vga device */
383 struct dev_pm_domain hdmi_pm_domain;
384};
385
386#ifdef CONFIG_SND_VERBOSE_PRINTK
387#define SFX /* nop */
388#else
389#define SFX "hda-intel "
390#endif
391
392#ifdef CONFIG_X86
393#define azx_snoop(chip) ((chip)->snoop)
394#else
395#define azx_snoop(chip) true
396#endif
397
398#endif /* __SOUND_HDA_PRIV_H */