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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c19
2 files changed, 14 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b401788e1791..59afb7eb6db6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -533,6 +533,7 @@
533#define MI_MODE 0x0209c 533#define MI_MODE 0x0209c
534# define VS_TIMER_DISPATCH (1 << 6) 534# define VS_TIMER_DISPATCH (1 << 6)
535# define MI_FLUSH_ENABLE (1 << 12) 535# define MI_FLUSH_ENABLE (1 << 12)
536# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
536 537
537#define GEN6_GT_MODE 0x20d0 538#define GEN6_GT_MODE 0x20d0
538#define GEN6_GT_MODE_HI (1 << 9) 539#define GEN6_GT_MODE_HI (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ae253e04c391..1f46a8bf2b05 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -505,13 +505,20 @@ static int init_render_ring(struct intel_ring_buffer *ring)
505 struct drm_i915_private *dev_priv = dev->dev_private; 505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring); 506 int ret = init_ring_common(ring);
507 507
508 if (INTEL_INFO(dev)->gen > 3) { 508 if (INTEL_INFO(dev)->gen > 3)
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); 509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
510 if (IS_GEN7(dev)) 510
511 I915_WRITE(GFX_MODE_GEN7, 511 /* We need to disable the AsyncFlip performance optimisations in order
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | 512 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); 513 * programmed to '1' on all products.
514 } 514 */
515 if (INTEL_INFO(dev)->gen >= 6)
516 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
517
518 if (IS_GEN7(dev))
519 I915_WRITE(GFX_MODE_GEN7,
520 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
521 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
515 522
516 if (INTEL_INFO(dev)->gen >= 5) { 523 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring); 524 ret = init_pipe_control(ring);