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-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts22
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts18
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts48
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi149
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi124
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi125
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi125
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts27
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts12
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts30
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi240
12 files changed, 711 insertions, 210 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0ae79496752c..a4d8b617e5bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
322 sun4i-a10-cubieboard.dtb \ 322 sun4i-a10-cubieboard.dtb \
323 sun4i-a10-mini-xplus.dtb \ 323 sun4i-a10-mini-xplus.dtb \
324 sun4i-a10-hackberry.dtb \ 324 sun4i-a10-hackberry.dtb \
325 sun4i-a10-pcduino.dtb \
325 sun5i-a10s-olinuxino-micro.dtb \ 326 sun5i-a10s-olinuxino-micro.dtb \
326 sun5i-a13-olinuxino.dtb \ 327 sun5i-a13-olinuxino.dtb \
327 sun5i-a13-olinuxino-micro.dtb \ 328 sun5i-a13-olinuxino-micro.dtb \
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index d4b081d6a167..cbd2e135bc09 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -80,18 +80,14 @@
80 }; 80 };
81 }; 81 };
82 82
83 regulators { 83 reg_emac_3v3: emac-3v3 {
84 compatible = "simple-bus"; 84 compatible = "regulator-fixed";
85 85 pinctrl-names = "default";
86 reg_emac_3v3: emac-3v3 { 86 pinctrl-0 = <&emac_power_pin_a1000>;
87 compatible = "regulator-fixed"; 87 regulator-name = "emac-3v3";
88 pinctrl-names = "default"; 88 regulator-min-microvolt = <3300000>;
89 pinctrl-0 = <&emac_power_pin_a1000>; 89 regulator-max-microvolt = <3300000>;
90 regulator-name = "emac-3v3"; 90 enable-active-high;
91 regulator-min-microvolt = <3300000>; 91 gpio = <&pio 7 15 0>;
92 regulator-max-microvolt = <3300000>;
93 enable-active-high;
94 gpio = <&pio 7 15 0>;
95 };
96 }; 92 };
97}; 93};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 3a1595f67823..6692d336335d 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -54,16 +54,12 @@
54 }; 54 };
55 }; 55 };
56 56
57 regulators { 57 reg_emac_3v3: emac-3v3 {
58 compatible = "simple-bus"; 58 compatible = "regulator-fixed";
59 59 regulator-name = "emac-3v3";
60 reg_emac_3v3: emac-3v3 { 60 regulator-min-microvolt = <3300000>;
61 compatible = "regulator-fixed"; 61 regulator-max-microvolt = <3300000>;
62 regulator-name = "emac-3v3"; 62 enable-active-high;
63 regulator-min-microvolt = <3300000>; 63 gpio = <&pio 7 19 0>;
64 regulator-max-microvolt = <3300000>;
65 enable-active-high;
66 gpio = <&pio 7 19 0>;
67 };
68 }; 64 };
69}; 65};
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
new file mode 100644
index 000000000000..f5692a3b80db
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "sun4i-a10.dtsi"
15
16/ {
17 model = "LinkSprite pcDuino";
18 compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
19
20 soc@01c00000 {
21 emac: ethernet@01c0b000 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&emac_pins_a>;
24 phy = <&phy1>;
25 status = "okay";
26 };
27
28 mdio@01c0b080 {
29 status = "okay";
30
31 phy1: ethernet-phy@1 {
32 reg = <1>;
33 };
34 };
35
36 uart0: serial@01c28000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&uart0_pins_a>;
39 status = "okay";
40 };
41
42 i2c0: i2c@01c2ac00 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&i2c0_pins_a>;
45 status = "okay";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 10666ca8aee1..a850482c69f1 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -19,6 +19,12 @@
19 ethernet0 = &emac; 19 ethernet0 = &emac;
20 serial0 = &uart0; 20 serial0 = &uart0;
21 serial1 = &uart1; 21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 serial6 = &uart6;
27 serial7 = &uart7;
22 }; 28 };
23 29
24 cpus { 30 cpus {
@@ -52,44 +58,48 @@
52 clock-frequency = <0>; 58 clock-frequency = <0>;
53 }; 59 };
54 60
55 osc24M: osc24M@01c20050 { 61 osc24M: clk@01c20050 {
56 #clock-cells = <0>; 62 #clock-cells = <0>;
57 compatible = "allwinner,sun4i-osc-clk"; 63 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>; 64 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>; 65 clock-frequency = <24000000>;
66 clock-output-names = "osc24M";
60 }; 67 };
61 68
62 osc32k: osc32k { 69 osc32k: clk@0 {
63 #clock-cells = <0>; 70 #clock-cells = <0>;
64 compatible = "fixed-clock"; 71 compatible = "fixed-clock";
65 clock-frequency = <32768>; 72 clock-frequency = <32768>;
73 clock-output-names = "osc32k";
66 }; 74 };
67 75
68 pll1: pll1@01c20000 { 76 pll1: clk@01c20000 {
69 #clock-cells = <0>; 77 #clock-cells = <0>;
70 compatible = "allwinner,sun4i-pll1-clk"; 78 compatible = "allwinner,sun4i-a10-pll1-clk";
71 reg = <0x01c20000 0x4>; 79 reg = <0x01c20000 0x4>;
72 clocks = <&osc24M>; 80 clocks = <&osc24M>;
81 clock-output-names = "pll1";
73 }; 82 };
74 83
75 pll4: pll4@01c20018 { 84 pll4: clk@01c20018 {
76 #clock-cells = <0>; 85 #clock-cells = <0>;
77 compatible = "allwinner,sun4i-pll1-clk"; 86 compatible = "allwinner,sun4i-a10-pll1-clk";
78 reg = <0x01c20018 0x4>; 87 reg = <0x01c20018 0x4>;
79 clocks = <&osc24M>; 88 clocks = <&osc24M>;
89 clock-output-names = "pll4";
80 }; 90 };
81 91
82 pll5: pll5@01c20020 { 92 pll5: clk@01c20020 {
83 #clock-cells = <1>; 93 #clock-cells = <1>;
84 compatible = "allwinner,sun4i-pll5-clk"; 94 compatible = "allwinner,sun4i-a10-pll5-clk";
85 reg = <0x01c20020 0x4>; 95 reg = <0x01c20020 0x4>;
86 clocks = <&osc24M>; 96 clocks = <&osc24M>;
87 clock-output-names = "pll5_ddr", "pll5_other"; 97 clock-output-names = "pll5_ddr", "pll5_other";
88 }; 98 };
89 99
90 pll6: pll6@01c20028 { 100 pll6: clk@01c20028 {
91 #clock-cells = <1>; 101 #clock-cells = <1>;
92 compatible = "allwinner,sun4i-pll6-clk"; 102 compatible = "allwinner,sun4i-a10-pll6-clk";
93 reg = <0x01c20028 0x4>; 103 reg = <0x01c20028 0x4>;
94 clocks = <&osc24M>; 104 clocks = <&osc24M>;
95 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 105 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -98,21 +108,23 @@
98 /* dummy is 200M */ 108 /* dummy is 200M */
99 cpu: cpu@01c20054 { 109 cpu: cpu@01c20054 {
100 #clock-cells = <0>; 110 #clock-cells = <0>;
101 compatible = "allwinner,sun4i-cpu-clk"; 111 compatible = "allwinner,sun4i-a10-cpu-clk";
102 reg = <0x01c20054 0x4>; 112 reg = <0x01c20054 0x4>;
103 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
114 clock-output-names = "cpu";
104 }; 115 };
105 116
106 axi: axi@01c20054 { 117 axi: axi@01c20054 {
107 #clock-cells = <0>; 118 #clock-cells = <0>;
108 compatible = "allwinner,sun4i-axi-clk"; 119 compatible = "allwinner,sun4i-a10-axi-clk";
109 reg = <0x01c20054 0x4>; 120 reg = <0x01c20054 0x4>;
110 clocks = <&cpu>; 121 clocks = <&cpu>;
122 clock-output-names = "axi";
111 }; 123 };
112 124
113 axi_gates: axi_gates@01c2005c { 125 axi_gates: clk@01c2005c {
114 #clock-cells = <1>; 126 #clock-cells = <1>;
115 compatible = "allwinner,sun4i-axi-gates-clk"; 127 compatible = "allwinner,sun4i-a10-axi-gates-clk";
116 reg = <0x01c2005c 0x4>; 128 reg = <0x01c2005c 0x4>;
117 clocks = <&axi>; 129 clocks = <&axi>;
118 clock-output-names = "axi_dram"; 130 clock-output-names = "axi_dram";
@@ -120,14 +132,15 @@
120 132
121 ahb: ahb@01c20054 { 133 ahb: ahb@01c20054 {
122 #clock-cells = <0>; 134 #clock-cells = <0>;
123 compatible = "allwinner,sun4i-ahb-clk"; 135 compatible = "allwinner,sun4i-a10-ahb-clk";
124 reg = <0x01c20054 0x4>; 136 reg = <0x01c20054 0x4>;
125 clocks = <&axi>; 137 clocks = <&axi>;
138 clock-output-names = "ahb";
126 }; 139 };
127 140
128 ahb_gates: ahb_gates@01c20060 { 141 ahb_gates: clk@01c20060 {
129 #clock-cells = <1>; 142 #clock-cells = <1>;
130 compatible = "allwinner,sun4i-ahb-gates-clk"; 143 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
131 reg = <0x01c20060 0x8>; 144 reg = <0x01c20060 0x8>;
132 clocks = <&ahb>; 145 clocks = <&ahb>;
133 clock-output-names = "ahb_usb0", "ahb_ehci0", 146 clock-output-names = "ahb_usb0", "ahb_ehci0",
@@ -145,14 +158,15 @@
145 158
146 apb0: apb0@01c20054 { 159 apb0: apb0@01c20054 {
147 #clock-cells = <0>; 160 #clock-cells = <0>;
148 compatible = "allwinner,sun4i-apb0-clk"; 161 compatible = "allwinner,sun4i-a10-apb0-clk";
149 reg = <0x01c20054 0x4>; 162 reg = <0x01c20054 0x4>;
150 clocks = <&ahb>; 163 clocks = <&ahb>;
164 clock-output-names = "apb0";
151 }; 165 };
152 166
153 apb0_gates: apb0_gates@01c20068 { 167 apb0_gates: clk@01c20068 {
154 #clock-cells = <1>; 168 #clock-cells = <1>;
155 compatible = "allwinner,sun4i-apb0-gates-clk"; 169 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
156 reg = <0x01c20068 0x4>; 170 reg = <0x01c20068 0x4>;
157 clocks = <&apb0>; 171 clocks = <&apb0>;
158 clock-output-names = "apb0_codec", "apb0_spdif", 172 clock-output-names = "apb0_codec", "apb0_spdif",
@@ -162,21 +176,23 @@
162 176
163 apb1_mux: apb1_mux@01c20058 { 177 apb1_mux: apb1_mux@01c20058 {
164 #clock-cells = <0>; 178 #clock-cells = <0>;
165 compatible = "allwinner,sun4i-apb1-mux-clk"; 179 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
166 reg = <0x01c20058 0x4>; 180 reg = <0x01c20058 0x4>;
167 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
182 clock-output-names = "apb1_mux";
168 }; 183 };
169 184
170 apb1: apb1@01c20058 { 185 apb1: apb1@01c20058 {
171 #clock-cells = <0>; 186 #clock-cells = <0>;
172 compatible = "allwinner,sun4i-apb1-clk"; 187 compatible = "allwinner,sun4i-a10-apb1-clk";
173 reg = <0x01c20058 0x4>; 188 reg = <0x01c20058 0x4>;
174 clocks = <&apb1_mux>; 189 clocks = <&apb1_mux>;
190 clock-output-names = "apb1";
175 }; 191 };
176 192
177 apb1_gates: apb1_gates@01c2006c { 193 apb1_gates: clk@01c2006c {
178 #clock-cells = <1>; 194 #clock-cells = <1>;
179 compatible = "allwinner,sun4i-apb1-gates-clk"; 195 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
180 reg = <0x01c2006c 0x4>; 196 reg = <0x01c2006c 0x4>;
181 clocks = <&apb1>; 197 clocks = <&apb1>;
182 clock-output-names = "apb1_i2c0", "apb1_i2c1", 198 clock-output-names = "apb1_i2c0", "apb1_i2c1",
@@ -189,7 +205,7 @@
189 205
190 nand_clk: clk@01c20080 { 206 nand_clk: clk@01c20080 {
191 #clock-cells = <0>; 207 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk"; 208 compatible = "allwinner,sun4i-a10-mod0-clk";
193 reg = <0x01c20080 0x4>; 209 reg = <0x01c20080 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "nand"; 211 clock-output-names = "nand";
@@ -197,7 +213,7 @@
197 213
198 ms_clk: clk@01c20084 { 214 ms_clk: clk@01c20084 {
199 #clock-cells = <0>; 215 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk"; 216 compatible = "allwinner,sun4i-a10-mod0-clk";
201 reg = <0x01c20084 0x4>; 217 reg = <0x01c20084 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "ms"; 219 clock-output-names = "ms";
@@ -205,7 +221,7 @@
205 221
206 mmc0_clk: clk@01c20088 { 222 mmc0_clk: clk@01c20088 {
207 #clock-cells = <0>; 223 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk"; 224 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20088 0x4>; 225 reg = <0x01c20088 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc0"; 227 clock-output-names = "mmc0";
@@ -213,7 +229,7 @@
213 229
214 mmc1_clk: clk@01c2008c { 230 mmc1_clk: clk@01c2008c {
215 #clock-cells = <0>; 231 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk"; 232 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c2008c 0x4>; 233 reg = <0x01c2008c 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "mmc1"; 235 clock-output-names = "mmc1";
@@ -221,7 +237,7 @@
221 237
222 mmc2_clk: clk@01c20090 { 238 mmc2_clk: clk@01c20090 {
223 #clock-cells = <0>; 239 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk"; 240 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c20090 0x4>; 241 reg = <0x01c20090 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc2"; 243 clock-output-names = "mmc2";
@@ -229,7 +245,7 @@
229 245
230 mmc3_clk: clk@01c20094 { 246 mmc3_clk: clk@01c20094 {
231 #clock-cells = <0>; 247 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk"; 248 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c20094 0x4>; 249 reg = <0x01c20094 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc3"; 251 clock-output-names = "mmc3";
@@ -237,7 +253,7 @@
237 253
238 ts_clk: clk@01c20098 { 254 ts_clk: clk@01c20098 {
239 #clock-cells = <0>; 255 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk"; 256 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c20098 0x4>; 257 reg = <0x01c20098 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "ts"; 259 clock-output-names = "ts";
@@ -245,7 +261,7 @@
245 261
246 ss_clk: clk@01c2009c { 262 ss_clk: clk@01c2009c {
247 #clock-cells = <0>; 263 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk"; 264 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c2009c 0x4>; 265 reg = <0x01c2009c 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "ss"; 267 clock-output-names = "ss";
@@ -253,7 +269,7 @@
253 269
254 spi0_clk: clk@01c200a0 { 270 spi0_clk: clk@01c200a0 {
255 #clock-cells = <0>; 271 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk"; 272 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c200a0 0x4>; 273 reg = <0x01c200a0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "spi0"; 275 clock-output-names = "spi0";
@@ -261,7 +277,7 @@
261 277
262 spi1_clk: clk@01c200a4 { 278 spi1_clk: clk@01c200a4 {
263 #clock-cells = <0>; 279 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk"; 280 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c200a4 0x4>; 281 reg = <0x01c200a4 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "spi1"; 283 clock-output-names = "spi1";
@@ -269,7 +285,7 @@
269 285
270 spi2_clk: clk@01c200a8 { 286 spi2_clk: clk@01c200a8 {
271 #clock-cells = <0>; 287 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
273 reg = <0x01c200a8 0x4>; 289 reg = <0x01c200a8 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi2"; 291 clock-output-names = "spi2";
@@ -277,7 +293,7 @@
277 293
278 pata_clk: clk@01c200ac { 294 pata_clk: clk@01c200ac {
279 #clock-cells = <0>; 295 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-mod0-clk"; 296 compatible = "allwinner,sun4i-a10-mod0-clk";
281 reg = <0x01c200ac 0x4>; 297 reg = <0x01c200ac 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "pata"; 299 clock-output-names = "pata";
@@ -285,7 +301,7 @@
285 301
286 ir0_clk: clk@01c200b0 { 302 ir0_clk: clk@01c200b0 {
287 #clock-cells = <0>; 303 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-mod0-clk"; 304 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c200b0 0x4>; 305 reg = <0x01c200b0 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "ir0"; 307 clock-output-names = "ir0";
@@ -293,15 +309,24 @@
293 309
294 ir1_clk: clk@01c200b4 { 310 ir1_clk: clk@01c200b4 {
295 #clock-cells = <0>; 311 #clock-cells = <0>;
296 compatible = "allwinner,sun4i-mod0-clk"; 312 compatible = "allwinner,sun4i-a10-mod0-clk";
297 reg = <0x01c200b4 0x4>; 313 reg = <0x01c200b4 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "ir1"; 315 clock-output-names = "ir1";
300 }; 316 };
301 317
318 usb_clk: clk@01c200cc {
319 #clock-cells = <1>;
320 #reset-cells = <1>;
321 compatible = "allwinner,sun4i-a10-usb-clk";
322 reg = <0x01c200cc 0x4>;
323 clocks = <&pll6 1>;
324 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
325 };
326
302 spi3_clk: clk@01c200d4 { 327 spi3_clk: clk@01c200d4 {
303 #clock-cells = <0>; 328 #clock-cells = <0>;
304 compatible = "allwinner,sun4i-mod0-clk"; 329 compatible = "allwinner,sun4i-a10-mod0-clk";
305 reg = <0x01c200d4 0x4>; 330 reg = <0x01c200d4 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "spi3"; 332 clock-output-names = "spi3";
@@ -314,6 +339,28 @@
314 #size-cells = <1>; 339 #size-cells = <1>;
315 ranges; 340 ranges;
316 341
342 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>;
345 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod";
348 status = "disabled";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 };
352
353 spi1: spi@01c06000 {
354 compatible = "allwinner,sun4i-a10-spi";
355 reg = <0x01c06000 0x1000>;
356 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod";
359 status = "disabled";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 };
363
317 emac: ethernet@01c0b000 { 364 emac: ethernet@01c0b000 {
318 compatible = "allwinner,sun4i-a10-emac"; 365 compatible = "allwinner,sun4i-a10-emac";
319 reg = <0x01c0b000 0x1000>; 366 reg = <0x01c0b000 0x1000>;
@@ -330,6 +377,28 @@
330 #size-cells = <0>; 377 #size-cells = <0>;
331 }; 378 };
332 379
380 spi2: spi@01c17000 {
381 compatible = "allwinner,sun4i-a10-spi";
382 reg = <0x01c17000 0x1000>;
383 interrupts = <12>;
384 clocks = <&ahb_gates 22>, <&spi2_clk>;
385 clock-names = "ahb", "mod";
386 status = "disabled";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 };
390
391 spi3: spi@01c1f000 {
392 compatible = "allwinner,sun4i-a10-spi";
393 reg = <0x01c1f000 0x1000>;
394 interrupts = <50>;
395 clocks = <&ahb_gates 23>, <&spi3_clk>;
396 clock-names = "ahb", "mod";
397 status = "disabled";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 };
401
333 intc: interrupt-controller@01c20400 { 402 intc: interrupt-controller@01c20400 {
334 compatible = "allwinner,sun4i-ic"; 403 compatible = "allwinner,sun4i-ic";
335 reg = <0x01c20400 0x400>; 404 reg = <0x01c20400 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 64961595e8d6..a7198b615afd 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -18,6 +18,10 @@
18 18
19 aliases { 19 aliases {
20 ethernet0 = &emac; 20 ethernet0 = &emac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
21 }; 25 };
22 26
23 cpus { 27 cpus {
@@ -47,44 +51,48 @@
47 clock-frequency = <0>; 51 clock-frequency = <0>;
48 }; 52 };
49 53
50 osc24M: osc24M@01c20050 { 54 osc24M: clk@01c20050 {
51 #clock-cells = <0>; 55 #clock-cells = <0>;
52 compatible = "allwinner,sun4i-osc-clk"; 56 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>; 57 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>; 58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M";
55 }; 60 };
56 61
57 osc32k: osc32k { 62 osc32k: clk@0 {
58 #clock-cells = <0>; 63 #clock-cells = <0>;
59 compatible = "fixed-clock"; 64 compatible = "fixed-clock";
60 clock-frequency = <32768>; 65 clock-frequency = <32768>;
66 clock-output-names = "osc32k";
61 }; 67 };
62 68
63 pll1: pll1@01c20000 { 69 pll1: clk@01c20000 {
64 #clock-cells = <0>; 70 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 71 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 72 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 73 clocks = <&osc24M>;
74 clock-output-names = "pll1";
68 }; 75 };
69 76
70 pll4: pll4@01c20018 { 77 pll4: clk@01c20018 {
71 #clock-cells = <0>; 78 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 79 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 80 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 81 clocks = <&osc24M>;
82 clock-output-names = "pll4";
75 }; 83 };
76 84
77 pll5: pll5@01c20020 { 85 pll5: clk@01c20020 {
78 #clock-cells = <1>; 86 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 87 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 88 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 89 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 90 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 91 };
84 92
85 pll6: pll6@01c20028 { 93 pll6: clk@01c20028 {
86 #clock-cells = <1>; 94 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 95 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 96 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 97 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +101,23 @@
93 /* dummy is 200M */ 101 /* dummy is 200M */
94 cpu: cpu@01c20054 { 102 cpu: cpu@01c20054 {
95 #clock-cells = <0>; 103 #clock-cells = <0>;
96 compatible = "allwinner,sun4i-cpu-clk"; 104 compatible = "allwinner,sun4i-a10-cpu-clk";
97 reg = <0x01c20054 0x4>; 105 reg = <0x01c20054 0x4>;
98 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu";
99 }; 108 };
100 109
101 axi: axi@01c20054 { 110 axi: axi@01c20054 {
102 #clock-cells = <0>; 111 #clock-cells = <0>;
103 compatible = "allwinner,sun4i-axi-clk"; 112 compatible = "allwinner,sun4i-a10-axi-clk";
104 reg = <0x01c20054 0x4>; 113 reg = <0x01c20054 0x4>;
105 clocks = <&cpu>; 114 clocks = <&cpu>;
115 clock-output-names = "axi";
106 }; 116 };
107 117
108 axi_gates: axi_gates@01c2005c { 118 axi_gates: clk@01c2005c {
109 #clock-cells = <1>; 119 #clock-cells = <1>;
110 compatible = "allwinner,sun4i-axi-gates-clk"; 120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
111 reg = <0x01c2005c 0x4>; 121 reg = <0x01c2005c 0x4>;
112 clocks = <&axi>; 122 clocks = <&axi>;
113 clock-output-names = "axi_dram"; 123 clock-output-names = "axi_dram";
@@ -115,12 +125,13 @@
115 125
116 ahb: ahb@01c20054 { 126 ahb: ahb@01c20054 {
117 #clock-cells = <0>; 127 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 128 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 129 reg = <0x01c20054 0x4>;
120 clocks = <&axi>; 130 clocks = <&axi>;
131 clock-output-names = "ahb";
121 }; 132 };
122 133
123 ahb_gates: ahb_gates@01c20060 { 134 ahb_gates: clk@01c20060 {
124 #clock-cells = <1>; 135 #clock-cells = <1>;
125 compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; 136 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
126 reg = <0x01c20060 0x8>; 137 reg = <0x01c20060 0x8>;
@@ -136,12 +147,13 @@
136 147
137 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
138 #clock-cells = <0>; 149 #clock-cells = <0>;
139 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
140 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
141 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0";
142 }; 154 };
143 155
144 apb0_gates: apb0_gates@01c20068 { 156 apb0_gates: clk@01c20068 {
145 #clock-cells = <1>; 157 #clock-cells = <1>;
146 compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; 158 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
147 reg = <0x01c20068 0x4>; 159 reg = <0x01c20068 0x4>;
@@ -152,19 +164,21 @@
152 164
153 apb1_mux: apb1_mux@01c20058 { 165 apb1_mux: apb1_mux@01c20058 {
154 #clock-cells = <0>; 166 #clock-cells = <0>;
155 compatible = "allwinner,sun4i-apb1-mux-clk"; 167 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
156 reg = <0x01c20058 0x4>; 168 reg = <0x01c20058 0x4>;
157 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1_mux";
158 }; 171 };
159 172
160 apb1: apb1@01c20058 { 173 apb1: apb1@01c20058 {
161 #clock-cells = <0>; 174 #clock-cells = <0>;
162 compatible = "allwinner,sun4i-apb1-clk"; 175 compatible = "allwinner,sun4i-a10-apb1-clk";
163 reg = <0x01c20058 0x4>; 176 reg = <0x01c20058 0x4>;
164 clocks = <&apb1_mux>; 177 clocks = <&apb1_mux>;
178 clock-output-names = "apb1";
165 }; 179 };
166 180
167 apb1_gates: apb1_gates@01c2006c { 181 apb1_gates: clk@01c2006c {
168 #clock-cells = <1>; 182 #clock-cells = <1>;
169 compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; 183 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
170 reg = <0x01c2006c 0x4>; 184 reg = <0x01c2006c 0x4>;
@@ -176,7 +190,7 @@
176 190
177 nand_clk: clk@01c20080 { 191 nand_clk: clk@01c20080 {
178 #clock-cells = <0>; 192 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-mod0-clk"; 193 compatible = "allwinner,sun4i-a10-mod0-clk";
180 reg = <0x01c20080 0x4>; 194 reg = <0x01c20080 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
182 clock-output-names = "nand"; 196 clock-output-names = "nand";
@@ -184,7 +198,7 @@
184 198
185 ms_clk: clk@01c20084 { 199 ms_clk: clk@01c20084 {
186 #clock-cells = <0>; 200 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-mod0-clk"; 201 compatible = "allwinner,sun4i-a10-mod0-clk";
188 reg = <0x01c20084 0x4>; 202 reg = <0x01c20084 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "ms"; 204 clock-output-names = "ms";
@@ -192,7 +206,7 @@
192 206
193 mmc0_clk: clk@01c20088 { 207 mmc0_clk: clk@01c20088 {
194 #clock-cells = <0>; 208 #clock-cells = <0>;
195 compatible = "allwinner,sun4i-mod0-clk"; 209 compatible = "allwinner,sun4i-a10-mod0-clk";
196 reg = <0x01c20088 0x4>; 210 reg = <0x01c20088 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "mmc0"; 212 clock-output-names = "mmc0";
@@ -200,7 +214,7 @@
200 214
201 mmc1_clk: clk@01c2008c { 215 mmc1_clk: clk@01c2008c {
202 #clock-cells = <0>; 216 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-mod0-clk"; 217 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c2008c 0x4>; 218 reg = <0x01c2008c 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "mmc1"; 220 clock-output-names = "mmc1";
@@ -208,7 +222,7 @@
208 222
209 mmc2_clk: clk@01c20090 { 223 mmc2_clk: clk@01c20090 {
210 #clock-cells = <0>; 224 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-mod0-clk"; 225 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c20090 0x4>; 226 reg = <0x01c20090 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc2"; 228 clock-output-names = "mmc2";
@@ -216,7 +230,7 @@
216 230
217 ts_clk: clk@01c20098 { 231 ts_clk: clk@01c20098 {
218 #clock-cells = <0>; 232 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-mod0-clk"; 233 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c20098 0x4>; 234 reg = <0x01c20098 0x4>;
221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
222 clock-output-names = "ts"; 236 clock-output-names = "ts";
@@ -224,7 +238,7 @@
224 238
225 ss_clk: clk@01c2009c { 239 ss_clk: clk@01c2009c {
226 #clock-cells = <0>; 240 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-mod0-clk"; 241 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c2009c 0x4>; 242 reg = <0x01c2009c 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
230 clock-output-names = "ss"; 244 clock-output-names = "ss";
@@ -232,7 +246,7 @@
232 246
233 spi0_clk: clk@01c200a0 { 247 spi0_clk: clk@01c200a0 {
234 #clock-cells = <0>; 248 #clock-cells = <0>;
235 compatible = "allwinner,sun4i-mod0-clk"; 249 compatible = "allwinner,sun4i-a10-mod0-clk";
236 reg = <0x01c200a0 0x4>; 250 reg = <0x01c200a0 0x4>;
237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
238 clock-output-names = "spi0"; 252 clock-output-names = "spi0";
@@ -240,7 +254,7 @@
240 254
241 spi1_clk: clk@01c200a4 { 255 spi1_clk: clk@01c200a4 {
242 #clock-cells = <0>; 256 #clock-cells = <0>;
243 compatible = "allwinner,sun4i-mod0-clk"; 257 compatible = "allwinner,sun4i-a10-mod0-clk";
244 reg = <0x01c200a4 0x4>; 258 reg = <0x01c200a4 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "spi1"; 260 clock-output-names = "spi1";
@@ -248,7 +262,7 @@
248 262
249 spi2_clk: clk@01c200a8 { 263 spi2_clk: clk@01c200a8 {
250 #clock-cells = <0>; 264 #clock-cells = <0>;
251 compatible = "allwinner,sun4i-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mod0-clk";
252 reg = <0x01c200a8 0x4>; 266 reg = <0x01c200a8 0x4>;
253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
254 clock-output-names = "spi2"; 268 clock-output-names = "spi2";
@@ -256,15 +270,24 @@
256 270
257 ir0_clk: clk@01c200b0 { 271 ir0_clk: clk@01c200b0 {
258 #clock-cells = <0>; 272 #clock-cells = <0>;
259 compatible = "allwinner,sun4i-mod0-clk"; 273 compatible = "allwinner,sun4i-a10-mod0-clk";
260 reg = <0x01c200b0 0x4>; 274 reg = <0x01c200b0 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "ir0"; 276 clock-output-names = "ir0";
263 }; 277 };
264 278
279 usb_clk: clk@01c200cc {
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 compatible = "allwinner,sun5i-a13-usb-clk";
283 reg = <0x01c200cc 0x4>;
284 clocks = <&pll6 1>;
285 clock-output-names = "usb_ohci0", "usb_phy";
286 };
287
265 mbus_clk: clk@01c2015c { 288 mbus_clk: clk@01c2015c {
266 #clock-cells = <0>; 289 #clock-cells = <0>;
267 compatible = "allwinner,sun4i-mod0-clk"; 290 compatible = "allwinner,sun4i-a10-mod0-clk";
268 reg = <0x01c2015c 0x4>; 291 reg = <0x01c2015c 0x4>;
269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
270 clock-output-names = "mbus"; 293 clock-output-names = "mbus";
@@ -277,6 +300,28 @@
277 #size-cells = <1>; 300 #size-cells = <1>;
278 ranges; 301 ranges;
279 302
303 spi0: spi@01c05000 {
304 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>;
306 interrupts = <10>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod";
309 status = "disabled";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 };
313
314 spi1: spi@01c06000 {
315 compatible = "allwinner,sun4i-a10-spi";
316 reg = <0x01c06000 0x1000>;
317 interrupts = <11>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod";
320 status = "disabled";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
324
280 emac: ethernet@01c0b000 { 325 emac: ethernet@01c0b000 {
281 compatible = "allwinner,sun4i-a10-emac"; 326 compatible = "allwinner,sun4i-a10-emac";
282 reg = <0x01c0b000 0x1000>; 327 reg = <0x01c0b000 0x1000>;
@@ -293,6 +338,17 @@
293 #size-cells = <0>; 338 #size-cells = <0>;
294 }; 339 };
295 340
341 spi2: spi@01c17000 {
342 compatible = "allwinner,sun4i-a10-spi";
343 reg = <0x01c17000 0x1000>;
344 interrupts = <12>;
345 clocks = <&ahb_gates 22>, <&spi2_clk>;
346 clock-names = "ahb", "mod";
347 status = "disabled";
348 #address-cells = <1>;
349 #size-cells = <0>;
350 };
351
296 intc: interrupt-controller@01c20400 { 352 intc: interrupt-controller@01c20400 {
297 compatible = "allwinner,sun4i-ic"; 353 compatible = "allwinner,sun4i-ic";
298 reg = <0x01c20400 0x400>; 354 reg = <0x01c20400 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 320335abfccd..cda1d4bbe2e2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -16,6 +16,11 @@
16/ { 16/ {
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart3;
22 };
23
19 cpus { 24 cpus {
20 #address-cells = <1>; 25 #address-cells = <1>;
21 #size-cells = <0>; 26 #size-cells = <0>;
@@ -47,44 +52,48 @@
47 clock-frequency = <0>; 52 clock-frequency = <0>;
48 }; 53 };
49 54
50 osc24M: osc24M@01c20050 { 55 osc24M: clk@01c20050 {
51 #clock-cells = <0>; 56 #clock-cells = <0>;
52 compatible = "allwinner,sun4i-osc-clk"; 57 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>; 58 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>; 59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
55 }; 61 };
56 62
57 osc32k: osc32k { 63 osc32k: clk@0 {
58 #clock-cells = <0>; 64 #clock-cells = <0>;
59 compatible = "fixed-clock"; 65 compatible = "fixed-clock";
60 clock-frequency = <32768>; 66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
61 }; 68 };
62 69
63 pll1: pll1@01c20000 { 70 pll1: clk@01c20000 {
64 #clock-cells = <0>; 71 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 72 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 73 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 74 clocks = <&osc24M>;
75 clock-output-names = "pll1";
68 }; 76 };
69 77
70 pll4: pll4@01c20018 { 78 pll4: clk@01c20018 {
71 #clock-cells = <0>; 79 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 80 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 81 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 82 clocks = <&osc24M>;
83 clock-output-names = "pll4";
75 }; 84 };
76 85
77 pll5: pll5@01c20020 { 86 pll5: clk@01c20020 {
78 #clock-cells = <1>; 87 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 88 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 89 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 90 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 91 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 92 };
84 93
85 pll6: pll6@01c20028 { 94 pll6: clk@01c20028 {
86 #clock-cells = <1>; 95 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 96 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 97 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 98 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +102,23 @@
93 /* dummy is 200M */ 102 /* dummy is 200M */
94 cpu: cpu@01c20054 { 103 cpu: cpu@01c20054 {
95 #clock-cells = <0>; 104 #clock-cells = <0>;
96 compatible = "allwinner,sun4i-cpu-clk"; 105 compatible = "allwinner,sun4i-a10-cpu-clk";
97 reg = <0x01c20054 0x4>; 106 reg = <0x01c20054 0x4>;
98 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu";
99 }; 109 };
100 110
101 axi: axi@01c20054 { 111 axi: axi@01c20054 {
102 #clock-cells = <0>; 112 #clock-cells = <0>;
103 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
104 reg = <0x01c20054 0x4>; 114 reg = <0x01c20054 0x4>;
105 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi";
106 }; 117 };
107 118
108 axi_gates: axi_gates@01c2005c { 119 axi_gates: clk@01c2005c {
109 #clock-cells = <1>; 120 #clock-cells = <1>;
110 compatible = "allwinner,sun4i-axi-gates-clk"; 121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
111 reg = <0x01c2005c 0x4>; 122 reg = <0x01c2005c 0x4>;
112 clocks = <&axi>; 123 clocks = <&axi>;
113 clock-output-names = "axi_dram"; 124 clock-output-names = "axi_dram";
@@ -115,12 +126,13 @@
115 126
116 ahb: ahb@01c20054 { 127 ahb: ahb@01c20054 {
117 #clock-cells = <0>; 128 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
120 clocks = <&axi>; 131 clocks = <&axi>;
132 clock-output-names = "ahb";
121 }; 133 };
122 134
123 ahb_gates: ahb_gates@01c20060 { 135 ahb_gates: clk@01c20060 {
124 #clock-cells = <1>; 136 #clock-cells = <1>;
125 compatible = "allwinner,sun5i-a13-ahb-gates-clk"; 137 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
126 reg = <0x01c20060 0x8>; 138 reg = <0x01c20060 0x8>;
@@ -135,12 +147,13 @@
135 147
136 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
137 #clock-cells = <0>; 149 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
139 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
140 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0";
141 }; 154 };
142 155
143 apb0_gates: apb0_gates@01c20068 { 156 apb0_gates: clk@01c20068 {
144 #clock-cells = <1>; 157 #clock-cells = <1>;
145 compatible = "allwinner,sun5i-a13-apb0-gates-clk"; 158 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
146 reg = <0x01c20068 0x4>; 159 reg = <0x01c20068 0x4>;
@@ -150,19 +163,21 @@
150 163
151 apb1_mux: apb1_mux@01c20058 { 164 apb1_mux: apb1_mux@01c20058 {
152 #clock-cells = <0>; 165 #clock-cells = <0>;
153 compatible = "allwinner,sun4i-apb1-mux-clk"; 166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
154 reg = <0x01c20058 0x4>; 167 reg = <0x01c20058 0x4>;
155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux";
156 }; 170 };
157 171
158 apb1: apb1@01c20058 { 172 apb1: apb1@01c20058 {
159 #clock-cells = <0>; 173 #clock-cells = <0>;
160 compatible = "allwinner,sun4i-apb1-clk"; 174 compatible = "allwinner,sun4i-a10-apb1-clk";
161 reg = <0x01c20058 0x4>; 175 reg = <0x01c20058 0x4>;
162 clocks = <&apb1_mux>; 176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1";
163 }; 178 };
164 179
165 apb1_gates: apb1_gates@01c2006c { 180 apb1_gates: clk@01c2006c {
166 #clock-cells = <1>; 181 #clock-cells = <1>;
167 compatible = "allwinner,sun5i-a13-apb1-gates-clk"; 182 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
168 reg = <0x01c2006c 0x4>; 183 reg = <0x01c2006c 0x4>;
@@ -173,7 +188,7 @@
173 188
174 nand_clk: clk@01c20080 { 189 nand_clk: clk@01c20080 {
175 #clock-cells = <0>; 190 #clock-cells = <0>;
176 compatible = "allwinner,sun4i-mod0-clk"; 191 compatible = "allwinner,sun4i-a10-mod0-clk";
177 reg = <0x01c20080 0x4>; 192 reg = <0x01c20080 0x4>;
178 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
179 clock-output-names = "nand"; 194 clock-output-names = "nand";
@@ -181,7 +196,7 @@
181 196
182 ms_clk: clk@01c20084 { 197 ms_clk: clk@01c20084 {
183 #clock-cells = <0>; 198 #clock-cells = <0>;
184 compatible = "allwinner,sun4i-mod0-clk"; 199 compatible = "allwinner,sun4i-a10-mod0-clk";
185 reg = <0x01c20084 0x4>; 200 reg = <0x01c20084 0x4>;
186 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187 clock-output-names = "ms"; 202 clock-output-names = "ms";
@@ -189,7 +204,7 @@
189 204
190 mmc0_clk: clk@01c20088 { 205 mmc0_clk: clk@01c20088 {
191 #clock-cells = <0>; 206 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk"; 207 compatible = "allwinner,sun4i-a10-mod0-clk";
193 reg = <0x01c20088 0x4>; 208 reg = <0x01c20088 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "mmc0"; 210 clock-output-names = "mmc0";
@@ -197,7 +212,7 @@
197 212
198 mmc1_clk: clk@01c2008c { 213 mmc1_clk: clk@01c2008c {
199 #clock-cells = <0>; 214 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk"; 215 compatible = "allwinner,sun4i-a10-mod0-clk";
201 reg = <0x01c2008c 0x4>; 216 reg = <0x01c2008c 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "mmc1"; 218 clock-output-names = "mmc1";
@@ -205,7 +220,7 @@
205 220
206 mmc2_clk: clk@01c20090 { 221 mmc2_clk: clk@01c20090 {
207 #clock-cells = <0>; 222 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk"; 223 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20090 0x4>; 224 reg = <0x01c20090 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc2"; 226 clock-output-names = "mmc2";
@@ -213,7 +228,7 @@
213 228
214 ts_clk: clk@01c20098 { 229 ts_clk: clk@01c20098 {
215 #clock-cells = <0>; 230 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk"; 231 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c20098 0x4>; 232 reg = <0x01c20098 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ts"; 234 clock-output-names = "ts";
@@ -221,7 +236,7 @@
221 236
222 ss_clk: clk@01c2009c { 237 ss_clk: clk@01c2009c {
223 #clock-cells = <0>; 238 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk"; 239 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c2009c 0x4>; 240 reg = <0x01c2009c 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "ss"; 242 clock-output-names = "ss";
@@ -229,7 +244,7 @@
229 244
230 spi0_clk: clk@01c200a0 { 245 spi0_clk: clk@01c200a0 {
231 #clock-cells = <0>; 246 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk"; 247 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c200a0 0x4>; 248 reg = <0x01c200a0 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "spi0"; 250 clock-output-names = "spi0";
@@ -237,7 +252,7 @@
237 252
238 spi1_clk: clk@01c200a4 { 253 spi1_clk: clk@01c200a4 {
239 #clock-cells = <0>; 254 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk"; 255 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c200a4 0x4>; 256 reg = <0x01c200a4 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "spi1"; 258 clock-output-names = "spi1";
@@ -245,7 +260,7 @@
245 260
246 spi2_clk: clk@01c200a8 { 261 spi2_clk: clk@01c200a8 {
247 #clock-cells = <0>; 262 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk"; 263 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c200a8 0x4>; 264 reg = <0x01c200a8 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "spi2"; 266 clock-output-names = "spi2";
@@ -253,15 +268,24 @@
253 268
254 ir0_clk: clk@01c200b0 { 269 ir0_clk: clk@01c200b0 {
255 #clock-cells = <0>; 270 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c200b0 0x4>; 272 reg = <0x01c200b0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ir0"; 274 clock-output-names = "ir0";
260 }; 275 };
261 276
277 usb_clk: clk@01c200cc {
278 #clock-cells = <1>;
279 #reset-cells = <1>;
280 compatible = "allwinner,sun5i-a13-usb-clk";
281 reg = <0x01c200cc 0x4>;
282 clocks = <&pll6 1>;
283 clock-output-names = "usb_ohci0", "usb_phy";
284 };
285
262 mbus_clk: clk@01c2015c { 286 mbus_clk: clk@01c2015c {
263 #clock-cells = <0>; 287 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c2015c 0x4>; 289 reg = <0x01c2015c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "mbus"; 291 clock-output-names = "mbus";
@@ -274,6 +298,39 @@
274 #size-cells = <1>; 298 #size-cells = <1>;
275 ranges; 299 ranges;
276 300
301 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
304 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 spi1: spi@01c06000 {
313 compatible = "allwinner,sun4i-a10-spi";
314 reg = <0x01c06000 0x1000>;
315 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
322
323 spi2: spi@01c17000 {
324 compatible = "allwinner,sun4i-a10-spi";
325 reg = <0x01c17000 0x1000>;
326 interrupts = <12>;
327 clocks = <&ahb_gates 22>, <&spi2_clk>;
328 clock-names = "ahb", "mod";
329 status = "disabled";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 };
333
277 intc: interrupt-controller@01c20400 { 334 intc: interrupt-controller@01c20400 {
278 compatible = "allwinner,sun4i-ic"; 335 compatible = "allwinner,sun4i-ic";
279 reg = <0x01c20400 0x400>; 336 reg = <0x01c20400 0x400>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 5256ad9be52c..42f310a925c4 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -16,6 +16,16 @@
16/ { 16/ {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases {
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 };
27
28
19 cpus { 29 cpus {
20 #address-cells = <1>; 30 #address-cells = <1>;
21 #size-cells = <0>; 31 #size-cells = <0>;
@@ -60,34 +70,32 @@
60 clock-frequency = <24000000>; 70 clock-frequency = <24000000>;
61 }; 71 };
62 72
63 osc32k: osc32k { 73 osc32k: clk@0 {
64 #clock-cells = <0>; 74 #clock-cells = <0>;
65 compatible = "fixed-clock"; 75 compatible = "fixed-clock";
66 clock-frequency = <32768>; 76 clock-frequency = <32768>;
77 clock-output-names = "osc32k";
67 }; 78 };
68 79
69 pll1: pll1@01c20000 { 80 pll1: clk@01c20000 {
70 #clock-cells = <0>; 81 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk"; 82 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>; 83 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>; 84 clocks = <&osc24M>;
85 clock-output-names = "pll1";
74 }; 86 };
75 87
76 /* 88 pll6: clk@01c20028 {
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>; 89 #clock-cells = <0>;
84 compatible = "fixed-clock"; 90 compatible = "allwinner,sun6i-a31-pll6-clk";
85 clock-frequency = <0>; 91 reg = <0x01c20028 0x4>;
92 clocks = <&osc24M>;
93 clock-output-names = "pll6";
86 }; 94 };
87 95
88 cpu: cpu@01c20050 { 96 cpu: cpu@01c20050 {
89 #clock-cells = <0>; 97 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk"; 98 compatible = "allwinner,sun4i-a10-cpu-clk";
91 reg = <0x01c20050 0x4>; 99 reg = <0x01c20050 0x4>;
92 100
93 /* 101 /*
@@ -97,13 +105,15 @@
97 * Allwinner. 105 * Allwinner.
98 */ 106 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
108 clock-output-names = "cpu";
100 }; 109 };
101 110
102 axi: axi@01c20050 { 111 axi: axi@01c20050 {
103 #clock-cells = <0>; 112 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
105 reg = <0x01c20050 0x4>; 114 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi";
107 }; 117 };
108 118
109 ahb1_mux: ahb1_mux@01c20054 { 119 ahb1_mux: ahb1_mux@01c20054 {
@@ -111,16 +121,18 @@
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; 121 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>; 122 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; 123 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
124 clock-output-names = "ahb1_mux";
114 }; 125 };
115 126
116 ahb1: ahb1@01c20054 { 127 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>; 128 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>; 131 clocks = <&ahb1_mux>;
132 clock-output-names = "ahb1";
121 }; 133 };
122 134
123 ahb1_gates: ahb1_gates@01c20060 { 135 ahb1_gates: clk@01c20060 {
124 #clock-cells = <1>; 136 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; 137 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>; 138 reg = <0x01c20060 0x8>;
@@ -143,12 +155,13 @@
143 155
144 apb1: apb1@01c20054 { 156 apb1: apb1@01c20054 {
145 #clock-cells = <0>; 157 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
147 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>; 160 clocks = <&ahb1>;
161 clock-output-names = "apb1";
149 }; 162 };
150 163
151 apb1_gates: apb1_gates@01c20060 { 164 apb1_gates: clk@01c20068 {
152 #clock-cells = <1>; 165 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk"; 166 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>; 167 reg = <0x01c20068 0x4>;
@@ -160,9 +173,10 @@
160 173
161 apb2_mux: apb2_mux@01c20058 { 174 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>; 175 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk"; 176 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
164 reg = <0x01c20058 0x4>; 177 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 178 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
179 clock-output-names = "apb2_mux";
166 }; 180 };
167 181
168 apb2: apb2@01c20058 { 182 apb2: apb2@01c20058 {
@@ -170,9 +184,10 @@
170 compatible = "allwinner,sun6i-a31-apb2-div-clk"; 184 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>; 185 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>; 186 clocks = <&apb2_mux>;
187 clock-output-names = "apb2";
173 }; 188 };
174 189
175 apb2_gates: apb2_gates@01c2006c { 190 apb2_gates: clk@01c2006c {
176 #clock-cells = <1>; 191 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk"; 192 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x4>; 193 reg = <0x01c2006c 0x4>;
@@ -182,6 +197,38 @@
182 "apb2_uart1", "apb2_uart2", "apb2_uart3", 197 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5"; 198 "apb2_uart4", "apb2_uart5";
184 }; 199 };
200
201 spi0_clk: clk@01c200a0 {
202 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c200a0 0x4>;
205 clocks = <&osc24M>, <&pll6>;
206 clock-output-names = "spi0";
207 };
208
209 spi1_clk: clk@01c200a4 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c200a4 0x4>;
213 clocks = <&osc24M>, <&pll6>;
214 clock-output-names = "spi1";
215 };
216
217 spi2_clk: clk@01c200a8 {
218 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c200a8 0x4>;
221 clocks = <&osc24M>, <&pll6>;
222 clock-output-names = "spi2";
223 };
224
225 spi3_clk: clk@01c200ac {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c200ac 0x4>;
229 clocks = <&osc24M>, <&pll6>;
230 clock-output-names = "spi3";
231 };
185 }; 232 };
186 233
187 soc@01c00000 { 234 soc@01c00000 {
@@ -312,6 +359,46 @@
312 status = "disabled"; 359 status = "disabled";
313 }; 360 };
314 361
362 spi0: spi@01c68000 {
363 compatible = "allwinner,sun6i-a31-spi";
364 reg = <0x01c68000 0x1000>;
365 interrupts = <0 65 4>;
366 clocks = <&ahb1_gates 20>, <&spi0_clk>;
367 clock-names = "ahb", "mod";
368 resets = <&ahb1_rst 20>;
369 status = "disabled";
370 };
371
372 spi1: spi@01c69000 {
373 compatible = "allwinner,sun6i-a31-spi";
374 reg = <0x01c69000 0x1000>;
375 interrupts = <0 66 4>;
376 clocks = <&ahb1_gates 21>, <&spi1_clk>;
377 clock-names = "ahb", "mod";
378 resets = <&ahb1_rst 21>;
379 status = "disabled";
380 };
381
382 spi2: spi@01c6a000 {
383 compatible = "allwinner,sun6i-a31-spi";
384 reg = <0x01c6a000 0x1000>;
385 interrupts = <0 67 4>;
386 clocks = <&ahb1_gates 22>, <&spi2_clk>;
387 clock-names = "ahb", "mod";
388 resets = <&ahb1_rst 22>;
389 status = "disabled";
390 };
391
392 spi3: spi@01c6b000 {
393 compatible = "allwinner,sun6i-a31-spi";
394 reg = <0x01c6b000 0x1000>;
395 interrupts = <0 68 4>;
396 clocks = <&ahb1_gates 23>, <&spi3_clk>;
397 clock-names = "ahb", "mod";
398 resets = <&ahb1_rst 23>;
399 status = "disabled";
400 };
401
315 gic: interrupt-controller@01c81000 { 402 gic: interrupt-controller@01c81000 {
316 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 403 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
317 reg = <0x01c81000 0x1000>, 404 reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8a98b0..7bf4935a58a9 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -19,21 +19,6 @@
19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; 19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
20 20
21 soc@01c00000 { 21 soc@01c00000 {
22 emac: ethernet@01c0b000 {
23 pinctrl-names = "default";
24 pinctrl-0 = <&emac_pins_a>;
25 phy = <&phy1>;
26 status = "okay";
27 };
28
29 mdio@01c0b080 {
30 status = "okay";
31
32 phy1: ethernet-phy@1 {
33 reg = <1>;
34 };
35 };
36
37 pinctrl@01c20800 { 22 pinctrl@01c20800 {
38 led_pins_cubieboard2: led_pins@0 { 23 led_pins_cubieboard2: led_pins@0 {
39 allwinner,pins = "PH20", "PH21"; 24 allwinner,pins = "PH20", "PH21";
@@ -60,6 +45,18 @@
60 pinctrl-0 = <&i2c1_pins_a>; 45 pinctrl-0 = <&i2c1_pins_a>;
61 status = "okay"; 46 status = "okay";
62 }; 47 };
48
49 gmac: ethernet@01c50000 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&gmac_pins_mii_a>;
52 phy = <&phy1>;
53 phy-mode = "mii";
54 status = "okay";
55
56 phy1: ethernet-phy@1 {
57 reg = <1>;
58 };
59 };
63 }; 60 };
64 61
65 leds { 62 leds {
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61a5305..025ce5234692 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -51,6 +51,18 @@
51 pinctrl-0 = <&i2c2_pins_a>; 51 pinctrl-0 = <&i2c2_pins_a>;
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54
55 gmac: ethernet@01c50000 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&gmac_pins_rgmii_a>;
58 phy = <&phy1>;
59 phy-mode = "rgmii";
60 status = "okay";
61
62 phy1: ethernet-phy@1 {
63 reg = <1>;
64 };
65 };
54 }; 66 };
55 67
56 leds { 68 leds {
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013f9aca..9d98316c9928 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -18,20 +18,22 @@
18 model = "Olimex A20-Olinuxino Micro"; 18 model = "Olimex A20-Olinuxino Micro";
19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; 19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
20 20
21 aliases {
22 spi0 = &spi1;
23 spi1 = &spi2;
24 };
25
21 soc@01c00000 { 26 soc@01c00000 {
22 emac: ethernet@01c0b000 { 27 spi1: spi@01c06000 {
23 pinctrl-names = "default"; 28 pinctrl-names = "default";
24 pinctrl-0 = <&emac_pins_a>; 29 pinctrl-0 = <&spi1_pins_a>;
25 phy = <&phy1>;
26 status = "okay"; 30 status = "okay";
27 }; 31 };
28 32
29 mdio@01c0b080 { 33 spi2: spi@01c17000 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&spi2_pins_a>;
30 status = "okay"; 36 status = "okay";
31
32 phy1: ethernet-phy@1 {
33 reg = <1>;
34 };
35 }; 37 };
36 38
37 pinctrl@01c20800 { 39 pinctrl@01c20800 {
@@ -78,6 +80,18 @@
78 pinctrl-0 = <&i2c2_pins_a>; 80 pinctrl-0 = <&i2c2_pins_a>;
79 status = "okay"; 81 status = "okay";
80 }; 82 };
83
84 gmac: ethernet@01c50000 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&gmac_pins_mii_a>;
87 phy = <&phy1>;
88 phy-mode = "mii";
89 status = "okay";
90
91 phy1: ethernet-phy@1 {
92 reg = <1>;
93 };
94 };
81 }; 95 };
82 96
83 leds { 97 leds {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9ff09484847b..52507e4e3a91 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,15 @@
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases { 19 aliases {
20 ethernet0 = &emac; 20 ethernet0 = &gmac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
27 serial6 = &uart6;
28 serial7 = &uart7;
21 }; 29 };
22 30
23 cpus { 31 cpus {
@@ -41,16 +49,25 @@
41 reg = <0x40000000 0x80000000>; 49 reg = <0x40000000 0x80000000>;
42 }; 50 };
43 51
52 timer {
53 compatible = "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
55 <1 14 0xf08>,
56 <1 11 0xf08>,
57 <1 10 0xf08>;
58 };
59
44 clocks { 60 clocks {
45 #address-cells = <1>; 61 #address-cells = <1>;
46 #size-cells = <1>; 62 #size-cells = <1>;
47 ranges; 63 ranges;
48 64
49 osc24M: osc24M@01c20050 { 65 osc24M: clk@01c20050 {
50 #clock-cells = <0>; 66 #clock-cells = <0>;
51 compatible = "allwinner,sun4i-osc-clk"; 67 compatible = "allwinner,sun4i-a10-osc-clk";
52 reg = <0x01c20050 0x4>; 68 reg = <0x01c20050 0x4>;
53 clock-frequency = <24000000>; 69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M";
54 }; 71 };
55 72
56 osc32k: clk@0 { 73 osc32k: clk@0 {
@@ -60,31 +77,33 @@
60 clock-output-names = "osc32k"; 77 clock-output-names = "osc32k";
61 }; 78 };
62 79
63 pll1: pll1@01c20000 { 80 pll1: clk@01c20000 {
64 #clock-cells = <0>; 81 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 82 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 83 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 84 clocks = <&osc24M>;
85 clock-output-names = "pll1";
68 }; 86 };
69 87
70 pll4: pll4@01c20018 { 88 pll4: clk@01c20018 {
71 #clock-cells = <0>; 89 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 90 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 91 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 92 clocks = <&osc24M>;
93 clock-output-names = "pll4";
75 }; 94 };
76 95
77 pll5: pll5@01c20020 { 96 pll5: clk@01c20020 {
78 #clock-cells = <1>; 97 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 98 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 99 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 100 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 101 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 102 };
84 103
85 pll6: pll6@01c20028 { 104 pll6: clk@01c20028 {
86 #clock-cells = <1>; 105 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 106 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 107 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 108 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -92,26 +111,29 @@
92 111
93 cpu: cpu@01c20054 { 112 cpu: cpu@01c20054 {
94 #clock-cells = <0>; 113 #clock-cells = <0>;
95 compatible = "allwinner,sun4i-cpu-clk"; 114 compatible = "allwinner,sun4i-a10-cpu-clk";
96 reg = <0x01c20054 0x4>; 115 reg = <0x01c20054 0x4>;
97 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
117 clock-output-names = "cpu";
98 }; 118 };
99 119
100 axi: axi@01c20054 { 120 axi: axi@01c20054 {
101 #clock-cells = <0>; 121 #clock-cells = <0>;
102 compatible = "allwinner,sun4i-axi-clk"; 122 compatible = "allwinner,sun4i-a10-axi-clk";
103 reg = <0x01c20054 0x4>; 123 reg = <0x01c20054 0x4>;
104 clocks = <&cpu>; 124 clocks = <&cpu>;
125 clock-output-names = "axi";
105 }; 126 };
106 127
107 ahb: ahb@01c20054 { 128 ahb: ahb@01c20054 {
108 #clock-cells = <0>; 129 #clock-cells = <0>;
109 compatible = "allwinner,sun4i-ahb-clk"; 130 compatible = "allwinner,sun4i-a10-ahb-clk";
110 reg = <0x01c20054 0x4>; 131 reg = <0x01c20054 0x4>;
111 clocks = <&axi>; 132 clocks = <&axi>;
133 clock-output-names = "ahb";
112 }; 134 };
113 135
114 ahb_gates: ahb_gates@01c20060 { 136 ahb_gates: clk@01c20060 {
115 #clock-cells = <1>; 137 #clock-cells = <1>;
116 compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 138 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
117 reg = <0x01c20060 0x8>; 139 reg = <0x01c20060 0x8>;
@@ -133,12 +155,13 @@
133 155
134 apb0: apb0@01c20054 { 156 apb0: apb0@01c20054 {
135 #clock-cells = <0>; 157 #clock-cells = <0>;
136 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
137 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
138 clocks = <&ahb>; 160 clocks = <&ahb>;
161 clock-output-names = "apb0";
139 }; 162 };
140 163
141 apb0_gates: apb0_gates@01c20068 { 164 apb0_gates: clk@01c20068 {
142 #clock-cells = <1>; 165 #clock-cells = <1>;
143 compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 166 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
144 reg = <0x01c20068 0x4>; 167 reg = <0x01c20068 0x4>;
@@ -151,19 +174,21 @@
151 174
152 apb1_mux: apb1_mux@01c20058 { 175 apb1_mux: apb1_mux@01c20058 {
153 #clock-cells = <0>; 176 #clock-cells = <0>;
154 compatible = "allwinner,sun4i-apb1-mux-clk"; 177 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
155 reg = <0x01c20058 0x4>; 178 reg = <0x01c20058 0x4>;
156 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
180 clock-output-names = "apb1_mux";
157 }; 181 };
158 182
159 apb1: apb1@01c20058 { 183 apb1: apb1@01c20058 {
160 #clock-cells = <0>; 184 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-apb1-clk"; 185 compatible = "allwinner,sun4i-a10-apb1-clk";
162 reg = <0x01c20058 0x4>; 186 reg = <0x01c20058 0x4>;
163 clocks = <&apb1_mux>; 187 clocks = <&apb1_mux>;
188 clock-output-names = "apb1";
164 }; 189 };
165 190
166 apb1_gates: apb1_gates@01c2006c { 191 apb1_gates: clk@01c2006c {
167 #clock-cells = <1>; 192 #clock-cells = <1>;
168 compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 193 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
169 reg = <0x01c2006c 0x4>; 194 reg = <0x01c2006c 0x4>;
@@ -178,7 +203,7 @@
178 203
179 nand_clk: clk@01c20080 { 204 nand_clk: clk@01c20080 {
180 #clock-cells = <0>; 205 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-mod0-clk"; 206 compatible = "allwinner,sun4i-a10-mod0-clk";
182 reg = <0x01c20080 0x4>; 207 reg = <0x01c20080 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
184 clock-output-names = "nand"; 209 clock-output-names = "nand";
@@ -186,7 +211,7 @@
186 211
187 ms_clk: clk@01c20084 { 212 ms_clk: clk@01c20084 {
188 #clock-cells = <0>; 213 #clock-cells = <0>;
189 compatible = "allwinner,sun4i-mod0-clk"; 214 compatible = "allwinner,sun4i-a10-mod0-clk";
190 reg = <0x01c20084 0x4>; 215 reg = <0x01c20084 0x4>;
191 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
192 clock-output-names = "ms"; 217 clock-output-names = "ms";
@@ -194,7 +219,7 @@
194 219
195 mmc0_clk: clk@01c20088 { 220 mmc0_clk: clk@01c20088 {
196 #clock-cells = <0>; 221 #clock-cells = <0>;
197 compatible = "allwinner,sun4i-mod0-clk"; 222 compatible = "allwinner,sun4i-a10-mod0-clk";
198 reg = <0x01c20088 0x4>; 223 reg = <0x01c20088 0x4>;
199 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
200 clock-output-names = "mmc0"; 225 clock-output-names = "mmc0";
@@ -202,7 +227,7 @@
202 227
203 mmc1_clk: clk@01c2008c { 228 mmc1_clk: clk@01c2008c {
204 #clock-cells = <0>; 229 #clock-cells = <0>;
205 compatible = "allwinner,sun4i-mod0-clk"; 230 compatible = "allwinner,sun4i-a10-mod0-clk";
206 reg = <0x01c2008c 0x4>; 231 reg = <0x01c2008c 0x4>;
207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
208 clock-output-names = "mmc1"; 233 clock-output-names = "mmc1";
@@ -210,7 +235,7 @@
210 235
211 mmc2_clk: clk@01c20090 { 236 mmc2_clk: clk@01c20090 {
212 #clock-cells = <0>; 237 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-mod0-clk"; 238 compatible = "allwinner,sun4i-a10-mod0-clk";
214 reg = <0x01c20090 0x4>; 239 reg = <0x01c20090 0x4>;
215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
216 clock-output-names = "mmc2"; 241 clock-output-names = "mmc2";
@@ -218,7 +243,7 @@
218 243
219 mmc3_clk: clk@01c20094 { 244 mmc3_clk: clk@01c20094 {
220 #clock-cells = <0>; 245 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-mod0-clk"; 246 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20094 0x4>; 247 reg = <0x01c20094 0x4>;
223 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
224 clock-output-names = "mmc3"; 249 clock-output-names = "mmc3";
@@ -226,7 +251,7 @@
226 251
227 ts_clk: clk@01c20098 { 252 ts_clk: clk@01c20098 {
228 #clock-cells = <0>; 253 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-mod0-clk"; 254 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c20098 0x4>; 255 reg = <0x01c20098 0x4>;
231 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
232 clock-output-names = "ts"; 257 clock-output-names = "ts";
@@ -234,7 +259,7 @@
234 259
235 ss_clk: clk@01c2009c { 260 ss_clk: clk@01c2009c {
236 #clock-cells = <0>; 261 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-mod0-clk"; 262 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c2009c 0x4>; 263 reg = <0x01c2009c 0x4>;
239 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
240 clock-output-names = "ss"; 265 clock-output-names = "ss";
@@ -242,7 +267,7 @@
242 267
243 spi0_clk: clk@01c200a0 { 268 spi0_clk: clk@01c200a0 {
244 #clock-cells = <0>; 269 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-mod0-clk"; 270 compatible = "allwinner,sun4i-a10-mod0-clk";
246 reg = <0x01c200a0 0x4>; 271 reg = <0x01c200a0 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "spi0"; 273 clock-output-names = "spi0";
@@ -250,7 +275,7 @@
250 275
251 spi1_clk: clk@01c200a4 { 276 spi1_clk: clk@01c200a4 {
252 #clock-cells = <0>; 277 #clock-cells = <0>;
253 compatible = "allwinner,sun4i-mod0-clk"; 278 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c200a4 0x4>; 279 reg = <0x01c200a4 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "spi1"; 281 clock-output-names = "spi1";
@@ -258,7 +283,7 @@
258 283
259 spi2_clk: clk@01c200a8 { 284 spi2_clk: clk@01c200a8 {
260 #clock-cells = <0>; 285 #clock-cells = <0>;
261 compatible = "allwinner,sun4i-mod0-clk"; 286 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c200a8 0x4>; 287 reg = <0x01c200a8 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "spi2"; 289 clock-output-names = "spi2";
@@ -266,7 +291,7 @@
266 291
267 pata_clk: clk@01c200ac { 292 pata_clk: clk@01c200ac {
268 #clock-cells = <0>; 293 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-mod0-clk"; 294 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c200ac 0x4>; 295 reg = <0x01c200ac 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "pata"; 297 clock-output-names = "pata";
@@ -274,7 +299,7 @@
274 299
275 ir0_clk: clk@01c200b0 { 300 ir0_clk: clk@01c200b0 {
276 #clock-cells = <0>; 301 #clock-cells = <0>;
277 compatible = "allwinner,sun4i-mod0-clk"; 302 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c200b0 0x4>; 303 reg = <0x01c200b0 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "ir0"; 305 clock-output-names = "ir0";
@@ -282,15 +307,24 @@
282 307
283 ir1_clk: clk@01c200b4 { 308 ir1_clk: clk@01c200b4 {
284 #clock-cells = <0>; 309 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-mod0-clk"; 310 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c200b4 0x4>; 311 reg = <0x01c200b4 0x4>;
287 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clock-output-names = "ir1"; 313 clock-output-names = "ir1";
289 }; 314 };
290 315
316 usb_clk: clk@01c200cc {
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 compatible = "allwinner,sun4i-a10-usb-clk";
320 reg = <0x01c200cc 0x4>;
321 clocks = <&pll6 1>;
322 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
323 };
324
291 spi3_clk: clk@01c200d4 { 325 spi3_clk: clk@01c200d4 {
292 #clock-cells = <0>; 326 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-mod0-clk"; 327 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c200d4 0x4>; 328 reg = <0x01c200d4 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clock-output-names = "spi3"; 330 clock-output-names = "spi3";
@@ -298,13 +332,41 @@
298 332
299 mbus_clk: clk@01c2015c { 333 mbus_clk: clk@01c2015c {
300 #clock-cells = <0>; 334 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-mod0-clk"; 335 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c2015c 0x4>; 336 reg = <0x01c2015c 0x4>;
303 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 337 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
304 clock-output-names = "mbus"; 338 clock-output-names = "mbus";
305 }; 339 };
306 340
307 /* 341 /*
342 * The following two are dummy clocks, placeholders used in the gmac_tx
343 * clock. The gmac driver will choose one parent depending on the PHY
344 * interface mode, using clk_set_rate auto-reparenting.
345 * The actual TX clock rate is not controlled by the gmac_tx clock.
346 */
347 mii_phy_tx_clk: clk@2 {
348 #clock-cells = <0>;
349 compatible = "fixed-clock";
350 clock-frequency = <25000000>;
351 clock-output-names = "mii_phy_tx";
352 };
353
354 gmac_int_tx_clk: clk@3 {
355 #clock-cells = <0>;
356 compatible = "fixed-clock";
357 clock-frequency = <125000000>;
358 clock-output-names = "gmac_int_tx";
359 };
360
361 gmac_tx_clk: clk@01c20164 {
362 #clock-cells = <0>;
363 compatible = "allwinner,sun7i-a20-gmac-clk";
364 reg = <0x01c20164 0x4>;
365 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
366 clock-output-names = "gmac_tx";
367 };
368
369 /*
308 * Dummy clock used by output clocks 370 * Dummy clock used by output clocks
309 */ 371 */
310 osc24M_32k: clk@1 { 372 osc24M_32k: clk@1 {
@@ -339,6 +401,28 @@
339 #size-cells = <1>; 401 #size-cells = <1>;
340 ranges; 402 ranges;
341 403
404 spi0: spi@01c05000 {
405 compatible = "allwinner,sun4i-a10-spi";
406 reg = <0x01c05000 0x1000>;
407 interrupts = <0 10 4>;
408 clocks = <&ahb_gates 20>, <&spi0_clk>;
409 clock-names = "ahb", "mod";
410 status = "disabled";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 };
414
415 spi1: spi@01c06000 {
416 compatible = "allwinner,sun4i-a10-spi";
417 reg = <0x01c06000 0x1000>;
418 interrupts = <0 11 4>;
419 clocks = <&ahb_gates 21>, <&spi1_clk>;
420 clock-names = "ahb", "mod";
421 status = "disabled";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 };
425
342 emac: ethernet@01c0b000 { 426 emac: ethernet@01c0b000 {
343 compatible = "allwinner,sun4i-a10-emac"; 427 compatible = "allwinner,sun4i-a10-emac";
344 reg = <0x01c0b000 0x1000>; 428 reg = <0x01c0b000 0x1000>;
@@ -355,6 +439,28 @@
355 #size-cells = <0>; 439 #size-cells = <0>;
356 }; 440 };
357 441
442 spi2: spi@01c17000 {
443 compatible = "allwinner,sun4i-a10-spi";
444 reg = <0x01c17000 0x1000>;
445 interrupts = <0 12 4>;
446 clocks = <&ahb_gates 22>, <&spi2_clk>;
447 clock-names = "ahb", "mod";
448 status = "disabled";
449 #address-cells = <1>;
450 #size-cells = <0>;
451 };
452
453 spi3: spi@01c1f000 {
454 compatible = "allwinner,sun4i-a10-spi";
455 reg = <0x01c1f000 0x1000>;
456 interrupts = <0 50 4>;
457 clocks = <&ahb_gates 23>, <&spi3_clk>;
458 clock-names = "ahb", "mod";
459 status = "disabled";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 };
463
358 pio: pinctrl@01c20800 { 464 pio: pinctrl@01c20800 {
359 compatible = "allwinner,sun7i-a20-pinctrl"; 465 compatible = "allwinner,sun7i-a20-pinctrl";
360 reg = <0x01c20800 0x400>; 466 reg = <0x01c20800 0x400>;
@@ -373,6 +479,13 @@
373 allwinner,pull = <0>; 479 allwinner,pull = <0>;
374 }; 480 };
375 481
482 uart2_pins_a: uart2@0 {
483 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
484 allwinner,function = "uart2";
485 allwinner,drive = <0>;
486 allwinner,pull = <0>;
487 };
488
376 uart6_pins_a: uart6@0 { 489 uart6_pins_a: uart6@0 {
377 allwinner,pins = "PI12", "PI13"; 490 allwinner,pins = "PI12", "PI13";
378 allwinner,function = "uart6"; 491 allwinner,function = "uart6";
@@ -432,6 +545,46 @@
432 allwinner,drive = <0>; 545 allwinner,drive = <0>;
433 allwinner,pull = <0>; 546 allwinner,pull = <0>;
434 }; 547 };
548
549 gmac_pins_mii_a: gmac_mii@0 {
550 allwinner,pins = "PA0", "PA1", "PA2",
551 "PA3", "PA4", "PA5", "PA6",
552 "PA7", "PA8", "PA9", "PA10",
553 "PA11", "PA12", "PA13", "PA14",
554 "PA15", "PA16";
555 allwinner,function = "gmac";
556 allwinner,drive = <0>;
557 allwinner,pull = <0>;
558 };
559
560 gmac_pins_rgmii_a: gmac_rgmii@0 {
561 allwinner,pins = "PA0", "PA1", "PA2",
562 "PA3", "PA4", "PA5", "PA6",
563 "PA7", "PA8", "PA10",
564 "PA11", "PA12", "PA13",
565 "PA15", "PA16";
566 allwinner,function = "gmac";
567 /*
568 * data lines in RGMII mode use DDR mode
569 * and need a higher signal drive strength
570 */
571 allwinner,drive = <3>;
572 allwinner,pull = <0>;
573 };
574
575 spi1_pins_a: spi1@0 {
576 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
577 allwinner,function = "spi1";
578 allwinner,drive = <0>;
579 allwinner,pull = <0>;
580 };
581
582 spi2_pins_a: spi2@0 {
583 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
584 allwinner,function = "spi2";
585 allwinner,drive = <0>;
586 allwinner,pull = <0>;
587 };
435 }; 588 };
436 589
437 timer@01c20c00 { 590 timer@01c20c00 {
@@ -593,6 +746,21 @@
593 status = "disabled"; 746 status = "disabled";
594 }; 747 };
595 748
749 gmac: ethernet@01c50000 {
750 compatible = "allwinner,sun7i-a20-gmac";
751 reg = <0x01c50000 0x10000>;
752 interrupts = <0 85 4>;
753 interrupt-names = "macirq";
754 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
755 clock-names = "stmmaceth", "allwinner_gmac_tx";
756 snps,pbl = <2>;
757 snps,fixed-burst;
758 snps,force_sf_dma_mode;
759 status = "disabled";
760 #address-cells = <1>;
761 #size-cells = <0>;
762 };
763
596 hstimer@01c60000 { 764 hstimer@01c60000 {
597 compatible = "allwinner,sun7i-a20-hstimer"; 765 compatible = "allwinner,sun7i-a20-hstimer";
598 reg = <0x01c60000 0x1000>; 766 reg = <0x01c60000 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 12:17:31 -0400