178 files changed, 4157 insertions, 3386 deletions

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 91f26148af79..fc81a7d6b0f1 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -1,3 +1,15 @@
+ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
+-----------------------------------------------------------------------------
+ARM's oldest Linux-supported platform with connectors for different core
+tiles of ARMv4, ARMv5 and ARMv6 type.
+
+Required properties (in root node):
+        compatible = "arm,integrator-ap";  /* Application Platform */
+        compatible = "arm,integrator-cp";  /* Compact Platform */
+
+FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
+
+
 ARM Versatile Application and Platform Baseboards
 -------------------------------------------------
 ARM's development hardware platform with connectors for customizable
diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
new file mode 100644
index 000000000000..9989eda755d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
@@ -0,0 +1,31 @@
+* ARM Versatile FPGA interrupt controller
+
+One or more FPGA IRQ controllers can be synthesized in an ARM reference board
+such as the Integrator or Versatile family. The output of these different
+controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
+instance can handle up to 32 interrupts.
+
+Required properties:
+- compatible: "arm,versatile-fpga-irq"
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: The number of cells to define the interrupts.  Must be 1
+  as the FPGA IRQ controller has no configuration options for interrupt
+  sources.  The cell is a u32 and defines the interrupt number.
+- reg: The register bank for the FPGA interrupt controller.
+- clear-mask: a u32 number representing the mask written to clear all IRQs
+  on the controller at boot for example.
+- valid-mask: a u32 number representing a bit mask determining which of
+  the interrupts are valid. Unconnected/unused lines are set to 0, and
+  the system till not make it possible for devices to request these
+  interrupts.
+
+Example:
+
+pic: pic@14000000 {
+        compatible = "arm,versatile-fpga-irq";
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        reg = <0x14000000 0x100>;
+        clear-mask = <0xffffffff>;
+        valid-mask = <0x003fffff>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
index 548892c08c59..7da578d72123 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
@@ -7,7 +7,7 @@ as "armctrl" in the SoC documentation, hence naming of this binding.
 
 Required properties:
 
-- compatible : should be "brcm,bcm2835-armctrl-ic.txt"
+- compatible : should be "brcm,bcm2835-armctrl-ic"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
index 2de21c2acf55..844bd5fbd04c 100644
--- a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
+++ b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
@@ -7,7 +7,7 @@ free running counter values, and generates an interrupt.
 
 Required properties:
 
-- compatible : should be "brcm,bcm2835-system-timer.txt"
+- compatible : should be "brcm,bcm2835-system-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 4 interrupt sinks; one per timer channel.
 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c0065c777e9b..5520b033ee84 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
         select HAVE_ARCH_KGDB
         select HAVE_ARCH_TRACEHOOK
+        select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_KPROBES if !XIP_KERNEL
         select HAVE_KRETPROBES if (HAVE_KPROBES)
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -490,7 +491,6 @@ config ARCH_IOP32X
         depends on MMU
         select CPU_XSCALE
         select NEED_MACH_GPIO_H
-        select NEED_MACH_IO_H
         select NEED_RET_TO_USER
         select PLAT_IOP
         select PCI
@@ -504,7 +504,6 @@ config ARCH_IOP33X
         depends on MMU
         select CPU_XSCALE
         select NEED_MACH_GPIO_H
-        select NEED_MACH_IO_H
         select NEED_RET_TO_USER
         select PLAT_IOP
         select PCI
@@ -1402,6 +1401,16 @@ config PL310_ERRATA_769419
           on systems with an outer cache, the store buffer is drained
           explicitly.
 
+config ARM_ERRATA_775420
+       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+         operation aborts with MMU exception, it might cause the processor
+         to deadlock. This workaround puts DSB before executing ISB if
+         an abort may occur on cache maintenance.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1787,8 +1796,8 @@ config ALIGNMENT_TRAP
           configuration it is safe to say N, otherwise say Y.
 
 config UACCESS_WITH_MEMCPY
-        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
-        depends on MMU && EXPERIMENTAL
+        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
+        depends on MMU
         default y if CPU_FEROCEON
         help
           Implement faster copy_to_user and clear_user methods for CPU
@@ -1829,12 +1838,6 @@ config CC_STACKPROTECTOR
           neutralized via a kernel panic.
           This feature requires gcc version 4.2 or above.
 
-config DEPRECATED_PARAM_STRUCT
-        bool "Provide old way to pass kernel parameters"
-        help
-          This was deprecated in 2001 and announced to live on for 5 years.
-          Some old boot loaders still use this way.
-
 config XEN_DOM0
         def_bool y
         depends on XEN
@@ -1857,6 +1860,23 @@ config USE_OF
         help
           Include support for flattened device tree machine descriptions.
 
+config ATAGS
+        bool "Support for the traditional ATAGS boot data passing" if USE_OF
+        default y
+        help
+          This is the traditional way of passing data to the kernel at boot
+          time. If you are solely relying on the flattened device tree (or
+          the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
+          to remove ATAGS support from your kernel binary.  If unsure,
+          leave this to y.
+
+config DEPRECATED_PARAM_STRUCT
+        bool "Provide old way to pass kernel parameters"
+        depends on ATAGS
+        help
+          This was deprecated in 2001 and announced to live on for 5 years.
+          Some old boot loaders still use this way.
+
 # Compressed boot loader in ROM.  Yes, we really want to ask about
 # TEXT and BSS so we preserve their values in the config files.
 config ZBOOT_ROM_TEXT
@@ -1983,6 +2003,7 @@ config CMDLINE
 choice
         prompt "Kernel command line type" if CMDLINE != ""
         default CMDLINE_FROM_BOOTLOADER
+        depends on ATAGS
 
 config CMDLINE_FROM_BOOTLOADER
         bool "Use bootloader kernel arguments if available"
@@ -2052,7 +2073,7 @@ config KEXEC
 
 config ATAGS_PROC
         bool "Export atags in procfs"
-        depends on KEXEC
+        depends on ATAGS && KEXEC
         default y
         help
           Should the atags used to boot the kernel be exported in an "atags"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 40ea991b6782..f023e3acdfbd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -269,7 +269,12 @@ else
 KBUILD_IMAGE := zImage
 endif
 
-all:    $(KBUILD_IMAGE)
+# Build the DT binary blobs if we have OF configured
+ifeq ($(CONFIG_USE_OF),y)
+KBUILD_DTBS := dtbs
+endif
+
+all:    $(KBUILD_IMAGE) $(KBUILD_DTBS)
 
 boot := arch/arm/boot
 
@@ -307,7 +312,7 @@ define archhelp
   echo  '  uImage        - U-Boot wrapped zImage'
   echo  '  bootpImage    - Combined zImage and initial RAM disk' 
   echo  '                  (supply initrd image via make variable INITRD=<path>)'
-  echo  '  dtbs          - Build device tree blobs for enabled boards'
+  echo  '* dtbs          - Build device tree blobs for enabled boards'
   echo  '  install       - Install uncompressed kernel'
   echo  '  zinstall      - Install compressed kernel'
   echo  '  uinstall      - Install U-Boot wrapped compressed kernel'
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index f41b38cafce8..9deb56a702ce 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -32,6 +32,9 @@ extern void error(char *);
 #  define Tracecv(c,x)
 #endif
 
+/* Not needed, but used in some headers pulled in by decompressors */
+extern char * strstr(const char * s1, const char *s2);
+
 #ifdef CONFIG_KERNEL_GZIP
 #include "../../../../lib/decompress_inflate.c"
 #endif
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5c28db351c28..c1ce813fcc4a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -25,14 +25,6 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-trats.dtb \
         exynos5250-smdk5250.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
-dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
-        imx53-ard.dtb \
-        imx53-evk.dtb \
-        imx53-qsb.dtb \
-        imx53-smd.dtb
-dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
-        imx6q-sabrelite.dtb \
-        imx6q-sabresd.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
@@ -106,5 +98,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca15-tc1.dtb \
         vexpress-v2p-ca15_a7.dtb \
         xenvm-4.2.dtb
+dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
+        wm8505-ref.dtb \
+        wm8650-mid.dtb
 
 endif
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
new file mode 100644
index 000000000000..813b91d7bea2
--- /dev/null
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -0,0 +1,76 @@
+/*
+ * SoC core Device Tree for the ARM Integrator platforms
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        timer@13000000 {
+                reg = <0x13000000 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <5>;
+        };
+
+        timer@13000100 {
+                reg = <0x13000100 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <6>;
+        };
+
+        timer@13000200 {
+                reg = <0x13000200 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <7>;
+        };
+
+        pic@14000000 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0x14000000 0x100>;
+                clear-mask = <0xffffffff>;
+        };
+
+        flash@24000000 {
+                compatible = "cfi-flash";
+                reg = <0x24000000 0x02000000>;
+        };
+
+        fpga {
+                compatible = "arm,amba-bus", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                interrupt-parent = <&pic>;
+
+                /*
+                 * These PrimeCells are in the same locations and using the
+                 * same interrupts in all Integrators, however the silicon
+                 * version deployed is different.
+                 */
+                rtc@15000000 {
+                        reg = <0x15000000 0x1000>;
+                        interrupts = <8>;
+                };
+
+                uart@16000000 {
+                        reg = <0x16000000 0x1000>;
+                        interrupts = <1>;
+                };
+
+                uart@17000000 {
+                        reg = <0x17000000 0x1000>;
+                        interrupts = <2>;
+                };
+
+                kmi@18000000 {
+                        reg = <0x18000000 0x1000>;
+                        interrupts = <3>;
+                };
+
+                kmi@19000000 {
+                        reg = <0x19000000 0x1000>;
+                        interrupts = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
new file mode 100644
index 000000000000..61767757b50a
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -0,0 +1,68 @@
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ */
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+        model = "ARM Integrator/AP";
+        compatible = "arm,integrator-ap";
+
+        aliases {
+                arm,timer-primary = &timer2;
+                arm,timer-secondary = &timer1;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
+        };
+
+        timer0: timer@13000000 {
+                compatible = "arm,integrator-timer";
+        };
+
+        timer1: timer@13000100 {
+                compatible = "arm,integrator-timer";
+        };
+
+        timer2: timer@13000200 {
+                compatible = "arm,integrator-timer";
+        };
+
+        pic: pic@14000000 {
+                valid-mask = <0x003fffff>;
+        };
+
+        fpga {
+                /*
+                 * The Integator/AP predates the idea to have magic numbers
+                 * identifying the PrimeCell in hardware, thus we have to
+                 * supply these from the device tree.
+                 */
+                rtc: rtc@15000000 {
+                        compatible = "arm,pl030", "arm,primecell";
+                        arm,primecell-periphid = <0x00041030>;
+                };
+
+                uart0: uart@16000000 {
+                        compatible = "arm,pl010", "arm,primecell";
+                        arm,primecell-periphid = <0x00041010>;
+                };
+
+                uart1: uart@17000000 {
+                        compatible = "arm,pl010", "arm,primecell";
+                        arm,primecell-periphid = <0x00041010>;
+                };
+
+                kmi0: kmi@18000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        arm,primecell-periphid = <0x00041050>;
+                };
+
+                kmi1: kmi@19000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        arm,primecell-periphid = <0x00041050>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
new file mode 100644
index 000000000000..2dd5e4e48481
--- /dev/null
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -0,0 +1,110 @@
+/*
+ * Device Tree for the ARM Integrator/CP platform
+ */
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+        model = "ARM Integrator/CP";
+        compatible = "arm,integrator-cp";
+
+        aliases {
+                arm,timer-primary = &timer2;
+                arm,timer-secondary = &timer1;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
+        };
+
+        timer0: timer@13000000 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+
+        timer1: timer@13000100 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+
+        timer2: timer@13000200 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+
+        pic: pic@14000000 {
+                valid-mask = <0x1fc003ff>;
+        };
+
+        cic: cic@10000040 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0x10000040 0x100>;
+                clear-mask = <0xffffffff>;
+                valid-mask = <0x00000007>;
+        };
+
+        sic: sic@ca000000 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0xca000000 0x100>;
+                clear-mask = <0x00000fff>;
+                valid-mask = <0x00000fff>;
+        };
+
+        ethernet@c8000000 {
+                compatible = "smsc,lan91c111";
+                reg = <0xc8000000 0x10>;
+                interrupt-parent = <&pic>;
+                interrupts = <27>;
+        };
+
+        fpga {
+                /*
+                 * These PrimeCells are at the same location and using
+                 * the same interrupts in all Integrators, but in the CP
+                 * slightly newer versions are deployed.
+                 */
+                rtc@15000000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                };
+
+                uart@16000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                };
+
+                uart@17000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                };
+
+                kmi@18000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                };
+
+                kmi@19000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                };
+
+                /*
+                 * These PrimeCells are only available on the Integrator/CP
+                 */
+                mmc@1c000000 {
+                        compatible = "arm,pl180", "arm,primecell";
+                        reg = <0x1c000000 0x1000>;
+                        interrupts = <23 24>;
+                        max-frequency = <515633>;
+                };
+
+                aaci@1d000000 {
+                        compatible = "arm,pl041", "arm,primecell";
+                        reg = <0x1d000000 0x1000>;
+                        interrupts = <25>;
+                };
+
+                clcd@c0000000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0xC0000000 0x1000>;
+                        interrupts = <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index e60dc7124e92..f0ba901676ac 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -539,7 +539,7 @@
                 nvidia,invert-interrupt;
         };
 
-        memory-controller@0x7000f400 {
+        memory-controller@7000f400 {
                 emc-table@190000 {
                         reg = <190000>;
                         compatible = "nvidia,tegra20-emc-table";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 67a6cd910b96..f3a09d0d45bc 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -170,7 +170,7 @@
                 reg = <0x7000e400 0x400>;
         };
 
-        memory-controller@0x7000f000 {
+        memory-controller@7000f000 {
                 compatible = "nvidia,tegra20-mc";
                 reg = <0x7000f000 0x024
                        0x7000f03c 0x3c4>;
@@ -183,7 +183,7 @@
                        0x58000000 0x02000000>;  /* GART aperture */
         };
 
-        memory-controller@0x7000f400 {
+        memory-controller@7000f400 {
                 compatible = "nvidia,tegra20-emc";
                 reg = <0x7000f400 0x200>;
                 #address-cells = <1>;
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index c4110d1b1f2d..001f4913799c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -284,11 +284,17 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
 
 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 {
-        it8152_io.start = IT8152_IO_BASE + 0x12000;
-        it8152_io.end   = IT8152_IO_BASE + 0x12000 + 0x100000;
+        /*
+         * FIXME: use pci_ioremap_io to remap the IO space here and
+         * move over to the generic io.h implementation.
+         * This requires solving the same problem for PXA PCMCIA
+         * support.
+         */
+        it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
+        it8152_io.end   = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
 
         sys->mem_offset = 0x10000000;
-        sys->io_offset  = IT8152_IO_BASE;
+        sys->io_offset  = (unsigned long)IT8152_IO_BASE;
 
         if (request_resource(&ioport_resource, &it8152_io)) {
                 printk(KERN_ERR "PCI: unable to allocate IO region\n");
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 960abceb8e14..8a7196ca5106 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -5,16 +5,33 @@ header-y += hwcap.h
 generic-y += auxvec.h
 generic-y += bitsperlong.h
 generic-y += cputime.h
+generic-y += current.h
 generic-y += emergency-restart.h
 generic-y += errno.h
+generic-y += exec.h
 generic-y += ioctl.h
+generic-y += ipcbuf.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += local.h
 generic-y += local64.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += parport.h
 generic-y += percpu.h
 generic-y += poll.h
 generic-y += resource.h
 generic-y += sections.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += shmbuf.h
 generic-y += siginfo.h
 generic-y += sizes.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += timex.h
+generic-y += types.h
+generic-y += unaligned.h
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e75475e57e..d40229d9a1c9 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -2,11 +2,12 @@
 #define __ASMARM_ARCH_TIMER_H
 
 #include <asm/errno.h>
+#include <linux/clocksource.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
-#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
+struct timecounter *arch_timer_get_timecounter(void);
 #else
 static inline int arch_timer_of_register(void)
 {
@@ -17,6 +18,11 @@ static inline int arch_timer_sched_clock_init(void)
 {
         return -ENXIO;
 }
+
+static inline struct timecounter *arch_timer_get_timecounter(void)
+{
+        return NULL;
+}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h
deleted file mode 100644
index 75d21e2a3ff7..000000000000
--- a/arch/arm/include/asm/current.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ASMARM_CURRENT_H
-#define _ASMARM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-static inline struct task_struct *get_current(void) __attribute_const__;
-
-static inline struct task_struct *get_current(void)
-{
-        return current_thread_info()->task;
-}
-
-#define current (get_current())
-
-#endif /* _ASMARM_CURRENT_H */
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index dc6145120de3..ab98fdd083bd 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -15,6 +15,11 @@
 
 #ifndef __ASSEMBLY__
 
+struct delay_timer {
+        unsigned long (*read_current_timer)(void);
+        unsigned long freq;
+};
+
 extern struct arm_delay_ops {
         void (*delay)(unsigned long);
         void (*const_udelay)(unsigned long);
@@ -56,6 +61,10 @@ extern void __loop_delay(unsigned long loops);
 extern void __loop_udelay(unsigned long usecs);
 extern void __loop_const_udelay(unsigned long);
 
+/* Delay-loop timer registration. */
+#define ARCH_HAS_READ_CURRENT_TIMER
+extern void register_current_timer_delay(const struct delay_timer *timer);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* defined(_ARM_DELAY_H) */
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
deleted file mode 100644
index 7c4fbef72b3a..000000000000
--- a/arch/arm/include/asm/exec.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARM_EXEC_H
-#define __ASM_ARM_EXEC_H
-
-#define arch_align_stack(x) (x)
-
-#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874377e6..4f8d2c0dc441 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -110,19 +110,19 @@
 #endif
 
 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
-//# ifdef _CACHE
+# ifdef _CACHE
 #  define MULTI_CACHE 1
-//# else
-//#  define _CACHE v6
-//# endif
+# else
+#  define _CACHE v6
+# endif
 #endif
 
 #if defined(CONFIG_CPU_V7)
-//# ifdef _CACHE
+# ifdef _CACHE
 #  define MULTI_CACHE 1
-//# else
-//#  define _CACHE v7
-//# endif
+# else
+#  define _CACHE v7
+# endif
 #endif
 
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 436e60b2cf7a..2740c2a2df63 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
 
-#define NR_IPI  5
+#define NR_IPI  6
 
 typedef struct {
         unsigned int __softirq_pending;
diff --git a/arch/arm/include/asm/hardware/linkup-l1110.h b/arch/arm/include/asm/hardware/linkup-l1110.h
deleted file mode 100644
index 7ec91168a576..000000000000
--- a/arch/arm/include/asm/hardware/linkup-l1110.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
-*
-* Definitions for H3600 Handheld Computer
-*
-* Copyright 2001 Compaq Computer Corporation.
-*
-* Use consistent with the GNU GPL is permitted,
-* provided that this copyright notice is
-* preserved in its entirety in all copies and derived works.
-*
-* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
-* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
-* FITNESS FOR ANY PARTICULAR PURPOSE.
-*
-* Author: Jamey Hicks.
-*
-*/
-
-/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
-
-/* PC Card Status Register */
-#define LINKUP_PRS_S1   (1 << 0) /* voltage control bits S1-S4 */
-#define LINKUP_PRS_S2   (1 << 1)
-#define LINKUP_PRS_S3   (1 << 2)
-#define LINKUP_PRS_S4   (1 << 3)
-#define LINKUP_PRS_BVD1 (1 << 4)
-#define LINKUP_PRS_BVD2 (1 << 5)
-#define LINKUP_PRS_VS1  (1 << 6)
-#define LINKUP_PRS_VS2  (1 << 7)
-#define LINKUP_PRS_RDY  (1 << 8)
-#define LINKUP_PRS_CD1  (1 << 9)
-#define LINKUP_PRS_CD2  (1 << 10)
-
-/* PC Card Command Register */
-#define LINKUP_PRC_S1   (1 << 0)
-#define LINKUP_PRC_S2   (1 << 1)
-#define LINKUP_PRC_S3   (1 << 2)
-#define LINKUP_PRC_S4   (1 << 3)
-#define LINKUP_PRC_RESET (1 << 4)
-#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
-#define LINKUP_PRC_CFE  (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
-#define LINKUP_PRC_SOE  (1 << 7) /* signal output driver enable */
-#define LINKUP_PRC_SSP  (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
-#define LINKUP_PRC_MBZ  (1 << 15) /* must be zero */
-
-struct linkup_l1110 {
-        volatile short prc;
-};
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 8f4db67533e5..35c1ed89b936 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,68 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v)))
-#define __raw_writew(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
-#define __raw_writel(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v)))
+#if __LINUX_ARM_ARCH__ < 6
+/*
+ * Half-word accesses are problematic with RiscPC due to limitations of
+ * the bus. Rather than special-case the machine, just let the compiler
+ * generate the access for CPUs prior to ARMv6.
+ */
+#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+#else
+/*
+ * When running under a hypervisor, we want to avoid I/O accesses with
+ * writeback addressing modes as these incur a significant performance
+ * overhead (the address generation must be emulated in software).
+ */
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+        asm volatile("strh %1, %0"
+                     : "+Qo" (*(volatile u16 __force *)addr)
+                     : "r" (val));
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+        u16 val;
+        asm volatile("ldrh %1, %0"
+                     : "+Qo" (*(volatile u16 __force *)addr),
+                       "=r" (val));
+        return val;
+}
+#endif
 
-#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
-#define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
-#define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+        asm volatile("strb %1, %0"
+                     : "+Qo" (*(volatile u8 __force *)addr)
+                     : "r" (val));
+}
+
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+        asm volatile("str %1, %0"
+                     : "+Qo" (*(volatile u32 __force *)addr)
+                     : "r" (val));
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+        u8 val;
+        asm volatile("ldrb %1, %0"
+                     : "+Qo" (*(volatile u8 __force *)addr),
+                       "=r" (val));
+        return val;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+        u32 val;
+        asm volatile("ldr %1, %0"
+                     : "+Qo" (*(volatile u32 __force *)addr),
+                       "=r" (val));
+        return val;
+}
 
 /*
  * Architecture ioremap implementation.
diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/arm/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/arm/include/asm/msgbuf.h b/arch/arm/include/asm/msgbuf.h
deleted file mode 100644
index 33b35b946eaa..000000000000
--- a/arch/arm/include/asm/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASMARM_MSGBUF_H
-#define _ASMARM_MSGBUF_H
-
-/* 
- * The msqid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        unsigned long   __unused1;
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        unsigned long   __unused2;
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long   __unused3;
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-
-#endif /* _ASMARM_MSGBUF_H */
diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
index b1479fd04a95..87c044910fe0 100644
--- a/arch/arm/include/asm/mutex.h
+++ b/arch/arm/include/asm/mutex.h
@@ -9,8 +9,13 @@
 #define _ASM_MUTEX_H
 /*
  * On pre-ARMv6 hardware this results in a swp-based implementation,
- * which is the most efficient. For ARMv6+, we emit a pair of exclusive
- * accesses instead.
+ * which is the most efficient. For ARMv6+, we have exclusive memory
+ * accessors and use atomic_dec to avoid the extra xchg operations
+ * on the locking slowpaths.
  */
+#if __LINUX_ARM_ARCH__ < 6
 #include <asm-generic/mutex-xchg.h>
+#else
+#include <asm-generic/mutex-dec.h>
 #endif
+#endif  /* _ASM_MUTEX_H */
diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 000000000000..b85665a96f8e
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,29 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(                                \
+        0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),    \
+        0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)     \
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 19c48deda70f..74e211a6fb24 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 
 
 /*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (       \
+          (((x) << 24) & 0xFF000000)    \
+        | (((x) <<  8) & 0x00FF0000)    \
+        | (((x) >>  8) & 0x0000FF00)    \
+        | (((x) >> 24) & 0x000000FF)    \
+)
+#define ___asm_opcode_swab16(x) (       \
+          (((x) << 8) & 0xFF00)         \
+        | (((x) >> 8) & 0x00FF)         \
+)
+#define ___asm_opcode_swahb32(x) (      \
+          (((x) << 8) & 0xFF00FF00)     \
+        | (((x) >> 8) & 0x00FF00FF)     \
+)
+#define ___asm_opcode_swahw32(x) (      \
+          (((x) << 16) & 0xFFFF0000)    \
+        | (((x) >> 16) & 0x0000FFFF)    \
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
  * Opcode byteswap helpers
  *
  * These macros help with converting instructions between a canonical integer
@@ -41,39 +68,163 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
  * represent any valid Thumb-2 instruction.  For this range,
  * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
  */
+#ifdef __ASSEMBLY__
 
-#ifndef __ASSEMBLY__
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
 
 #include <linux/types.h>
 #include <linux/swab.h>
 
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
 #ifdef CONFIG_CPU_ENDIAN_BE8
-#define __opcode_to_mem_arm(x) swab32(x)
-#define __opcode_to_mem_thumb16(x) swab16(x)
-#define __opcode_to_mem_thumb32(x) swahb32(x)
-#else
-#define __opcode_to_mem_arm(x) ((u32)(x))
-#define __opcode_to_mem_thumb16(x) ((u16)(x))
-#define __opcode_to_mem_thumb32(x) swahw32(x)
+
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
 #endif
 
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
 #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
 
 /* Operations specific to Thumb opcodes */
 
 /* Instruction size checks: */
-#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
-#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
+#define __opcode_is_thumb32(x) (                \
+           ((x) & 0xF8000000) == 0xE8000000     \
+        || ((x) & 0xF0000000) == 0xF0000000     \
+)
+#define __opcode_is_thumb16(x) (                                        \
+           ((x) & 0xFFFF0000) == 0                                      \
+        && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)      \
+)
 
 /* Operations to construct or split 32-bit Thumb instructions: */
-#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
-#define __opcode_thumb32_second(x) ((u16)(x))
-#define __opcode_thumb32_compose(first, second) \
-        (((u32)(u16)(first) << 16) | (u32)(u16)(second))
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (                       \
+          (___opcode_identity32(___opcode_identity16(first)) << 16)     \
+        | ___opcode_identity32(___opcode_identity16(second))            \
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (                      \
+          (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+        | ___asm_opcode_identity32(___asm_opcode_identity16(second))        \
+)
 
-#endif /* __ASSEMBLY__ */
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *      16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *      kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *      32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *      kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(                              \
+        ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),   \
+        ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))   \
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+        __inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+        __inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+        ".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
 
 #endif /* __ASM_ARM_OPCODES_H */
diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h
deleted file mode 100644
index 8b24bf94c06b..000000000000
--- a/arch/arm/include/asm/param.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  arch/arm/include/asm/param.h
- *
- *  Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PARAM_H
-#define __ASM_PARAM_H
-
-#ifdef __KERNEL__
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* User interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
-#else
-# define HZ             100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-/* max length of hostname */
-#define MAXHOSTNAMELEN  64
-
-#endif
-
diff --git a/arch/arm/include/asm/parport.h b/arch/arm/include/asm/parport.h
deleted file mode 100644
index 26e94b09035a..000000000000
--- a/arch/arm/include/asm/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  arch/arm/include/asm/parport.h: ARM-specific parport initialisation
- *
- *  Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-
-#ifndef __ASMARM_PARPORT_H
-#define __ASMARM_PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports (autoirq, autodma);
-}
-
-#endif /* !(_ASMARM_PARPORT_H) */
diff --git a/arch/arm/include/asm/segment.h b/arch/arm/include/asm/segment.h
deleted file mode 100644
index 9e24c21f6304..000000000000
--- a/arch/arm/include/asm/segment.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_ARM_SEGMENT_H
-#define __ASM_ARM_SEGMENT_H
-
-#define __KERNEL_CS   0x0
-#define __KERNEL_DS   0x0
-
-#define __USER_CS     0x1
-#define __USER_DS     0x1
-
-#endif /* __ASM_ARM_SEGMENT_H */
-
diff --git a/arch/arm/include/asm/sembuf.h b/arch/arm/include/asm/sembuf.h
deleted file mode 100644
index 1c0283954289..000000000000
--- a/arch/arm/include/asm/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASMARM_SEMBUF_H
-#define _ASMARM_SEMBUF_H
-
-/* 
- * The semid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;              /* last semop time */
-        unsigned long   __unused1;
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   __unused2;
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ASMARM_SEMBUF_H */
diff --git a/arch/arm/include/asm/serial.h b/arch/arm/include/asm/serial.h
deleted file mode 100644
index ebb049091e26..000000000000
--- a/arch/arm/include/asm/serial.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  arch/arm/include/asm/serial.h
- *
- *  Copyright (C) 1996 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   15-10-1996 RMK     Created
- */
-
-#ifndef __ASM_SERIAL_H
-#define __ASM_SERIAL_H
-
-#define BASE_BAUD       (1843200 / 16)
-
-#endif
diff --git a/arch/arm/include/asm/shmbuf.h b/arch/arm/include/asm/shmbuf.h
deleted file mode 100644
index 2e5c67ba1c97..000000000000
--- a/arch/arm/include/asm/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _ASMARM_SHMBUF_H
-#define _ASMARM_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-        unsigned long           __unused1;
-        __kernel_time_t         shm_dtime;      /* last detach time */
-        unsigned long           __unused2;
-        __kernel_time_t         shm_ctime;      /* last change time */
-        unsigned long           __unused3;
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused4;
-        unsigned long           __unused5;
-};
-
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ASMARM_SHMBUF_H */
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
deleted file mode 100644
index 6433cadb6ed4..000000000000
--- a/arch/arm/include/asm/socket.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef _ASMARM_SOCKET_H
-#define _ASMARM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET      1
-
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_ACCEPTCONN           30
-
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-#define SO_MARK                 36
-
-#define SO_TIMESTAMPING         37
-#define SCM_TIMESTAMPING        SO_TIMESTAMPING
-
-#define SO_PROTOCOL             38
-#define SO_DOMAIN               39
-
-#define SO_RXQ_OVFL             40
-
-#define SO_WIFI_STATUS          41
-#define SCM_WIFI_STATUS         SO_WIFI_STATUS
-#define SO_PEEK_OFF             42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS                43
-
-#endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/sockios.h b/arch/arm/include/asm/sockios.h
deleted file mode 100644
index a2588a2512df..000000000000
--- a/arch/arm/include/asm/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_ARM_SOCKIOS_H
-#define __ARCH_ARM_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-
-#endif
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23ddf75..9fdded6b1089 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -8,6 +8,11 @@
 #define _ASM_ARM_SYSCALL_H
 
 #include <linux/err.h>
+#include <linux/sched.h>
+
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
 
 extern const unsigned long sys_call_table[];
 
diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h
deleted file mode 100644
index 704135d28d1d..000000000000
--- a/arch/arm/include/asm/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __ASM_ARM_TERMBITS_H
-#define __ASM_ARM_TERMBITS_H
-
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-};
-
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000          /* input baud rate */
-#define CMSPAR    010000000000          /* mark or space (stick) parity */
-#define CRTSCTS   020000000000          /* flow control */
-
-#define IBSHIFT    16
-
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif  /* __ASM_ARM_TERMBITS_H */
diff --git a/arch/arm/include/asm/termios.h b/arch/arm/include/asm/termios.h
deleted file mode 100644
index 293e3f1bc3f2..000000000000
--- a/arch/arm/include/asm/termios.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __ASM_ARM_TERMIOS_H
-#define __ASM_ARM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-#ifdef __KERNEL__
-/*      intr=^C         quit=^|         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#endif
-
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) {              \
-        unsigned short __tmp;                                   \
-        get_user(__tmp,&(termio)->x);                           \
-        *(unsigned short *) &(termios)->x = __tmp;              \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif  /* __KERNEL__ */
-
-#endif  /* __ASM_ARM_TERMIOS_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bda3355..f71cdab18b87 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -59,7 +59,9 @@ struct thread_info {
         __u32                   syscall;        /* syscall number */
         __u8                    used_cp[16];    /* thread used copro */
         unsigned long           tp_value;
+#ifdef CONFIG_CRUNCH
         struct crunch_state     crunchstate;
+#endif
         union fp_state          fpstate __attribute__((aligned(8)));
         union vfp_state         vfpstate;
 #ifdef CONFIG_ARM_THUMBEE
@@ -148,6 +150,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
 #define TIF_SYSCALL_TRACE       8
 #define TIF_SYSCALL_AUDIT       9
+#define TIF_SYSCALL_TRACEPOINT  10
 #define TIF_POLLING_NRFLAG      16
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
@@ -160,12 +163,13 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 963342acebb7..83f2aa83899c 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,7 +12,6 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
-#include <asm/arch_timer.h>
 #ifdef CONFIG_ARCH_MULTIPLATFORM
 #define CLOCK_TICK_RATE 1000000
 #else
@@ -20,11 +19,6 @@
 #endif
 
 typedef unsigned long cycles_t;
-
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
 #define get_cycles()    ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
-#else
-#define get_cycles()    (0)
-#endif
 
 #endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
deleted file mode 100644
index 28beab917ffc..000000000000
--- a/arch/arm/include/asm/types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_ARM_TYPES_H
-#define __ASM_ARM_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#endif /* __KERNEL__ */
-
-#endif
-
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
deleted file mode 100644
index 44593a894903..000000000000
--- a/arch/arm/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#ifndef __ARMEB__
-#define get_unaligned   __get_unaligned_le
-#define put_unaligned   __put_unaligned_le
-#else
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-#endif
-
-#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2fde5fd1acce..d9ff5cc3a506 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -407,6 +407,14 @@
                                         /* 378 for kcmp */
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE                   (__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index d81f3a6d9ad8..5dfef9d97ed9 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -19,7 +19,9 @@ obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
                    process.o ptrace.o return_address.o sched_clock.o \
                    setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
-obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+obj-$(CONFIG_ATAGS)             += atags_parse.o
+obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
@@ -51,7 +53,6 @@ test-kprobes-objs		+= kprobes-test-thumb.o
 else
 test-kprobes-objs               += kprobes-test-arm.o
 endif
-obj-$(CONFIG_ATAGS_PROC)        += atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf258807160d..c8ef20747ee7 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -21,18 +21,28 @@
 #include <linux/io.h>
 
 #include <asm/cputype.h>
+#include <asm/delay.h>
 #include <asm/localtimer.h>
 #include <asm/arch_timer.h>
 #include <asm/system_info.h>
 #include <asm/sched_clock.h>
 
 static unsigned long arch_timer_rate;
-static int arch_timer_ppi;
-static int arch_timer_ppi2;
+
+enum ppi_nr {
+        PHYS_SECURE_PPI,
+        PHYS_NONSECURE_PPI,
+        VIRT_PPI,
+        HYP_PPI,
+        MAX_TIMER_PPI
+};
+
+static int arch_timer_ppi[MAX_TIMER_PPI];
 
 static struct clock_event_device __percpu **arch_timer_evt;
+static struct delay_timer arch_delay_timer;
 
-extern void init_current_timer_delay(unsigned long freq);
+static bool arch_timer_use_virtual = true;
 
 /*
  * Architected system timer support.
@@ -46,50 +56,104 @@ extern void init_current_timer_delay(unsigned long freq);
 #define ARCH_TIMER_REG_FREQ             1
 #define ARCH_TIMER_REG_TVAL             2
 
-static void arch_timer_reg_write(int reg, u32 val)
+#define ARCH_TIMER_PHYS_ACCESS          0
+#define ARCH_TIMER_VIRT_ACCESS          1
+
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code. At least it does so with a recent GCC (4.6.3).
+ */
+static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
 {
-        switch (reg) {
-        case ARCH_TIMER_REG_CTRL:
-                asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
-                break;
-        case ARCH_TIMER_REG_TVAL:
-                asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
-                break;
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+                        break;
+                }
+        }
+
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+                        break;
+                }
         }
 
         isb();
 }
 
-static u32 arch_timer_reg_read(int reg)
+static inline u32 arch_timer_reg_read(const int access, const int reg)
 {
-        u32 val;
+        u32 val = 0;
+
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_FREQ:
+                        asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+                        break;
+                }
+        }
 
-        switch (reg) {
-        case ARCH_TIMER_REG_CTRL:
-                asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
-                break;
-        case ARCH_TIMER_REG_FREQ:
-                asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
-                break;
-        case ARCH_TIMER_REG_TVAL:
-                asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
-                break;
-        default:
-                BUG();
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+                        break;
+                }
         }
 
         return val;
 }
 
-static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+static inline cycle_t arch_timer_counter_read(const int access)
 {
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        unsigned long ctrl;
+        cycle_t cval = 0;
+
+        if (access == ARCH_TIMER_PHYS_ACCESS)
+                asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+
+        if (access == ARCH_TIMER_VIRT_ACCESS)
+                asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
+
+        return cval;
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+        return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS);
+}
 
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+        return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS);
+}
+
+static irqreturn_t inline timer_handler(const int access,
+                                        struct clock_event_device *evt)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
                 evt->event_handler(evt);
                 return IRQ_HANDLED;
         }
@@ -97,63 +161,100 @@ static irqreturn_t arch_timer_handler(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static void arch_timer_disable(void)
+static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 {
-        unsigned long ctrl;
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
 
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
-        ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
-        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+        return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 }
 
-static void arch_timer_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *clk)
+static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 {
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+
+        return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
+}
+
+static inline void timer_set_mode(const int access, int mode)
+{
+        unsigned long ctrl;
         switch (mode) {
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
-                arch_timer_disable();
+                ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+                ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
                 break;
         default:
                 break;
         }
 }
 
-static int arch_timer_set_next_event(unsigned long evt,
-                                     struct clock_event_device *unused)
+static void arch_timer_set_mode_virt(enum clock_event_mode mode,
+                                     struct clock_event_device *clk)
 {
-        unsigned long ctrl;
+        timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
+}
 
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static void arch_timer_set_mode_phys(enum clock_event_mode mode,
+                                     struct clock_event_device *clk)
+{
+        timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
+}
+
+static inline void set_next_event(const int access, unsigned long evt)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
         ctrl |= ARCH_TIMER_CTRL_ENABLE;
         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+        arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
+        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+}
 
-        arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
-        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+static int arch_timer_set_next_event_virt(unsigned long evt,
+                                          struct clock_event_device *unused)
+{
+        set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
+        return 0;
+}
 
+static int arch_timer_set_next_event_phys(unsigned long evt,
+                                          struct clock_event_device *unused)
+{
+        set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
         return 0;
 }
 
 static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 {
-        /* Be safe... */
-        arch_timer_disable();
-
         clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
         clk->name = "arch_sys_timer";
         clk->rating = 450;
-        clk->set_mode = arch_timer_set_mode;
-        clk->set_next_event = arch_timer_set_next_event;
-        clk->irq = arch_timer_ppi;
+        if (arch_timer_use_virtual) {
+                clk->irq = arch_timer_ppi[VIRT_PPI];
+                clk->set_mode = arch_timer_set_mode_virt;
+                clk->set_next_event = arch_timer_set_next_event_virt;
+        } else {
+                clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
+                clk->set_mode = arch_timer_set_mode_phys;
+                clk->set_next_event = arch_timer_set_next_event_phys;
+        }
+
+        clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
 
         clockevents_config_and_register(clk, arch_timer_rate,
                                         0xf, 0x7fffffff);
 
         *__this_cpu_ptr(arch_timer_evt) = clk;
 
-        enable_percpu_irq(clk->irq, 0);
-        if (arch_timer_ppi2)
-                enable_percpu_irq(arch_timer_ppi2, 0);
+        if (arch_timer_use_virtual)
+                enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
+        else {
+                enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+        }
 
         return 0;
 }
@@ -173,8 +274,8 @@ static int arch_timer_available(void)
                 return -ENXIO;
 
         if (arch_timer_rate == 0) {
-                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
-                freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+                freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
+                                           ARCH_TIMER_REG_FREQ);
 
                 /* Check the timer frequency. */
                 if (freq == 0) {
@@ -185,52 +286,57 @@ static int arch_timer_available(void)
                 arch_timer_rate = freq;
         }
 
-        pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
-                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+        pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
+                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
+                     arch_timer_use_virtual ? "virt" : "phys");
         return 0;
 }
 
-static inline cycle_t arch_counter_get_cntpct(void)
+static u32 notrace arch_counter_get_cntpct32(void)
 {
-        u32 cvall, cvalh;
-
-        asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+        cycle_t cnt = arch_counter_get_cntpct();
 
-        return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static inline cycle_t arch_counter_get_cntvct(void)
-{
-        u32 cvall, cvalh;
-
-        asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-        return ((cycle_t) cvalh << 32) | cvall;
+        /*
+         * The sched_clock infrastructure only knows about counters
+         * with at most 32bits. Forget about the upper 24 bits for the
+         * time being...
+         */
+        return (u32)cnt;
 }
 
 static u32 notrace arch_counter_get_cntvct32(void)
 {
-        cycle_t cntvct = arch_counter_get_cntvct();
+        cycle_t cnt = arch_counter_get_cntvct();
 
         /*
          * The sched_clock infrastructure only knows about counters
          * with at most 32bits. Forget about the upper 24 bits for the
          * time being...
          */
-        return (u32)(cntvct & (u32)~0);
+        return (u32)cnt;
 }
 
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
+        /*
+         * Always use the physical counter for the clocksource.
+         * CNTHCTL.PL1PCTEN must be set to 1.
+         */
         return arch_counter_get_cntpct();
 }
 
-int read_current_timer(unsigned long *timer_val)
+static unsigned long arch_timer_read_current_timer(void)
 {
-        if (!arch_timer_rate)
-                return -ENXIO;
-        *timer_val = arch_counter_get_cntpct();
-        return 0;
+        return arch_counter_get_cntpct();
+}
+
+static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
+{
+        /*
+         * Always use the physical counter for the clocksource.
+         * CNTHCTL.PL1PCTEN must be set to 1.
+         */
+        return arch_counter_get_cntpct();
 }
 
 static struct clocksource clocksource_counter = {
@@ -241,14 +347,32 @@ static struct clocksource clocksource_counter = {
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct cyclecounter cyclecounter = {
+        .read   = arch_counter_read_cc,
+        .mask   = CLOCKSOURCE_MASK(56),
+};
+
+static struct timecounter timecounter;
+
+struct timecounter *arch_timer_get_timecounter(void)
+{
+        return &timecounter;
+}
+
 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
                  clk->irq, smp_processor_id());
-        disable_percpu_irq(clk->irq);
-        if (arch_timer_ppi2)
-                disable_percpu_irq(arch_timer_ppi2);
-        arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+
+        if (arch_timer_use_virtual)
+                disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
+        else {
+                disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+        }
+
+        clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 }
 
 static struct local_timer_ops arch_timer_ops __cpuinitdata = {
@@ -261,36 +385,48 @@ static struct clock_event_device arch_timer_global_evt;
 static int __init arch_timer_register(void)
 {
         int err;
+        int ppi;
 
         err = arch_timer_available();
         if (err)
-                return err;
+                goto out;
 
         arch_timer_evt = alloc_percpu(struct clock_event_device *);
-        if (!arch_timer_evt)
-                return -ENOMEM;
+        if (!arch_timer_evt) {
+                err = -ENOMEM;
+                goto out;
+        }
 
         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+        cyclecounter.mult = clocksource_counter.mult;
+        cyclecounter.shift = clocksource_counter.shift;
+        timecounter_init(&timecounter, &cyclecounter,
+                         arch_counter_get_cntpct());
+
+        if (arch_timer_use_virtual) {
+                ppi = arch_timer_ppi[VIRT_PPI];
+                err = request_percpu_irq(ppi, arch_timer_handler_virt,
+                                         "arch_timer", arch_timer_evt);
+        } else {
+                ppi = arch_timer_ppi[PHYS_SECURE_PPI];
+                err = request_percpu_irq(ppi, arch_timer_handler_phys,
+                                         "arch_timer", arch_timer_evt);
+                if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+                        ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
+                        err = request_percpu_irq(ppi, arch_timer_handler_phys,
+                                                 "arch_timer", arch_timer_evt);
+                        if (err)
+                                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+                                                arch_timer_evt);
+                }
+        }
 
-        err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
-                                 "arch_timer", arch_timer_evt);
         if (err) {
                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                       arch_timer_ppi, err);
+                       ppi, err);
                 goto out_free;
         }
 
-        if (arch_timer_ppi2) {
-                err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
-                                         "arch_timer", arch_timer_evt);
-                if (err) {
-                        pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                               arch_timer_ppi2, err);
-                        arch_timer_ppi2 = 0;
-                        goto out_free_irq;
-                }
-        }
-
         err = local_timer_register(&arch_timer_ops);
         if (err) {
                 /*
@@ -302,21 +438,29 @@ static int __init arch_timer_register(void)
                 arch_timer_global_evt.cpumask = cpumask_of(0);
                 err = arch_timer_setup(&arch_timer_global_evt);
         }
-
         if (err)
                 goto out_free_irq;
 
-        init_current_timer_delay(arch_timer_rate);
+        /* Use the architected timer for the delay loop. */
+        arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
+        arch_delay_timer.freq = arch_timer_rate;
+        register_current_timer_delay(&arch_delay_timer);
         return 0;
 
 out_free_irq:
-        free_percpu_irq(arch_timer_ppi, arch_timer_evt);
-        if (arch_timer_ppi2)
-                free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+        if (arch_timer_use_virtual)
+                free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
+        else {
+                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+                                arch_timer_evt);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
+                                        arch_timer_evt);
+        }
 
 out_free:
         free_percpu(arch_timer_evt);
-
+out:
         return err;
 }
 
@@ -329,6 +473,7 @@ int __init arch_timer_of_register(void)
 {
         struct device_node *np;
         u32 freq;
+        int i;
 
         np = of_find_matching_node(NULL, arch_timer_of_match);
         if (!np) {
@@ -340,22 +485,40 @@ int __init arch_timer_of_register(void)
         if (!of_property_read_u32(np, "clock-frequency", &freq))
                 arch_timer_rate = freq;
 
-        arch_timer_ppi = irq_of_parse_and_map(np, 0);
-        arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
-        pr_info("arch_timer: found %s irqs %d %d\n",
-                np->name, arch_timer_ppi, arch_timer_ppi2);
+        for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+                arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+
+        /*
+         * If no interrupt provided for virtual timer, we'll have to
+         * stick to the physical timer. It'd better be accessible...
+         */
+        if (!arch_timer_ppi[VIRT_PPI]) {
+                arch_timer_use_virtual = false;
+
+                if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
+                    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+                        pr_warn("arch_timer: No interrupt available, giving up\n");
+                        return -EINVAL;
+                }
+        }
 
         return arch_timer_register();
 }
 
 int __init arch_timer_sched_clock_init(void)
 {
+        u32 (*cnt32)(void);
         int err;
 
         err = arch_timer_available();
         if (err)
                 return err;
 
-        setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+        if (arch_timer_use_virtual)
+                cnt32 = arch_counter_get_cntvct32;
+        else
+                cnt32 = arch_counter_get_cntpct32;
+
+        setup_sched_clock(cnt32, 32, arch_timer_rate);
         return 0;
 }
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d8989fb9..c985b481192c 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -59,10 +59,12 @@ int main(void)
   DEFINE(TI_USED_CP,            offsetof(struct thread_info, used_cp));
   DEFINE(TI_TP_VALUE,           offsetof(struct thread_info, tp_value));
   DEFINE(TI_FPSTATE,            offsetof(struct thread_info, fpstate));
+#ifdef CONFIG_VFP
   DEFINE(TI_VFPSTATE,           offsetof(struct thread_info, vfpstate));
 #ifdef CONFIG_SMP
   DEFINE(VFP_CPU,               offsetof(union vfp_state, hard.cpu));
 #endif
+#endif
 #ifdef CONFIG_ARM_THUMBEE
   DEFINE(TI_THUMBEE_STATE,      offsetof(struct thread_info, thumbee_state));
 #endif
diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h
index e5f028d214a1..9edc9692332d 100644
--- a/arch/arm/kernel/atags.h
+++ b/arch/arm/kernel/atags.h
@@ -3,3 +3,17 @@ extern void save_atags(struct tag *tags);
 #else
 static inline void save_atags(struct tag *tags) { }
 #endif
+
+void convert_to_tag_list(struct tag *tags);
+
+#ifdef CONFIG_ATAGS
+struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr);
+#else
+static inline struct machine_desc *
+setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr)
+{
+        early_print("no ATAGS support: can't continue\n");
+        while (true);
+        unreachable();
+}
+#endif
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/atags_compat.c
index 925652318b8b..5236ad38f417 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/atags_compat.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/kernel/compat.c
+ *  linux/arch/arm/kernel/atags_compat.c
  *
  *  Copyright (C) 2001 Russell King
  *
@@ -26,7 +26,7 @@
 
 #include <asm/mach/arch.h>
 
-#include "compat.h"
+#include "atags.h"
 
 /*
  * Usage:
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
new file mode 100644
index 000000000000..14512e6931d8
--- /dev/null
+++ b/arch/arm/kernel/atags_parse.c
@@ -0,0 +1,238 @@
+/*
+ * Tag parsing.
+ *
+ * Copyright (C) 1995-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This is the traditional way of passing data to the kernel at boot time.  Rather
+ * than passing a fixed inflexible structure to the kernel, we pass a list
+ * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
+ * tag for the list to be recognised (to distinguish the tagged list from
+ * a param_struct).  The list is terminated with a zero-length tag (this tag
+ * is not parsed in any way).
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/screen_info.h>
+
+#include <asm/setup.h>
+#include <asm/system_info.h>
+#include <asm/page.h>
+#include <asm/mach/arch.h>
+
+#include "atags.h"
+
+static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
+
+#ifndef MEM_SIZE
+#define MEM_SIZE        (16*1024*1024)
+#endif
+
+static struct {
+        struct tag_header hdr1;
+        struct tag_core   core;
+        struct tag_header hdr2;
+        struct tag_mem32  mem;
+        struct tag_header hdr3;
+} default_tags __initdata = {
+        { tag_size(tag_core), ATAG_CORE },
+        { 1, PAGE_SIZE, 0xff },
+        { tag_size(tag_mem32), ATAG_MEM },
+        { MEM_SIZE },
+        { 0, ATAG_NONE }
+};
+
+static int __init parse_tag_core(const struct tag *tag)
+{
+        if (tag->hdr.size > 2) {
+                if ((tag->u.core.flags & 1) == 0)
+                        root_mountflags &= ~MS_RDONLY;
+                ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
+        }
+        return 0;
+}
+
+__tagtable(ATAG_CORE, parse_tag_core);
+
+static int __init parse_tag_mem32(const struct tag *tag)
+{
+        return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
+}
+
+__tagtable(ATAG_MEM, parse_tag_mem32);
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
+static int __init parse_tag_videotext(const struct tag *tag)
+{
+        screen_info.orig_x            = tag->u.videotext.x;
+        screen_info.orig_y            = tag->u.videotext.y;
+        screen_info.orig_video_page   = tag->u.videotext.video_page;
+        screen_info.orig_video_mode   = tag->u.videotext.video_mode;
+        screen_info.orig_video_cols   = tag->u.videotext.video_cols;
+        screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
+        screen_info.orig_video_lines  = tag->u.videotext.video_lines;
+        screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
+        screen_info.orig_video_points = tag->u.videotext.video_points;
+        return 0;
+}
+
+__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
+#endif
+
+#ifdef CONFIG_BLK_DEV_RAM
+static int __init parse_tag_ramdisk(const struct tag *tag)
+{
+        extern int rd_size, rd_image_start, rd_prompt, rd_doload;
+
+        rd_image_start = tag->u.ramdisk.start;
+        rd_doload = (tag->u.ramdisk.flags & 1) == 0;
+        rd_prompt = (tag->u.ramdisk.flags & 2) == 0;
+
+        if (tag->u.ramdisk.size)
+                rd_size = tag->u.ramdisk.size;
+
+        return 0;
+}
+
+__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
+#endif
+
+static int __init parse_tag_serialnr(const struct tag *tag)
+{
+        system_serial_low = tag->u.serialnr.low;
+        system_serial_high = tag->u.serialnr.high;
+        return 0;
+}
+
+__tagtable(ATAG_SERIAL, parse_tag_serialnr);
+
+static int __init parse_tag_revision(const struct tag *tag)
+{
+        system_rev = tag->u.revision.rev;
+        return 0;
+}
+
+__tagtable(ATAG_REVISION, parse_tag_revision);
+
+static int __init parse_tag_cmdline(const struct tag *tag)
+{
+#if defined(CONFIG_CMDLINE_EXTEND)
+        strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
+        strlcat(default_command_line, tag->u.cmdline.cmdline,
+                COMMAND_LINE_SIZE);
+#elif defined(CONFIG_CMDLINE_FORCE)
+        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
+#else
+        strlcpy(default_command_line, tag->u.cmdline.cmdline,
+                COMMAND_LINE_SIZE);
+#endif
+        return 0;
+}
+
+__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
+
+/*
+ * Scan the tag table for this tag, and call its parse function.
+ * The tag table is built by the linker from all the __tagtable
+ * declarations.
+ */
+static int __init parse_tag(const struct tag *tag)
+{
+        extern struct tagtable __tagtable_begin, __tagtable_end;
+        struct tagtable *t;
+
+        for (t = &__tagtable_begin; t < &__tagtable_end; t++)
+                if (tag->hdr.tag == t->tag) {
+                        t->parse(tag);
+                        break;
+                }
+
+        return t < &__tagtable_end;
+}
+
+/*
+ * Parse all tags in the list, checking both the global and architecture
+ * specific tag tables.
+ */
+static void __init parse_tags(const struct tag *t)
+{
+        for (; t->hdr.size; t = tag_next(t))
+                if (!parse_tag(t))
+                        printk(KERN_WARNING
+                                "Ignoring unrecognised tag 0x%08x\n",
+                                t->hdr.tag);
+}
+
+static void __init squash_mem_tags(struct tag *tag)
+{
+        for (; tag->hdr.size; tag = tag_next(tag))
+                if (tag->hdr.tag == ATAG_MEM)
+                        tag->hdr.tag = ATAG_NONE;
+}
+
+struct machine_desc * __init setup_machine_tags(phys_addr_t __atags_pointer,
+                                                unsigned int machine_nr)
+{
+        struct tag *tags = (struct tag *)&default_tags;
+        struct machine_desc *mdesc = NULL, *p;
+        char *from = default_command_line;
+
+        default_tags.mem.start = PHYS_OFFSET;
+
+        /*
+         * locate machine in the list of supported machines.
+         */
+        for_each_machine_desc(p)
+                if (machine_nr == p->nr) {
+                        printk("Machine: %s\n", p->name);
+                        mdesc = p;
+                        break;
+                }
+
+        if (!mdesc) {
+                early_print("\nError: unrecognized/unsupported machine ID"
+                            " (r1 = 0x%08x).\n\n", machine_nr);
+                dump_machine_table(); /* does not return */
+        }
+
+        if (__atags_pointer)
+                tags = phys_to_virt(__atags_pointer);
+        else if (mdesc->atag_offset)
+                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
+
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
+        /*
+         * If we have the old style parameters, convert them to
+         * a tag list.
+         */
+        if (tags->hdr.tag != ATAG_CORE)
+                convert_to_tag_list(tags);
+#endif
+        if (tags->hdr.tag != ATAG_CORE) {
+                early_print("Warning: Neither atags nor dtb found\n");
+                tags = (struct tag *)&default_tags;
+        }
+
+        if (mdesc->fixup)
+                mdesc->fixup(tags, &from, &meminfo);
+
+        if (tags->hdr.tag == ATAG_CORE) {
+                if (meminfo.nr_banks != 0)
+                        squash_mem_tags(tags);
+                save_atags(tags);
+                parse_tags(tags);
+        }
+
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+
+        return mdesc;
+}
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags_proc.c
index 42a1a1415fa6..42a1a1415fa6 100644
--- a/arch/arm/kernel/atags.c
+++ b/arch/arm/kernel/atags_proc.c
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
deleted file mode 100644
index 39264ab1b9c6..000000000000
--- a/arch/arm/kernel/compat.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  linux/arch/arm/kernel/compat.h
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void convert_to_tag_list(struct tag *tags);
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac57e04a..f45987037bf1 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
         .equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index dfcdb9f7c126..e29c3337ca81 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -8,7 +8,9 @@
 #include <linux/reboot.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/memblock.h>
 #include <asm/pgtable.h>
+#include <linux/of_fdt.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
@@ -32,6 +34,29 @@ static atomic_t waiting_for_crash_ipi;
 
 int machine_kexec_prepare(struct kimage *image)
 {
+        struct kexec_segment *current_segment;
+        __be32 header;
+        int i, err;
+
+        /*
+         * No segment at default ATAGs address. try to locate
+         * a dtb using magic.
+         */
+        for (i = 0; i < image->nr_segments; i++) {
+                current_segment = &image->segment[i];
+
+                err = memblock_is_region_memory(current_segment->mem,
+                                                current_segment->memsz);
+                if (err)
+                        return - EINVAL;
+
+                err = get_user(header, (__be32*)current_segment->buf);
+                if (err)
+                        return err;
+
+                if (be32_to_cpu(header) == OF_DT_HEADER)
+                        kexec_boot_atags = current_segment->mem;
+        }
         return 0;
 }
 
@@ -122,7 +147,9 @@ void machine_kexec(struct kimage *image)
         kexec_start_address = image->start;
         kexec_indirection_page = page_list;
         kexec_mach_type = machine_arch_type;
-        kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
+        if (!kexec_boot_atags)
+                kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
+
 
         /* copy our kernel relocation code to the control code page */
         memcpy(reboot_code_buffer,
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f7ed4b..739db3a1b2d2 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC  15
 #define REG_PSR 16
 /*
@@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
         unsigned long ip;
 
+        current_thread_info()->syscall = scno;
+
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
                 return scno;
 
-        current_thread_info()->syscall = scno;
-
         /*
          * IP is used to denote syscall entry/exit:
          * IP = 0 -> entry, =1 -> exit
@@ -941,15 +944,19 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
-        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_enter(regs, scno);
         audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
                             regs->ARM_r2, regs->ARM_r3);
-        return ret;
+        return scno;
 }
 
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
-        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_exit(regs, scno);
         audit_syscall_exit(regs);
-        return ret;
+        return scno;
 }
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index f4515393248d..e21bac20d90d 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -9,6 +9,7 @@
 #include <linux/init.h>
 #include <linux/jiffies.h>
 #include <linux/kernel.h>
+#include <linux/moduleparam.h>
 #include <linux/sched.h>
 #include <linux/syscore_ops.h>
 #include <linux/timer.h>
@@ -27,6 +28,9 @@ struct clock_data {
 
 static void sched_clock_poll(unsigned long wrap_ticks);
 static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
+static int irqtime = -1;
+
+core_param(irqtime, irqtime, int, 0400);
 
 static struct clock_data cd = {
         .mult   = NSEC_PER_SEC / HZ,
@@ -157,6 +161,10 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
          */
         cd.epoch_ns = 0;
 
+        /* Enable IRQ time accounting if we have a fast enough sched_clock */
+        if (irqtime > 0 || (irqtime == -1 && rate >= 1000000))
+                enable_sched_clock_irqtime();
+
         pr_debug("Registered %pF as sched_clock source\n", read);
 }
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 725f9f2a9541..febafa0f552d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -21,11 +21,9 @@
 #include <linux/init.h>
 #include <linux/kexec.h>
 #include <linux/of_fdt.h>
-#include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
-#include <linux/fs.h>
 #include <linux/proc_fs.h>
 #include <linux/memblock.h>
 #include <linux/bug.h>
@@ -56,15 +54,9 @@
 #include <asm/unwind.h>
 #include <asm/memblock.h>
 
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-#include "compat.h"
-#endif
 #include "atags.h"
 #include "tcm.h"
 
-#ifndef MEM_SIZE
-#define MEM_SIZE        (16*1024*1024)
-#endif
 
 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
 char fpe_type[8];
@@ -145,7 +137,6 @@ static const char *machine_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
 struct machine_desc *machine_desc __initdata;
 
-static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
 #define ENDIANNESS ((char)endian_test.l)
 
@@ -583,21 +574,6 @@ static int __init early_mem(char *p)
 }
 early_param("mem", early_mem);
 
-static void __init
-setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
-{
-#ifdef CONFIG_BLK_DEV_RAM
-        extern int rd_size, rd_image_start, rd_prompt, rd_doload;
-
-        rd_image_start = image_start;
-        rd_prompt = prompt;
-        rd_doload = doload;
-
-        if (rd_sz)
-                rd_size = rd_sz;
-#endif
-}
-
 static void __init request_standard_resources(struct machine_desc *mdesc)
 {
         struct memblock_region *region;
@@ -643,35 +619,6 @@ static void __init request_standard_resources(struct machine_desc *mdesc)
                 request_resource(&ioport_resource, &lp2);
 }
 
-/*
- *  Tag parsing.
- *
- * This is the new way of passing data to the kernel at boot time.  Rather
- * than passing a fixed inflexible structure to the kernel, we pass a list
- * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
- * tag for the list to be recognised (to distinguish the tagged list from
- * a param_struct).  The list is terminated with a zero-length tag (this tag
- * is not parsed in any way).
- */
-static int __init parse_tag_core(const struct tag *tag)
-{
-        if (tag->hdr.size > 2) {
-                if ((tag->u.core.flags & 1) == 0)
-                        root_mountflags &= ~MS_RDONLY;
-                ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
-        }
-        return 0;
-}
-
-__tagtable(ATAG_CORE, parse_tag_core);
-
-static int __init parse_tag_mem32(const struct tag *tag)
-{
-        return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
-}
-
-__tagtable(ATAG_MEM, parse_tag_mem32);
-
 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
 struct screen_info screen_info = {
  .orig_video_lines      = 30,
@@ -681,117 +628,8 @@ struct screen_info screen_info = {
  .orig_video_isVGA      = 1,
  .orig_video_points     = 8
 };
-
-static int __init parse_tag_videotext(const struct tag *tag)
-{
-        screen_info.orig_x            = tag->u.videotext.x;
-        screen_info.orig_y            = tag->u.videotext.y;
-        screen_info.orig_video_page   = tag->u.videotext.video_page;
-        screen_info.orig_video_mode   = tag->u.videotext.video_mode;
-        screen_info.orig_video_cols   = tag->u.videotext.video_cols;
-        screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
-        screen_info.orig_video_lines  = tag->u.videotext.video_lines;
-        screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
-        screen_info.orig_video_points = tag->u.videotext.video_points;
-        return 0;
-}
-
-__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
 #endif
 
-static int __init parse_tag_ramdisk(const struct tag *tag)
-{
-        setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
-                      (tag->u.ramdisk.flags & 2) == 0,
-                      tag->u.ramdisk.start, tag->u.ramdisk.size);
-        return 0;
-}
-
-__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
-
-static int __init parse_tag_serialnr(const struct tag *tag)
-{
-        system_serial_low = tag->u.serialnr.low;
-        system_serial_high = tag->u.serialnr.high;
-        return 0;
-}
-
-__tagtable(ATAG_SERIAL, parse_tag_serialnr);
-
-static int __init parse_tag_revision(const struct tag *tag)
-{
-        system_rev = tag->u.revision.rev;
-        return 0;
-}
-
-__tagtable(ATAG_REVISION, parse_tag_revision);
-
-static int __init parse_tag_cmdline(const struct tag *tag)
-{
-#if defined(CONFIG_CMDLINE_EXTEND)
-        strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
-        strlcat(default_command_line, tag->u.cmdline.cmdline,
-                COMMAND_LINE_SIZE);
-#elif defined(CONFIG_CMDLINE_FORCE)
-        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
-#else
-        strlcpy(default_command_line, tag->u.cmdline.cmdline,
-                COMMAND_LINE_SIZE);
-#endif
-        return 0;
-}
-
-__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
-
-/*
- * Scan the tag table for this tag, and call its parse function.
- * The tag table is built by the linker from all the __tagtable
- * declarations.
- */
-static int __init parse_tag(const struct tag *tag)
-{
-        extern struct tagtable __tagtable_begin, __tagtable_end;
-        struct tagtable *t;
-
-        for (t = &__tagtable_begin; t < &__tagtable_end; t++)
-                if (tag->hdr.tag == t->tag) {
-                        t->parse(tag);
-                        break;
-                }
-
-        return t < &__tagtable_end;
-}
-
-/*
- * Parse all tags in the list, checking both the global and architecture
- * specific tag tables.
- */
-static void __init parse_tags(const struct tag *t)
-{
-        for (; t->hdr.size; t = tag_next(t))
-                if (!parse_tag(t))
-                        printk(KERN_WARNING
-                                "Ignoring unrecognised tag 0x%08x\n",
-                                t->hdr.tag);
-}
-
-/*
- * This holds our defaults.
- */
-static struct init_tags {
-        struct tag_header hdr1;
-        struct tag_core   core;
-        struct tag_header hdr2;
-        struct tag_mem32  mem;
-        struct tag_header hdr3;
-} init_tags __initdata = {
-        { tag_size(tag_core), ATAG_CORE },
-        { 1, PAGE_SIZE, 0xff },
-        { tag_size(tag_mem32), ATAG_MEM },
-        { MEM_SIZE },
-        { 0, ATAG_NONE }
-};
-
 static int __init customize_machine(void)
 {
         /* customizes platform devices, or adds new ones */
@@ -858,78 +696,6 @@ static void __init reserve_crashkernel(void)
 static inline void reserve_crashkernel(void) {}
 #endif /* CONFIG_KEXEC */
 
-static void __init squash_mem_tags(struct tag *tag)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM)
-                        tag->hdr.tag = ATAG_NONE;
-}
-
-static struct machine_desc * __init setup_machine_tags(unsigned int nr)
-{
-        struct tag *tags = (struct tag *)&init_tags;
-        struct machine_desc *mdesc = NULL, *p;
-        char *from = default_command_line;
-
-        init_tags.mem.start = PHYS_OFFSET;
-
-        /*
-         * locate machine in the list of supported machines.
-         */
-        for_each_machine_desc(p)
-                if (nr == p->nr) {
-                        printk("Machine: %s\n", p->name);
-                        mdesc = p;
-                        break;
-                }
-
-        if (!mdesc) {
-                early_print("\nError: unrecognized/unsupported machine ID"
-                        " (r1 = 0x%08x).\n\n", nr);
-                dump_machine_table(); /* does not return */
-        }
-
-        if (__atags_pointer)
-                tags = phys_to_virt(__atags_pointer);
-        else if (mdesc->atag_offset)
-                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
-
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-        /*
-         * If we have the old style parameters, convert them to
-         * a tag list.
-         */
-        if (tags->hdr.tag != ATAG_CORE)
-                convert_to_tag_list(tags);
-#endif
-
-        if (tags->hdr.tag != ATAG_CORE) {
-#if defined(CONFIG_OF)
-                /*
-                 * If CONFIG_OF is set, then assume this is a reasonably
-                 * modern system that should pass boot parameters
-                 */
-                early_print("Warning: Neither atags nor dtb found\n");
-#endif
-                tags = (struct tag *)&init_tags;
-        }
-
-        if (mdesc->fixup)
-                mdesc->fixup(tags, &from, &meminfo);
-
-        if (tags->hdr.tag == ATAG_CORE) {
-                if (meminfo.nr_banks != 0)
-                        squash_mem_tags(tags);
-                save_atags(tags);
-                parse_tags(tags);
-        }
-
-        /* parse_early_param needs a boot_command_line */
-        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-
-        return mdesc;
-}
-
 static int __init meminfo_cmp(const void *_a, const void *_b)
 {
         const struct membank *a = _a, *b = _b;
@@ -944,7 +710,7 @@ void __init setup_arch(char **cmdline_p)
         setup_processor();
         mdesc = setup_machine_fdt(__atags_pointer);
         if (!mdesc)
-                mdesc = setup_machine_tags(machine_arch_type);
+                mdesc = setup_machine_tags(__atags_pointer, machine_arch_type);
         machine_desc = mdesc;
         machine_name = mdesc->name;
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index dea7a925c7e2..d100eacdb798 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -59,7 +59,8 @@ struct secondary_data secondary_data;
 volatile int __cpuinitdata pen_release = -1;
 
 enum ipi_msg_type {
-        IPI_TIMER = 2,
+        IPI_WAKEUP,
+        IPI_TIMER,
         IPI_RESCHEDULE,
         IPI_CALL_FUNC,
         IPI_CALL_FUNC_SINGLE,
@@ -414,7 +415,8 @@ void arch_send_call_function_single_ipi(int cpu)
 }
 
 static const char *ipi_types[NR_IPI] = {
-#define S(x,s)  [x - IPI_TIMER] = s
+#define S(x,s)  [x] = s
+        S(IPI_WAKEUP, "CPU wakeup interrupts"),
         S(IPI_TIMER, "Timer broadcast interrupts"),
         S(IPI_RESCHEDULE, "Rescheduling interrupts"),
         S(IPI_CALL_FUNC, "Function call interrupts"),
@@ -567,10 +569,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
         unsigned int cpu = smp_processor_id();
         struct pt_regs *old_regs = set_irq_regs(regs);
 
-        if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
-                __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
+        if (ipinr < NR_IPI)
+                __inc_irq_stat(cpu, ipi_irqs[ipinr]);
 
         switch (ipinr) {
+        case IPI_WAKEUP:
+                break;
+
         case IPI_TIMER:
                 irq_enter();
                 ipi_timer();
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 395d5fbb8fa2..9d0a30032d7f 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -34,7 +34,18 @@ struct arm_delay_ops arm_delay_ops = {
         .udelay         = __loop_udelay,
 };
 
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static const struct delay_timer *delay_timer;
+static bool delay_calibrated;
+
+int read_current_timer(unsigned long *timer_val)
+{
+        if (!delay_timer)
+                return -ENXIO;
+
+        *timer_val = delay_timer->read_current_timer();
+        return 0;
+}
+
 static void __timer_delay(unsigned long cycles)
 {
         cycles_t start = get_cycles();
@@ -55,18 +66,24 @@ static void __timer_udelay(unsigned long usecs)
         __timer_const_udelay(usecs * UDELAY_MULT);
 }
 
-void __init init_current_timer_delay(unsigned long freq)
+void __init register_current_timer_delay(const struct delay_timer *timer)
 {
-        pr_info("Switching to timer-based delay loop\n");
-        lpj_fine                        = freq / HZ;
-        loops_per_jiffy                 = lpj_fine;
-        arm_delay_ops.delay             = __timer_delay;
-        arm_delay_ops.const_udelay      = __timer_const_udelay;
-        arm_delay_ops.udelay            = __timer_udelay;
+        if (!delay_calibrated) {
+                pr_info("Switching to timer-based delay loop\n");
+                delay_timer                     = timer;
+                lpj_fine                        = timer->freq / HZ;
+                loops_per_jiffy                 = lpj_fine;
+                arm_delay_ops.delay             = __timer_delay;
+                arm_delay_ops.const_udelay      = __timer_const_udelay;
+                arm_delay_ops.udelay            = __timer_udelay;
+                delay_calibrated                = true;
+        } else {
+                pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
+        }
 }
 
 unsigned long __cpuinit calibrate_delay_is_known(void)
 {
+        delay_calibrated = true;
         return lpj_fine;
 }
-#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2c2d86505a54..5315f05896e9 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -153,7 +153,9 @@ static int at91_pm_verify_clocks(void)
                 }
         }
 
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+        if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS))
+                return 1;
+
         /* PCK0..PCK3 must be disabled, or configured to use clk32k */
         for (i = 0; i < 4; i++) {
                 u32 css;
@@ -167,7 +169,6 @@ static int at91_pm_verify_clocks(void)
                         return 0;
                 }
         }
-#endif
 
         return 1;
 }
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index e6f52de1062f..da9881b161e1 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -87,7 +87,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
         iotable_init(desc, 1);
 }
 
-static struct map_desc at91_io_desc __initdata = {
+static struct map_desc at91_io_desc __initdata __maybe_unused = {
         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
         .length         = SZ_16K,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 6676dee7104e..e517e1036b09 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -939,7 +939,7 @@ static struct platform_device da850_cpufreq_device = {
 
 unsigned int da850_max_speed = 300000;
 
-int __init da850_register_cpufreq(char *async_clk)
+int da850_register_cpufreq(char *async_clk)
 {
         int i;
 
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8d57e4223bdb..f93d820ecab5 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -134,7 +134,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
 
                 __raw_writel(virt_to_phys(exynos4_secondary_startup),
                         CPU1_BOOT_REG);
-                gic_raise_softirq(cpumask_of(cpu), 1);
+                gic_raise_softirq(cpumask_of(cpu), 0);
 
                 if (pen_release == -1)
                         break;
diff --git a/arch/arm/mach-footbridge/include/mach/irqs.h b/arch/arm/mach-footbridge/include/mach/irqs.h
index 400551e43e4e..61c714c4920e 100644
--- a/arch/arm/mach-footbridge/include/mach/irqs.h
+++ b/arch/arm/mach-footbridge/include/mach/irqs.h
@@ -89,8 +89,6 @@
 #define IRQ_NETWINDER_VGA       _ISA_IRQ(11)
 #define IRQ_NETWINDER_SOUND     _ISA_IRQ(12)
 
-#undef RTC_IRQ
-#define RTC_IRQ         IRQ_ISA_RTC_ALARM
 #define I8042_KBD_IRQ   IRQ_ISA_KEYBOARD
 #define I8042_AUX_IRQ   (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
 #define IRQ_FLOPPYDISK  IRQ_ISA_FLOPPY
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 899561d8db28..c3ff21b5ea24 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,6 @@
+#include <linux/amba/serial.h>
+extern struct amba_pl010_data integrator_uart_data;
 void integrator_init_early(void);
+int integrator_init(bool is_cp);
 void integrator_reserve(void);
 void integrator_restart(char, const char *);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index dad3cb74ed31..ea22a17246d7 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -32,7 +32,9 @@
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
 
-static struct amba_pl010_data integrator_uart_data;
+#include "common.h"
+
+#ifdef CONFIG_ATAGS
 
 #define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
 #define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
@@ -60,7 +62,7 @@ static struct amba_device *amba_devs[] __initdata = {
         &kmi1_device,
 };
 
-static int __init integrator_init(void)
+int __init integrator_init(bool is_cp)
 {
         int i;
 
@@ -69,7 +71,7 @@ static int __init integrator_init(void)
          * hard-code them. The Integator/CP and forward have proper cell IDs.
          * Else we leave them undefined to the bus driver can autoprobe them.
          */
-        if (machine_is_integrator()) {
+        if (!is_cp) {
                 rtc_device.periphid     = 0x00041030;
                 uart0_device.periphid   = 0x00041010;
                 uart1_device.periphid   = 0x00041010;
@@ -85,7 +87,7 @@ static int __init integrator_init(void)
         return 0;
 }
 
-arch_initcall(integrator_init);
+#endif
 
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
@@ -100,11 +102,14 @@ arch_initcall(integrator_init);
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
+        u32 phybase = dev->res.start;
 
-        if (dev == &uart0_device) {
+        if (phybase == INTEGRATOR_UART0_BASE) {
+                /* UART0 */
                 rts_mask = 1 << 4;
                 dtr_mask = 1 << 5;
         } else {
+                /* UART1 */
                 rts_mask = 1 << 6;
                 dtr_mask = 1 << 7;
         }
@@ -123,7 +128,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
         __raw_writel(ctrlc, SC_CTRLC);
 }
 
-static struct amba_pl010_data integrator_uart_data = {
+struct amba_pl010_data integrator_uart_data = {
         .set_mctrl = integrator_uart_set_mctrl,
 };
 
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h
index 1a78692e32a4..202e6a57f100 100644
--- a/arch/arm/mach-integrator/include/mach/cm.h
+++ b/arch/arm/mach-integrator/include/mach/cm.h
@@ -3,7 +3,7 @@
  */
 void cm_control(u32, u32);
 
-#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
+#define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL)
 
 #define CM_CTRL_LED                     (1 << 0)
 #define CM_CTRL_nMBDET                  (1 << 1)
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index 4c0347526851..efeac5d0bc9e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -324,9 +324,9 @@
  */
 #define PHYS_PCI_V3_BASE                0x62000000
 
-#define PCI_MEMORY_VADDR                0xe8000000
-#define PCI_CONFIG_VADDR                0xec000000
-#define PCI_V3_VADDR                    0xed000000
+#define PCI_MEMORY_VADDR                IOMEM(0xe8000000)
+#define PCI_CONFIG_VADDR                IOMEM(0xec000000)
+#define PCI_V3_VADDR                    IOMEM(0xed000000)
 
 /* ------------------------------------------------------------------------
  *  Integrator Interrupt Controllers
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2215d96cd735..e6617c134faf 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -34,6 +34,9 @@
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -154,27 +157,10 @@ static struct map_desc ap_io_desc[] __initdata = {
 static void __init ap_map_io(void)
 {
         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
-        vga_base = PCI_MEMORY_VADDR;
+        vga_base = (unsigned long)PCI_MEMORY_VADDR;
         pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 }
 
-#define INTEGRATOR_SC_VALID_INT 0x003fffff
-
-static void __init ap_init_irq(void)
-{
-        /* Disable all interrupts initially. */
-        /* Do the core module ones */
-        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-
-        /* do the header card stuff next */
-        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-
-        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-                -1, INTEGRATOR_SC_VALID_INT, NULL);
-        integrator_clk_init(false);
-}
-
 #ifdef CONFIG_PM
 static unsigned long ic_irq_enable;
 
@@ -267,50 +253,6 @@ static struct physmap_flash_data ap_flash_data = {
         .set_vpp        = ap_flash_set_vpp,
 };
 
-static struct resource cfi_flash_resource = {
-        .start          = INTEGRATOR_FLASH_BASE,
-        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device cfi_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &ap_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &cfi_flash_resource,
-};
-
-static void __init ap_init(void)
-{
-        unsigned long sc_dec;
-        int i;
-
-        platform_device_register(&cfi_flash_device);
-
-        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
-        for (i = 0; i < 4; i++) {
-                struct lm_device *lmdev;
-
-                if ((sc_dec & (16 << i)) == 0)
-                        continue;
-
-                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
-                if (!lmdev)
-                        continue;
-
-                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-                lmdev->resource.flags = IORESOURCE_MEM;
-                lmdev->irq = IRQ_AP_EXPINT0 + i;
-                lmdev->id = i;
-
-                lm_device_register(lmdev);
-        }
-}
-
 /*
  * Where is the timer (VA)?
  */
@@ -325,9 +267,9 @@ static u32 notrace integrator_read_sched_clock(void)
         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 }
 
-static void integrator_clocksource_init(unsigned long inrate)
+static void integrator_clocksource_init(unsigned long inrate,
+                                        void __iomem *base)
 {
-        void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
         unsigned long rate = inrate;
 
@@ -344,7 +286,7 @@ static void integrator_clocksource_init(unsigned long inrate)
         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 }
 
-static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
+static void __iomem * clkevt_base;
 
 /*
  * IRQ handler for the timer
@@ -416,11 +358,13 @@ static struct irqaction integrator_timer_irq = {
         .dev_id         = &integrator_clockevent,
 };
 
-static void integrator_clockevent_init(unsigned long inrate)
+static void integrator_clockevent_init(unsigned long inrate,
+                                void __iomem *base, int irq)
 {
         unsigned long rate = inrate;
         unsigned int ctrl = 0;
 
+        clkevt_base = base;
         /* Calculate and program a divisor */
         if (rate > 0x100000 * HZ) {
                 rate /= 256;
@@ -432,7 +376,7 @@ static void integrator_clockevent_init(unsigned long inrate)
         timer_reload = rate / HZ;
         writel(ctrl, clkevt_base + TIMER_CTRL);
 
-        setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
+        setup_irq(irq, &integrator_timer_irq);
         clockevents_config_and_register(&integrator_clockevent,
                                         rate,
                                         1,
@@ -443,9 +387,153 @@ void __init ap_init_early(void)
 {
 }
 
+#ifdef CONFIG_OF
+
+static void __init ap_init_timer_of(void)
+{
+        struct device_node *node;
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+        struct clk *clk;
+        unsigned long rate;
+
+        clk = clk_get_sys("ap_timer", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        writel(0, base + TIMER_CTRL);
+        integrator_clocksource_init(rate, base);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(node, 0);
+        writel(0, base + TIMER_CTRL);
+        integrator_clockevent_init(rate, base, irq);
+}
+
+static struct sys_timer ap_of_timer = {
+        .init           = ap_init_timer_of,
+};
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+        { /* Sentinel */ }
+};
+
+static void __init ap_init_irq_of(void)
+{
+        /* disable core module IRQs */
+        writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+        of_irq_init(fpga_irq_of_match);
+        integrator_clk_init(false);
+}
+
+/* For the Device Tree, add in the UART callbacks as AUXDATA */
+static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+                "rtc", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+                "uart0", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+                "uart1", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+                "kmi0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+                "kmi1", NULL),
+        OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
+                "physmap-flash", &ap_flash_data),
+        { /* sentinel */ },
+};
+
+static void __init ap_init_of(void)
+{
+        unsigned long sc_dec;
+        int i;
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        ap_auxdata_lookup, NULL);
+
+        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        for (i = 0; i < 4; i++) {
+                struct lm_device *lmdev;
+
+                if ((sc_dec & (16 << i)) == 0)
+                        continue;
+
+                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+                if (!lmdev)
+                        continue;
+
+                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+                lmdev->resource.flags = IORESOURCE_MEM;
+                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->id = i;
+
+                lm_device_register(lmdev);
+        }
+}
+
+static const char * ap_dt_board_compat[] = {
+        "arm,integrator-ap",
+        NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
+        .reserve        = integrator_reserve,
+        .map_io         = ap_map_io,
+        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
+        .init_early     = ap_init_early,
+        .init_irq       = ap_init_irq_of,
+        .handle_irq     = fpga_handle_irq,
+        .timer          = &ap_of_timer,
+        .init_machine   = ap_init_of,
+        .restart        = integrator_restart,
+        .dt_compat      = ap_dt_board_compat,
+MACHINE_END
+
+#endif
+
+#ifdef CONFIG_ATAGS
+
 /*
- * Set up timer(s).
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
  */
+
+static struct resource cfi_flash_resource = {
+        .start          = INTEGRATOR_FLASH_BASE,
+        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device cfi_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &ap_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &cfi_flash_resource,
+};
+
 static void __init ap_init_timer(void)
 {
         struct clk *clk;
@@ -460,14 +548,62 @@ static void __init ap_init_timer(void)
         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 
-        integrator_clocksource_init(rate);
-        integrator_clockevent_init(rate);
+        integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
+        integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
+                                IRQ_TIMERINT1);
 }
 
 static struct sys_timer ap_timer = {
         .init           = ap_init_timer,
 };
 
+#define INTEGRATOR_SC_VALID_INT 0x003fffff
+
+static void __init ap_init_irq(void)
+{
+        /* Disable all interrupts initially. */
+        /* Do the core module ones */
+        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+
+        /* do the header card stuff next */
+        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+
+        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+                -1, INTEGRATOR_SC_VALID_INT, NULL);
+        integrator_clk_init(false);
+}
+
+static void __init ap_init(void)
+{
+        unsigned long sc_dec;
+        int i;
+
+        platform_device_register(&cfi_flash_device);
+
+        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        for (i = 0; i < 4; i++) {
+                struct lm_device *lmdev;
+
+                if ((sc_dec & (16 << i)) == 0)
+                        continue;
+
+                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+                if (!lmdev)
+                        continue;
+
+                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+                lmdev->resource.flags = IORESOURCE_MEM;
+                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->id = i;
+
+                lm_device_register(lmdev);
+        }
+
+        integrator_init(false);
+}
+
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
@@ -481,3 +617,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
         .init_machine   = ap_init,
         .restart        = integrator_restart,
 MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 3df5fc369361..5b08e8e4cc83 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -23,6 +23,9 @@
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -49,16 +52,9 @@
 #include "common.h"
 
 #define INTCP_PA_FLASH_BASE             0x24000000
-#define INTCP_FLASH_SIZE                SZ_32M
 
 #define INTCP_PA_CLCD_BASE              0xc0000000
 
-#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
-#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
-
-#define INTCP_ETH_SIZE                  0x10
-
 #define INTCP_VA_CTRL_BASE              __io_address(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
@@ -143,37 +139,6 @@ static void __init intcp_map_io(void)
         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
 
-static void __init intcp_init_irq(void)
-{
-        u32 pic_mask, cic_mask, sic_mask;
-
-        /* These masks are for the HW IRQ registers */
-        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
-        pic_mask |= (~((~0u) << (29 - 22))) << 22;
-        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-
-        /*
-         * Disable all interrupt sources
-         */
-        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-
-        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-                      -1, pic_mask, NULL);
-
-        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-                      -1, cic_mask, NULL);
-
-        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-                      IRQ_CP_CPPLDINT, sic_mask, NULL);
-        integrator_clk_init(true);
-}
-
 /*
  * Flash handling.
  */
@@ -216,47 +181,6 @@ static struct physmap_flash_data intcp_flash_data = {
         .set_vpp        = intcp_flash_set_vpp,
 };
 
-static struct resource intcp_flash_resource = {
-        .start          = INTCP_PA_FLASH_BASE,
-        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device intcp_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &intcp_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &intcp_flash_resource,
-};
-
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = INTEGRATOR_CP_ETH_BASE,
-                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CP_ETHINT,
-                .end    = IRQ_CP_ETHINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
-
-static struct platform_device *intcp_devs[] __initdata = {
-        &intcp_flash_device,
-        &smc91x_device,
-};
-
 /*
  * It seems that the card insertion interrupt remains active after
  * we've acknowledged it.  We therefore ignore the interrupt, and
@@ -278,16 +202,6 @@ static struct mmci_platform_data mmc_data = {
         .gpio_cd        = -1,
 };
 
-#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
-#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
-
-static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
-        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
-
-static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
-        INTEGRATOR_CP_AACI_IRQS, NULL);
-
-
 /*
  * CLCD support
  */
@@ -338,15 +252,6 @@ static struct clcd_board clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
-        { IRQ_CP_CLCDCINT }, &clcd_data);
-
-static struct amba_device *amba_devs[] __initdata = {
-        &mmc_device,
-        &aaci_device,
-        &clcd_device,
-};
-
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 
 static void __init intcp_init_early(void)
@@ -356,16 +261,193 @@ static void __init intcp_init_early(void)
 #endif
 }
 
-static void __init intcp_init(void)
+#ifdef CONFIG_OF
+
+static void __init intcp_timer_init_of(void)
 {
-        int i;
+        struct device_node *node;
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        writel(0, base + TIMER_CTRL);
+        sp804_clocksource_init(base, node->name);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(node, 0);
+        writel(0, base + TIMER_CTRL);
+        sp804_clockevents_init(base, irq, node->name);
+}
 
-        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+static struct sys_timer cp_of_timer = {
+        .init           = intcp_timer_init_of,
+};
 
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+        { /* Sentinel */ }
+};
+
+static void __init intcp_init_irq_of(void)
+{
+        of_irq_init(fpga_irq_of_match);
+        integrator_clk_init(true);
+}
+
+/*
+ * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
+ * and enforce the bus names since these are used for clock lookups.
+ */
+static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+                "rtc", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+                "uart0", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+                "uart1", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+                "kmi0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+                "kmi1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
+                "mmci", &mmc_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
+                "aaci", &mmc_data),
+        OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
+                "clcd", &clcd_data),
+        OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
+                "physmap-flash", &intcp_flash_data),
+        { /* sentinel */ },
+};
+
+static void __init intcp_init_of(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        intcp_auxdata_lookup, NULL);
+}
+
+static const char * intcp_dt_board_compat[] = {
+        "arm,integrator-cp",
+        NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
+        .reserve        = integrator_reserve,
+        .map_io         = intcp_map_io,
+        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
+        .init_early     = intcp_init_early,
+        .init_irq       = intcp_init_irq_of,
+        .handle_irq     = fpga_handle_irq,
+        .timer          = &cp_of_timer,
+        .init_machine   = intcp_init_of,
+        .restart        = integrator_restart,
+        .dt_compat      = intcp_dt_board_compat,
+MACHINE_END
+
+#endif
+
+#ifdef CONFIG_ATAGS
+
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+
+#define INTCP_FLASH_SIZE                SZ_32M
+
+static struct resource intcp_flash_resource = {
+        .start          = INTCP_PA_FLASH_BASE,
+        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device intcp_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &intcp_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &intcp_flash_resource,
+};
+
+#define INTCP_ETH_SIZE                  0x10
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start  = INTEGRATOR_CP_ETH_BASE,
+                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CP_ETHINT,
+                .end    = IRQ_CP_ETHINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+static struct platform_device *intcp_devs[] __initdata = {
+        &intcp_flash_device,
+        &smc91x_device,
+};
+
+#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
+
+static void __init intcp_init_irq(void)
+{
+        u32 pic_mask, cic_mask, sic_mask;
+
+        /* These masks are for the HW IRQ registers */
+        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+        pic_mask |= (~((~0u) << (29 - 22))) << 22;
+        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
+        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
+
+        /*
+         * Disable all interrupt sources
+         */
+        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
+        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
+
+        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+                      -1, pic_mask, NULL);
+
+        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+                      -1, cic_mask, NULL);
+
+        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+                      IRQ_CP_CPPLDINT, sic_mask, NULL);
+
+        integrator_clk_init(true);
 }
 
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -386,6 +468,37 @@ static struct sys_timer cp_timer = {
         .init           = intcp_timer_init,
 };
 
+#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
+
+static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
+        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+
+static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
+        INTEGRATOR_CP_AACI_IRQS, NULL);
+
+static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
+        { IRQ_CP_CLCDCINT }, &clcd_data);
+
+static struct amba_device *amba_devs[] __initdata = {
+        &mmc_device,
+        &aaci_device,
+        &clcd_device,
+};
+
+static void __init intcp_init(void)
+{
+        int i;
+
+        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+        integrator_init(true);
+}
+
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
@@ -399,3 +512,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         .init_machine   = intcp_init,
         .restart        = integrator_restart,
 MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 060cddde2fd4..e94744111634 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -30,7 +30,7 @@
 extern int init_atu;
 
 static int __init
-iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
 {
         WARN_ON(idsel < 1 || idsel > 2);
 
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 9082b84aeebb..2f28018c4447 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -504,7 +504,7 @@ iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 
 /* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
  */
-struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __devinit iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
 {
         int which_atu;
         struct pci_bus *bus = NULL;
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index f7e1b9bce345..95e731a7ed6a 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -34,7 +34,8 @@ extern struct bus_type platform_bus_type;
 #define __arch_dma_to_virt(dev, x)      ({ (void *) (is_lbus_device(dev) ? \
                                         __phys_to_virt(x) : __bus_to_virt(x)); })
 #define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
-                                        (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
+                                        (dma_addr_t)__virt_to_phys((unsigned long)x) \
+                                        : (dma_addr_t)__virt_to_bus(x); })
 #define __arch_pfn_to_dma(dev, pfn)     \
         ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
            if (!is_lbus_device(dev)) \
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 343c435b4176..26e9876b50e9 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -54,7 +54,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
 /*
  * Description of the windows needed by the platform code
  */
-static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+static struct orion_addr_map_cfg addr_map_cfg __initdata = {
         .num_wins = 14,
         .remappable_wins = 8,
         .win_cfg_base = win_cfg_base,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 131cd4883f3d..d0cb4857b4b3 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -336,7 +336,7 @@ void __init mv78xx0_init_early(void)
         orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static void mv78xx0_timer_init(void)
+static void __init_refok mv78xx0_timer_init(void)
 {
         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
                         IRQ_MV78XX0_TIMER_1, get_tclk());
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index fc3afc7cd366..a103c8ffea9f 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -22,6 +22,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/pxa25x.h>
+#undef GPIO24_SSP1_SFRM
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <linux/platform_data/video-pxafb.h>
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 997e6da9a9c4..32e0d7998355 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -105,6 +105,7 @@ static struct pxamci_platform_data palmte2_mci_platform_data = {
         .gpio_power             = GPIO_NR_PALMTE2_SD_POWER,
 };
 
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 /******************************************************************************
  * GPIO keys
  ******************************************************************************/
@@ -132,6 +133,7 @@ static struct platform_device palmte2_pxa_keys = {
                 .platform_data = &palmte2_pxa_keys_data,
         },
 };
+#endif
 
 /******************************************************************************
  * Backlight
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 5a406f794798..ec55c575ed19 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -55,7 +55,6 @@
 #ifdef CONFIG_PM
 static int sharpsl_off_charge_battery(void);
 static int sharpsl_check_battery_voltage(void);
-static int sharpsl_fatal_check(void);
 #endif
 static int sharpsl_check_battery_temp(void);
 static int sharpsl_ac_check(void);
@@ -686,53 +685,6 @@ static int corgi_pxa_pm_enter(suspend_state_t state)
         return 0;
 }
 
-/*
- * Check for fatal battery errors
- * Fatal returns -1
- */
-static int sharpsl_fatal_check(void)
-{
-        int buff[5], temp, i, acin;
-
-        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check entered\n");
-
-        /* Check AC-Adapter */
-        acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-
-        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
-                sharpsl_pm.machinfo->charge(0);
-                udelay(100);
-                sharpsl_pm.machinfo->discharge(1);      /* enable discharge */
-                mdelay(SHARPSL_WAIT_DISCHARGE_ON);
-        }
-
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(1);
-
-        /* Check battery : check inserting battery ? */
-        for (i = 0; i < 5; i++) {
-                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
-        }
-
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(0);
-
-        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
-                udelay(100);
-                sharpsl_pm.machinfo->charge(1);
-                sharpsl_pm.machinfo->discharge(0);
-        }
-
-        temp = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT));
-
-        if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) ||
-                        (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt)))
-                return -1;
-        return 0;
-}
-
 static int sharpsl_off_charge_error(void)
 {
         dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 392412ce4dac..c773e4dded64 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -768,8 +768,7 @@ static unsigned long viper_tpm;
 
 static int __init viper_tpm_setup(char *str)
 {
-        strict_strtoul(str, 10, &viper_tpm);
-        return 1;
+        return strict_strtoul(str, 10, &viper_tpm) >= 0;
 }
 
 __setup("tpm=", viper_tpm_setup);
diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
index b91bc87b3dcf..fcb1d59f7aec 100644
--- a/arch/arm/mach-rpc/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -960,7 +960,9 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
         *ecp = ec;
         slot_to_expcard[slot] = ec;
 
-        device_register(&ec->dev);
+        rc = device_register(&ec->dev);
+        if (rc)
+                goto nodev;
 
         return 0;
 
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index 23ec97370f32..ff141b0af26b 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
@@ -232,7 +232,7 @@ struct irq_chip s3c2416_irq_second = {
 
 /* IRQ initialisation code */
 
-static int __init s3c2416_add_sub(unsigned int base,
+static int s3c2416_add_sub(unsigned int base,
                                    void (*demux)(unsigned int,
                                                  struct irq_desc *),
                                    struct irq_chip *chip,
@@ -251,7 +251,7 @@ static int __init s3c2416_add_sub(unsigned int base,
         return 0;
 }
 
-static void __init s3c2416_irq_add_second(void)
+static void s3c2416_irq_add_second(void)
 {
         unsigned long pend;
         unsigned long last;
@@ -287,7 +287,7 @@ static void __init s3c2416_irq_add_second(void)
         }
 }
 
-static int __init s3c2416_irq_add(struct device *dev,
+static int s3c2416_irq_add(struct device *dev,
                                   struct subsys_interface *sif)
 {
         printk(KERN_INFO "S3C2416: IRQ Support\n");
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
index ac2829f56d12..5e69109c0928 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
@@ -222,7 +222,7 @@ static struct irq_chip s3c2443_irq_cam = {
 
 /* IRQ initialisation code */
 
-static int __init s3c2443_add_sub(unsigned int base,
+static int s3c2443_add_sub(unsigned int base,
                                    void (*demux)(unsigned int,
                                                  struct irq_desc *),
                                    struct irq_chip *chip,
@@ -241,7 +241,7 @@ static int __init s3c2443_add_sub(unsigned int base,
         return 0;
 }
 
-static int __init s3c2443_irq_add(struct device *dev,
+static int s3c2443_irq_add(struct device *dev,
                                   struct subsys_interface *sif)
 {
         printk("S3C2443: IRQ Support\n");
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index 17f8356177c1..ddf7a3c743ac 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -104,7 +104,7 @@ static struct s3c2410_hcd_info usb_simtec_info __initdata = {
 };
 
 
-int usb_simtec_init(void)
+int __init usb_simtec_init(void)
 {
         int ret;
 
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index e1ccda6128eb..6a7ad3c2a3fc 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -388,7 +388,7 @@ static void __init map_sa1100_gpio_regs( void )
  */
 static void __init get_assabet_scr(void)
 {
-        unsigned long scr, i;
+        unsigned long uninitialized_var(scr), i;
 
         GPDR |= 0x3fc;                  /* Configure GPIO 9:2 as outputs */
         GPSR = 0x3fc;                   /* Write 0xFF to GPIO 9:2 */
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h
deleted file mode 100644
index c38f60915cb6..000000000000
--- a/arch/arm/mach-sa1100/include/mach/SA-1111.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * Moved to new location
- */
-#warning using old SA-1111.h - update to <asm/hardware/sa1111.h>
-#include <asm/hardware/sa1111.h>
diff --git a/arch/arm/mach-sa1100/include/mach/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h
deleted file mode 100644
index 8a5482d908db..000000000000
--- a/arch/arm/mach-sa1100/include/mach/lart.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _INCLUDE_LART_H
-#define _INCLUDE_LART_H
-
-#define LART_GPIO_ETH0                  GPIO_GPIO0
-#define LART_IRQ_ETH0                   IRQ_GPIO0
-
-#define LART_GPIO_IDE                   GPIO_GPIO1
-#define LART_IRQ_IDE                    IRQ_GPIO1
-
-#define LART_GPIO_UCB1200               GPIO_GPIO18
-#define LART_IRQ_UCB1200                IRQ_GPIO18
-
-#endif
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index b8b4ab323a3e..6d91a914c1dd 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -41,7 +41,7 @@ static struct hw_pci shark_pci __initdata = {
 static int __init shark_pci_init(void)
 {
         if (!machine_is_shark())
-                return;
+                return -ENODEV;
 
         pcibios_min_io = 0x6000;
         pcibios_min_mem = 0x50000000;
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index ed77ab8c9143..d47e215aca87 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -100,7 +100,7 @@ static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
 
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
-static inline void shmobile_init_late(void)
+static inline void __init shmobile_init_late(void)
 {
         shmobile_suspend_init();
         shmobile_cpuidle_init();
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f978c5d0e1ae..f67456286280 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
         /* Tell ROM loader about our vector (in headsmp.S) */
         emev2_set_boot_vector(__pa(shmobile_secondary_vector));
 
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
         return 0;
 }
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 5f3c03b61f8e..11680c532b38 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -16,7 +16,7 @@ config ARCH_TEGRA_2x_SOC
         select ARM_ERRATA_742230
         select ARM_ERRATA_751472
         select ARM_ERRATA_754327
-        select ARM_ERRATA_764369
+        select ARM_ERRATA_764369 if SMP
         select PL310_ERRATA_727915 if CACHE_L2X0
         select PL310_ERRATA_769419 if CACHE_L2X0
         select CPU_FREQ_TABLE if CPU_FREQ
@@ -37,7 +37,7 @@ config ARCH_TEGRA_3x_SOC
         select ARM_ERRATA_743622
         select ARM_ERRATA_751472
         select ARM_ERRATA_754322
-        select ARM_ERRATA_764369
+        select ARM_ERRATA_764369 if SMP
         select PL310_ERRATA_769419 if CACHE_L2X0
         select CPU_FREQ_TABLE if CPU_FREQ
         help
@@ -57,8 +57,6 @@ config TEGRA_AHB
           which controls AHB bus master arbitration and some
           perfomance parameters(priority, prefech size).
 
-comment "Tegra board type"
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c77c86c47369..5848206ee9b9 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -5,9 +5,9 @@ config UX500_SOC_COMMON
         default y
         select ARM_GIC
         select HAS_MTU
-        select PL310_ERRATA_753970
+        select PL310_ERRATA_753970 if CACHE_PL310
         select ARM_ERRATA_754322
-        select ARM_ERRATA_764369
+        select ARM_ERRATA_764369 if SMP
         select CACHE_L2X0
         select PINCTRL
         select PINCTRL_NOMADIK
diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h
index bb9e2d23fee3..e6e81fdaf109 100644
--- a/arch/arm/mach-vt8500/include/mach/uncompress.h
+++ b/arch/arm/mach-vt8500/include/mach/uncompress.h
@@ -15,15 +15,15 @@
  *
  */
 
-#define UART0_PHYS 0xd8200000
-#include <asm/io.h>
+#define UART0_PHYS      0xd8200000
+#define UART0_ADDR(x)   *(volatile unsigned char *)(UART0_PHYS + x)
 
 static void putc(const char c)
 {
-        while (readb(UART0_PHYS + 0x1c) & 0x2)
+        while (UART0_ADDR(0x1c) & 0x2)
                 /* Tx busy, wait and poll */;
 
-        writeb(c, UART0_PHYS);
+        UART0_ADDR(0) = c;
 }
 
 static void flush(void)
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 587ea950d08b..8d3871f110a5 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -77,8 +77,11 @@ static void vt8500_power_off(void)
 
 void __init vt8500_init(void)
 {
-        struct device_node *np, *fb;
+        struct device_node *np;
+#if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505)
+        struct device_node *fb;
         void __iomem *gpio_base;
+#endif
 
 #ifdef CONFIG_FB_VT8500
         fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231aacc5..b9f60ebe3bc4 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -699,7 +699,6 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
         unsigned long instr = *pinstr;
         u16 tinst1 = (instr >> 16) & 0xffff;
         u16 tinst2 = instr & 0xffff;
-        poffset->un = 0;
 
         switch (tinst1 & 0xffe0) {
         /* A6.3.5 Load/Store multiple */
@@ -854,9 +853,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 break;
 
         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
-                if (thumb2_32b)
+                if (thumb2_32b) {
+                        offset.un = 0;
                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
-                else
+                } else
                         handler = do_alignment_ldmstm;
                 break;
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 577baf7d0a8d..8a97e6443c62 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -368,14 +368,18 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                 /* l2x0 controller is disabled */
                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
 
-                l2x0_saved_regs.aux_ctrl = aux;
-
                 l2x0_inv_all();
 
                 /* enable L2X0 */
                 writel_relaxed(1, l2x0_base + L2X0_CTRL);
         }
 
+        /* Re-read it in case some bits are reserved. */
+        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+
+        /* Save the value for resuming. */
+        l2x0_saved_regs.aux_ctrl = aux;
+
         outer_cache.inv_range = l2x0_inv_range;
         outer_cache.clean_range = l2x0_clean_range;
         outer_cache.flush_range = l2x0_flush_range;
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 39e3fb3db801..3b172275262e 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
  * isn't mapped, fail with -EFAULT.
  */
 9001:
+#ifdef CONFIG_ARM_ERRATA_775420
+        dsb
+#endif
         mov     r0, #-EFAULT
         mov     pc, lr
  UNWIND(.fnend          )
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9aec41fa80ae..ad722f1208a5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
 
         BUG_ON(!arm_memblock_steal_permitted);
 
-        phys = memblock_alloc(size, align);
+        phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
         memblock_free(phys, size);
         memblock_remove(phys, size);
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 9d869f93a3da..5dcc2fd46c46 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -248,6 +248,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         if (!area)
                 return NULL;
         addr = (unsigned long)area->addr;
+        area->phys_addr = __pfn_to_phys(pfn);
 
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
         if (DOMAIN_IO == 0 &&
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 6e70d03824a1..091ae1030045 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -5,6 +5,8 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -14,11 +16,17 @@
 #define IRQ_RAW_STATUS          0x04
 #define IRQ_ENABLE_SET          0x08
 #define IRQ_ENABLE_CLEAR        0x0c
+#define INT_SOFT_SET            0x10
+#define INT_SOFT_CLEAR          0x14
+#define FIQ_STATUS              0x20
+#define FIQ_RAW_STATUS          0x24
+#define FIQ_ENABLE              0x28
+#define FIQ_ENABLE_SET          0x28
+#define FIQ_ENABLE_CLEAR        0x2C
 
 /**
  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
  * @base: memory offset in virtual memory
- * @irq_start: first IRQ number handled by this instance
  * @chip: chip container for this instance
  * @domain: IRQ domain for this instance
  * @valid: mask for valid IRQs on this controller
@@ -26,7 +34,6 @@
  */
 struct fpga_irq_data {
         void __iomem *base;
-        unsigned int irq_start;
         struct irq_chip chip;
         u32 valid;
         struct irq_domain *domain;
@@ -125,34 +132,79 @@ static struct irq_domain_ops fpga_irqdomain_ops = {
         .xlate = irq_domain_xlate_onetwocell,
 };
 
-void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
-                          int parent_irq, u32 valid, struct device_node *node)
-{
+static __init struct fpga_irq_data *
+fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
         struct fpga_irq_data *f;
 
         if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
                 printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
-                return;
+                return NULL;
         }
-
         f = &fpga_irq_devices[fpga_irq_id];
         f->base = base;
-        f->irq_start = irq_start;
         f->chip.name = name;
         f->chip.irq_ack = fpga_irq_mask;
         f->chip.irq_mask = fpga_irq_mask;
         f->chip.irq_unmask = fpga_irq_unmask;
         f->valid = valid;
+        fpga_irq_id++;
+
+        return f;
+}
+
+void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+                          int parent_irq, u32 valid, struct device_node *node)
+{
+        struct fpga_irq_data *f;
+
+        f = fpga_irq_prep_struct(base, name, valid);
+        if (!f)
+                return;
 
         if (parent_irq != -1) {
                 irq_set_handler_data(parent_irq, f);
                 irq_set_chained_handler(parent_irq, fpga_irq_handle);
         }
 
-        f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
+        f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0,
                                           &fpga_irqdomain_ops, f);
         pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
                 fpga_irq_id, name, base, f->used_irqs);
+}
 
-        fpga_irq_id++;
+#ifdef CONFIG_OF
+int __init fpga_irq_of_init(struct device_node *node,
+                            struct device_node *parent)
+{
+        struct fpga_irq_data *f;
+        void __iomem *base;
+        u32 clear_mask;
+        u32 valid_mask;
+
+        if (WARN_ON(!node))
+                return -ENODEV;
+
+        base = of_iomap(node, 0);
+        WARN(!base, "unable to map fpga irq registers\n");
+
+        if (of_property_read_u32(node, "clear-mask", &clear_mask))
+                clear_mask = 0;
+
+        if (of_property_read_u32(node, "valid-mask", &valid_mask))
+                valid_mask = 0;
+
+        f = fpga_irq_prep_struct(base, node->name, valid_mask);
+        if (!f)
+                return -ENOMEM;
+
+        writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+        writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+
+        f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f);
+        f->used_irqs = hweight32(valid_mask);
+
+        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
+                fpga_irq_id, node->name, base, f->used_irqs);
+        return 0;
 }
+#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
index 91bcfb67551d..1fac9651d3ca 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h
@@ -7,5 +7,7 @@ struct pt_regs;
 void fpga_handle_irq(struct pt_regs *regs);
 void fpga_irq_init(void __iomem *, const char *, int, int, u32,
                 struct device_node *node);
+int fpga_irq_of_init(struct device_node *node,
+                     struct device_node *parent);
 
 #endif
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 7cafb537d03c..d2b3935ae147 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
 {
 #ifdef CACHE_INVALIDATE
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATE) : "d0" );
+                : : "r" (CACHE_INVALIDATE) );
 #endif
 }
 
@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
 {
 #ifdef CACHE_INVALIDATEI
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATEI) : "d0" );
+                : : "r" (CACHE_INVALIDATEI) );
 #endif
 }
 
@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
 #endif
 #ifdef CACHE_INVALIDATED
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATED) : "d0" );
+                : : "r" (CACHE_INVALIDATED) );
 #else
-        /* Flush the wrtite buffer */
+        /* Flush the write buffer */
         __asm__ __volatile__ ( "nop" );
 #endif
 }
 
 /*
  * Push cache entries at supplied address. We want to write back any dirty
- * data and the invalidate the cache lines associated with this address.
+ * data and then invalidate the cache lines associated with this address.
  */
 static inline void cache_push(unsigned long paddr, int len)
 {
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 69722366b084..4cf864f5ea7a 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -21,33 +21,33 @@
 /*
  *      Define the 5206 SIM register set addresses.
  */
-#define MCFSIM_SIMR             0x03            /* SIM Config reg (r/w) */
-#define MCFSIM_ICR1             0x14            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x15            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x16            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x17            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x18            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x19            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x1a            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x1b            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x1c            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x1d            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x1e            /* Intr Ctrl reg 11 (r/w) */
-#define MCFSIM_ICR12            0x1f            /* Intr Ctrl reg 12 (r/w) */
-#define MCFSIM_ICR13            0x20            /* Intr Ctrl reg 13 (r/w) */
+#define MCFSIM_SIMR             (MCF_MBAR + 0x03)       /* SIM Config reg */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x14)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x15)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x16)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x17)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x18)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x19)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x1a)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x1b)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x1c)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x1d)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x1e)       /* Intr Ctrl reg 11 */
+#define MCFSIM_ICR12            (MCF_MBAR + 0x1f)       /* Intr Ctrl reg 12 */
+#define MCFSIM_ICR13            (MCF_MBAR + 0x20)       /* Intr Ctrl reg 13 */
 #ifdef CONFIG_M5206e
-#define MCFSIM_ICR14            0x21            /* Intr Ctrl reg 14 (r/w) */
-#define MCFSIM_ICR15            0x22            /* Intr Ctrl reg 15 (r/w) */
+#define MCFSIM_ICR14            (MCF_MBAR + 0x21)       /* Intr Ctrl reg 14 */
+#define MCFSIM_ICR15            (MCF_MBAR + 0x22)       /* Intr Ctrl reg 15 */
 #endif
 
-#define MCFSIM_IMR              0x36            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_IPR              0x3a            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              (MCF_MBAR + 0x36)       /* Interrupt Mask */
+#define MCFSIM_IPR              (MCF_MBAR + 0x3a)       /* Interrupt Pending */
 
-#define MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/
+#define MCFSIM_RSR              (MCF_MBAR + 0x40)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x41)       /* System Protection */
 
-#define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x42)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x43)       /* SW Watchdog srv */
 
 #define MCFSIM_DCRR             (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
 #define MCFSIM_DCTR             (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
@@ -58,36 +58,36 @@
 #define MCFSIM_DMR1             (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
 #define MCFSIM_DCR1             (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
 
-#define MCFSIM_CSAR0            0x64            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x68            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x6e            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x70            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x74            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x7a            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x7c            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x80            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0x86            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0x88            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0x8c            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0x92            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0x94            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0x98            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0x9e            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xa0            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xa4            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xaa            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xac            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xb0            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xb6            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xb8            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xbc            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xc2            /* CS 7 Control reg (r/w) */
-#define MCFSIM_DMCR             0xc6            /* Default control */
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x64)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x68)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x6e)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x70)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x74)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x7a)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x7c)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x80)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0x86)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0x88)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0x8c)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0x92)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0x94)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0x98)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0x9e)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xa0)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xa4)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xaa)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xac)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xb0)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xb6)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xb8)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xbc)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xc2)       /* CS 7 Control reg */
+#define MCFSIM_DMCR             (MCF_MBAR + 0xc6)       /* Default control */
 
 #ifdef CONFIG_M5206e
-#define MCFSIM_PAR              0xca            /* Pin Assignment reg (r/w) */
+#define MCFSIM_PAR              (MCF_MBAR + 0xca)       /* Pin Assignment */
 #else
-#define MCFSIM_PAR              0xcb            /* Pin Assignment reg (r/w) */
+#define MCFSIM_PAR              (MCF_MBAR + 0xcb)       /* Pin Assignment */
 #endif
 
 #define MCFTIMER_BASE1          (MCF_MBAR + 0x100)      /* Base of TIMER1 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 91d3abc3f2a5..5e06b4eb57f3 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -176,21 +176,29 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR            MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX                 107
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         107
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
 /*
  * Pin Assignment
 */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
+#define MCFGPIO_PAR_ETPU        (MCF_IPSBAR + 0x10004E)
 
 /*
  * DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 7f0c2c3660fd..fdf45e6807c9 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -25,41 +25,41 @@
 /*
  *      Define the 5249 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
@@ -134,23 +134,23 @@
 #define MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
 #define MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
 
-#define MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
-#define MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
-#define MCFSIM2_GPIOINTENABLE   0xc4            /* GPIO interrupt enable */
+#define MCFSIM2_GPIOINTSTAT     (MCF_MBAR2 + 0xc0)      /* GPIO intr status */
+#define MCFSIM2_GPIOINTCLEAR    (MCF_MBAR2 + 0xc0)      /* GPIO intr clear */
+#define MCFSIM2_GPIOINTENABLE   (MCF_MBAR2 + 0xc4)      /* GPIO intr enable */
 
-#define MCFSIM2_INTLEVEL1       0x140           /* Interrupt level reg 1 */
-#define MCFSIM2_INTLEVEL2       0x144           /* Interrupt level reg 2 */
-#define MCFSIM2_INTLEVEL3       0x148           /* Interrupt level reg 3 */
-#define MCFSIM2_INTLEVEL4       0x14c           /* Interrupt level reg 4 */
-#define MCFSIM2_INTLEVEL5       0x150           /* Interrupt level reg 5 */
-#define MCFSIM2_INTLEVEL6       0x154           /* Interrupt level reg 6 */
-#define MCFSIM2_INTLEVEL7       0x158           /* Interrupt level reg 7 */
-#define MCFSIM2_INTLEVEL8       0x15c           /* Interrupt level reg 8 */
+#define MCFSIM2_INTLEVEL1       (MCF_MBAR2 + 0x140)     /* Intr level reg 1 */
+#define MCFSIM2_INTLEVEL2       (MCF_MBAR2 + 0x144)     /* Intr level reg 2 */
+#define MCFSIM2_INTLEVEL3       (MCF_MBAR2 + 0x148)     /* Intr level reg 3 */
+#define MCFSIM2_INTLEVEL4       (MCF_MBAR2 + 0x14c)     /* Intr level reg 4 */
+#define MCFSIM2_INTLEVEL5       (MCF_MBAR2 + 0x150)     /* Intr level reg 5 */
+#define MCFSIM2_INTLEVEL6       (MCF_MBAR2 + 0x154)     /* Intr level reg 6 */
+#define MCFSIM2_INTLEVEL7       (MCF_MBAR2 + 0x158)     /* Intr level reg 7 */
+#define MCFSIM2_INTLEVEL8       (MCF_MBAR2 + 0x15c)     /* Intr level reg 8 */
 
-#define MCFSIM2_DMAROUTE        0x188           /* DMA routing */
+#define MCFSIM2_DMAROUTE        (MCF_MBAR2 + 0x188)     /* DMA routing */
 
-#define MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
-#define MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
+#define MCFSIM2_IDECONFIG1      (MCF_MBAR2 + 0x18c)     /* IDEconfig1 */
+#define MCFSIM2_IDECONFIG2      (MCF_MBAR2 + 0x190)     /* IDEconfig2 */
 
 /*
  * Define the base interrupt for the second interrupt controller.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 6da24f653902..acab61cb91ed 100644
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -26,41 +26,41 @@
 /*
  *      Define the 525x SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index a58f1760d858..1fb01bb05d6c 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -21,52 +21,52 @@
 /*
  *      Define the 5272 SIM register set addresses.
  */
-#define MCFSIM_SCR              0x04            /* SIM Config reg (r/w) */
-#define MCFSIM_SPR              0x06            /* System Protection reg (r/w)*/
-#define MCFSIM_PMR              0x08            /* Power Management reg (r/w) */
-#define MCFSIM_APMR             0x0e            /* Active Low Power reg (r/w) */
-#define MCFSIM_DIR              0x10            /* Device Identity reg (r/w) */
-
-#define MCFSIM_ICR1             0x20            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x24            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x28            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x2c            /* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR              0x30            /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR             0x34            /* Interrupt Transition (r/w) */
-#define MCFSIM_PIWR             0x38            /* Interrupt Wakeup reg (r/w) */
-#define MCFSIM_PIVR             0x3f            /* Interrupt Vector reg (r/w( */
-
-#define MCFSIM_WRRR             0x280           /* Watchdog reference (r/w) */
-#define MCFSIM_WIRR             0x284           /* Watchdog interrupt (r/w) */
-#define MCFSIM_WCR              0x288           /* Watchdog counter (r/w) */
-#define MCFSIM_WER              0x28c           /* Watchdog event (r/w) */
-
-#define MCFSIM_CSBR0            0x40            /* CS0 Base Address (r/w) */
-#define MCFSIM_CSOR0            0x44            /* CS0 Option (r/w) */
-#define MCFSIM_CSBR1            0x48            /* CS1 Base Address (r/w) */
-#define MCFSIM_CSOR1            0x4c            /* CS1 Option (r/w) */
-#define MCFSIM_CSBR2            0x50            /* CS2 Base Address (r/w) */
-#define MCFSIM_CSOR2            0x54            /* CS2 Option (r/w) */
-#define MCFSIM_CSBR3            0x58            /* CS3 Base Address (r/w) */
-#define MCFSIM_CSOR3            0x5c            /* CS3 Option (r/w) */
-#define MCFSIM_CSBR4            0x60            /* CS4 Base Address (r/w) */
-#define MCFSIM_CSOR4            0x64            /* CS4 Option (r/w) */
-#define MCFSIM_CSBR5            0x68            /* CS5 Base Address (r/w) */
-#define MCFSIM_CSOR5            0x6c            /* CS5 Option (r/w) */
-#define MCFSIM_CSBR6            0x70            /* CS6 Base Address (r/w) */
-#define MCFSIM_CSOR6            0x74            /* CS6 Option (r/w) */
-#define MCFSIM_CSBR7            0x78            /* CS7 Base Address (r/w) */
-#define MCFSIM_CSOR7            0x7c            /* CS7 Option (r/w) */
-
-#define MCFSIM_SDCR             0x180           /* SDRAM Configuration (r/w) */
-#define MCFSIM_SDTR             0x184           /* SDRAM Timing (r/w) */
-#define MCFSIM_DCAR0            0x4c            /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DCMR0            0x50            /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCCR0            0x57            /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DCAR1            0x58            /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DCMR1            0x5c            /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCCR1            0x63            /* DRAM 1 Control reg (r/w) */
+#define MCFSIM_SCR              (MCF_MBAR + 0x04)       /* SIM Config reg */
+#define MCFSIM_SPR              (MCF_MBAR + 0x06)       /* System Protection */
+#define MCFSIM_PMR              (MCF_MBAR + 0x08)       /* Power Management */
+#define MCFSIM_APMR             (MCF_MBAR + 0x0e)       /* Active Low Power */
+#define MCFSIM_DIR              (MCF_MBAR + 0x10)       /* Device Identity */
+
+#define MCFSIM_ICR1             (MCF_MBAR + 0x20)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x24)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x28)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x2c)       /* Intr Ctrl reg 4 */
+
+#define MCFSIM_ISR              (MCF_MBAR + 0x30)       /* Intr Source */
+#define MCFSIM_PITR             (MCF_MBAR + 0x34)       /* Intr Transition */
+#define MCFSIM_PIWR             (MCF_MBAR + 0x38)       /* Intr Wakeup */
+#define MCFSIM_PIVR             (MCF_MBAR + 0x3f)       /* Intr Vector */
+
+#define MCFSIM_WRRR             (MCF_MBAR + 0x280)      /* Watchdog reference */
+#define MCFSIM_WIRR             (MCF_MBAR + 0x284)      /* Watchdog interrupt */
+#define MCFSIM_WCR              (MCF_MBAR + 0x288)      /* Watchdog counter */
+#define MCFSIM_WER              (MCF_MBAR + 0x28c)      /* Watchdog event */
+
+#define MCFSIM_CSBR0            (MCF_MBAR + 0x40)       /* CS0 Base Address */
+#define MCFSIM_CSOR0            (MCF_MBAR + 0x44)       /* CS0 Option */
+#define MCFSIM_CSBR1            (MCF_MBAR + 0x48)       /* CS1 Base Address */
+#define MCFSIM_CSOR1            (MCF_MBAR + 0x4c)       /* CS1 Option */
+#define MCFSIM_CSBR2            (MCF_MBAR + 0x50)       /* CS2 Base Address */
+#define MCFSIM_CSOR2            (MCF_MBAR + 0x54)       /* CS2 Option */
+#define MCFSIM_CSBR3            (MCF_MBAR + 0x58)       /* CS3 Base Address */
+#define MCFSIM_CSOR3            (MCF_MBAR + 0x5c)       /* CS3 Option */
+#define MCFSIM_CSBR4            (MCF_MBAR + 0x60)       /* CS4 Base Address */
+#define MCFSIM_CSOR4            (MCF_MBAR + 0x64)       /* CS4 Option */
+#define MCFSIM_CSBR5            (MCF_MBAR + 0x68)       /* CS5 Base Address */
+#define MCFSIM_CSOR5            (MCF_MBAR + 0x6c)       /* CS5 Option */
+#define MCFSIM_CSBR6            (MCF_MBAR + 0x70)       /* CS6 Base Address */
+#define MCFSIM_CSOR6            (MCF_MBAR + 0x74)       /* CS6 Option */
+#define MCFSIM_CSBR7            (MCF_MBAR + 0x78)       /* CS7 Base Address */
+#define MCFSIM_CSOR7            (MCF_MBAR + 0x7c)       /* CS7 Option */
+
+#define MCFSIM_SDCR             (MCF_MBAR + 0x180)      /* SDRAM Config */
+#define MCFSIM_SDTR             (MCF_MBAR + 0x184)      /* SDRAM Timing */
+#define MCFSIM_DCAR0            (MCF_MBAR + 0x4c)       /* DRAM 0 Address */
+#define MCFSIM_DCMR0            (MCF_MBAR + 0x50)       /* DRAM 0 Mask */
+#define MCFSIM_DCCR0            (MCF_MBAR + 0x57)       /* DRAM 0 Control */
+#define MCFSIM_DCAR1            (MCF_MBAR + 0x58)       /* DRAM 1 Address */
+#define MCFSIM_DCMR1            (MCF_MBAR + 0x5c)       /* DRAM 1 Mask reg */
+#define MCFSIM_DCCR1            (MCF_MBAR + 0x63)       /* DRAM 1 Control */
 
 #define MCFUART_BASE0           (MCF_MBAR + 0x100) /* Base address UART0 */
 #define MCFUART_BASE1           (MCF_MBAR + 0x140) /* Base address UART1 */
@@ -132,8 +132,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 48
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         48
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
+
 /****************************************************************************/
 #endif  /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 71aa5104d3d6..1bebbe78055a 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -184,19 +184,33 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR            MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX                 100
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         100
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
-#endif
+
+#define UART0_ENABLE_MASK       0x000f
+#define UART1_ENABLE_MASK       0x0ff0
+#define UART2_ENABLE_MASK       0x3000
+#endif /* CONFIG_M5271 */
 
 #ifdef CONFIG_M5275
 #define MCFGPIO_PODR_BUSCTL     (MCF_IPSBAR + 0x100004)
@@ -279,18 +293,36 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_BUSCTL
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_BUSCTL
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_BUSCTL
+#define MCFGPIO_PODR            MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_BUSCTL
 
-#define MCFGPIO_PIN_MAX                 148
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         148
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB         (MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL      (MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL      (MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x10007C)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10007E)
-#endif
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK       0x000f
+#define UART1_ENABLE_MASK       0x00f0
+#define UART2_ENABLE_MASK       0x3f00
+#endif /* CONFIG_M5275 */
 
 /*
  * PIT timer base addresses.
@@ -311,22 +343,6 @@
 #define MCFEPORT_EPFR           (MCF_IPSBAR + 0x130006)
 
 /*
- *      GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART       0x100048        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x0ff0
-#define UART2_ENABLE_MASK       0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART       0x10007c        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x00f0
-#define UART2_ENABLE_MASK       0x3f00 
-#endif
-
-/*
  *  Reset Control Unit (relative to IPSBAR).
  */
 #define MCF_RCR                 (MCF_IPSBAR + 0x110000)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 4acb3c0a642e..cf68ca0ac3a5 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -233,23 +233,6 @@
 #define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 #define MCFGPIO_PIN_MAX         180
 
-
-/*
- *      Derek Cheung - 6 Feb 2005
- *              add I2C and QSPI register definition using Freescale's MCF5282
- */
-/* set Port AS pin for I2C or UART */
-#define MCF5282_GPIO_PASPAR     (volatile u16 *) (MCF_IPSBAR + 0x00100056)
-
-/* Port UA Pin Assignment Register (8 Bit) */
-#define MCF5282_GPIO_PUAPAR     0x10005C
-
-/* Interrupt Mask Register Register Low */ 
-#define MCF5282_INTC0_IMRL      (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
-/* Interrupt Control Register 7 */
-#define MCF5282_INTC0_ICR17     (volatile u8 *) (MCF_IPSBAR + 0x0C51)
-
-
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
@@ -259,37 +242,5 @@
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
 
-/*********************************************************************
-*
-* Inter-IC (I2C) Module
-*
-*********************************************************************/
-/* Read/Write access macros for general use */
-#define MCF5282_I2C_I2ADR       (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address 
-#define MCF5282_I2C_I2FDR       (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
-#define MCF5282_I2C_I2CR        (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
-#define MCF5282_I2C_I2SR        (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
-#define MCF5282_I2C_I2DR        (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF5282_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF5282_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF5282_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF5282_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF5282_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF5282_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF5282_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF5282_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF5282_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF5282_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF5282_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF5282_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF5282_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF5282_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF5282_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-
+/****************************************************************************/
 #endif  /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 3bc3adaa7ee0..5d0bb7ec31f8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -23,71 +23,71 @@
 /*
  *      Define the 5307 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status reg */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Itr Assignment */
+#define MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl Reg */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pend */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
 
 #ifdef CONFIG_OLDMASK
-#define MCFSIM_CSBAR            0x98            /* CS Base Address reg (r/w) */
-#define MCFSIM_CSBAMR           0x9c            /* CS Base Mask reg (r/w) */
-#define MCFSIM_CSMR2            0x9e            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSMR3            0xaa            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSMR4            0xb6            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSMR5            0xc2            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSMR6            0xce            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSMR7            0xda            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_CSBAR            (MCF_MBAR + 0x98)       /* CS Base Address */
+#define MCFSIM_CSBAMR           (MCF_MBAR + 0x9c)       /* CS Base Mask */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9e)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xaa)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb6)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc2)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xce)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xda)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 #else
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xbc)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc0)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xc8)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xcc)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xd4)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xd8)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 #endif /* CONFIG_OLDMASK */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
@@ -127,9 +127,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 16
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         16
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
 
 
 /* Definition offset address for CS2-7  -- old mask 5307 */
@@ -167,9 +167,9 @@
 /*
  *       Defines for the IRQPAR Register
  */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
+#define IRQ5_LEVEL4             0x80
+#define IRQ3_LEVEL6             0x40
+#define IRQ1_LEVEL2             0x20
 
 /*
  *      Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b298c6eb..8668e47ced0e 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -15,10 +15,6 @@
 
 #include <asm/m53xxacr.h>
 
-#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
-#define MCF_REG16(x) (*(volatile unsigned short *)(x))
-#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
-
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
@@ -38,7 +34,7 @@
 
 #define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
 
-#define MCF_WTM_WCR     MCF_REG16(0xFC098000)
+#define MCF_WTM_WCR             0xFC098000
 
 /*
  *      Define the 532x SIM register set addresses.
@@ -152,42 +148,6 @@
 #define MCFPM_PPMHR1            0xfc040038
 #define MCFPM_LPCR              0xec090007
 
-/*********************************************************************
- *
- * Inter-IC (I2C) Module
- *
- *********************************************************************/
-
-/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR       (volatile u8 *) (0xFC058000) // Address 
-#define MCF532x_I2C_I2FDR       (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR        (volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR        (volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR        (volatile u8 *) (0xFC058010) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF532x_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF532x_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF532x_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF532x_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF532x_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF532x_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-#define MCF532x_PAR_FECI2C      (volatile u8 *) (0xFC0A4053)
-
-
 /*
  *      The M5329EVB board needs a help getting its devices initialized 
  *      at kernel start time if dBUG doesn't set it up (for example 
@@ -217,13 +177,13 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_CCM_CCR               MCF_REG16(0xFC0A0004)
-#define MCF_CCM_RCON              MCF_REG16(0xFC0A0008)
-#define MCF_CCM_CIR               MCF_REG16(0xFC0A000A)
-#define MCF_CCM_MISCCR            MCF_REG16(0xFC0A0010)
-#define MCF_CCM_CDR               MCF_REG16(0xFC0A0012)
-#define MCF_CCM_UHCSR             MCF_REG16(0xFC0A0014)
-#define MCF_CCM_UOCSR             MCF_REG16(0xFC0A0016)
+#define MCF_CCM_CCR               0xFC0A0004
+#define MCF_CCM_RCON              0xFC0A0008
+#define MCF_CCM_CIR               0xFC0A000A
+#define MCF_CCM_MISCCR            0xFC0A0010
+#define MCF_CCM_CDR               0xFC0A0012
+#define MCF_CCM_UHCSR             0xFC0A0014
+#define MCF_CCM_UOCSR             0xFC0A0016
 
 /* Bit definitions and macros for MCF_CCM_CCR */
 #define MCF_CCM_CCR_RESERVED      (0x0001)
@@ -287,104 +247,29 @@
 
 /*********************************************************************
  *
- * DMA Timers (DTIM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_DTIM0_DTMR           MCF_REG16(0xFC070000)
-#define MCF_DTIM0_DTXMR          MCF_REG08(0xFC070002)
-#define MCF_DTIM0_DTER           MCF_REG08(0xFC070003)
-#define MCF_DTIM0_DTRR           MCF_REG32(0xFC070004)
-#define MCF_DTIM0_DTCR           MCF_REG32(0xFC070008)
-#define MCF_DTIM0_DTCN           MCF_REG32(0xFC07000C)
-#define MCF_DTIM1_DTMR           MCF_REG16(0xFC074000)
-#define MCF_DTIM1_DTXMR          MCF_REG08(0xFC074002)
-#define MCF_DTIM1_DTER           MCF_REG08(0xFC074003)
-#define MCF_DTIM1_DTRR           MCF_REG32(0xFC074004)
-#define MCF_DTIM1_DTCR           MCF_REG32(0xFC074008)
-#define MCF_DTIM1_DTCN           MCF_REG32(0xFC07400C)
-#define MCF_DTIM2_DTMR           MCF_REG16(0xFC078000)
-#define MCF_DTIM2_DTXMR          MCF_REG08(0xFC078002)
-#define MCF_DTIM2_DTER           MCF_REG08(0xFC078003)
-#define MCF_DTIM2_DTRR           MCF_REG32(0xFC078004)
-#define MCF_DTIM2_DTCR           MCF_REG32(0xFC078008)
-#define MCF_DTIM2_DTCN           MCF_REG32(0xFC07800C)
-#define MCF_DTIM3_DTMR           MCF_REG16(0xFC07C000)
-#define MCF_DTIM3_DTXMR          MCF_REG08(0xFC07C002)
-#define MCF_DTIM3_DTER           MCF_REG08(0xFC07C003)
-#define MCF_DTIM3_DTRR           MCF_REG32(0xFC07C004)
-#define MCF_DTIM3_DTCR           MCF_REG32(0xFC07C008)
-#define MCF_DTIM3_DTCN           MCF_REG32(0xFC07C00C)
-#define MCF_DTIM_DTMR(x)         MCF_REG16(0xFC070000+((x)*0x4000))
-#define MCF_DTIM_DTXMR(x)        MCF_REG08(0xFC070002+((x)*0x4000))
-#define MCF_DTIM_DTER(x)         MCF_REG08(0xFC070003+((x)*0x4000))
-#define MCF_DTIM_DTRR(x)         MCF_REG32(0xFC070004+((x)*0x4000))
-#define MCF_DTIM_DTCR(x)         MCF_REG32(0xFC070008+((x)*0x4000))
-#define MCF_DTIM_DTCN(x)         MCF_REG32(0xFC07000C+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_DTIM_DTMR */
-#define MCF_DTIM_DTMR_RST        (0x0001)
-#define MCF_DTIM_DTMR_CLK(x)     (((x)&0x0003)<<1)
-#define MCF_DTIM_DTMR_FRR        (0x0008)
-#define MCF_DTIM_DTMR_ORRI       (0x0010)
-#define MCF_DTIM_DTMR_OM         (0x0020)
-#define MCF_DTIM_DTMR_CE(x)      (((x)&0x0003)<<6)
-#define MCF_DTIM_DTMR_PS(x)      (((x)&0x00FF)<<8)
-#define MCF_DTIM_DTMR_CE_ANY     (0x00C0)
-#define MCF_DTIM_DTMR_CE_FALL    (0x0080)
-#define MCF_DTIM_DTMR_CE_RISE    (0x0040)
-#define MCF_DTIM_DTMR_CE_NONE    (0x0000)
-#define MCF_DTIM_DTMR_CLK_DTIN   (0x0006)
-#define MCF_DTIM_DTMR_CLK_DIV16  (0x0004)
-#define MCF_DTIM_DTMR_CLK_DIV1   (0x0002)
-#define MCF_DTIM_DTMR_CLK_STOP   (0x0000)
-
-/* Bit definitions and macros for MCF_DTIM_DTXMR */
-#define MCF_DTIM_DTXMR_MODE16    (0x01)
-#define MCF_DTIM_DTXMR_DMAEN     (0x80)
-
-/* Bit definitions and macros for MCF_DTIM_DTER */
-#define MCF_DTIM_DTER_CAP        (0x01)
-#define MCF_DTIM_DTER_REF        (0x02)
-
-/* Bit definitions and macros for MCF_DTIM_DTRR */
-#define MCF_DTIM_DTRR_REF(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCR */
-#define MCF_DTIM_DTCR_CAP(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCN */
-#define MCF_DTIM_DTCN_CNT(x)     (((x)&0xFFFFFFFF)<<0)
-
-/*********************************************************************
- *
  * FlexBus Chip Selects (FBCS)
  *
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_FBCS0_CSAR          MCF_REG32(0xFC008000)
-#define MCF_FBCS0_CSMR          MCF_REG32(0xFC008004)
-#define MCF_FBCS0_CSCR          MCF_REG32(0xFC008008)
-#define MCF_FBCS1_CSAR          MCF_REG32(0xFC00800C)
-#define MCF_FBCS1_CSMR          MCF_REG32(0xFC008010)
-#define MCF_FBCS1_CSCR          MCF_REG32(0xFC008014)
-#define MCF_FBCS2_CSAR          MCF_REG32(0xFC008018)
-#define MCF_FBCS2_CSMR          MCF_REG32(0xFC00801C)
-#define MCF_FBCS2_CSCR          MCF_REG32(0xFC008020)
-#define MCF_FBCS3_CSAR          MCF_REG32(0xFC008024)
-#define MCF_FBCS3_CSMR          MCF_REG32(0xFC008028)
-#define MCF_FBCS3_CSCR          MCF_REG32(0xFC00802C)
-#define MCF_FBCS4_CSAR          MCF_REG32(0xFC008030)
-#define MCF_FBCS4_CSMR          MCF_REG32(0xFC008034)
-#define MCF_FBCS4_CSCR          MCF_REG32(0xFC008038)
-#define MCF_FBCS5_CSAR          MCF_REG32(0xFC00803C)
-#define MCF_FBCS5_CSMR          MCF_REG32(0xFC008040)
-#define MCF_FBCS5_CSCR          MCF_REG32(0xFC008044)
-#define MCF_FBCS_CSAR(x)        MCF_REG32(0xFC008000+((x)*0x00C))
-#define MCF_FBCS_CSMR(x)        MCF_REG32(0xFC008004+((x)*0x00C))
-#define MCF_FBCS_CSCR(x)        MCF_REG32(0xFC008008+((x)*0x00C))
+#define MCF_FBCS0_CSAR          0xFC008000
+#define MCF_FBCS0_CSMR          0xFC008004
+#define MCF_FBCS0_CSCR          0xFC008008
+#define MCF_FBCS1_CSAR          0xFC00800C
+#define MCF_FBCS1_CSMR          0xFC008010
+#define MCF_FBCS1_CSCR          0xFC008014
+#define MCF_FBCS2_CSAR          0xFC008018
+#define MCF_FBCS2_CSMR          0xFC00801C
+#define MCF_FBCS2_CSCR          0xFC008020
+#define MCF_FBCS3_CSAR          0xFC008024
+#define MCF_FBCS3_CSMR          0xFC008028
+#define MCF_FBCS3_CSCR          0xFC00802C
+#define MCF_FBCS4_CSAR          0xFC008030
+#define MCF_FBCS4_CSMR          0xFC008034
+#define MCF_FBCS4_CSCR          0xFC008038
+#define MCF_FBCS5_CSAR          0xFC00803C
+#define MCF_FBCS5_CSMR          0xFC008040
+#define MCF_FBCS5_CSCR          0xFC008044
 
 /* Bit definitions and macros for MCF_FBCS_CSAR */
 #define MCF_FBCS_CSAR_BA(x)     ((x)&0xFFFF0000)
@@ -501,32 +386,32 @@
 #define MCFGPIO_PCLRR_LCDDATAL          (0xFC0A404B)
 #define MCFGPIO_PCLRR_LCDCTLH           (0xFC0A404C)
 #define MCFGPIO_PCLRR_LCDCTLL           (0xFC0A404D)
-#define MCF_GPIO_PAR_FEC                MCF_REG08(0xFC0A4050)
-#define MCF_GPIO_PAR_PWM                MCF_REG08(0xFC0A4051)
-#define MCF_GPIO_PAR_BUSCTL             MCF_REG08(0xFC0A4052)
-#define MCF_GPIO_PAR_FECI2C             MCF_REG08(0xFC0A4053)
-#define MCF_GPIO_PAR_BE                 MCF_REG08(0xFC0A4054)
-#define MCF_GPIO_PAR_CS                 MCF_REG08(0xFC0A4055)
-#define MCF_GPIO_PAR_SSI                MCF_REG16(0xFC0A4056)
-#define MCF_GPIO_PAR_UART               MCF_REG16(0xFC0A4058)
-#define MCF_GPIO_PAR_QSPI               MCF_REG16(0xFC0A405A)
-#define MCF_GPIO_PAR_TIMER              MCF_REG08(0xFC0A405C)
-#define MCF_GPIO_PAR_LCDDATA            MCF_REG08(0xFC0A405D)
-#define MCF_GPIO_PAR_LCDCTL             MCF_REG16(0xFC0A405E)
-#define MCF_GPIO_PAR_IRQ                MCF_REG16(0xFC0A4060)
-#define MCF_GPIO_MSCR_FLEXBUS           MCF_REG08(0xFC0A4064)
-#define MCF_GPIO_MSCR_SDRAM             MCF_REG08(0xFC0A4065)
-#define MCF_GPIO_DSCR_I2C               MCF_REG08(0xFC0A4068)
-#define MCF_GPIO_DSCR_PWM               MCF_REG08(0xFC0A4069)
-#define MCF_GPIO_DSCR_FEC               MCF_REG08(0xFC0A406A)
-#define MCF_GPIO_DSCR_UART              MCF_REG08(0xFC0A406B)
-#define MCF_GPIO_DSCR_QSPI              MCF_REG08(0xFC0A406C)
-#define MCF_GPIO_DSCR_TIMER             MCF_REG08(0xFC0A406D)
-#define MCF_GPIO_DSCR_SSI               MCF_REG08(0xFC0A406E)
-#define MCF_GPIO_DSCR_LCD               MCF_REG08(0xFC0A406F)
-#define MCF_GPIO_DSCR_DEBUG             MCF_REG08(0xFC0A4070)
-#define MCF_GPIO_DSCR_CLKRST            MCF_REG08(0xFC0A4071)
-#define MCF_GPIO_DSCR_IRQ               MCF_REG08(0xFC0A4072)
+#define MCFGPIO_PAR_FEC                 (0xFC0A4050)
+#define MCFGPIO_PAR_PWM                 (0xFC0A4051)
+#define MCFGPIO_PAR_BUSCTL              (0xFC0A4052)
+#define MCFGPIO_PAR_FECI2C              (0xFC0A4053)
+#define MCFGPIO_PAR_BE                  (0xFC0A4054)
+#define MCFGPIO_PAR_CS                  (0xFC0A4055)
+#define MCFGPIO_PAR_SSI                 (0xFC0A4056)
+#define MCFGPIO_PAR_UART                (0xFC0A4058)
+#define MCFGPIO_PAR_QSPI                (0xFC0A405A)
+#define MCFGPIO_PAR_TIMER               (0xFC0A405C)
+#define MCFGPIO_PAR_LCDDATA             (0xFC0A405D)
+#define MCFGPIO_PAR_LCDCTL              (0xFC0A405E)
+#define MCFGPIO_PAR_IRQ                 (0xFC0A4060)
+#define MCFGPIO_MSCR_FLEXBUS            (0xFC0A4064)
+#define MCFGPIO_MSCR_SDRAM              (0xFC0A4065)
+#define MCFGPIO_DSCR_I2C                (0xFC0A4068)
+#define MCFGPIO_DSCR_PWM                (0xFC0A4069)
+#define MCFGPIO_DSCR_FEC                (0xFC0A406A)
+#define MCFGPIO_DSCR_UART               (0xFC0A406B)
+#define MCFGPIO_DSCR_QSPI               (0xFC0A406C)
+#define MCFGPIO_DSCR_TIMER              (0xFC0A406D)
+#define MCFGPIO_DSCR_SSI                (0xFC0A406E)
+#define MCFGPIO_DSCR_LCD                (0xFC0A406F)
+#define MCFGPIO_DSCR_DEBUG              (0xFC0A4070)
+#define MCFGPIO_DSCR_CLKRST             (0xFC0A4071)
+#define MCFGPIO_DSCR_IRQ                (0xFC0A4072)
 
 /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
 #define MCF_GPIO_PODR_FECH_PODR_FECH0              (0x01)
@@ -1215,709 +1100,6 @@
 #define MCFGPIO_IRQ_MAX                 8
 #define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
 
-
-/*********************************************************************
- *
- * Interrupt Controller (INTC)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH             MCF_REG32(0xFC048000)
-#define MCF_INTC0_IPRL             MCF_REG32(0xFC048004)
-#define MCF_INTC0_IMRH             MCF_REG32(0xFC048008)
-#define MCF_INTC0_IMRL             MCF_REG32(0xFC04800C)
-#define MCF_INTC0_INTFRCH          MCF_REG32(0xFC048010)
-#define MCF_INTC0_INTFRCL          MCF_REG32(0xFC048014)
-#define MCF_INTC0_ICONFIG          MCF_REG16(0xFC04801A)
-#define MCF_INTC0_SIMR             MCF_REG08(0xFC04801C)
-#define MCF_INTC0_CIMR             MCF_REG08(0xFC04801D)
-#define MCF_INTC0_CLMASK           MCF_REG08(0xFC04801E)
-#define MCF_INTC0_SLMASK           MCF_REG08(0xFC04801F)
-#define MCF_INTC0_ICR0             MCF_REG08(0xFC048040)
-#define MCF_INTC0_ICR1             MCF_REG08(0xFC048041)
-#define MCF_INTC0_ICR2             MCF_REG08(0xFC048042)
-#define MCF_INTC0_ICR3             MCF_REG08(0xFC048043)
-#define MCF_INTC0_ICR4             MCF_REG08(0xFC048044)
-#define MCF_INTC0_ICR5             MCF_REG08(0xFC048045)
-#define MCF_INTC0_ICR6             MCF_REG08(0xFC048046)
-#define MCF_INTC0_ICR7             MCF_REG08(0xFC048047)
-#define MCF_INTC0_ICR8             MCF_REG08(0xFC048048)
-#define MCF_INTC0_ICR9             MCF_REG08(0xFC048049)
-#define MCF_INTC0_ICR10            MCF_REG08(0xFC04804A)
-#define MCF_INTC0_ICR11            MCF_REG08(0xFC04804B)
-#define MCF_INTC0_ICR12            MCF_REG08(0xFC04804C)
-#define MCF_INTC0_ICR13            MCF_REG08(0xFC04804D)
-#define MCF_INTC0_ICR14            MCF_REG08(0xFC04804E)
-#define MCF_INTC0_ICR15            MCF_REG08(0xFC04804F)
-#define MCF_INTC0_ICR16            MCF_REG08(0xFC048050)
-#define MCF_INTC0_ICR17            MCF_REG08(0xFC048051)
-#define MCF_INTC0_ICR18            MCF_REG08(0xFC048052)
-#define MCF_INTC0_ICR19            MCF_REG08(0xFC048053)
-#define MCF_INTC0_ICR20            MCF_REG08(0xFC048054)
-#define MCF_INTC0_ICR21            MCF_REG08(0xFC048055)
-#define MCF_INTC0_ICR22            MCF_REG08(0xFC048056)
-#define MCF_INTC0_ICR23            MCF_REG08(0xFC048057)
-#define MCF_INTC0_ICR24            MCF_REG08(0xFC048058)
-#define MCF_INTC0_ICR25            MCF_REG08(0xFC048059)
-#define MCF_INTC0_ICR26            MCF_REG08(0xFC04805A)
-#define MCF_INTC0_ICR27            MCF_REG08(0xFC04805B)
-#define MCF_INTC0_ICR28            MCF_REG08(0xFC04805C)
-#define MCF_INTC0_ICR29            MCF_REG08(0xFC04805D)
-#define MCF_INTC0_ICR30            MCF_REG08(0xFC04805E)
-#define MCF_INTC0_ICR31            MCF_REG08(0xFC04805F)
-#define MCF_INTC0_ICR32            MCF_REG08(0xFC048060)
-#define MCF_INTC0_ICR33            MCF_REG08(0xFC048061)
-#define MCF_INTC0_ICR34            MCF_REG08(0xFC048062)
-#define MCF_INTC0_ICR35            MCF_REG08(0xFC048063)
-#define MCF_INTC0_ICR36            MCF_REG08(0xFC048064)
-#define MCF_INTC0_ICR37            MCF_REG08(0xFC048065)
-#define MCF_INTC0_ICR38            MCF_REG08(0xFC048066)
-#define MCF_INTC0_ICR39            MCF_REG08(0xFC048067)
-#define MCF_INTC0_ICR40            MCF_REG08(0xFC048068)
-#define MCF_INTC0_ICR41            MCF_REG08(0xFC048069)
-#define MCF_INTC0_ICR42            MCF_REG08(0xFC04806A)
-#define MCF_INTC0_ICR43            MCF_REG08(0xFC04806B)
-#define MCF_INTC0_ICR44            MCF_REG08(0xFC04806C)
-#define MCF_INTC0_ICR45            MCF_REG08(0xFC04806D)
-#define MCF_INTC0_ICR46            MCF_REG08(0xFC04806E)
-#define MCF_INTC0_ICR47            MCF_REG08(0xFC04806F)
-#define MCF_INTC0_ICR48            MCF_REG08(0xFC048070)
-#define MCF_INTC0_ICR49            MCF_REG08(0xFC048071)
-#define MCF_INTC0_ICR50            MCF_REG08(0xFC048072)
-#define MCF_INTC0_ICR51            MCF_REG08(0xFC048073)
-#define MCF_INTC0_ICR52            MCF_REG08(0xFC048074)
-#define MCF_INTC0_ICR53            MCF_REG08(0xFC048075)
-#define MCF_INTC0_ICR54            MCF_REG08(0xFC048076)
-#define MCF_INTC0_ICR55            MCF_REG08(0xFC048077)
-#define MCF_INTC0_ICR56            MCF_REG08(0xFC048078)
-#define MCF_INTC0_ICR57            MCF_REG08(0xFC048079)
-#define MCF_INTC0_ICR58            MCF_REG08(0xFC04807A)
-#define MCF_INTC0_ICR59            MCF_REG08(0xFC04807B)
-#define MCF_INTC0_ICR60            MCF_REG08(0xFC04807C)
-#define MCF_INTC0_ICR61            MCF_REG08(0xFC04807D)
-#define MCF_INTC0_ICR62            MCF_REG08(0xFC04807E)
-#define MCF_INTC0_ICR63            MCF_REG08(0xFC04807F)
-#define MCF_INTC0_ICR(x)           MCF_REG08(0xFC048040+((x)*0x001))
-#define MCF_INTC0_SWIACK           MCF_REG08(0xFC0480E0)
-#define MCF_INTC0_L1IACK           MCF_REG08(0xFC0480E4)
-#define MCF_INTC0_L2IACK           MCF_REG08(0xFC0480E8)
-#define MCF_INTC0_L3IACK           MCF_REG08(0xFC0480EC)
-#define MCF_INTC0_L4IACK           MCF_REG08(0xFC0480F0)
-#define MCF_INTC0_L5IACK           MCF_REG08(0xFC0480F4)
-#define MCF_INTC0_L6IACK           MCF_REG08(0xFC0480F8)
-#define MCF_INTC0_L7IACK           MCF_REG08(0xFC0480FC)
-#define MCF_INTC0_LIACK(x)         MCF_REG08(0xFC0480E4+((x)*0x004))
-#define MCF_INTC1_IPRH             MCF_REG32(0xFC04C000)
-#define MCF_INTC1_IPRL             MCF_REG32(0xFC04C004)
-#define MCF_INTC1_IMRH             MCF_REG32(0xFC04C008)
-#define MCF_INTC1_IMRL             MCF_REG32(0xFC04C00C)
-#define MCF_INTC1_INTFRCH          MCF_REG32(0xFC04C010)
-#define MCF_INTC1_INTFRCL          MCF_REG32(0xFC04C014)
-#define MCF_INTC1_ICONFIG          MCF_REG16(0xFC04C01A)
-#define MCF_INTC1_SIMR             MCF_REG08(0xFC04C01C)
-#define MCF_INTC1_CIMR             MCF_REG08(0xFC04C01D)
-#define MCF_INTC1_CLMASK           MCF_REG08(0xFC04C01E)
-#define MCF_INTC1_SLMASK           MCF_REG08(0xFC04C01F)
-#define MCF_INTC1_ICR0             MCF_REG08(0xFC04C040)
-#define MCF_INTC1_ICR1             MCF_REG08(0xFC04C041)
-#define MCF_INTC1_ICR2             MCF_REG08(0xFC04C042)
-#define MCF_INTC1_ICR3             MCF_REG08(0xFC04C043)
-#define MCF_INTC1_ICR4             MCF_REG08(0xFC04C044)
-#define MCF_INTC1_ICR5             MCF_REG08(0xFC04C045)
-#define MCF_INTC1_ICR6             MCF_REG08(0xFC04C046)
-#define MCF_INTC1_ICR7             MCF_REG08(0xFC04C047)
-#define MCF_INTC1_ICR8             MCF_REG08(0xFC04C048)
-#define MCF_INTC1_ICR9             MCF_REG08(0xFC04C049)
-#define MCF_INTC1_ICR10            MCF_REG08(0xFC04C04A)
-#define MCF_INTC1_ICR11            MCF_REG08(0xFC04C04B)
-#define MCF_INTC1_ICR12            MCF_REG08(0xFC04C04C)
-#define MCF_INTC1_ICR13            MCF_REG08(0xFC04C04D)
-#define MCF_INTC1_ICR14            MCF_REG08(0xFC04C04E)
-#define MCF_INTC1_ICR15            MCF_REG08(0xFC04C04F)
-#define MCF_INTC1_ICR16            MCF_REG08(0xFC04C050)
-#define MCF_INTC1_ICR17            MCF_REG08(0xFC04C051)
-#define MCF_INTC1_ICR18            MCF_REG08(0xFC04C052)
-#define MCF_INTC1_ICR19            MCF_REG08(0xFC04C053)
-#define MCF_INTC1_ICR20            MCF_REG08(0xFC04C054)
-#define MCF_INTC1_ICR21            MCF_REG08(0xFC04C055)
-#define MCF_INTC1_ICR22            MCF_REG08(0xFC04C056)
-#define MCF_INTC1_ICR23            MCF_REG08(0xFC04C057)
-#define MCF_INTC1_ICR24            MCF_REG08(0xFC04C058)
-#define MCF_INTC1_ICR25            MCF_REG08(0xFC04C059)
-#define MCF_INTC1_ICR26            MCF_REG08(0xFC04C05A)
-#define MCF_INTC1_ICR27            MCF_REG08(0xFC04C05B)
-#define MCF_INTC1_ICR28            MCF_REG08(0xFC04C05C)
-#define MCF_INTC1_ICR29            MCF_REG08(0xFC04C05D)
-#define MCF_INTC1_ICR30            MCF_REG08(0xFC04C05E)
-#define MCF_INTC1_ICR31            MCF_REG08(0xFC04C05F)
-#define MCF_INTC1_ICR32            MCF_REG08(0xFC04C060)
-#define MCF_INTC1_ICR33            MCF_REG08(0xFC04C061)
-#define MCF_INTC1_ICR34            MCF_REG08(0xFC04C062)
-#define MCF_INTC1_ICR35            MCF_REG08(0xFC04C063)
-#define MCF_INTC1_ICR36            MCF_REG08(0xFC04C064)
-#define MCF_INTC1_ICR37            MCF_REG08(0xFC04C065)
-#define MCF_INTC1_ICR38            MCF_REG08(0xFC04C066)
-#define MCF_INTC1_ICR39            MCF_REG08(0xFC04C067)
-#define MCF_INTC1_ICR40            MCF_REG08(0xFC04C068)
-#define MCF_INTC1_ICR41            MCF_REG08(0xFC04C069)
-#define MCF_INTC1_ICR42            MCF_REG08(0xFC04C06A)
-#define MCF_INTC1_ICR43            MCF_REG08(0xFC04C06B)
-#define MCF_INTC1_ICR44            MCF_REG08(0xFC04C06C)
-#define MCF_INTC1_ICR45            MCF_REG08(0xFC04C06D)
-#define MCF_INTC1_ICR46            MCF_REG08(0xFC04C06E)
-#define MCF_INTC1_ICR47            MCF_REG08(0xFC04C06F)
-#define MCF_INTC1_ICR48            MCF_REG08(0xFC04C070)
-#define MCF_INTC1_ICR49            MCF_REG08(0xFC04C071)
-#define MCF_INTC1_ICR50            MCF_REG08(0xFC04C072)
-#define MCF_INTC1_ICR51            MCF_REG08(0xFC04C073)
-#define MCF_INTC1_ICR52            MCF_REG08(0xFC04C074)
-#define MCF_INTC1_ICR53            MCF_REG08(0xFC04C075)
-#define MCF_INTC1_ICR54            MCF_REG08(0xFC04C076)
-#define MCF_INTC1_ICR55            MCF_REG08(0xFC04C077)
-#define MCF_INTC1_ICR56            MCF_REG08(0xFC04C078)
-#define MCF_INTC1_ICR57            MCF_REG08(0xFC04C079)
-#define MCF_INTC1_ICR58            MCF_REG08(0xFC04C07A)
-#define MCF_INTC1_ICR59            MCF_REG08(0xFC04C07B)
-#define MCF_INTC1_ICR60            MCF_REG08(0xFC04C07C)
-#define MCF_INTC1_ICR61            MCF_REG08(0xFC04C07D)
-#define MCF_INTC1_ICR62            MCF_REG08(0xFC04C07E)
-#define MCF_INTC1_ICR63            MCF_REG08(0xFC04C07F)
-#define MCF_INTC1_ICR(x)           MCF_REG08(0xFC04C040+((x)*0x001))
-#define MCF_INTC1_SWIACK           MCF_REG08(0xFC04C0E0)
-#define MCF_INTC1_L1IACK           MCF_REG08(0xFC04C0E4)
-#define MCF_INTC1_L2IACK           MCF_REG08(0xFC04C0E8)
-#define MCF_INTC1_L3IACK           MCF_REG08(0xFC04C0EC)
-#define MCF_INTC1_L4IACK           MCF_REG08(0xFC04C0F0)
-#define MCF_INTC1_L5IACK           MCF_REG08(0xFC04C0F4)
-#define MCF_INTC1_L6IACK           MCF_REG08(0xFC04C0F8)
-#define MCF_INTC1_L7IACK           MCF_REG08(0xFC04C0FC)
-#define MCF_INTC1_LIACK(x)         MCF_REG08(0xFC04C0E4+((x)*0x004))
-#define MCF_INTC_IPRH(x)           MCF_REG32(0xFC048000+((x)*0x4000))
-#define MCF_INTC_IPRL(x)           MCF_REG32(0xFC048004+((x)*0x4000))
-#define MCF_INTC_IMRH(x)           MCF_REG32(0xFC048008+((x)*0x4000))
-#define MCF_INTC_IMRL(x)           MCF_REG32(0xFC04800C+((x)*0x4000))
-#define MCF_INTC_INTFRCH(x)        MCF_REG32(0xFC048010+((x)*0x4000))
-#define MCF_INTC_INTFRCL(x)        MCF_REG32(0xFC048014+((x)*0x4000))
-#define MCF_INTC_ICONFIG(x)        MCF_REG16(0xFC04801A+((x)*0x4000))
-#define MCF_INTC_SIMR(x)           MCF_REG08(0xFC04801C+((x)*0x4000))
-#define MCF_INTC_CIMR(x)           MCF_REG08(0xFC04801D+((x)*0x4000))
-#define MCF_INTC_CLMASK(x)         MCF_REG08(0xFC04801E+((x)*0x4000))
-#define MCF_INTC_SLMASK(x)         MCF_REG08(0xFC04801F+((x)*0x4000))
-#define MCF_INTC_ICR0(x)           MCF_REG08(0xFC048040+((x)*0x4000))
-#define MCF_INTC_ICR1(x)           MCF_REG08(0xFC048041+((x)*0x4000))
-#define MCF_INTC_ICR2(x)           MCF_REG08(0xFC048042+((x)*0x4000))
-#define MCF_INTC_ICR3(x)           MCF_REG08(0xFC048043+((x)*0x4000))
-#define MCF_INTC_ICR4(x)           MCF_REG08(0xFC048044+((x)*0x4000))
-#define MCF_INTC_ICR5(x)           MCF_REG08(0xFC048045+((x)*0x4000))
-#define MCF_INTC_ICR6(x)           MCF_REG08(0xFC048046+((x)*0x4000))
-#define MCF_INTC_ICR7(x)           MCF_REG08(0xFC048047+((x)*0x4000))
-#define MCF_INTC_ICR8(x)           MCF_REG08(0xFC048048+((x)*0x4000))
-#define MCF_INTC_ICR9(x)           MCF_REG08(0xFC048049+((x)*0x4000))
-#define MCF_INTC_ICR10(x)          MCF_REG08(0xFC04804A+((x)*0x4000))
-#define MCF_INTC_ICR11(x)          MCF_REG08(0xFC04804B+((x)*0x4000))
-#define MCF_INTC_ICR12(x)          MCF_REG08(0xFC04804C+((x)*0x4000))
-#define MCF_INTC_ICR13(x)          MCF_REG08(0xFC04804D+((x)*0x4000))
-#define MCF_INTC_ICR14(x)          MCF_REG08(0xFC04804E+((x)*0x4000))
-#define MCF_INTC_ICR15(x)          MCF_REG08(0xFC04804F+((x)*0x4000))
-#define MCF_INTC_ICR16(x)          MCF_REG08(0xFC048050+((x)*0x4000))
-#define MCF_INTC_ICR17(x)          MCF_REG08(0xFC048051+((x)*0x4000))
-#define MCF_INTC_ICR18(x)          MCF_REG08(0xFC048052+((x)*0x4000))
-#define MCF_INTC_ICR19(x)          MCF_REG08(0xFC048053+((x)*0x4000))
-#define MCF_INTC_ICR20(x)          MCF_REG08(0xFC048054+((x)*0x4000))
-#define MCF_INTC_ICR21(x)          MCF_REG08(0xFC048055+((x)*0x4000))
-#define MCF_INTC_ICR22(x)          MCF_REG08(0xFC048056+((x)*0x4000))
-#define MCF_INTC_ICR23(x)          MCF_REG08(0xFC048057+((x)*0x4000))
-#define MCF_INTC_ICR24(x)          MCF_REG08(0xFC048058+((x)*0x4000))
-#define MCF_INTC_ICR25(x)          MCF_REG08(0xFC048059+((x)*0x4000))
-#define MCF_INTC_ICR26(x)          MCF_REG08(0xFC04805A+((x)*0x4000))
-#define MCF_INTC_ICR27(x)          MCF_REG08(0xFC04805B+((x)*0x4000))
-#define MCF_INTC_ICR28(x)          MCF_REG08(0xFC04805C+((x)*0x4000))
-#define MCF_INTC_ICR29(x)          MCF_REG08(0xFC04805D+((x)*0x4000))
-#define MCF_INTC_ICR30(x)          MCF_REG08(0xFC04805E+((x)*0x4000))
-#define MCF_INTC_ICR31(x)          MCF_REG08(0xFC04805F+((x)*0x4000))
-#define MCF_INTC_ICR32(x)          MCF_REG08(0xFC048060+((x)*0x4000))
-#define MCF_INTC_ICR33(x)          MCF_REG08(0xFC048061+((x)*0x4000))
-#define MCF_INTC_ICR34(x)          MCF_REG08(0xFC048062+((x)*0x4000))
-#define MCF_INTC_ICR35(x)          MCF_REG08(0xFC048063+((x)*0x4000))
-#define MCF_INTC_ICR36(x)          MCF_REG08(0xFC048064+((x)*0x4000))
-#define MCF_INTC_ICR37(x)          MCF_REG08(0xFC048065+((x)*0x4000))
-#define MCF_INTC_ICR38(x)          MCF_REG08(0xFC048066+((x)*0x4000))
-#define MCF_INTC_ICR39(x)          MCF_REG08(0xFC048067+((x)*0x4000))
-#define MCF_INTC_ICR40(x)          MCF_REG08(0xFC048068+((x)*0x4000))
-#define MCF_INTC_ICR41(x)          MCF_REG08(0xFC048069+((x)*0x4000))
-#define MCF_INTC_ICR42(x)          MCF_REG08(0xFC04806A+((x)*0x4000))
-#define MCF_INTC_ICR43(x)          MCF_REG08(0xFC04806B+((x)*0x4000))
-#define MCF_INTC_ICR44(x)          MCF_REG08(0xFC04806C+((x)*0x4000))
-#define MCF_INTC_ICR45(x)          MCF_REG08(0xFC04806D+((x)*0x4000))
-#define MCF_INTC_ICR46(x)          MCF_REG08(0xFC04806E+((x)*0x4000))
-#define MCF_INTC_ICR47(x)          MCF_REG08(0xFC04806F+((x)*0x4000))
-#define MCF_INTC_ICR48(x)          MCF_REG08(0xFC048070+((x)*0x4000))
-#define MCF_INTC_ICR49(x)          MCF_REG08(0xFC048071+((x)*0x4000))
-#define MCF_INTC_ICR50(x)          MCF_REG08(0xFC048072+((x)*0x4000))
-#define MCF_INTC_ICR51(x)          MCF_REG08(0xFC048073+((x)*0x4000))
-#define MCF_INTC_ICR52(x)          MCF_REG08(0xFC048074+((x)*0x4000))
-#define MCF_INTC_ICR53(x)          MCF_REG08(0xFC048075+((x)*0x4000))
-#define MCF_INTC_ICR54(x)          MCF_REG08(0xFC048076+((x)*0x4000))
-#define MCF_INTC_ICR55(x)          MCF_REG08(0xFC048077+((x)*0x4000))
-#define MCF_INTC_ICR56(x)          MCF_REG08(0xFC048078+((x)*0x4000))
-#define MCF_INTC_ICR57(x)          MCF_REG08(0xFC048079+((x)*0x4000))
-#define MCF_INTC_ICR58(x)          MCF_REG08(0xFC04807A+((x)*0x4000))
-#define MCF_INTC_ICR59(x)          MCF_REG08(0xFC04807B+((x)*0x4000))
-#define MCF_INTC_ICR60(x)          MCF_REG08(0xFC04807C+((x)*0x4000))
-#define MCF_INTC_ICR61(x)          MCF_REG08(0xFC04807D+((x)*0x4000))
-#define MCF_INTC_ICR62(x)          MCF_REG08(0xFC04807E+((x)*0x4000))
-#define MCF_INTC_ICR63(x)          MCF_REG08(0xFC04807F+((x)*0x4000))
-#define MCF_INTC_SWIACK(x)         MCF_REG08(0xFC0480E0+((x)*0x4000))
-#define MCF_INTC_L1IACK(x)         MCF_REG08(0xFC0480E4+((x)*0x4000))
-#define MCF_INTC_L2IACK(x)         MCF_REG08(0xFC0480E8+((x)*0x4000))
-#define MCF_INTC_L3IACK(x)         MCF_REG08(0xFC0480EC+((x)*0x4000))
-#define MCF_INTC_L4IACK(x)         MCF_REG08(0xFC0480F0+((x)*0x4000))
-#define MCF_INTC_L5IACK(x)         MCF_REG08(0xFC0480F4+((x)*0x4000))
-#define MCF_INTC_L6IACK(x)         MCF_REG08(0xFC0480F8+((x)*0x4000))
-#define MCF_INTC_L7IACK(x)         MCF_REG08(0xFC0480FC+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_INTC_IPRH */
-#define MCF_INTC_IPRH_INT32        (0x00000001)
-#define MCF_INTC_IPRH_INT33        (0x00000002)
-#define MCF_INTC_IPRH_INT34        (0x00000004)
-#define MCF_INTC_IPRH_INT35        (0x00000008)
-#define MCF_INTC_IPRH_INT36        (0x00000010)
-#define MCF_INTC_IPRH_INT37        (0x00000020)
-#define MCF_INTC_IPRH_INT38        (0x00000040)
-#define MCF_INTC_IPRH_INT39        (0x00000080)
-#define MCF_INTC_IPRH_INT40        (0x00000100)
-#define MCF_INTC_IPRH_INT41        (0x00000200)
-#define MCF_INTC_IPRH_INT42        (0x00000400)
-#define MCF_INTC_IPRH_INT43        (0x00000800)
-#define MCF_INTC_IPRH_INT44        (0x00001000)
-#define MCF_INTC_IPRH_INT45        (0x00002000)
-#define MCF_INTC_IPRH_INT46        (0x00004000)
-#define MCF_INTC_IPRH_INT47        (0x00008000)
-#define MCF_INTC_IPRH_INT48        (0x00010000)
-#define MCF_INTC_IPRH_INT49        (0x00020000)
-#define MCF_INTC_IPRH_INT50        (0x00040000)
-#define MCF_INTC_IPRH_INT51        (0x00080000)
-#define MCF_INTC_IPRH_INT52        (0x00100000)
-#define MCF_INTC_IPRH_INT53        (0x00200000)
-#define MCF_INTC_IPRH_INT54        (0x00400000)
-#define MCF_INTC_IPRH_INT55        (0x00800000)
-#define MCF_INTC_IPRH_INT56        (0x01000000)
-#define MCF_INTC_IPRH_INT57        (0x02000000)
-#define MCF_INTC_IPRH_INT58        (0x04000000)
-#define MCF_INTC_IPRH_INT59        (0x08000000)
-#define MCF_INTC_IPRH_INT60        (0x10000000)
-#define MCF_INTC_IPRH_INT61        (0x20000000)
-#define MCF_INTC_IPRH_INT62        (0x40000000)
-#define MCF_INTC_IPRH_INT63        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IPRL */
-#define MCF_INTC_IPRL_INT0         (0x00000001)
-#define MCF_INTC_IPRL_INT1         (0x00000002)
-#define MCF_INTC_IPRL_INT2         (0x00000004)
-#define MCF_INTC_IPRL_INT3         (0x00000008)
-#define MCF_INTC_IPRL_INT4         (0x00000010)
-#define MCF_INTC_IPRL_INT5         (0x00000020)
-#define MCF_INTC_IPRL_INT6         (0x00000040)
-#define MCF_INTC_IPRL_INT7         (0x00000080)
-#define MCF_INTC_IPRL_INT8         (0x00000100)
-#define MCF_INTC_IPRL_INT9         (0x00000200)
-#define MCF_INTC_IPRL_INT10        (0x00000400)
-#define MCF_INTC_IPRL_INT11        (0x00000800)
-#define MCF_INTC_IPRL_INT12        (0x00001000)
-#define MCF_INTC_IPRL_INT13        (0x00002000)
-#define MCF_INTC_IPRL_INT14        (0x00004000)
-#define MCF_INTC_IPRL_INT15        (0x00008000)
-#define MCF_INTC_IPRL_INT16        (0x00010000)
-#define MCF_INTC_IPRL_INT17        (0x00020000)
-#define MCF_INTC_IPRL_INT18        (0x00040000)
-#define MCF_INTC_IPRL_INT19        (0x00080000)
-#define MCF_INTC_IPRL_INT20        (0x00100000)
-#define MCF_INTC_IPRL_INT21        (0x00200000)
-#define MCF_INTC_IPRL_INT22        (0x00400000)
-#define MCF_INTC_IPRL_INT23        (0x00800000)
-#define MCF_INTC_IPRL_INT24        (0x01000000)
-#define MCF_INTC_IPRL_INT25        (0x02000000)
-#define MCF_INTC_IPRL_INT26        (0x04000000)
-#define MCF_INTC_IPRL_INT27        (0x08000000)
-#define MCF_INTC_IPRL_INT28        (0x10000000)
-#define MCF_INTC_IPRL_INT29        (0x20000000)
-#define MCF_INTC_IPRL_INT30        (0x40000000)
-#define MCF_INTC_IPRL_INT31        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRH */
-#define MCF_INTC_IMRH_INT_MASK32   (0x00000001)
-#define MCF_INTC_IMRH_INT_MASK33   (0x00000002)
-#define MCF_INTC_IMRH_INT_MASK34   (0x00000004)
-#define MCF_INTC_IMRH_INT_MASK35   (0x00000008)
-#define MCF_INTC_IMRH_INT_MASK36   (0x00000010)
-#define MCF_INTC_IMRH_INT_MASK37   (0x00000020)
-#define MCF_INTC_IMRH_INT_MASK38   (0x00000040)
-#define MCF_INTC_IMRH_INT_MASK39   (0x00000080)
-#define MCF_INTC_IMRH_INT_MASK40   (0x00000100)
-#define MCF_INTC_IMRH_INT_MASK41   (0x00000200)
-#define MCF_INTC_IMRH_INT_MASK42   (0x00000400)
-#define MCF_INTC_IMRH_INT_MASK43   (0x00000800)
-#define MCF_INTC_IMRH_INT_MASK44   (0x00001000)
-#define MCF_INTC_IMRH_INT_MASK45   (0x00002000)
-#define MCF_INTC_IMRH_INT_MASK46   (0x00004000)
-#define MCF_INTC_IMRH_INT_MASK47   (0x00008000)
-#define MCF_INTC_IMRH_INT_MASK48   (0x00010000)
-#define MCF_INTC_IMRH_INT_MASK49   (0x00020000)
-#define MCF_INTC_IMRH_INT_MASK50   (0x00040000)
-#define MCF_INTC_IMRH_INT_MASK51   (0x00080000)
-#define MCF_INTC_IMRH_INT_MASK52   (0x00100000)
-#define MCF_INTC_IMRH_INT_MASK53   (0x00200000)
-#define MCF_INTC_IMRH_INT_MASK54   (0x00400000)
-#define MCF_INTC_IMRH_INT_MASK55   (0x00800000)
-#define MCF_INTC_IMRH_INT_MASK56   (0x01000000)
-#define MCF_INTC_IMRH_INT_MASK57   (0x02000000)
-#define MCF_INTC_IMRH_INT_MASK58   (0x04000000)
-#define MCF_INTC_IMRH_INT_MASK59   (0x08000000)
-#define MCF_INTC_IMRH_INT_MASK60   (0x10000000)
-#define MCF_INTC_IMRH_INT_MASK61   (0x20000000)
-#define MCF_INTC_IMRH_INT_MASK62   (0x40000000)
-#define MCF_INTC_IMRH_INT_MASK63   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRL */
-#define MCF_INTC_IMRL_INT_MASK0    (0x00000001)
-#define MCF_INTC_IMRL_INT_MASK1    (0x00000002)
-#define MCF_INTC_IMRL_INT_MASK2    (0x00000004)
-#define MCF_INTC_IMRL_INT_MASK3    (0x00000008)
-#define MCF_INTC_IMRL_INT_MASK4    (0x00000010)
-#define MCF_INTC_IMRL_INT_MASK5    (0x00000020)
-#define MCF_INTC_IMRL_INT_MASK6    (0x00000040)
-#define MCF_INTC_IMRL_INT_MASK7    (0x00000080)
-#define MCF_INTC_IMRL_INT_MASK8    (0x00000100)
-#define MCF_INTC_IMRL_INT_MASK9    (0x00000200)
-#define MCF_INTC_IMRL_INT_MASK10   (0x00000400)
-#define MCF_INTC_IMRL_INT_MASK11   (0x00000800)
-#define MCF_INTC_IMRL_INT_MASK12   (0x00001000)
-#define MCF_INTC_IMRL_INT_MASK13   (0x00002000)
-#define MCF_INTC_IMRL_INT_MASK14   (0x00004000)
-#define MCF_INTC_IMRL_INT_MASK15   (0x00008000)
-#define MCF_INTC_IMRL_INT_MASK16   (0x00010000)
-#define MCF_INTC_IMRL_INT_MASK17   (0x00020000)
-#define MCF_INTC_IMRL_INT_MASK18   (0x00040000)
-#define MCF_INTC_IMRL_INT_MASK19   (0x00080000)
-#define MCF_INTC_IMRL_INT_MASK20   (0x00100000)
-#define MCF_INTC_IMRL_INT_MASK21   (0x00200000)
-#define MCF_INTC_IMRL_INT_MASK22   (0x00400000)
-#define MCF_INTC_IMRL_INT_MASK23   (0x00800000)
-#define MCF_INTC_IMRL_INT_MASK24   (0x01000000)
-#define MCF_INTC_IMRL_INT_MASK25   (0x02000000)
-#define MCF_INTC_IMRL_INT_MASK26   (0x04000000)
-#define MCF_INTC_IMRL_INT_MASK27   (0x08000000)
-#define MCF_INTC_IMRL_INT_MASK28   (0x10000000)
-#define MCF_INTC_IMRL_INT_MASK29   (0x20000000)
-#define MCF_INTC_IMRL_INT_MASK30   (0x40000000)
-#define MCF_INTC_IMRL_INT_MASK31   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCH */
-#define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
-#define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
-#define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
-#define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
-#define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
-#define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
-#define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
-#define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
-#define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
-#define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
-#define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
-#define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
-#define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
-#define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
-#define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
-#define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
-#define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
-#define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
-#define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
-#define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
-#define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
-#define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
-#define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
-#define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
-#define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
-#define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
-#define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
-#define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
-#define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
-#define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
-#define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
-#define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCL */
-#define MCF_INTC_INTFRCL_INTFRC0   (0x00000001)
-#define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
-#define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
-#define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
-#define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
-#define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
-#define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
-#define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
-#define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
-#define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
-#define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
-#define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
-#define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
-#define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
-#define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
-#define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
-#define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
-#define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
-#define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
-#define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
-#define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
-#define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
-#define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
-#define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
-#define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
-#define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
-#define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
-#define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
-#define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
-#define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
-#define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
-#define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_ICONFIG */
-#define MCF_INTC_ICONFIG_EMASK     (0x0020)
-#define MCF_INTC_ICONFIG_ELVLPRI1  (0x0200)
-#define MCF_INTC_ICONFIG_ELVLPRI2  (0x0400)
-#define MCF_INTC_ICONFIG_ELVLPRI3  (0x0800)
-#define MCF_INTC_ICONFIG_ELVLPRI4  (0x1000)
-#define MCF_INTC_ICONFIG_ELVLPRI5  (0x2000)
-#define MCF_INTC_ICONFIG_ELVLPRI6  (0x4000)
-#define MCF_INTC_ICONFIG_ELVLPRI7  (0x8000)
-
-/* Bit definitions and macros for MCF_INTC_SIMR */
-#define MCF_INTC_SIMR_SIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CIMR */
-#define MCF_INTC_CIMR_CIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CLMASK */
-#define MCF_INTC_CLMASK_CLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SLMASK */
-#define MCF_INTC_SLMASK_SLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_ICR */
-#define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SWIACK */
-#define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)
-
-/* Bit definitions and macros for MCF_INTC_LIACK */
-#define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)
-
-/********************************************************************/
-/*********************************************************************
-*
-* LCD Controller (LCDC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_LCDC_LSSAR                  MCF_REG32(0xFC0AC000)
-#define MCF_LCDC_LSR                    MCF_REG32(0xFC0AC004)
-#define MCF_LCDC_LVPWR                  MCF_REG32(0xFC0AC008)
-#define MCF_LCDC_LCPR                   MCF_REG32(0xFC0AC00C)
-#define MCF_LCDC_LCWHBR                 MCF_REG32(0xFC0AC010)
-#define MCF_LCDC_LCCMR                  MCF_REG32(0xFC0AC014)
-#define MCF_LCDC_LPCR                   MCF_REG32(0xFC0AC018)
-#define MCF_LCDC_LHCR                   MCF_REG32(0xFC0AC01C)
-#define MCF_LCDC_LVCR                   MCF_REG32(0xFC0AC020)
-#define MCF_LCDC_LPOR                   MCF_REG32(0xFC0AC024)
-#define MCF_LCDC_LSCR                   MCF_REG32(0xFC0AC028)
-#define MCF_LCDC_LPCCR                  MCF_REG32(0xFC0AC02C)
-#define MCF_LCDC_LDCR                   MCF_REG32(0xFC0AC030)
-#define MCF_LCDC_LRMCR                  MCF_REG32(0xFC0AC034)
-#define MCF_LCDC_LICR                   MCF_REG32(0xFC0AC038)
-#define MCF_LCDC_LIER                   MCF_REG32(0xFC0AC03C)
-#define MCF_LCDC_LISR                   MCF_REG32(0xFC0AC040)
-#define MCF_LCDC_LGWSAR                 MCF_REG32(0xFC0AC050)
-#define MCF_LCDC_LGWSR                  MCF_REG32(0xFC0AC054)
-#define MCF_LCDC_LGWVPWR                MCF_REG32(0xFC0AC058)
-#define MCF_LCDC_LGWPOR                 MCF_REG32(0xFC0AC05C)
-#define MCF_LCDC_LGWPR                  MCF_REG32(0xFC0AC060)
-#define MCF_LCDC_LGWCR                  MCF_REG32(0xFC0AC064)
-#define MCF_LCDC_LGWDCR                 MCF_REG32(0xFC0AC068)
-#define MCF_LCDC_BPLUT_BASE             MCF_REG32(0xFC0AC800)
-#define MCF_LCDC_GWLUT_BASE             MCF_REG32(0xFC0ACC00)
-
-/* Bit definitions and macros for MCF_LCDC_LSSAR */
-#define MCF_LCDC_LSSAR_SSA(x)           (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LSR */
-#define MCF_LCDC_LSR_YMAX(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LSR_XMAX(x)            (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LVPWR */
-#define MCF_LCDC_LVPWR_VPW(x)           (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LCPR */
-#define MCF_LCDC_LCPR_CYP(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LCPR_CXP(x)            (((x)&0x000003FF)<<16)
-#define MCF_LCDC_LCPR_OP                (0x10000000)
-#define MCF_LCDC_LCPR_CC(x)             (((x)&0x00000003)<<30)
-#define MCF_LCDC_LCPR_CC_TRANSPARENT    (0x00000000)
-#define MCF_LCDC_LCPR_CC_OR             (0x40000000)
-#define MCF_LCDC_LCPR_CC_XOR            (0x80000000)
-#define MCF_LCDC_LCPR_CC_AND            (0xC0000000)
-#define MCF_LCDC_LCPR_OP_ON             (0x10000000)
-#define MCF_LCDC_LCPR_OP_OFF            (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCWHBR */
-#define MCF_LCDC_LCWHBR_BD(x)           (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LCWHBR_CH(x)           (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LCWHBR_CW(x)           (((x)&0x0000001F)<<24)
-#define MCF_LCDC_LCWHBR_BK_EN           (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_ON        (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_OFF       (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCCMR */
-#define MCF_LCDC_LCCMR_CUR_COL_B(x)     (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LCCMR_CUR_COL_G(x)     (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LCCMR_CUR_COL_R(x)     (((x)&0x0000003F)<<12)
-
-/* Bit definitions and macros for MCF_LCDC_LPCR */
-#define MCF_LCDC_LPCR_PCD(x)            (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LPCR_SHARP             (0x00000040)
-#define MCF_LCDC_LPCR_SCLKSEL           (0x00000080)
-#define MCF_LCDC_LPCR_ACD(x)            (((x)&0x0000007F)<<8)
-#define MCF_LCDC_LPCR_ACDSEL            (0x00008000)
-#define MCF_LCDC_LPCR_REV_VS            (0x00010000)
-#define MCF_LCDC_LPCR_SWAP_SEL          (0x00020000)
-#define MCF_LCDC_LPCR_ENDSEL            (0x00040000)
-#define MCF_LCDC_LPCR_SCLKIDLE          (0x00080000)
-#define MCF_LCDC_LPCR_OEPOL             (0x00100000)
-#define MCF_LCDC_LPCR_CLKPOL            (0x00200000)
-#define MCF_LCDC_LPCR_LPPOL             (0x00400000)
-#define MCF_LCDC_LPCR_FLM               (0x00800000)
-#define MCF_LCDC_LPCR_PIXPOL            (0x01000000)
-#define MCF_LCDC_LPCR_BPIX(x)           (((x)&0x00000007)<<25)
-#define MCF_LCDC_LPCR_PBSIZ(x)          (((x)&0x00000003)<<28)
-#define MCF_LCDC_LPCR_COLOR             (0x40000000)
-#define MCF_LCDC_LPCR_TFT               (0x80000000)
-#define MCF_LCDC_LPCR_MODE_MONOCGROME   (0x00000000)
-#define MCF_LCDC_LPCR_MODE_CSTN         (0x40000000)
-#define MCF_LCDC_LPCR_MODE_TFT          (0xC0000000)
-#define MCF_LCDC_LPCR_PBSIZ_1           (0x00000000)
-#define MCF_LCDC_LPCR_PBSIZ_2           (0x10000000)
-#define MCF_LCDC_LPCR_PBSIZ_4           (0x20000000)
-#define MCF_LCDC_LPCR_PBSIZ_8           (0x30000000)
-#define MCF_LCDC_LPCR_BPIX_1bpp         (0x00000000)
-#define MCF_LCDC_LPCR_BPIX_2bpp         (0x02000000)
-#define MCF_LCDC_LPCR_BPIX_4bpp         (0x04000000)
-#define MCF_LCDC_LPCR_BPIX_8bpp         (0x06000000)
-#define MCF_LCDC_LPCR_BPIX_12bpp        (0x08000000)
-#define MCF_LCDC_LPCR_BPIX_16bpp        (0x0A000000)
-#define MCF_LCDC_LPCR_BPIX_18bpp        (0x0C000000)
-
-#define MCF_LCDC_LPCR_PANEL_TYPE(x)     (((x)&0x00000003)<<30) 
-
-/* Bit definitions and macros for MCF_LCDC_LHCR */
-#define MCF_LCDC_LHCR_H_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LHCR_H_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LHCR_H_WIDTH(x)        (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LVCR */
-#define MCF_LCDC_LVCR_V_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LVCR_V_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LVCR_V_WIDTH(x)      (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LPOR */
-#define MCF_LCDC_LPOR_POS(x)            (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LPCCR */
-#define MCF_LCDC_LPCCR_PW(x)            (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LPCCR_CC_EN            (0x00000100)
-#define MCF_LCDC_LPCCR_SCR(x)           (((x)&0x00000003)<<9)
-#define MCF_LCDC_LPCCR_LDMSK            (0x00008000)
-#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x)  (((x)&0x000001FF)<<16)
-#define MCF_LCDC_LPCCR_SCR_LINEPULSE    (0x00000000)
-#define MCF_LCDC_LPCCR_SCR_PIXELCLK     (0x00002000)
-#define MCF_LCDC_LPCCR_SCR_LCDCLOCK     (0x00004000)
-
-/* Bit definitions and macros for MCF_LCDC_LDCR */
-#define MCF_LCDC_LDCR_TM(x)             (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LDCR_HM(x)             (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LDCR_BURST             (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LRMCR */
-#define MCF_LCDC_LRMCR_SEL_REF          (0x00000001)
-
-/* Bit definitions and macros for MCF_LCDC_LICR */
-#define MCF_LCDC_LICR_INTCON            (0x00000001)
-#define MCF_LCDC_LICR_INTSYN            (0x00000004)
-#define MCF_LCDC_LICR_GW_INT_CON        (0x00000010)
-
-/* Bit definitions and macros for MCF_LCDC_LIER */
-#define MCF_LCDC_LIER_BOF_EN            (0x00000001)
-#define MCF_LCDC_LIER_EOF_EN            (0x00000002)
-#define MCF_LCDC_LIER_ERR_RES_EN        (0x00000004)
-#define MCF_LCDC_LIER_UDR_ERR_EN        (0x00000008)
-#define MCF_LCDC_LIER_GW_BOF_EN         (0x00000010)
-#define MCF_LCDC_LIER_GW_EOF_EN         (0x00000020)
-#define MCF_LCDC_LIER_GW_ERR_RES_EN     (0x00000040)
-#define MCF_LCDC_LIER_GW_UDR_ERR_EN     (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LISR */
-#define MCF_LCDC_LISR_BOF               (0x00000001)
-#define MCF_LCDC_LISR_EOF               (0x00000002)
-#define MCF_LCDC_LISR_ERR_RES           (0x00000004)
-#define MCF_LCDC_LISR_UDR_ERR           (0x00000008)
-#define MCF_LCDC_LISR_GW_BOF            (0x00000010)
-#define MCF_LCDC_LISR_GW_EOF            (0x00000020)
-#define MCF_LCDC_LISR_GW_ERR_RES        (0x00000040)
-#define MCF_LCDC_LISR_GW_UDR_ERR        (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSAR */
-#define MCF_LCDC_LGWSAR_GWSA(x)         (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSR */
-#define MCF_LCDC_LGWSR_GWH(x)           (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWSR_GWW(x)           (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
-#define MCF_LCDC_LGWVPWR_GWVPW(x)       (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPOR */
-#define MCF_LCDC_LGWPOR_GWPO(x)         (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPR */
-#define MCF_LCDC_LGWPR_GWYP(x)          (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWPR_GWXP(x)          (((x)&0x000003FF)<<16)
-
-/* Bit definitions and macros for MCF_LCDC_LGWCR */
-#define MCF_LCDC_LGWCR_GWCKB(x)         (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LGWCR_GWCKG(x)         (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LGWCR_GWCKR(x)         (((x)&0x0000003F)<<12)
-#define MCF_LCDC_LGWCR_GW_RVS           (0x00200000)
-#define MCF_LCDC_LGWCR_GWE              (0x00400000)
-#define MCF_LCDC_LGWCR_GWCKE            (0x00800000)
-#define MCF_LCDC_LGWCR_GWAV(x)          (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_LCDC_LGWDCR */
-#define MCF_LCDC_LGWDCR_GWTM(x)         (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LGWDCR_GWHM(x)         (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LGWDCR_GWBT            (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LSCR */
-#define MCF_LCDC_LSCR_PS_RISE_DELAY(x)    (((x)&0x0000003F)<<26)
-#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x)   (((x)&0x000000FF)<<16)
-#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
-#define MCF_LCDC_LSCR_GRAY_2(x)                   (((x)&0x0000000F)<<4)
-#define MCF_LCDC_LSCR_GRAY_1(x)                   (((x)&0x0000000F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
-#define MCF_LCDC_BPLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
-#define MCF_LCDC_GWLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
 /*********************************************************************
  *
  * Phase Locked Loop (PLL)
@@ -1925,10 +1107,10 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_PLL_PODR              MCF_REG08(0xFC0C0000)
-#define MCF_PLL_PLLCR             MCF_REG08(0xFC0C0004)
-#define MCF_PLL_PMDR              MCF_REG08(0xFC0C0008)
-#define MCF_PLL_PFDR              MCF_REG08(0xFC0C000C)
+#define MCF_PLL_PODR              0xFC0C0000
+#define MCF_PLL_PLLCR             0xFC0C0004
+#define MCF_PLL_PMDR              0xFC0C0008
+#define MCF_PLL_PFDR              0xFC0C000C
 
 /* Bit definitions and macros for MCF_PLL_PODR */
 #define MCF_PLL_PODR_BUSDIV(x)    (((x)&0x0F)<<0)
@@ -1951,15 +1133,15 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SCM_MPR                     MCF_REG32(0xFC000000)
-#define MCF_SCM_PACRA                   MCF_REG32(0xFC000020)
-#define MCF_SCM_PACRB                   MCF_REG32(0xFC000024)
-#define MCF_SCM_PACRC                   MCF_REG32(0xFC000028)
-#define MCF_SCM_PACRD                   MCF_REG32(0xFC00002C)
-#define MCF_SCM_PACRE                   MCF_REG32(0xFC000040)
-#define MCF_SCM_PACRF                   MCF_REG32(0xFC000044)
+#define MCF_SCM_MPR                     0xFC000000
+#define MCF_SCM_PACRA                   0xFC000020
+#define MCF_SCM_PACRB                   0xFC000024
+#define MCF_SCM_PACRC                   0xFC000028
+#define MCF_SCM_PACRD                   0xFC00002C
+#define MCF_SCM_PACRE                   0xFC000040
+#define MCF_SCM_PACRF                   0xFC000044
 
-#define MCF_SCM_BCR                     MCF_REG32(0xFC040024)
+#define MCF_SCM_BCR                     0xFC040024
 
 /*********************************************************************
  *
@@ -1968,17 +1150,16 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SDRAMC_SDMR                 MCF_REG32(0xFC0B8000)
-#define MCF_SDRAMC_SDCR                 MCF_REG32(0xFC0B8004)
-#define MCF_SDRAMC_SDCFG1               MCF_REG32(0xFC0B8008)
-#define MCF_SDRAMC_SDCFG2               MCF_REG32(0xFC0B800C)
-#define MCF_SDRAMC_LIMP_FIX             MCF_REG32(0xFC0B8080)
-#define MCF_SDRAMC_SDDS                 MCF_REG32(0xFC0B8100)
-#define MCF_SDRAMC_SDCS0                MCF_REG32(0xFC0B8110)
-#define MCF_SDRAMC_SDCS1                MCF_REG32(0xFC0B8114)
-#define MCF_SDRAMC_SDCS2                MCF_REG32(0xFC0B8118)
-#define MCF_SDRAMC_SDCS3                MCF_REG32(0xFC0B811C)
-#define MCF_SDRAMC_SDCS(x)              MCF_REG32(0xFC0B8110+((x)*0x004))
+#define MCF_SDRAMC_SDMR                 0xFC0B8000
+#define MCF_SDRAMC_SDCR                 0xFC0B8004
+#define MCF_SDRAMC_SDCFG1               0xFC0B8008
+#define MCF_SDRAMC_SDCFG2               0xFC0B800C
+#define MCF_SDRAMC_LIMP_FIX             0xFC0B8080
+#define MCF_SDRAMC_SDDS                 0xFC0B8100
+#define MCF_SDRAMC_SDCS0                0xFC0B8110
+#define MCF_SDRAMC_SDCS1                0xFC0B8114
+#define MCF_SDRAMC_SDCS2                0xFC0B8118
+#define MCF_SDRAMC_SDCS3                0xFC0B811C
 
 /* Bit definitions and macros for MCF_SDRAMC_SDMR */
 #define MCF_SDRAMC_SDMR_CMD             (0x00010000)
@@ -2046,143 +1227,9 @@
 #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE     (0x0000001E)
 #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE     (0x0000001F)
 
-/*********************************************************************
- *
- *      FlexCAN module registers
- *
- *********************************************************************/
-#define MCF_FLEXCAN_BASEADDR(x)         (0xFC020000+(x)*0x0800)
-#define MCF_FLEXCAN_CANMCR(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x00)
-#define MCF_FLEXCAN_CANCTRL(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x04)
-#define MCF_FLEXCAN_TIMER(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x08)
-#define MCF_FLEXCAN_RXGMASK(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x10)
-#define MCF_FLEXCAN_RX14MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x14)
-#define MCF_FLEXCAN_RX15MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x18)
-#define MCF_FLEXCAN_ERRCNT(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
-#define MCF_FLEXCAN_ERRSTAT(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x20)
-#define MCF_FLEXCAN_IMASK(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x28)
-#define MCF_FLEXCAN_IFLAG(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x30)
-
-#define MCF_FLEXCAN_MB_CNT(x,y)         MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
-#define MCF_FLEXCAN_MB_ID(x,y)          MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
-#define MCF_FLEXCAN_MB_DB(x,y,z)        MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
-
-/*
- *      FlexCAN Module Configuration Register
- */
-#define CANMCR_MDIS             (0x80000000)
-#define CANMCR_FRZ              (0x40000000)
-#define CANMCR_HALT             (0x10000000)
-#define CANMCR_SOFTRST          (0x02000000)
-#define CANMCR_FRZACK           (0x01000000)
-#define CANMCR_SUPV             (0x00800000)
-#define CANMCR_MAXMB(x)         ((x)&0x0F)
-
-/*
- *      FlexCAN Control Register
- */
-#define CANCTRL_PRESDIV(x)      (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)          (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)        (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)        (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK         (0x00008000)
-#define CANCTRL_ERRMSK          (0x00004000)
-#define CANCTRL_CLKSRC          (0x00002000)
-#define CANCTRL_LPB             (0x00001000)
-#define CANCTRL_SAMP            (0x00000080)
-#define CANCTRL_BOFFREC         (0x00000040)
-#define CANCTRL_TSYNC           (0x00000020)
-#define CANCTRL_LBUF            (0x00000010)
-#define CANCTRL_LOM             (0x00000008)
-#define CANCTRL_PROPSEG(x)      ((x)&0x07)
-
-/*
- *      FlexCAN Error Counter Register
- */
-#define ERRCNT_RXECTR(x)        (((x)&0xFF)<<8)
-#define ERRCNT_TXECTR(x)        ((x)&0xFF)
-
-/*
- *      FlexCAN Error and Status Register
- */
-#define ERRSTAT_BITERR(x)       (((x)&0x03)<<14)
-#define ERRSTAT_ACKERR           (0x00002000)
-#define ERRSTAT_CRCERR           (0x00001000)
-#define ERRSTAT_FRMERR           (0x00000800)
-#define ERRSTAT_STFERR           (0x00000400)
-#define ERRSTAT_TXWRN            (0x00000200)
-#define ERRSTAT_RXWRN            (0x00000100)
-#define ERRSTAT_IDLE             (0x00000080)
-#define ERRSTAT_TXRX             (0x00000040)
-#define ERRSTAT_FLTCONF(x)       (((x)&0x03)<<4)
-#define ERRSTAT_BOFFINT          (0x00000004)
-#define ERRSTAT_ERRINT           (0x00000002)
-
 /*
- *      Interrupt Mask Register
- */
-#define IMASK_BUF15M            (0x8000)
-#define IMASK_BUF14M            (0x4000)
-#define IMASK_BUF13M            (0x2000)
-#define IMASK_BUF12M            (0x1000)
-#define IMASK_BUF11M            (0x0800)
-#define IMASK_BUF10M            (0x0400)
-#define IMASK_BUF9M             (0x0200)
-#define IMASK_BUF8M             (0x0100)
-#define IMASK_BUF7M             (0x0080)
-#define IMASK_BUF6M             (0x0040)
-#define IMASK_BUF5M             (0x0020)
-#define IMASK_BUF4M             (0x0010)
-#define IMASK_BUF3M             (0x0008)
-#define IMASK_BUF2M             (0x0004)
-#define IMASK_BUF1M             (0x0002)
-#define IMASK_BUF0M             (0x0001)
-#define IMASK_BUFnM(x)          (0x1<<(x))
-#define IMASK_BUFF_ENABLE_ALL   (0x1111)
-#define IMASK_BUFF_DISABLE_ALL  (0x0000)
-
-/*
- *      Interrupt Flag Register
- */
-#define IFLAG_BUF15M            (0x8000)
-#define IFLAG_BUF14M            (0x4000)
-#define IFLAG_BUF13M            (0x2000)
-#define IFLAG_BUF12M            (0x1000)
-#define IFLAG_BUF11M            (0x0800)
-#define IFLAG_BUF10M            (0x0400)
-#define IFLAG_BUF9M             (0x0200)
-#define IFLAG_BUF8M             (0x0100)
-#define IFLAG_BUF7M             (0x0080)
-#define IFLAG_BUF6M             (0x0040)
-#define IFLAG_BUF5M             (0x0020)
-#define IFLAG_BUF4M             (0x0010)
-#define IFLAG_BUF3M             (0x0008)
-#define IFLAG_BUF2M             (0x0004)
-#define IFLAG_BUF1M             (0x0002)
-#define IFLAG_BUF0M             (0x0001)
-#define IFLAG_BUFF_SET_ALL      (0xFFFF)
-#define IFLAG_BUFF_CLEAR_ALL    (0x0000)
-#define IFLAG_BUFnM(x)          (0x1<<(x))
-
-/*
- *      Message Buffers
- */
-#define MB_CNT_CODE(x)          (((x)&0x0F)<<24)
-#define MB_CNT_SRR              (0x00400000)
-#define MB_CNT_IDE              (0x00200000)
-#define MB_CNT_RTR              (0x00100000)
-#define MB_CNT_LENGTH(x)        (((x)&0x0F)<<16)
-#define MB_CNT_TIMESTAMP(x)     ((x)&0xFFFF)
-#define MB_ID_STD(x)            (((x)&0x07FF)<<18)
-#define MB_ID_EXT(x)            ((x)&0x3FFFF)
-
-/*********************************************************************
- *
  * Edge Port Module (EPORT)
- *
- *********************************************************************/
-
-/* Register read/write macros */
+ */
 #define MCFEPORT_EPPAR                (0xFC094000)
 #define MCFEPORT_EPDDR                (0xFC094002)
 #define MCFEPORT_EPIER                (0xFC094003)
@@ -2190,91 +1237,5 @@
 #define MCFEPORT_EPPDR                (0xFC094005)
 #define MCFEPORT_EPFR                 (0xFC094006)
 
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x)       (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x)       (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x)       (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x)       (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x)       (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x)       (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x)       (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_LEVEL          (0)
-#define MCF_EPORT_EPPAR_RISING         (1)
-#define MCF_EPORT_EPPAR_FALLING        (2)
-#define MCF_EPORT_EPPAR_BOTH           (3)
-#define MCF_EPORT_EPPAR_EPPA7_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA7_RISING   (0x4000)
-#define MCF_EPORT_EPPAR_EPPA7_FALLING  (0x8000)
-#define MCF_EPORT_EPPAR_EPPA7_BOTH     (0xC000)
-#define MCF_EPORT_EPPAR_EPPA6_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA6_RISING   (0x1000)
-#define MCF_EPORT_EPPAR_EPPA6_FALLING  (0x2000)
-#define MCF_EPORT_EPPAR_EPPA6_BOTH     (0x3000)
-#define MCF_EPORT_EPPAR_EPPA5_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA5_RISING   (0x0400)
-#define MCF_EPORT_EPPAR_EPPA5_FALLING  (0x0800)
-#define MCF_EPORT_EPPAR_EPPA5_BOTH     (0x0C00)
-#define MCF_EPORT_EPPAR_EPPA4_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA4_RISING   (0x0100)
-#define MCF_EPORT_EPPAR_EPPA4_FALLING  (0x0200)
-#define MCF_EPORT_EPPAR_EPPA4_BOTH     (0x0300)
-#define MCF_EPORT_EPPAR_EPPA3_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA3_RISING   (0x0040)
-#define MCF_EPORT_EPPAR_EPPA3_FALLING  (0x0080)
-#define MCF_EPORT_EPPAR_EPPA3_BOTH     (0x00C0)
-#define MCF_EPORT_EPPAR_EPPA2_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA2_RISING   (0x0010)
-#define MCF_EPORT_EPPAR_EPPA2_FALLING  (0x0020)
-#define MCF_EPORT_EPPAR_EPPA2_BOTH     (0x0030)
-#define MCF_EPORT_EPPAR_EPPA1_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA1_RISING   (0x0004)
-#define MCF_EPORT_EPPAR_EPPA1_FALLING  (0x0008)
-#define MCF_EPORT_EPPAR_EPPA1_BOTH     (0x000C)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1          (0x02)
-#define MCF_EPORT_EPDDR_EPDD2          (0x04)
-#define MCF_EPORT_EPDDR_EPDD3          (0x08)
-#define MCF_EPORT_EPDDR_EPDD4          (0x10)
-#define MCF_EPORT_EPDDR_EPDD5          (0x20)
-#define MCF_EPORT_EPDDR_EPDD6          (0x40)
-#define MCF_EPORT_EPDDR_EPDD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1          (0x02)
-#define MCF_EPORT_EPIER_EPIE2          (0x04)
-#define MCF_EPORT_EPIER_EPIE3          (0x08)
-#define MCF_EPORT_EPIER_EPIE4          (0x10)
-#define MCF_EPORT_EPIER_EPIE5          (0x20)
-#define MCF_EPORT_EPIER_EPIE6          (0x40)
-#define MCF_EPORT_EPIER_EPIE7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1            (0x02)
-#define MCF_EPORT_EPDR_EPD2            (0x04)
-#define MCF_EPORT_EPDR_EPD3            (0x08)
-#define MCF_EPORT_EPDR_EPD4            (0x10)
-#define MCF_EPORT_EPDR_EPD5            (0x20)
-#define MCF_EPORT_EPDR_EPD6            (0x40)
-#define MCF_EPORT_EPDR_EPD7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1          (0x02)
-#define MCF_EPORT_EPPDR_EPPD2          (0x04)
-#define MCF_EPORT_EPPDR_EPPD3          (0x08)
-#define MCF_EPORT_EPPDR_EPPD4          (0x10)
-#define MCF_EPORT_EPPDR_EPPD5          (0x20)
-#define MCF_EPORT_EPPDR_EPPD6          (0x40)
-#define MCF_EPORT_EPPDR_EPPD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1            (0x02)
-#define MCF_EPORT_EPFR_EPF2            (0x04)
-#define MCF_EPORT_EPFR_EPF3            (0x08)
-#define MCF_EPORT_EPFR_EPF4            (0x10)
-#define MCF_EPORT_EPFR_EPF5            (0x20)
-#define MCF_EPORT_EPFR_EPF6            (0x40)
-#define MCF_EPORT_EPFR_EPF7            (0x80)
-
 /********************************************************************/
 #endif  /* m532xsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 79f58dd6a83d..a7550bc5cd1e 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -23,55 +23,55 @@
 /*
  *      Define the 5407 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xbc)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc0)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xc8)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xcc)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xd4)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xd8)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
@@ -102,9 +102,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 16
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         16
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
 
 /*
  *      Some symbol defines for the above...
@@ -130,9 +130,9 @@
 /*
  *       Defines for the IRQPAR Register
  */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
+#define IRQ5_LEVEL4             0x80
+#define IRQ3_LEVEL6             0x40
+#define IRQ1_LEVEL2             0x20
 
 /*
  *      Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index df75dd87ae7a..0b69cd1ed0ed 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
 *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_GPT_GMS0       0x000800
-#define MCF_GPT_GCIR0      0x000804
-#define MCF_GPT_GPWM0      0x000808
-#define MCF_GPT_GSR0       0x00080C
-#define MCF_GPT_GMS1       0x000810
-#define MCF_GPT_GCIR1      0x000814
-#define MCF_GPT_GPWM1      0x000818
-#define MCF_GPT_GSR1       0x00081C
-#define MCF_GPT_GMS2       0x000820
-#define MCF_GPT_GCIR2      0x000824
-#define MCF_GPT_GPWM2      0x000828
-#define MCF_GPT_GSR2       0x00082C
-#define MCF_GPT_GMS3       0x000830
-#define MCF_GPT_GCIR3      0x000834
-#define MCF_GPT_GPWM3      0x000838
-#define MCF_GPT_GSR3       0x00083C
-#define MCF_GPT_GMS(x)     (0x000800+((x)*0x010))
-#define MCF_GPT_GCIR(x)    (0x000804+((x)*0x010))
-#define MCF_GPT_GPWM(x)    (0x000808+((x)*0x010))
-#define MCF_GPT_GSR(x)     (0x00080C+((x)*0x010))
+#define MCF_GPT_GMS0       (MCF_MBAR + 0x000800)
+#define MCF_GPT_GCIR0      (MCF_MBAR + 0x000804)
+#define MCF_GPT_GPWM0      (MCF_MBAR + 0x000808)
+#define MCF_GPT_GSR0       (MCF_MBAR + 0x00080C)
+#define MCF_GPT_GMS1       (MCF_MBAR + 0x000810)
+#define MCF_GPT_GCIR1      (MCF_MBAR + 0x000814)
+#define MCF_GPT_GPWM1      (MCF_MBAR + 0x000818)
+#define MCF_GPT_GSR1       (MCF_MBAR + 0x00081C)
+#define MCF_GPT_GMS2       (MCF_MBAR + 0x000820)
+#define MCF_GPT_GCIR2      (MCF_MBAR + 0x000824)
+#define MCF_GPT_GPWM2      (MCF_MBAR + 0x000828)
+#define MCF_GPT_GSR2       (MCF_MBAR + 0x00082C)
+#define MCF_GPT_GMS3       (MCF_MBAR + 0x000830)
+#define MCF_GPT_GCIR3      (MCF_MBAR + 0x000834)
+#define MCF_GPT_GPWM3      (MCF_MBAR + 0x000838)
+#define MCF_GPT_GSR3       (MCF_MBAR + 0x00083C)
+#define MCF_GPT_GMS(x)     (MCF_MBAR + 0x000800 + ((x) * 0x010))
+#define MCF_GPT_GCIR(x)    (MCF_MBAR + 0x000804 + ((x) * 0x010))
+#define MCF_GPT_GPWM(x)    (MCF_MBAR + 0x000808 + ((x) * 0x010))
+#define MCF_GPT_GSR(x)     (MCF_MBAR + 0x00080C + ((x) * 0x010))
 
 /* Bit definitions and macros for MCF_GPT_GMS */
 #define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d3c5e0dbdadf..d3bd83887429 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -47,6 +47,12 @@
 #define MCF_IRQ_UART3           (MCFINT_VECBASE + 32)
 
 /*
+ *      Slice Timer support.
+ */
+#define MCFSLT_TIMER0           (MCF_MBAR + 0x900)      /* Base addr TIMER0 */
+#define MCFSLT_TIMER1           (MCF_MBAR + 0x910)      /* Base addr TIMER1 */
+
+/*
  *      Generic GPIO support
  */
 #define MCFGPIO_PIN_MAX         0       /* I am too lazy to count */
@@ -64,15 +70,25 @@
 #define MCFEPORT_EPFR           (MCF_MBAR + 0xf0c)      /* Flags */
 
 /*
- *      Some PSC related definitions
+ *      Pin Assignment register definitions
  */
-#define MCF_PAR_PSC(x)          (0x000A4F-((x)&0x3))
+#define MCFGPIO_PAR_FBCTL       (MCF_MBAR + 0xA40)
+#define MCFGPIO_PAR_FBCS        (MCF_MBAR + 0xA42)
+#define MCFGPIO_PAR_DMA         (MCF_MBAR + 0xA43)
+#define MCFGPIO_PAR_FECI2CIRQ   (MCF_MBAR + 0xA44)
+#define MCFGPIO_PAR_PCIBG       (MCF_MBAR + 0xA48)      /* PCI bus grant */
+#define MCFGPIO_PAR_PCIBR       (MCF_MBAR + 0xA4A)      /* PCI */
+#define MCFGPIO_PAR_PSC0        (MCF_MBAR + 0xA4F)
+#define MCFGPIO_PAR_PSC1        (MCF_MBAR + 0xA4E)
+#define MCFGPIO_PAR_PSC2        (MCF_MBAR + 0xA4D)
+#define MCFGPIO_PAR_PSC3        (MCF_MBAR + 0xA4C)
+#define MCFGPIO_PAR_DSPI        (MCF_MBAR + 0xA50)
+#define MCFGPIO_PAR_TIMER       (MCF_MBAR + 0xA52)
+
 #define MCF_PAR_SDA             (0x0008)
 #define MCF_PAR_SCL             (0x0004)
 #define MCF_PAR_PSC_TXD         (0x04)
 #define MCF_PAR_PSC_RXD         (0x08)
-#define MCF_PAR_PSC_RTS(x)      (((x)&0x03)<<4)
-#define MCF_PAR_PSC_CTS(x)      (((x)&0x03)<<6)
 #define MCF_PAR_PSC_CTS_GPIO    (0x00)
 #define MCF_PAR_PSC_CTS_BCLK    (0x80)
 #define MCF_PAR_PSC_CTS_CTS     (0xC0)
@@ -81,7 +97,4 @@
 #define MCF_PAR_PSC_RTS_RTS     (0x30)
 #define MCF_PAR_PSC_CANRX       (0x40)
 
-#define MCF_PAR_PCIBG           (CONFIG_MBAR + 0xa48)   /* PCI bus grant */
-#define MCF_PAR_PCIBR           (CONFIG_MBAR + 0xa4a)   /* PCI */
-
 #endif  /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
index d0d0ecba5333..c2314b6f8caa 100644
--- a/arch/m68k/include/asm/mcfslt.h
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -13,13 +13,6 @@
 /****************************************************************************/
 
 /*
- *      Get address specific defines for the 547x.
- */
-#define MCFSLT_TIMER0           0x900   /* Base address of TIMER0 */
-#define MCFSLT_TIMER1           0x910   /* Base address of TIMER1 */
-
-
-/*
  *      Define the SLT timer register set addresses.
  */
 #define MCFSLT_STCNT            0x00    /* Terminal count */
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 4dec2d9fb994..2a7a7667d807 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -21,6 +21,7 @@
 #ifdef CONFIG_COLDFIRE
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/io.h>
 #endif
 
 /*---------------------------------------------------------------------------*/
@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
  */
 static __inline__ unsigned int mcf_getppdata(void)
 {
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        return((unsigned int) *pp);
+        return readw(MCFSIM_PBDAT);
 }
 
 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
 {
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        *pp = (*pp & ~mask) | bits;
+        write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
 }
 #endif
 
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
index a49d75e65489..816674164682 100644
--- a/arch/m68k/platform/68VZ328/Makefile
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -1,11 +1,5 @@
 #
-# Makefile for arch/m68knommu/platform/68VZ328.
+# Makefile for arch/m68k/platform/68VZ328.
 #
 
 obj-y           := config.o
-extra-$(DRAGEN2):= screen.h
-
-$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
-        perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
-
-clean-files := $(obj)/screen.h
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 81f0fb5e51cf..71ea4c02795d 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
 {
 #ifdef MCFUART_UIVR
         /* UART0 interrupt setup */
-        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
         writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
         mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
 
         /* UART1 interrupt setup */
-        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
         writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
         mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
 #endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index b88f5716f357..fa31be297b85 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -60,7 +60,7 @@
 
 #elif defined(CONFIG_M5272)
 .macro GET_MEM_SIZE
-        movel   MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
+        movel   MCFSIM_CSOR7,%d0        /* get SDRAM address mask */
         andil   #0xfffff000,%d0         /* mask out chip select options */
         negl    %d0                     /* negate bits */
 .endm
diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c
index f343bf7bf5b0..0864b836699a 100644
--- a/arch/m68k/platform/coldfire/intc-5249.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
@@ -20,22 +20,22 @@
 static void intc2_irq_gpio_mask(struct irq_data *d)
 {
         u32 imr;
-        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr = readl(MCFSIM2_GPIOINTENABLE);
         imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
-        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
 }
 
 static void intc2_irq_gpio_unmask(struct irq_data *d)
 {
         u32 imr;
-        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr = readl(MCFSIM2_GPIOINTENABLE);
         imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
-        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
 }
 
 static void intc2_irq_gpio_ack(struct irq_data *d)
 {
-        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
+        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
 }
 
 static struct irq_chip intc2_irq_gpio_chip = {
diff --git a/arch/m68k/platform/coldfire/intc-5272.c b/arch/m68k/platform/coldfire/intc-5272.c
index 7160e618b0a9..d7b695629a7e 100644
--- a/arch/m68k/platform/coldfire/intc-5272.c
+++ b/arch/m68k/platform/coldfire/intc-5272.c
@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
                 u32 v;
                 irq -= MCFINT_VECBASE;
                 v = 0x8 << intc_irqmap[irq].index;
-                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                writel(v, intc_irqmap[irq].icr);
         }
 }
 
@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
                 u32 v;
                 irq -= MCFINT_VECBASE;
                 v = 0xd << intc_irqmap[irq].index;
-                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                writel(v, intc_irqmap[irq].icr);
         }
 }
 
@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
                 irq -= MCFINT_VECBASE;
                 if (intc_irqmap[irq].ack) {
                         u32 v;
-                        v = readl(MCF_MBAR + intc_irqmap[irq].icr);
+                        v = readl(intc_irqmap[irq].icr);
                         v &= (0x7 << intc_irqmap[irq].index);
                         v |= (0x8 << intc_irqmap[irq].index);
-                        writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                        writel(v, intc_irqmap[irq].icr);
                 }
         }
 }
@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
                 irq -= MCFINT_VECBASE;
                 if (intc_irqmap[irq].ack) {
                         u32 v;
-                        v = readl(MCF_MBAR + MCFSIM_PITR);
+                        v = readl(MCFSIM_PITR);
                         if (type == IRQ_TYPE_EDGE_FALLING)
                                 v &= ~(0x1 << (32 - irq));
                         else
                                 v |= (0x1 << (32 - irq));
-                        writel(v, MCF_MBAR + MCFSIM_PITR);
+                        writel(v, MCFSIM_PITR);
                 }
         }
         return 0;
@@ -163,10 +163,10 @@ void __init init_IRQ(void)
         int irq, edge;
 
         /* Mask all interrupt sources */
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
+        writel(0x88888888, MCFSIM_ICR1);
+        writel(0x88888888, MCFSIM_ICR2);
+        writel(0x88888888, MCFSIM_ICR3);
+        writel(0x88888888, MCFSIM_ICR4);
 
         for (irq = 0; (irq < NR_IRQS); irq++) {
                 irq_set_chip(irq, &intc_irq_chip);
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index 5c0c150b4067..cce257420388 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
 void mcf_setimr(int index)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-        __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
+        __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-        __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
+        __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
         imr |= mask;
-        __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
+        __raw_writew(imr, MCFSIM_IMR);
 }
 
 #else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
 void mcf_setimr(int index)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-        __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
+        __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-        __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
+        __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
         imr |= mask;
-        __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
+        __raw_writel(imr, MCFSIM_IMR);
 }
 
 #endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
 #ifdef MCFSIM_AVR
         if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
                 u8 avec;
-                avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
+                avec = __raw_readb(MCFSIM_AVR);
                 avec |= (0x1 << (irq - EIRQ1 + 1));
-                __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
+                __raw_writeb(avec, MCFSIM_AVR);
         }
 #endif
 }
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index d47dfd8f50a2..ff37fe9553ea 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void)
 
 static void __init m523x_fec_init(void)
 {
-        u16 par;
-        u8 v;
-
         /* Set multi-function pins to ethernet use */
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100078);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+        writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index 300e729a58d0..23b19cb7ab50 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void)
 {
         /* QSPI irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
-               MCF_MBAR + MCFSIM_QSPIICR);
+               MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 }
 
@@ -72,11 +72,11 @@ static void __init m5249_smc91x_init(void)
         u32  gpio;
 
         /* Set the GPIO line as interrupt source for smc91x device */
-        gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
-        writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        gpio = readl(MCFSIM2_GPIOINTENABLE);
+        writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
 
-        gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
-        writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
+        gpio = readl(MCFSIM2_INTLEVEL5);
+        writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
 }
 
 #endif /* CONFIG_M5249C3 */
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
index 8ce905f9b84f..fce8f8a45bf0 100644
--- a/arch/m68k/platform/coldfire/m525x.c
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void)
 
         /* QSPI irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
-               MCF_MBAR + MCFSIM_QSPIICR);
+               MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 }
@@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void)
 
         /* first I2C controller uses regular irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
-                        MCF_MBAR + MCFSIM_I2CICR);
+                MCFSIM_I2CICR);
         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
 
         /* second I2C controller is completely different */
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index e68bc7a148eb..45b246d052ef 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void)
         u32 v;
 
         /* Enable the output lines for the serial ports */
-        v = readl(MCF_MBAR + MCFSIM_PBCNT);
+        v = readl(MCFSIM_PBCNT);
         v = (v & ~0x000000ff) | 0x00000055;
-        writel(v, MCF_MBAR + MCFSIM_PBCNT);
+        writel(v, MCFSIM_PBCNT);
 
-        v = readl(MCF_MBAR + MCFSIM_PDCNT);
+        v = readl(MCFSIM_PDCNT);
         v = (v & ~0x000003fc) | 0x000002a8;
-        writel(v, MCF_MBAR + MCFSIM_PDCNT);
+        writel(v, MCFSIM_PDCNT);
 }
 
 /***************************************************************************/
@@ -50,9 +50,9 @@ static void m5272_cpu_reset(void)
 {
         local_irq_disable();
         /* Set watchdog to reset, and enabled */
-        __raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
-        __raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
-        __raw_writew(0, MCF_MBAR + MCFSIM_WCR);
+        __raw_writew(0, MCFSIM_WIRR);
+        __raw_writew(1, MCFSIM_WRRR);
+        __raw_writew(0, MCFSIM_WCR);
         for (;;)
                 /* wait for watchdog to timeout */;
 }
@@ -62,11 +62,8 @@ static void m5272_cpu_reset(void)
 void __init config_BSP(char *commandp, int size)
 {
 #if defined (CONFIG_MOD5272)
-        volatile unsigned char  *pivrp;
-
         /* Set base of device vectors to be 64 */
-        pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
-        *pivrp = 0x40;
+        writeb(0x40, MCFSIM_PIVR);
 #endif
 
 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index b3cb378c5e94..1431ba03c602 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
         /*
          * External Pin Mask Setting & Enable External Pin for Interface
          */
-        sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        sepmask = readw(MCFGPIO_PAR_UART);
         sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
-        writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        writew(sepmask, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
 
         /* Set multi-function pins to ethernet mode for fec0 */
 #if defined(CONFIG_M5271)
-        v = readb(MCF_IPSBAR + 0x100047);
-        writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+        v = readb(MCFGPIO_PAR_FECI2C);
+        writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 #else
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100078);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+        par = readw(MCFGPIO_PAR_FECI2C);
+        writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
+        v = readb(MCFGPIO_PAR_FEC0HL);
+        writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
 
         /* Set multi-function pins to ethernet mode for fec1 */
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xa0, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100079);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+        par = readw(MCFGPIO_PAR_FECI2C);
+        writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
+        v = readb(MCFGPIO_PAR_FEC1HL);
+        writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
 #endif
 }
 
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index f1319e5d2546..f9f7e6a13d04 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void)
         u16 v16;
 
         /* Set multi-function pins to ethernet mode for fec0 */
-        v16 = readw(MCF_IPSBAR + 0x100056);
-        writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
-        writeb(0xc0, MCF_IPSBAR + 0x100058);
+        v16 = readw(MCFGPIO_PASPAR);
+        writew(v16 | 0xf00, MCFGPIO_PASPAR);
+        writeb(0xc0, MCFGPIO_PEHLPAR);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 4819a44991ed..7951d1d43357 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void)
 static void __init m532x_qspi_init(void)
 {
         /* setup QSPS pins for QSPI with gpio CS control */
-        writew(0x01f0, MCF_GPIO_PAR_QSPI);
+        writew(0x01f0, MCFGPIO_PAR_QSPI);
 }
 
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void)
 static void __init m532x_uarts_init(void)
 {
         /* UART GPIO initialization */
-        MCF_GPIO_PAR_UART |= 0x0FFF;
+        writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
 
 static void __init m532x_fec_init(void)
 {
+        u8 v;
+
         /* Set multi-function pins to ethernet mode for fec0 */
-        MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
-                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
-        MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
-                MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
+        v = readb(MCFGPIO_PAR_FECI2C);
+        v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
+                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
+        writeb(v, MCFGPIO_PAR_FECI2C);
+
+        v = readb(MCFGPIO_PAR_FEC);
+        v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
+        writeb(v, MCFGPIO_PAR_FEC);
 }
 
 /***************************************************************************/
@@ -298,7 +304,7 @@ asmlinkage void __init sysinit(void)
 void wtm_init(void)
 {
         /* Disable watchdog timer */
-        MCF_WTM_WCR = 0;
+        writew(0, MCF_WTM_WCR);
 }
 
 #define MCF_SCM_BCR_GBW         (0x00000100)
@@ -307,53 +313,53 @@ void wtm_init(void)
 void scm_init(void)
 {
         /* All masters are trusted */
-        MCF_SCM_MPR = 0x77777777;
+        writel(0x77777777, MCF_SCM_MPR);
     
         /* Allow supervisor/user, read/write, and trusted/untrusted
            access to all slaves */
-        MCF_SCM_PACRA = 0;
-        MCF_SCM_PACRB = 0;
-        MCF_SCM_PACRC = 0;
-        MCF_SCM_PACRD = 0;
-        MCF_SCM_PACRE = 0;
-        MCF_SCM_PACRF = 0;
+        writel(0, MCF_SCM_PACRA);
+        writel(0, MCF_SCM_PACRB);
+        writel(0, MCF_SCM_PACRC);
+        writel(0, MCF_SCM_PACRD);
+        writel(0, MCF_SCM_PACRE);
+        writel(0, MCF_SCM_PACRF);
 
         /* Enable bursts */
-        MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
+        writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
 }
 
 
 void fbcs_init(void)
 {
-        MCF_GPIO_PAR_CS = 0x0000003E;
+        writeb(0x3E, MCFGPIO_PAR_CS);
 
         /* Latch chip select */
-        MCF_FBCS1_CSAR = 0x10080000;
+        writel(0x10080000, MCF_FBCS1_CSAR);
 
-        MCF_FBCS1_CSCR = 0x002A3780;
-        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
+        writel(0x002A3780, MCF_FBCS1_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
 
         /* Initialize latch to drive signals to inactive states */
-        *((u16 *)(0x10080000)) = 0xFFFF;
+        writew(0xffff, 0x10080000);
 
         /* External SRAM */
-        MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
-        MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
-                        | MCF_FBCS_CSCR_AA
-                        | MCF_FBCS_CSCR_SBM
-                        | MCF_FBCS_CSCR_WS(1));
-        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
-                        | MCF_FBCS_CSMR_V);
+        writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
+        writel(MCF_FBCS_CSCR_PS_16 |
+                MCF_FBCS_CSCR_AA |
+                MCF_FBCS_CSCR_SBM |
+                MCF_FBCS_CSCR_WS(1),
+                MCF_FBCS1_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
 
         /* Boot Flash connected to FBCS0 */
-        MCF_FBCS0_CSAR = FLASH_ADDRESS;
-        MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
-                        | MCF_FBCS_CSCR_BEM
-                        | MCF_FBCS_CSCR_AA
-                        | MCF_FBCS_CSCR_SBM
-                        | MCF_FBCS_CSCR_WS(7));
-        MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
-                        | MCF_FBCS_CSMR_V);
+        writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
+        writel(MCF_FBCS_CSCR_PS_16 |
+                MCF_FBCS_CSCR_BEM |
+                MCF_FBCS_CSCR_AA |
+                MCF_FBCS_CSCR_SBM |
+                MCF_FBCS_CSCR_WS(7),
+                MCF_FBCS0_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
 }
 
 void sdramc_init(void)
@@ -362,102 +368,102 @@ void sdramc_init(void)
          * Check to see if the SDRAM has already been initialized
          * by a run control tool
          */
-        if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
+        if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
                 /* SDRAM chip select initialization */
                 
                 /* Initialize SDRAM chip select */
-                MCF_SDRAMC_SDCS0 = (0
-                        | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
-                        | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
+                writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
+                        MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
+                        MCF_SDRAMC_SDCS0);
 
         /*
          * Basic configuration and initialization
          */
-        MCF_SDRAMC_SDCFG1 = (0
-                | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
-                | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
-                | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
-                | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_WTLAT(3));
-        MCF_SDRAMC_SDCFG2 = (0
-                | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
-                | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
-                | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
-                | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
+        writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
+                MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
+                MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
+                MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
+                MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
+                MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
+                MCF_SDRAMC_SDCFG1_WTLAT(3),
+                MCF_SDRAMC_SDCFG1);
+        writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
+                MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
+                MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
+                MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
+                MCF_SDRAMC_SDCFG2);
 
             
         /*
          * Precharge and enable write to SDMR
          */
-        MCF_SDRAMC_SDCR = (0
-                | MCF_SDRAMC_SDCR_MODE_EN
-                | MCF_SDRAMC_SDCR_CKE
-                | MCF_SDRAMC_SDCR_DDR
-                | MCF_SDRAMC_SDCR_MUX(1)
-                | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
-                | MCF_SDRAMC_SDCR_PS_16
-                | MCF_SDRAMC_SDCR_IPALL);            
+        writel(MCF_SDRAMC_SDCR_MODE_EN |
+                MCF_SDRAMC_SDCR_CKE |
+                MCF_SDRAMC_SDCR_DDR |
+                MCF_SDRAMC_SDCR_MUX(1) |
+                MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
+                MCF_SDRAMC_SDCR_PS_16 |
+                MCF_SDRAMC_SDCR_IPALL,
+                MCF_SDRAMC_SDCR);
 
         /*
          * Write extended mode register
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LEMR
-                | MCF_SDRAMC_SDMR_AD(0x0)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
+                MCF_SDRAMC_SDMR_AD(0x0) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
 
         /*
          * Write mode register and reset DLL
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LMR
-                | MCF_SDRAMC_SDMR_AD(0x163)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
+                MCF_SDRAMC_SDMR_AD(0x163) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
 
         /*
          * Execute a PALL command
          */
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
 
         /*
          * Perform two REF cycles
          */
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
 
         /*
          * Write mode register and clear reset DLL
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LMR
-                | MCF_SDRAMC_SDMR_AD(0x063)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
+                MCF_SDRAMC_SDMR_AD(0x063) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
                                 
         /*
          * Enable auto refresh and lock SDMR
          */
-        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
-        MCF_SDRAMC_SDCR |= (0
-                | MCF_SDRAMC_SDCR_REF
-                | MCF_SDRAMC_SDCR_DQS_OE(0xC));
+        writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
+                MCF_SDRAMC_SDCR);
+        writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
+                MCF_SDRAMC_SDCR);
         }
 }
 
 void gpio_init(void)
 {
         /* Enable UART0 pins */
-        MCF_GPIO_PAR_UART = ( 0
-                | MCF_GPIO_PAR_UART_PAR_URXD0
-                | MCF_GPIO_PAR_UART_PAR_UTXD0);
-
-        /* Initialize TIN3 as a GPIO output to enable the write
-           half of the latch */
-        MCF_GPIO_PAR_TIMER = 0x00;
-        __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
-        __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
+        writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
+                MCFGPIO_PAR_UART);
 
+        /*
+         * Initialize TIN3 as a GPIO output to enable the write
+         * half of the latch.
+         */
+        writeb(0x00, MCFGPIO_PAR_TIMER);
+        writeb(0x08, MCFGPIO_PDDR_TIMER);
+        writeb(0x00, MCFGPIO_PCLRR_TIMER);
 }
 
 int clock_pll(int fsys, int flags)
@@ -469,7 +475,7 @@ int clock_pll(int fsys, int flags)
         
         if (fsys == 0) {
                 /* Return current PLL output */
-                mfd = MCF_PLL_PFDR;
+                mfd = readb(MCF_PLL_PFDR);
 
                 return (fref * mfd / (BUSDIV * 4));
         }
@@ -495,9 +501,10 @@ int clock_pll(int fsys, int flags)
          * If it has then the SDRAM needs to be put into self refresh
          * mode before reprogramming the PLL.
          */
-        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+        if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
                 /* Put SDRAM into self refresh mode */
-                MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
+                writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
+                        MCF_SDRAMC_SDCR);
 
         /*
          * Initialize the PLL to generate the new system clock frequency.
@@ -508,11 +515,10 @@ int clock_pll(int fsys, int flags)
         clock_limp(DEFAULT_LPD);
                                         
         /* Reprogram PLL for desired fsys */
-        MCF_PLL_PODR = (0
-                | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
-                | MCF_PLL_PODR_BUSDIV(BUSDIV));
+        writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
+                MCF_PLL_PODR);
                                                 
-        MCF_PLL_PFDR = mfd;
+        writeb(mfd, MCF_PLL_PFDR);
                 
         /* Exit LIMP mode */
         clock_exit_limp();
@@ -520,12 +526,13 @@ int clock_pll(int fsys, int flags)
         /*
          * Return the SDRAM to normal operation if it is in use.
          */
-        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+        if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
                 /* Exit self refresh mode */
-                MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
+                writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
+                        MCF_SDRAMC_SDCR);
 
         /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
-        MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
+        writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
 
         /* wait for DQS logic to relock */
         for (i = 0; i < 0x200; i++)
@@ -546,14 +553,12 @@ int clock_limp(int div)
     
         /* Save of the current value of the SSIDIV so we don't
            overwrite the value*/
-        temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
+        temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
       
         /* Apply the divider to the system clock */
-        MCF_CCM_CDR = ( 0
-                | MCF_CCM_CDR_LPDIV(div)
-                | MCF_CCM_CDR_SSIDIV(temp));
+        writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
     
-        MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
+        writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
     
         return (FREF/(3*(1 << div)));
 }
@@ -563,10 +568,10 @@ int clock_exit_limp(void)
         int fout;
         
         /* Exit LIMP mode */
-        MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
+        writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
 
         /* Wait for PLL to lock */
-        while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
+        while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
                 ;
         
         fout = get_sys_clock();
@@ -579,10 +584,10 @@ int get_sys_clock(void)
         int divider;
         
         /* Test to see if device is in LIMP mode */
-        if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
-                divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
+        if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
+                divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
                 return (FREF/(2 << divider));
         }
         else
-                return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
+                return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
 }
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3de..b587bf35175b 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -30,14 +30,12 @@
 static void __init m54xx_uarts_init(void)
 {
         /* enable io pins */
-        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-                MCF_MBAR + MCF_PAR_PSC(0));
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
-                MCF_MBAR + MCF_PAR_PSC(1));
+                MCFGPIO_PAR_PSC1);
         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
-                MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
-        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-                MCF_MBAR + MCF_PAR_PSC(3));
+                MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
 }
 
 /***************************************************************************/
@@ -46,10 +44,10 @@ static void mcf54xx_reset(void)
 {
         /* disable interrupts and enable the watchdog */
         asm("movew #0x2700, %sr\n");
-        __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
-        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
+        __raw_writel(0, MCF_GPT_GMS0);
+        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
         __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
-                                                MCF_MBAR + MCF_GPT_GMS0);
+                MCF_GPT_GMS0);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/nettel.c b/arch/m68k/platform/coldfire/nettel.c
index e925ea4602f8..ddc48ec1b800 100644
--- a/arch/m68k/platform/coldfire/nettel.c
+++ b/arch/m68k/platform/coldfire/nettel.c
@@ -121,14 +121,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
 
 static void __init nettel_smc91x_init(void)
 {
-        writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
+        writew(0x00ec, MCFSIM_PADDR);
         mcf_setppdata(0, 0x0080);
         writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
         writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
         mcf_setppdata(0x0080, 0);
 
         /* Set correct chip select timing for SMC9196 accesses */
-        writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
+        writew(0x1180, MCFSIM_CSCR3);
 
         /* Set the SMC interrupts to be auto-vectored */
         mcf_autovector(NETTEL_SMC0_IRQ);
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
index 553210d3d4c1..8572246db84d 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
                 PACR_EXTMINTE(0x1f), PACR);
 
         /* Set required multi-function pins for PCI bus use */
-        __raw_writew(0x3ff, MCF_PAR_PCIBG);
-        __raw_writew(0x3ff, MCF_PAR_PCIBR);
+        __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
+        __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
 
         /* Set up config space for local host bus controller */
         __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
index 933e54eacc69..f30952f0cbe6 100644
--- a/arch/m68k/platform/coldfire/reset.c
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
 {
         local_irq_disable();
         /* Set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        __raw_writeb(0xc0, MCFSIM_SYPCR);
         for (;;)
                 /* wait for watchdog to timeout */;
 }
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 2027fc20b876..bb5a25ada848 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -32,7 +32,7 @@
 /*
  *      By default use Slice Timer 1 as the profiler clock timer.
  */
-#define PA(a)   (MCF_MBAR + MCFSLT_TIMER1 + (a))
+#define PA(a)   (MCFSLT_TIMER1 + (a))
 
 /*
  *      Choose a reasonably fast profile timer. Make it an odd value to
@@ -76,7 +76,7 @@ void mcfslt_profile_init(void)
 /*
  *      By default use Slice Timer 0 as the system clock timer.
  */
-#define TA(a)   (MCF_MBAR + MCFSLT_TIMER0 + (a))
+#define TA(a)   (MCFSLT_TIMER0 + (a))
 
 static u32 mcfslt_cycles_per_jiffy;
 static u32 mcfslt_cnt;
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 0a273e75408c..51f6d2af807f 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -56,13 +56,13 @@ static void init_timer_irq(void)
 #ifdef MCFSIM_ICR_AUTOVEC
         /* Timer1 is always used as system timer */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
+                MCFSIM_TIMER1ICR);
         mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
 
 #ifdef CONFIG_HIGHPROFILE
         /* Timer2 is to be used as a high speed profile timer  */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
+                MCFSIM_TIMER2ICR);
         mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
 #endif
 #endif /* MCFSIM_ICR_AUTOVEC */
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ab9afcaa7f6a..6133bed2b855 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -243,14 +243,11 @@ choice
 config MICROBLAZE_4K_PAGES
         bool "4k page size"
 
-config MICROBLAZE_8K_PAGES
-        bool "8k page size"
-
 config MICROBLAZE_16K_PAGES
         bool "16k page size"
 
-config MICROBLAZE_32K_PAGES
-        bool "32k page size"
+config MICROBLAZE_64K_PAGES
+        bool "64k page size"
 
 endchoice
 
diff --git a/arch/microblaze/include/asm/clinkage.h b/arch/microblaze/include/asm/clinkage.h
deleted file mode 100644
index 9e218435a55c..000000000000
--- a/arch/microblaze/include/asm/clinkage.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/linkage.h>
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8cdac14b55b0..4fbfdc1ac7f8 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -35,6 +35,10 @@ extern resource_size_t isa_mem_base;
 
 #define IO_SPACE_LIMIT (0xFFFFFFFF)
 
+/* the following is needed to support PCI with some drivers */
+
+#define mmiowb()
+
 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 {
         return *(volatile unsigned char __force *)addr;
@@ -248,4 +252,94 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 #define ioport_map(port, nr)    ((void __iomem *)(port))
 #define ioport_unmap(addr)
 
+/* from asm-generic/io.h */
+#ifndef insb
+static inline void insb(unsigned long addr, void *buffer, int count)
+{
+        if (count) {
+                u8 *buf = buffer;
+                do {
+                        u8 x = inb(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef insw
+static inline void insw(unsigned long addr, void *buffer, int count)
+{
+        if (count) {
+                u16 *buf = buffer;
+                do {
+                        u16 x = inw(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef insl
+static inline void insl(unsigned long addr, void *buffer, int count)
+{
+        if (count) {
+                u32 *buf = buffer;
+                do {
+                        u32 x = inl(addr);
+                        *buf++ = x;
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef outsb
+static inline void outsb(unsigned long addr, const void *buffer, int count)
+{
+        if (count) {
+                const u8 *buf = buffer;
+                do {
+                        outb(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef outsw
+static inline void outsw(unsigned long addr, const void *buffer, int count)
+{
+        if (count) {
+                const u16 *buf = buffer;
+                do {
+                        outw(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+
+#ifndef outsl
+static inline void outsl(unsigned long addr, const void *buffer, int count)
+{
+        if (count) {
+                const u32 *buf = buffer;
+                do {
+                        outl(*buf++, addr);
+                } while (--count);
+        }
+}
+#endif
+
+#define ioread8_rep(p, dst, count) \
+        insb((unsigned long) (p), (dst), (count))
+#define ioread16_rep(p, dst, count) \
+        insw((unsigned long) (p), (dst), (count))
+#define ioread32_rep(p, dst, count) \
+        insl((unsigned long) (p), (dst), (count))
+
+#define iowrite8_rep(p, src, count) \
+        outsb((unsigned long) (p), (src), (count))
+#define iowrite16_rep(p, src, count) \
+        outsw((unsigned long) (p), (src), (count))
+#define iowrite32_rep(p, src, count) \
+        outsl((unsigned long) (p), (src), (count))
+
 #endif /* _ASM_MICROBLAZE_IO_H */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 287c5485d286..85a5ae8e9bd0 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -23,12 +23,10 @@
 #ifdef __KERNEL__
 
 /* PAGE_SHIFT determines the page size */
-#if defined(CONFIG_MICROBLAZE_32K_PAGES)
-#define PAGE_SHIFT              15
+#if defined(CONFIG_MICROBLAZE_64K_PAGES)
+#define PAGE_SHIFT              16
 #elif defined(CONFIG_MICROBLAZE_16K_PAGES)
 #define PAGE_SHIFT              14
-#elif defined(CONFIG_MICROBLAZE_8K_PAGES)
-#define PAGE_SHIFT              13
 #else
 #define PAGE_SHIFT              12
 #endif
@@ -37,6 +35,8 @@
 
 #define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
 
+#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
+
 #ifndef __ASSEMBLY__
 
 /* MS be sure that SLAB allocates aligned objects */
@@ -71,7 +71,6 @@ extern unsigned int __page_offset;
  * The basic type of a PTE - 32 bit physical addressing.
  */
 typedef unsigned long pte_basic_t;
-#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
 #define PTE_FMT         "%.8lx"
 
 #endif /* CONFIG_MMU */
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index a0da88bf70c5..41cc841091b0 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -22,6 +22,8 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 
+#include <asm-generic/pci-dma-compat.h>
+
 #define PCIBIOS_MIN_IO          0x1000
 #define PCIBIOS_MIN_MEM         0x10000000
 
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index 3ef7b9cafeca..a7311cd9dee0 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -234,12 +234,6 @@ static inline pte_t pte_mkspecial(pte_t pte)	{ return pte; }
 #ifndef _PAGE_SHARED
 #define _PAGE_SHARED    0
 #endif
-#ifndef _PAGE_HWWRITE
-#define _PAGE_HWWRITE   0
-#endif
-#ifndef _PAGE_HWEXEC
-#define _PAGE_HWEXEC    0
-#endif
 #ifndef _PAGE_EXEC
 #define _PAGE_EXEC      0
 #endif
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 98b17f9f904b..eef84de5e8c8 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -109,20 +109,24 @@ no_fdt_arg:
 #ifndef CONFIG_CMDLINE_BOOL
 /*
  * handling command line
- * copy command line to __init_end. There is space for storing command line.
+ * copy command line directly to cmd_line placed in data section.
  */
+        beqid   r5, skip        /* Skip if NULL pointer */
         or      r6, r0, r0              /* incremment */
-        ori     r4, r0, __init_end      /* load address of command line */
+        ori     r4, r0, cmd_line        /* load address of command line */
         tophys(r4,r4)                   /* convert to phys address */
         ori     r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
 _copy_command_line:
-        lbu     r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
-        sb      r2, r4, r6              /* addr[r4+r6]= r2*/
+        /* r2=r5+r6 - r5 contain pointer to command line */
+        lbu             r2, r5, r6
+        beqid   r2, skip                /* Skip if no data */
+        sb              r2, r4, r6              /* addr[r4+r6]= r2*/
         addik   r6, r6, 1               /* increment counting */
         bgtid   r3, _copy_command_line  /* loop for all entries       */
-        addik   r3, r3, -1              /* descrement loop */
+        addik   r3, r3, -1              /* decrement loop */
         addik   r5, r4, 0               /* add new space for command line */
         tovirt(r5,r5)
+skip:
 #endif /* CONFIG_CMDLINE_BOOL */
 
 #ifdef NOT_COMPILE
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index aa510f450ac6..61b3a1fed46f 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -75,6 +75,7 @@
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/signal.h>
+#include <asm/registers.h>
 #include <asm/asm-offsets.h>
 
 #undef DEBUG
@@ -581,7 +582,7 @@ ex_handler_done:
                  * tried to access a kernel or read-protected page - always
                  * a SEGV). All other faults here must be stores, so no
                  * need to check ESR_S as well. */
-                andi    r4, r4, 0x800           /* ESR_Z - zone protection */
+                andi    r4, r4, ESR_DIZ         /* ESR_Z - zone protection */
                 bnei    r4, ex2
 
                 ori     r4, r0, swapper_pg_dir
@@ -595,25 +596,25 @@ ex_handler_done:
                  * tried to access a kernel or read-protected page - always
                  * a SEGV). All other faults here must be stores, so no
                  * need to check ESR_S as well. */
-                andi    r4, r4, 0x800           /* ESR_Z */
+                andi    r4, r4, ESR_DIZ         /* ESR_Z */
                 bnei    r4, ex2
                 /* get current task address */
                 addi    r4 ,CURRENT_TASK, TOPHYS(0);
                 lwi     r4, r4, TASK_THREAD+PGDIR
         ex4:
                 tophys(r4,r4)
-                BSRLI(r5,r3,20)         /* Create L1 (pgdir/pmd) address */
-                andi    r5, r5, 0xffc
+                /* Create L1 (pgdir/pmd) address */
+                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
                 lwi     r4, r4, 0               /* Get L1 entry */
-                andi    r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
+                andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
                 beqi    r5, ex2                 /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,10)                 /* Compute PTE address */
-                andi    r6, r6, 0xffc
-                andi    r5, r5, 0xfffff003
+                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
@@ -632,7 +633,9 @@ ex_handler_done:
                  * Many of these bits are software only. Bits we don't set
                  * here we (properly should) assume have the appropriate value.
                  */
-                andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
+/* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
+                andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
+                                                TLB_ZSEL(1) | TLB_ATTR_MASK
                 ori     r4, r4, _PAGE_HWEXEC    /* make it executable */
 
                 /* find the TLB index that caused the fault. It has to be here*/
@@ -701,18 +704,18 @@ ex_handler_done:
                 lwi     r4, r4, TASK_THREAD+PGDIR
         ex6:
                 tophys(r4,r4)
-                BSRLI(r5,r3,20)         /* Create L1 (pgdir/pmd) address */
-                andi    r5, r5, 0xffc
+                /* Create L1 (pgdir/pmd) address */
+                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
                 lwi     r4, r4, 0               /* Get L1 entry */
-                andi    r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
+                andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
                 beqi    r5, ex7                 /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,10)                 /* Compute PTE address */
-                andi    r6, r6, 0xffc
-                andi    r5, r5, 0xfffff003
+                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
@@ -731,7 +734,8 @@ ex_handler_done:
                  * here we (properly should) assume have the appropriate value.
                  */
                 brid    finish_tlb_load
-                andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
+                andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
+                                                TLB_ZSEL(1) | TLB_ATTR_MASK
         ex7:
                 /* The bailout. Restore registers to pre-exception conditions
                  * and call the heavyweights to help us out.
@@ -771,18 +775,18 @@ ex_handler_done:
                 lwi     r4, r4, TASK_THREAD+PGDIR
         ex9:
                 tophys(r4,r4)
-                BSRLI(r5,r3,20)         /* Create L1 (pgdir/pmd) address */
-                andi    r5, r5, 0xffc
+                /* Create L1 (pgdir/pmd) address */
+                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
                 lwi     r4, r4, 0               /* Get L1 entry */
-                andi    r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
+                andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
                 beqi    r5, ex10                /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,10)                 /* Compute PTE address */
-                andi    r6, r6, 0xffc
-                andi    r5, r5, 0xfffff003
+                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
@@ -801,7 +805,8 @@ ex_handler_done:
                  * here we (properly should) assume have the appropriate value.
                  */
                 brid    finish_tlb_load
-                andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
+                andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
+                                                TLB_ZSEL(1) | TLB_ATTR_MASK
         ex10:
                 /* The bailout. Restore registers to pre-exception conditions
                  * and call the heavyweights to help us out.
@@ -854,8 +859,14 @@ ex_handler_done:
                  * set of bits. These are size, valid, E, U0, and ensure
                  * bits 20 and 21 are zero.
                  */
-                andi    r3, r3, 0xfffff000
-                ori     r3, r3, 0x0c0
+                andi    r3, r3, PAGE_MASK
+#ifdef CONFIG_MICROBLAZE_64K_PAGES
+                ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
+#elif CONFIG_MICROBLAZE_16K_PAGES
+                ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
+#else
+                ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
+#endif
                 mts     rtlbhi, r3              /* Load TLB HI */
                 nop
 
diff --git a/arch/microblaze/kernel/reset.c b/arch/microblaze/kernel/reset.c
index 88a01636f785..2e5079ab53d2 100644
--- a/arch/microblaze/kernel/reset.c
+++ b/arch/microblaze/kernel/reset.c
@@ -26,13 +26,14 @@ void of_platform_reset_gpio_probe(void)
                                    "hard-reset-gpios", 0);
 
         if (!gpio_is_valid(handle)) {
-                printk(KERN_INFO "Skipping unavailable RESET gpio %d (%s)\n",
+                pr_info("Skipping unavailable RESET gpio %d (%s)\n",
                                 handle, "reset");
+                return;
         }
 
         ret = gpio_request(handle, "reset");
         if (ret < 0) {
-                printk(KERN_INFO "GPIO pin is already allocated\n");
+                pr_info("GPIO pin is already allocated\n");
                 return;
         }
 
@@ -49,7 +50,7 @@ void of_platform_reset_gpio_probe(void)
         /* Setup output direction */
         gpio_set_value(handle, 0);
 
-        printk(KERN_INFO "RESET: Registered gpio device: %d, current val: %d\n",
+        pr_info("RESET: Registered gpio device: %d, current val: %d\n",
                                                         handle, reset_val);
         return;
 err:
@@ -60,7 +61,10 @@ err:
 
 static void gpio_system_reset(void)
 {
-        gpio_set_value(handle, 1 - reset_val);
+        if (gpio_is_valid(handle))
+                gpio_set_value(handle, 1 - reset_val);
+        else
+                pr_notice("Reset GPIO unavailable - halting!\n");
 }
 #else
 #define gpio_system_reset() do {} while (0)
@@ -72,30 +76,29 @@ void of_platform_reset_gpio_probe(void)
 
 void machine_restart(char *cmd)
 {
-        printk(KERN_NOTICE "Machine restart...\n");
+        pr_notice("Machine restart...\n");
         gpio_system_reset();
-        dump_stack();
         while (1)
                 ;
 }
 
 void machine_shutdown(void)
 {
-        printk(KERN_NOTICE "Machine shutdown...\n");
+        pr_notice("Machine shutdown...\n");
         while (1)
                 ;
 }
 
 void machine_halt(void)
 {
-        printk(KERN_NOTICE "Machine halt...\n");
+        pr_notice("Machine halt...\n");
         while (1)
                 ;
 }
 
 void machine_power_off(void)
 {
-        printk(KERN_NOTICE "Machine power off...\n");
+        pr_notice("Machine power off...\n");
         while (1)
                 ;
 }
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 4da971d4392f..954348f83505 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -40,7 +40,12 @@ DEFINE_PER_CPU(unsigned int, R11_SAVE);	/* Temp variable for entry */
 DEFINE_PER_CPU(unsigned int, CURRENT_SAVE);     /* Saved current pointer */
 
 unsigned int boot_cpuid;
-char cmd_line[COMMAND_LINE_SIZE];
+/*
+ * Placed cmd_line to .data section because can be initialized from
+ * ASM code. Default position is BSS section which is cleared
+ * in machine_early_init().
+ */
+char cmd_line[COMMAND_LINE_SIZE] __attribute__ ((section(".data")));
 
 void __init setup_arch(char **cmdline_p)
 {
@@ -64,7 +69,7 @@ void __init setup_arch(char **cmdline_p)
         xilinx_pci_init();
 
 #if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
-        printk(KERN_NOTICE "Self modified code enable\n");
+        pr_notice("Self modified code enable\n");
 #endif
 
 #ifdef CONFIG_VT
@@ -130,12 +135,6 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         memset(__bss_start, 0, __bss_stop-__bss_start);
         memset(_ssbss, 0, _esbss-_ssbss);
 
-        /* Copy command line passed from bootloader */
-#ifndef CONFIG_CMDLINE_BOOL
-        if (cmdline && cmdline[0] != '\0')
-                strlcpy(cmd_line, cmdline, COMMAND_LINE_SIZE);
-#endif
-
         lockdep_init();
 
 /* initialize device tree for usage in early_printk */
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index 76b9722557db..c1220dbf87cd 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -290,15 +290,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
         case -ERESTARTNOINTR:
 do_restart:
                 /* offset of 4 bytes to re-execute trap (brki) instruction */
-#ifndef CONFIG_MMU
                 regs->pc -= 4;
-#else
-                /* offset of 8 bytes required = 4 for rtbd
-                   offset, plus 4 for size of
-                        "brki r14,8"
-                   instruction. */
-                regs->pc -= 8;
-#endif
                 break;
         }
 }
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index 522defa7d41f..aec5020a6e31 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -116,21 +116,21 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
 {
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                printk(KERN_INFO "%s: periodic\n", __func__);
+                pr_info("%s: periodic\n", __func__);
                 microblaze_timer0_start_periodic(freq_div_hz);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
-                printk(KERN_INFO "%s: oneshot\n", __func__);
+                pr_info("%s: oneshot\n", __func__);
                 break;
         case CLOCK_EVT_MODE_UNUSED:
-                printk(KERN_INFO "%s: unused\n", __func__);
+                pr_info("%s: unused\n", __func__);
                 break;
         case CLOCK_EVT_MODE_SHUTDOWN:
-                printk(KERN_INFO "%s: shutdown\n", __func__);
+                pr_info("%s: shutdown\n", __func__);
                 microblaze_timer0_stop();
                 break;
         case CLOCK_EVT_MODE_RESUME:
-                printk(KERN_INFO "%s: resume\n", __func__);
+                pr_info("%s: resume\n", __func__);
                 break;
         }
 }
@@ -257,7 +257,15 @@ void __init time_init(void)
                                 0
                         };
 #endif
-        timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a");
+        prop = of_get_property(of_chosen, "system-timer", NULL);
+        if (prop)
+                timer = of_find_node_by_phandle(be32_to_cpup(prop));
+        else
+                pr_info("No chosen timer found, using default\n");
+
+        if (!timer)
+                timer = of_find_compatible_node(NULL, NULL,
+                                                "xlnx,xps-timer-1.00.a");
         BUG_ON(!timer);
 
         timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
@@ -266,14 +274,14 @@ void __init time_init(void)
         timer_num = be32_to_cpup(of_get_property(timer,
                                                 "xlnx,one-timer-only", NULL));
         if (timer_num) {
-                printk(KERN_EMERG "Please enable two timers in HW\n");
+                pr_emerg("Please   enable two timers in HW\n");
                 BUG();
         }
 
 #ifdef CONFIG_SELFMOD_TIMER
         selfmod_function((int *) arr_func, timer_baseaddr);
 #endif
-        printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
+        pr_info("%s #0 at 0x%08x, irq=%d\n",
                 timer->name, timer_baseaddr, irq);
 
         /* If there is clock-frequency property than use it */
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index f9acddd9ace3..c8af429991d9 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -656,7 +656,6 @@ config S390_GUEST
         depends on 64BIT && EXPERIMENTAL
         select VIRTUALIZATION
         select VIRTIO
-        select VIRTIO_RING
         select VIRTIO_CONSOLE
         help
           Enabling this option adds support for virtio based paravirtual device
diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig
index 6e121a2a49e1..7872a3330fb5 100644
--- a/arch/x86/lguest/Kconfig
+++ b/arch/x86/lguest/Kconfig
@@ -4,7 +4,6 @@ config LGUEST_GUEST
         depends on X86_32
         select VIRTUALIZATION
         select VIRTIO
-        select VIRTIO_RING
         select VIRTIO_CONSOLE
         help
           Lguest is a tiny in-kernel hypervisor.  Selecting this will
diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
index c0bbeb470754..0bdde8fba397 100644
--- a/drivers/block/virtio_blk.c
+++ b/drivers/block/virtio_blk.c
@@ -14,6 +14,9 @@
 
 #define PART_BITS 4
 
+static bool use_bio;
+module_param(use_bio, bool, S_IRUGO);
+
 static int major;
 static DEFINE_IDA(vd_index_ida);
 
@@ -23,6 +26,7 @@ struct virtio_blk
 {
         struct virtio_device *vdev;
         struct virtqueue *vq;
+        wait_queue_head_t queue_wait;
 
         /* The disk structure for the kernel. */
         struct gendisk *disk;
@@ -51,53 +55,244 @@ struct virtio_blk
 struct virtblk_req
 {
         struct request *req;
+        struct bio *bio;
         struct virtio_blk_outhdr out_hdr;
         struct virtio_scsi_inhdr in_hdr;
+        struct work_struct work;
+        struct virtio_blk *vblk;
+        int flags;
         u8 status;
+        struct scatterlist sg[];
+};
+
+enum {
+        VBLK_IS_FLUSH           = 1,
+        VBLK_REQ_FLUSH          = 2,
+        VBLK_REQ_DATA           = 4,
+        VBLK_REQ_FUA            = 8,
 };
 
-static void blk_done(struct virtqueue *vq)
+static inline int virtblk_result(struct virtblk_req *vbr)
+{
+        switch (vbr->status) {
+        case VIRTIO_BLK_S_OK:
+                return 0;
+        case VIRTIO_BLK_S_UNSUPP:
+                return -ENOTTY;
+        default:
+                return -EIO;
+        }
+}
+
+static inline struct virtblk_req *virtblk_alloc_req(struct virtio_blk *vblk,
+                                                    gfp_t gfp_mask)
 {
-        struct virtio_blk *vblk = vq->vdev->priv;
         struct virtblk_req *vbr;
-        unsigned int len;
-        unsigned long flags;
 
-        spin_lock_irqsave(vblk->disk->queue->queue_lock, flags);
-        while ((vbr = virtqueue_get_buf(vblk->vq, &len)) != NULL) {
-                int error;
+        vbr = mempool_alloc(vblk->pool, gfp_mask);
+        if (!vbr)
+                return NULL;
 
-                switch (vbr->status) {
-                case VIRTIO_BLK_S_OK:
-                        error = 0;
-                        break;
-                case VIRTIO_BLK_S_UNSUPP:
-                        error = -ENOTTY;
-                        break;
-                default:
-                        error = -EIO;
+        vbr->vblk = vblk;
+        if (use_bio)
+                sg_init_table(vbr->sg, vblk->sg_elems);
+
+        return vbr;
+}
+
+static void virtblk_add_buf_wait(struct virtio_blk *vblk,
+                                 struct virtblk_req *vbr,
+                                 unsigned long out,
+                                 unsigned long in)
+{
+        DEFINE_WAIT(wait);
+
+        for (;;) {
+                prepare_to_wait_exclusive(&vblk->queue_wait, &wait,
+                                          TASK_UNINTERRUPTIBLE);
+
+                spin_lock_irq(vblk->disk->queue->queue_lock);
+                if (virtqueue_add_buf(vblk->vq, vbr->sg, out, in, vbr,
+                                      GFP_ATOMIC) < 0) {
+                        spin_unlock_irq(vblk->disk->queue->queue_lock);
+                        io_schedule();
+                } else {
+                        virtqueue_kick(vblk->vq);
+                        spin_unlock_irq(vblk->disk->queue->queue_lock);
                         break;
                 }
 
-                switch (vbr->req->cmd_type) {
-                case REQ_TYPE_BLOCK_PC:
-                        vbr->req->resid_len = vbr->in_hdr.residual;
-                        vbr->req->sense_len = vbr->in_hdr.sense_len;
-                        vbr->req->errors = vbr->in_hdr.errors;
-                        break;
-                case REQ_TYPE_SPECIAL:
-                        vbr->req->errors = (error != 0);
-                        break;
-                default:
-                        break;
+        }
+
+        finish_wait(&vblk->queue_wait, &wait);
+}
+
+static inline void virtblk_add_req(struct virtblk_req *vbr,
+                                   unsigned int out, unsigned int in)
+{
+        struct virtio_blk *vblk = vbr->vblk;
+
+        spin_lock_irq(vblk->disk->queue->queue_lock);
+        if (unlikely(virtqueue_add_buf(vblk->vq, vbr->sg, out, in, vbr,
+                                        GFP_ATOMIC) < 0)) {
+                spin_unlock_irq(vblk->disk->queue->queue_lock);
+                virtblk_add_buf_wait(vblk, vbr, out, in);
+                return;
+        }
+        virtqueue_kick(vblk->vq);
+        spin_unlock_irq(vblk->disk->queue->queue_lock);
+}
+
+static int virtblk_bio_send_flush(struct virtblk_req *vbr)
+{
+        unsigned int out = 0, in = 0;
+
+        vbr->flags |= VBLK_IS_FLUSH;
+        vbr->out_hdr.type = VIRTIO_BLK_T_FLUSH;
+        vbr->out_hdr.sector = 0;
+        vbr->out_hdr.ioprio = 0;
+        sg_set_buf(&vbr->sg[out++], &vbr->out_hdr, sizeof(vbr->out_hdr));
+        sg_set_buf(&vbr->sg[out + in++], &vbr->status, sizeof(vbr->status));
+
+        virtblk_add_req(vbr, out, in);
+
+        return 0;
+}
+
+static int virtblk_bio_send_data(struct virtblk_req *vbr)
+{
+        struct virtio_blk *vblk = vbr->vblk;
+        unsigned int num, out = 0, in = 0;
+        struct bio *bio = vbr->bio;
+
+        vbr->flags &= ~VBLK_IS_FLUSH;
+        vbr->out_hdr.type = 0;
+        vbr->out_hdr.sector = bio->bi_sector;
+        vbr->out_hdr.ioprio = bio_prio(bio);
+
+        sg_set_buf(&vbr->sg[out++], &vbr->out_hdr, sizeof(vbr->out_hdr));
+
+        num = blk_bio_map_sg(vblk->disk->queue, bio, vbr->sg + out);
+
+        sg_set_buf(&vbr->sg[num + out + in++], &vbr->status,
+                   sizeof(vbr->status));
+
+        if (num) {
+                if (bio->bi_rw & REQ_WRITE) {
+                        vbr->out_hdr.type |= VIRTIO_BLK_T_OUT;
+                        out += num;
+                } else {
+                        vbr->out_hdr.type |= VIRTIO_BLK_T_IN;
+                        in += num;
                 }
+        }
+
+        virtblk_add_req(vbr, out, in);
+
+        return 0;
+}
+
+static void virtblk_bio_send_data_work(struct work_struct *work)
+{
+        struct virtblk_req *vbr;
+
+        vbr = container_of(work, struct virtblk_req, work);
+
+        virtblk_bio_send_data(vbr);
+}
+
+static void virtblk_bio_send_flush_work(struct work_struct *work)
+{
+        struct virtblk_req *vbr;
+
+        vbr = container_of(work, struct virtblk_req, work);
+
+        virtblk_bio_send_flush(vbr);
+}
+
+static inline void virtblk_request_done(struct virtblk_req *vbr)
+{
+        struct virtio_blk *vblk = vbr->vblk;
+        struct request *req = vbr->req;
+        int error = virtblk_result(vbr);
+
+        if (req->cmd_type == REQ_TYPE_BLOCK_PC) {
+                req->resid_len = vbr->in_hdr.residual;
+                req->sense_len = vbr->in_hdr.sense_len;
+                req->errors = vbr->in_hdr.errors;
+        } else if (req->cmd_type == REQ_TYPE_SPECIAL) {
+                req->errors = (error != 0);
+        }
+
+        __blk_end_request_all(req, error);
+        mempool_free(vbr, vblk->pool);
+}
+
+static inline void virtblk_bio_flush_done(struct virtblk_req *vbr)
+{
+        struct virtio_blk *vblk = vbr->vblk;
+
+        if (vbr->flags & VBLK_REQ_DATA) {
+                /* Send out the actual write data */
+                INIT_WORK(&vbr->work, virtblk_bio_send_data_work);
+                queue_work(virtblk_wq, &vbr->work);
+        } else {
+                bio_endio(vbr->bio, virtblk_result(vbr));
+                mempool_free(vbr, vblk->pool);
+        }
+}
+
+static inline void virtblk_bio_data_done(struct virtblk_req *vbr)
+{
+        struct virtio_blk *vblk = vbr->vblk;
 
-                __blk_end_request_all(vbr->req, error);
+        if (unlikely(vbr->flags & VBLK_REQ_FUA)) {
+                /* Send out a flush before end the bio */
+                vbr->flags &= ~VBLK_REQ_DATA;
+                INIT_WORK(&vbr->work, virtblk_bio_send_flush_work);
+                queue_work(virtblk_wq, &vbr->work);
+        } else {
+                bio_endio(vbr->bio, virtblk_result(vbr));
                 mempool_free(vbr, vblk->pool);
         }
+}
+
+static inline void virtblk_bio_done(struct virtblk_req *vbr)
+{
+        if (unlikely(vbr->flags & VBLK_IS_FLUSH))
+                virtblk_bio_flush_done(vbr);
+        else
+                virtblk_bio_data_done(vbr);
+}
+
+static void virtblk_done(struct virtqueue *vq)
+{
+        struct virtio_blk *vblk = vq->vdev->priv;
+        bool bio_done = false, req_done = false;
+        struct virtblk_req *vbr;
+        unsigned long flags;
+        unsigned int len;
+
+        spin_lock_irqsave(vblk->disk->queue->queue_lock, flags);
+        do {
+                virtqueue_disable_cb(vq);
+                while ((vbr = virtqueue_get_buf(vblk->vq, &len)) != NULL) {
+                        if (vbr->bio) {
+                                virtblk_bio_done(vbr);
+                                bio_done = true;
+                        } else {
+                                virtblk_request_done(vbr);
+                                req_done = true;
+                        }
+                }
+        } while (!virtqueue_enable_cb(vq));
         /* In case queue is stopped waiting for more buffers. */
-        blk_start_queue(vblk->disk->queue);
+        if (req_done)
+                blk_start_queue(vblk->disk->queue);
         spin_unlock_irqrestore(vblk->disk->queue->queue_lock, flags);
+
+        if (bio_done)
+                wake_up(&vblk->queue_wait);
 }
 
 static bool do_req(struct request_queue *q, struct virtio_blk *vblk,
@@ -106,13 +301,13 @@ static bool do_req(struct request_queue *q, struct virtio_blk *vblk,
         unsigned long num, out = 0, in = 0;
         struct virtblk_req *vbr;
 
-        vbr = mempool_alloc(vblk->pool, GFP_ATOMIC);
+        vbr = virtblk_alloc_req(vblk, GFP_ATOMIC);
         if (!vbr)
                 /* When another request finishes we'll try again. */
                 return false;
 
         vbr->req = req;
-
+        vbr->bio = NULL;
         if (req->cmd_flags & REQ_FLUSH) {
                 vbr->out_hdr.type = VIRTIO_BLK_T_FLUSH;
                 vbr->out_hdr.sector = 0;
@@ -172,7 +367,8 @@ static bool do_req(struct request_queue *q, struct virtio_blk *vblk,
                 }
         }
 
-        if (virtqueue_add_buf(vblk->vq, vblk->sg, out, in, vbr, GFP_ATOMIC)<0) {
+        if (virtqueue_add_buf(vblk->vq, vblk->sg, out, in, vbr,
+                              GFP_ATOMIC) < 0) {
                 mempool_free(vbr, vblk->pool);
                 return false;
         }
@@ -180,7 +376,7 @@ static bool do_req(struct request_queue *q, struct virtio_blk *vblk,
         return true;
 }
 
-static void do_virtblk_request(struct request_queue *q)
+static void virtblk_request(struct request_queue *q)
 {
         struct virtio_blk *vblk = q->queuedata;
         struct request *req;
@@ -203,6 +399,34 @@ static void do_virtblk_request(struct request_queue *q)
                 virtqueue_kick(vblk->vq);
 }
 
+static void virtblk_make_request(struct request_queue *q, struct bio *bio)
+{
+        struct virtio_blk *vblk = q->queuedata;
+        struct virtblk_req *vbr;
+
+        BUG_ON(bio->bi_phys_segments + 2 > vblk->sg_elems);
+
+        vbr = virtblk_alloc_req(vblk, GFP_NOIO);
+        if (!vbr) {
+                bio_endio(bio, -ENOMEM);
+                return;
+        }
+
+        vbr->bio = bio;
+        vbr->flags = 0;
+        if (bio->bi_rw & REQ_FLUSH)
+                vbr->flags |= VBLK_REQ_FLUSH;
+        if (bio->bi_rw & REQ_FUA)
+                vbr->flags |= VBLK_REQ_FUA;
+        if (bio->bi_size)
+                vbr->flags |= VBLK_REQ_DATA;
+
+        if (unlikely(vbr->flags & VBLK_REQ_FLUSH))
+                virtblk_bio_send_flush(vbr);
+        else
+                virtblk_bio_send_data(vbr);
+}
+
 /* return id (s/n) string for *disk to *id_str
  */
 static int virtblk_get_id(struct gendisk *disk, char *id_str)
@@ -360,7 +584,7 @@ static int init_vq(struct virtio_blk *vblk)
         int err = 0;
 
         /* We expect one virtqueue, for output. */
-        vblk->vq = virtio_find_single_vq(vblk->vdev, blk_done, "requests");
+        vblk->vq = virtio_find_single_vq(vblk->vdev, virtblk_done, "requests");
         if (IS_ERR(vblk->vq))
                 err = PTR_ERR(vblk->vq);
 
@@ -477,6 +701,8 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
         struct virtio_blk *vblk;
         struct request_queue *q;
         int err, index;
+        int pool_size;
+
         u64 cap;
         u32 v, blk_size, sg_elems, opt_io_size;
         u16 min_io_size;
@@ -506,10 +732,12 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
                 goto out_free_index;
         }
 
+        init_waitqueue_head(&vblk->queue_wait);
         vblk->vdev = vdev;
         vblk->sg_elems = sg_elems;
         sg_init_table(vblk->sg, vblk->sg_elems);
         mutex_init(&vblk->config_lock);
+
         INIT_WORK(&vblk->config_work, virtblk_config_changed_work);
         vblk->config_enable = true;
 
@@ -517,7 +745,10 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
         if (err)
                 goto out_free_vblk;
 
-        vblk->pool = mempool_create_kmalloc_pool(1,sizeof(struct virtblk_req));
+        pool_size = sizeof(struct virtblk_req);
+        if (use_bio)
+                pool_size += sizeof(struct scatterlist) * sg_elems;
+        vblk->pool = mempool_create_kmalloc_pool(1, pool_size);
         if (!vblk->pool) {
                 err = -ENOMEM;
                 goto out_free_vq;
@@ -530,12 +761,14 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
                 goto out_mempool;
         }
 
-        q = vblk->disk->queue = blk_init_queue(do_virtblk_request, NULL);
+        q = vblk->disk->queue = blk_init_queue(virtblk_request, NULL);
         if (!q) {
                 err = -ENOMEM;
                 goto out_put_disk;
         }
 
+        if (use_bio)
+                blk_queue_make_request(q, virtblk_make_request);
         q->queuedata = vblk;
 
         virtblk_name_format("vd", index, vblk->disk->disk_name, DISK_NAME_LEN);
@@ -620,7 +853,6 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
         if (!err && opt_io_size)
                 blk_queue_io_opt(q, blk_size * opt_io_size);
 
-
         add_disk(vblk->disk);
         err = device_create_file(disk_to_dev(vblk->disk), &dev_attr_serial);
         if (err)
diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index aab9605f0b43..24ffd8cec51e 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -74,21 +74,21 @@ static inline void netwinder_ds1620_reset(void)
 
 static inline void netwinder_lock(unsigned long *flags)
 {
-        spin_lock_irqsave(&nw_gpio_lock, *flags);
+        raw_spin_lock_irqsave(&nw_gpio_lock, *flags);
 }
 
 static inline void netwinder_unlock(unsigned long *flags)
 {
-        spin_unlock_irqrestore(&nw_gpio_lock, *flags);
+        raw_spin_unlock_irqrestore(&nw_gpio_lock, *flags);
 }
 
 static inline void netwinder_set_fan(int i)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&nw_gpio_lock, flags);
+        raw_spin_lock_irqsave(&nw_gpio_lock, flags);
         nw_gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0);
-        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 static inline int netwinder_get_fan(void)
diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c
index a0e2f7d70355..e371480d3639 100644
--- a/drivers/char/nwflash.c
+++ b/drivers/char/nwflash.c
@@ -583,9 +583,9 @@ static void kick_open(void)
          * we want to write a bit pattern XXX1 to Xilinx to enable
          * the write gate, which will be open for about the next 2ms.
          */
-        spin_lock_irqsave(&nw_gpio_lock, flags);
+        raw_spin_lock_irqsave(&nw_gpio_lock, flags);
         nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
-        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 
         /*
          * let the ISA bus to catch on...
diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c
index 060a672ebb7b..8ab9c3d4bf13 100644
--- a/drivers/char/virtio_console.c
+++ b/drivers/char/virtio_console.c
@@ -24,6 +24,8 @@
 #include <linux/err.h>
 #include <linux/freezer.h>
 #include <linux/fs.h>
+#include <linux/splice.h>
+#include <linux/pagemap.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/poll.h>
@@ -474,26 +476,53 @@ static ssize_t send_control_msg(struct port *port, unsigned int event,
         return 0;
 }
 
+struct buffer_token {
+        union {
+                void *buf;
+                struct scatterlist *sg;
+        } u;
+        /* If sgpages == 0 then buf is used, else sg is used */
+        unsigned int sgpages;
+};
+
+static void reclaim_sg_pages(struct scatterlist *sg, unsigned int nrpages)
+{
+        int i;
+        struct page *page;
+
+        for (i = 0; i < nrpages; i++) {
+                page = sg_page(&sg[i]);
+                if (!page)
+                        break;
+                put_page(page);
+        }
+        kfree(sg);
+}
+
 /* Callers must take the port->outvq_lock */
 static void reclaim_consumed_buffers(struct port *port)
 {
-        void *buf;
+        struct buffer_token *tok;
         unsigned int len;
 
         if (!port->portdev) {
                 /* Device has been unplugged.  vqs are already gone. */
                 return;
         }
-        while ((buf = virtqueue_get_buf(port->out_vq, &len))) {
-                kfree(buf);
+        while ((tok = virtqueue_get_buf(port->out_vq, &len))) {
+                if (tok->sgpages)
+                        reclaim_sg_pages(tok->u.sg, tok->sgpages);
+                else
+                        kfree(tok->u.buf);
+                kfree(tok);
                 port->outvq_full = false;
         }
 }
 
-static ssize_t send_buf(struct port *port, void *in_buf, size_t in_count,
-                        bool nonblock)
+static ssize_t __send_to_port(struct port *port, struct scatterlist *sg,
+                              int nents, size_t in_count,
+                              struct buffer_token *tok, bool nonblock)
 {
-        struct scatterlist sg[1];
         struct virtqueue *out_vq;
         ssize_t ret;
         unsigned long flags;
@@ -505,8 +534,7 @@ static ssize_t send_buf(struct port *port, void *in_buf, size_t in_count,
 
         reclaim_consumed_buffers(port);
 
-        sg_init_one(sg, in_buf, in_count);
-        ret = virtqueue_add_buf(out_vq, sg, 1, 0, in_buf, GFP_ATOMIC);
+        ret = virtqueue_add_buf(out_vq, sg, nents, 0, tok, GFP_ATOMIC);
 
         /* Tell Host to go! */
         virtqueue_kick(out_vq);
@@ -544,6 +572,37 @@ done:
         return in_count;
 }
 
+static ssize_t send_buf(struct port *port, void *in_buf, size_t in_count,
+                        bool nonblock)
+{
+        struct scatterlist sg[1];
+        struct buffer_token *tok;
+
+        tok = kmalloc(sizeof(*tok), GFP_ATOMIC);
+        if (!tok)
+                return -ENOMEM;
+        tok->sgpages = 0;
+        tok->u.buf = in_buf;
+
+        sg_init_one(sg, in_buf, in_count);
+
+        return __send_to_port(port, sg, 1, in_count, tok, nonblock);
+}
+
+static ssize_t send_pages(struct port *port, struct scatterlist *sg, int nents,
+                          size_t in_count, bool nonblock)
+{
+        struct buffer_token *tok;
+
+        tok = kmalloc(sizeof(*tok), GFP_ATOMIC);
+        if (!tok)
+                return -ENOMEM;
+        tok->sgpages = nents;
+        tok->u.sg = sg;
+
+        return __send_to_port(port, sg, nents, in_count, tok, nonblock);
+}
+
 /*
  * Give out the data that's requested from the buffer that we have
  * queued up.
@@ -665,6 +724,26 @@ static ssize_t port_fops_read(struct file *filp, char __user *ubuf,
         return fill_readbuf(port, ubuf, count, true);
 }
 
+static int wait_port_writable(struct port *port, bool nonblock)
+{
+        int ret;
+
+        if (will_write_block(port)) {
+                if (nonblock)
+                        return -EAGAIN;
+
+                ret = wait_event_freezable(port->waitqueue,
+                                           !will_write_block(port));
+                if (ret < 0)
+                        return ret;
+        }
+        /* Port got hot-unplugged. */
+        if (!port->guest_connected)
+                return -ENODEV;
+
+        return 0;
+}
+
 static ssize_t port_fops_write(struct file *filp, const char __user *ubuf,
                                size_t count, loff_t *offp)
 {
@@ -681,18 +760,9 @@ static ssize_t port_fops_write(struct file *filp, const char __user *ubuf,
 
         nonblock = filp->f_flags & O_NONBLOCK;
 
-        if (will_write_block(port)) {
-                if (nonblock)
-                        return -EAGAIN;
-
-                ret = wait_event_freezable(port->waitqueue,
-                                           !will_write_block(port));
-                if (ret < 0)
-                        return ret;
-        }
-        /* Port got hot-unplugged. */
-        if (!port->guest_connected)
-                return -ENODEV;
+        ret = wait_port_writable(port, nonblock);
+        if (ret < 0)
+                return ret;
 
         count = min((size_t)(32 * 1024), count);
 
@@ -725,6 +795,93 @@ out:
         return ret;
 }
 
+struct sg_list {
+        unsigned int n;
+        unsigned int size;
+        size_t len;
+        struct scatterlist *sg;
+};
+
+static int pipe_to_sg(struct pipe_inode_info *pipe, struct pipe_buffer *buf,
+                        struct splice_desc *sd)
+{
+        struct sg_list *sgl = sd->u.data;
+        unsigned int offset, len;
+
+        if (sgl->n == sgl->size)
+                return 0;
+
+        /* Try lock this page */
+        if (buf->ops->steal(pipe, buf) == 0) {
+                /* Get reference and unlock page for moving */
+                get_page(buf->page);
+                unlock_page(buf->page);
+
+                len = min(buf->len, sd->len);
+                sg_set_page(&(sgl->sg[sgl->n]), buf->page, len, buf->offset);
+        } else {
+                /* Failback to copying a page */
+                struct page *page = alloc_page(GFP_KERNEL);
+                char *src = buf->ops->map(pipe, buf, 1);
+                char *dst;
+
+                if (!page)
+                        return -ENOMEM;
+                dst = kmap(page);
+
+                offset = sd->pos & ~PAGE_MASK;
+
+                len = sd->len;
+                if (len + offset > PAGE_SIZE)
+                        len = PAGE_SIZE - offset;
+
+                memcpy(dst + offset, src + buf->offset, len);
+
+                kunmap(page);
+                buf->ops->unmap(pipe, buf, src);
+
+                sg_set_page(&(sgl->sg[sgl->n]), page, len, offset);
+        }
+        sgl->n++;
+        sgl->len += len;
+
+        return len;
+}
+
+/* Faster zero-copy write by splicing */
+static ssize_t port_fops_splice_write(struct pipe_inode_info *pipe,
+                                      struct file *filp, loff_t *ppos,
+                                      size_t len, unsigned int flags)
+{
+        struct port *port = filp->private_data;
+        struct sg_list sgl;
+        ssize_t ret;
+        struct splice_desc sd = {
+                .total_len = len,
+                .flags = flags,
+                .pos = *ppos,
+                .u.data = &sgl,
+        };
+
+        ret = wait_port_writable(port, filp->f_flags & O_NONBLOCK);
+        if (ret < 0)
+                return ret;
+
+        sgl.n = 0;
+        sgl.len = 0;
+        sgl.size = pipe->nrbufs;
+        sgl.sg = kmalloc(sizeof(struct scatterlist) * sgl.size, GFP_KERNEL);
+        if (unlikely(!sgl.sg))
+                return -ENOMEM;
+
+        sg_init_table(sgl.sg, sgl.size);
+        ret = __splice_from_pipe(pipe, &sd, pipe_to_sg);
+        if (likely(ret > 0))
+                ret = send_pages(port, sgl.sg, sgl.n, sgl.len, true);
+
+        return ret;
+}
+
 static unsigned int port_fops_poll(struct file *filp, poll_table *wait)
 {
         struct port *port;
@@ -856,6 +1013,7 @@ static const struct file_operations port_fops = {
         .open  = port_fops_open,
         .read  = port_fops_read,
         .write = port_fops_write,
+        .splice_write = port_fops_splice_write,
         .poll  = port_fops_poll,
         .release = port_fops_release,
         .fasync = port_fops_fasync,
diff --git a/drivers/lguest/lguest_device.c b/drivers/lguest/lguest_device.c
index 9e8388efd88e..fc92ccbd71dc 100644
--- a/drivers/lguest/lguest_device.c
+++ b/drivers/lguest/lguest_device.c
@@ -263,6 +263,9 @@ static struct virtqueue *lg_find_vq(struct virtio_device *vdev,
         struct virtqueue *vq;
         int err;
 
+        if (!name)
+                return NULL;
+
         /* We must have this many virtqueues. */
         if (index >= ldev->desc->num_vq)
                 return ERR_PTR(-ENOENT);
@@ -296,7 +299,7 @@ static struct virtqueue *lg_find_vq(struct virtio_device *vdev,
          * to 'true': the host just a(nother) SMP CPU, so we only need inter-cpu
          * barriers.
          */
-        vq = vring_new_virtqueue(lvq->config.num, LGUEST_VRING_ALIGN, vdev,
+        vq = vring_new_virtqueue(index, lvq->config.num, LGUEST_VRING_ALIGN, vdev,
                                  true, lvq->pages, lg_notify, callback, name);
         if (!vq) {
                 err = -ENOMEM;
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index d43e7462941f..aa8c4dec356e 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -27,7 +27,6 @@
 
 #include <asm/gpio.h>
 
-#include <mach/gpio-tegra.h>
 #include <linux/platform_data/mmc-sdhci-tegra.h>
 
 #include "sdhci-pltfm.h"
diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c
index 3541b4492f64..e7a4780e93db 100644
--- a/drivers/remoteproc/remoteproc_virtio.c
+++ b/drivers/remoteproc/remoteproc_virtio.c
@@ -84,6 +84,9 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev,
         if (id >= ARRAY_SIZE(rvdev->vring))
                 return ERR_PTR(-EINVAL);
 
+        if (!name)
+                return NULL;
+
         ret = rproc_alloc_vring(rvdev, id);
         if (ret)
                 return ERR_PTR(ret);
@@ -103,7 +106,7 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev,
          * Create the new vq, and tell virtio we're not interested in
          * the 'weak' smp barriers, since we're talking with a real device.
          */
-        vq = vring_new_virtqueue(len, rvring->align, vdev, false, addr,
+        vq = vring_new_virtqueue(id, len, rvring->align, vdev, false, addr,
                                         rproc_virtio_notify, callback, name);
         if (!vq) {
                 dev_err(dev, "vring_new_virtqueue %s failed\n", name);
diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig
index 32aead65735a..2bd911f12571 100644
--- a/drivers/rpmsg/Kconfig
+++ b/drivers/rpmsg/Kconfig
@@ -4,7 +4,6 @@ menu "Rpmsg drivers (EXPERIMENTAL)"
 config RPMSG
         tristate
         select VIRTIO
-        select VIRTIO_RING
         depends on EXPERIMENTAL
 
 endmenu
diff --git a/drivers/s390/kvm/kvm_virtio.c b/drivers/s390/kvm/kvm_virtio.c
index 47cccd52aae8..7dabef624da3 100644
--- a/drivers/s390/kvm/kvm_virtio.c
+++ b/drivers/s390/kvm/kvm_virtio.c
@@ -190,6 +190,9 @@ static struct virtqueue *kvm_find_vq(struct virtio_device *vdev,
         if (index >= kdev->desc->num_vq)
                 return ERR_PTR(-ENOENT);
 
+        if (!name)
+                return NULL;
+
         config = kvm_vq_config(kdev->desc)+index;
 
         err = vmem_add_mapping(config->address,
@@ -198,7 +201,7 @@ static struct virtqueue *kvm_find_vq(struct virtio_device *vdev,
         if (err)
                 goto out;
 
-        vq = vring_new_virtqueue(config->num, KVM_S390_VIRTIO_RING_ALIGN,
+        vq = vring_new_virtqueue(index, config->num, KVM_S390_VIRTIO_RING_ALIGN,
                                  vdev, true, (void *) config->address,
                                  kvm_notify, callback, name);
         if (!vq) {
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index f38b17a86c35..8d5bddb56cb1 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -1,11 +1,9 @@
-# Virtio always gets selected by whoever wants it.
 config VIRTIO
         tristate
-
-# Similarly the virtio ring implementation.
-config VIRTIO_RING
-        tristate
-        depends on VIRTIO
+        ---help---
+          This option is selected by any driver which implements the virtio
+          bus, such as CONFIG_VIRTIO_PCI, CONFIG_VIRTIO_MMIO, CONFIG_LGUEST,
+          CONFIG_RPMSG or CONFIG_S390_GUEST.
 
 menu "Virtio drivers"
 
@@ -13,7 +11,6 @@ config VIRTIO_PCI
         tristate "PCI driver for virtio devices (EXPERIMENTAL)"
         depends on PCI && EXPERIMENTAL
         select VIRTIO
-        select VIRTIO_RING
         ---help---
           This drivers provides support for virtio based paravirtual device
           drivers over PCI.  This requires that your VMM has appropriate PCI
@@ -26,9 +23,8 @@ config VIRTIO_PCI
           If unsure, say M.
 
 config VIRTIO_BALLOON
-        tristate "Virtio balloon driver (EXPERIMENTAL)"
-        select VIRTIO
-        select VIRTIO_RING
+        tristate "Virtio balloon driver"
+        depends on VIRTIO
         ---help---
          This driver supports increasing and decreasing the amount
          of memory within a KVM guest.
@@ -39,7 +35,6 @@ config VIRTIO_BALLOON
         tristate "Platform bus driver for memory mapped virtio devices (EXPERIMENTAL)"
         depends on HAS_IOMEM && EXPERIMENTAL
         select VIRTIO
-        select VIRTIO_RING
         ---help---
          This drivers provides support for memory mapped virtio
          platform device driver.
diff --git a/drivers/virtio/Makefile b/drivers/virtio/Makefile
index 5a4c63cfd380..9076635697bb 100644
--- a/drivers/virtio/Makefile
+++ b/drivers/virtio/Makefile
@@ -1,5 +1,4 @@
-obj-$(CONFIG_VIRTIO) += virtio.o
-obj-$(CONFIG_VIRTIO_RING) += virtio_ring.o
+obj-$(CONFIG_VIRTIO) += virtio.o virtio_ring.o
 obj-$(CONFIG_VIRTIO_MMIO) += virtio_mmio.o
 obj-$(CONFIG_VIRTIO_PCI) += virtio_pci.o
 obj-$(CONFIG_VIRTIO_BALLOON) += virtio_balloon.o
diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c
index c3b3f7f0d9d1..1e8659ca27ef 100644
--- a/drivers/virtio/virtio.c
+++ b/drivers/virtio/virtio.c
@@ -159,7 +159,7 @@ static int virtio_dev_remove(struct device *_d)
         drv->remove(dev);
 
         /* Driver should have reset device. */
-        BUG_ON(dev->config->get_status(dev));
+        WARN_ON_ONCE(dev->config->get_status(dev));
 
         /* Acknowledge the device's existence again. */
         add_status(dev, VIRTIO_CONFIG_S_ACKNOWLEDGE);
diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index 453db0c403d8..6b1b7e184939 100644
--- a/drivers/virtio/virtio_mmio.c
+++ b/drivers/virtio/virtio_mmio.c
@@ -131,9 +131,6 @@ struct virtio_mmio_vq_info {
         /* the number of entries in the queue */
         unsigned int num;
 
-        /* the index of the queue */
-        int queue_index;
-
         /* the virtual address of the ring queue */
         void *queue;
 
@@ -225,11 +222,10 @@ static void vm_reset(struct virtio_device *vdev)
 static void vm_notify(struct virtqueue *vq)
 {
         struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vq->vdev);
-        struct virtio_mmio_vq_info *info = vq->priv;
 
         /* We write the queue's selector into the notification register to
          * signal the other end */
-        writel(info->queue_index, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY);
+        writel(virtqueue_get_queue_index(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY);
 }
 
 /* Notify all virtqueues on an interrupt. */
@@ -270,6 +266,7 @@ static void vm_del_vq(struct virtqueue *vq)
         struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vq->vdev);
         struct virtio_mmio_vq_info *info = vq->priv;
         unsigned long flags, size;
+        unsigned int index = virtqueue_get_queue_index(vq);
 
         spin_lock_irqsave(&vm_dev->lock, flags);
         list_del(&info->node);
@@ -278,7 +275,7 @@ static void vm_del_vq(struct virtqueue *vq)
         vring_del_virtqueue(vq);
 
         /* Select and deactivate the queue */
-        writel(info->queue_index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
+        writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
         writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
 
         size = PAGE_ALIGN(vring_size(info->num, VIRTIO_MMIO_VRING_ALIGN));
@@ -309,6 +306,9 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
         unsigned long flags, size;
         int err;
 
+        if (!name)
+                return NULL;
+
         /* Select the queue we're interested in */
         writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
 
@@ -324,7 +324,6 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
                 err = -ENOMEM;
                 goto error_kmalloc;
         }
-        info->queue_index = index;
 
         /* Allocate pages for the queue - start with a queue as big as
          * possible (limited by maximum size allowed by device), drop down
@@ -332,11 +331,21 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
          * and two rings (which makes it "alignment_size * 2")
          */
         info->num = readl(vm_dev->base + VIRTIO_MMIO_QUEUE_NUM_MAX);
+
+        /* If the device reports a 0 entry queue, we won't be able to
+         * use it to perform I/O, and vring_new_virtqueue() can't create
+         * empty queues anyway, so don't bother to set up the device.
+         */
+        if (info->num == 0) {
+                err = -ENOENT;
+                goto error_alloc_pages;
+        }
+
         while (1) {
                 size = PAGE_ALIGN(vring_size(info->num,
                                 VIRTIO_MMIO_VRING_ALIGN));
-                /* Already smallest possible allocation? */
-                if (size <= VIRTIO_MMIO_VRING_ALIGN * 2) {
+                /* Did the last iter shrink the queue below minimum size? */
+                if (size < VIRTIO_MMIO_VRING_ALIGN * 2) {
                         err = -ENOMEM;
                         goto error_alloc_pages;
                 }
@@ -356,7 +365,7 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
                         vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
 
         /* Create the vring */
-        vq = vring_new_virtqueue(info->num, VIRTIO_MMIO_VRING_ALIGN, vdev,
+        vq = vring_new_virtqueue(index, info->num, VIRTIO_MMIO_VRING_ALIGN, vdev,
                                  true, info->queue, vm_notify, callback, name);
         if (!vq) {
                 err = -ENOMEM;
diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/virtio_pci.c
index 2e03d416b9af..c33aea36598a 100644
--- a/drivers/virtio/virtio_pci.c
+++ b/drivers/virtio/virtio_pci.c
@@ -48,6 +48,7 @@ struct virtio_pci_device
         int msix_enabled;
         int intx_enabled;
         struct msix_entry *msix_entries;
+        cpumask_var_t *msix_affinity_masks;
         /* Name strings for interrupts. This size should be enough,
          * and I'm too lazy to allocate each name separately. */
         char (*msix_names)[256];
@@ -79,9 +80,6 @@ struct virtio_pci_vq_info
         /* the number of entries in the queue */
         int num;
 
-        /* the index of the queue */
-        int queue_index;
-
         /* the virtual address of the ring queue */
         void *queue;
 
@@ -202,11 +200,11 @@ static void vp_reset(struct virtio_device *vdev)
 static void vp_notify(struct virtqueue *vq)
 {
         struct virtio_pci_device *vp_dev = to_vp_device(vq->vdev);
-        struct virtio_pci_vq_info *info = vq->priv;
 
         /* we write the queue's selector into the notification register to
          * signal the other end */
-        iowrite16(info->queue_index, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_NOTIFY);
+        iowrite16(virtqueue_get_queue_index(vq),
+                  vp_dev->ioaddr + VIRTIO_PCI_QUEUE_NOTIFY);
 }
 
 /* Handle a configuration change: Tell driver if it wants to know. */
@@ -279,6 +277,10 @@ static void vp_free_vectors(struct virtio_device *vdev)
         for (i = 0; i < vp_dev->msix_used_vectors; ++i)
                 free_irq(vp_dev->msix_entries[i].vector, vp_dev);
 
+        for (i = 0; i < vp_dev->msix_vectors; i++)
+                if (vp_dev->msix_affinity_masks[i])
+                        free_cpumask_var(vp_dev->msix_affinity_masks[i]);
+
         if (vp_dev->msix_enabled) {
                 /* Disable the vector used for configuration */
                 iowrite16(VIRTIO_MSI_NO_VECTOR,
@@ -296,6 +298,8 @@ static void vp_free_vectors(struct virtio_device *vdev)
         vp_dev->msix_names = NULL;
         kfree(vp_dev->msix_entries);
         vp_dev->msix_entries = NULL;
+        kfree(vp_dev->msix_affinity_masks);
+        vp_dev->msix_affinity_masks = NULL;
 }
 
 static int vp_request_msix_vectors(struct virtio_device *vdev, int nvectors,
@@ -314,6 +318,15 @@ static int vp_request_msix_vectors(struct virtio_device *vdev, int nvectors,
                                      GFP_KERNEL);
         if (!vp_dev->msix_names)
                 goto error;
+        vp_dev->msix_affinity_masks
+                = kzalloc(nvectors * sizeof *vp_dev->msix_affinity_masks,
+                          GFP_KERNEL);
+        if (!vp_dev->msix_affinity_masks)
+                goto error;
+        for (i = 0; i < nvectors; ++i)
+                if (!alloc_cpumask_var(&vp_dev->msix_affinity_masks[i],
+                                        GFP_KERNEL))
+                        goto error;
 
         for (i = 0; i < nvectors; ++i)
                 vp_dev->msix_entries[i].entry = i;
@@ -402,7 +415,6 @@ static struct virtqueue *setup_vq(struct virtio_device *vdev, unsigned index,
         if (!info)
                 return ERR_PTR(-ENOMEM);
 
-        info->queue_index = index;
         info->num = num;
         info->msix_vector = msix_vec;
 
@@ -418,7 +430,7 @@ static struct virtqueue *setup_vq(struct virtio_device *vdev, unsigned index,
                   vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN);
 
         /* create the vring */
-        vq = vring_new_virtqueue(info->num, VIRTIO_PCI_VRING_ALIGN, vdev,
+        vq = vring_new_virtqueue(index, info->num, VIRTIO_PCI_VRING_ALIGN, vdev,
                                  true, info->queue, vp_notify, callback, name);
         if (!vq) {
                 err = -ENOMEM;
@@ -467,7 +479,8 @@ static void vp_del_vq(struct virtqueue *vq)
         list_del(&info->node);
         spin_unlock_irqrestore(&vp_dev->lock, flags);
 
-        iowrite16(info->queue_index, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_SEL);
+        iowrite16(virtqueue_get_queue_index(vq),
+                vp_dev->ioaddr + VIRTIO_PCI_QUEUE_SEL);
 
         if (vp_dev->msix_enabled) {
                 iowrite16(VIRTIO_MSI_NO_VECTOR,
@@ -542,7 +555,10 @@ static int vp_try_to_find_vqs(struct virtio_device *vdev, unsigned nvqs,
         vp_dev->per_vq_vectors = per_vq_vectors;
         allocated_vectors = vp_dev->msix_used_vectors;
         for (i = 0; i < nvqs; ++i) {
-                if (!callbacks[i] || !vp_dev->msix_enabled)
+                if (!names[i]) {
+                        vqs[i] = NULL;
+                        continue;
+                } else if (!callbacks[i] || !vp_dev->msix_enabled)
                         msix_vec = VIRTIO_MSI_NO_VECTOR;
                 else if (vp_dev->per_vq_vectors)
                         msix_vec = allocated_vectors++;
@@ -609,6 +625,35 @@ static const char *vp_bus_name(struct virtio_device *vdev)
         return pci_name(vp_dev->pci_dev);
 }
 
+/* Setup the affinity for a virtqueue:
+ * - force the affinity for per vq vector
+ * - OR over all affinities for shared MSI
+ * - ignore the affinity request if we're using INTX
+ */
+static int vp_set_vq_affinity(struct virtqueue *vq, int cpu)
+{
+        struct virtio_device *vdev = vq->vdev;
+        struct virtio_pci_device *vp_dev = to_vp_device(vdev);
+        struct virtio_pci_vq_info *info = vq->priv;
+        struct cpumask *mask;
+        unsigned int irq;
+
+        if (!vq->callback)
+                return -EINVAL;
+
+        if (vp_dev->msix_enabled) {
+                mask = vp_dev->msix_affinity_masks[info->msix_vector];
+                irq = vp_dev->msix_entries[info->msix_vector].vector;
+                if (cpu == -1)
+                        irq_set_affinity_hint(irq, NULL);
+                else {
+                        cpumask_set_cpu(cpu, mask);
+                        irq_set_affinity_hint(irq, mask);
+                }
+        }
+        return 0;
+}
+
 static struct virtio_config_ops virtio_pci_config_ops = {
         .get            = vp_get,
         .set            = vp_set,
@@ -620,6 +665,7 @@ static struct virtio_config_ops virtio_pci_config_ops = {
         .get_features   = vp_get_features,
         .finalize_features = vp_finalize_features,
         .bus_name       = vp_bus_name,
+        .set_vq_affinity = vp_set_vq_affinity,
 };
 
 static void virtio_pci_release_dev(struct device *_d)
@@ -673,8 +719,10 @@ static int __devinit virtio_pci_probe(struct pci_dev *pci_dev,
                 goto out_enable_device;
 
         vp_dev->ioaddr = pci_iomap(pci_dev, 0, 0);
-        if (vp_dev->ioaddr == NULL)
+        if (vp_dev->ioaddr == NULL) {
+                err = -ENOMEM;
                 goto out_req_regions;
+        }
 
         pci_set_drvdata(pci_dev, vp_dev);
         pci_set_master(pci_dev);
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 5aa43c3392a2..e639584b2dbd 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -106,6 +106,9 @@ struct vring_virtqueue
         /* How to notify other side. FIXME: commonalize hcalls! */
         void (*notify)(struct virtqueue *vq);
 
+        /* Index of the queue */
+        int queue_index;
+
 #ifdef DEBUG
         /* They're supposed to lock for us. */
         unsigned int in_use;
@@ -171,6 +174,13 @@ static int vring_add_indirect(struct vring_virtqueue *vq,
         return head;
 }
 
+int virtqueue_get_queue_index(struct virtqueue *_vq)
+{
+        struct vring_virtqueue *vq = to_vvq(_vq);
+        return vq->queue_index;
+}
+EXPORT_SYMBOL_GPL(virtqueue_get_queue_index);
+
 /**
  * virtqueue_add_buf - expose buffer to other end
  * @vq: the struct virtqueue we're talking about.
@@ -616,7 +626,8 @@ irqreturn_t vring_interrupt(int irq, void *_vq)
 }
 EXPORT_SYMBOL_GPL(vring_interrupt);
 
-struct virtqueue *vring_new_virtqueue(unsigned int num,
+struct virtqueue *vring_new_virtqueue(unsigned int index,
+                                      unsigned int num,
                                       unsigned int vring_align,
                                       struct virtio_device *vdev,
                                       bool weak_barriers,
@@ -647,6 +658,7 @@ struct virtqueue *vring_new_virtqueue(unsigned int num,
         vq->broken = false;
         vq->last_used_idx = 0;
         vq->num_added = 0;
+        vq->queue_index = index;
         list_add_tail(&vq->vq.list, &vdev->vqs);
 #ifdef DEBUG
         vq->in_use = false;
diff --git a/drivers/watchdog/m54xx_wdt.c b/drivers/watchdog/m54xx_wdt.c
index 663cad86c633..173494a681e6 100644
--- a/drivers/watchdog/m54xx_wdt.c
+++ b/drivers/watchdog/m54xx_wdt.c
@@ -46,17 +46,17 @@ static void wdt_enable(void)
         unsigned int gms0;
 
         /* preserve GPIO usage, if any */
-        gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0);
+        gms0 = __raw_readl(MCF_GPT_GMS0);
         if (gms0 & MCF_GPT_GMS_TMS_GPIO)
                 gms0 &= (MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_GPIO_MASK
                                                         | MCF_GPT_GMS_OD);
         else
                 gms0 = MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_OD;
-        __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0);
+        __raw_writel(gms0, MCF_GPT_GMS0);
         __raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0xffff)) |
-                        MCF_GPT_GCIR_CNT(0xffff), MCF_MBAR + MCF_GPT_GCIR0);
+                        MCF_GPT_GCIR_CNT(0xffff), MCF_GPT_GCIR0);
         gms0 |= MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE;
-        __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0);
+        __raw_writel(gms0, MCF_GPT_GMS0);
 }
 
 static void wdt_disable(void)
@@ -64,18 +64,18 @@ static void wdt_disable(void)
         unsigned int gms0;
 
         /* disable watchdog */
-        gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0);
+        gms0 = __raw_readl(MCF_GPT_GMS0);
         gms0 &= ~(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE);
-        __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0);
+        __raw_writel(gms0, MCF_GPT_GMS0);
 }
 
 static void wdt_keepalive(void)
 {
         unsigned int gms0;
 
-        gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0);
+        gms0 = __raw_readl(MCF_GPT_GMS0);
         gms0 |= MCF_GPT_GMS_OCPW(0xA5);
-        __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0);
+        __raw_writel(gms0, MCF_GPT_GMS0);
 }
 
 static int m54xx_wdt_open(struct inode *inode, struct file *file)
@@ -195,8 +195,7 @@ static struct miscdevice m54xx_wdt_miscdev = {
 
 static int __init m54xx_wdt_init(void)
 {
-        if (!request_mem_region(MCF_MBAR + MCF_GPT_GCIR0, 4,
-                                                "Coldfire M54xx Watchdog")) {
+        if (!request_mem_region(MCF_GPT_GCIR0, 4, "Coldfire M54xx Watchdog")) {
                 pr_warn("I/O region busy\n");
                 return -EBUSY;
         }
@@ -208,7 +207,7 @@ static int __init m54xx_wdt_init(void)
 static void __exit m54xx_wdt_exit(void)
 {
         misc_deregister(&m54xx_wdt_miscdev);
-        release_mem_region(MCF_MBAR + MCF_GPT_GCIR0, 4);
+        release_mem_region(MCF_GPT_GCIR0, 4);
 }
 
 module_init(m54xx_wdt_init);
diff --git a/include/linux/virtio.h b/include/linux/virtio.h
index a1ba8bbd9fbe..533b1157f22e 100644
--- a/include/linux/virtio.h
+++ b/include/linux/virtio.h
@@ -50,6 +50,8 @@ void *virtqueue_detach_unused_buf(struct virtqueue *vq);
 
 unsigned int virtqueue_get_vring_size(struct virtqueue *vq);
 
+int virtqueue_get_queue_index(struct virtqueue *vq);
+
 /**
  * virtio_device - representation of a device using virtio
  * @index: unique position on the virtio bus
diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h
index fc457f452f64..e2850a7ea276 100644
--- a/include/linux/virtio_config.h
+++ b/include/linux/virtio_config.h
@@ -84,7 +84,9 @@
  *      nvqs: the number of virtqueues to find
  *      vqs: on success, includes new virtqueues
  *      callbacks: array of callbacks, for each virtqueue
+ *              include a NULL entry for vqs that do not need a callback
  *      names: array of virtqueue names (mainly for debugging)
+ *              include a NULL entry for vqs unused by driver
  *      Returns 0 on success or error status
  * @del_vqs: free virtqueues found by find_vqs().
  * @get_features: get the array of feature bits for this device.
@@ -98,6 +100,7 @@
  *      vdev: the virtio_device
  *      This returns a pointer to the bus name a la pci_name from which
  *      the caller can then copy.
+ * @set_vq_affinity: set the affinity for a virtqueue.
  */
 typedef void vq_callback_t(struct virtqueue *);
 struct virtio_config_ops {
@@ -116,6 +119,7 @@ struct virtio_config_ops {
         u32 (*get_features)(struct virtio_device *vdev);
         void (*finalize_features)(struct virtio_device *vdev);
         const char *(*bus_name)(struct virtio_device *vdev);
+        int (*set_vq_affinity)(struct virtqueue *vq, int cpu);
 };
 
 /* If driver didn't advertise the feature, it will never appear. */
@@ -190,5 +194,24 @@ const char *virtio_bus_name(struct virtio_device *vdev)
         return vdev->config->bus_name(vdev);
 }
 
+/**
+ * virtqueue_set_affinity - setting affinity for a virtqueue
+ * @vq: the virtqueue
+ * @cpu: the cpu no.
+ *
+ * Pay attention the function are best-effort: the affinity hint may not be set
+ * due to config support, irq type and sharing.
+ *
+ */
+static inline
+int virtqueue_set_affinity(struct virtqueue *vq, int cpu)
+{
+        struct virtio_device *vdev = vq->vdev;
+        if (vdev->config->set_vq_affinity)
+                return vdev->config->set_vq_affinity(vq, cpu);
+        return 0;
+}
+
+
 #endif /* __KERNEL__ */
 #endif /* _LINUX_VIRTIO_CONFIG_H */
diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h
index e338730c2660..c2d793a06ad7 100644
--- a/include/linux/virtio_ring.h
+++ b/include/linux/virtio_ring.h
@@ -165,7 +165,8 @@ static inline int vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old)
 struct virtio_device;
 struct virtqueue;
 
-struct virtqueue *vring_new_virtqueue(unsigned int num,
+struct virtqueue *vring_new_virtqueue(unsigned int index,
+                                      unsigned int num,
                                       unsigned int vring_align,
                                       struct virtio_device *vdev,
                                       bool weak_barriers,
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index cdcb59450b49..31e4f55773f1 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -4200,12 +4200,6 @@ static void buffer_pipe_buf_release(struct pipe_inode_info *pipe,
         buf->private = 0;
 }
 
-static int buffer_pipe_buf_steal(struct pipe_inode_info *pipe,
-                                 struct pipe_buffer *buf)
-{
-        return 1;
-}
-
 static void buffer_pipe_buf_get(struct pipe_inode_info *pipe,
                                 struct pipe_buffer *buf)
 {
@@ -4221,7 +4215,7 @@ static const struct pipe_buf_operations buffer_pipe_buf_ops = {
         .unmap                  = generic_pipe_buf_unmap,
         .confirm                = generic_pipe_buf_confirm,
         .release                = buffer_pipe_buf_release,
-        .steal                  = buffer_pipe_buf_steal,
+        .steal                  = generic_pipe_buf_steal,
         .get                    = buffer_pipe_buf_get,
 };
 
diff --git a/security/integrity/ima/ima.h b/security/integrity/ima/ima.h
index 8180adde10b7..6ee8826662cc 100644
--- a/security/integrity/ima/ima.h
+++ b/security/integrity/ima/ima.h
@@ -143,7 +143,7 @@ void ima_delete_rules(void);
 #ifdef CONFIG_IMA_APPRAISE
 int ima_appraise_measurement(struct integrity_iint_cache *iint,
                              struct file *file, const unsigned char *filename);
-int ima_must_appraise(struct inode *inode, enum ima_hooks func, int mask);
+int ima_must_appraise(struct inode *inode, int mask, enum ima_hooks func);
 void ima_update_xattr(struct integrity_iint_cache *iint, struct file *file);
 
 #else
@@ -154,8 +154,8 @@ static inline int ima_appraise_measurement(struct integrity_iint_cache *iint,
         return INTEGRITY_UNKNOWN;
 }
 
-static inline int ima_must_appraise(struct inode *inode,
-                                    enum ima_hooks func, int mask)
+static inline int ima_must_appraise(struct inode *inode, int mask,
+                                    enum ima_hooks func)
 {
         return 0;
 }
diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c
index 0aa43bde441c..bdc8ba1d1d27 100644
--- a/security/integrity/ima/ima_appraise.c
+++ b/security/integrity/ima/ima_appraise.c
@@ -34,7 +34,7 @@ __setup("ima_appraise=", default_appraise_setup);
  *
  * Return 1 to appraise
  */
-int ima_must_appraise(struct inode *inode, enum ima_hooks func, int mask)
+int ima_must_appraise(struct inode *inode, int mask, enum ima_hooks func)
 {
         if (!ima_appraise)
                 return 0;
diff --git a/sound/oss/waveartist.c b/sound/oss/waveartist.c
index 24c430f721d4..672af8b56542 100644
--- a/sound/oss/waveartist.c
+++ b/sound/oss/waveartist.c
@@ -1482,9 +1482,9 @@ vnc_mute_spkr(wavnc_info *devc)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&nw_gpio_lock, flags);
+        raw_spin_lock_irqsave(&nw_gpio_lock, flags);
         nw_cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE);
-        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 static void
diff --git a/tools/lguest/lguest.c b/tools/lguest/lguest.c
index f759f4f097c7..fd2f9221b241 100644
--- a/tools/lguest/lguest.c
+++ b/tools/lguest/lguest.c
@@ -1299,6 +1299,7 @@ static struct device *new_device(const char *name, u16 type)
         dev->feature_len = 0;
         dev->num_vq = 0;
         dev->running = false;
+        dev->next = NULL;
 
         /*
          * Append to device list.  Prepending to a single-linked list is
diff --git a/tools/virtio/virtio-trace/Makefile b/tools/virtio/virtio-trace/Makefile
new file mode 100644
index 000000000000..0d2381633475
--- /dev/null
+++ b/tools/virtio/virtio-trace/Makefile
@@ -0,0 +1,13 @@
+CC = gcc
+CFLAGS = -O2 -Wall -pthread
+
+all: trace-agent
+
+.c.o:
+        $(CC) $(CFLAGS) -c $^ -o $@
+
+trace-agent: trace-agent.o trace-agent-ctl.o trace-agent-rw.o
+        $(CC) $(CFLAGS) -o $@ $^
+
+clean:
+        rm -f *.o trace-agent
diff --git a/tools/virtio/virtio-trace/README b/tools/virtio/virtio-trace/README
new file mode 100644
index 000000000000..b64845b823ab
--- /dev/null
+++ b/tools/virtio/virtio-trace/README
@@ -0,0 +1,118 @@
+Trace Agent for virtio-trace
+============================
+
+Trace agent is a user tool for sending trace data of a guest to a Host in low
+overhead. Trace agent has the following functions:
+ - splice a page of ring-buffer to read_pipe without memory copying
+ - splice the page from write_pipe to virtio-console without memory copying
+ - write trace data to stdout by using -o option
+ - controlled by start/stop orders from a Host
+
+The trace agent operates as follows:
+ 1) Initialize all structures.
+ 2) Create a read/write thread per CPU. Each thread is bound to a CPU.
+    The read/write threads hold it.
+ 3) A controller thread does poll() for a start order of a host.
+ 4) After the controller of the trace agent receives a start order from a host,
+    the controller wake read/write threads.
+ 5) The read/write threads start to read trace data from ring-buffers and
+    write the data to virtio-serial.
+ 6) If the controller receives a stop order from a host, the read/write threads
+    stop to read trace data.
+
+
+Files
+=====
+
+README: this file
+Makefile: Makefile of trace agent for virtio-trace
+trace-agent.c: includes main function, sets up for operating trace agent
+trace-agent.h: includes all structures and some macros
+trace-agent-ctl.c: includes controller function for read/write threads
+trace-agent-rw.c: includes read/write threads function
+
+
+Setup
+=====
+
+To use this trace agent for virtio-trace, we need to prepare some virtio-serial
+I/Fs.
+
+1) Make FIFO in a host
+ virtio-trace uses virtio-serial pipe as trace data paths as to the number
+of CPUs and a control path, so FIFO (named pipe) should be created as follows:
+        # mkdir /tmp/virtio-trace/
+        # mkfifo /tmp/virtio-trace/trace-path-cpu{0,1,2,...,X}.{in,out}
+        # mkfifo /tmp/virtio-trace/agent-ctl-path.{in,out}
+
+For example, if a guest use three CPUs, the names are
+        trace-path-cpu{0,1,2}.{in.out}
+and
+        agent-ctl-path.{in,out}.
+
+2) Set up of virtio-serial pipe in a host
+ Add qemu option to use virtio-serial pipe.
+
+ ##virtio-serial device##
+     -device virtio-serial-pci,id=virtio-serial0\
+ ##control path##
+     -chardev pipe,id=charchannel0,path=/tmp/virtio-trace/agent-ctl-path\
+     -device virtserialport,bus=virtio-serial0.0,nr=1,chardev=charchannel0,\
+      id=channel0,name=agent-ctl-path\
+ ##data path##
+     -chardev pipe,id=charchannel1,path=/tmp/virtio-trace/trace-path-cpu0\
+     -device virtserialport,bus=virtio-serial0.0,nr=2,chardev=charchannel0,\
+      id=channel1,name=trace-path-cpu0\
+      ...
+
+If you manage guests with libvirt, add the following tags to domain XML files.
+Then, libvirt passes the same command option to qemu.
+
+        <channel type='pipe'>
+           <source path='/tmp/virtio-trace/agent-ctl-path'/>
+           <target type='virtio' name='agent-ctl-path'/>
+           <address type='virtio-serial' controller='0' bus='0' port='0'/>
+        </channel>
+        <channel type='pipe'>
+           <source path='/tmp/virtio-trace/trace-path-cpu0'/>
+           <target type='virtio' name='trace-path-cpu0'/>
+           <address type='virtio-serial' controller='0' bus='0' port='1'/>
+        </channel>
+        ...
+Here, chardev names are restricted to trace-path-cpuX and agent-ctl-path. For
+example, if a guest use three CPUs, chardev names should be trace-path-cpu0,
+trace-path-cpu1, trace-path-cpu2, and agent-ctl-path.
+
+3) Boot the guest
+ You can find some chardev in /dev/virtio-ports/ in the guest.
+
+
+Run
+===
+
+0) Build trace agent in a guest
+        $ make
+
+1) Enable ftrace in the guest
+ <Example>
+        # echo 1 > /sys/kernel/debug/tracing/events/sched/enable
+
+2) Run trace agent in the guest
+ This agent must be operated as root.
+        # ./trace-agent
+read/write threads in the agent wait for start order from host. If you add -o
+option, trace data are output via stdout in the guest.
+
+3) Open FIFO in a host
+        # cat /tmp/virtio-trace/trace-path-cpu0.out
+If a host does not open these, trace data get stuck in buffers of virtio. Then,
+the guest will stop by specification of chardev in QEMU. This blocking mode may
+be solved in the future.
+
+4) Start to read trace data by ordering from a host
+ A host injects read start order to the guest via virtio-serial.
+        # echo 1 > /tmp/virtio-trace/agent-ctl-path.in
+
+5) Stop to read trace data by ordering from a host
+ A host injects read stop order to the guest via virtio-serial.
+        # echo 0 > /tmp/virtio-trace/agent-ctl-path.in
diff --git a/tools/virtio/virtio-trace/trace-agent-ctl.c b/tools/virtio/virtio-trace/trace-agent-ctl.c
new file mode 100644
index 000000000000..a2d0403c4f94
--- /dev/null
+++ b/tools/virtio/virtio-trace/trace-agent-ctl.c
@@ -0,0 +1,137 @@
+/*
+ * Controller of read/write threads for virtio-trace
+ *
+ * Copyright (C) 2012 Hitachi, Ltd.
+ * Created by Yoshihiro Yunomae <yoshihiro.yunomae.ez@hitachi.com>
+ *            Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
+ *
+ * Licensed under GPL version 2 only.
+ *
+ */
+
+#define _GNU_SOURCE
+#include <fcntl.h>
+#include <poll.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include "trace-agent.h"
+
+#define HOST_MSG_SIZE           256
+#define EVENT_WAIT_MSEC         100
+
+static volatile sig_atomic_t global_signal_val;
+bool global_sig_receive;        /* default false */
+bool global_run_operation;      /* default false*/
+
+/* Handle SIGTERM/SIGINT/SIGQUIT to exit */
+static void signal_handler(int sig)
+{
+        global_signal_val = sig;
+}
+
+int rw_ctl_init(const char *ctl_path)
+{
+        int ctl_fd;
+
+        ctl_fd = open(ctl_path, O_RDONLY);
+        if (ctl_fd == -1) {
+                pr_err("Cannot open ctl_fd\n");
+                goto error;
+        }
+
+        return ctl_fd;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+static int wait_order(int ctl_fd)
+{
+        struct pollfd poll_fd;
+        int ret = 0;
+
+        while (!global_sig_receive) {
+                poll_fd.fd = ctl_fd;
+                poll_fd.events = POLLIN;
+
+                ret = poll(&poll_fd, 1, EVENT_WAIT_MSEC);
+
+                if (global_signal_val) {
+                        global_sig_receive = true;
+                        pr_info("Receive interrupt %d\n", global_signal_val);
+
+                        /* Wakes rw-threads when they are sleeping */
+                        if (!global_run_operation)
+                                pthread_cond_broadcast(&cond_wakeup);
+
+                        ret = -1;
+                        break;
+                }
+
+                if (ret < 0) {
+                        pr_err("Polling error\n");
+                        goto error;
+                }
+
+                if (ret)
+                        break;
+        };
+
+        return ret;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+/*
+ * contol read/write threads by handling global_run_operation
+ */
+void *rw_ctl_loop(int ctl_fd)
+{
+        ssize_t rlen;
+        char buf[HOST_MSG_SIZE];
+        int ret;
+
+        /* Setup signal handlers */
+        signal(SIGTERM, signal_handler);
+        signal(SIGINT, signal_handler);
+        signal(SIGQUIT, signal_handler);
+
+        while (!global_sig_receive) {
+
+                ret = wait_order(ctl_fd);
+                if (ret < 0)
+                        break;
+
+                rlen = read(ctl_fd, buf, sizeof(buf));
+                if (rlen < 0) {
+                        pr_err("read data error in ctl thread\n");
+                        goto error;
+                }
+
+                if (rlen == 2 && buf[0] == '1') {
+                        /*
+                         * If host writes '1' to a control path,
+                         * this controller wakes all read/write threads.
+                         */
+                        global_run_operation = true;
+                        pthread_cond_broadcast(&cond_wakeup);
+                        pr_debug("Wake up all read/write threads\n");
+                } else if (rlen == 2 && buf[0] == '0') {
+                        /*
+                         * If host writes '0' to a control path, read/write
+                         * threads will wait for notification from Host.
+                         */
+                        global_run_operation = false;
+                        pr_debug("Stop all read/write threads\n");
+                } else
+                        pr_info("Invalid host notification: %s\n", buf);
+        }
+
+        return NULL;
+
+error:
+        exit(EXIT_FAILURE);
+}
diff --git a/tools/virtio/virtio-trace/trace-agent-rw.c b/tools/virtio/virtio-trace/trace-agent-rw.c
new file mode 100644
index 000000000000..3aace5ea4842
--- /dev/null
+++ b/tools/virtio/virtio-trace/trace-agent-rw.c
@@ -0,0 +1,192 @@
+/*
+ * Read/write thread of a guest agent for virtio-trace
+ *
+ * Copyright (C) 2012 Hitachi, Ltd.
+ * Created by Yoshihiro Yunomae <yoshihiro.yunomae.ez@hitachi.com>
+ *            Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
+ *
+ * Licensed under GPL version 2 only.
+ *
+ */
+
+#define _GNU_SOURCE
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/syscall.h>
+#include "trace-agent.h"
+
+#define READ_WAIT_USEC  100000
+
+void *rw_thread_info_new(void)
+{
+        struct rw_thread_info *rw_ti;
+
+        rw_ti = zalloc(sizeof(struct rw_thread_info));
+        if (rw_ti == NULL) {
+                pr_err("rw_thread_info zalloc error\n");
+                exit(EXIT_FAILURE);
+        }
+
+        rw_ti->cpu_num = -1;
+        rw_ti->in_fd = -1;
+        rw_ti->out_fd = -1;
+        rw_ti->read_pipe = -1;
+        rw_ti->write_pipe = -1;
+        rw_ti->pipe_size = PIPE_INIT;
+
+        return rw_ti;
+}
+
+void *rw_thread_init(int cpu, const char *in_path, const char *out_path,
+                                bool stdout_flag, unsigned long pipe_size,
+                                struct rw_thread_info *rw_ti)
+{
+        int data_pipe[2];
+
+        rw_ti->cpu_num = cpu;
+
+        /* set read(input) fd */
+        rw_ti->in_fd = open(in_path, O_RDONLY);
+        if (rw_ti->in_fd == -1) {
+                pr_err("Could not open in_fd (CPU:%d)\n", cpu);
+                goto error;
+        }
+
+        /* set write(output) fd */
+        if (!stdout_flag) {
+                /* virtio-serial output mode */
+                rw_ti->out_fd = open(out_path, O_WRONLY);
+                if (rw_ti->out_fd == -1) {
+                        pr_err("Could not open out_fd (CPU:%d)\n", cpu);
+                        goto error;
+                }
+        } else
+                /* stdout mode */
+                rw_ti->out_fd = STDOUT_FILENO;
+
+        if (pipe2(data_pipe, O_NONBLOCK) < 0) {
+                pr_err("Could not create pipe in rw-thread(%d)\n", cpu);
+                goto error;
+        }
+
+        /*
+         * Size of pipe is 64kB in default based on fs/pipe.c.
+         * To read/write trace data speedy, pipe size is changed.
+         */
+        if (fcntl(*data_pipe, F_SETPIPE_SZ, pipe_size) < 0) {
+                pr_err("Could not change pipe size in rw-thread(%d)\n", cpu);
+                goto error;
+        }
+
+        rw_ti->read_pipe = data_pipe[1];
+        rw_ti->write_pipe = data_pipe[0];
+        rw_ti->pipe_size = pipe_size;
+
+        return NULL;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+/* Bind a thread to a cpu */
+static void bind_cpu(int cpu_num)
+{
+        cpu_set_t mask;
+
+        CPU_ZERO(&mask);
+        CPU_SET(cpu_num, &mask);
+
+        /* bind my thread to cpu_num by assigning zero to the first argument */
+        if (sched_setaffinity(0, sizeof(mask), &mask) == -1)
+                pr_err("Could not set CPU#%d affinity\n", (int)cpu_num);
+}
+
+static void *rw_thread_main(void *thread_info)
+{
+        ssize_t rlen, wlen;
+        ssize_t ret;
+        struct rw_thread_info *ts = (struct rw_thread_info *)thread_info;
+
+        bind_cpu(ts->cpu_num);
+
+        while (1) {
+                /* Wait for a read order of trace data by Host OS */
+                if (!global_run_operation) {
+                        pthread_mutex_lock(&mutex_notify);
+                        pthread_cond_wait(&cond_wakeup, &mutex_notify);
+                        pthread_mutex_unlock(&mutex_notify);
+                }
+
+                if (global_sig_receive)
+                        break;
+
+                /*
+                 * Each thread read trace_pipe_raw of each cpu bounding the
+                 * thread, so contention of multi-threads does not occur.
+                 */
+                rlen = splice(ts->in_fd, NULL, ts->read_pipe, NULL,
+                                ts->pipe_size, SPLICE_F_MOVE | SPLICE_F_MORE);
+
+                if (rlen < 0) {
+                        pr_err("Splice_read in rw-thread(%d)\n", ts->cpu_num);
+                        goto error;
+                } else if (rlen == 0) {
+                        /*
+                         * If trace data do not exist or are unreadable not
+                         * for exceeding the page size, splice_read returns
+                         * NULL. Then, this waits for being filled the data in a
+                         * ring-buffer.
+                         */
+                        usleep(READ_WAIT_USEC);
+                        pr_debug("Read retry(cpu:%d)\n", ts->cpu_num);
+                        continue;
+                }
+
+                wlen = 0;
+
+                do {
+                        ret = splice(ts->write_pipe, NULL, ts->out_fd, NULL,
+                                        rlen - wlen,
+                                        SPLICE_F_MOVE | SPLICE_F_MORE);
+
+                        if (ret < 0) {
+                                pr_err("Splice_write in rw-thread(%d)\n",
+                                                                ts->cpu_num);
+                                goto error;
+                        } else if (ret == 0)
+                                /*
+                                 * When host reader is not in time for reading
+                                 * trace data, guest will be stopped. This is
+                                 * because char dev in QEMU is not supported
+                                 * non-blocking mode. Then, writer might be
+                                 * sleep in that case.
+                                 * This sleep will be removed by supporting
+                                 * non-blocking mode.
+                                 */
+                                sleep(1);
+                        wlen += ret;
+                } while (wlen < rlen);
+        }
+
+        return NULL;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+
+pthread_t rw_thread_run(struct rw_thread_info *rw_ti)
+{
+        int ret;
+        pthread_t rw_thread_per_cpu;
+
+        ret = pthread_create(&rw_thread_per_cpu, NULL, rw_thread_main, rw_ti);
+        if (ret != 0) {
+                pr_err("Could not create a rw thread(%d)\n", rw_ti->cpu_num);
+                exit(EXIT_FAILURE);
+        }
+
+        return rw_thread_per_cpu;
+}
diff --git a/tools/virtio/virtio-trace/trace-agent.c b/tools/virtio/virtio-trace/trace-agent.c
new file mode 100644
index 000000000000..0a0a7dd4eff7
--- /dev/null
+++ b/tools/virtio/virtio-trace/trace-agent.c
@@ -0,0 +1,270 @@
+/*
+ * Guest agent for virtio-trace
+ *
+ * Copyright (C) 2012 Hitachi, Ltd.
+ * Created by Yoshihiro Yunomae <yoshihiro.yunomae.ez@hitachi.com>
+ *            Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
+ *
+ * Licensed under GPL version 2 only.
+ *
+ */
+
+#define _GNU_SOURCE
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include "trace-agent.h"
+
+#define PAGE_SIZE               (sysconf(_SC_PAGE_SIZE))
+#define PIPE_DEF_BUFS           16
+#define PIPE_MIN_SIZE           (PAGE_SIZE*PIPE_DEF_BUFS)
+#define PIPE_MAX_SIZE           (1024*1024)
+#define READ_PATH_FMT   \
+                "/sys/kernel/debug/tracing/per_cpu/cpu%d/trace_pipe_raw"
+#define WRITE_PATH_FMT          "/dev/virtio-ports/trace-path-cpu%d"
+#define CTL_PATH                "/dev/virtio-ports/agent-ctl-path"
+
+pthread_mutex_t mutex_notify = PTHREAD_MUTEX_INITIALIZER;
+pthread_cond_t cond_wakeup = PTHREAD_COND_INITIALIZER;
+
+static int get_total_cpus(void)
+{
+        int nr_cpus = (int)sysconf(_SC_NPROCESSORS_CONF);
+
+        if (nr_cpus <= 0) {
+                pr_err("Could not read cpus\n");
+                goto error;
+        } else if (nr_cpus > MAX_CPUS) {
+                pr_err("Exceed max cpus(%d)\n", (int)MAX_CPUS);
+                goto error;
+        }
+
+        return nr_cpus;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+static void *agent_info_new(void)
+{
+        struct agent_info *s;
+        int i;
+
+        s = zalloc(sizeof(struct agent_info));
+        if (s == NULL) {
+                pr_err("agent_info zalloc error\n");
+                exit(EXIT_FAILURE);
+        }
+
+        s->pipe_size = PIPE_INIT;
+        s->use_stdout = false;
+        s->cpus = get_total_cpus();
+        s->ctl_fd = -1;
+
+        /* read/write threads init */
+        for (i = 0; i < s->cpus; i++)
+                s->rw_ti[i] = rw_thread_info_new();
+
+        return s;
+}
+
+static unsigned long parse_size(const char *arg)
+{
+        unsigned long value, round;
+        char *ptr;
+
+        value = strtoul(arg, &ptr, 10);
+        switch (*ptr) {
+        case 'K': case 'k':
+                value <<= 10;
+                break;
+        case 'M': case 'm':
+                value <<= 20;
+                break;
+        default:
+                break;
+        }
+
+        if (value > PIPE_MAX_SIZE) {
+                pr_err("Pipe size must be less than 1MB\n");
+                goto error;
+        } else if (value < PIPE_MIN_SIZE) {
+                pr_err("Pipe size must be over 64KB\n");
+                goto error;
+        }
+
+        /* Align buffer size with page unit */
+        round = value & (PAGE_SIZE - 1);
+        value = value - round;
+
+        return value;
+error:
+        return 0;
+}
+
+static void usage(char const *prg)
+{
+        pr_err("usage: %s [-h] [-o] [-s <size of pipe>]\n", prg);
+}
+
+static const char *make_path(int cpu_num, bool this_is_write_path)
+{
+        int ret;
+        char *buf;
+
+        buf = zalloc(PATH_MAX);
+        if (buf == NULL) {
+                pr_err("Could not allocate buffer\n");
+                goto error;
+        }
+
+        if (this_is_write_path)
+                /* write(output) path */
+                ret = snprintf(buf, PATH_MAX, WRITE_PATH_FMT, cpu_num);
+        else
+                /* read(input) path */
+                ret = snprintf(buf, PATH_MAX, READ_PATH_FMT, cpu_num);
+
+        if (ret <= 0) {
+                pr_err("Failed to generate %s path(CPU#%d):%d\n",
+                        this_is_write_path ? "read" : "write", cpu_num, ret);
+                goto error;
+        }
+
+        return buf;
+
+error:
+        free(buf);
+        return NULL;
+}
+
+static const char *make_input_path(int cpu_num)
+{
+        return make_path(cpu_num, false);
+}
+
+static const char *make_output_path(int cpu_num)
+{
+        return make_path(cpu_num, true);
+}
+
+static void *agent_info_init(struct agent_info *s)
+{
+        int cpu;
+        const char *in_path = NULL;
+        const char *out_path = NULL;
+
+        /* init read/write threads */
+        for (cpu = 0; cpu < s->cpus; cpu++) {
+                /* set read(input) path per read/write thread */
+                in_path = make_input_path(cpu);
+                if (in_path == NULL)
+                        goto error;
+
+                /* set write(output) path per read/write thread*/
+                if (!s->use_stdout) {
+                        out_path = make_output_path(cpu);
+                        if (out_path == NULL)
+                                goto error;
+                } else
+                        /* stdout mode */
+                        pr_debug("stdout mode\n");
+
+                rw_thread_init(cpu, in_path, out_path, s->use_stdout,
+                                                s->pipe_size, s->rw_ti[cpu]);
+        }
+
+        /* init controller of read/write threads */
+        s->ctl_fd = rw_ctl_init((const char *)CTL_PATH);
+
+        return NULL;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+static void *parse_args(int argc, char *argv[], struct agent_info *s)
+{
+        int cmd;
+        unsigned long size;
+
+        while ((cmd = getopt(argc, argv, "hos:")) != -1) {
+                switch (cmd) {
+                /* stdout mode */
+                case 'o':
+                        s->use_stdout = true;
+                        break;
+                /* size of pipe */
+                case 's':
+                        size = parse_size(optarg);
+                        if (size == 0)
+                                goto error;
+                        s->pipe_size = size;
+                        break;
+                case 'h':
+                default:
+                        usage(argv[0]);
+                        goto error;
+                }
+        }
+
+        agent_info_init(s);
+
+        return NULL;
+
+error:
+        exit(EXIT_FAILURE);
+}
+
+static void agent_main_loop(struct agent_info *s)
+{
+        int cpu;
+        pthread_t rw_thread_per_cpu[MAX_CPUS];
+
+        /* Start all read/write threads */
+        for (cpu = 0; cpu < s->cpus; cpu++)
+                rw_thread_per_cpu[cpu] = rw_thread_run(s->rw_ti[cpu]);
+
+        rw_ctl_loop(s->ctl_fd);
+
+        /* Finish all read/write threads */
+        for (cpu = 0; cpu < s->cpus; cpu++) {
+                int ret;
+
+                ret = pthread_join(rw_thread_per_cpu[cpu], NULL);
+                if (ret != 0) {
+                        pr_err("pthread_join() error:%d (cpu %d)\n", ret, cpu);
+                        exit(EXIT_FAILURE);
+                }
+        }
+}
+
+static void agent_info_free(struct agent_info *s)
+{
+        int i;
+
+        close(s->ctl_fd);
+        for (i = 0; i < s->cpus; i++) {
+                close(s->rw_ti[i]->in_fd);
+                close(s->rw_ti[i]->out_fd);
+                close(s->rw_ti[i]->read_pipe);
+                close(s->rw_ti[i]->write_pipe);
+                free(s->rw_ti[i]);
+        }
+        free(s);
+}
+
+int main(int argc, char *argv[])
+{
+        struct agent_info *s = NULL;
+
+        s = agent_info_new();
+        parse_args(argc, argv, s);
+
+        agent_main_loop(s);
+
+        agent_info_free(s);
+
+        return 0;
+}
diff --git a/tools/virtio/virtio-trace/trace-agent.h b/tools/virtio/virtio-trace/trace-agent.h
new file mode 100644
index 000000000000..8de79bfeaa73
--- /dev/null
+++ b/tools/virtio/virtio-trace/trace-agent.h
@@ -0,0 +1,75 @@
+#ifndef __TRACE_AGENT_H__
+#define __TRACE_AGENT_H__
+#include <pthread.h>
+#include <stdbool.h>
+
+#define MAX_CPUS        256
+#define PIPE_INIT       (1024*1024)
+
+/*
+ * agent_info - structure managing total information of guest agent
+ * @pipe_size:  size of pipe (default 1MB)
+ * @use_stdout: set to true when o option is added (default false)
+ * @cpus:       total number of CPUs
+ * @ctl_fd:     fd of control path, /dev/virtio-ports/agent-ctl-path
+ * @rw_ti:      structure managing information of read/write threads
+ */
+struct agent_info {
+        unsigned long pipe_size;
+        bool use_stdout;
+        int cpus;
+        int ctl_fd;
+        struct rw_thread_info *rw_ti[MAX_CPUS];
+};
+
+/*
+ * rw_thread_info - structure managing a read/write thread a cpu
+ * @cpu_num:    cpu number operating this read/write thread
+ * @in_fd:      fd of reading trace data path in cpu_num
+ * @out_fd:     fd of writing trace data path in cpu_num
+ * @read_pipe:  fd of read pipe
+ * @write_pipe: fd of write pipe
+ * @pipe_size:  size of pipe (default 1MB)
+ */
+struct rw_thread_info {
+        int cpu_num;
+        int in_fd;
+        int out_fd;
+        int read_pipe;
+        int write_pipe;
+        unsigned long pipe_size;
+};
+
+/* use for stopping rw threads */
+extern bool global_sig_receive;
+
+/* use for notification */
+extern bool global_run_operation;
+extern pthread_mutex_t mutex_notify;
+extern pthread_cond_t cond_wakeup;
+
+/* for controller of read/write threads */
+extern int rw_ctl_init(const char *ctl_path);
+extern void *rw_ctl_loop(int ctl_fd);
+
+/* for trace read/write thread */
+extern void *rw_thread_info_new(void);
+extern void *rw_thread_init(int cpu, const char *in_path, const char *out_path,
+                        bool stdout_flag, unsigned long pipe_size,
+                        struct rw_thread_info *rw_ti);
+extern pthread_t rw_thread_run(struct rw_thread_info *rw_ti);
+
+static inline void *zalloc(size_t size)
+{
+        return calloc(1, size);
+}
+
+#define pr_err(format, ...) fprintf(stderr, format, ## __VA_ARGS__)
+#define pr_info(format, ...) fprintf(stdout, format, ## __VA_ARGS__)
+#ifdef DEBUG
+#define pr_debug(format, ...) fprintf(stderr, format, ## __VA_ARGS__)
+#else
+#define pr_debug(format, ...) do {} while (0)
+#endif
+
+#endif /*__TRACE_AGENT_H__*/