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-rw-r--r--drivers/scsi/bfa/bfa.h14
-rw-r--r--drivers/scsi/bfa/bfa_core.c209
-rw-r--r--drivers/scsi/bfa/bfa_defs.h13
-rw-r--r--drivers/scsi/bfa/bfa_hw_cb.c34
-rw-r--r--drivers/scsi/bfa/bfa_hw_ct.c75
-rw-r--r--drivers/scsi/bfa/bfa_ioc.c144
-rw-r--r--drivers/scsi/bfa/bfa_ioc.h117
-rw-r--r--drivers/scsi/bfa/bfa_ioc_cb.c56
-rw-r--r--drivers/scsi/bfa/bfa_ioc_ct.c418
-rw-r--r--drivers/scsi/bfa/bfa_port.c2
-rw-r--r--drivers/scsi/bfa/bfad.c81
-rw-r--r--drivers/scsi/bfa/bfad_drv.h1
-rw-r--r--drivers/scsi/bfa/bfad_im.c2
-rw-r--r--drivers/scsi/bfa/bfi.h62
-rw-r--r--drivers/scsi/bfa/bfi_cbreg.h305
-rw-r--r--drivers/scsi/bfa/bfi_ctreg.h636
-rw-r--r--drivers/scsi/bfa/bfi_ms.h36
-rw-r--r--drivers/scsi/bfa/bfi_reg.h428
18 files changed, 1262 insertions, 1371 deletions
diff --git a/drivers/scsi/bfa/bfa.h b/drivers/scsi/bfa/bfa.h
index 7be6b5a8114b..708bab093c14 100644
--- a/drivers/scsi/bfa/bfa.h
+++ b/drivers/scsi/bfa/bfa.h
@@ -136,7 +136,6 @@ struct bfa_cb_qe_s {
136 struct list_head qe; 136 struct list_head qe;
137 bfa_cb_cbfn_t cbfn; 137 bfa_cb_cbfn_t cbfn;
138 bfa_boolean_t once; 138 bfa_boolean_t once;
139 u32 rsvd;
140 void *cbarg; 139 void *cbarg;
141}; 140};
142 141
@@ -205,11 +204,9 @@ struct bfa_iocfc_regs_s {
205 void __iomem *intr_mask; 204 void __iomem *intr_mask;
206 void __iomem *cpe_q_pi[BFI_IOC_MAX_CQS]; 205 void __iomem *cpe_q_pi[BFI_IOC_MAX_CQS];
207 void __iomem *cpe_q_ci[BFI_IOC_MAX_CQS]; 206 void __iomem *cpe_q_ci[BFI_IOC_MAX_CQS];
208 void __iomem *cpe_q_depth[BFI_IOC_MAX_CQS];
209 void __iomem *cpe_q_ctrl[BFI_IOC_MAX_CQS]; 207 void __iomem *cpe_q_ctrl[BFI_IOC_MAX_CQS];
210 void __iomem *rme_q_ci[BFI_IOC_MAX_CQS]; 208 void __iomem *rme_q_ci[BFI_IOC_MAX_CQS];
211 void __iomem *rme_q_pi[BFI_IOC_MAX_CQS]; 209 void __iomem *rme_q_pi[BFI_IOC_MAX_CQS];
212 void __iomem *rme_q_depth[BFI_IOC_MAX_CQS];
213 void __iomem *rme_q_ctrl[BFI_IOC_MAX_CQS]; 210 void __iomem *rme_q_ctrl[BFI_IOC_MAX_CQS];
214}; 211};
215 212
@@ -238,6 +235,8 @@ struct bfa_hwif_s {
238 u32 *nvecs, u32 *maxvec); 235 u32 *nvecs, u32 *maxvec);
239 void (*hw_msix_get_rme_range) (struct bfa_s *bfa, u32 *start, 236 void (*hw_msix_get_rme_range) (struct bfa_s *bfa, u32 *start,
240 u32 *end); 237 u32 *end);
238 int cpe_vec_q0;
239 int rme_vec_q0;
241}; 240};
242typedef void (*bfa_cb_iocfc_t) (void *cbarg, enum bfa_status status); 241typedef void (*bfa_cb_iocfc_t) (void *cbarg, enum bfa_status status);
243 242
@@ -257,7 +256,6 @@ struct bfa_iocfc_s {
257 struct bfi_iocfc_cfg_s *cfginfo; 256 struct bfi_iocfc_cfg_s *cfginfo;
258 struct bfa_dma_s cfgrsp_dma; 257 struct bfa_dma_s cfgrsp_dma;
259 struct bfi_iocfc_cfgrsp_s *cfgrsp; 258 struct bfi_iocfc_cfgrsp_s *cfgrsp;
260 struct bfi_iocfc_cfg_reply_s *cfg_reply;
261 struct bfa_dma_s req_cq_ba[BFI_IOC_MAX_CQS]; 259 struct bfa_dma_s req_cq_ba[BFI_IOC_MAX_CQS];
262 struct bfa_dma_s req_cq_shadow_ci[BFI_IOC_MAX_CQS]; 260 struct bfa_dma_s req_cq_shadow_ci[BFI_IOC_MAX_CQS];
263 struct bfa_dma_s rsp_cq_ba[BFI_IOC_MAX_CQS]; 261 struct bfa_dma_s rsp_cq_ba[BFI_IOC_MAX_CQS];
@@ -277,8 +275,11 @@ struct bfa_iocfc_s {
277 ((__bfa)->iocfc.hwif.hw_msix_install(__bfa)) 275 ((__bfa)->iocfc.hwif.hw_msix_install(__bfa))
278#define bfa_msix_uninstall(__bfa) \ 276#define bfa_msix_uninstall(__bfa) \
279 ((__bfa)->iocfc.hwif.hw_msix_uninstall(__bfa)) 277 ((__bfa)->iocfc.hwif.hw_msix_uninstall(__bfa))
280#define bfa_isr_mode_set(__bfa, __msix) \ 278#define bfa_isr_mode_set(__bfa, __msix) do { \
281 ((__bfa)->iocfc.hwif.hw_isr_mode_set(__bfa, __msix)) 279 if ((__bfa)->iocfc.hwif.hw_isr_mode_set) \
280 (__bfa)->iocfc.hwif.hw_isr_mode_set(__bfa, __msix); \
281} while (0)
282
282#define bfa_msix_getvecs(__bfa, __vecmap, __nvecs, __maxvec) \ 283#define bfa_msix_getvecs(__bfa, __vecmap, __nvecs, __maxvec) \
283 ((__bfa)->iocfc.hwif.hw_msix_getvecs(__bfa, __vecmap, \ 284 ((__bfa)->iocfc.hwif.hw_msix_getvecs(__bfa, __vecmap, \
284 __nvecs, __maxvec)) 285 __nvecs, __maxvec))
@@ -321,6 +322,7 @@ void bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *vecmap, u32 *nvecs,
321void bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, 322void bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start,
322 u32 *end); 323 u32 *end);
323void bfa_hwct_reginit(struct bfa_s *bfa); 324void bfa_hwct_reginit(struct bfa_s *bfa);
325void bfa_hwct2_reginit(struct bfa_s *bfa);
324void bfa_hwct_reqq_ack(struct bfa_s *bfa, int rspq); 326void bfa_hwct_reqq_ack(struct bfa_s *bfa, int rspq);
325void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq); 327void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq);
326void bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs); 328void bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs);
diff --git a/drivers/scsi/bfa/bfa_core.c b/drivers/scsi/bfa/bfa_core.c
index 8e496e16a2a8..5a00217ee5be 100644
--- a/drivers/scsi/bfa/bfa_core.c
+++ b/drivers/scsi/bfa/bfa_core.c
@@ -17,7 +17,7 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_modules.h" 19#include "bfa_modules.h"
20#include "bfi_ctreg.h" 20#include "bfi_reg.h"
21 21
22BFA_TRC_FILE(HAL, CORE); 22BFA_TRC_FILE(HAL, CORE);
23 23
@@ -173,6 +173,58 @@ bfa_reqq_resume(struct bfa_s *bfa, int qid)
173 } 173 }
174} 174}
175 175
176static inline void
177bfa_isr_rspq(struct bfa_s *bfa, int qid)
178{
179 struct bfi_msg_s *m;
180 u32 pi, ci;
181 struct list_head *waitq;
182
183 bfa->iocfc.hwif.hw_rspq_ack(bfa, qid);
184
185 ci = bfa_rspq_ci(bfa, qid);
186 pi = bfa_rspq_pi(bfa, qid);
187
188 while (ci != pi) {
189 m = bfa_rspq_elem(bfa, qid, ci);
190 WARN_ON(m->mhdr.msg_class >= BFI_MC_MAX);
191
192 bfa_isrs[m->mhdr.msg_class] (bfa, m);
193 CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems);
194 }
195
196 /*
197 * update CI
198 */
199 bfa_rspq_ci(bfa, qid) = pi;
200 writel(pi, bfa->iocfc.bfa_regs.rme_q_ci[qid]);
201 mmiowb();
202
203 /*
204 * Resume any pending requests in the corresponding reqq.
205 */
206 waitq = bfa_reqq(bfa, qid);
207 if (!list_empty(waitq))
208 bfa_reqq_resume(bfa, qid);
209}
210
211static inline void
212bfa_isr_reqq(struct bfa_s *bfa, int qid)
213{
214 struct list_head *waitq;
215
216 qid &= (BFI_IOC_MAX_CQS - 1);
217
218 bfa->iocfc.hwif.hw_reqq_ack(bfa, qid);
219
220 /*
221 * Resume any pending requests in the corresponding reqq.
222 */
223 waitq = bfa_reqq(bfa, qid);
224 if (!list_empty(waitq))
225 bfa_reqq_resume(bfa, qid);
226}
227
176void 228void
177bfa_msix_all(struct bfa_s *bfa, int vec) 229bfa_msix_all(struct bfa_s *bfa, int vec)
178{ 230{
@@ -197,7 +249,7 @@ bfa_intx(struct bfa_s *bfa)
197 249
198 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) { 250 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
199 if (intr & (__HFN_INT_RME_Q0 << queue)) 251 if (intr & (__HFN_INT_RME_Q0 << queue))
200 bfa_msix_rspq(bfa, queue & (BFI_IOC_MAX_CQS - 1)); 252 bfa_isr_rspq(bfa, queue & (BFI_IOC_MAX_CQS - 1));
201 } 253 }
202 intr &= ~qintr; 254 intr &= ~qintr;
203 if (!intr) 255 if (!intr)
@@ -211,7 +263,7 @@ bfa_intx(struct bfa_s *bfa)
211 263
212 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) { 264 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
213 if (intr & (__HFN_INT_CPE_Q0 << queue)) 265 if (intr & (__HFN_INT_CPE_Q0 << queue))
214 bfa_msix_reqq(bfa, queue & (BFI_IOC_MAX_CQS - 1)); 266 bfa_isr_reqq(bfa, queue & (BFI_IOC_MAX_CQS - 1));
215 } 267 }
216 intr &= ~qintr; 268 intr &= ~qintr;
217 if (!intr) 269 if (!intr)
@@ -225,32 +277,25 @@ bfa_intx(struct bfa_s *bfa)
225void 277void
226bfa_isr_enable(struct bfa_s *bfa) 278bfa_isr_enable(struct bfa_s *bfa)
227{ 279{
228 u32 intr_unmask; 280 u32 umsk;
229 int pci_func = bfa_ioc_pcifn(&bfa->ioc); 281 int pci_func = bfa_ioc_pcifn(&bfa->ioc);
230 282
231 bfa_trc(bfa, pci_func); 283 bfa_trc(bfa, pci_func);
232 284
233 bfa_msix_install(bfa); 285 bfa_msix_install(bfa);
234 intr_unmask = (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | 286
235 __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS | 287 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) {
236 __HFN_INT_LL_HALT); 288 umsk = __HFN_INT_ERR_MASK_CT2;
237 289 umsk |= pci_func == 0 ?
238 if (pci_func == 0) 290 __HFN_INT_FN0_MASK_CT2 : __HFN_INT_FN1_MASK_CT2;
239 intr_unmask |= (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | 291 } else {
240 __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 | 292 umsk = __HFN_INT_ERR_MASK;
241 __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | 293 umsk |= pci_func == 0 ? __HFN_INT_FN0_MASK : __HFN_INT_FN1_MASK;
242 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | 294 }
243 __HFN_INT_MBOX_LPU0); 295
244 else 296 writel(umsk, bfa->iocfc.bfa_regs.intr_status);
245 intr_unmask |= (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | 297 writel(~umsk, bfa->iocfc.bfa_regs.intr_mask);
246 __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 | 298 bfa->iocfc.intr_mask = ~umsk;
247 __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
248 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
249 __HFN_INT_MBOX_LPU1);
250
251 writel(intr_unmask, bfa->iocfc.bfa_regs.intr_status);
252 writel(~intr_unmask, bfa->iocfc.bfa_regs.intr_mask);
253 bfa->iocfc.intr_mask = ~intr_unmask;
254 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0); 299 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
255} 300}
256 301
@@ -263,20 +308,9 @@ bfa_isr_disable(struct bfa_s *bfa)
263} 308}
264 309
265void 310void
266bfa_msix_reqq(struct bfa_s *bfa, int qid) 311bfa_msix_reqq(struct bfa_s *bfa, int vec)
267{ 312{
268 struct list_head *waitq; 313 bfa_isr_reqq(bfa, vec - bfa->iocfc.hwif.cpe_vec_q0);
269
270 qid &= (BFI_IOC_MAX_CQS - 1);
271
272 bfa->iocfc.hwif.hw_reqq_ack(bfa, qid);
273
274 /*
275 * Resume any pending requests in the corresponding reqq.
276 */
277 waitq = bfa_reqq(bfa, qid);
278 if (!list_empty(waitq))
279 bfa_reqq_resume(bfa, qid);
280} 314}
281 315
282void 316void
@@ -290,57 +324,40 @@ bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m)
290} 324}
291 325
292void 326void
293bfa_msix_rspq(struct bfa_s *bfa, int qid) 327bfa_msix_rspq(struct bfa_s *bfa, int vec)
294{ 328{
295 struct bfi_msg_s *m; 329 if (!bfa->rme_process)
296 u32 pi, ci; 330 return;
297 struct list_head *waitq;
298
299 qid &= (BFI_IOC_MAX_CQS - 1);
300
301 bfa->iocfc.hwif.hw_rspq_ack(bfa, qid);
302
303 ci = bfa_rspq_ci(bfa, qid);
304 pi = bfa_rspq_pi(bfa, qid);
305
306 if (bfa->rme_process) {
307 while (ci != pi) {
308 m = bfa_rspq_elem(bfa, qid, ci);
309 bfa_isrs[m->mhdr.msg_class] (bfa, m);
310 CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems);
311 }
312 }
313
314 /*
315 * update CI
316 */
317 bfa_rspq_ci(bfa, qid) = pi;
318 writel(pi, bfa->iocfc.bfa_regs.rme_q_ci[qid]);
319 mmiowb();
320 331
321 /* 332 bfa_isr_rspq(bfa, vec - bfa->iocfc.hwif.rme_vec_q0);
322 * Resume any pending requests in the corresponding reqq.
323 */
324 waitq = bfa_reqq(bfa, qid);
325 if (!list_empty(waitq))
326 bfa_reqq_resume(bfa, qid);
327} 333}
328 334
329void 335void
330bfa_msix_lpu_err(struct bfa_s *bfa, int vec) 336bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
331{ 337{
332 u32 intr, curr_value; 338 u32 intr, curr_value;
339 bfa_boolean_t lpu_isr, halt_isr, pss_isr;
333 340
334 intr = readl(bfa->iocfc.bfa_regs.intr_status); 341 intr = readl(bfa->iocfc.bfa_regs.intr_status);
335 342
336 if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1)) 343 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) {
337 bfa_ioc_mbox_isr(&bfa->ioc); 344 halt_isr = intr & __HFN_INT_CPQ_HALT_CT2;
345 pss_isr = intr & __HFN_INT_ERR_PSS_CT2;
346 lpu_isr = intr & (__HFN_INT_MBOX_LPU0_CT2 |
347 __HFN_INT_MBOX_LPU1_CT2);
348 intr &= __HFN_INT_ERR_MASK_CT2;
349 } else {
350 halt_isr = intr & __HFN_INT_LL_HALT;
351 pss_isr = intr & __HFN_INT_ERR_PSS;
352 lpu_isr = intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1);
353 intr &= __HFN_INT_ERR_MASK;
354 }
338 355
339 intr &= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | 356 if (lpu_isr)
340 __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT); 357 bfa_ioc_mbox_isr(&bfa->ioc);
341 358
342 if (intr) { 359 if (intr) {
343 if (intr & __HFN_INT_LL_HALT) { 360 if (halt_isr) {
344 /* 361 /*
345 * If LL_HALT bit is set then FW Init Halt LL Port 362 * If LL_HALT bit is set then FW Init Halt LL Port
346 * Register needs to be cleared as well so Interrupt 363 * Register needs to be cleared as well so Interrupt
@@ -351,7 +368,7 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
351 writel(curr_value, bfa->ioc.ioc_regs.ll_halt); 368 writel(curr_value, bfa->ioc.ioc_regs.ll_halt);
352 } 369 }
353 370
354 if (intr & __HFN_INT_ERR_PSS) { 371 if (pss_isr) {
355 /* 372 /*
356 * ERR_PSS bit needs to be cleared as well in case 373 * ERR_PSS bit needs to be cleared as well in case
357 * interrups are shared so driver's interrupt handler is 374 * interrups are shared so driver's interrupt handler is
@@ -359,7 +376,6 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
359 */ 376 */
360 curr_value = readl( 377 curr_value = readl(
361 bfa->ioc.ioc_regs.pss_err_status_reg); 378 bfa->ioc.ioc_regs.pss_err_status_reg);
362 curr_value &= __PSS_ERR_STATUS_SET;
363 writel(curr_value, 379 writel(curr_value,
364 bfa->ioc.ioc_regs.pss_err_status_reg); 380 bfa->ioc.ioc_regs.pss_err_status_reg);
365 } 381 }
@@ -491,7 +507,7 @@ bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
491 /* 507 /*
492 * Initialize chip specific handlers. 508 * Initialize chip specific handlers.
493 */ 509 */
494 if (bfa_asic_id_ct(bfa_ioc_devid(&bfa->ioc))) { 510 if (bfa_asic_id_ctc(bfa_ioc_devid(&bfa->ioc))) {
495 iocfc->hwif.hw_reginit = bfa_hwct_reginit; 511 iocfc->hwif.hw_reginit = bfa_hwct_reginit;
496 iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack; 512 iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack;
497 iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack; 513 iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack;
@@ -501,6 +517,8 @@ bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
501 iocfc->hwif.hw_isr_mode_set = bfa_hwct_isr_mode_set; 517 iocfc->hwif.hw_isr_mode_set = bfa_hwct_isr_mode_set;
502 iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs; 518 iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs;
503 iocfc->hwif.hw_msix_get_rme_range = bfa_hwct_msix_get_rme_range; 519 iocfc->hwif.hw_msix_get_rme_range = bfa_hwct_msix_get_rme_range;
520 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CT;
521 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CT;
504 } else { 522 } else {
505 iocfc->hwif.hw_reginit = bfa_hwcb_reginit; 523 iocfc->hwif.hw_reginit = bfa_hwcb_reginit;
506 iocfc->hwif.hw_reqq_ack = bfa_hwcb_reqq_ack; 524 iocfc->hwif.hw_reqq_ack = bfa_hwcb_reqq_ack;
@@ -511,6 +529,15 @@ bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
511 iocfc->hwif.hw_isr_mode_set = bfa_hwcb_isr_mode_set; 529 iocfc->hwif.hw_isr_mode_set = bfa_hwcb_isr_mode_set;
512 iocfc->hwif.hw_msix_getvecs = bfa_hwcb_msix_getvecs; 530 iocfc->hwif.hw_msix_getvecs = bfa_hwcb_msix_getvecs;
513 iocfc->hwif.hw_msix_get_rme_range = bfa_hwcb_msix_get_rme_range; 531 iocfc->hwif.hw_msix_get_rme_range = bfa_hwcb_msix_get_rme_range;
532 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CB +
533 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS;
534 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CB +
535 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS;
536 }
537
538 if (bfa_asic_id_ct2(bfa_ioc_devid(&bfa->ioc))) {
539 iocfc->hwif.hw_reginit = bfa_hwct2_reginit;
540 iocfc->hwif.hw_isr_mode_set = NULL;
514 } 541 }
515 542
516 iocfc->hwif.hw_reginit(bfa); 543 iocfc->hwif.hw_reginit(bfa);
@@ -614,6 +641,8 @@ bfa_iocfc_start_submod(struct bfa_s *bfa)
614 int i; 641 int i;
615 642
616 bfa->rme_process = BFA_TRUE; 643 bfa->rme_process = BFA_TRUE;
644 for (i = 0; i < BFI_IOC_MAX_CQS; i++)
645 bfa->iocfc.hwif.hw_rspq_ack(bfa, i);
617 646
618 for (i = 0; hal_mods[i]; i++) 647 for (i = 0; hal_mods[i]; i++)
619 hal_mods[i]->start(bfa); 648 hal_mods[i]->start(bfa);
@@ -669,6 +698,26 @@ bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl)
669 complete(&bfad->disable_comp); 698 complete(&bfad->disable_comp);
670} 699}
671 700
701/**
702 * configure queue registers from firmware response
703 */
704static void
705bfa_iocfc_qreg(struct bfa_s *bfa, struct bfi_iocfc_qreg_s *qreg)
706{
707 int i;
708 struct bfa_iocfc_regs_s *r = &bfa->iocfc.bfa_regs;
709 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
710
711 for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
712 r->cpe_q_ci[i] = kva + be32_to_cpu(qreg->cpe_q_ci_off[i]);
713 r->cpe_q_pi[i] = kva + be32_to_cpu(qreg->cpe_q_pi_off[i]);
714 r->cpe_q_ctrl[i] = kva + be32_to_cpu(qreg->cpe_qctl_off[i]);
715 r->rme_q_ci[i] = kva + be32_to_cpu(qreg->rme_q_ci_off[i]);
716 r->rme_q_pi[i] = kva + be32_to_cpu(qreg->rme_q_pi_off[i]);
717 r->rme_q_ctrl[i] = kva + be32_to_cpu(qreg->rme_qctl_off[i]);
718 }
719}
720
672/* 721/*
673 * Update BFA configuration from firmware configuration. 722 * Update BFA configuration from firmware configuration.
674 */ 723 */
@@ -689,6 +738,11 @@ bfa_iocfc_cfgrsp(struct bfa_s *bfa)
689 iocfc->cfgdone = BFA_TRUE; 738 iocfc->cfgdone = BFA_TRUE;
690 739
691 /* 740 /*
741 * configure queue register offsets as learnt from firmware
742 */
743 bfa_iocfc_qreg(bfa, &cfgrsp->qreg);
744
745 /*
692 * Configuration is complete - initialize/start submodules 746 * Configuration is complete - initialize/start submodules
693 */ 747 */
694 bfa_fcport_init(bfa); 748 bfa_fcport_init(bfa);
@@ -879,7 +933,6 @@ bfa_iocfc_isr(void *bfaarg, struct bfi_mbmsg_s *m)
879 933
880 switch (msg->mh.msg_id) { 934 switch (msg->mh.msg_id) {
881 case BFI_IOCFC_I2H_CFG_REPLY: 935 case BFI_IOCFC_I2H_CFG_REPLY:
882 iocfc->cfg_reply = &msg->cfg_reply;
883 bfa_iocfc_cfgrsp(bfa); 936 bfa_iocfc_cfgrsp(bfa);
884 break; 937 break;
885 case BFI_IOCFC_I2H_UPDATEQ_RSP: 938 case BFI_IOCFC_I2H_UPDATEQ_RSP:
diff --git a/drivers/scsi/bfa/bfa_defs.h b/drivers/scsi/bfa/bfa_defs.h
index d85f93aea465..be1ba54fa193 100644
--- a/drivers/scsi/bfa/bfa_defs.h
+++ b/drivers/scsi/bfa/bfa_defs.h
@@ -386,11 +386,18 @@ enum {
386 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17, 386 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
387 BFA_PCI_DEVICE_ID_CT = 0x14, 387 BFA_PCI_DEVICE_ID_CT = 0x14,
388 BFA_PCI_DEVICE_ID_CT_FC = 0x21, 388 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
389 BFA_PCI_DEVICE_ID_CT2 = 0x22,
389}; 390};
390 391
391#define bfa_asic_id_ct(devid) \ 392#define bfa_asic_id_cb(__d) \
392 ((devid) == BFA_PCI_DEVICE_ID_CT || \ 393 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \
393 (devid) == BFA_PCI_DEVICE_ID_CT_FC) 394 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P)
395#define bfa_asic_id_ct(__d) \
396 ((__d) == BFA_PCI_DEVICE_ID_CT || \
397 (__d) == BFA_PCI_DEVICE_ID_CT_FC)
398#define bfa_asic_id_ct2(__d) ((__d) == BFA_PCI_DEVICE_ID_CT2)
399#define bfa_asic_id_ctc(__d) \
400 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d))
394 401
395/* 402/*
396 * PCI sub-system device and vendor ID information 403 * PCI sub-system device and vendor ID information
diff --git a/drivers/scsi/bfa/bfa_hw_cb.c b/drivers/scsi/bfa/bfa_hw_cb.c
index 977e681ec803..4ef3cf2e7d98 100644
--- a/drivers/scsi/bfa/bfa_hw_cb.c
+++ b/drivers/scsi/bfa/bfa_hw_cb.c
@@ -17,14 +17,14 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_modules.h" 19#include "bfa_modules.h"
20#include "bfi_cbreg.h" 20#include "bfi_reg.h"
21 21
22void 22void
23bfa_hwcb_reginit(struct bfa_s *bfa) 23bfa_hwcb_reginit(struct bfa_s *bfa)
24{ 24{
25 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 25 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
26 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 26 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
27 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); 27 int fn = bfa_ioc_pcifn(&bfa->ioc);
28 28
29 if (fn == 0) { 29 if (fn == 0) {
30 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); 30 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
@@ -33,24 +33,6 @@ bfa_hwcb_reginit(struct bfa_s *bfa)
33 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); 33 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
34 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); 34 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
35 } 35 }
36
37 for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
38 /*
39 * CPE registers
40 */
41 q = CPE_Q_NUM(fn, i);
42 bfa_regs->cpe_q_pi[i] = (kva + CPE_Q_PI(q));
43 bfa_regs->cpe_q_ci[i] = (kva + CPE_Q_CI(q));
44 bfa_regs->cpe_q_depth[i] = (kva + CPE_Q_DEPTH(q));
45
46 /*
47 * RME registers
48 */
49 q = CPE_Q_NUM(fn, i);
50 bfa_regs->rme_q_pi[i] = (kva + RME_Q_PI(q));
51 bfa_regs->rme_q_ci[i] = (kva + RME_Q_CI(q));
52 bfa_regs->rme_q_depth[i] = (kva + RME_Q_DEPTH(q));
53 }
54} 36}
55 37
56void 38void
@@ -115,18 +97,18 @@ bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs)
115 97
116 bfa->msix.nvecs = nvecs; 98 bfa->msix.nvecs = nvecs;
117 if (nvecs == 1) { 99 if (nvecs == 1) {
118 for (i = 0; i < BFA_MSIX_CB_MAX; i++) 100 for (i = 0; i < BFI_MSIX_CB_MAX; i++)
119 bfa->msix.handler[i] = bfa_msix_all; 101 bfa->msix.handler[i] = bfa_msix_all;
120 return; 102 return;
121 } 103 }
122 104
123 for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q7; i++) 105 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++)
124 bfa->msix.handler[i] = bfa_msix_reqq; 106 bfa->msix.handler[i] = bfa_msix_reqq;
125 107
126 for (i = BFA_MSIX_RME_Q0; i <= BFA_MSIX_RME_Q7; i++) 108 for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
127 bfa->msix.handler[i] = bfa_msix_rspq; 109 bfa->msix.handler[i] = bfa_msix_rspq;
128 110
129 for (; i < BFA_MSIX_CB_MAX; i++) 111 for (; i < BFI_MSIX_CB_MAX; i++)
130 bfa->msix.handler[i] = bfa_msix_lpu_err; 112 bfa->msix.handler[i] = bfa_msix_lpu_err;
131} 113}
132 114
@@ -156,6 +138,6 @@ bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
156void 138void
157bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) 139bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
158{ 140{
159 *start = BFA_MSIX_RME_Q0; 141 *start = BFI_MSIX_RME_QMIN_CB;
160 *end = BFA_MSIX_RME_Q7; 142 *end = BFI_MSIX_RME_QMAX_CB;
161} 143}
diff --git a/drivers/scsi/bfa/bfa_hw_ct.c b/drivers/scsi/bfa/bfa_hw_ct.c
index 21018d98a07b..66e2d29ff45a 100644
--- a/drivers/scsi/bfa/bfa_hw_ct.c
+++ b/drivers/scsi/bfa/bfa_hw_ct.c
@@ -17,29 +17,10 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_modules.h" 19#include "bfa_modules.h"
20#include "bfi_ctreg.h" 20#include "bfi_reg.h"
21 21
22BFA_TRC_FILE(HAL, IOCFC_CT); 22BFA_TRC_FILE(HAL, IOCFC_CT);
23 23
24static u32 __ct_msix_err_vec_reg[] = {
25 HOST_MSIX_ERR_INDEX_FN0,
26 HOST_MSIX_ERR_INDEX_FN1,
27 HOST_MSIX_ERR_INDEX_FN2,
28 HOST_MSIX_ERR_INDEX_FN3,
29};
30
31static void
32bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
33{
34 int fn = bfa_ioc_pcifn(&bfa->ioc);
35 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
36
37 if (msix)
38 writel(vec, kva + __ct_msix_err_vec_reg[fn]);
39 else
40 writel(0, kva + __ct_msix_err_vec_reg[fn]);
41}
42
43/* 24/*
44 * Dummy interrupt handler for handling spurious interrupt during chip-reinit. 25 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
45 */ 26 */
@@ -53,7 +34,7 @@ bfa_hwct_reginit(struct bfa_s *bfa)
53{ 34{
54 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 35 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
55 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 36 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
56 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); 37 int fn = bfa_ioc_pcifn(&bfa->ioc);
57 38
58 if (fn == 0) { 39 if (fn == 0) {
59 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); 40 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
@@ -62,26 +43,16 @@ bfa_hwct_reginit(struct bfa_s *bfa)
62 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); 43 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
63 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); 44 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
64 } 45 }
46}
65 47
66 for (i = 0; i < BFI_IOC_MAX_CQS; i++) { 48void
67 /* 49bfa_hwct2_reginit(struct bfa_s *bfa)
68 * CPE registers 50{
69 */ 51 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
70 q = CPE_Q_NUM(fn, i); 52 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
71 bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5)); 53
72 bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5)); 54 bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
73 bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5)); 55 bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
74 bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));
75
76 /*
77 * RME registers
78 */
79 q = CPE_Q_NUM(fn, i);
80 bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
81 bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
82 bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
83 bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
84 }
85} 56}
86 57
87void 58void
@@ -106,9 +77,9 @@ void
106bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, 77bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
107 u32 *num_vecs, u32 *max_vec_bit) 78 u32 *num_vecs, u32 *max_vec_bit)
108{ 79{
109 *msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1; 80 *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
110 *max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1)); 81 *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
111 *num_vecs = BFA_MSIX_CT_MAX; 82 *num_vecs = BFI_MSIX_CT_MAX;
112} 83}
113 84
114/* 85/*
@@ -117,7 +88,7 @@ bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
117void 88void
118bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs) 89bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
119{ 90{
120 WARN_ON((nvecs != 1) && (nvecs != BFA_MSIX_CT_MAX)); 91 WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
121 bfa_trc(bfa, nvecs); 92 bfa_trc(bfa, nvecs);
122 93
123 bfa->msix.nvecs = nvecs; 94 bfa->msix.nvecs = nvecs;
@@ -133,19 +104,18 @@ bfa_hwct_msix_install(struct bfa_s *bfa)
133 return; 104 return;
134 105
135 if (bfa->msix.nvecs == 1) { 106 if (bfa->msix.nvecs == 1) {
136 for (i = 0; i < BFA_MSIX_CT_MAX; i++) 107 for (i = 0; i < BFI_MSIX_CT_MAX; i++)
137 bfa->msix.handler[i] = bfa_msix_all; 108 bfa->msix.handler[i] = bfa_msix_all;
138 return; 109 return;
139 } 110 }
140 111
141 for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++) 112 for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
142 bfa->msix.handler[i] = bfa_msix_reqq; 113 bfa->msix.handler[i] = bfa_msix_reqq;
143 114
144 for (; i <= BFA_MSIX_RME_Q3; i++) 115 for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
145 bfa->msix.handler[i] = bfa_msix_rspq; 116 bfa->msix.handler[i] = bfa_msix_rspq;
146 117
147 WARN_ON(i != BFA_MSIX_LPU_ERR); 118 bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
148 bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
149} 119}
150 120
151void 121void
@@ -153,7 +123,7 @@ bfa_hwct_msix_uninstall(struct bfa_s *bfa)
153{ 123{
154 int i; 124 int i;
155 125
156 for (i = 0; i < BFA_MSIX_CT_MAX; i++) 126 for (i = 0; i < BFI_MSIX_CT_MAX; i++)
157 bfa->msix.handler[i] = bfa_hwct_msix_dummy; 127 bfa->msix.handler[i] = bfa_hwct_msix_dummy;
158} 128}
159 129
@@ -164,13 +134,12 @@ void
164bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) 134bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
165{ 135{
166 bfa_trc(bfa, 0); 136 bfa_trc(bfa, 0);
167 bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
168 bfa_ioc_isr_mode_set(&bfa->ioc, msix); 137 bfa_ioc_isr_mode_set(&bfa->ioc, msix);
169} 138}
170 139
171void 140void
172bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) 141bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
173{ 142{
174 *start = BFA_MSIX_RME_Q0; 143 *start = BFI_MSIX_RME_QMIN_CT;
175 *end = BFA_MSIX_RME_Q3; 144 *end = BFI_MSIX_RME_QMAX_CT;
176} 145}
diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c
index d215168ab8b5..3d336c279c42 100644
--- a/drivers/scsi/bfa/bfa_ioc.c
+++ b/drivers/scsi/bfa/bfa_ioc.c
@@ -17,7 +17,7 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_ioc.h" 19#include "bfa_ioc.h"
20#include "bfi_ctreg.h" 20#include "bfi_reg.h"
21#include "bfa_defs.h" 21#include "bfa_defs.h"
22#include "bfa_defs_svc.h" 22#include "bfa_defs_svc.h"
23 23
@@ -1219,13 +1219,13 @@ bfa_ioc_sem_get(void __iomem *sem_reg)
1219 1219
1220 r32 = readl(sem_reg); 1220 r32 = readl(sem_reg);
1221 1221
1222 while (r32 && (cnt < BFA_SEM_SPINCNT)) { 1222 while ((r32 & 1) && (cnt < BFA_SEM_SPINCNT)) {
1223 cnt++; 1223 cnt++;
1224 udelay(2); 1224 udelay(2);
1225 r32 = readl(sem_reg); 1225 r32 = readl(sem_reg);
1226 } 1226 }
1227 1227
1228 if (r32 == 0) 1228 if (!(r32 & 1))
1229 return BFA_TRUE; 1229 return BFA_TRUE;
1230 1230
1231 WARN_ON(cnt >= BFA_SEM_SPINCNT); 1231 WARN_ON(cnt >= BFA_SEM_SPINCNT);
@@ -1242,7 +1242,7 @@ bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc)
1242 * will return 1. Semaphore is released by writing 1 to the register 1242 * will return 1. Semaphore is released by writing 1 to the register
1243 */ 1243 */
1244 r32 = readl(ioc->ioc_regs.ioc_sem_reg); 1244 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
1245 if (r32 == 0) { 1245 if (!(r32 & 1)) {
1246 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED); 1246 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
1247 return; 1247 return;
1248 } 1248 }
@@ -1351,7 +1351,7 @@ bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr)
1351 int i; 1351 int i;
1352 1352
1353 drv_fwhdr = (struct bfi_ioc_image_hdr_s *) 1353 drv_fwhdr = (struct bfi_ioc_image_hdr_s *)
1354 bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), 0); 1354 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
1355 1355
1356 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) { 1356 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
1357 if (fwhdr->md5sum[i] != drv_fwhdr->md5sum[i]) { 1357 if (fwhdr->md5sum[i] != drv_fwhdr->md5sum[i]) {
@@ -1377,7 +1377,7 @@ bfa_ioc_fwver_valid(struct bfa_ioc_s *ioc, u32 boot_env)
1377 1377
1378 bfa_ioc_fwver_get(ioc, &fwhdr); 1378 bfa_ioc_fwver_get(ioc, &fwhdr);
1379 drv_fwhdr = (struct bfi_ioc_image_hdr_s *) 1379 drv_fwhdr = (struct bfi_ioc_image_hdr_s *)
1380 bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), 0); 1380 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
1381 1381
1382 if (fwhdr.signature != drv_fwhdr->signature) { 1382 if (fwhdr.signature != drv_fwhdr->signature) {
1383 bfa_trc(ioc, fwhdr.signature); 1383 bfa_trc(ioc, fwhdr.signature);
@@ -1385,8 +1385,8 @@ bfa_ioc_fwver_valid(struct bfa_ioc_s *ioc, u32 boot_env)
1385 return BFA_FALSE; 1385 return BFA_FALSE;
1386 } 1386 }
1387 1387
1388 if (swab32(fwhdr.param) != boot_env) { 1388 if (swab32(fwhdr.bootenv) != boot_env) {
1389 bfa_trc(ioc, fwhdr.param); 1389 bfa_trc(ioc, fwhdr.bootenv);
1390 bfa_trc(ioc, boot_env); 1390 bfa_trc(ioc, boot_env);
1391 return BFA_FALSE; 1391 return BFA_FALSE;
1392 } 1392 }
@@ -1422,8 +1422,8 @@ bfa_ioc_hwinit(struct bfa_ioc_s *ioc, bfa_boolean_t force)
1422 1422
1423 bfa_trc(ioc, ioc_fwstate); 1423 bfa_trc(ioc, ioc_fwstate);
1424 1424
1425 boot_type = BFI_BOOT_TYPE_NORMAL; 1425 boot_type = BFI_FWBOOT_TYPE_NORMAL;
1426 boot_env = BFI_BOOT_LOADER_OS; 1426 boot_env = BFI_FWBOOT_ENV_OS;
1427 1427
1428 /* 1428 /*
1429 * check if firmware is valid 1429 * check if firmware is valid
@@ -1580,25 +1580,26 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type,
1580 u32 loff = 0; 1580 u32 loff = 0;
1581 u32 chunkno = 0; 1581 u32 chunkno = 0;
1582 u32 i; 1582 u32 i;
1583 u32 asicmode;
1583 1584
1584 /* 1585 /*
1585 * Initialize LMEM first before code download 1586 * Initialize LMEM first before code download
1586 */ 1587 */
1587 bfa_ioc_lmem_init(ioc); 1588 bfa_ioc_lmem_init(ioc);
1588 1589
1589 bfa_trc(ioc, bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc))); 1590 bfa_trc(ioc, bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)));
1590 fwimg = bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), chunkno); 1591 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), chunkno);
1591 1592
1592 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff); 1593 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
1593 pgoff = PSS_SMEM_PGOFF(loff); 1594 pgoff = PSS_SMEM_PGOFF(loff);
1594 1595
1595 writel(pgnum, ioc->ioc_regs.host_page_num_fn); 1596 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1596 1597
1597 for (i = 0; i < bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)); i++) { 1598 for (i = 0; i < bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)); i++) {
1598 1599
1599 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) { 1600 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
1600 chunkno = BFA_IOC_FLASH_CHUNK_NO(i); 1601 chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
1601 fwimg = bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), 1602 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc),
1602 BFA_IOC_FLASH_CHUNK_ADDR(chunkno)); 1603 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
1603 } 1604 }
1604 1605
@@ -1624,11 +1625,15 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type,
1624 ioc->ioc_regs.host_page_num_fn); 1625 ioc->ioc_regs.host_page_num_fn);
1625 1626
1626 /* 1627 /*
1627 * Set boot type and boot param at the end. 1628 * Set boot type and device mode at the end.
1628 */ 1629 */
1629 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_TYPE_OFF, 1630 asicmode = BFI_FWBOOT_DEVMODE(ioc->asic_gen, ioc->asic_mode,
1631 ioc->port0_mode, ioc->port1_mode);
1632 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_FWBOOT_DEVMODE_OFF,
1633 swab32(asicmode));
1634 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_FWBOOT_TYPE_OFF,
1630 swab32(boot_type)); 1635 swab32(boot_type));
1631 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_LOADER_OFF, 1636 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_FWBOOT_ENV_OFF,
1632 swab32(boot_env)); 1637 swab32(boot_env));
1633} 1638}
1634 1639
@@ -1879,8 +1884,6 @@ bfa_ioc_pll_init(struct bfa_ioc_s *ioc)
1879void 1884void
1880bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env) 1885bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env)
1881{ 1886{
1882 void __iomem *rb;
1883
1884 bfa_ioc_stats(ioc, ioc_boots); 1887 bfa_ioc_stats(ioc, ioc_boots);
1885 1888
1886 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK) 1889 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
@@ -1889,13 +1892,12 @@ bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env)
1889 /* 1892 /*
1890 * Initialize IOC state of all functions on a chip reset. 1893 * Initialize IOC state of all functions on a chip reset.
1891 */ 1894 */
1892 rb = ioc->pcidev.pci_bar_kva; 1895 if (boot_type == BFI_FWBOOT_TYPE_MEMTEST) {
1893 if (boot_type == BFI_BOOT_TYPE_MEMTEST) { 1896 writel(BFI_IOC_MEMTEST, ioc->ioc_regs.ioc_fwstate);
1894 writel(BFI_IOC_MEMTEST, (rb + BFA_IOC0_STATE_REG)); 1897 writel(BFI_IOC_MEMTEST, ioc->ioc_regs.alt_ioc_fwstate);
1895 writel(BFI_IOC_MEMTEST, (rb + BFA_IOC1_STATE_REG));
1896 } else { 1898 } else {
1897 writel(BFI_IOC_INITING, (rb + BFA_IOC0_STATE_REG)); 1899 writel(BFI_IOC_INITING, ioc->ioc_regs.ioc_fwstate);
1898 writel(BFI_IOC_INITING, (rb + BFA_IOC1_STATE_REG)); 1900 writel(BFI_IOC_INITING, ioc->ioc_regs.alt_ioc_fwstate);
1899 } 1901 }
1900 1902
1901 bfa_ioc_msgflush(ioc); 1903 bfa_ioc_msgflush(ioc);
@@ -1935,13 +1937,17 @@ bfa_ioc_is_initialized(struct bfa_ioc_s *ioc)
1935 (r32 != BFI_IOC_MEMTEST)); 1937 (r32 != BFI_IOC_MEMTEST));
1936} 1938}
1937 1939
1938void 1940bfa_boolean_t
1939bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg) 1941bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg)
1940{ 1942{
1941 __be32 *msgp = mbmsg; 1943 __be32 *msgp = mbmsg;
1942 u32 r32; 1944 u32 r32;
1943 int i; 1945 int i;
1944 1946
1947 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
1948 if ((r32 & 1) == 0)
1949 return BFA_FALSE;
1950
1945 /* 1951 /*
1946 * read the MBOX msg 1952 * read the MBOX msg
1947 */ 1953 */
@@ -1957,6 +1963,8 @@ bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg)
1957 */ 1963 */
1958 writel(1, ioc->ioc_regs.lpu_mbox_cmd); 1964 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1959 readl(ioc->ioc_regs.lpu_mbox_cmd); 1965 readl(ioc->ioc_regs.lpu_mbox_cmd);
1966
1967 return BFA_TRUE;
1960} 1968}
1961 1969
1962void 1970void
@@ -2040,16 +2048,55 @@ bfa_ioc_pci_init(struct bfa_ioc_s *ioc, struct bfa_pcidev_s *pcidev,
2040{ 2048{
2041 ioc->clscode = clscode; 2049 ioc->clscode = clscode;
2042 ioc->pcidev = *pcidev; 2050 ioc->pcidev = *pcidev;
2043 ioc->ctdev = bfa_asic_id_ct(ioc->pcidev.device_id); 2051
2044 ioc->cna = ioc->ctdev && !ioc->fcmode; 2052 /*
2053 * Initialize IOC and device personality
2054 */
2055 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_FC;
2056 ioc->asic_mode = BFI_ASIC_MODE_FC;
2057
2058 switch (pcidev->device_id) {
2059 case BFA_PCI_DEVICE_ID_FC_8G1P:
2060 case BFA_PCI_DEVICE_ID_FC_8G2P:
2061 ioc->asic_gen = BFI_ASIC_GEN_CB;
2062 break;
2063
2064 case BFA_PCI_DEVICE_ID_CT:
2065 ioc->asic_gen = BFI_ASIC_GEN_CT;
2066 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2067 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2068 break;
2069
2070 case BFA_PCI_DEVICE_ID_CT_FC:
2071 ioc->asic_gen = BFI_ASIC_GEN_CT;
2072 break;
2073
2074 case BFA_PCI_DEVICE_ID_CT2:
2075 ioc->asic_gen = BFI_ASIC_GEN_CT2;
2076 if (clscode == BFI_PCIFN_CLASS_FC)
2077 ioc->asic_mode = BFI_ASIC_MODE_FC16;
2078 else {
2079 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2080 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2081 }
2082 break;
2083
2084 default:
2085 WARN_ON(1);
2086 }
2045 2087
2046 /* 2088 /*
2047 * Set asic specific interfaces. See bfa_ioc_cb.c and bfa_ioc_ct.c 2089 * Set asic specific interfaces. See bfa_ioc_cb.c and bfa_ioc_ct.c
2048 */ 2090 */
2049 if (ioc->ctdev) 2091 if (ioc->asic_gen == BFI_ASIC_GEN_CB)
2050 bfa_ioc_set_ct_hwif(ioc);
2051 else
2052 bfa_ioc_set_cb_hwif(ioc); 2092 bfa_ioc_set_cb_hwif(ioc);
2093 else if (ioc->asic_gen == BFI_ASIC_GEN_CT)
2094 bfa_ioc_set_ct_hwif(ioc);
2095 else {
2096 WARN_ON(ioc->asic_gen != BFI_ASIC_GEN_CT2);
2097 bfa_ioc_set_ct2_hwif(ioc);
2098 bfa_ioc_ct2_poweron(ioc);
2099 }
2053 2100
2054 bfa_ioc_map_port(ioc); 2101 bfa_ioc_map_port(ioc);
2055 bfa_ioc_reg_init(ioc); 2102 bfa_ioc_reg_init(ioc);
@@ -2175,7 +2222,8 @@ bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc)
2175 struct bfi_mbmsg_s m; 2222 struct bfi_mbmsg_s m;
2176 int mc; 2223 int mc;
2177 2224
2178 bfa_ioc_msgget(ioc, &m); 2225 if (!bfa_ioc_msgget(ioc, &m))
2226 return;
2179 2227
2180 /* 2228 /*
2181 * Treat IOC message class as special. 2229 * Treat IOC message class as special.
@@ -2202,7 +2250,6 @@ void
2202bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc) 2250bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc)
2203{ 2251{
2204 ioc->fcmode = BFA_TRUE; 2252 ioc->fcmode = BFA_TRUE;
2205 ioc->port_id = bfa_ioc_pcifn(ioc);
2206} 2253}
2207 2254
2208/* 2255/*
@@ -2242,17 +2289,16 @@ bfa_boolean_t
2242bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc) 2289bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc)
2243{ 2290{
2244 u32 ioc_state; 2291 u32 ioc_state;
2245 void __iomem *rb = ioc->pcidev.pci_bar_kva;
2246 2292
2247 if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled)) 2293 if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled))
2248 return BFA_FALSE; 2294 return BFA_FALSE;
2249 2295
2250 ioc_state = readl(rb + BFA_IOC0_STATE_REG); 2296 ioc_state = readl(ioc->ioc_regs.ioc_fwstate);
2251 if (!bfa_ioc_state_disabled(ioc_state)) 2297 if (!bfa_ioc_state_disabled(ioc_state))
2252 return BFA_FALSE; 2298 return BFA_FALSE;
2253 2299
2254 if (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_FC_8G1P) { 2300 if (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_FC_8G1P) {
2255 ioc_state = readl(rb + BFA_IOC1_STATE_REG); 2301 ioc_state = readl(ioc->ioc_regs.alt_ioc_fwstate);
2256 if (!bfa_ioc_state_disabled(ioc_state)) 2302 if (!bfa_ioc_state_disabled(ioc_state))
2257 return BFA_FALSE; 2303 return BFA_FALSE;
2258 } 2304 }
@@ -2311,22 +2357,24 @@ bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc,
2311 2357
2312 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver); 2358 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
2313 2359
2314 ad_attr->cna_capable = ioc->cna; 2360 ad_attr->cna_capable = bfa_ioc_is_cna(ioc);
2315 ad_attr->trunk_capable = (ad_attr->nports > 1) && !ioc->cna && 2361 ad_attr->trunk_capable = (ad_attr->nports > 1) &&
2316 !ad_attr->is_mezz; 2362 !bfa_ioc_is_cna(ioc) && !ad_attr->is_mezz;
2317} 2363}
2318 2364
2319enum bfa_ioc_type_e 2365enum bfa_ioc_type_e
2320bfa_ioc_get_type(struct bfa_ioc_s *ioc) 2366bfa_ioc_get_type(struct bfa_ioc_s *ioc)
2321{ 2367{
2322 if (!ioc->ctdev || ioc->fcmode) 2368 enum bfi_port_mode mode;
2323 return BFA_IOC_TYPE_FC; 2369
2324 else if (ioc->clscode == BFI_PCIFN_CLASS_FC) 2370 if (ioc->clscode == BFI_PCIFN_CLASS_ETH)
2325 return BFA_IOC_TYPE_FCoE;
2326 else {
2327 WARN_ON(ioc->clscode != BFI_PCIFN_CLASS_ETH);
2328 return BFA_IOC_TYPE_LL; 2371 return BFA_IOC_TYPE_LL;
2329 } 2372
2373 WARN_ON(ioc->clscode != BFI_PCIFN_CLASS_FC);
2374
2375 mode = (ioc->port_id == 0) ? ioc->port0_mode : ioc->port1_mode;
2376 return (mode == BFI_PORT_MODE_FC)
2377 ? BFA_IOC_TYPE_FC : BFA_IOC_TYPE_FCoE;
2330} 2378}
2331 2379
2332void 2380void
@@ -2479,7 +2527,7 @@ bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc)
2479bfa_boolean_t 2527bfa_boolean_t
2480bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc) 2528bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc)
2481{ 2529{
2482 return ioc->fcmode || !bfa_asic_id_ct(ioc->pcidev.device_id); 2530 return ioc->fcmode || bfa_asic_id_cb(ioc->pcidev.device_id);
2483} 2531}
2484 2532
2485/* 2533/*
diff --git a/drivers/scsi/bfa/bfa_ioc.h b/drivers/scsi/bfa/bfa_ioc.h
index ff8e21d579df..39382ea21449 100644
--- a/drivers/scsi/bfa/bfa_ioc.h
+++ b/drivers/scsi/bfa/bfa_ioc.h
@@ -246,8 +246,6 @@ struct bfa_ioc_s {
246 struct bfa_trc_mod_s *trcmod; 246 struct bfa_trc_mod_s *trcmod;
247 struct bfa_ioc_drv_stats_s stats; 247 struct bfa_ioc_drv_stats_s stats;
248 bfa_boolean_t fcmode; 248 bfa_boolean_t fcmode;
249 bfa_boolean_t ctdev;
250 bfa_boolean_t cna;
251 bfa_boolean_t pllinit; 249 bfa_boolean_t pllinit;
252 bfa_boolean_t stats_busy; /* outstanding stats */ 250 bfa_boolean_t stats_busy; /* outstanding stats */
253 u8 port_id; 251 u8 port_id;
@@ -257,10 +255,14 @@ struct bfa_ioc_s {
257 struct bfa_ioc_mbox_mod_s mbox_mod; 255 struct bfa_ioc_mbox_mod_s mbox_mod;
258 struct bfa_ioc_hwif_s *ioc_hwif; 256 struct bfa_ioc_hwif_s *ioc_hwif;
259 struct bfa_iocpf_s iocpf; 257 struct bfa_iocpf_s iocpf;
258 enum bfi_asic_gen asic_gen;
259 enum bfi_asic_mode asic_mode;
260 enum bfi_port_mode port0_mode;
261 enum bfi_port_mode port1_mode;
260}; 262};
261 263
262struct bfa_ioc_hwif_s { 264struct bfa_ioc_hwif_s {
263 bfa_status_t (*ioc_pll_init) (void __iomem *rb, bfa_boolean_t fcmode); 265 bfa_status_t (*ioc_pll_init) (void __iomem *rb, enum bfi_asic_mode m);
264 bfa_boolean_t (*ioc_firmware_lock) (struct bfa_ioc_s *ioc); 266 bfa_boolean_t (*ioc_firmware_lock) (struct bfa_ioc_s *ioc);
265 void (*ioc_firmware_unlock) (struct bfa_ioc_s *ioc); 267 void (*ioc_firmware_unlock) (struct bfa_ioc_s *ioc);
266 void (*ioc_reg_init) (struct bfa_ioc_s *ioc); 268 void (*ioc_reg_init) (struct bfa_ioc_s *ioc);
@@ -280,6 +282,10 @@ struct bfa_ioc_hwif_s {
280#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id) 282#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
281#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva) 283#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
282#define bfa_ioc_portid(__ioc) ((__ioc)->port_id) 284#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
285#define bfa_ioc_asic_gen(__ioc) ((__ioc)->asic_gen)
286#define bfa_ioc_is_cna(__ioc) \
287 ((bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_FCoE) || \
288 (bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_LL))
283#define bfa_ioc_fetch_stats(__ioc, __stats) \ 289#define bfa_ioc_fetch_stats(__ioc, __stats) \
284 (((__stats)->drv_stats) = (__ioc)->stats) 290 (((__stats)->drv_stats) = (__ioc)->stats)
285#define bfa_ioc_clr_stats(__ioc) \ 291#define bfa_ioc_clr_stats(__ioc) \
@@ -293,12 +299,9 @@ struct bfa_ioc_hwif_s {
293 299
294#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++) 300#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
295#define BFA_IOC_FWIMG_MINSZ (16 * 1024) 301#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
296#define BFA_IOC_FWIMG_TYPE(__ioc) \ 302#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
297 (((__ioc)->ctdev) ? \ 303 ((bfa_ioc_asic_gen(__ioc) == BFI_ASIC_GEN_CB) \
298 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \ 304 ? BFI_SMEM_CB_SIZE : BFI_SMEM_CT_SIZE)
299 BFI_IMAGE_CB_FC)
300#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
301 (((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
302#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS) 305#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
303#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS) 306#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
304#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS) 307#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
@@ -311,7 +314,7 @@ void bfa_ioc_mbox_register(struct bfa_ioc_s *ioc,
311 bfa_ioc_mbox_mcfunc_t *mcfuncs); 314 bfa_ioc_mbox_mcfunc_t *mcfuncs);
312void bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc); 315void bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc);
313void bfa_ioc_mbox_send(struct bfa_ioc_s *ioc, void *ioc_msg, int len); 316void bfa_ioc_mbox_send(struct bfa_ioc_s *ioc, void *ioc_msg, int len);
314void bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg); 317bfa_boolean_t bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg);
315void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc, 318void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
316 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg); 319 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
317 320
@@ -321,21 +324,25 @@ void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
321 324
322#define bfa_ioc_pll_init_asic(__ioc) \ 325#define bfa_ioc_pll_init_asic(__ioc) \
323 ((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \ 326 ((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
324 (__ioc)->fcmode)) 327 (__ioc)->asic_mode))
325 328
326bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc); 329bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc);
327bfa_status_t bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode); 330bfa_status_t bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode mode);
328bfa_boolean_t bfa_ioc_ct_pll_init_complete(void __iomem *rb); 331bfa_status_t bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode mode);
329bfa_status_t bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode); 332bfa_status_t bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode);
330 333
331#define bfa_ioc_isr_mode_set(__ioc, __msix) \ 334#define bfa_ioc_isr_mode_set(__ioc, __msix) do { \
332 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix)) 335 if ((__ioc)->ioc_hwif->ioc_isr_mode_set) \
336 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix)); \
337} while (0)
333#define bfa_ioc_ownership_reset(__ioc) \ 338#define bfa_ioc_ownership_reset(__ioc) \
334 ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc)) 339 ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
335 340
336 341
337void bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc);
338void bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc); 342void bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc);
343void bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc);
344void bfa_ioc_set_ct2_hwif(struct bfa_ioc_s *ioc);
345void bfa_ioc_ct2_poweron(struct bfa_ioc_s *ioc);
339 346
340void bfa_ioc_attach(struct bfa_ioc_s *ioc, void *bfa, 347void bfa_ioc_attach(struct bfa_ioc_s *ioc, void *bfa,
341 struct bfa_ioc_cbfn_s *cbfn, struct bfa_timer_mod_s *timer_mod); 348 struct bfa_ioc_cbfn_s *cbfn, struct bfa_timer_mod_s *timer_mod);
@@ -349,7 +356,7 @@ void bfa_ioc_disable(struct bfa_ioc_s *ioc);
349bfa_boolean_t bfa_ioc_intx_claim(struct bfa_ioc_s *ioc); 356bfa_boolean_t bfa_ioc_intx_claim(struct bfa_ioc_s *ioc);
350 357
351void bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, 358void bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type,
352 u32 boot_param); 359 u32 boot_env);
353void bfa_ioc_isr(struct bfa_ioc_s *ioc, struct bfi_mbmsg_s *msg); 360void bfa_ioc_isr(struct bfa_ioc_s *ioc, struct bfi_mbmsg_s *msg);
354void bfa_ioc_error_isr(struct bfa_ioc_s *ioc); 361void bfa_ioc_error_isr(struct bfa_ioc_s *ioc);
355bfa_boolean_t bfa_ioc_is_operational(struct bfa_ioc_s *ioc); 362bfa_boolean_t bfa_ioc_is_operational(struct bfa_ioc_s *ioc);
@@ -397,50 +404,64 @@ mac_t bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc);
397/* 404/*
398 * F/W Image Size & Chunk 405 * F/W Image Size & Chunk
399 */ 406 */
400extern u32 bfi_image_ct_fc_size; 407extern u32 bfi_image_cb_size;
401extern u32 bfi_image_ct_cna_size; 408extern u32 bfi_image_ct_size;
402extern u32 bfi_image_cb_fc_size; 409extern u32 bfi_image_ct2_size;
403extern u32 *bfi_image_ct_fc; 410extern u32 *bfi_image_cb;
404extern u32 *bfi_image_ct_cna; 411extern u32 *bfi_image_ct;
405extern u32 *bfi_image_cb_fc; 412extern u32 *bfi_image_ct2;
406 413
407static inline u32 * 414static inline u32 *
408bfi_image_ct_fc_get_chunk(u32 off) 415bfi_image_cb_get_chunk(u32 off)
409{ return (u32 *)(bfi_image_ct_fc + off); } 416{
417 return (u32 *)(bfi_image_cb + off);
418}
410 419
411static inline u32 * 420static inline u32 *
412bfi_image_ct_cna_get_chunk(u32 off) 421bfi_image_ct_get_chunk(u32 off)
413{ return (u32 *)(bfi_image_ct_cna + off); } 422{
423 return (u32 *)(bfi_image_ct + off);
424}
414 425
415static inline u32 * 426static inline u32 *
416bfi_image_cb_fc_get_chunk(u32 off) 427bfi_image_ct2_get_chunk(u32 off)
417{ return (u32 *)(bfi_image_cb_fc + off); } 428{
429 return (u32 *)(bfi_image_ct2 + off);
430}
418 431
419static inline u32* 432static inline u32*
420bfa_cb_image_get_chunk(int type, u32 off) 433bfa_cb_image_get_chunk(enum bfi_asic_gen asic_gen, u32 off)
421{ 434{
422 switch (type) { 435 switch (asic_gen) {
423 case BFI_IMAGE_CT_FC: 436 case BFI_ASIC_GEN_CB:
424 return bfi_image_ct_fc_get_chunk(off); break; 437 return bfi_image_cb_get_chunk(off);
425 case BFI_IMAGE_CT_CNA: 438 break;
426 return bfi_image_ct_cna_get_chunk(off); break; 439 case BFI_ASIC_GEN_CT:
427 case BFI_IMAGE_CB_FC: 440 return bfi_image_ct_get_chunk(off);
428 return bfi_image_cb_fc_get_chunk(off); break; 441 break;
429 default: return NULL; 442 case BFI_ASIC_GEN_CT2:
443 return bfi_image_ct2_get_chunk(off);
444 break;
445 default:
446 return NULL;
430 } 447 }
431} 448}
432 449
433static inline u32 450static inline u32
434bfa_cb_image_get_size(int type) 451bfa_cb_image_get_size(enum bfi_asic_gen asic_gen)
435{ 452{
436 switch (type) { 453 switch (asic_gen) {
437 case BFI_IMAGE_CT_FC: 454 case BFI_ASIC_GEN_CB:
438 return bfi_image_ct_fc_size; break; 455 return bfi_image_cb_size;
439 case BFI_IMAGE_CT_CNA: 456 break;
440 return bfi_image_ct_cna_size; break; 457 case BFI_ASIC_GEN_CT:
441 case BFI_IMAGE_CB_FC: 458 return bfi_image_ct_size;
442 return bfi_image_cb_fc_size; break; 459 break;
443 default: return 0; 460 case BFI_ASIC_GEN_CT2:
461 return bfi_image_ct2_size;
462 break;
463 default:
464 return 0;
444 } 465 }
445} 466}
446 467
diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c
index 89ae4c8f95a2..e858bc0c48d0 100644
--- a/drivers/scsi/bfa/bfa_ioc_cb.c
+++ b/drivers/scsi/bfa/bfa_ioc_cb.c
@@ -17,7 +17,7 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_ioc.h" 19#include "bfa_ioc.h"
20#include "bfi_cbreg.h" 20#include "bfi_reg.h"
21#include "bfa_defs.h" 21#include "bfa_defs.h"
22 22
23BFA_TRC_FILE(CNA, IOC_CB); 23BFA_TRC_FILE(CNA, IOC_CB);
@@ -77,7 +77,7 @@ bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
77 77
78 bfa_ioc_fwver_get(ioc, &fwhdr); 78 bfa_ioc_fwver_get(ioc, &fwhdr);
79 79
80 if (swab32(fwhdr.exec) == BFI_BOOT_TYPE_NORMAL) 80 if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL)
81 return BFA_TRUE; 81 return BFA_TRUE;
82 82
83 bfa_trc(ioc, fwstate); 83 bfa_trc(ioc, fwstate);
@@ -98,7 +98,7 @@ bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
98static void 98static void
99bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) 99bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc)
100{ 100{
101 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set); 101 writel(~0U, ioc->ioc_regs.err_set);
102 readl(ioc->ioc_regs.err_set); 102 readl(ioc->ioc_regs.err_set);
103} 103}
104 104
@@ -152,8 +152,8 @@ bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
152 */ 152 */
153 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); 153 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
154 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); 154 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
155 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG); 155 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
156 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG); 156 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
157 157
158 /* 158 /*
159 * IOC semaphore registers and serialization 159 * IOC semaphore registers and serialization
@@ -285,18 +285,18 @@ bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc)
285} 285}
286 286
287bfa_status_t 287bfa_status_t
288bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode) 288bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode)
289{ 289{
290 u32 pll_sclk, pll_fclk; 290 u32 pll_sclk, pll_fclk;
291 291
292 pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN | 292 pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN |
293 __APP_PLL_212_P0_1(3U) | 293 __APP_PLL_SCLK_P0_1(3U) |
294 __APP_PLL_212_JITLMT0_1(3U) | 294 __APP_PLL_SCLK_JITLMT0_1(3U) |
295 __APP_PLL_212_CNTLMT0_1(3U); 295 __APP_PLL_SCLK_CNTLMT0_1(3U);
296 pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN | 296 pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN |
297 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) | 297 __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
298 __APP_PLL_400_JITLMT0_1(3U) | 298 __APP_PLL_LCLK_JITLMT0_1(3U) |
299 __APP_PLL_400_CNTLMT0_1(3U); 299 __APP_PLL_LCLK_CNTLMT0_1(3U);
300 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); 300 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
301 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); 301 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
302 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 302 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
@@ -305,24 +305,24 @@ bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
305 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 305 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
306 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 306 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
307 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 307 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
308 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); 308 writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
309 writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET, 309 writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
310 rb + APP_PLL_212_CTL_REG); 310 rb + APP_PLL_SCLK_CTL_REG);
311 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); 311 writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
312 writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET, 312 writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
313 rb + APP_PLL_400_CTL_REG); 313 rb + APP_PLL_LCLK_CTL_REG);
314 udelay(2); 314 udelay(2);
315 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); 315 writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
316 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); 316 writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
317 writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET, 317 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
318 rb + APP_PLL_212_CTL_REG); 318 rb + APP_PLL_SCLK_CTL_REG);
319 writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET, 319 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
320 rb + APP_PLL_400_CTL_REG); 320 rb + APP_PLL_LCLK_CTL_REG);
321 udelay(2000); 321 udelay(2000);
322 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 322 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
323 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 323 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
324 writel(pll_sclk, (rb + APP_PLL_212_CTL_REG)); 324 writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
325 writel(pll_fclk, (rb + APP_PLL_400_CTL_REG)); 325 writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));
326 326
327 return BFA_STATUS_OK; 327 return BFA_STATUS_OK;
328} 328}
diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c
index 93612520f0d2..118ed8c7fc2e 100644
--- a/drivers/scsi/bfa/bfa_ioc_ct.c
+++ b/drivers/scsi/bfa/bfa_ioc_ct.c
@@ -17,7 +17,7 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_ioc.h" 19#include "bfa_ioc.h"
20#include "bfi_ctreg.h" 20#include "bfi_reg.h"
21#include "bfa_defs.h" 21#include "bfa_defs.h"
22 22
23BFA_TRC_FILE(CNA, IOC_CT); 23BFA_TRC_FILE(CNA, IOC_CT);
@@ -36,9 +36,6 @@ BFA_TRC_FILE(CNA, IOC_CT);
36 */ 36 */
37static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc); 37static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc);
38static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc); 38static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc);
39static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc);
40static void bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc);
41static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
42static void bfa_ioc_ct_notify_fail(struct bfa_ioc_s *ioc); 39static void bfa_ioc_ct_notify_fail(struct bfa_ioc_s *ioc);
43static void bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc); 40static void bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc);
44static bfa_boolean_t bfa_ioc_ct_sync_start(struct bfa_ioc_s *ioc); 41static bfa_boolean_t bfa_ioc_ct_sync_start(struct bfa_ioc_s *ioc);
@@ -48,29 +45,7 @@ static void bfa_ioc_ct_sync_ack(struct bfa_ioc_s *ioc);
48static bfa_boolean_t bfa_ioc_ct_sync_complete(struct bfa_ioc_s *ioc); 45static bfa_boolean_t bfa_ioc_ct_sync_complete(struct bfa_ioc_s *ioc);
49 46
50static struct bfa_ioc_hwif_s hwif_ct; 47static struct bfa_ioc_hwif_s hwif_ct;
51 48static struct bfa_ioc_hwif_s hwif_ct2;
52/*
53 * Called from bfa_ioc_attach() to map asic specific calls.
54 */
55void
56bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc)
57{
58 hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
59 hwif_ct.ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
60 hwif_ct.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
61 hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
62 hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
63 hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
64 hwif_ct.ioc_notify_fail = bfa_ioc_ct_notify_fail;
65 hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
66 hwif_ct.ioc_sync_start = bfa_ioc_ct_sync_start;
67 hwif_ct.ioc_sync_join = bfa_ioc_ct_sync_join;
68 hwif_ct.ioc_sync_leave = bfa_ioc_ct_sync_leave;
69 hwif_ct.ioc_sync_ack = bfa_ioc_ct_sync_ack;
70 hwif_ct.ioc_sync_complete = bfa_ioc_ct_sync_complete;
71
72 ioc->ioc_hwif = &hwif_ct;
73}
74 49
75/* 50/*
76 * Return true if firmware of current driver matches the running firmware. 51 * Return true if firmware of current driver matches the running firmware.
@@ -85,13 +60,13 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
85 /* 60 /*
86 * Firmware match check is relevant only for CNA. 61 * Firmware match check is relevant only for CNA.
87 */ 62 */
88 if (!ioc->cna) 63 if (!bfa_ioc_is_cna(ioc))
89 return BFA_TRUE; 64 return BFA_TRUE;
90 65
91 /* 66 /*
92 * If bios boot (flash based) -- do not increment usage count 67 * If bios boot (flash based) -- do not increment usage count
93 */ 68 */
94 if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < 69 if (bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)) <
95 BFA_IOC_FWIMG_MINSZ) 70 BFA_IOC_FWIMG_MINSZ)
96 return BFA_TRUE; 71 return BFA_TRUE;
97 72
@@ -145,13 +120,13 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc)
145 /* 120 /*
146 * Firmware lock is relevant only for CNA. 121 * Firmware lock is relevant only for CNA.
147 */ 122 */
148 if (!ioc->cna) 123 if (!bfa_ioc_is_cna(ioc))
149 return; 124 return;
150 125
151 /* 126 /*
152 * If bios boot (flash based) -- do not decrement usage count 127 * If bios boot (flash based) -- do not decrement usage count
153 */ 128 */
154 if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < 129 if (bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)) <
155 BFA_IOC_FWIMG_MINSZ) 130 BFA_IOC_FWIMG_MINSZ)
156 return; 131 return;
157 132
@@ -175,14 +150,14 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc)
175static void 150static void
176bfa_ioc_ct_notify_fail(struct bfa_ioc_s *ioc) 151bfa_ioc_ct_notify_fail(struct bfa_ioc_s *ioc)
177{ 152{
178 if (ioc->cna) { 153 if (bfa_ioc_is_cna(ioc)) {
179 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); 154 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
180 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); 155 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
181 /* Wait for halt to take effect */ 156 /* Wait for halt to take effect */
182 readl(ioc->ioc_regs.ll_halt); 157 readl(ioc->ioc_regs.ll_halt);
183 readl(ioc->ioc_regs.alt_ll_halt); 158 readl(ioc->ioc_regs.alt_ll_halt);
184 } else { 159 } else {
185 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set); 160 writel(~0U, ioc->ioc_regs.err_set);
186 readl(ioc->ioc_regs.err_set); 161 readl(ioc->ioc_regs.err_set);
187 } 162 }
188} 163}
@@ -190,7 +165,7 @@ bfa_ioc_ct_notify_fail(struct bfa_ioc_s *ioc)
190/* 165/*
191 * Host to LPU mailbox message addresses 166 * Host to LPU mailbox message addresses
192 */ 167 */
193static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { 168static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = {
194 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, 169 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
195 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }, 170 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
196 { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 }, 171 { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
@@ -200,21 +175,28 @@ static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
200/* 175/*
201 * Host <-> LPU mailbox command/status registers - port 0 176 * Host <-> LPU mailbox command/status registers - port 0
202 */ 177 */
203static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = { 178static struct { u32 hfn, lpu; } ct_p0reg[] = {
204 { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT }, 179 { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
205 { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT }, 180 { HOSTFN1_LPU0_CMD_STAT, LPU0_HOSTFN1_CMD_STAT },
206 { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT }, 181 { HOSTFN2_LPU0_CMD_STAT, LPU0_HOSTFN2_CMD_STAT },
207 { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT } 182 { HOSTFN3_LPU0_CMD_STAT, LPU0_HOSTFN3_CMD_STAT }
208}; 183};
209 184
210/* 185/*
211 * Host <-> LPU mailbox command/status registers - port 1 186 * Host <-> LPU mailbox command/status registers - port 1
212 */ 187 */
213static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = { 188static struct { u32 hfn, lpu; } ct_p1reg[] = {
214 { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT }, 189 { HOSTFN0_LPU1_CMD_STAT, LPU1_HOSTFN0_CMD_STAT },
215 { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT }, 190 { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT },
216 { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT }, 191 { HOSTFN2_LPU1_CMD_STAT, LPU1_HOSTFN2_CMD_STAT },
217 { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT } 192 { HOSTFN3_LPU1_CMD_STAT, LPU1_HOSTFN3_CMD_STAT }
193};
194
195static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn, hfn, lpu; } ct2_reg[] = {
196 { CT2_HOSTFN_LPU0_MBOX0, CT2_LPU0_HOSTFN_MBOX0, CT2_HOSTFN_PAGE_NUM,
197 CT2_HOSTFN_LPU0_CMD_STAT, CT2_LPU0_HOSTFN_CMD_STAT },
198 { CT2_HOSTFN_LPU1_MBOX0, CT2_LPU1_HOSTFN_MBOX0, CT2_HOSTFN_PAGE_NUM,
199 CT2_HOSTFN_LPU1_CMD_STAT, CT2_LPU1_HOSTFN_CMD_STAT },
218}; 200};
219 201
220static void 202static void
@@ -225,24 +207,24 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
225 207
226 rb = bfa_ioc_bar0(ioc); 208 rb = bfa_ioc_bar0(ioc);
227 209
228 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; 210 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox;
229 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; 211 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox;
230 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; 212 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn;
231 213
232 if (ioc->port_id == 0) { 214 if (ioc->port_id == 0) {
233 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; 215 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
234 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; 216 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
235 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; 217 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
236 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn; 218 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn;
237 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu; 219 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu;
238 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; 220 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
239 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; 221 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
240 } else { 222 } else {
241 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); 223 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
242 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); 224 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
243 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; 225 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
244 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn; 226 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;
245 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu; 227 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
246 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; 228 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
247 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; 229 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
248 } 230 }
@@ -252,8 +234,8 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
252 */ 234 */
253 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); 235 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
254 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); 236 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
255 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG); 237 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
256 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG); 238 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
257 239
258 /* 240 /*
259 * IOC semaphore registers and serialization 241 * IOC semaphore registers and serialization
@@ -276,6 +258,63 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
276 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); 258 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
277} 259}
278 260
261static void
262bfa_ioc_ct2_reg_init(struct bfa_ioc_s *ioc)
263{
264 void __iomem *rb;
265 int port = bfa_ioc_portid(ioc);
266
267 rb = bfa_ioc_bar0(ioc);
268
269 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox;
270 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox;
271 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn;
272 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn;
273 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu;
274
275 if (port == 0) {
276 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG;
277 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
278 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;
279 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
280 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
281 } else {
282 ioc->ioc_regs.heartbeat = (rb + CT2_BFA_IOC1_HBEAT_REG);
283 ioc->ioc_regs.ioc_fwstate = (rb + CT2_BFA_IOC1_STATE_REG);
284 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
285 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
286 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
287 }
288
289 /*
290 * PSS control registers
291 */
292 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
293 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
294 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + CT2_APP_PLL_LCLK_CTL_REG);
295 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + CT2_APP_PLL_SCLK_CTL_REG);
296
297 /*
298 * IOC semaphore registers and serialization
299 */
300 ioc->ioc_regs.ioc_sem_reg = (rb + CT2_HOST_SEM0_REG);
301 ioc->ioc_regs.ioc_usage_sem_reg = (rb + CT2_HOST_SEM1_REG);
302 ioc->ioc_regs.ioc_init_sem_reg = (rb + CT2_HOST_SEM2_REG);
303 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
304 ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
305
306 /*
307 * sram memory access
308 */
309 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
310 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
311
312 /*
313 * err set reg : for notification of hb failure in fcmode
314 */
315 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
316}
317
279/* 318/*
280 * Initialize IOC to port mapping. 319 * Initialize IOC to port mapping.
281 */ 320 */
@@ -298,6 +337,15 @@ bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
298 bfa_trc(ioc, ioc->port_id); 337 bfa_trc(ioc, ioc->port_id);
299} 338}
300 339
340static void
341bfa_ioc_ct2_map_port(struct bfa_ioc_s *ioc)
342{
343 ioc->port_id = bfa_ioc_pcifn(ioc) % 2;
344
345 bfa_trc(ioc, bfa_ioc_pcifn(ioc));
346 bfa_trc(ioc, ioc->port_id);
347}
348
301/* 349/*
302 * Set interrupt mode for a function: INTX or MSIX 350 * Set interrupt mode for a function: INTX or MSIX
303 */ 351 */
@@ -316,7 +364,7 @@ bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
316 /* 364 /*
317 * If already in desired mode, do not change anything 365 * If already in desired mode, do not change anything
318 */ 366 */
319 if (!msix && mode) 367 if ((!msix && mode) || (msix && !mode))
320 return; 368 return;
321 369
322 if (msix) 370 if (msix)
@@ -338,7 +386,7 @@ static void
338bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc) 386bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
339{ 387{
340 388
341 if (ioc->cna) { 389 if (bfa_ioc_is_cna(ioc)) {
342 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); 390 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
343 writel(0, ioc->ioc_regs.ioc_usage_reg); 391 writel(0, ioc->ioc_regs.ioc_usage_reg);
344 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); 392 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
@@ -449,32 +497,91 @@ bfa_ioc_ct_sync_complete(struct bfa_ioc_s *ioc)
449 return BFA_FALSE; 497 return BFA_FALSE;
450} 498}
451 499
500/**
501 * Called from bfa_ioc_attach() to map asic specific calls.
502 */
503static void
504bfa_ioc_set_ctx_hwif(struct bfa_ioc_s *ioc, struct bfa_ioc_hwif_s *hwif)
505{
506 hwif->ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
507 hwif->ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
508 hwif->ioc_notify_fail = bfa_ioc_ct_notify_fail;
509 hwif->ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
510 hwif->ioc_sync_start = bfa_ioc_ct_sync_start;
511 hwif->ioc_sync_join = bfa_ioc_ct_sync_join;
512 hwif->ioc_sync_leave = bfa_ioc_ct_sync_leave;
513 hwif->ioc_sync_ack = bfa_ioc_ct_sync_ack;
514 hwif->ioc_sync_complete = bfa_ioc_ct_sync_complete;
515}
516
517/**
518 * Called from bfa_ioc_attach() to map asic specific calls.
519 */
520void
521bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc)
522{
523 bfa_ioc_set_ctx_hwif(ioc, &hwif_ct);
524
525 hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
526 hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
527 hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
528 hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
529 ioc->ioc_hwif = &hwif_ct;
530}
531
532/**
533 * Called from bfa_ioc_attach() to map asic specific calls.
534 */
535void
536bfa_ioc_set_ct2_hwif(struct bfa_ioc_s *ioc)
537{
538 bfa_ioc_set_ctx_hwif(ioc, &hwif_ct2);
539
540 hwif_ct2.ioc_pll_init = bfa_ioc_ct2_pll_init;
541 hwif_ct2.ioc_reg_init = bfa_ioc_ct2_reg_init;
542 hwif_ct2.ioc_map_port = bfa_ioc_ct2_map_port;
543 hwif_ct2.ioc_isr_mode_set = NULL;
544 ioc->ioc_hwif = &hwif_ct2;
545}
546
452/* 547/*
453 * Check the firmware state to know if pll_init has been completed already 548 * Temporary workaround for MSI-X resource allocation for catapult-2.
454 */ 549 */
455bfa_boolean_t 550#define HOSTFN_MSIX_DEFAULT 16
456bfa_ioc_ct_pll_init_complete(void __iomem *rb) 551#define HOSTFN_MSIX_VT_OFST_NUMVT 0x3013c
552#define __MSIX_VT_NUMVT__MK 0x003ff800
553#define __MSIX_VT_NUMVT__SH 11
554#define __MSIX_VT_NUMVT_(_v) ((_v) << __MSIX_VT_NUMVT__SH)
555void
556bfa_ioc_ct2_poweron(struct bfa_ioc_s *ioc)
457{ 557{
458 if ((readl(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) || 558 void __iomem *rb = ioc->pcidev.pci_bar_kva;
459 (readl(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP)) 559 u32 r32;
460 return BFA_TRUE;
461 560
462 return BFA_FALSE; 561 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
562 if (r32 & __MSIX_VT_NUMVT__MK)
563 return;
564
565 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) |
566 HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
567 rb + HOSTFN_MSIX_VT_OFST_NUMVT);
463} 568}
464 569
465bfa_status_t 570bfa_status_t
466bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode) 571bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
467{ 572{
468 u32 pll_sclk, pll_fclk, r32; 573 u32 pll_sclk, pll_fclk, r32;
574 bfa_boolean_t fcmode = (mode == BFI_ASIC_MODE_FC);
575
576 pll_sclk = __APP_PLL_SCLK_LRESETN | __APP_PLL_SCLK_ENARST |
577 __APP_PLL_SCLK_RSEL200500 | __APP_PLL_SCLK_P0_1(3U) |
578 __APP_PLL_SCLK_JITLMT0_1(3U) |
579 __APP_PLL_SCLK_CNTLMT0_1(1U);
580 pll_fclk = __APP_PLL_LCLK_LRESETN | __APP_PLL_LCLK_ENARST |
581 __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
582 __APP_PLL_LCLK_JITLMT0_1(3U) |
583 __APP_PLL_LCLK_CNTLMT0_1(1U);
469 584
470 pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
471 __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
472 __APP_PLL_312_JITLMT0_1(3U) |
473 __APP_PLL_312_CNTLMT0_1(1U);
474 pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
475 __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
476 __APP_PLL_425_JITLMT0_1(3U) |
477 __APP_PLL_425_CNTLMT0_1(1U);
478 if (fcmode) { 585 if (fcmode) {
479 writel(0, (rb + OP_MODE)); 586 writel(0, (rb + OP_MODE));
480 writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 | 587 writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 |
@@ -491,20 +598,21 @@ bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
491 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 598 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
492 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 599 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
493 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 600 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
494 writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET, 601 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
495 rb + APP_PLL_312_CTL_REG); 602 rb + APP_PLL_SCLK_CTL_REG);
496 writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET, 603 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
497 rb + APP_PLL_425_CTL_REG); 604 rb + APP_PLL_LCLK_CTL_REG);
498 writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE, 605 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET |
499 rb + APP_PLL_312_CTL_REG); 606 __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG);
500 writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE, 607 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET |
501 rb + APP_PLL_425_CTL_REG); 608 __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG);
502 readl(rb + HOSTFN0_INT_MSK); 609 readl(rb + HOSTFN0_INT_MSK);
503 udelay(2000); 610 udelay(2000);
504 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 611 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
505 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 612 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
506 writel(pll_sclk | __APP_PLL_312_ENABLE, rb + APP_PLL_312_CTL_REG); 613 writel(pll_sclk | __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG);
507 writel(pll_fclk | __APP_PLL_425_ENABLE, rb + APP_PLL_425_CTL_REG); 614 writel(pll_fclk | __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG);
615
508 if (!fcmode) { 616 if (!fcmode) {
509 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); 617 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
510 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); 618 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
@@ -524,3 +632,151 @@ bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
524 writel(0, (rb + MBIST_CTL_REG)); 632 writel(0, (rb + MBIST_CTL_REG));
525 return BFA_STATUS_OK; 633 return BFA_STATUS_OK;
526} 634}
635
636static struct { u32 sclk, speed, half_speed; } ct2_pll[] = {
637 {0}, /* unused */
638 {__APP_PLL_SCLK_CLK_DIV2, 0, 0}, /* FC 8G */
639 {0, __APP_LPU_SPEED, 0}, /* FC 16G */
640 {__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2, 0, /* ETH */
641 __APP_LPUCLK_HALFSPEED},
642 {0, __APP_LPU_SPEED, 0}, /* COMBO */
643};
644
645static void
646bfa_ioc_ct2_sclk_init(void __iomem *rb, enum bfi_asic_mode mode)
647{
648 u32 r32;
649
650 /*
651 * put s_clk PLL and PLL FSM in reset
652 */
653 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
654 r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);
655 r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |
656 __APP_PLL_SCLK_LOGIC_SOFT_RESET);
657 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
658
659 /*
660 * select clock speed based on mode
661 */
662 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
663 r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
664 writel(r32 | ct2_pll[mode].sclk, (rb + CT2_APP_PLL_SCLK_CTL_REG));
665
666 /*
667 * remove clock gating for ethernet subsystem for ethernet mode
668 */
669 if (mode == BFI_ASIC_MODE_ETH) {
670 r32 = readl((rb + CT2_CHIP_MISC_PRG));
671 writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG));
672
673 r32 = readl((rb + CT2_PCIE_MISC_REG));
674 writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG));
675 }
676
677 /*
678 * set sclk value
679 */
680 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
681 r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |
682 __APP_PLL_SCLK_CLK_DIV2);
683 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
684
685 /*
686 * poll for s_clk lock or delay 1ms
687 */
688 udelay(1000);
689
690 /*
691 * release soft reset on s_clk & l_clk
692 */
693 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
694 writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
695 (rb + CT2_APP_PLL_SCLK_CTL_REG));
696}
697
698static void
699bfa_ioc_ct2_lclk_init(void __iomem *rb, enum bfi_asic_mode mode)
700{
701 u32 r32;
702
703 /*
704 * put l_clk PLL and PLL FSM in reset
705 */
706 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
707 r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);
708 r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |
709 __APP_PLL_LCLK_LOGIC_SOFT_RESET);
710 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
711
712 /*
713 * set LPU speed
714 */
715 r32 = readl((rb + CT2_CHIP_MISC_PRG));
716 writel(r32 | ct2_pll[mode].speed,
717 (rb + CT2_CHIP_MISC_PRG));
718
719 /*
720 * set LPU half speed
721 */
722 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
723 writel(r32 | ct2_pll[mode].half_speed,
724 (rb + CT2_APP_PLL_LCLK_CTL_REG));
725
726 /*
727 * set lclk for mode
728 */
729 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
730 r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);
731 if (mode == BFI_ASIC_MODE_FC || mode == BFI_ASIC_MODE_ETH)
732 r32 |= 0x20c1731b;
733 else
734 r32 |= 0x2081731b;
735 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
736
737 /*
738 * poll for s_clk lock or delay 1ms
739 */
740 udelay(1000);
741
742 /*
743 * release soft reset on s_clk & l_clk
744 */
745 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
746 writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
747 (rb + CT2_APP_PLL_LCLK_CTL_REG));
748}
749
750static void
751bfa_ioc_ct2_mem_init(void __iomem *rb, enum bfi_asic_mode mode)
752{
753 bfa_boolean_t fcmode;
754 u32 r32;
755
756 fcmode = (mode == BFI_ASIC_MODE_FC) || (mode == BFI_ASIC_MODE_FC16);
757 if (!fcmode) {
758 writel(__PMM_1T_RESET_P, (rb + CT2_PMM_1T_CONTROL_REG_P0));
759 writel(__PMM_1T_RESET_P, (rb + CT2_PMM_1T_CONTROL_REG_P1));
760 }
761
762 r32 = readl((rb + PSS_CTL_REG));
763 r32 &= ~__PSS_LMEM_RESET;
764 writel(r32, (rb + PSS_CTL_REG));
765 udelay(1000);
766
767 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
768 udelay(1000);
769 writel(0, (rb + CT2_MBIST_CTL_REG));
770}
771
772bfa_status_t
773bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
774{
775 bfa_ioc_ct2_sclk_init(rb, mode);
776 bfa_ioc_ct2_lclk_init(rb, mode);
777 bfa_ioc_ct2_mem_init(rb, mode);
778
779 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
780 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));
781 return BFA_STATUS_OK;
782}
diff --git a/drivers/scsi/bfa/bfa_port.c b/drivers/scsi/bfa/bfa_port.c
index 6b759364ac90..8bb6d75f9160 100644
--- a/drivers/scsi/bfa/bfa_port.c
+++ b/drivers/scsi/bfa/bfa_port.c
@@ -24,8 +24,6 @@
24 24
25BFA_TRC_FILE(CNA, PORT); 25BFA_TRC_FILE(CNA, PORT);
26 26
27#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
28
29static void 27static void
30bfa_port_stats_swap(struct bfa_port_s *port, union bfa_port_stats_u *stats) 28bfa_port_stats_swap(struct bfa_port_s *port, union bfa_port_stats_u *stats)
31{ 29{
diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c
index 59b5e9b61d71..8ddae0d85fa8 100644
--- a/drivers/scsi/bfa/bfad.c
+++ b/drivers/scsi/bfa/bfad.c
@@ -58,12 +58,12 @@ int bfa_debugfs_enable = 1;
58int msix_disable_cb = 0, msix_disable_ct = 0; 58int msix_disable_cb = 0, msix_disable_ct = 0;
59 59
60/* Firmware releated */ 60/* Firmware releated */
61u32 bfi_image_ct_fc_size, bfi_image_ct_cna_size, bfi_image_cb_fc_size; 61u32 bfi_image_cb_size, bfi_image_ct_size, bfi_image_ct2_size;
62u32 *bfi_image_ct_fc, *bfi_image_ct_cna, *bfi_image_cb_fc; 62u32 *bfi_image_cb, *bfi_image_ct, *bfi_image_ct2;
63 63
64#define BFAD_FW_FILE_CT_FC "ctfw_fc.bin" 64#define BFAD_FW_FILE_CB "cbfw.bin"
65#define BFAD_FW_FILE_CT_CNA "ctfw_cna.bin" 65#define BFAD_FW_FILE_CT "ctfw.bin"
66#define BFAD_FW_FILE_CB_FC "cbfw_fc.bin" 66#define BFAD_FW_FILE_CT2 "ct2fw.bin"
67 67
68static u32 *bfad_load_fwimg(struct pci_dev *pdev); 68static u32 *bfad_load_fwimg(struct pci_dev *pdev);
69static void bfad_free_fwimg(void); 69static void bfad_free_fwimg(void);
@@ -71,18 +71,18 @@ static void bfad_read_firmware(struct pci_dev *pdev, u32 **bfi_image,
71 u32 *bfi_image_size, char *fw_name); 71 u32 *bfi_image_size, char *fw_name);
72 72
73static const char *msix_name_ct[] = { 73static const char *msix_name_ct[] = {
74 "ctrl",
74 "cpe0", "cpe1", "cpe2", "cpe3", 75 "cpe0", "cpe1", "cpe2", "cpe3",
75 "rme0", "rme1", "rme2", "rme3", 76 "rme0", "rme1", "rme2", "rme3" };
76 "ctrl" };
77 77
78static const char *msix_name_cb[] = { 78static const char *msix_name_cb[] = {
79 "cpe0", "cpe1", "cpe2", "cpe3", 79 "cpe0", "cpe1", "cpe2", "cpe3",
80 "rme0", "rme1", "rme2", "rme3", 80 "rme0", "rme1", "rme2", "rme3",
81 "eemc", "elpu0", "elpu1", "epss", "mlpu" }; 81 "eemc", "elpu0", "elpu1", "epss", "mlpu" };
82 82
83MODULE_FIRMWARE(BFAD_FW_FILE_CT_FC); 83MODULE_FIRMWARE(BFAD_FW_FILE_CB);
84MODULE_FIRMWARE(BFAD_FW_FILE_CT_CNA); 84MODULE_FIRMWARE(BFAD_FW_FILE_CT);
85MODULE_FIRMWARE(BFAD_FW_FILE_CB_FC); 85MODULE_FIRMWARE(BFAD_FW_FILE_CT2);
86 86
87module_param(os_name, charp, S_IRUGO | S_IWUSR); 87module_param(os_name, charp, S_IRUGO | S_IWUSR);
88MODULE_PARM_DESC(os_name, "OS name of the hba host machine"); 88MODULE_PARM_DESC(os_name, "OS name of the hba host machine");
@@ -787,6 +787,7 @@ bfad_pci_init(struct pci_dev *pdev, struct bfad_s *bfad)
787 } 787 }
788 788
789 bfad->pci_bar0_kva = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); 789 bfad->pci_bar0_kva = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
790 bfad->pci_bar2_kva = pci_iomap(pdev, 2, pci_resource_len(pdev, 2));
790 791
791 if (bfad->pci_bar0_kva == NULL) { 792 if (bfad->pci_bar0_kva == NULL) {
792 printk(KERN_ERR "Fail to map bar0\n"); 793 printk(KERN_ERR "Fail to map bar0\n");
@@ -868,6 +869,7 @@ void
868bfad_pci_uninit(struct pci_dev *pdev, struct bfad_s *bfad) 869bfad_pci_uninit(struct pci_dev *pdev, struct bfad_s *bfad)
869{ 870{
870 pci_iounmap(pdev, bfad->pci_bar0_kva); 871 pci_iounmap(pdev, bfad->pci_bar0_kva);
872 pci_iounmap(pdev, bfad->pci_bar2_kva);
871 pci_release_regions(pdev); 873 pci_release_regions(pdev);
872 pci_disable_device(pdev); 874 pci_disable_device(pdev);
873 pci_set_drvdata(pdev, NULL); 875 pci_set_drvdata(pdev, NULL);
@@ -1233,8 +1235,8 @@ bfad_install_msix_handler(struct bfad_s *bfad)
1233 for (i = 0; i < bfad->nvec; i++) { 1235 for (i = 0; i < bfad->nvec; i++) {
1234 sprintf(bfad->msix_tab[i].name, "bfa-%s-%s", 1236 sprintf(bfad->msix_tab[i].name, "bfa-%s-%s",
1235 bfad->pci_name, 1237 bfad->pci_name,
1236 ((bfa_asic_id_ct(bfad->hal_pcidev.device_id)) ? 1238 ((bfa_asic_id_cb(bfad->hal_pcidev.device_id)) ?
1237 msix_name_ct[i] : msix_name_cb[i])); 1239 msix_name_cb[i] : msix_name_ct[i]));
1238 1240
1239 error = request_irq(bfad->msix_tab[i].msix.vector, 1241 error = request_irq(bfad->msix_tab[i].msix.vector,
1240 (irq_handler_t) bfad_msix, 0, 1242 (irq_handler_t) bfad_msix, 0,
@@ -1272,8 +1274,8 @@ bfad_setup_intr(struct bfad_s *bfad)
1272 /* Set up the msix entry table */ 1274 /* Set up the msix entry table */
1273 bfad_init_msix_entry(bfad, msix_entries, mask, max_bit); 1275 bfad_init_msix_entry(bfad, msix_entries, mask, max_bit);
1274 1276
1275 if ((bfa_asic_id_ct(pdev->device) && !msix_disable_ct) || 1277 if ((bfa_asic_id_ctc(pdev->device) && !msix_disable_ct) ||
1276 (!bfa_asic_id_ct(pdev->device) && !msix_disable_cb)) { 1278 (bfa_asic_id_cb(pdev->device) && !msix_disable_cb)) {
1277 1279
1278 error = pci_enable_msix(bfad->pcidev, msix_entries, bfad->nvec); 1280 error = pci_enable_msix(bfad->pcidev, msix_entries, bfad->nvec);
1279 if (error) { 1281 if (error) {
@@ -1346,7 +1348,8 @@ bfad_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
1346 int error = -ENODEV, retval; 1348 int error = -ENODEV, retval;
1347 1349
1348 /* For single port cards - only claim function 0 */ 1350 /* For single port cards - only claim function 0 */
1349 if ((pdev->device == BFA_PCI_DEVICE_ID_FC_8G1P) && 1351 if ((pdev->device == BFA_PCI_DEVICE_ID_FC_8G1P ||
1352 pdev->device == BFA_PCI_DEVICE_ID_CT2) &&
1350 (PCI_FUNC(pdev->devfn) != 0)) 1353 (PCI_FUNC(pdev->devfn) != 0))
1351 return -ENODEV; 1354 return -ENODEV;
1352 1355
@@ -1501,6 +1504,14 @@ struct pci_device_id bfad_id_table[] = {
1501 .class = (PCI_CLASS_SERIAL_FIBER << 8), 1504 .class = (PCI_CLASS_SERIAL_FIBER << 8),
1502 .class_mask = ~0, 1505 .class_mask = ~0,
1503 }, 1506 },
1507 {
1508 .vendor = BFA_PCI_VENDOR_ID_BROCADE,
1509 .device = BFA_PCI_DEVICE_ID_CT2,
1510 .subvendor = PCI_ANY_ID,
1511 .subdevice = PCI_ANY_ID,
1512 .class = (PCI_CLASS_SERIAL_FIBER << 8),
1513 .class_mask = ~0,
1514 },
1504 1515
1505 {0, 0}, 1516 {0, 0},
1506}; 1517};
@@ -1594,33 +1605,33 @@ out:
1594static u32 * 1605static u32 *
1595bfad_load_fwimg(struct pci_dev *pdev) 1606bfad_load_fwimg(struct pci_dev *pdev)
1596{ 1607{
1597 if (pdev->device == BFA_PCI_DEVICE_ID_CT_FC) { 1608 if (pdev->device == BFA_PCI_DEVICE_ID_CT2) {
1598 if (bfi_image_ct_fc_size == 0) 1609 if (bfi_image_ct2_size == 0)
1599 bfad_read_firmware(pdev, &bfi_image_ct_fc, 1610 bfad_read_firmware(pdev, &bfi_image_ct2,
1600 &bfi_image_ct_fc_size, BFAD_FW_FILE_CT_FC); 1611 &bfi_image_ct2_size, BFAD_FW_FILE_CT2);
1601 return bfi_image_ct_fc; 1612 return bfi_image_ct2;
1602 } else if (pdev->device == BFA_PCI_DEVICE_ID_CT) { 1613 } else if (bfa_asic_id_ct(pdev->device)) {
1603 if (bfi_image_ct_cna_size == 0) 1614 if (bfi_image_ct_size == 0)
1604 bfad_read_firmware(pdev, &bfi_image_ct_cna, 1615 bfad_read_firmware(pdev, &bfi_image_ct,
1605 &bfi_image_ct_cna_size, BFAD_FW_FILE_CT_CNA); 1616 &bfi_image_ct_size, BFAD_FW_FILE_CT);
1606 return bfi_image_ct_cna; 1617 return bfi_image_ct;
1607 } else { 1618 } else {
1608 if (bfi_image_cb_fc_size == 0) 1619 if (bfi_image_cb_size == 0)
1609 bfad_read_firmware(pdev, &bfi_image_cb_fc, 1620 bfad_read_firmware(pdev, &bfi_image_cb,
1610 &bfi_image_cb_fc_size, BFAD_FW_FILE_CB_FC); 1621 &bfi_image_cb_size, BFAD_FW_FILE_CB);
1611 return bfi_image_cb_fc; 1622 return bfi_image_cb;
1612 } 1623 }
1613} 1624}
1614 1625
1615static void 1626static void
1616bfad_free_fwimg(void) 1627bfad_free_fwimg(void)
1617{ 1628{
1618 if (bfi_image_ct_fc_size && bfi_image_ct_fc) 1629 if (bfi_image_ct2_size && bfi_image_ct2)
1619 vfree(bfi_image_ct_fc); 1630 vfree(bfi_image_ct2);
1620 if (bfi_image_ct_cna_size && bfi_image_ct_cna) 1631 if (bfi_image_ct_size && bfi_image_ct)
1621 vfree(bfi_image_ct_cna); 1632 vfree(bfi_image_ct);
1622 if (bfi_image_cb_fc_size && bfi_image_cb_fc) 1633 if (bfi_image_cb_size && bfi_image_cb)
1623 vfree(bfi_image_cb_fc); 1634 vfree(bfi_image_cb);
1624} 1635}
1625 1636
1626module_init(bfad_init); 1637module_init(bfad_init);
diff --git a/drivers/scsi/bfa/bfad_drv.h b/drivers/scsi/bfa/bfad_drv.h
index 7f9ea90254cd..4af1b02e2dbb 100644
--- a/drivers/scsi/bfa/bfad_drv.h
+++ b/drivers/scsi/bfa/bfad_drv.h
@@ -189,6 +189,7 @@ struct bfad_s {
189 struct bfa_pcidev_s hal_pcidev; 189 struct bfa_pcidev_s hal_pcidev;
190 struct bfa_ioc_pci_attr_s pci_attr; 190 struct bfa_ioc_pci_attr_s pci_attr;
191 void __iomem *pci_bar0_kva; 191 void __iomem *pci_bar0_kva;
192 void __iomem *pci_bar2_kva;
192 struct completion comp; 193 struct completion comp;
193 struct completion suspend; 194 struct completion suspend;
194 struct completion disable_comp; 195 struct completion disable_comp;
diff --git a/drivers/scsi/bfa/bfad_im.c b/drivers/scsi/bfa/bfad_im.c
index c2b36179e8e8..d6d89fbfa65d 100644
--- a/drivers/scsi/bfa/bfad_im.c
+++ b/drivers/scsi/bfa/bfad_im.c
@@ -182,7 +182,7 @@ bfad_im_info(struct Scsi_Host *shost)
182 bfa_get_adapter_model(bfa, model); 182 bfa_get_adapter_model(bfa, model);
183 183
184 memset(bfa_buf, 0, sizeof(bfa_buf)); 184 memset(bfa_buf, 0, sizeof(bfa_buf));
185 if (ioc->ctdev && !ioc->fcmode) 185 if (bfa_ioc_is_cna(ioc))
186 snprintf(bfa_buf, sizeof(bfa_buf), 186 snprintf(bfa_buf, sizeof(bfa_buf),
187 "Brocade FCOE Adapter, " "model: %s hwpath: %s driver: %s", 187 "Brocade FCOE Adapter, " "model: %s hwpath: %s driver: %s",
188 model, bfad->pci_name, BFAD_DRIVER_VERSION); 188 model, bfad->pci_name, BFAD_DRIVER_VERSION);
diff --git a/drivers/scsi/bfa/bfi.h b/drivers/scsi/bfa/bfi.h
index 5b69d07af99c..391796710c8f 100644
--- a/drivers/scsi/bfa/bfi.h
+++ b/drivers/scsi/bfa/bfi.h
@@ -28,12 +28,6 @@
28 */ 28 */
29#define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */ 29#define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */
30#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32)) 30#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
31enum {
32 BFI_IMAGE_CB_FC,
33 BFI_IMAGE_CT_FC,
34 BFI_IMAGE_CT_CNA,
35 BFI_IMAGE_MAX,
36};
37 31
38/* 32/*
39 * Msg header common to all msgs 33 * Msg header common to all msgs
@@ -193,23 +187,28 @@ enum bfi_mclass {
193#define BFI_IOC_MAX_CQS_ASIC 8 187#define BFI_IOC_MAX_CQS_ASIC 8
194#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */ 188#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
195 189
196#define BFI_BOOT_TYPE_OFF 8
197#define BFI_BOOT_LOADER_OFF 12
198
199#define BFI_BOOT_TYPE_NORMAL 0
200#define BFI_BOOT_TYPE_FLASH 1
201#define BFI_BOOT_TYPE_MEMTEST 2
202
203#define BFI_BOOT_LOADER_OS 0
204#define BFI_BOOT_LOADER_BIOS 1
205#define BFI_BOOT_LOADER_UEFI 2
206
207/* 190/*
208 *---------------------------------------------------------------------- 191 *----------------------------------------------------------------------
209 * IOC 192 * IOC
210 *---------------------------------------------------------------------- 193 *----------------------------------------------------------------------
211 */ 194 */
212 195
196/*
197 * Different asic generations
198 */
199enum bfi_asic_gen {
200 BFI_ASIC_GEN_CB = 1, /* crossbow 8G FC */
201 BFI_ASIC_GEN_CT = 2, /* catapult 8G FC or 10G CNA */
202 BFI_ASIC_GEN_CT2 = 3, /* catapult-2 16G FC or 10G CNA */
203};
204
205enum bfi_asic_mode {
206 BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */
207 BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */
208 BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
209 BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
210};
211
213enum bfi_ioc_h2i_msgs { 212enum bfi_ioc_h2i_msgs {
214 BFI_IOC_H2I_ENABLE_REQ = 1, 213 BFI_IOC_H2I_ENABLE_REQ = 1,
215 BFI_IOC_H2I_DISABLE_REQ = 2, 214 BFI_IOC_H2I_DISABLE_REQ = 2,
@@ -290,14 +289,35 @@ struct bfi_ioc_getattr_reply_s {
290#define BFI_IOC_FW_SIGNATURE (0xbfadbfad) 289#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
291#define BFI_IOC_MD5SUM_SZ 4 290#define BFI_IOC_MD5SUM_SZ 4
292struct bfi_ioc_image_hdr_s { 291struct bfi_ioc_image_hdr_s {
293 u32 signature; /* constant signature */ 292 u32 signature; /* constant signature */
294 u32 rsvd_a; 293 u8 asic_gen; /* asic generation */
295 u32 exec; /* exec vector */ 294 u8 asic_mode;
296 u32 param; /* parameters */ 295 u8 port0_mode; /* device mode for port 0 */
296 u8 port1_mode; /* device mode for port 1 */
297 u32 exec; /* exec vector */
298 u32 bootenv; /* fimware boot env */
297 u32 rsvd_b[4]; 299 u32 rsvd_b[4];
298 u32 md5sum[BFI_IOC_MD5SUM_SZ]; 300 u32 md5sum[BFI_IOC_MD5SUM_SZ];
299}; 301};
300 302
303#define BFI_FWBOOT_DEVMODE_OFF 4
304#define BFI_FWBOOT_TYPE_OFF 8
305#define BFI_FWBOOT_ENV_OFF 12
306#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
307 (((u32)(__asic_gen)) << 24 | \
308 ((u32)(__asic_mode)) << 16 | \
309 ((u32)(__p0_mode)) << 8 | \
310 ((u32)(__p1_mode)))
311
312#define BFI_FWBOOT_TYPE_NORMAL 0
313#define BFI_FWBOOT_TYPE_MEMTEST 1
314#define BFI_FWBOOT_ENV_OS 0
315
316enum bfi_port_mode {
317 BFI_PORT_MODE_FC = 1,
318 BFI_PORT_MODE_ETH = 2,
319};
320
301/* 321/*
302 * BFI_IOC_I2H_READY_EVENT message 322 * BFI_IOC_I2H_READY_EVENT message
303 */ 323 */
diff --git a/drivers/scsi/bfa/bfi_cbreg.h b/drivers/scsi/bfa/bfi_cbreg.h
deleted file mode 100644
index 39ad42b66b5b..000000000000
--- a/drivers/scsi/bfa/bfi_cbreg.h
+++ /dev/null
@@ -1,305 +0,0 @@
1
2/*
3 * bfi_cbreg.h crossbow host block register definitions
4 *
5 * !!! Do not edit. Auto generated. !!!
6 */
7
8#ifndef __BFI_CBREG_H__
9#define __BFI_CBREG_H__
10
11
12#define HOSTFN0_INT_STATUS 0x00014000
13#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
14#define __HOSTFN0_INT_STATUS_LVL_SH 20
15#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
16#define __HOSTFN0_INT_STATUS_P 0x000fffff
17#define HOSTFN0_INT_MSK 0x00014004
18#define HOST_PAGE_NUM_FN0 0x00014008
19#define __HOST_PAGE_NUM_FN 0x000001ff
20#define HOSTFN1_INT_STATUS 0x00014100
21#define __HOSTFN1_INT_STAT_LVL_MK 0x00f00000
22#define __HOSTFN1_INT_STAT_LVL_SH 20
23#define __HOSTFN1_INT_STAT_LVL(_v) ((_v) << __HOSTFN1_INT_STAT_LVL_SH)
24#define __HOSTFN1_INT_STAT_P 0x000fffff
25#define HOSTFN1_INT_MSK 0x00014104
26#define HOST_PAGE_NUM_FN1 0x00014108
27#define APP_PLL_400_CTL_REG 0x00014204
28#define __P_400_PLL_LOCK 0x80000000
29#define __APP_PLL_400_SRAM_USE_100MHZ 0x00100000
30#define __APP_PLL_400_RESET_TIMER_MK 0x000e0000
31#define __APP_PLL_400_RESET_TIMER_SH 17
32#define __APP_PLL_400_RESET_TIMER(_v) ((_v) << __APP_PLL_400_RESET_TIMER_SH)
33#define __APP_PLL_400_LOGIC_SOFT_RESET 0x00010000
34#define __APP_PLL_400_CNTLMT0_1_MK 0x0000c000
35#define __APP_PLL_400_CNTLMT0_1_SH 14
36#define __APP_PLL_400_CNTLMT0_1(_v) ((_v) << __APP_PLL_400_CNTLMT0_1_SH)
37#define __APP_PLL_400_JITLMT0_1_MK 0x00003000
38#define __APP_PLL_400_JITLMT0_1_SH 12
39#define __APP_PLL_400_JITLMT0_1(_v) ((_v) << __APP_PLL_400_JITLMT0_1_SH)
40#define __APP_PLL_400_HREF 0x00000800
41#define __APP_PLL_400_HDIV 0x00000400
42#define __APP_PLL_400_P0_1_MK 0x00000300
43#define __APP_PLL_400_P0_1_SH 8
44#define __APP_PLL_400_P0_1(_v) ((_v) << __APP_PLL_400_P0_1_SH)
45#define __APP_PLL_400_Z0_2_MK 0x000000e0
46#define __APP_PLL_400_Z0_2_SH 5
47#define __APP_PLL_400_Z0_2(_v) ((_v) << __APP_PLL_400_Z0_2_SH)
48#define __APP_PLL_400_RSEL200500 0x00000010
49#define __APP_PLL_400_ENARST 0x00000008
50#define __APP_PLL_400_BYPASS 0x00000004
51#define __APP_PLL_400_LRESETN 0x00000002
52#define __APP_PLL_400_ENABLE 0x00000001
53#define APP_PLL_212_CTL_REG 0x00014208
54#define __P_212_PLL_LOCK 0x80000000
55#define __APP_PLL_212_RESET_TIMER_MK 0x000e0000
56#define __APP_PLL_212_RESET_TIMER_SH 17
57#define __APP_PLL_212_RESET_TIMER(_v) ((_v) << __APP_PLL_212_RESET_TIMER_SH)
58#define __APP_PLL_212_LOGIC_SOFT_RESET 0x00010000
59#define __APP_PLL_212_CNTLMT0_1_MK 0x0000c000
60#define __APP_PLL_212_CNTLMT0_1_SH 14
61#define __APP_PLL_212_CNTLMT0_1(_v) ((_v) << __APP_PLL_212_CNTLMT0_1_SH)
62#define __APP_PLL_212_JITLMT0_1_MK 0x00003000
63#define __APP_PLL_212_JITLMT0_1_SH 12
64#define __APP_PLL_212_JITLMT0_1(_v) ((_v) << __APP_PLL_212_JITLMT0_1_SH)
65#define __APP_PLL_212_HREF 0x00000800
66#define __APP_PLL_212_HDIV 0x00000400
67#define __APP_PLL_212_P0_1_MK 0x00000300
68#define __APP_PLL_212_P0_1_SH 8
69#define __APP_PLL_212_P0_1(_v) ((_v) << __APP_PLL_212_P0_1_SH)
70#define __APP_PLL_212_Z0_2_MK 0x000000e0
71#define __APP_PLL_212_Z0_2_SH 5
72#define __APP_PLL_212_Z0_2(_v) ((_v) << __APP_PLL_212_Z0_2_SH)
73#define __APP_PLL_212_RSEL200500 0x00000010
74#define __APP_PLL_212_ENARST 0x00000008
75#define __APP_PLL_212_BYPASS 0x00000004
76#define __APP_PLL_212_LRESETN 0x00000002
77#define __APP_PLL_212_ENABLE 0x00000001
78#define HOST_SEM0_REG 0x00014230
79#define __HOST_SEMAPHORE 0x00000001
80#define HOST_SEM1_REG 0x00014234
81#define HOST_SEM2_REG 0x00014238
82#define HOST_SEM3_REG 0x0001423c
83#define HOST_SEM0_INFO_REG 0x00014240
84#define HOST_SEM1_INFO_REG 0x00014244
85#define HOST_SEM2_INFO_REG 0x00014248
86#define HOST_SEM3_INFO_REG 0x0001424c
87#define HOSTFN0_LPU0_CMD_STAT 0x00019000
88#define __HOSTFN0_LPU0_MBOX_INFO_MK 0xfffffffe
89#define __HOSTFN0_LPU0_MBOX_INFO_SH 1
90#define __HOSTFN0_LPU0_MBOX_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX_INFO_SH)
91#define __HOSTFN0_LPU0_MBOX_CMD_STATUS 0x00000001
92#define LPU0_HOSTFN0_CMD_STAT 0x00019008
93#define __LPU0_HOSTFN0_MBOX_INFO_MK 0xfffffffe
94#define __LPU0_HOSTFN0_MBOX_INFO_SH 1
95#define __LPU0_HOSTFN0_MBOX_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX_INFO_SH)
96#define __LPU0_HOSTFN0_MBOX_CMD_STATUS 0x00000001
97#define HOSTFN1_LPU1_CMD_STAT 0x00019014
98#define __HOSTFN1_LPU1_MBOX_INFO_MK 0xfffffffe
99#define __HOSTFN1_LPU1_MBOX_INFO_SH 1
100#define __HOSTFN1_LPU1_MBOX_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX_INFO_SH)
101#define __HOSTFN1_LPU1_MBOX_CMD_STATUS 0x00000001
102#define LPU1_HOSTFN1_CMD_STAT 0x0001901c
103#define __LPU1_HOSTFN1_MBOX_INFO_MK 0xfffffffe
104#define __LPU1_HOSTFN1_MBOX_INFO_SH 1
105#define __LPU1_HOSTFN1_MBOX_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX_INFO_SH)
106#define __LPU1_HOSTFN1_MBOX_CMD_STATUS 0x00000001
107#define CPE_Q0_DEPTH 0x00010014
108#define CPE_Q0_PI 0x0001001c
109#define CPE_Q0_CI 0x00010020
110#define CPE_Q1_DEPTH 0x00010034
111#define CPE_Q1_PI 0x0001003c
112#define CPE_Q1_CI 0x00010040
113#define CPE_Q2_DEPTH 0x00010054
114#define CPE_Q2_PI 0x0001005c
115#define CPE_Q2_CI 0x00010060
116#define CPE_Q3_DEPTH 0x00010074
117#define CPE_Q3_PI 0x0001007c
118#define CPE_Q3_CI 0x00010080
119#define CPE_Q4_DEPTH 0x00010094
120#define CPE_Q4_PI 0x0001009c
121#define CPE_Q4_CI 0x000100a0
122#define CPE_Q5_DEPTH 0x000100b4
123#define CPE_Q5_PI 0x000100bc
124#define CPE_Q5_CI 0x000100c0
125#define CPE_Q6_DEPTH 0x000100d4
126#define CPE_Q6_PI 0x000100dc
127#define CPE_Q6_CI 0x000100e0
128#define CPE_Q7_DEPTH 0x000100f4
129#define CPE_Q7_PI 0x000100fc
130#define CPE_Q7_CI 0x00010100
131#define RME_Q0_DEPTH 0x00011014
132#define RME_Q0_PI 0x0001101c
133#define RME_Q0_CI 0x00011020
134#define RME_Q1_DEPTH 0x00011034
135#define RME_Q1_PI 0x0001103c
136#define RME_Q1_CI 0x00011040
137#define RME_Q2_DEPTH 0x00011054
138#define RME_Q2_PI 0x0001105c
139#define RME_Q2_CI 0x00011060
140#define RME_Q3_DEPTH 0x00011074
141#define RME_Q3_PI 0x0001107c
142#define RME_Q3_CI 0x00011080
143#define RME_Q4_DEPTH 0x00011094
144#define RME_Q4_PI 0x0001109c
145#define RME_Q4_CI 0x000110a0
146#define RME_Q5_DEPTH 0x000110b4
147#define RME_Q5_PI 0x000110bc
148#define RME_Q5_CI 0x000110c0
149#define RME_Q6_DEPTH 0x000110d4
150#define RME_Q6_PI 0x000110dc
151#define RME_Q6_CI 0x000110e0
152#define RME_Q7_DEPTH 0x000110f4
153#define RME_Q7_PI 0x000110fc
154#define RME_Q7_CI 0x00011100
155#define PSS_CTL_REG 0x00018800
156#define __PSS_I2C_CLK_DIV_MK 0x00030000
157#define __PSS_I2C_CLK_DIV_SH 16
158#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
159#define __PSS_LMEM_INIT_DONE 0x00001000
160#define __PSS_LMEM_RESET 0x00000200
161#define __PSS_LMEM_INIT_EN 0x00000100
162#define __PSS_LPU1_RESET 0x00000002
163#define __PSS_LPU0_RESET 0x00000001
164#define PSS_ERR_STATUS_REG 0x00018810
165#define __PSS_LMEM1_CORR_ERR 0x00000800
166#define __PSS_LMEM0_CORR_ERR 0x00000400
167#define __PSS_LMEM1_UNCORR_ERR 0x00000200
168#define __PSS_LMEM0_UNCORR_ERR 0x00000100
169#define __PSS_BAL_PERR 0x00000080
170#define __PSS_DIP_IF_ERR 0x00000040
171#define __PSS_IOH_IF_ERR 0x00000020
172#define __PSS_TDS_IF_ERR 0x00000010
173#define __PSS_RDS_IF_ERR 0x00000008
174#define __PSS_SGM_IF_ERR 0x00000004
175#define __PSS_LPU1_RAM_ERR 0x00000002
176#define __PSS_LPU0_RAM_ERR 0x00000001
177#define ERR_SET_REG 0x00018818
178#define __PSS_ERR_STATUS_SET 0x00000fff
179
180
181/*
182 * These definitions are either in error/missing in spec. Its auto-generated
183 * from hard coded values in regparse.pl.
184 */
185#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
186#define __EMPHPOST_AT_4G_SH_FIX 0x00000002
187#define __EMPHPRE_AT_4G_FIX 0x00000003
188#define __SFP_TXRATE_EN_FIX 0x00000100
189#define __SFP_RXRATE_EN_FIX 0x00000080
190
191
192/*
193 * These register definitions are auto-generated from hard coded values
194 * in regparse.pl.
195 */
196#define HOSTFN0_LPU_MBOX0_0 0x00019200
197#define HOSTFN1_LPU_MBOX0_8 0x00019260
198#define LPU_HOSTFN0_MBOX0_0 0x00019280
199#define LPU_HOSTFN1_MBOX0_8 0x000192e0
200
201
202/*
203 * These register mapping definitions are auto-generated from mapping tables
204 * in regparse.pl.
205 */
206#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
207#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
208#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
209#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
210#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
211#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG
212
213#define CPE_Q_DEPTH(__n) \
214 (CPE_Q0_DEPTH + (__n) * (CPE_Q1_DEPTH - CPE_Q0_DEPTH))
215#define CPE_Q_PI(__n) \
216 (CPE_Q0_PI + (__n) * (CPE_Q1_PI - CPE_Q0_PI))
217#define CPE_Q_CI(__n) \
218 (CPE_Q0_CI + (__n) * (CPE_Q1_CI - CPE_Q0_CI))
219#define RME_Q_DEPTH(__n) \
220 (RME_Q0_DEPTH + (__n) * (RME_Q1_DEPTH - RME_Q0_DEPTH))
221#define RME_Q_PI(__n) \
222 (RME_Q0_PI + (__n) * (RME_Q1_PI - RME_Q0_PI))
223#define RME_Q_CI(__n) \
224 (RME_Q0_CI + (__n) * (RME_Q1_CI - RME_Q0_CI))
225
226#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
227#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
228#define CPE_Q_MASK(__q) ((__q) & 0x3)
229#define RME_Q_MASK(__q) ((__q) & 0x3)
230
231
232/*
233 * PCI MSI-X vector defines
234 */
235enum {
236 BFA_MSIX_CPE_Q0 = 0,
237 BFA_MSIX_CPE_Q1 = 1,
238 BFA_MSIX_CPE_Q2 = 2,
239 BFA_MSIX_CPE_Q3 = 3,
240 BFA_MSIX_CPE_Q4 = 4,
241 BFA_MSIX_CPE_Q5 = 5,
242 BFA_MSIX_CPE_Q6 = 6,
243 BFA_MSIX_CPE_Q7 = 7,
244 BFA_MSIX_RME_Q0 = 8,
245 BFA_MSIX_RME_Q1 = 9,
246 BFA_MSIX_RME_Q2 = 10,
247 BFA_MSIX_RME_Q3 = 11,
248 BFA_MSIX_RME_Q4 = 12,
249 BFA_MSIX_RME_Q5 = 13,
250 BFA_MSIX_RME_Q6 = 14,
251 BFA_MSIX_RME_Q7 = 15,
252 BFA_MSIX_ERR_EMC = 16,
253 BFA_MSIX_ERR_LPU0 = 17,
254 BFA_MSIX_ERR_LPU1 = 18,
255 BFA_MSIX_ERR_PSS = 19,
256 BFA_MSIX_MBOX_LPU0 = 20,
257 BFA_MSIX_MBOX_LPU1 = 21,
258 BFA_MSIX_CB_MAX = 22,
259};
260
261/*
262 * And corresponding host interrupt status bit field defines
263 */
264#define __HFN_INT_CPE_Q0 0x00000001U
265#define __HFN_INT_CPE_Q1 0x00000002U
266#define __HFN_INT_CPE_Q2 0x00000004U
267#define __HFN_INT_CPE_Q3 0x00000008U
268#define __HFN_INT_CPE_Q4 0x00000010U
269#define __HFN_INT_CPE_Q5 0x00000020U
270#define __HFN_INT_CPE_Q6 0x00000040U
271#define __HFN_INT_CPE_Q7 0x00000080U
272#define __HFN_INT_RME_Q0 0x00000100U
273#define __HFN_INT_RME_Q1 0x00000200U
274#define __HFN_INT_RME_Q2 0x00000400U
275#define __HFN_INT_RME_Q3 0x00000800U
276#define __HFN_INT_RME_Q4 0x00001000U
277#define __HFN_INT_RME_Q5 0x00002000U
278#define __HFN_INT_RME_Q6 0x00004000U
279#define __HFN_INT_RME_Q7 0x00008000U
280#define __HFN_INT_ERR_EMC 0x00010000U
281#define __HFN_INT_ERR_LPU0 0x00020000U
282#define __HFN_INT_ERR_LPU1 0x00040000U
283#define __HFN_INT_ERR_PSS 0x00080000U
284#define __HFN_INT_MBOX_LPU0 0x00100000U
285#define __HFN_INT_MBOX_LPU1 0x00200000U
286#define __HFN_INT_MBOX1_LPU0 0x00400000U
287#define __HFN_INT_MBOX1_LPU1 0x00800000U
288#define __HFN_INT_CPE_MASK 0x000000ffU
289#define __HFN_INT_RME_MASK 0x0000ff00U
290
291
292/*
293 * crossbow memory map.
294 */
295#define PSS_SMEM_PAGE_START 0x8000
296#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
297#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
298
299/*
300 * End of crossbow memory map
301 */
302
303
304#endif /* __BFI_CBREG_H__ */
305
diff --git a/drivers/scsi/bfa/bfi_ctreg.h b/drivers/scsi/bfa/bfi_ctreg.h
deleted file mode 100644
index fc4ce4a5a183..000000000000
--- a/drivers/scsi/bfa/bfi_ctreg.h
+++ /dev/null
@@ -1,636 +0,0 @@
1
2/*
3 * bfi_ctreg.h catapult host block register definitions
4 *
5 * !!! Do not edit. Auto generated. !!!
6 */
7
8#ifndef __BFI_CTREG_H__
9#define __BFI_CTREG_H__
10
11
12#define HOSTFN0_LPU_MBOX0_0 0x00019200
13#define HOSTFN1_LPU_MBOX0_8 0x00019260
14#define LPU_HOSTFN0_MBOX0_0 0x00019280
15#define LPU_HOSTFN1_MBOX0_8 0x000192e0
16#define HOSTFN2_LPU_MBOX0_0 0x00019400
17#define HOSTFN3_LPU_MBOX0_8 0x00019460
18#define LPU_HOSTFN2_MBOX0_0 0x00019480
19#define LPU_HOSTFN3_MBOX0_8 0x000194e0
20#define HOSTFN0_INT_STATUS 0x00014000
21#define __HOSTFN0_HALT_OCCURRED 0x01000000
22#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
23#define __HOSTFN0_INT_STATUS_LVL_SH 20
24#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
25#define __HOSTFN0_INT_STATUS_P_MK 0x000f0000
26#define __HOSTFN0_INT_STATUS_P_SH 16
27#define __HOSTFN0_INT_STATUS_P(_v) ((_v) << __HOSTFN0_INT_STATUS_P_SH)
28#define __HOSTFN0_INT_STATUS_F 0x0000ffff
29#define HOSTFN0_INT_MSK 0x00014004
30#define HOST_PAGE_NUM_FN0 0x00014008
31#define __HOST_PAGE_NUM_FN 0x000001ff
32#define HOST_MSIX_ERR_INDEX_FN0 0x0001400c
33#define __MSIX_ERR_INDEX_FN 0x000001ff
34#define HOSTFN1_INT_STATUS 0x00014100
35#define __HOSTFN1_HALT_OCCURRED 0x01000000
36#define __HOSTFN1_INT_STATUS_LVL_MK 0x00f00000
37#define __HOSTFN1_INT_STATUS_LVL_SH 20
38#define __HOSTFN1_INT_STATUS_LVL(_v) ((_v) << __HOSTFN1_INT_STATUS_LVL_SH)
39#define __HOSTFN1_INT_STATUS_P_MK 0x000f0000
40#define __HOSTFN1_INT_STATUS_P_SH 16
41#define __HOSTFN1_INT_STATUS_P(_v) ((_v) << __HOSTFN1_INT_STATUS_P_SH)
42#define __HOSTFN1_INT_STATUS_F 0x0000ffff
43#define HOSTFN1_INT_MSK 0x00014104
44#define HOST_PAGE_NUM_FN1 0x00014108
45#define HOST_MSIX_ERR_INDEX_FN1 0x0001410c
46#define APP_PLL_425_CTL_REG 0x00014204
47#define __P_425_PLL_LOCK 0x80000000
48#define __APP_PLL_425_SRAM_USE_100MHZ 0x00100000
49#define __APP_PLL_425_RESET_TIMER_MK 0x000e0000
50#define __APP_PLL_425_RESET_TIMER_SH 17
51#define __APP_PLL_425_RESET_TIMER(_v) ((_v) << __APP_PLL_425_RESET_TIMER_SH)
52#define __APP_PLL_425_LOGIC_SOFT_RESET 0x00010000
53#define __APP_PLL_425_CNTLMT0_1_MK 0x0000c000
54#define __APP_PLL_425_CNTLMT0_1_SH 14
55#define __APP_PLL_425_CNTLMT0_1(_v) ((_v) << __APP_PLL_425_CNTLMT0_1_SH)
56#define __APP_PLL_425_JITLMT0_1_MK 0x00003000
57#define __APP_PLL_425_JITLMT0_1_SH 12
58#define __APP_PLL_425_JITLMT0_1(_v) ((_v) << __APP_PLL_425_JITLMT0_1_SH)
59#define __APP_PLL_425_HREF 0x00000800
60#define __APP_PLL_425_HDIV 0x00000400
61#define __APP_PLL_425_P0_1_MK 0x00000300
62#define __APP_PLL_425_P0_1_SH 8
63#define __APP_PLL_425_P0_1(_v) ((_v) << __APP_PLL_425_P0_1_SH)
64#define __APP_PLL_425_Z0_2_MK 0x000000e0
65#define __APP_PLL_425_Z0_2_SH 5
66#define __APP_PLL_425_Z0_2(_v) ((_v) << __APP_PLL_425_Z0_2_SH)
67#define __APP_PLL_425_RSEL200500 0x00000010
68#define __APP_PLL_425_ENARST 0x00000008
69#define __APP_PLL_425_BYPASS 0x00000004
70#define __APP_PLL_425_LRESETN 0x00000002
71#define __APP_PLL_425_ENABLE 0x00000001
72#define APP_PLL_312_CTL_REG 0x00014208
73#define __P_312_PLL_LOCK 0x80000000
74#define __ENABLE_MAC_AHB_1 0x00800000
75#define __ENABLE_MAC_AHB_0 0x00400000
76#define __ENABLE_MAC_1 0x00200000
77#define __ENABLE_MAC_0 0x00100000
78#define __APP_PLL_312_RESET_TIMER_MK 0x000e0000
79#define __APP_PLL_312_RESET_TIMER_SH 17
80#define __APP_PLL_312_RESET_TIMER(_v) ((_v) << __APP_PLL_312_RESET_TIMER_SH)
81#define __APP_PLL_312_LOGIC_SOFT_RESET 0x00010000
82#define __APP_PLL_312_CNTLMT0_1_MK 0x0000c000
83#define __APP_PLL_312_CNTLMT0_1_SH 14
84#define __APP_PLL_312_CNTLMT0_1(_v) ((_v) << __APP_PLL_312_CNTLMT0_1_SH)
85#define __APP_PLL_312_JITLMT0_1_MK 0x00003000
86#define __APP_PLL_312_JITLMT0_1_SH 12
87#define __APP_PLL_312_JITLMT0_1(_v) ((_v) << __APP_PLL_312_JITLMT0_1_SH)
88#define __APP_PLL_312_HREF 0x00000800
89#define __APP_PLL_312_HDIV 0x00000400
90#define __APP_PLL_312_P0_1_MK 0x00000300
91#define __APP_PLL_312_P0_1_SH 8
92#define __APP_PLL_312_P0_1(_v) ((_v) << __APP_PLL_312_P0_1_SH)
93#define __APP_PLL_312_Z0_2_MK 0x000000e0
94#define __APP_PLL_312_Z0_2_SH 5
95#define __APP_PLL_312_Z0_2(_v) ((_v) << __APP_PLL_312_Z0_2_SH)
96#define __APP_PLL_312_RSEL200500 0x00000010
97#define __APP_PLL_312_ENARST 0x00000008
98#define __APP_PLL_312_BYPASS 0x00000004
99#define __APP_PLL_312_LRESETN 0x00000002
100#define __APP_PLL_312_ENABLE 0x00000001
101#define MBIST_CTL_REG 0x00014220
102#define __EDRAM_BISTR_START 0x00000004
103#define __MBIST_RESET 0x00000002
104#define __MBIST_START 0x00000001
105#define MBIST_STAT_REG 0x00014224
106#define __EDRAM_BISTR_STATUS 0x00000008
107#define __EDRAM_BISTR_DONE 0x00000004
108#define __MEM_BIT_STATUS 0x00000002
109#define __MBIST_DONE 0x00000001
110#define HOST_SEM0_REG 0x00014230
111#define __HOST_SEMAPHORE 0x00000001
112#define HOST_SEM1_REG 0x00014234
113#define HOST_SEM2_REG 0x00014238
114#define HOST_SEM3_REG 0x0001423c
115#define HOST_SEM0_INFO_REG 0x00014240
116#define HOST_SEM1_INFO_REG 0x00014244
117#define HOST_SEM2_INFO_REG 0x00014248
118#define HOST_SEM3_INFO_REG 0x0001424c
119#define ETH_MAC_SER_REG 0x00014288
120#define __APP_EMS_CKBUFAMPIN 0x00000020
121#define __APP_EMS_REFCLKSEL 0x00000010
122#define __APP_EMS_CMLCKSEL 0x00000008
123#define __APP_EMS_REFCKBUFEN2 0x00000004
124#define __APP_EMS_REFCKBUFEN1 0x00000002
125#define __APP_EMS_CHANNEL_SEL 0x00000001
126#define HOSTFN2_INT_STATUS 0x00014300
127#define __HOSTFN2_HALT_OCCURRED 0x01000000
128#define __HOSTFN2_INT_STATUS_LVL_MK 0x00f00000
129#define __HOSTFN2_INT_STATUS_LVL_SH 20
130#define __HOSTFN2_INT_STATUS_LVL(_v) ((_v) << __HOSTFN2_INT_STATUS_LVL_SH)
131#define __HOSTFN2_INT_STATUS_P_MK 0x000f0000
132#define __HOSTFN2_INT_STATUS_P_SH 16
133#define __HOSTFN2_INT_STATUS_P(_v) ((_v) << __HOSTFN2_INT_STATUS_P_SH)
134#define __HOSTFN2_INT_STATUS_F 0x0000ffff
135#define HOSTFN2_INT_MSK 0x00014304
136#define HOST_PAGE_NUM_FN2 0x00014308
137#define HOST_MSIX_ERR_INDEX_FN2 0x0001430c
138#define HOSTFN3_INT_STATUS 0x00014400
139#define __HALT_OCCURRED 0x01000000
140#define __HOSTFN3_INT_STATUS_LVL_MK 0x00f00000
141#define __HOSTFN3_INT_STATUS_LVL_SH 20
142#define __HOSTFN3_INT_STATUS_LVL(_v) ((_v) << __HOSTFN3_INT_STATUS_LVL_SH)
143#define __HOSTFN3_INT_STATUS_P_MK 0x000f0000
144#define __HOSTFN3_INT_STATUS_P_SH 16
145#define __HOSTFN3_INT_STATUS_P(_v) ((_v) << __HOSTFN3_INT_STATUS_P_SH)
146#define __HOSTFN3_INT_STATUS_F 0x0000ffff
147#define HOSTFN3_INT_MSK 0x00014404
148#define HOST_PAGE_NUM_FN3 0x00014408
149#define HOST_MSIX_ERR_INDEX_FN3 0x0001440c
150#define FNC_ID_REG 0x00014600
151#define __FUNCTION_NUMBER 0x00000007
152#define FNC_PERS_REG 0x00014604
153#define __F3_FUNCTION_ACTIVE 0x80000000
154#define __F3_FUNCTION_MODE 0x40000000
155#define __F3_PORT_MAP_MK 0x30000000
156#define __F3_PORT_MAP_SH 28
157#define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH)
158#define __F3_VM_MODE 0x08000000
159#define __F3_INTX_STATUS_MK 0x07000000
160#define __F3_INTX_STATUS_SH 24
161#define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH)
162#define __F2_FUNCTION_ACTIVE 0x00800000
163#define __F2_FUNCTION_MODE 0x00400000
164#define __F2_PORT_MAP_MK 0x00300000
165#define __F2_PORT_MAP_SH 20
166#define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH)
167#define __F2_VM_MODE 0x00080000
168#define __F2_INTX_STATUS_MK 0x00070000
169#define __F2_INTX_STATUS_SH 16
170#define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH)
171#define __F1_FUNCTION_ACTIVE 0x00008000
172#define __F1_FUNCTION_MODE 0x00004000
173#define __F1_PORT_MAP_MK 0x00003000
174#define __F1_PORT_MAP_SH 12
175#define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH)
176#define __F1_VM_MODE 0x00000800
177#define __F1_INTX_STATUS_MK 0x00000700
178#define __F1_INTX_STATUS_SH 8
179#define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH)
180#define __F0_FUNCTION_ACTIVE 0x00000080
181#define __F0_FUNCTION_MODE 0x00000040
182#define __F0_PORT_MAP_MK 0x00000030
183#define __F0_PORT_MAP_SH 4
184#define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH)
185#define __F0_VM_MODE 0x00000008
186#define __F0_INTX_STATUS 0x00000007
187enum {
188 __F0_INTX_STATUS_MSIX = 0x0,
189 __F0_INTX_STATUS_INTA = 0x1,
190 __F0_INTX_STATUS_INTB = 0x2,
191 __F0_INTX_STATUS_INTC = 0x3,
192 __F0_INTX_STATUS_INTD = 0x4,
193};
194#define OP_MODE 0x0001460c
195#define __APP_ETH_CLK_LOWSPEED 0x00000004
196#define __GLOBAL_CORECLK_HALFSPEED 0x00000002
197#define __GLOBAL_FCOE_MODE 0x00000001
198#define HOST_SEM4_REG 0x00014610
199#define HOST_SEM5_REG 0x00014614
200#define HOST_SEM6_REG 0x00014618
201#define HOST_SEM7_REG 0x0001461c
202#define HOST_SEM4_INFO_REG 0x00014620
203#define HOST_SEM5_INFO_REG 0x00014624
204#define HOST_SEM6_INFO_REG 0x00014628
205#define HOST_SEM7_INFO_REG 0x0001462c
206#define HOSTFN0_LPU0_MBOX0_CMD_STAT 0x00019000
207#define __HOSTFN0_LPU0_MBOX0_INFO_MK 0xfffffffe
208#define __HOSTFN0_LPU0_MBOX0_INFO_SH 1
209#define __HOSTFN0_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX0_INFO_SH)
210#define __HOSTFN0_LPU0_MBOX0_CMD_STATUS 0x00000001
211#define HOSTFN0_LPU1_MBOX0_CMD_STAT 0x00019004
212#define __HOSTFN0_LPU1_MBOX0_INFO_MK 0xfffffffe
213#define __HOSTFN0_LPU1_MBOX0_INFO_SH 1
214#define __HOSTFN0_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU1_MBOX0_INFO_SH)
215#define __HOSTFN0_LPU1_MBOX0_CMD_STATUS 0x00000001
216#define LPU0_HOSTFN0_MBOX0_CMD_STAT 0x00019008
217#define __LPU0_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
218#define __LPU0_HOSTFN0_MBOX0_INFO_SH 1
219#define __LPU0_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX0_INFO_SH)
220#define __LPU0_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
221#define LPU1_HOSTFN0_MBOX0_CMD_STAT 0x0001900c
222#define __LPU1_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
223#define __LPU1_HOSTFN0_MBOX0_INFO_SH 1
224#define __LPU1_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN0_MBOX0_INFO_SH)
225#define __LPU1_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
226#define HOSTFN1_LPU0_MBOX0_CMD_STAT 0x00019010
227#define __HOSTFN1_LPU0_MBOX0_INFO_MK 0xfffffffe
228#define __HOSTFN1_LPU0_MBOX0_INFO_SH 1
229#define __HOSTFN1_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU0_MBOX0_INFO_SH)
230#define __HOSTFN1_LPU0_MBOX0_CMD_STATUS 0x00000001
231#define HOSTFN1_LPU1_MBOX0_CMD_STAT 0x00019014
232#define __HOSTFN1_LPU1_MBOX0_INFO_MK 0xfffffffe
233#define __HOSTFN1_LPU1_MBOX0_INFO_SH 1
234#define __HOSTFN1_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX0_INFO_SH)
235#define __HOSTFN1_LPU1_MBOX0_CMD_STATUS 0x00000001
236#define LPU0_HOSTFN1_MBOX0_CMD_STAT 0x00019018
237#define __LPU0_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
238#define __LPU0_HOSTFN1_MBOX0_INFO_SH 1
239#define __LPU0_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN1_MBOX0_INFO_SH)
240#define __LPU0_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
241#define LPU1_HOSTFN1_MBOX0_CMD_STAT 0x0001901c
242#define __LPU1_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
243#define __LPU1_HOSTFN1_MBOX0_INFO_SH 1
244#define __LPU1_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX0_INFO_SH)
245#define __LPU1_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
246#define HOSTFN2_LPU0_MBOX0_CMD_STAT 0x00019150
247#define __HOSTFN2_LPU0_MBOX0_INFO_MK 0xfffffffe
248#define __HOSTFN2_LPU0_MBOX0_INFO_SH 1
249#define __HOSTFN2_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU0_MBOX0_INFO_SH)
250#define __HOSTFN2_LPU0_MBOX0_CMD_STATUS 0x00000001
251#define HOSTFN2_LPU1_MBOX0_CMD_STAT 0x00019154
252#define __HOSTFN2_LPU1_MBOX0_INFO_MK 0xfffffffe
253#define __HOSTFN2_LPU1_MBOX0_INFO_SH 1
254#define __HOSTFN2_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU1_MBOX0_INFO_SH)
255#define __HOSTFN2_LPU1_MBOX0BOX0_CMD_STATUS 0x00000001
256#define LPU0_HOSTFN2_MBOX0_CMD_STAT 0x00019158
257#define __LPU0_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
258#define __LPU0_HOSTFN2_MBOX0_INFO_SH 1
259#define __LPU0_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN2_MBOX0_INFO_SH)
260#define __LPU0_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
261#define LPU1_HOSTFN2_MBOX0_CMD_STAT 0x0001915c
262#define __LPU1_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
263#define __LPU1_HOSTFN2_MBOX0_INFO_SH 1
264#define __LPU1_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN2_MBOX0_INFO_SH)
265#define __LPU1_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
266#define HOSTFN3_LPU0_MBOX0_CMD_STAT 0x00019160
267#define __HOSTFN3_LPU0_MBOX0_INFO_MK 0xfffffffe
268#define __HOSTFN3_LPU0_MBOX0_INFO_SH 1
269#define __HOSTFN3_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU0_MBOX0_INFO_SH)
270#define __HOSTFN3_LPU0_MBOX0_CMD_STATUS 0x00000001
271#define HOSTFN3_LPU1_MBOX0_CMD_STAT 0x00019164
272#define __HOSTFN3_LPU1_MBOX0_INFO_MK 0xfffffffe
273#define __HOSTFN3_LPU1_MBOX0_INFO_SH 1
274#define __HOSTFN3_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU1_MBOX0_INFO_SH)
275#define __HOSTFN3_LPU1_MBOX0_CMD_STATUS 0x00000001
276#define LPU0_HOSTFN3_MBOX0_CMD_STAT 0x00019168
277#define __LPU0_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
278#define __LPU0_HOSTFN3_MBOX0_INFO_SH 1
279#define __LPU0_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN3_MBOX0_INFO_SH)
280#define __LPU0_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
281#define LPU1_HOSTFN3_MBOX0_CMD_STAT 0x0001916c
282#define __LPU1_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
283#define __LPU1_HOSTFN3_MBOX0_INFO_SH 1
284#define __LPU1_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN3_MBOX0_INFO_SH)
285#define __LPU1_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
286#define FW_INIT_HALT_P0 0x000191ac
287#define __FW_INIT_HALT_P 0x00000001
288#define FW_INIT_HALT_P1 0x000191bc
289#define CPE_PI_PTR_Q0 0x00038000
290#define __CPE_PI_UNUSED_MK 0xffff0000
291#define __CPE_PI_UNUSED_SH 16
292#define __CPE_PI_UNUSED(_v) ((_v) << __CPE_PI_UNUSED_SH)
293#define __CPE_PI_PTR 0x0000ffff
294#define CPE_PI_PTR_Q1 0x00038040
295#define CPE_CI_PTR_Q0 0x00038004
296#define __CPE_CI_UNUSED_MK 0xffff0000
297#define __CPE_CI_UNUSED_SH 16
298#define __CPE_CI_UNUSED(_v) ((_v) << __CPE_CI_UNUSED_SH)
299#define __CPE_CI_PTR 0x0000ffff
300#define CPE_CI_PTR_Q1 0x00038044
301#define CPE_DEPTH_Q0 0x00038008
302#define __CPE_DEPTH_UNUSED_MK 0xf8000000
303#define __CPE_DEPTH_UNUSED_SH 27
304#define __CPE_DEPTH_UNUSED(_v) ((_v) << __CPE_DEPTH_UNUSED_SH)
305#define __CPE_MSIX_VEC_INDEX_MK 0x07ff0000
306#define __CPE_MSIX_VEC_INDEX_SH 16
307#define __CPE_MSIX_VEC_INDEX(_v) ((_v) << __CPE_MSIX_VEC_INDEX_SH)
308#define __CPE_DEPTH 0x0000ffff
309#define CPE_DEPTH_Q1 0x00038048
310#define CPE_QCTRL_Q0 0x0003800c
311#define __CPE_CTRL_UNUSED30_MK 0xfc000000
312#define __CPE_CTRL_UNUSED30_SH 26
313#define __CPE_CTRL_UNUSED30(_v) ((_v) << __CPE_CTRL_UNUSED30_SH)
314#define __CPE_FUNC_INT_CTRL_MK 0x03000000
315#define __CPE_FUNC_INT_CTRL_SH 24
316#define __CPE_FUNC_INT_CTRL(_v) ((_v) << __CPE_FUNC_INT_CTRL_SH)
317enum {
318 __CPE_FUNC_INT_CTRL_DISABLE = 0x0,
319 __CPE_FUNC_INT_CTRL_F2NF = 0x1,
320 __CPE_FUNC_INT_CTRL_3QUART = 0x2,
321 __CPE_FUNC_INT_CTRL_HALF = 0x3,
322};
323#define __CPE_CTRL_UNUSED20_MK 0x00f00000
324#define __CPE_CTRL_UNUSED20_SH 20
325#define __CPE_CTRL_UNUSED20(_v) ((_v) << __CPE_CTRL_UNUSED20_SH)
326#define __CPE_SCI_TH_MK 0x000f0000
327#define __CPE_SCI_TH_SH 16
328#define __CPE_SCI_TH(_v) ((_v) << __CPE_SCI_TH_SH)
329#define __CPE_CTRL_UNUSED10_MK 0x0000c000
330#define __CPE_CTRL_UNUSED10_SH 14
331#define __CPE_CTRL_UNUSED10(_v) ((_v) << __CPE_CTRL_UNUSED10_SH)
332#define __CPE_ACK_PENDING 0x00002000
333#define __CPE_CTRL_UNUSED40_MK 0x00001c00
334#define __CPE_CTRL_UNUSED40_SH 10
335#define __CPE_CTRL_UNUSED40(_v) ((_v) << __CPE_CTRL_UNUSED40_SH)
336#define __CPE_PCIEID_MK 0x00000300
337#define __CPE_PCIEID_SH 8
338#define __CPE_PCIEID(_v) ((_v) << __CPE_PCIEID_SH)
339#define __CPE_CTRL_UNUSED00_MK 0x000000fe
340#define __CPE_CTRL_UNUSED00_SH 1
341#define __CPE_CTRL_UNUSED00(_v) ((_v) << __CPE_CTRL_UNUSED00_SH)
342#define __CPE_ESIZE 0x00000001
343#define CPE_QCTRL_Q1 0x0003804c
344#define __CPE_CTRL_UNUSED31_MK 0xfc000000
345#define __CPE_CTRL_UNUSED31_SH 26
346#define __CPE_CTRL_UNUSED31(_v) ((_v) << __CPE_CTRL_UNUSED31_SH)
347#define __CPE_CTRL_UNUSED21_MK 0x00f00000
348#define __CPE_CTRL_UNUSED21_SH 20
349#define __CPE_CTRL_UNUSED21(_v) ((_v) << __CPE_CTRL_UNUSED21_SH)
350#define __CPE_CTRL_UNUSED11_MK 0x0000c000
351#define __CPE_CTRL_UNUSED11_SH 14
352#define __CPE_CTRL_UNUSED11(_v) ((_v) << __CPE_CTRL_UNUSED11_SH)
353#define __CPE_CTRL_UNUSED41_MK 0x00001c00
354#define __CPE_CTRL_UNUSED41_SH 10
355#define __CPE_CTRL_UNUSED41(_v) ((_v) << __CPE_CTRL_UNUSED41_SH)
356#define __CPE_CTRL_UNUSED01_MK 0x000000fe
357#define __CPE_CTRL_UNUSED01_SH 1
358#define __CPE_CTRL_UNUSED01(_v) ((_v) << __CPE_CTRL_UNUSED01_SH)
359#define RME_PI_PTR_Q0 0x00038020
360#define __LATENCY_TIME_STAMP_MK 0xffff0000
361#define __LATENCY_TIME_STAMP_SH 16
362#define __LATENCY_TIME_STAMP(_v) ((_v) << __LATENCY_TIME_STAMP_SH)
363#define __RME_PI_PTR 0x0000ffff
364#define RME_PI_PTR_Q1 0x00038060
365#define RME_CI_PTR_Q0 0x00038024
366#define __DELAY_TIME_STAMP_MK 0xffff0000
367#define __DELAY_TIME_STAMP_SH 16
368#define __DELAY_TIME_STAMP(_v) ((_v) << __DELAY_TIME_STAMP_SH)
369#define __RME_CI_PTR 0x0000ffff
370#define RME_CI_PTR_Q1 0x00038064
371#define RME_DEPTH_Q0 0x00038028
372#define __RME_DEPTH_UNUSED_MK 0xf8000000
373#define __RME_DEPTH_UNUSED_SH 27
374#define __RME_DEPTH_UNUSED(_v) ((_v) << __RME_DEPTH_UNUSED_SH)
375#define __RME_MSIX_VEC_INDEX_MK 0x07ff0000
376#define __RME_MSIX_VEC_INDEX_SH 16
377#define __RME_MSIX_VEC_INDEX(_v) ((_v) << __RME_MSIX_VEC_INDEX_SH)
378#define __RME_DEPTH 0x0000ffff
379#define RME_DEPTH_Q1 0x00038068
380#define RME_QCTRL_Q0 0x0003802c
381#define __RME_INT_LATENCY_TIMER_MK 0xff000000
382#define __RME_INT_LATENCY_TIMER_SH 24
383#define __RME_INT_LATENCY_TIMER(_v) ((_v) << __RME_INT_LATENCY_TIMER_SH)
384#define __RME_INT_DELAY_TIMER_MK 0x00ff0000
385#define __RME_INT_DELAY_TIMER_SH 16
386#define __RME_INT_DELAY_TIMER(_v) ((_v) << __RME_INT_DELAY_TIMER_SH)
387#define __RME_INT_DELAY_DISABLE 0x00008000
388#define __RME_DLY_DELAY_DISABLE 0x00004000
389#define __RME_ACK_PENDING 0x00002000
390#define __RME_FULL_INTERRUPT_DISABLE 0x00001000
391#define __RME_CTRL_UNUSED10_MK 0x00000c00
392#define __RME_CTRL_UNUSED10_SH 10
393#define __RME_CTRL_UNUSED10(_v) ((_v) << __RME_CTRL_UNUSED10_SH)
394#define __RME_PCIEID_MK 0x00000300
395#define __RME_PCIEID_SH 8
396#define __RME_PCIEID(_v) ((_v) << __RME_PCIEID_SH)
397#define __RME_CTRL_UNUSED00_MK 0x000000fe
398#define __RME_CTRL_UNUSED00_SH 1
399#define __RME_CTRL_UNUSED00(_v) ((_v) << __RME_CTRL_UNUSED00_SH)
400#define __RME_ESIZE 0x00000001
401#define RME_QCTRL_Q1 0x0003806c
402#define __RME_CTRL_UNUSED11_MK 0x00000c00
403#define __RME_CTRL_UNUSED11_SH 10
404#define __RME_CTRL_UNUSED11(_v) ((_v) << __RME_CTRL_UNUSED11_SH)
405#define __RME_CTRL_UNUSED01_MK 0x000000fe
406#define __RME_CTRL_UNUSED01_SH 1
407#define __RME_CTRL_UNUSED01(_v) ((_v) << __RME_CTRL_UNUSED01_SH)
408#define PSS_CTL_REG 0x00018800
409#define __PSS_I2C_CLK_DIV_MK 0x007f0000
410#define __PSS_I2C_CLK_DIV_SH 16
411#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
412#define __PSS_LMEM_INIT_DONE 0x00001000
413#define __PSS_LMEM_RESET 0x00000200
414#define __PSS_LMEM_INIT_EN 0x00000100
415#define __PSS_LPU1_RESET 0x00000002
416#define __PSS_LPU0_RESET 0x00000001
417#define PSS_ERR_STATUS_REG 0x00018810
418#define __PSS_LPU1_TCM_READ_ERR 0x00200000
419#define __PSS_LPU0_TCM_READ_ERR 0x00100000
420#define __PSS_LMEM5_CORR_ERR 0x00080000
421#define __PSS_LMEM4_CORR_ERR 0x00040000
422#define __PSS_LMEM3_CORR_ERR 0x00020000
423#define __PSS_LMEM2_CORR_ERR 0x00010000
424#define __PSS_LMEM1_CORR_ERR 0x00008000
425#define __PSS_LMEM0_CORR_ERR 0x00004000
426#define __PSS_LMEM5_UNCORR_ERR 0x00002000
427#define __PSS_LMEM4_UNCORR_ERR 0x00001000
428#define __PSS_LMEM3_UNCORR_ERR 0x00000800
429#define __PSS_LMEM2_UNCORR_ERR 0x00000400
430#define __PSS_LMEM1_UNCORR_ERR 0x00000200
431#define __PSS_LMEM0_UNCORR_ERR 0x00000100
432#define __PSS_BAL_PERR 0x00000080
433#define __PSS_DIP_IF_ERR 0x00000040
434#define __PSS_IOH_IF_ERR 0x00000020
435#define __PSS_TDS_IF_ERR 0x00000010
436#define __PSS_RDS_IF_ERR 0x00000008
437#define __PSS_SGM_IF_ERR 0x00000004
438#define __PSS_LPU1_RAM_ERR 0x00000002
439#define __PSS_LPU0_RAM_ERR 0x00000001
440#define ERR_SET_REG 0x00018818
441#define __PSS_ERR_STATUS_SET 0x003fffff
442#define PMM_1T_RESET_REG_P0 0x0002381c
443#define __PMM_1T_RESET_P 0x00000001
444#define PMM_1T_RESET_REG_P1 0x00023c1c
445#define HQM_QSET0_RXQ_DRBL_P0 0x00038000
446#define __RXQ0_ADD_VECTORS_P 0x80000000
447#define __RXQ0_STOP_P 0x40000000
448#define __RXQ0_PRD_PTR_P 0x0000ffff
449#define HQM_QSET1_RXQ_DRBL_P0 0x00038080
450#define __RXQ1_ADD_VECTORS_P 0x80000000
451#define __RXQ1_STOP_P 0x40000000
452#define __RXQ1_PRD_PTR_P 0x0000ffff
453#define HQM_QSET0_RXQ_DRBL_P1 0x0003c000
454#define HQM_QSET1_RXQ_DRBL_P1 0x0003c080
455#define HQM_QSET0_TXQ_DRBL_P0 0x00038020
456#define __TXQ0_ADD_VECTORS_P 0x80000000
457#define __TXQ0_STOP_P 0x40000000
458#define __TXQ0_PRD_PTR_P 0x0000ffff
459#define HQM_QSET1_TXQ_DRBL_P0 0x000380a0
460#define __TXQ1_ADD_VECTORS_P 0x80000000
461#define __TXQ1_STOP_P 0x40000000
462#define __TXQ1_PRD_PTR_P 0x0000ffff
463#define HQM_QSET0_TXQ_DRBL_P1 0x0003c020
464#define HQM_QSET1_TXQ_DRBL_P1 0x0003c0a0
465#define HQM_QSET0_IB_DRBL_1_P0 0x00038040
466#define __IB1_0_ACK_P 0x80000000
467#define __IB1_0_DISABLE_P 0x40000000
468#define __IB1_0_COALESCING_CFG_P_MK 0x00ff0000
469#define __IB1_0_COALESCING_CFG_P_SH 16
470#define __IB1_0_COALESCING_CFG_P(_v) ((_v) << __IB1_0_COALESCING_CFG_P_SH)
471#define __IB1_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
472#define HQM_QSET1_IB_DRBL_1_P0 0x000380c0
473#define __IB1_1_ACK_P 0x80000000
474#define __IB1_1_DISABLE_P 0x40000000
475#define __IB1_1_COALESCING_CFG_P_MK 0x00ff0000
476#define __IB1_1_COALESCING_CFG_P_SH 16
477#define __IB1_1_COALESCING_CFG_P(_v) ((_v) << __IB1_1_COALESCING_CFG_P_SH)
478#define __IB1_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
479#define HQM_QSET0_IB_DRBL_1_P1 0x0003c040
480#define HQM_QSET1_IB_DRBL_1_P1 0x0003c0c0
481#define HQM_QSET0_IB_DRBL_2_P0 0x00038060
482#define __IB2_0_ACK_P 0x80000000
483#define __IB2_0_DISABLE_P 0x40000000
484#define __IB2_0_COALESCING_CFG_P_MK 0x00ff0000
485#define __IB2_0_COALESCING_CFG_P_SH 16
486#define __IB2_0_COALESCING_CFG_P(_v) ((_v) << __IB2_0_COALESCING_CFG_P_SH)
487#define __IB2_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
488#define HQM_QSET1_IB_DRBL_2_P0 0x000380e0
489#define __IB2_1_ACK_P 0x80000000
490#define __IB2_1_DISABLE_P 0x40000000
491#define __IB2_1_COALESCING_CFG_P_MK 0x00ff0000
492#define __IB2_1_COALESCING_CFG_P_SH 16
493#define __IB2_1_COALESCING_CFG_P(_v) ((_v) << __IB2_1_COALESCING_CFG_P_SH)
494#define __IB2_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
495#define HQM_QSET0_IB_DRBL_2_P1 0x0003c060
496#define HQM_QSET1_IB_DRBL_2_P1 0x0003c0e0
497
498
499/*
500 * These definitions are either in error/missing in spec. Its auto-generated
501 * from hard coded values in regparse.pl.
502 */
503#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
504#define __EMPHPOST_AT_4G_SH_FIX 0x00000002
505#define __EMPHPRE_AT_4G_FIX 0x00000003
506#define __SFP_TXRATE_EN_FIX 0x00000100
507#define __SFP_RXRATE_EN_FIX 0x00000080
508
509
510/*
511 * These register definitions are auto-generated from hard coded values
512 * in regparse.pl.
513 */
514
515
516/*
517 * These register mapping definitions are auto-generated from mapping tables
518 * in regparse.pl.
519 */
520#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
521#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
522#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
523#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
524#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
525#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG
526
527#define CPE_DEPTH_Q(__n) \
528 (CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
529#define CPE_QCTRL_Q(__n) \
530 (CPE_QCTRL_Q0 + (__n) * (CPE_QCTRL_Q1 - CPE_QCTRL_Q0))
531#define CPE_PI_PTR_Q(__n) \
532 (CPE_PI_PTR_Q0 + (__n) * (CPE_PI_PTR_Q1 - CPE_PI_PTR_Q0))
533#define CPE_CI_PTR_Q(__n) \
534 (CPE_CI_PTR_Q0 + (__n) * (CPE_CI_PTR_Q1 - CPE_CI_PTR_Q0))
535#define RME_DEPTH_Q(__n) \
536 (RME_DEPTH_Q0 + (__n) * (RME_DEPTH_Q1 - RME_DEPTH_Q0))
537#define RME_QCTRL_Q(__n) \
538 (RME_QCTRL_Q0 + (__n) * (RME_QCTRL_Q1 - RME_QCTRL_Q0))
539#define RME_PI_PTR_Q(__n) \
540 (RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
541#define RME_CI_PTR_Q(__n) \
542 (RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
543#define HQM_QSET_RXQ_DRBL_P0(__n) \
544 (HQM_QSET0_RXQ_DRBL_P0 + (__n) * \
545 (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
546#define HQM_QSET_TXQ_DRBL_P0(__n) \
547 (HQM_QSET0_TXQ_DRBL_P0 + (__n) * \
548 (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
549#define HQM_QSET_IB_DRBL_1_P0(__n) \
550 (HQM_QSET0_IB_DRBL_1_P0 + (__n) * \
551 (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
552#define HQM_QSET_IB_DRBL_2_P0(__n) \
553 (HQM_QSET0_IB_DRBL_2_P0 + (__n) * \
554 (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
555#define HQM_QSET_RXQ_DRBL_P1(__n) \
556 (HQM_QSET0_RXQ_DRBL_P1 + (__n) * \
557 (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
558#define HQM_QSET_TXQ_DRBL_P1(__n) \
559 (HQM_QSET0_TXQ_DRBL_P1 + (__n) * \
560 (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
561#define HQM_QSET_IB_DRBL_1_P1(__n) \
562 (HQM_QSET0_IB_DRBL_1_P1 + (__n) * \
563 (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
564#define HQM_QSET_IB_DRBL_2_P1(__n) \
565 (HQM_QSET0_IB_DRBL_2_P1 + (__n) * \
566 (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
567
568#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
569#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
570#define CPE_Q_MASK(__q) ((__q) & 0x3)
571#define RME_Q_MASK(__q) ((__q) & 0x3)
572
573
574/*
575 * PCI MSI-X vector defines
576 */
577enum {
578 BFA_MSIX_CPE_Q0 = 0,
579 BFA_MSIX_CPE_Q1 = 1,
580 BFA_MSIX_CPE_Q2 = 2,
581 BFA_MSIX_CPE_Q3 = 3,
582 BFA_MSIX_RME_Q0 = 4,
583 BFA_MSIX_RME_Q1 = 5,
584 BFA_MSIX_RME_Q2 = 6,
585 BFA_MSIX_RME_Q3 = 7,
586 BFA_MSIX_LPU_ERR = 8,
587 BFA_MSIX_CT_MAX = 9,
588};
589
590/*
591 * And corresponding host interrupt status bit field defines
592 */
593#define __HFN_INT_CPE_Q0 0x00000001U
594#define __HFN_INT_CPE_Q1 0x00000002U
595#define __HFN_INT_CPE_Q2 0x00000004U
596#define __HFN_INT_CPE_Q3 0x00000008U
597#define __HFN_INT_CPE_Q4 0x00000010U
598#define __HFN_INT_CPE_Q5 0x00000020U
599#define __HFN_INT_CPE_Q6 0x00000040U
600#define __HFN_INT_CPE_Q7 0x00000080U
601#define __HFN_INT_RME_Q0 0x00000100U
602#define __HFN_INT_RME_Q1 0x00000200U
603#define __HFN_INT_RME_Q2 0x00000400U
604#define __HFN_INT_RME_Q3 0x00000800U
605#define __HFN_INT_RME_Q4 0x00001000U
606#define __HFN_INT_RME_Q5 0x00002000U
607#define __HFN_INT_RME_Q6 0x00004000U
608#define __HFN_INT_RME_Q7 0x00008000U
609#define __HFN_INT_ERR_EMC 0x00010000U
610#define __HFN_INT_ERR_LPU0 0x00020000U
611#define __HFN_INT_ERR_LPU1 0x00040000U
612#define __HFN_INT_ERR_PSS 0x00080000U
613#define __HFN_INT_MBOX_LPU0 0x00100000U
614#define __HFN_INT_MBOX_LPU1 0x00200000U
615#define __HFN_INT_MBOX1_LPU0 0x00400000U
616#define __HFN_INT_MBOX1_LPU1 0x00800000U
617#define __HFN_INT_LL_HALT 0x01000000U
618#define __HFN_INT_CPE_MASK 0x000000ffU
619#define __HFN_INT_RME_MASK 0x0000ff00U
620
621
622/*
623 * catapult memory map.
624 */
625#define LL_PGN_HQM0 0x0096
626#define LL_PGN_HQM1 0x0097
627#define PSS_SMEM_PAGE_START 0x8000
628#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
629#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
630
631/*
632 * End of catapult memory map
633 */
634
635
636#endif /* __BFI_CTREG_H__ */
diff --git a/drivers/scsi/bfa/bfi_ms.h b/drivers/scsi/bfa/bfi_ms.h
index dd2aad9ac6fe..c9c8e8da5bd1 100644
--- a/drivers/scsi/bfa/bfi_ms.h
+++ b/drivers/scsi/bfa/bfi_ms.h
@@ -68,11 +68,24 @@ struct bfi_iocfc_bootwwns {
68 u8 rsvd[7]; 68 u8 rsvd[7];
69}; 69};
70 70
71/**
72 * Queue configuration response from firmware
73 */
74struct bfi_iocfc_qreg_s {
75 u32 cpe_q_ci_off[BFI_IOC_MAX_CQS];
76 u32 cpe_q_pi_off[BFI_IOC_MAX_CQS];
77 u32 cpe_qctl_off[BFI_IOC_MAX_CQS];
78 u32 rme_q_ci_off[BFI_IOC_MAX_CQS];
79 u32 rme_q_pi_off[BFI_IOC_MAX_CQS];
80 u32 rme_qctl_off[BFI_IOC_MAX_CQS];
81};
82
71struct bfi_iocfc_cfgrsp_s { 83struct bfi_iocfc_cfgrsp_s {
72 struct bfa_iocfc_fwcfg_s fwcfg; 84 struct bfa_iocfc_fwcfg_s fwcfg;
73 struct bfa_iocfc_intr_attr_s intr_attr; 85 struct bfa_iocfc_intr_attr_s intr_attr;
74 struct bfi_iocfc_bootwwns bootwwns; 86 struct bfi_iocfc_bootwwns bootwwns;
75 struct bfi_pbc_s pbc_cfg; 87 struct bfi_pbc_s pbc_cfg;
88 struct bfi_iocfc_qreg_s qreg;
76}; 89};
77 90
78/* 91/*
@@ -772,4 +785,27 @@ struct bfi_tskim_rsp_s {
772 785
773#pragma pack() 786#pragma pack()
774 787
788/*
789 * Crossbow PCI MSI-X vector defines
790 */
791enum {
792 BFI_MSIX_CPE_QMIN_CB = 0,
793 BFI_MSIX_CPE_QMAX_CB = 7,
794 BFI_MSIX_RME_QMIN_CB = 8,
795 BFI_MSIX_RME_QMAX_CB = 15,
796 BFI_MSIX_CB_MAX = 22,
797};
798
799/*
800 * Catapult FC PCI MSI-X vector defines
801 */
802enum {
803 BFI_MSIX_LPU_ERR_CT = 0,
804 BFI_MSIX_CPE_QMIN_CT = 1,
805 BFI_MSIX_CPE_QMAX_CT = 4,
806 BFI_MSIX_RME_QMIN_CT = 5,
807 BFI_MSIX_RME_QMAX_CT = 8,
808 BFI_MSIX_CT_MAX = 9,
809};
810
775#endif /* __BFI_MS_H__ */ 811#endif /* __BFI_MS_H__ */
diff --git a/drivers/scsi/bfa/bfi_reg.h b/drivers/scsi/bfa/bfi_reg.h
new file mode 100644
index 000000000000..0e8b68540018
--- /dev/null
+++ b/drivers/scsi/bfa/bfi_reg.h
@@ -0,0 +1,428 @@
1/*
2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
3 * All rights reserved
4 * www.brocade.com
5 *
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
18/*
19 * bfi_reg.h ASIC register defines for all Brocade adapter ASICs
20 */
21
22#ifndef __BFI_REG_H__
23#define __BFI_REG_H__
24
25#define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
26#define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
27#define HOSTFN2_INT_STATUS 0x00014300 /* ct */
28#define HOSTFN3_INT_STATUS 0x00014400 /* ct */
29#define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
30#define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
31#define HOSTFN2_INT_MSK 0x00014304 /* ct */
32#define HOSTFN3_INT_MSK 0x00014404 /* ct */
33
34#define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
35#define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
36#define HOST_PAGE_NUM_FN2 0x00014308 /* ct */
37#define HOST_PAGE_NUM_FN3 0x00014408 /* ct */
38
39#define APP_PLL_LCLK_CTL_REG 0x00014204 /* cb/ct */
40#define __P_LCLK_PLL_LOCK 0x80000000
41#define __APP_PLL_LCLK_SRAM_USE_100MHZ 0x00100000
42#define __APP_PLL_LCLK_RESET_TIMER_MK 0x000e0000
43#define __APP_PLL_LCLK_RESET_TIMER_SH 17
44#define __APP_PLL_LCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)
45#define __APP_PLL_LCLK_LOGIC_SOFT_RESET 0x00010000
46#define __APP_PLL_LCLK_CNTLMT0_1_MK 0x0000c000
47#define __APP_PLL_LCLK_CNTLMT0_1_SH 14
48#define __APP_PLL_LCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)
49#define __APP_PLL_LCLK_JITLMT0_1_MK 0x00003000
50#define __APP_PLL_LCLK_JITLMT0_1_SH 12
51#define __APP_PLL_LCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)
52#define __APP_PLL_LCLK_HREF 0x00000800
53#define __APP_PLL_LCLK_HDIV 0x00000400
54#define __APP_PLL_LCLK_P0_1_MK 0x00000300
55#define __APP_PLL_LCLK_P0_1_SH 8
56#define __APP_PLL_LCLK_P0_1(_v) ((_v) << __APP_PLL_LCLK_P0_1_SH)
57#define __APP_PLL_LCLK_Z0_2_MK 0x000000e0
58#define __APP_PLL_LCLK_Z0_2_SH 5
59#define __APP_PLL_LCLK_Z0_2(_v) ((_v) << __APP_PLL_LCLK_Z0_2_SH)
60#define __APP_PLL_LCLK_RSEL200500 0x00000010
61#define __APP_PLL_LCLK_ENARST 0x00000008
62#define __APP_PLL_LCLK_BYPASS 0x00000004
63#define __APP_PLL_LCLK_LRESETN 0x00000002
64#define __APP_PLL_LCLK_ENABLE 0x00000001
65#define APP_PLL_SCLK_CTL_REG 0x00014208 /* cb/ct */
66#define __P_SCLK_PLL_LOCK 0x80000000
67#define __APP_PLL_SCLK_RESET_TIMER_MK 0x000e0000
68#define __APP_PLL_SCLK_RESET_TIMER_SH 17
69#define __APP_PLL_SCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)
70#define __APP_PLL_SCLK_LOGIC_SOFT_RESET 0x00010000
71#define __APP_PLL_SCLK_CNTLMT0_1_MK 0x0000c000
72#define __APP_PLL_SCLK_CNTLMT0_1_SH 14
73#define __APP_PLL_SCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)
74#define __APP_PLL_SCLK_JITLMT0_1_MK 0x00003000
75#define __APP_PLL_SCLK_JITLMT0_1_SH 12
76#define __APP_PLL_SCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)
77#define __APP_PLL_SCLK_HREF 0x00000800
78#define __APP_PLL_SCLK_HDIV 0x00000400
79#define __APP_PLL_SCLK_P0_1_MK 0x00000300
80#define __APP_PLL_SCLK_P0_1_SH 8
81#define __APP_PLL_SCLK_P0_1(_v) ((_v) << __APP_PLL_SCLK_P0_1_SH)
82#define __APP_PLL_SCLK_Z0_2_MK 0x000000e0
83#define __APP_PLL_SCLK_Z0_2_SH 5
84#define __APP_PLL_SCLK_Z0_2(_v) ((_v) << __APP_PLL_SCLK_Z0_2_SH)
85#define __APP_PLL_SCLK_RSEL200500 0x00000010
86#define __APP_PLL_SCLK_ENARST 0x00000008
87#define __APP_PLL_SCLK_BYPASS 0x00000004
88#define __APP_PLL_SCLK_LRESETN 0x00000002
89#define __APP_PLL_SCLK_ENABLE 0x00000001
90#define __ENABLE_MAC_AHB_1 0x00800000 /* ct */
91#define __ENABLE_MAC_AHB_0 0x00400000 /* ct */
92#define __ENABLE_MAC_1 0x00200000 /* ct */
93#define __ENABLE_MAC_0 0x00100000 /* ct */
94
95#define HOST_SEM0_REG 0x00014230 /* cb/ct */
96#define HOST_SEM1_REG 0x00014234 /* cb/ct */
97#define HOST_SEM2_REG 0x00014238 /* cb/ct */
98#define HOST_SEM3_REG 0x0001423c /* cb/ct */
99#define HOST_SEM4_REG 0x00014610 /* cb/ct */
100#define HOST_SEM5_REG 0x00014614 /* cb/ct */
101#define HOST_SEM6_REG 0x00014618 /* cb/ct */
102#define HOST_SEM7_REG 0x0001461c /* cb/ct */
103#define HOST_SEM0_INFO_REG 0x00014240 /* cb/ct */
104#define HOST_SEM1_INFO_REG 0x00014244 /* cb/ct */
105#define HOST_SEM2_INFO_REG 0x00014248 /* cb/ct */
106#define HOST_SEM3_INFO_REG 0x0001424c /* cb/ct */
107#define HOST_SEM4_INFO_REG 0x00014620 /* cb/ct */
108#define HOST_SEM5_INFO_REG 0x00014624 /* cb/ct */
109#define HOST_SEM6_INFO_REG 0x00014628 /* cb/ct */
110#define HOST_SEM7_INFO_REG 0x0001462c /* cb/ct */
111
112#define HOSTFN0_LPU0_CMD_STAT 0x00019000 /* cb/ct */
113#define HOSTFN0_LPU1_CMD_STAT 0x00019004 /* cb/ct */
114#define HOSTFN1_LPU0_CMD_STAT 0x00019010 /* cb/ct */
115#define HOSTFN1_LPU1_CMD_STAT 0x00019014 /* cb/ct */
116#define HOSTFN2_LPU0_CMD_STAT 0x00019150 /* ct */
117#define HOSTFN2_LPU1_CMD_STAT 0x00019154 /* ct */
118#define HOSTFN3_LPU0_CMD_STAT 0x00019160 /* ct */
119#define HOSTFN3_LPU1_CMD_STAT 0x00019164 /* ct */
120#define LPU0_HOSTFN0_CMD_STAT 0x00019008 /* cb/ct */
121#define LPU1_HOSTFN0_CMD_STAT 0x0001900c /* cb/ct */
122#define LPU0_HOSTFN1_CMD_STAT 0x00019018 /* cb/ct */
123#define LPU1_HOSTFN1_CMD_STAT 0x0001901c /* cb/ct */
124#define LPU0_HOSTFN2_CMD_STAT 0x00019158 /* ct */
125#define LPU1_HOSTFN2_CMD_STAT 0x0001915c /* ct */
126#define LPU0_HOSTFN3_CMD_STAT 0x00019168 /* ct */
127#define LPU1_HOSTFN3_CMD_STAT 0x0001916c /* ct */
128
129#define PSS_CTL_REG 0x00018800 /* cb/ct */
130#define __PSS_I2C_CLK_DIV_MK 0x007f0000
131#define __PSS_I2C_CLK_DIV_SH 16
132#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
133#define __PSS_LMEM_INIT_DONE 0x00001000
134#define __PSS_LMEM_RESET 0x00000200
135#define __PSS_LMEM_INIT_EN 0x00000100
136#define __PSS_LPU1_RESET 0x00000002
137#define __PSS_LPU0_RESET 0x00000001
138#define PSS_ERR_STATUS_REG 0x00018810 /* cb/ct */
139#define ERR_SET_REG 0x00018818 /* cb/ct */
140
141#define HOSTFN0_LPU_MBOX0_0 0x00019200 /* cb/ct */
142#define HOSTFN1_LPU_MBOX0_8 0x00019260 /* cb/ct */
143#define LPU_HOSTFN0_MBOX0_0 0x00019280 /* cb/ct */
144#define LPU_HOSTFN1_MBOX0_8 0x000192e0 /* cb/ct */
145#define HOSTFN2_LPU_MBOX0_0 0x00019400 /* ct */
146#define HOSTFN3_LPU_MBOX0_8 0x00019460 /* ct */
147#define LPU_HOSTFN2_MBOX0_0 0x00019480 /* ct */
148#define LPU_HOSTFN3_MBOX0_8 0x000194e0 /* ct */
149
150#define HOST_MSIX_ERR_INDEX_FN0 0x0001400c /* ct */
151#define HOST_MSIX_ERR_INDEX_FN1 0x0001410c /* ct */
152#define HOST_MSIX_ERR_INDEX_FN2 0x0001430c /* ct */
153#define HOST_MSIX_ERR_INDEX_FN3 0x0001440c /* ct */
154
155#define MBIST_CTL_REG 0x00014220 /* ct */
156#define __EDRAM_BISTR_START 0x00000004
157#define MBIST_STAT_REG 0x00014224 /* ct */
158#define ETH_MAC_SER_REG 0x00014288 /* ct */
159#define __APP_EMS_CKBUFAMPIN 0x00000020
160#define __APP_EMS_REFCLKSEL 0x00000010
161#define __APP_EMS_CMLCKSEL 0x00000008
162#define __APP_EMS_REFCKBUFEN2 0x00000004
163#define __APP_EMS_REFCKBUFEN1 0x00000002
164#define __APP_EMS_CHANNEL_SEL 0x00000001
165#define FNC_PERS_REG 0x00014604 /* ct */
166#define __F3_FUNCTION_ACTIVE 0x80000000
167#define __F3_FUNCTION_MODE 0x40000000
168#define __F3_PORT_MAP_MK 0x30000000
169#define __F3_PORT_MAP_SH 28
170#define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH)
171#define __F3_VM_MODE 0x08000000
172#define __F3_INTX_STATUS_MK 0x07000000
173#define __F3_INTX_STATUS_SH 24
174#define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH)
175#define __F2_FUNCTION_ACTIVE 0x00800000
176#define __F2_FUNCTION_MODE 0x00400000
177#define __F2_PORT_MAP_MK 0x00300000
178#define __F2_PORT_MAP_SH 20
179#define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH)
180#define __F2_VM_MODE 0x00080000
181#define __F2_INTX_STATUS_MK 0x00070000
182#define __F2_INTX_STATUS_SH 16
183#define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH)
184#define __F1_FUNCTION_ACTIVE 0x00008000
185#define __F1_FUNCTION_MODE 0x00004000
186#define __F1_PORT_MAP_MK 0x00003000
187#define __F1_PORT_MAP_SH 12
188#define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH)
189#define __F1_VM_MODE 0x00000800
190#define __F1_INTX_STATUS_MK 0x00000700
191#define __F1_INTX_STATUS_SH 8
192#define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH)
193#define __F0_FUNCTION_ACTIVE 0x00000080
194#define __F0_FUNCTION_MODE 0x00000040
195#define __F0_PORT_MAP_MK 0x00000030
196#define __F0_PORT_MAP_SH 4
197#define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH)
198#define __F0_VM_MODE 0x00000008
199#define __F0_INTX_STATUS 0x00000007
200enum {
201 __F0_INTX_STATUS_MSIX = 0x0,
202 __F0_INTX_STATUS_INTA = 0x1,
203 __F0_INTX_STATUS_INTB = 0x2,
204 __F0_INTX_STATUS_INTC = 0x3,
205 __F0_INTX_STATUS_INTD = 0x4,
206};
207
208#define OP_MODE 0x0001460c /* ct */
209#define __APP_ETH_CLK_LOWSPEED 0x00000004
210#define __GLOBAL_CORECLK_HALFSPEED 0x00000002
211#define __GLOBAL_FCOE_MODE 0x00000001
212#define FW_INIT_HALT_P0 0x000191ac /* ct */
213#define __FW_INIT_HALT_P 0x00000001
214#define FW_INIT_HALT_P1 0x000191bc /* ct */
215#define PMM_1T_RESET_REG_P0 0x0002381c /* ct */
216#define __PMM_1T_RESET_P 0x00000001
217#define PMM_1T_RESET_REG_P1 0x00023c1c /* ct */
218
219/**
220 * Catapult-2 specific defines
221 */
222#define CT2_PCI_CPQ_BASE 0x00030000
223#define CT2_PCI_APP_BASE 0x00030100
224#define CT2_PCI_ETH_BASE 0x00030400
225
226/*
227 * APP block registers
228 */
229#define CT2_HOSTFN_INT_STATUS (CT2_PCI_APP_BASE + 0x00)
230#define CT2_HOSTFN_INTR_MASK (CT2_PCI_APP_BASE + 0x04)
231#define CT2_HOSTFN_PERSONALITY0 (CT2_PCI_APP_BASE + 0x08)
232#define __PME_STATUS_ 0x00200000
233#define __PF_VF_BAR_SIZE_MODE__MK 0x00180000
234#define __PF_VF_BAR_SIZE_MODE__SH 19
235#define __PF_VF_BAR_SIZE_MODE_(_v) ((_v) << __PF_VF_BAR_SIZE_MODE__SH)
236#define __FC_LL_PORT_MAP__MK 0x00060000
237#define __FC_LL_PORT_MAP__SH 17
238#define __FC_LL_PORT_MAP_(_v) ((_v) << __FC_LL_PORT_MAP__SH)
239#define __PF_VF_ACTIVE_ 0x00010000
240#define __PF_VF_CFG_RDY_ 0x00008000
241#define __PF_VF_ENABLE_ 0x00004000
242#define __PF_DRIVER_ACTIVE_ 0x00002000
243#define __PF_PME_SEND_ENABLE_ 0x00001000
244#define __PF_EXROM_OFFSET__MK 0x00000ff0
245#define __PF_EXROM_OFFSET__SH 4
246#define __PF_EXROM_OFFSET_(_v) ((_v) << __PF_EXROM_OFFSET__SH)
247#define __FC_LL_MODE_ 0x00000008
248#define __PF_INTX_PIN_ 0x00000007
249#define CT2_HOSTFN_PERSONALITY1 (CT2_PCI_APP_BASE + 0x0C)
250#define __PF_NUM_QUEUES1__MK 0xff000000
251#define __PF_NUM_QUEUES1__SH 24
252#define __PF_NUM_QUEUES1_(_v) ((_v) << __PF_NUM_QUEUES1__SH)
253#define __PF_VF_QUE_OFFSET1__MK 0x00ff0000
254#define __PF_VF_QUE_OFFSET1__SH 16
255#define __PF_VF_QUE_OFFSET1_(_v) ((_v) << __PF_VF_QUE_OFFSET1__SH)
256#define __PF_VF_NUM_QUEUES__MK 0x0000ff00
257#define __PF_VF_NUM_QUEUES__SH 8
258#define __PF_VF_NUM_QUEUES_(_v) ((_v) << __PF_VF_NUM_QUEUES__SH)
259#define __PF_VF_QUE_OFFSET_ 0x000000ff
260#define CT2_HOSTFN_PAGE_NUM (CT2_PCI_APP_BASE + 0x18)
261#define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR (CT2_PCI_APP_BASE + 0x38)
262
263/*
264 * Catapult-2 CPQ block registers
265 */
266#define CT2_HOSTFN_LPU0_MBOX0 (CT2_PCI_CPQ_BASE + 0x00)
267#define CT2_HOSTFN_LPU1_MBOX0 (CT2_PCI_CPQ_BASE + 0x20)
268#define CT2_LPU0_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x40)
269#define CT2_LPU1_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x60)
270#define CT2_HOSTFN_LPU0_CMD_STAT (CT2_PCI_CPQ_BASE + 0x80)
271#define CT2_HOSTFN_LPU1_CMD_STAT (CT2_PCI_CPQ_BASE + 0x84)
272#define CT2_LPU0_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x88)
273#define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c)
274#define CT2_HOST_SEM0_REG 0x000148f0
275#define CT2_HOST_SEM1_REG 0x000148f4
276#define CT2_HOST_SEM2_REG 0x000148f8
277#define CT2_HOST_SEM3_REG 0x000148fc
278#define CT2_HOST_SEM4_REG 0x00014900
279#define CT2_HOST_SEM5_REG 0x00014904
280#define CT2_HOST_SEM6_REG 0x00014908
281#define CT2_HOST_SEM7_REG 0x0001490c
282#define CT2_HOST_SEM0_INFO_REG 0x000148b0
283#define CT2_HOST_SEM1_INFO_REG 0x000148b4
284#define CT2_HOST_SEM2_INFO_REG 0x000148b8
285#define CT2_HOST_SEM3_INFO_REG 0x000148bc
286#define CT2_HOST_SEM4_INFO_REG 0x000148c0
287#define CT2_HOST_SEM5_INFO_REG 0x000148c4
288#define CT2_HOST_SEM6_INFO_REG 0x000148c8
289#define CT2_HOST_SEM7_INFO_REG 0x000148cc
290
291#define CT2_APP_PLL_LCLK_CTL_REG 0x00014808
292#define __APP_LPUCLK_HALFSPEED 0x40000000
293#define __APP_PLL_LCLK_LOAD 0x20000000
294#define __APP_PLL_LCLK_FBCNT_MK 0x1fe00000
295#define __APP_PLL_LCLK_FBCNT_SH 21
296#define __APP_PLL_LCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH)
297enum {
298 __APP_PLL_LCLK_FBCNT_425_MHZ = 6,
299 __APP_PLL_LCLK_FBCNT_468_MHZ = 4,
300};
301#define __APP_PLL_LCLK_EXTFB 0x00000800
302#define __APP_PLL_LCLK_ENOUTS 0x00000400
303#define __APP_PLL_LCLK_RATE 0x00000010
304#define CT2_APP_PLL_SCLK_CTL_REG 0x0001480c
305#define __P_SCLK_PLL_LOCK 0x80000000
306#define __APP_PLL_SCLK_REFCLK_SEL 0x40000000
307#define __APP_PLL_SCLK_CLK_DIV2 0x20000000
308#define __APP_PLL_SCLK_LOAD 0x10000000
309#define __APP_PLL_SCLK_FBCNT_MK 0x0ff00000
310#define __APP_PLL_SCLK_FBCNT_SH 20
311#define __APP_PLL_SCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH)
312enum {
313 __APP_PLL_SCLK_FBCNT_NORM = 6,
314 __APP_PLL_SCLK_FBCNT_10G_FC = 10,
315};
316#define __APP_PLL_SCLK_EXTFB 0x00000800
317#define __APP_PLL_SCLK_ENOUTS 0x00000400
318#define __APP_PLL_SCLK_RATE 0x00000010
319#define CT2_PCIE_MISC_REG 0x00014804
320#define __ETH_CLK_ENABLE_PORT1 0x00000010
321#define CT2_CHIP_MISC_PRG 0x000148a4
322#define __ETH_CLK_ENABLE_PORT0 0x00004000
323#define __APP_LPU_SPEED 0x00000002
324#define CT2_MBIST_STAT_REG 0x00014818
325#define CT2_MBIST_CTL_REG 0x0001481c
326#define CT2_PMM_1T_CONTROL_REG_P0 0x0002381c
327#define __PMM_1T_PNDB_P 0x00000002
328#define CT2_PMM_1T_CONTROL_REG_P1 0x00023c1c
329
330/*
331 * Name semaphore registers based on usage
332 */
333#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
334#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
335#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
336#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
337#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
338#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG
339
340/*
341 * CT2 semaphore register locations changed
342 */
343#define CT2_BFA_IOC0_HBEAT_REG CT2_HOST_SEM0_INFO_REG
344#define CT2_BFA_IOC0_STATE_REG CT2_HOST_SEM1_INFO_REG
345#define CT2_BFA_IOC1_HBEAT_REG CT2_HOST_SEM2_INFO_REG
346#define CT2_BFA_IOC1_STATE_REG CT2_HOST_SEM3_INFO_REG
347#define CT2_BFA_FW_USE_COUNT CT2_HOST_SEM4_INFO_REG
348#define CT2_BFA_IOC_FAIL_SYNC CT2_HOST_SEM5_INFO_REG
349
350#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
351#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
352
353/*
354 * And corresponding host interrupt status bit field defines
355 */
356#define __HFN_INT_CPE_Q0 0x00000001U
357#define __HFN_INT_CPE_Q1 0x00000002U
358#define __HFN_INT_CPE_Q2 0x00000004U
359#define __HFN_INT_CPE_Q3 0x00000008U
360#define __HFN_INT_CPE_Q4 0x00000010U
361#define __HFN_INT_CPE_Q5 0x00000020U
362#define __HFN_INT_CPE_Q6 0x00000040U
363#define __HFN_INT_CPE_Q7 0x00000080U
364#define __HFN_INT_RME_Q0 0x00000100U
365#define __HFN_INT_RME_Q1 0x00000200U
366#define __HFN_INT_RME_Q2 0x00000400U
367#define __HFN_INT_RME_Q3 0x00000800U
368#define __HFN_INT_RME_Q4 0x00001000U
369#define __HFN_INT_RME_Q5 0x00002000U
370#define __HFN_INT_RME_Q6 0x00004000U
371#define __HFN_INT_RME_Q7 0x00008000U
372#define __HFN_INT_ERR_EMC 0x00010000U
373#define __HFN_INT_ERR_LPU0 0x00020000U
374#define __HFN_INT_ERR_LPU1 0x00040000U
375#define __HFN_INT_ERR_PSS 0x00080000U
376#define __HFN_INT_MBOX_LPU0 0x00100000U
377#define __HFN_INT_MBOX_LPU1 0x00200000U
378#define __HFN_INT_MBOX1_LPU0 0x00400000U
379#define __HFN_INT_MBOX1_LPU1 0x00800000U
380#define __HFN_INT_LL_HALT 0x01000000U
381#define __HFN_INT_CPE_MASK 0x000000ffU
382#define __HFN_INT_RME_MASK 0x0000ff00U
383#define __HFN_INT_ERR_MASK \
384 (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \
385 __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT)
386#define __HFN_INT_FN0_MASK \
387 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
388 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
389 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0)
390#define __HFN_INT_FN1_MASK \
391 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
392 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
393 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1)
394
395/*
396 * Host interrupt status defines for catapult-2
397 */
398#define __HFN_INT_MBOX_LPU0_CT2 0x00010000U
399#define __HFN_INT_MBOX_LPU1_CT2 0x00020000U
400#define __HFN_INT_ERR_PSS_CT2 0x00040000U
401#define __HFN_INT_ERR_LPU0_CT2 0x00080000U
402#define __HFN_INT_ERR_LPU1_CT2 0x00100000U
403#define __HFN_INT_CPQ_HALT_CT2 0x00200000U
404#define __HFN_INT_ERR_WGN_CT2 0x00400000U
405#define __HFN_INT_ERR_LEHRX_CT2 0x00800000U
406#define __HFN_INT_ERR_LEHTX_CT2 0x01000000U
407#define __HFN_INT_ERR_MASK_CT2 \
408 (__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \
409 __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \
410 __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \
411 __HFN_INT_ERR_LEHTX_CT2)
412#define __HFN_INT_FN0_MASK_CT2 \
413 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
414 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
415 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2)
416#define __HFN_INT_FN1_MASK_CT2 \
417 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
418 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
419 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2)
420
421/*
422 * asic memory map.
423 */
424#define PSS_SMEM_PAGE_START 0x8000
425#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
426#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
427
428#endif /* __BFI_REG_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 23:53:01 -0500