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-rw-r--r--Documentation/hwmon/it8710
-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/imx27-3ds.dts8
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts13
-rw-r--r--arch/arm/boot/dts/imx27.dtsi11
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts2
-rw-r--r--arch/arm/boot/dts/sun4i-cubieboard.dts4
-rw-r--r--arch/arm/boot/dts/sun5i-olinuxino.dts4
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c1
-rw-r--r--arch/arm/mach-ep93xx/include/mach/uncompress.h10
-rw-r--r--arch/arm/mach-exynos/common.h2
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c16
-rw-r--r--arch/arm/mach-imx/devices/platform-mx2-emma.c (renamed from arch/arm/plat-mxc/devices/platform-mx2-emma.c)4
-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c1
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c1
-rw-r--r--arch/arm/mach-omap2/board-h4.c83
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c1
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c78
-rw-r--r--arch/arm/mach-omap2/clock.h10
-rw-r--r--arch/arm/mach-omap2/clockdomain.c3
-rw-r--r--arch/arm/mach-omap2/common.c3
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c14
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c28
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c46
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c64
-rw-r--r--arch/arm/mach-omap2/mux.c10
-rw-r--r--arch/arm/mach-omap2/mux.h20
-rw-r--r--arch/arm/mach-omap2/mux34xx.c2
-rw-r--r--arch/arm/mach-omap2/serial.c3
-rw-r--r--arch/arm/mach-omap2/timer.c6
-rw-r--r--arch/arm/mach-omap2/usb-host.c4
-rw-r--r--arch/arm/mach-tegra/common.c2
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c4
-rw-r--r--arch/arm/mach-u300/core.c34
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h1
-rw-r--r--arch/arm/plat-omap/Makefile1
-rw-r--r--arch/arm/plat-omap/debug-devices.c92
-rw-r--r--arch/arm/plat-omap/include/plat/debug-devices.h2
-rw-r--r--drivers/amba/tegra-ahb.c2
-rw-r--r--drivers/base/dma-buf.c2
-rw-r--r--drivers/hwmon/hwmon-vid.c10
-rw-r--r--drivers/hwmon/hwmon.c26
-rw-r--r--drivers/hwmon/it87.c918
-rw-r--r--drivers/hwmon/w83627ehf.c99
-rw-r--r--drivers/hwmon/w83627hf.c81
-rw-r--r--drivers/mfd/omap-usb-host.c3
-rw-r--r--drivers/tty/serial/omap-serial.c3
-rw-r--r--include/linux/dma-buf.h99
-rw-r--r--include/linux/platform_data/serial-omap.h (renamed from arch/arm/plat-omap/include/plat/omap-serial.h)0
-rw-r--r--include/linux/platform_data/usb-omap.h3
-rw-r--r--include/video/omap-panel-tfp410.h2
-rw-r--r--kernel/sched/fair.c5
-rw-r--r--mm/ksm.c16
-rw-r--r--mm/vmscan.c12
58 files changed, 1017 insertions, 873 deletions
diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87
index 87850d86c559..8386aadc0a82 100644
--- a/Documentation/hwmon/it87
+++ b/Documentation/hwmon/it87
@@ -209,3 +209,13 @@ doesn't use CPU cycles.
209Trip points must be set properly before switching to automatic fan speed 209Trip points must be set properly before switching to automatic fan speed
210control mode. The driver will perform basic integrity checks before 210control mode. The driver will perform basic integrity checks before
211actually switching to automatic control mode. 211actually switching to automatic control mode.
212
213
214Temperature offset attributes
215-----------------------------
216
217The driver supports temp[1-3]_offset sysfs attributes to adjust the reported
218temperature for thermal diodes or diode-connected thermal transistors.
219If a temperature sensor is configured for thermistors, the attribute values
220are ignored. If the thermal sensor type is Intel PECI, the temperature offset
221must be programmed to the critical CPU temperature.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0f441740c22a..d077ef8426df 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
107 omap3-evm.dtb \ 107 omap3-evm.dtb \
108 omap3-tobi.dtb \ 108 omap3-tobi.dtb \
109 omap4-panda.dtb \ 109 omap4-panda.dtb \
110 omap4-panda-a4.dtb \
110 omap4-panda-es.dtb \ 111 omap4-panda-es.dtb \
111 omap4-var-som.dtb \ 112 omap4-var-som.dtb \
112 omap4-sdp.dtb \ 113 omap4-sdp.dtb \
@@ -131,8 +132,8 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
131 spear320-evb.dtb \ 132 spear320-evb.dtb \
132 spear320-hmi.dtb 133 spear320-hmi.dtb
133dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 134dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
134dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \ 135dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
135 sun5i-olinuxino.dtb 136 sun5i-a13-olinuxino.dtb
136dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 137dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
137 tegra20-medcom-wide.dtb \ 138 tegra20-medcom-wide.dtb \
138 tegra20-paz00.dtb \ 139 tegra20-paz00.dtb \
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
index b01c0d745fc5..fa04c7b18bcb 100644
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -21,17 +21,17 @@
21 }; 21 };
22 22
23 soc { 23 soc {
24 aipi@10000000 { /* aipi */ 24 aipi@10000000 { /* aipi1 */
25
26 uart1: serial@1000a000 { 25 uart1: serial@1000a000 {
27 fsl,uart-has-rtscts; 26 fsl,uart-has-rtscts;
28 status = "okay"; 27 status = "okay";
29 }; 28 };
29 };
30 30
31 fec@1002b000 { 31 aipi@10020000 { /* aipi2 */
32 ethernet@1002b000 {
32 status = "okay"; 33 status = "okay";
33 }; 34 };
34 }; 35 };
35 }; 36 };
36
37}; 37};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index af50469e34b2..53b0ec0c228e 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -21,8 +21,7 @@
21 }; 21 };
22 22
23 soc { 23 soc {
24 aipi@10000000 { /* aipi */ 24 aipi@10000000 { /* aipi1 */
25
26 serial@1000a000 { 25 serial@1000a000 {
27 fsl,uart-has-rtscts; 26 fsl,uart-has-rtscts;
28 status = "okay"; 27 status = "okay";
@@ -38,10 +37,6 @@
38 status = "okay"; 37 status = "okay";
39 }; 38 };
40 39
41 ethernet@1002b000 {
42 status = "okay";
43 };
44
45 i2c@1001d000 { 40 i2c@1001d000 {
46 clock-frequency = <400000>; 41 clock-frequency = <400000>;
47 status = "okay"; 42 status = "okay";
@@ -60,6 +55,12 @@
60 }; 55 };
61 }; 56 };
62 }; 57 };
58
59 aipi@10020000 { /* aipi2 */
60 ethernet@1002b000 {
61 status = "okay";
62 };
63 };
63 }; 64 };
64 65
65 nor_flash@c0000000 { 66 nor_flash@c0000000 {
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index b8d3905915ac..5a82cb5707a8 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -55,7 +55,7 @@
55 compatible = "fsl,aipi-bus", "simple-bus"; 55 compatible = "fsl,aipi-bus", "simple-bus";
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <1>; 57 #size-cells = <1>;
58 reg = <0x10000000 0x10000000>; 58 reg = <0x10000000 0x20000>;
59 ranges; 59 ranges;
60 60
61 wdog: wdog@10002000 { 61 wdog: wdog@10002000 {
@@ -211,6 +211,15 @@
211 status = "disabled"; 211 status = "disabled";
212 }; 212 };
213 213
214 };
215
216 aipi@10020000 { /* AIPI2 */
217 compatible = "fsl,aipi-bus", "simple-bus";
218 #address-cells = <1>;
219 #size-cells = <1>;
220 reg = <0x10020000 0x20000>;
221 ranges;
222
214 fec: ethernet@1002b000 { 223 fec: ethernet@1002b000 {
215 compatible = "fsl,imx27-fec"; 224 compatible = "fsl,imx27-fec";
216 reg = <0x1002b000 0x4000>; 225 reg = <0x1002b000 0x4000>;
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 77b84e17c477..9b0d07746cba 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -15,6 +15,6 @@
15 15
16 memory { 16 memory {
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x84000000>; /* 64 MB */ 18 reg = <0x80000000 0x4000000>; /* 64 MB */
19 }; 19 };
20}; 20};
diff --git a/arch/arm/boot/dts/sun4i-cubieboard.dts b/arch/arm/boot/dts/sun4i-cubieboard.dts
index f4ca126ad994..5cab82540437 100644
--- a/arch/arm/boot/dts/sun4i-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-cubieboard.dts
@@ -11,11 +11,11 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "sun4i.dtsi" 14/include/ "sun4i-a10.dtsi"
15 15
16/ { 16/ {
17 model = "Cubietech Cubieboard"; 17 model = "Cubietech Cubieboard";
18 compatible = "cubietech,cubieboard", "allwinner,sun4i"; 18 compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
19 19
20 aliases { 20 aliases {
21 serial0 = &uart0; 21 serial0 = &uart0;
diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
index d6ff889a5d87..498a091a4ea2 100644
--- a/arch/arm/boot/dts/sun5i-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
@@ -12,11 +12,11 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun5i.dtsi" 15/include/ "sun5i-a13.dtsi"
16 16
17/ { 17/ {
18 model = "Olimex A13-Olinuxino"; 18 model = "Olimex A13-Olinuxino";
19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i"; 19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
20 20
21 chosen { 21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 7211772edd9d..0299915575a8 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -41,6 +41,7 @@
41#include <mach/cp_intc.h> 41#include <mach/cp_intc.h>
42#include <mach/da8xx.h> 42#include <mach/da8xx.h>
43#include <mach/mux.h> 43#include <mach/mux.h>
44#include <mach/sram.h>
44 45
45#include <asm/mach-types.h> 46#include <asm/mach-types.h>
46#include <asm/mach/arch.h> 47#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index 16026c2b1c8c..d64274fc5760 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -47,13 +47,9 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
47 47
48static inline void putc(int c) 48static inline void putc(int c)
49{ 49{
50 int i; 50 /* Transmit fifo not full? */
51 51 while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)
52 for (i = 0; i < 1000; i++) { 52 ;
53 /* Transmit fifo not full? */
54 if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
55 break;
56 }
57 53
58 __raw_writeb(c, PHYS_UART_DATA); 54 __raw_writeb(c, PHYS_UART_DATA);
59} 55}
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index dac146df79ac..04744f9c120f 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -25,7 +25,7 @@ void exynos_init_late(void);
25#ifdef CONFIG_PM_GENERIC_DOMAINS 25#ifdef CONFIG_PM_GENERIC_DOMAINS
26int exynos_pm_late_initcall(void); 26int exynos_pm_late_initcall(void);
27#else 27#else
28static int exynos_pm_late_initcall(void) { return 0; } 28static inline int exynos_pm_late_initcall(void) { return 0; }
29#endif 29#endif
30 30
31#ifdef CONFIG_ARCH_EXYNOS4 31#ifdef CONFIG_ARCH_EXYNOS4
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index e8c0473c7568..579023f59dc1 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
319 unsigned long rate_ckih1, unsigned long rate_ckih2) 319 unsigned long rate_ckih1, unsigned long rate_ckih2)
320{ 320{
321 int i; 321 int i;
322 u32 val;
322 struct device_node *np; 323 struct device_node *np;
323 324
324 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); 325 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
@@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
390 imx_print_silicon_rev("i.MX51", mx51_revision()); 391 imx_print_silicon_rev("i.MX51", mx51_revision());
391 clk_disable_unprepare(clk[iim_gate]); 392 clk_disable_unprepare(clk[iim_gate]);
392 393
394 /*
395 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
396 * longer supported. Set to one for better power saving.
397 *
398 * The effect of not setting these bits is that MIPI clocks can't be
399 * enabled without the IPU clock being enabled aswell.
400 */
401 val = readl(MXC_CCM_CCDR);
402 val |= 1 << 18;
403 writel(val, MXC_CCM_CCDR);
404
405 val = readl(MXC_CCM_CLPCR);
406 val |= 1 << 23;
407 writel(val, MXC_CCM_CLPCR);
408
393 return 0; 409 return 0;
394} 410}
395 411
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c
index 508404ddd4ea..11bd01d402f2 100644
--- a/arch/arm/plat-mxc/devices/platform-mx2-emma.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-emma.c
@@ -6,8 +6,8 @@
6 * the terms of the GNU General Public License version 2 as published by the 6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9#include <mach/hardware.h> 9#include "../hardware.h"
10#include <mach/devices-common.h> 10#include "devices-common.h"
11 11
12#define imx_mx2_emmaprp_data_entry_single(soc) \ 12#define imx_mx2_emmaprp_data_entry_single(soc) \
13 { \ 13 { \
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index be0f62bf9037..41b581fd0213 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -26,6 +26,8 @@ config SOC_HAS_OMAP2_SDRC
26 26
27config SOC_HAS_REALTIME_COUNTER 27config SOC_HAS_REALTIME_COUNTER
28 bool "Real time free running counter" 28 bool "Real time free running counter"
29 depends on SOC_OMAP5
30 default y
29 31
30config ARCH_OMAP2 32config ARCH_OMAP2
31 bool "TI OMAP2" 33 bool "TI OMAP2"
@@ -79,7 +81,6 @@ config SOC_OMAP5
79 select ARM_GIC 81 select ARM_GIC
80 select CPU_V7 82 select CPU_V7
81 select HAVE_SMP 83 select HAVE_SMP
82 select SOC_HAS_REALTIME_COUNTER
83 select COMMON_CLK 84 select COMMON_CLK
84 85
85comment "OMAP Core Type" 86comment "OMAP Core Type"
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 7b201546834d..bb73afc9ac17 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -157,6 +157,7 @@ static struct omap_dss_device sdp3430_lcd_device = {
157 157
158static struct tfp410_platform_data dvi_panel = { 158static struct tfp410_platform_data dvi_panel = {
159 .power_down_gpio = -1, 159 .power_down_gpio = -1,
160 .i2c_bus_num = -1,
160}; 161};
161 162
162static struct omap_dss_device sdp3430_dvi_device = { 163static struct omap_dss_device sdp3430_dvi_device = {
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4be58fd071f6..f81a303b87ff 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -208,6 +208,7 @@ static struct omap_dss_device am3517_evm_tv_device = {
208 208
209static struct tfp410_platform_data dvi_panel = { 209static struct tfp410_platform_data dvi_panel = {
210 .power_down_gpio = -1, 210 .power_down_gpio = -1,
211 .i2c_bus_num = -1,
211}; 212};
212 213
213static struct omap_dss_device am3517_evm_dvi_device = { 214static struct omap_dss_device am3517_evm_dvi_device = {
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index c8e37dc00892..b3102c2f4a3c 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -241,6 +241,7 @@ static struct omap_dss_device cm_t35_lcd_device = {
241 241
242static struct tfp410_platform_data dvi_panel = { 242static struct tfp410_platform_data dvi_panel = {
243 .power_down_gpio = CM_T35_DVI_EN_GPIO, 243 .power_down_gpio = CM_T35_DVI_EN_GPIO,
244 .i2c_bus_num = -1,
244}; 245};
245 246
246static struct omap_dss_device cm_t35_dvi_device = { 247static struct omap_dss_device cm_t35_dvi_device = {
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 7667eb749522..12865af25d3a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -141,6 +141,7 @@ static struct omap_dss_device devkit8000_lcd_device = {
141 141
142static struct tfp410_platform_data dvi_panel = { 142static struct tfp410_platform_data dvi_panel = {
143 .power_down_gpio = -1, 143 .power_down_gpio = -1,
144 .i2c_bus_num = 1,
144}; 145};
145 146
146static struct omap_dss_device devkit8000_dvi_device = { 147static struct omap_dss_device devkit8000_dvi_device = {
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 9a3878ec2256..3be1311f9e33 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -27,14 +27,12 @@
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/input/matrix_keypad.h> 28#include <linux/input/matrix_keypad.h>
29#include <linux/mfd/menelaus.h> 29#include <linux/mfd/menelaus.h>
30#include <linux/omap-dma.h>
30 31
31#include <asm/mach-types.h> 32#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
33#include <asm/mach/map.h> 34#include <asm/mach/map.h>
34 35
35#include <linux/omap-dma.h>
36#include <plat/debug-devices.h>
37
38#include <video/omapdss.h> 36#include <video/omapdss.h>
39#include <video/omap-panel-generic-dpi.h> 37#include <video/omap-panel-generic-dpi.h>
40 38
@@ -42,11 +40,9 @@
42#include "mux.h" 40#include "mux.h"
43#include "control.h" 41#include "control.h"
44#include "gpmc.h" 42#include "gpmc.h"
43#include "gpmc-smc91x.h"
45 44
46#define H4_FLASH_CS 0 45#define H4_FLASH_CS 0
47#define H4_SMC91X_CS 1
48
49#define H4_ETHR_GPIO_IRQ 92
50 46
51#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE) 47#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
52static const uint32_t board_matrix_keys[] = { 48static const uint32_t board_matrix_keys[] = {
@@ -250,71 +246,31 @@ static u32 is_gpmc_muxed(void)
250 return 0; 246 return 0;
251} 247}
252 248
253static inline void __init h4_init_debug(void) 249#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
254{
255 int eth_cs;
256 unsigned long cs_mem_base;
257 unsigned int muxed, rate;
258 struct clk *gpmc_fck;
259
260 eth_cs = H4_SMC91X_CS;
261 250
262 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ 251static struct omap_smc91x_platform_data board_smc91x_data = {
263 if (IS_ERR(gpmc_fck)) { 252 .cs = 1,
264 WARN_ON(1); 253 .gpio_irq = 92,
265 return; 254 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL,
266 } 255};
267
268 clk_prepare_enable(gpmc_fck);
269 rate = clk_get_rate(gpmc_fck);
270 clk_disable_unprepare(gpmc_fck);
271 clk_put(gpmc_fck);
272 256
257static void __init board_smc91x_init(void)
258{
273 if (is_gpmc_muxed()) 259 if (is_gpmc_muxed())
274 muxed = 0x200; 260 board_smc91x_data.flags |= GPMC_MUX_ADD_DATA;
275 else
276 muxed = 0;
277
278 /* Make sure CS1 timings are correct */
279 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
280 0x00011000 | muxed);
281
282 if (rate >= 160000000) {
283 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
284 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
285 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
286 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
287 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
288 } else if (rate >= 130000000) {
289 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
290 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
291 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
292 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
293 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
294 } else {/* rate = 100000000 */
295 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
296 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
297 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
298 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
299 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
300 }
301
302 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
303 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
304 goto out;
305 }
306 261
307 udelay(100); 262 omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT);
263 gpmc_smc91x_init(&board_smc91x_data);
264}
308 265
309 omap_mux_init_gpio(92, 0); 266#else
310 if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0)
311 gpmc_cs_free(eth_cs);
312 267
313out: 268static inline void board_smc91x_init(void)
314 clk_disable_unprepare(gpmc_fck); 269{
315 clk_put(gpmc_fck);
316} 270}
317 271
272#endif
273
318static void __init h4_init_flash(void) 274static void __init h4_init_flash(void)
319{ 275{
320 unsigned long base; 276 unsigned long base;
@@ -371,6 +327,7 @@ static void __init omap_h4_init(void)
371 omap_serial_init(); 327 omap_serial_init();
372 omap_sdrc_init(NULL, NULL); 328 omap_sdrc_init(NULL, NULL);
373 h4_init_flash(); 329 h4_init_flash();
330 board_smc91x_init();
374 331
375 omap_display_init(&h4_dss_data); 332 omap_display_init(&h4_dss_data);
376} 333}
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 54647d6286b4..3985f35aee06 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -240,6 +240,7 @@ static struct omap_dss_device omap3_evm_tv_device = {
240 240
241static struct tfp410_platform_data dvi_panel = { 241static struct tfp410_platform_data dvi_panel = {
242 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, 242 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
243 .i2c_bus_num = -1,
243}; 244};
244 245
245static struct omap_dss_device omap3_evm_dvi_device = { 246static struct omap_dss_device omap3_evm_dvi_device = {
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index d8638b3b4f94..53a6cbcf9747 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -118,6 +118,7 @@ static struct omap_dss_device omap3_stalker_tv_device = {
118 118
119static struct tfp410_platform_data dvi_panel = { 119static struct tfp410_platform_data dvi_panel = {
120 .power_down_gpio = DSS_ENABLE_GPIO, 120 .power_down_gpio = DSS_ENABLE_GPIO,
121 .i2c_bus_num = -1,
121}; 122};
122 123
123static struct omap_dss_device omap3_stalker_dvi_device = { 124static struct omap_dss_device omap3_stalker_dvi_device = {
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index aa56c3e5bb34..5789a5e25563 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -40,6 +40,14 @@
40#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 40#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
41#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 41#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
42 42
43/*
44 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
45 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
46 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
47 * half of this value.
48 */
49#define OMAP4_DPLL_ABE_DEFFREQ 98304000
50
43/* Root clocks */ 51/* Root clocks */
44 52
45DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); 53DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -124,6 +132,8 @@ static struct dpll_data dpll_abe_dd = {
124 .enable_mask = OMAP4430_DPLL_EN_MASK, 132 .enable_mask = OMAP4430_DPLL_EN_MASK,
125 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 133 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
126 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 134 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
135 .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
136 .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
127 .max_multiplier = 2047, 137 .max_multiplier = 2047,
128 .max_divider = 128, 138 .max_divider = 128,
129 .min_divider = 1, 139 .min_divider = 1,
@@ -233,7 +243,7 @@ static struct dpll_data dpll_core_dd = {
233 243
234 244
235static const char *dpll_core_ck_parents[] = { 245static const char *dpll_core_ck_parents[] = {
236 "sys_clkin_ck", 246 "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
237}; 247};
238 248
239static struct clk dpll_core_ck; 249static struct clk dpll_core_ck;
@@ -286,9 +296,9 @@ DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
286 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, 296 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
287 OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); 297 OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
288 298
289DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", 299DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
290 &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, 300 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
291 OMAP4430_CLKSEL_0_1_MASK); 301 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
292 302
293DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 303DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
294 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, 304 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
@@ -363,8 +373,21 @@ static struct dpll_data dpll_iva_dd = {
363 .min_divider = 1, 373 .min_divider = 1,
364}; 374};
365 375
376static const char *dpll_iva_ck_parents[] = {
377 "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
378};
379
366static struct clk dpll_iva_ck; 380static struct clk dpll_iva_ck;
367 381
382static const struct clk_ops dpll_ck_ops = {
383 .enable = &omap3_noncore_dpll_enable,
384 .disable = &omap3_noncore_dpll_disable,
385 .recalc_rate = &omap3_dpll_recalc,
386 .round_rate = &omap2_dpll_round_rate,
387 .set_rate = &omap3_noncore_dpll_set_rate,
388 .get_parent = &omap2_init_dpll_parent,
389};
390
368static struct clk_hw_omap dpll_iva_ck_hw = { 391static struct clk_hw_omap dpll_iva_ck_hw = {
369 .hw = { 392 .hw = {
370 .clk = &dpll_iva_ck, 393 .clk = &dpll_iva_ck,
@@ -373,7 +396,7 @@ static struct clk_hw_omap dpll_iva_ck_hw = {
373 .ops = &clkhwops_omap3_dpll, 396 .ops = &clkhwops_omap3_dpll,
374}; 397};
375 398
376DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops); 399DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
377 400
378static const char *dpll_iva_x2_ck_parents[] = { 401static const char *dpll_iva_x2_ck_parents[] = {
379 "dpll_iva_ck", 402 "dpll_iva_ck",
@@ -416,6 +439,10 @@ static struct dpll_data dpll_mpu_dd = {
416 .min_divider = 1, 439 .min_divider = 1,
417}; 440};
418 441
442static const char *dpll_mpu_ck_parents[] = {
443 "sys_clkin_ck", "div_mpu_hs_clk"
444};
445
419static struct clk dpll_mpu_ck; 446static struct clk dpll_mpu_ck;
420 447
421static struct clk_hw_omap dpll_mpu_ck_hw = { 448static struct clk_hw_omap dpll_mpu_ck_hw = {
@@ -426,7 +453,7 @@ static struct clk_hw_omap dpll_mpu_ck_hw = {
426 .ops = &clkhwops_omap3_dpll, 453 .ops = &clkhwops_omap3_dpll,
427}; 454};
428 455
429DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops); 456DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
430 457
431DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); 458DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
432 459
@@ -464,6 +491,9 @@ static struct dpll_data dpll_per_dd = {
464 .min_divider = 1, 491 .min_divider = 1,
465}; 492};
466 493
494static const char *dpll_per_ck_parents[] = {
495 "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
496};
467 497
468static struct clk dpll_per_ck; 498static struct clk dpll_per_ck;
469 499
@@ -475,7 +505,7 @@ static struct clk_hw_omap dpll_per_ck_hw = {
475 .ops = &clkhwops_omap3_dpll, 505 .ops = &clkhwops_omap3_dpll,
476}; 506};
477 507
478DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops); 508DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
479 509
480DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, 510DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
481 OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, 511 OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
@@ -559,6 +589,10 @@ static struct dpll_data dpll_usb_dd = {
559 .min_divider = 1, 589 .min_divider = 1,
560}; 590};
561 591
592static const char *dpll_usb_ck_parents[] = {
593 "sys_clkin_ck", "usb_hs_clk_div_ck"
594};
595
562static struct clk dpll_usb_ck; 596static struct clk dpll_usb_ck;
563 597
564static struct clk_hw_omap dpll_usb_ck_hw = { 598static struct clk_hw_omap dpll_usb_ck_hw = {
@@ -569,7 +603,7 @@ static struct clk_hw_omap dpll_usb_ck_hw = {
569 .ops = &clkhwops_omap3_dpll, 603 .ops = &clkhwops_omap3_dpll,
570}; 604};
571 605
572DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops); 606DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);
573 607
574static const char *dpll_usb_clkdcoldo_ck_parents[] = { 608static const char *dpll_usb_clkdcoldo_ck_parents[] = {
575 "dpll_usb_ck", 609 "dpll_usb_ck",
@@ -696,9 +730,13 @@ DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
696 OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, 730 OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
697 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); 731 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
698 732
733static const char *dbgclk_mux_ck_parents[] = {
734 "sys_clkin_ck"
735};
736
699static struct clk dbgclk_mux_ck; 737static struct clk dbgclk_mux_ck;
700DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); 738DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
701DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents, 739DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
702 dpll_usb_clkdcoldo_ck_ops); 740 dpll_usb_clkdcoldo_ck_ops);
703 741
704/* Leaf clocks controlled by modules */ 742/* Leaf clocks controlled by modules */
@@ -1935,10 +1973,10 @@ static struct omap_clk omap44xx_clks[] = {
1935 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1973 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1936 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1974 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1937 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1975 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1938 CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1976 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1939 CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1977 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1940 CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1978 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1941 CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1979 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1942 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), 1980 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
1943}; 1981};
1944 1982
@@ -1955,6 +1993,7 @@ int __init omap4xxx_clk_init(void)
1955{ 1993{
1956 u32 cpu_clkflg; 1994 u32 cpu_clkflg;
1957 struct omap_clk *c; 1995 struct omap_clk *c;
1996 int rc;
1958 1997
1959 if (cpu_is_omap443x()) { 1998 if (cpu_is_omap443x()) {
1960 cpu_mask = RATE_IN_4430; 1999 cpu_mask = RATE_IN_4430;
@@ -1983,5 +2022,18 @@ int __init omap4xxx_clk_init(void)
1983 omap2_clk_enable_init_clocks(enable_init_clks, 2022 omap2_clk_enable_init_clocks(enable_init_clks,
1984 ARRAY_SIZE(enable_init_clks)); 2023 ARRAY_SIZE(enable_init_clks));
1985 2024
2025 /*
2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
2027 * state when turning the ABE clock domain. Workaround this by
2028 * locking the ABE DPLL on boot.
2029 */
2030 if (cpu_is_omap446x()) {
2031 rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
2032 if (!rc)
2033 rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
2034 if (rc)
2035 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
2036 }
2037
1986 return 0; 2038 return 0;
1987} 2039}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 9917f793c3b6..b40204837bd7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -195,6 +195,10 @@ struct clksel {
195 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 195 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
196 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 196 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
197 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 197 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
198 * @last_rounded_m4xen: cache of the last M4X result of
199 * omap4_dpll_regm4xen_round_rate()
200 * @last_rounded_lpmode: cache of the last lpmode result of
201 * omap4_dpll_lpmode_recalc()
198 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 202 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
199 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() 203 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
200 * @min_divider: minimum valid non-bypass divider value (actual) 204 * @min_divider: minimum valid non-bypass divider value (actual)
@@ -205,6 +209,8 @@ struct clksel {
205 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg 209 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
206 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg 210 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
207 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg 211 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
212 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
213 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
208 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg 214 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
209 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs 215 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
210 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs 216 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
@@ -233,6 +239,8 @@ struct dpll_data {
233 u32 enable_mask; 239 u32 enable_mask;
234 unsigned long last_rounded_rate; 240 unsigned long last_rounded_rate;
235 u16 last_rounded_m; 241 u16 last_rounded_m;
242 u8 last_rounded_m4xen;
243 u8 last_rounded_lpmode;
236 u16 max_multiplier; 244 u16 max_multiplier;
237 u8 last_rounded_n; 245 u8 last_rounded_n;
238 u8 min_divider; 246 u8 min_divider;
@@ -245,6 +253,8 @@ struct dpll_data {
245 u32 idlest_mask; 253 u32 idlest_mask;
246 u32 dco_mask; 254 u32 dco_mask;
247 u32 sddiv_mask; 255 u32 sddiv_mask;
256 u32 lpmode_mask;
257 u32 m4xen_mask;
248 u8 auto_recal_bit; 258 u8 auto_recal_bit;
249 u8 recal_en_bit; 259 u8 recal_en_bit;
250 u8 recal_st_bit; 260 u8 recal_st_bit;
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 384873580b23..7faf82d4e85c 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -998,7 +998,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
998 spin_lock_irqsave(&clkdm->lock, flags); 998 spin_lock_irqsave(&clkdm->lock, flags);
999 999
1000 /* corner case: disabling unused clocks */ 1000 /* corner case: disabling unused clocks */
1001 if (__clk_get_enable_count(clk) == 0) 1001 if ((__clk_get_enable_count(clk) == 0) &&
1002 (atomic_read(&clkdm->usecount) == 0))
1002 goto ccd_exit; 1003 goto ccd_exit;
1003 1004
1004 if (atomic_read(&clkdm->usecount) == 0) { 1005 if (atomic_read(&clkdm->usecount) == 0) {
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 5c2fd4863b2b..2dabb9ecb986 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -16,8 +16,6 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/platform_data/dsp-omap.h> 17#include <linux/platform_data/dsp-omap.h>
18 18
19#include <plat/vram.h>
20
21#include "common.h" 19#include "common.h"
22#include "omap-secure.h" 20#include "omap-secure.h"
23 21
@@ -32,7 +30,6 @@ int __weak omap_secure_ram_reserve_memblock(void)
32 30
33void __init omap_reserve(void) 31void __init omap_reserve(void)
34{ 32{
35 omap_vram_reserve_sdram_memblock();
36 omap_dsp_reserve_sdram_memblock(); 33 omap_dsp_reserve_sdram_memblock();
37 omap_secure_ram_reserve_memblock(); 34 omap_secure_ram_reserve_memblock();
38 omap_barrier_reserve_memblock(); 35 omap_barrier_reserve_memblock();
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index bca7a8885703..22590dbe8f14 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -40,6 +40,8 @@ struct omap3_idle_statedata {
40 u32 core_state; 40 u32 core_state;
41}; 41};
42 42
43static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
44
43static struct omap3_idle_statedata omap3_idle_data[] = { 45static struct omap3_idle_statedata omap3_idle_data[] = {
44 { 46 {
45 .mpu_state = PWRDM_POWER_ON, 47 .mpu_state = PWRDM_POWER_ON,
@@ -71,7 +73,7 @@ static struct omap3_idle_statedata omap3_idle_data[] = {
71 }, 73 },
72}; 74};
73 75
74static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; 76/* Private functions */
75 77
76static int __omap3_enter_idle(struct cpuidle_device *dev, 78static int __omap3_enter_idle(struct cpuidle_device *dev,
77 struct cpuidle_driver *drv, 79 struct cpuidle_driver *drv,
@@ -260,11 +262,11 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
260 return ret; 262 return ret;
261} 263}
262 264
263DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); 265static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
264 266
265struct cpuidle_driver omap3_idle_driver = { 267static struct cpuidle_driver omap3_idle_driver = {
266 .name = "omap3_idle", 268 .name = "omap3_idle",
267 .owner = THIS_MODULE, 269 .owner = THIS_MODULE,
268 .states = { 270 .states = {
269 { 271 {
270 .enter = omap3_enter_idle_bm, 272 .enter = omap3_enter_idle_bm,
@@ -327,6 +329,8 @@ struct cpuidle_driver omap3_idle_driver = {
327 .safe_state_index = 0, 329 .safe_state_index = 0,
328}; 330};
329 331
332/* Public functions */
333
330/** 334/**
331 * omap3_idle_init - Init routine for OMAP3 idle 335 * omap3_idle_init - Init routine for OMAP3 idle
332 * 336 *
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 288bee6cbb76..d639aef0deda 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -54,6 +54,8 @@ static struct clockdomain *cpu_clkdm[NR_CPUS];
54static atomic_t abort_barrier; 54static atomic_t abort_barrier;
55static bool cpu_done[NR_CPUS]; 55static bool cpu_done[NR_CPUS];
56 56
57/* Private functions */
58
57/** 59/**
58 * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions 60 * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
59 * @dev: cpuidle device 61 * @dev: cpuidle device
@@ -161,9 +163,19 @@ fail:
161 return index; 163 return index;
162} 164}
163 165
164DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); 166/*
167 * For each cpu, setup the broadcast timer because local timers
168 * stops for the states above C1.
169 */
170static void omap_setup_broadcast_timer(void *arg)
171{
172 int cpu = smp_processor_id();
173 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
174}
175
176static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
165 177
166struct cpuidle_driver omap4_idle_driver = { 178static struct cpuidle_driver omap4_idle_driver = {
167 .name = "omap4_idle", 179 .name = "omap4_idle",
168 .owner = THIS_MODULE, 180 .owner = THIS_MODULE,
169 .en_core_tk_irqen = 1, 181 .en_core_tk_irqen = 1,
@@ -178,7 +190,7 @@ struct cpuidle_driver omap4_idle_driver = {
178 .desc = "MPUSS ON" 190 .desc = "MPUSS ON"
179 }, 191 },
180 { 192 {
181 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ 193 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
182 .exit_latency = 328 + 440, 194 .exit_latency = 328 + 440,
183 .target_residency = 960, 195 .target_residency = 960,
184 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, 196 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
@@ -200,15 +212,7 @@ struct cpuidle_driver omap4_idle_driver = {
200 .safe_state_index = 0, 212 .safe_state_index = 0,
201}; 213};
202 214
203/* 215/* Public functions */
204 * For each cpu, setup the broadcast timer because local timers
205 * stops for the states above C1.
206 */
207static void omap_setup_broadcast_timer(void *arg)
208{
209 int cpu = smp_processor_id();
210 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
211}
212 216
213/** 217/**
214 * omap4_idle_init - Init routine for OMAP4 idle 218 * omap4_idle_init - Init routine for OMAP4 idle
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fafb28c0dcbc..2bb18838cba9 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -291,16 +291,13 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
291 291
292/* 292/*
293 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly 293 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
294 * @clk: struct clk * of DPLL to set 294 * @clk: struct clk * of DPLL to set
295 * @m: DPLL multiplier to set 295 * @freqsel: FREQSEL value to set
296 * @n: DPLL divider to set
297 * @freqsel: FREQSEL value to set
298 * 296 *
299 * Program the DPLL with the supplied M, N values, and wait for the DPLL to 297 * Program the DPLL with the last M, N values calculated, and wait for
300 * lock.. Returns -EINVAL upon error, or 0 upon success. 298 * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
301 */ 299 */
302static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, 300static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
303 u16 freqsel)
304{ 301{
305 struct dpll_data *dd = clk->dpll_data; 302 struct dpll_data *dd = clk->dpll_data;
306 u8 dco, sd_div; 303 u8 dco, sd_div;
@@ -323,23 +320,45 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
323 /* Set DPLL multiplier, divider */ 320 /* Set DPLL multiplier, divider */
324 v = __raw_readl(dd->mult_div1_reg); 321 v = __raw_readl(dd->mult_div1_reg);
325 v &= ~(dd->mult_mask | dd->div1_mask); 322 v &= ~(dd->mult_mask | dd->div1_mask);
326 v |= m << __ffs(dd->mult_mask); 323 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
327 v |= (n - 1) << __ffs(dd->div1_mask); 324 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
328 325
329 /* Configure dco and sd_div for dplls that have these fields */ 326 /* Configure dco and sd_div for dplls that have these fields */
330 if (dd->dco_mask) { 327 if (dd->dco_mask) {
331 _lookup_dco(clk, &dco, m, n); 328 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
332 v &= ~(dd->dco_mask); 329 v &= ~(dd->dco_mask);
333 v |= dco << __ffs(dd->dco_mask); 330 v |= dco << __ffs(dd->dco_mask);
334 } 331 }
335 if (dd->sddiv_mask) { 332 if (dd->sddiv_mask) {
336 _lookup_sddiv(clk, &sd_div, m, n); 333 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
334 dd->last_rounded_n);
337 v &= ~(dd->sddiv_mask); 335 v &= ~(dd->sddiv_mask);
338 v |= sd_div << __ffs(dd->sddiv_mask); 336 v |= sd_div << __ffs(dd->sddiv_mask);
339 } 337 }
340 338
341 __raw_writel(v, dd->mult_div1_reg); 339 __raw_writel(v, dd->mult_div1_reg);
342 340
341 /* Set 4X multiplier and low-power mode */
342 if (dd->m4xen_mask || dd->lpmode_mask) {
343 v = __raw_readl(dd->control_reg);
344
345 if (dd->m4xen_mask) {
346 if (dd->last_rounded_m4xen)
347 v |= dd->m4xen_mask;
348 else
349 v &= ~dd->m4xen_mask;
350 }
351
352 if (dd->lpmode_mask) {
353 if (dd->last_rounded_lpmode)
354 v |= dd->lpmode_mask;
355 else
356 v &= ~dd->lpmode_mask;
357 }
358
359 __raw_writel(v, dd->control_reg);
360 }
361
343 /* We let the clock framework set the other output dividers later */ 362 /* We let the clock framework set the other output dividers later */
344 363
345 /* REVISIT: Set ramp-up delay? */ 364 /* REVISIT: Set ramp-up delay? */
@@ -492,8 +511,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
492 pr_debug("%s: %s: set rate: locking rate to %lu.\n", 511 pr_debug("%s: %s: set rate: locking rate to %lu.\n",
493 __func__, __clk_get_name(hw->clk), rate); 512 __func__, __clk_get_name(hw->clk), rate);
494 513
495 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, 514 ret = omap3_noncore_dpll_program(clk, freqsel);
496 dd->last_rounded_n, freqsel);
497 if (!ret) 515 if (!ret)
498 new_parent = dd->clk_ref; 516 new_parent = dd->clk_ref;
499 } 517 }
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index d3326c474fdc..d28b0f726715 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -20,6 +20,15 @@
20#include "clock44xx.h" 20#include "clock44xx.h"
21#include "cm-regbits-44xx.h" 21#include "cm-regbits-44xx.h"
22 22
23/*
24 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
25 * can supported when using the DPLL low-power mode. Frequencies are
26 * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
27 * Status, and Low-Power Operation Mode".
28 */
29#define OMAP4_DPLL_LP_FINT_MAX 1000000
30#define OMAP4_DPLL_LP_FOUT_MAX 100000000
31
23/* Supported only on OMAP4 */ 32/* Supported only on OMAP4 */
24int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) 33int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
25{ 34{
@@ -82,6 +91,31 @@ const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
82}; 91};
83 92
84/** 93/**
94 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
95 * @dd: pointer to the dpll data structure
96 *
97 * Calculates if low-power mode can be enabled based upon the last
98 * multiplier and divider values calculated. If low-power mode can be
99 * enabled, then the bit to enable low-power mode is stored in the
100 * last_rounded_lpmode variable. This implementation is based upon the
101 * criteria for enabling low-power mode as described in the OMAP4430/60
102 * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
103 * Operation Mode".
104 */
105static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
106{
107 long fint, fout;
108
109 fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
110 fout = fint * dd->last_rounded_m;
111
112 if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
113 dd->last_rounded_lpmode = 1;
114 else
115 dd->last_rounded_lpmode = 0;
116}
117
118/**
85 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit 119 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
86 * @clk: struct clk * of the DPLL to compute the rate for 120 * @clk: struct clk * of the DPLL to compute the rate for
87 * 121 *
@@ -130,7 +164,6 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
130 unsigned long *parent_rate) 164 unsigned long *parent_rate)
131{ 165{
132 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 166 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
133 u32 v;
134 struct dpll_data *dd; 167 struct dpll_data *dd;
135 long r; 168 long r;
136 169
@@ -139,18 +172,31 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
139 172
140 dd = clk->dpll_data; 173 dd = clk->dpll_data;
141 174
142 /* regm4xen adds a multiplier of 4 to DPLL calculations */ 175 dd->last_rounded_m4xen = 0;
143 v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
144
145 if (v)
146 target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
147 176
177 /*
178 * First try to compute the DPLL configuration for
179 * target rate without using the 4X multiplier.
180 */
148 r = omap2_dpll_round_rate(hw, target_rate, NULL); 181 r = omap2_dpll_round_rate(hw, target_rate, NULL);
182 if (r != ~0)
183 goto out;
184
185 /*
186 * If we did not find a valid DPLL configuration, try again, but
187 * this time see if using the 4X multiplier can help. Enabling the
188 * 4X multiplier is equivalent to dividing the target rate by 4.
189 */
190 r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
191 NULL);
149 if (r == ~0) 192 if (r == ~0)
150 return r; 193 return r;
151 194
152 if (v) 195 dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
153 clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; 196 dd->last_rounded_m4xen = 1;
197
198out:
199 omap4_dpll_lpmode_recalc(dd);
154 200
155 return clk->dpll_data->last_rounded_rate; 201 return dd->last_rounded_rate;
156} 202}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 26126343d6ac..6a217c98db54 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -135,10 +135,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
135 135
136 old_mode = omap_mux_read(partition, gpio_mux->reg_offset); 136 old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
137 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); 137 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
138 if (partition->flags & OMAP_MUX_GPIO_IN_MODE3) 138 mux_mode |= partition->gpio;
139 mux_mode |= OMAP_MUX_MODE3;
140 else
141 mux_mode |= OMAP_MUX_MODE4;
142 pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__, 139 pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
143 gpio_mux->muxnames[0], gpio, old_mode, mux_mode); 140 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
144 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); 141 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
@@ -800,7 +797,7 @@ int __init omap_mux_late_init(void)
800 struct omap_mux *m = &e->mux; 797 struct omap_mux *m = &e->mux;
801 u16 mode = omap_mux_read(partition, m->reg_offset); 798 u16 mode = omap_mux_read(partition, m->reg_offset);
802 799
803 if (OMAP_MODE_GPIO(mode)) 800 if (OMAP_MODE_GPIO(partition, mode))
804 continue; 801 continue;
805 802
806#ifndef CONFIG_DEBUG_FS 803#ifndef CONFIG_DEBUG_FS
@@ -1065,7 +1062,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition,
1065 } 1062 }
1066#else 1063#else
1067 /* Skip pins that are not muxed as GPIO by bootloader */ 1064 /* Skip pins that are not muxed as GPIO by bootloader */
1068 if (!OMAP_MODE_GPIO(omap_mux_read(partition, 1065 if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
1069 superset->reg_offset))) { 1066 superset->reg_offset))) {
1070 superset++; 1067 superset++;
1071 continue; 1068 continue;
@@ -1132,6 +1129,7 @@ int __init omap_mux_init(const char *name, u32 flags,
1132 1129
1133 partition->name = name; 1130 partition->name = name;
1134 partition->flags = flags; 1131 partition->flags = flags;
1132 partition->gpio = flags & OMAP_MUX_MODE7;
1135 partition->size = mux_size; 1133 partition->size = mux_size;
1136 partition->phys = mux_pbase; 1134 partition->phys = mux_pbase;
1137 partition->base = ioremap(mux_pbase, mux_size); 1135 partition->base = ioremap(mux_pbase, mux_size);
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 76f9b3c2f586..fdb22f14021f 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -58,7 +58,8 @@
58#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN) 58#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
59#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN 59#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
60 60
61#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) 61#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
62 partition->gpio)
62#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0) 63#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
63 64
64/* Flags for omapX_mux_init */ 65/* Flags for omapX_mux_init */
@@ -79,13 +80,20 @@
79/* 80/*
80 * omap_mux_init flags definition: 81 * omap_mux_init flags definition:
81 * 82 *
83 * OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
84 * register which includes values from 0-7.
82 * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits. 85 * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
83 * The default value is 16 bits. 86 * The default value is 16 bits.
84 * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
85 * The default is mode4.
86 */ 87 */
87#define OMAP_MUX_REG_8BIT (1 << 0) 88#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
88#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1) 89#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
90#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
91#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
92#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
93#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
94#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
95#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
96#define OMAP_MUX_REG_8BIT (1 << 3)
89 97
90/** 98/**
91 * struct omap_board_data - board specific device data 99 * struct omap_board_data - board specific device data
@@ -105,6 +113,7 @@ struct omap_board_data {
105 * struct mux_partition - contain partition related information 113 * struct mux_partition - contain partition related information
106 * @name: name of the current partition 114 * @name: name of the current partition
107 * @flags: flags specific to this partition 115 * @flags: flags specific to this partition
116 * @gpio: gpio mux mode
108 * @phys: physical address 117 * @phys: physical address
109 * @size: partition size 118 * @size: partition size
110 * @base: virtual address after ioremap 119 * @base: virtual address after ioremap
@@ -114,6 +123,7 @@ struct omap_board_data {
114struct omap_mux_partition { 123struct omap_mux_partition {
115 const char *name; 124 const char *name;
116 u32 flags; 125 u32 flags;
126 u32 gpio;
117 u32 phys; 127 u32 phys;
118 u32 size; 128 u32 size;
119 void __iomem *base; 129 void __iomem *base;
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index c47140bbbec4..c53609f46294 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -2053,7 +2053,7 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
2053 return -EINVAL; 2053 return -EINVAL;
2054 } 2054 }
2055 2055
2056 return omap_mux_init("core", 0, 2056 return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
2057 OMAP3_CONTROL_PADCONF_MUX_PBASE, 2057 OMAP3_CONTROL_PADCONF_MUX_PBASE,
2058 OMAP3_CONTROL_PADCONF_MUX_SIZE, 2058 OMAP3_CONTROL_PADCONF_MUX_SIZE,
2059 omap3_muxmodes, package_subset, board_subset, 2059 omap3_muxmodes, package_subset, board_subset,
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 93d102535c85..04fdbc4c499b 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -27,8 +27,7 @@
27#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
28#include <linux/console.h> 28#include <linux/console.h>
29#include <linux/omap-dma.h> 29#include <linux/omap-dma.h>
30 30#include <linux/platform_data/serial-omap.h>
31#include <plat/omap-serial.h>
32 31
33#include "common.h" 32#include "common.h"
34#include "omap_hwmod.h" 33#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 7016637b531c..06e141543623 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -190,7 +190,7 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
190 * kernel registering these devices remove them dynamically from the device 190 * kernel registering these devices remove them dynamically from the device
191 * tree on boot. 191 * tree on boot.
192 */ 192 */
193void __init omap_dmtimer_init(void) 193static void __init omap_dmtimer_init(void)
194{ 194{
195 struct device_node *np; 195 struct device_node *np;
196 196
@@ -210,7 +210,7 @@ void __init omap_dmtimer_init(void)
210 * 210 *
211 * Get the timer errata flags that are specific to the OMAP device being used. 211 * Get the timer errata flags that are specific to the OMAP device being used.
212 */ 212 */
213u32 __init omap_dm_timer_get_errata(void) 213static u32 __init omap_dm_timer_get_errata(void)
214{ 214{
215 if (cpu_is_omap24xx()) 215 if (cpu_is_omap24xx())
216 return 0; 216 return 0;
@@ -392,7 +392,7 @@ static struct of_device_id omap_counter_match[] __initdata = {
392}; 392};
393 393
394/* Setup free-running counter for clocksource */ 394/* Setup free-running counter for clocksource */
395static int __init omap2_sync32k_clocksource_init(void) 395static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
396{ 396{
397 int ret; 397 int ret;
398 struct device_node *np = NULL; 398 struct device_node *np = NULL;
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index d1dbe125b34f..2e44e8a22884 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -508,6 +508,10 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
508 if (cpu_is_omap34xx()) { 508 if (cpu_is_omap34xx()) {
509 setup_ehci_io_mux(pdata->port_mode); 509 setup_ehci_io_mux(pdata->port_mode);
510 setup_ohci_io_mux(pdata->port_mode); 510 setup_ohci_io_mux(pdata->port_mode);
511
512 if (omap_rev() <= OMAP3430_REV_ES2_1)
513 usbhs_data.single_ulpi_bypass = true;
514
511 } else if (cpu_is_omap44xx()) { 515 } else if (cpu_is_omap44xx()) {
512 setup_4430ehci_io_mux(pdata->port_mode); 516 setup_4430ehci_io_mux(pdata->port_mode);
513 setup_4430ohci_io_mux(pdata->port_mode); 517 setup_4430ohci_io_mux(pdata->port_mode);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0816562725f6..d54cfc54b9fe 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -104,7 +104,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
104static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { 104static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
105 /* name parent rate enabled */ 105 /* name parent rate enabled */
106 { "clk_m", NULL, 0, true }, 106 { "clk_m", NULL, 0, true },
107 { "pll_p", "clk_m", 408000000, true }, 107 { "pll_p", "pll_ref", 408000000, true },
108 { "pll_p_out1", "pll_p", 9600000, true }, 108 { "pll_p_out1", "pll_p", 9600000, true },
109 { "pll_p_out4", "pll_p", 102000000, true }, 109 { "pll_p_out4", "pll_p", 102000000, true },
110 { "sclk", "pll_p_out4", 102000000, true }, 110 { "sclk", "pll_p_out4", 102000000, true },
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index efc000e32e1c..d7147779f8ea 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2045,9 +2045,7 @@ struct clk_ops tegra30_periph_clk_ops = {
2045static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) 2045static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
2046{ 2046{
2047 struct clk *d = clk_get_sys(NULL, "pll_d"); 2047 struct clk *d = clk_get_sys(NULL, "pll_d");
2048 /* The DSIB parent selection bit is in PLLD base 2048 /* The DSIB parent selection bit is in PLLD base register */
2049 register - can not do direct r-m-w, must be
2050 protected by PLLD lock */
2051 tegra_clk_cfg_ex( 2049 tegra_clk_cfg_ex(
2052 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); 2050 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
2053 2051
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 8b204ae69002..4ce77cdc31cc 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -27,7 +27,6 @@
27#include <linux/mtd/nand.h> 27#include <linux/mtd/nand.h>
28#include <linux/mtd/fsmc.h> 28#include <linux/mtd/fsmc.h>
29#include <linux/pinctrl/machine.h> 29#include <linux/pinctrl/machine.h>
30#include <linux/pinctrl/consumer.h>
31#include <linux/pinctrl/pinconf-generic.h> 30#include <linux/pinctrl/pinconf-generic.h>
32#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
33#include <linux/platform_data/clk-u300.h> 32#include <linux/platform_data/clk-u300.h>
@@ -1553,39 +1552,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
1553 pin_highz_conf), 1552 pin_highz_conf),
1554}; 1553};
1555 1554
1556struct u300_mux_hog {
1557 struct device *dev;
1558 struct pinctrl *p;
1559};
1560
1561static struct u300_mux_hog u300_mux_hogs[] = {
1562 {
1563 .dev = &uart0_device.dev,
1564 },
1565 {
1566 .dev = &mmcsd_device.dev,
1567 },
1568};
1569
1570static int __init u300_pinctrl_fetch(void)
1571{
1572 int i;
1573
1574 for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1575 struct pinctrl *p;
1576
1577 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1578 if (IS_ERR(p)) {
1579 pr_err("u300: could not get pinmux hog for dev %s\n",
1580 dev_name(u300_mux_hogs[i].dev));
1581 continue;
1582 }
1583 u300_mux_hogs[i].p = p;
1584 }
1585 return 0;
1586}
1587subsys_initcall(u300_pinctrl_fetch);
1588
1589/* 1555/*
1590 * Notice that AMBA devices are initialized before platform devices. 1556 * Notice that AMBA devices are initialized before platform devices.
1591 * 1557 *
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 4b24c9992654..a5e05f6e256f 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -8,6 +8,7 @@
8#ifndef __DEVICES_DB8500_H 8#ifndef __DEVICES_DB8500_H
9#define __DEVICES_DB8500_H 9#define __DEVICES_DB8500_H
10 10
11#include <linux/platform_data/usb-musb-ux500.h>
11#include <mach/irqs.h> 12#include <mach/irqs.h>
12#include "devices-common.h" 13#include "devices-common.h"
13 14
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 8d885848600a..9d9aa2f55129 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -11,7 +11,6 @@ obj- :=
11# omap_device support (OMAP2+ only at the moment) 11# omap_device support (OMAP2+ only at the moment)
12 12
13obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 13obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
14obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
15obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 14obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
16i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o 15i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
17obj-y += $(i2c-omap-m) $(i2c-omap-y) 16obj-y += $(i2c-omap-m) $(i2c-omap-y)
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
deleted file mode 100644
index a609e2161817..000000000000
--- a/arch/arm/plat-omap/debug-devices.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/debug-devices.c
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Modified from mach-omap2/board-h4.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/gpio.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/smc91x.h>
17
18#include <plat/debug-devices.h>
19
20/* Many OMAP development platforms reuse the same "debug board"; these
21 * platforms include H2, H3, H4, and Perseus2.
22 */
23
24static struct smc91x_platdata smc91x_info = {
25 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
26 .leda = RPC_LED_100_10,
27 .ledb = RPC_LED_TX_RX,
28};
29
30static struct resource smc91x_resources[] = {
31 [0] = {
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
36 },
37};
38
39static struct platform_device smc91x_device = {
40 .name = "smc91x",
41 .id = -1,
42 .dev = {
43 .platform_data = &smc91x_info,
44 },
45 .num_resources = ARRAY_SIZE(smc91x_resources),
46 .resource = smc91x_resources,
47};
48
49static struct resource led_resources[] = {
50 [0] = {
51 .flags = IORESOURCE_MEM,
52 },
53};
54
55static struct platform_device led_device = {
56 .name = "omap_dbg_led",
57 .id = -1,
58 .num_resources = ARRAY_SIZE(led_resources),
59 .resource = led_resources,
60};
61
62static struct platform_device *debug_devices[] __initdata = {
63 &smc91x_device,
64 &led_device,
65 /* ps2 kbd + mouse ports */
66 /* 4 extra uarts */
67 /* 6 input dip switches */
68 /* 8 output pins */
69};
70
71int __init debug_card_init(u32 addr, unsigned gpio)
72{
73 int status;
74
75 smc91x_resources[0].start = addr + 0x300;
76 smc91x_resources[0].end = addr + 0x30f;
77
78 smc91x_resources[1].start = gpio_to_irq(gpio);
79 smc91x_resources[1].end = gpio_to_irq(gpio);
80
81 status = gpio_request(gpio, "SMC91x irq");
82 if (status < 0) {
83 printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio);
84 return status;
85 }
86 gpio_direction_input(gpio);
87
88 led_resources[0].start = addr;
89 led_resources[0].end = addr + SZ_4K - 1;
90
91 return platform_add_devices(debug_devices, ARRAY_SIZE(debug_devices));
92}
diff --git a/arch/arm/plat-omap/include/plat/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
deleted file mode 100644
index 8fc4287222dd..000000000000
--- a/arch/arm/plat-omap/include/plat/debug-devices.h
+++ /dev/null
@@ -1,2 +0,0 @@
1/* for TI reference platforms sharing the same debug card */
2extern int debug_card_init(u32 addr, unsigned gpio);
diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
index bd5de08ad6fd..0576a7dd32a5 100644
--- a/drivers/amba/tegra-ahb.c
+++ b/drivers/amba/tegra-ahb.c
@@ -157,6 +157,7 @@ int tegra_ahb_enable_smmu(struct device_node *dn)
157EXPORT_SYMBOL(tegra_ahb_enable_smmu); 157EXPORT_SYMBOL(tegra_ahb_enable_smmu);
158#endif 158#endif
159 159
160#ifdef CONFIG_PM_SLEEP
160static int tegra_ahb_suspend(struct device *dev) 161static int tegra_ahb_suspend(struct device *dev)
161{ 162{
162 int i; 163 int i;
@@ -176,6 +177,7 @@ static int tegra_ahb_resume(struct device *dev)
176 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]); 177 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
177 return 0; 178 return 0;
178} 179}
180#endif
179 181
180static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm, 182static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
181 tegra_ahb_suspend, 183 tegra_ahb_suspend,
diff --git a/drivers/base/dma-buf.c b/drivers/base/dma-buf.c
index 460e22dee36d..a3f79c495a41 100644
--- a/drivers/base/dma-buf.c
+++ b/drivers/base/dma-buf.c
@@ -298,6 +298,8 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach,
298 struct sg_table *sg_table, 298 struct sg_table *sg_table,
299 enum dma_data_direction direction) 299 enum dma_data_direction direction)
300{ 300{
301 might_sleep();
302
301 if (WARN_ON(!attach || !attach->dmabuf || !sg_table)) 303 if (WARN_ON(!attach || !attach->dmabuf || !sg_table))
302 return; 304 return;
303 305
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
index 9f26400713f0..89cfd64b3373 100644
--- a/drivers/hwmon/hwmon-vid.c
+++ b/drivers/hwmon/hwmon-vid.c
@@ -115,6 +115,12 @@ int vid_from_reg(int val, u8 vrm)
115 return (val < 32) ? 1550 - 25 * val 115 return (val < 32) ? 1550 - 25 * val
116 : 775 - (25 * (val - 31)) / 2; 116 : 775 - (25 * (val - 31)) / 2;
117 117
118 case 26: /* AMD family 10h to 15h, serial VID */
119 val &= 0x7f;
120 if (val >= 0x7c)
121 return 0;
122 return DIV_ROUND_CLOSEST(15500 - 125 * val, 10);
123
118 case 91: /* VRM 9.1 */ 124 case 91: /* VRM 9.1 */
119 case 90: /* VRM 9.0 */ 125 case 90: /* VRM 9.0 */
120 val &= 0x1f; 126 val &= 0x1f;
@@ -195,6 +201,10 @@ static struct vrm_model vrm_models[] = {
195 {X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24}, /* NPT family 0Fh */ 201 {X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24}, /* NPT family 0Fh */
196 {X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25}, /* future fam. 0Fh */ 202 {X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25}, /* future fam. 0Fh */
197 {X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25}, /* NPT family 10h */ 203 {X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25}, /* NPT family 10h */
204 {X86_VENDOR_AMD, 0x11, 0x0, ANY, ANY, 26}, /* family 11h */
205 {X86_VENDOR_AMD, 0x12, 0x0, ANY, ANY, 26}, /* family 12h */
206 {X86_VENDOR_AMD, 0x14, 0x0, ANY, ANY, 26}, /* family 14h */
207 {X86_VENDOR_AMD, 0x15, 0x0, ANY, ANY, 26}, /* family 15h */
198 208
199 {X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82}, /* Pentium Pro, 209 {X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82}, /* Pentium Pro,
200 * Pentium II, Xeon, 210 * Pentium II, Xeon,
diff --git a/drivers/hwmon/hwmon.c b/drivers/hwmon/hwmon.c
index c3c471ca202f..646314f7c839 100644
--- a/drivers/hwmon/hwmon.c
+++ b/drivers/hwmon/hwmon.c
@@ -84,19 +84,21 @@ static void __init hwmon_pci_quirks(void)
84 84
85 /* Open access to 0x295-0x296 on MSI MS-7031 */ 85 /* Open access to 0x295-0x296 on MSI MS-7031 */
86 sb = pci_get_device(PCI_VENDOR_ID_ATI, 0x436c, NULL); 86 sb = pci_get_device(PCI_VENDOR_ID_ATI, 0x436c, NULL);
87 if (sb && 87 if (sb) {
88 (sb->subsystem_vendor == 0x1462 && /* MSI */ 88 if (sb->subsystem_vendor == 0x1462 && /* MSI */
89 sb->subsystem_device == 0x0031)) { /* MS-7031 */ 89 sb->subsystem_device == 0x0031) { /* MS-7031 */
90 90 pci_read_config_byte(sb, 0x48, &enable);
91 pci_read_config_byte(sb, 0x48, &enable); 91 pci_read_config_word(sb, 0x64, &base);
92 pci_read_config_word(sb, 0x64, &base); 92
93 93 if (base == 0 && !(enable & BIT(2))) {
94 if (base == 0 && !(enable & BIT(2))) { 94 dev_info(&sb->dev,
95 dev_info(&sb->dev, 95 "Opening wide generic port at 0x295\n");
96 "Opening wide generic port at 0x295\n"); 96 pci_write_config_word(sb, 0x64, 0x295);
97 pci_write_config_word(sb, 0x64, 0x295); 97 pci_write_config_byte(sb, 0x48,
98 pci_write_config_byte(sb, 0x48, enable | BIT(2)); 98 enable | BIT(2));
99 }
99 } 100 }
101 pci_dev_put(sb);
100 } 102 }
101#endif 103#endif
102} 104}
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c
index d32aa354cbdf..117d66fcded6 100644
--- a/drivers/hwmon/it87.c
+++ b/drivers/hwmon/it87.c
@@ -203,6 +203,8 @@ static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
203static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 }; 203static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
204static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 }; 204static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
205static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 }; 205static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
206static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
207
206#define IT87_REG_FAN_MAIN_CTRL 0x13 208#define IT87_REG_FAN_MAIN_CTRL 0x13
207#define IT87_REG_FAN_CTL 0x14 209#define IT87_REG_FAN_CTL 0x14
208#define IT87_REG_PWM(nr) (0x15 + (nr)) 210#define IT87_REG_PWM(nr) (0x15 + (nr))
@@ -226,6 +228,83 @@ static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
226#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i)) 228#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
227#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i)) 229#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
228 230
231struct it87_devices {
232 const char *name;
233 u16 features;
234 u8 peci_mask;
235 u8 old_peci_mask;
236};
237
238#define FEAT_12MV_ADC (1 << 0)
239#define FEAT_NEWER_AUTOPWM (1 << 1)
240#define FEAT_OLD_AUTOPWM (1 << 2)
241#define FEAT_16BIT_FANS (1 << 3)
242#define FEAT_TEMP_OFFSET (1 << 4)
243#define FEAT_TEMP_PECI (1 << 5)
244#define FEAT_TEMP_OLD_PECI (1 << 6)
245
246static const struct it87_devices it87_devices[] = {
247 [it87] = {
248 .name = "it87",
249 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
250 },
251 [it8712] = {
252 .name = "it8712",
253 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
254 },
255 [it8716] = {
256 .name = "it8716",
257 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
258 },
259 [it8718] = {
260 .name = "it8718",
261 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
262 | FEAT_TEMP_OLD_PECI,
263 .old_peci_mask = 0x4,
264 },
265 [it8720] = {
266 .name = "it8720",
267 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
268 | FEAT_TEMP_OLD_PECI,
269 .old_peci_mask = 0x4,
270 },
271 [it8721] = {
272 .name = "it8721",
273 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
274 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI,
275 .peci_mask = 0x05,
276 .old_peci_mask = 0x02, /* Actually reports PCH */
277 },
278 [it8728] = {
279 .name = "it8728",
280 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
281 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
282 .peci_mask = 0x07,
283 },
284 [it8782] = {
285 .name = "it8782",
286 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
287 | FEAT_TEMP_OLD_PECI,
288 .old_peci_mask = 0x4,
289 },
290 [it8783] = {
291 .name = "it8783",
292 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
293 | FEAT_TEMP_OLD_PECI,
294 .old_peci_mask = 0x4,
295 },
296};
297
298#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
299#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
300#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
301#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
302#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
303#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
304 ((data)->peci_mask & (1 << nr)))
305#define has_temp_old_peci(data, nr) \
306 (((data)->features & FEAT_TEMP_OLD_PECI) && \
307 ((data)->old_peci_mask & (1 << nr)))
229 308
230struct it87_sio_data { 309struct it87_sio_data {
231 enum chips type; 310 enum chips type;
@@ -249,7 +328,9 @@ struct it87_sio_data {
249struct it87_data { 328struct it87_data {
250 struct device *hwmon_dev; 329 struct device *hwmon_dev;
251 enum chips type; 330 enum chips type;
252 u8 revision; 331 u16 features;
332 u8 peci_mask;
333 u8 old_peci_mask;
253 334
254 unsigned short addr; 335 unsigned short addr;
255 const char *name; 336 const char *name;
@@ -258,17 +339,13 @@ struct it87_data {
258 unsigned long last_updated; /* In jiffies */ 339 unsigned long last_updated; /* In jiffies */
259 340
260 u16 in_scaled; /* Internal voltage sensors are scaled */ 341 u16 in_scaled; /* Internal voltage sensors are scaled */
261 u8 in[9]; /* Register value */ 342 u8 in[9][3]; /* [nr][0]=in, [1]=min, [2]=max */
262 u8 in_max[8]; /* Register value */
263 u8 in_min[8]; /* Register value */
264 u8 has_fan; /* Bitfield, fans enabled */ 343 u8 has_fan; /* Bitfield, fans enabled */
265 u16 fan[5]; /* Register values, possibly combined */ 344 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
266 u16 fan_min[5]; /* Register values, possibly combined */
267 u8 has_temp; /* Bitfield, temp sensors enabled */ 345 u8 has_temp; /* Bitfield, temp sensors enabled */
268 s8 temp[3]; /* Register value */ 346 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
269 s8 temp_high[3]; /* Register value */ 347 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
270 s8 temp_low[3]; /* Register value */ 348 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
271 u8 sensor; /* Register value */
272 u8 fan_div[3]; /* Register encoding, shifted right */ 349 u8 fan_div[3]; /* Register encoding, shifted right */
273 u8 vid; /* Register encoding, combined */ 350 u8 vid; /* Register encoding, combined */
274 u8 vrm; 351 u8 vrm;
@@ -296,26 +373,6 @@ struct it87_data {
296 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */ 373 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
297}; 374};
298 375
299static inline int has_12mv_adc(const struct it87_data *data)
300{
301 /*
302 * IT8721F and later have a 12 mV ADC, also with internal scaling
303 * on selected inputs.
304 */
305 return data->type == it8721
306 || data->type == it8728;
307}
308
309static inline int has_newer_autopwm(const struct it87_data *data)
310{
311 /*
312 * IT8721F and later have separate registers for the temperature
313 * mapping and the manual duty cycle.
314 */
315 return data->type == it8721
316 || data->type == it8728;
317}
318
319static int adc_lsb(const struct it87_data *data, int nr) 376static int adc_lsb(const struct it87_data *data, int nr)
320{ 377{
321 int lsb = has_12mv_adc(data) ? 12 : 16; 378 int lsb = has_12mv_adc(data) ? 12 : 16;
@@ -398,35 +455,6 @@ static const unsigned int pwm_freq[8] = {
398 750000 / 128, 455 750000 / 128,
399}; 456};
400 457
401static inline int has_16bit_fans(const struct it87_data *data)
402{
403 /*
404 * IT8705F Datasheet 0.4.1, 3h == Version G.
405 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
406 * These are the first revisions with 16-bit tachometer support.
407 */
408 return (data->type == it87 && data->revision >= 0x03)
409 || (data->type == it8712 && data->revision >= 0x08)
410 || data->type == it8716
411 || data->type == it8718
412 || data->type == it8720
413 || data->type == it8721
414 || data->type == it8728
415 || data->type == it8782
416 || data->type == it8783;
417}
418
419static inline int has_old_autopwm(const struct it87_data *data)
420{
421 /*
422 * The old automatic fan speed control interface is implemented
423 * by IT8705F chips up to revision F and IT8712F chips up to
424 * revision G.
425 */
426 return (data->type == it87 && data->revision < 0x03)
427 || (data->type == it8712 && data->revision < 0x08);
428}
429
430static int it87_probe(struct platform_device *pdev); 458static int it87_probe(struct platform_device *pdev);
431static int it87_remove(struct platform_device *pdev); 459static int it87_remove(struct platform_device *pdev);
432 460
@@ -447,59 +475,22 @@ static struct platform_driver it87_driver = {
447}; 475};
448 476
449static ssize_t show_in(struct device *dev, struct device_attribute *attr, 477static ssize_t show_in(struct device *dev, struct device_attribute *attr,
450 char *buf) 478 char *buf)
451{
452 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
453 int nr = sensor_attr->index;
454
455 struct it87_data *data = it87_update_device(dev);
456 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr]));
457}
458
459static ssize_t show_in_min(struct device *dev, struct device_attribute *attr,
460 char *buf)
461{ 479{
462 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 480 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
463 int nr = sensor_attr->index; 481 int nr = sattr->nr;
482 int index = sattr->index;
464 483
465 struct it87_data *data = it87_update_device(dev); 484 struct it87_data *data = it87_update_device(dev);
466 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in_min[nr])); 485 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
467} 486}
468 487
469static ssize_t show_in_max(struct device *dev, struct device_attribute *attr, 488static ssize_t set_in(struct device *dev, struct device_attribute *attr,
470 char *buf) 489 const char *buf, size_t count)
471{
472 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
473 int nr = sensor_attr->index;
474
475 struct it87_data *data = it87_update_device(dev);
476 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in_max[nr]));
477}
478
479static ssize_t set_in_min(struct device *dev, struct device_attribute *attr,
480 const char *buf, size_t count)
481{
482 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
483 int nr = sensor_attr->index;
484
485 struct it87_data *data = dev_get_drvdata(dev);
486 unsigned long val;
487
488 if (kstrtoul(buf, 10, &val) < 0)
489 return -EINVAL;
490
491 mutex_lock(&data->update_lock);
492 data->in_min[nr] = in_to_reg(data, nr, val);
493 it87_write_value(data, IT87_REG_VIN_MIN(nr),
494 data->in_min[nr]);
495 mutex_unlock(&data->update_lock);
496 return count;
497}
498static ssize_t set_in_max(struct device *dev, struct device_attribute *attr,
499 const char *buf, size_t count)
500{ 490{
501 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 491 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
502 int nr = sensor_attr->index; 492 int nr = sattr->nr;
493 int index = sattr->index;
503 494
504 struct it87_data *data = dev_get_drvdata(dev); 495 struct it87_data *data = dev_get_drvdata(dev);
505 unsigned long val; 496 unsigned long val;
@@ -508,140 +499,167 @@ static ssize_t set_in_max(struct device *dev, struct device_attribute *attr,
508 return -EINVAL; 499 return -EINVAL;
509 500
510 mutex_lock(&data->update_lock); 501 mutex_lock(&data->update_lock);
511 data->in_max[nr] = in_to_reg(data, nr, val); 502 data->in[nr][index] = in_to_reg(data, nr, val);
512 it87_write_value(data, IT87_REG_VIN_MAX(nr), 503 it87_write_value(data,
513 data->in_max[nr]); 504 index == 1 ? IT87_REG_VIN_MIN(nr)
505 : IT87_REG_VIN_MAX(nr),
506 data->in[nr][index]);
514 mutex_unlock(&data->update_lock); 507 mutex_unlock(&data->update_lock);
515 return count; 508 return count;
516} 509}
517 510
518#define show_in_offset(offset) \ 511static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
519static SENSOR_DEVICE_ATTR(in##offset##_input, S_IRUGO, \ 512static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
520 show_in, NULL, offset); 513 0, 1);
521 514static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
522#define limit_in_offset(offset) \ 515 0, 2);
523static SENSOR_DEVICE_ATTR(in##offset##_min, S_IRUGO | S_IWUSR, \ 516
524 show_in_min, set_in_min, offset); \ 517static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
525static SENSOR_DEVICE_ATTR(in##offset##_max, S_IRUGO | S_IWUSR, \ 518static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
526 show_in_max, set_in_max, offset); 519 1, 1);
527 520static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
528show_in_offset(0); 521 1, 2);
529limit_in_offset(0); 522
530show_in_offset(1); 523static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
531limit_in_offset(1); 524static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
532show_in_offset(2); 525 2, 1);
533limit_in_offset(2); 526static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
534show_in_offset(3); 527 2, 2);
535limit_in_offset(3); 528
536show_in_offset(4); 529static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
537limit_in_offset(4); 530static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
538show_in_offset(5); 531 3, 1);
539limit_in_offset(5); 532static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
540show_in_offset(6); 533 3, 2);
541limit_in_offset(6); 534
542show_in_offset(7); 535static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
543limit_in_offset(7); 536static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
544show_in_offset(8); 537 4, 1);
538static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
539 4, 2);
540
541static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
542static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
543 5, 1);
544static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
545 5, 2);
546
547static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
548static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
549 6, 1);
550static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
551 6, 2);
552
553static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
554static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
555 7, 1);
556static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
557 7, 2);
558
559static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
545 560
546/* 3 temperatures */ 561/* 3 temperatures */
547static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 562static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
548 char *buf) 563 char *buf)
549{ 564{
550 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 565 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
551 int nr = sensor_attr->index; 566 int nr = sattr->nr;
552 567 int index = sattr->index;
553 struct it87_data *data = it87_update_device(dev); 568 struct it87_data *data = it87_update_device(dev);
554 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr]));
555}
556static ssize_t show_temp_max(struct device *dev, struct device_attribute *attr,
557 char *buf)
558{
559 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
560 int nr = sensor_attr->index;
561 569
562 struct it87_data *data = it87_update_device(dev); 570 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
563 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_high[nr]));
564} 571}
565static ssize_t show_temp_min(struct device *dev, struct device_attribute *attr,
566 char *buf)
567{
568 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
569 int nr = sensor_attr->index;
570 572
571 struct it87_data *data = it87_update_device(dev); 573static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
572 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_low[nr])); 574 const char *buf, size_t count)
573}
574static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr,
575 const char *buf, size_t count)
576{ 575{
577 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 576 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
578 int nr = sensor_attr->index; 577 int nr = sattr->nr;
579 578 int index = sattr->index;
580 struct it87_data *data = dev_get_drvdata(dev); 579 struct it87_data *data = dev_get_drvdata(dev);
581 long val; 580 long val;
581 u8 reg, regval;
582 582
583 if (kstrtol(buf, 10, &val) < 0) 583 if (kstrtol(buf, 10, &val) < 0)
584 return -EINVAL; 584 return -EINVAL;
585 585
586 mutex_lock(&data->update_lock); 586 mutex_lock(&data->update_lock);
587 data->temp_high[nr] = TEMP_TO_REG(val);
588 it87_write_value(data, IT87_REG_TEMP_HIGH(nr), data->temp_high[nr]);
589 mutex_unlock(&data->update_lock);
590 return count;
591}
592static ssize_t set_temp_min(struct device *dev, struct device_attribute *attr,
593 const char *buf, size_t count)
594{
595 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
596 int nr = sensor_attr->index;
597 587
598 struct it87_data *data = dev_get_drvdata(dev); 588 switch (index) {
599 long val; 589 default:
600 590 case 1:
601 if (kstrtol(buf, 10, &val) < 0) 591 reg = IT87_REG_TEMP_LOW(nr);
602 return -EINVAL; 592 break;
593 case 2:
594 reg = IT87_REG_TEMP_HIGH(nr);
595 break;
596 case 3:
597 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
598 if (!(regval & 0x80)) {
599 regval |= 0x80;
600 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
601 }
602 data->valid = 0;
603 reg = IT87_REG_TEMP_OFFSET[nr];
604 break;
605 }
603 606
604 mutex_lock(&data->update_lock); 607 data->temp[nr][index] = TEMP_TO_REG(val);
605 data->temp_low[nr] = TEMP_TO_REG(val); 608 it87_write_value(data, reg, data->temp[nr][index]);
606 it87_write_value(data, IT87_REG_TEMP_LOW(nr), data->temp_low[nr]);
607 mutex_unlock(&data->update_lock); 609 mutex_unlock(&data->update_lock);
608 return count; 610 return count;
609} 611}
610#define show_temp_offset(offset) \ 612
611static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, \ 613static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
612 show_temp, NULL, offset - 1); \ 614static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
613static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \ 615 0, 1);
614 show_temp_max, set_temp_max, offset - 1); \ 616static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
615static SENSOR_DEVICE_ATTR(temp##offset##_min, S_IRUGO | S_IWUSR, \ 617 0, 2);
616 show_temp_min, set_temp_min, offset - 1); 618static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
617 619 set_temp, 0, 3);
618show_temp_offset(1); 620static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
619show_temp_offset(2); 621static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
620show_temp_offset(3); 622 1, 1);
621 623static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
622static ssize_t show_sensor(struct device *dev, struct device_attribute *attr, 624 1, 2);
623 char *buf) 625static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
626 set_temp, 1, 3);
627static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
628static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
629 2, 1);
630static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
631 2, 2);
632static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
633 set_temp, 2, 3);
634
635static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
636 char *buf)
624{ 637{
625 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 638 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
626 int nr = sensor_attr->index; 639 int nr = sensor_attr->index;
627 struct it87_data *data = it87_update_device(dev); 640 struct it87_data *data = it87_update_device(dev);
628 u8 reg = data->sensor; /* In case value is updated while used */ 641 u8 reg = data->sensor; /* In case value is updated while used */
642 u8 extra = data->extra;
629 643
644 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
645 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
646 return sprintf(buf, "6\n"); /* Intel PECI */
630 if (reg & (1 << nr)) 647 if (reg & (1 << nr))
631 return sprintf(buf, "3\n"); /* thermal diode */ 648 return sprintf(buf, "3\n"); /* thermal diode */
632 if (reg & (8 << nr)) 649 if (reg & (8 << nr))
633 return sprintf(buf, "4\n"); /* thermistor */ 650 return sprintf(buf, "4\n"); /* thermistor */
634 return sprintf(buf, "0\n"); /* disabled */ 651 return sprintf(buf, "0\n"); /* disabled */
635} 652}
636static ssize_t set_sensor(struct device *dev, struct device_attribute *attr, 653
637 const char *buf, size_t count) 654static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
655 const char *buf, size_t count)
638{ 656{
639 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 657 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
640 int nr = sensor_attr->index; 658 int nr = sensor_attr->index;
641 659
642 struct it87_data *data = dev_get_drvdata(dev); 660 struct it87_data *data = dev_get_drvdata(dev);
643 long val; 661 long val;
644 u8 reg; 662 u8 reg, extra;
645 663
646 if (kstrtol(buf, 10, &val) < 0) 664 if (kstrtol(buf, 10, &val) < 0)
647 return -EINVAL; 665 return -EINVAL;
@@ -649,33 +667,45 @@ static ssize_t set_sensor(struct device *dev, struct device_attribute *attr,
649 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 667 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
650 reg &= ~(1 << nr); 668 reg &= ~(1 << nr);
651 reg &= ~(8 << nr); 669 reg &= ~(8 << nr);
670 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
671 reg &= 0x3f;
672 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
673 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
674 extra &= 0x7f;
652 if (val == 2) { /* backwards compatibility */ 675 if (val == 2) { /* backwards compatibility */
653 dev_warn(dev, "Sensor type 2 is deprecated, please use 4 " 676 dev_warn(dev,
654 "instead\n"); 677 "Sensor type 2 is deprecated, please use 4 instead\n");
655 val = 4; 678 val = 4;
656 } 679 }
657 /* 3 = thermal diode; 4 = thermistor; 0 = disabled */ 680 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
658 if (val == 3) 681 if (val == 3)
659 reg |= 1 << nr; 682 reg |= 1 << nr;
660 else if (val == 4) 683 else if (val == 4)
661 reg |= 8 << nr; 684 reg |= 8 << nr;
685 else if (has_temp_peci(data, nr) && val == 6)
686 reg |= (nr + 1) << 6;
687 else if (has_temp_old_peci(data, nr) && val == 6)
688 extra |= 0x80;
662 else if (val != 0) 689 else if (val != 0)
663 return -EINVAL; 690 return -EINVAL;
664 691
665 mutex_lock(&data->update_lock); 692 mutex_lock(&data->update_lock);
666 data->sensor = reg; 693 data->sensor = reg;
694 data->extra = extra;
667 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); 695 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
696 if (has_temp_old_peci(data, nr))
697 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
668 data->valid = 0; /* Force cache refresh */ 698 data->valid = 0; /* Force cache refresh */
669 mutex_unlock(&data->update_lock); 699 mutex_unlock(&data->update_lock);
670 return count; 700 return count;
671} 701}
672#define show_sensor_offset(offset) \
673static SENSOR_DEVICE_ATTR(temp##offset##_type, S_IRUGO | S_IWUSR, \
674 show_sensor, set_sensor, offset - 1);
675 702
676show_sensor_offset(1); 703static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
677show_sensor_offset(2); 704 set_temp_type, 0);
678show_sensor_offset(3); 705static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
706 set_temp_type, 1);
707static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
708 set_temp_type, 2);
679 709
680/* 3 Fans */ 710/* 3 Fans */
681 711
@@ -692,25 +722,21 @@ static int pwm_mode(const struct it87_data *data, int nr)
692} 722}
693 723
694static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 724static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
695 char *buf) 725 char *buf)
696{ 726{
697 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 727 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
698 int nr = sensor_attr->index; 728 int nr = sattr->nr;
699 729 int index = sattr->index;
730 int speed;
700 struct it87_data *data = it87_update_device(dev); 731 struct it87_data *data = it87_update_device(dev);
701 return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan[nr],
702 DIV_FROM_REG(data->fan_div[nr])));
703}
704static ssize_t show_fan_min(struct device *dev, struct device_attribute *attr,
705 char *buf)
706{
707 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
708 int nr = sensor_attr->index;
709 732
710 struct it87_data *data = it87_update_device(dev); 733 speed = has_16bit_fans(data) ?
711 return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan_min[nr], 734 FAN16_FROM_REG(data->fan[nr][index]) :
712 DIV_FROM_REG(data->fan_div[nr]))); 735 FAN_FROM_REG(data->fan[nr][index],
736 DIV_FROM_REG(data->fan_div[nr]));
737 return sprintf(buf, "%d\n", speed);
713} 738}
739
714static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, 740static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
715 char *buf) 741 char *buf)
716{ 742{
@@ -747,11 +773,13 @@ static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
747 773
748 return sprintf(buf, "%u\n", pwm_freq[index]); 774 return sprintf(buf, "%u\n", pwm_freq[index]);
749} 775}
750static ssize_t set_fan_min(struct device *dev, struct device_attribute *attr, 776
751 const char *buf, size_t count) 777static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
778 const char *buf, size_t count)
752{ 779{
753 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 780 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
754 int nr = sensor_attr->index; 781 int nr = sattr->nr;
782 int index = sattr->index;
755 783
756 struct it87_data *data = dev_get_drvdata(dev); 784 struct it87_data *data = dev_get_drvdata(dev);
757 long val; 785 long val;
@@ -761,24 +789,36 @@ static ssize_t set_fan_min(struct device *dev, struct device_attribute *attr,
761 return -EINVAL; 789 return -EINVAL;
762 790
763 mutex_lock(&data->update_lock); 791 mutex_lock(&data->update_lock);
764 reg = it87_read_value(data, IT87_REG_FAN_DIV); 792
765 switch (nr) { 793 if (has_16bit_fans(data)) {
766 case 0: 794 data->fan[nr][index] = FAN16_TO_REG(val);
767 data->fan_div[nr] = reg & 0x07; 795 it87_write_value(data, IT87_REG_FAN_MIN[nr],
768 break; 796 data->fan[nr][index] & 0xff);
769 case 1: 797 it87_write_value(data, IT87_REG_FANX_MIN[nr],
770 data->fan_div[nr] = (reg >> 3) & 0x07; 798 data->fan[nr][index] >> 8);
771 break; 799 } else {
772 case 2: 800 reg = it87_read_value(data, IT87_REG_FAN_DIV);
773 data->fan_div[nr] = (reg & 0x40) ? 3 : 1; 801 switch (nr) {
774 break; 802 case 0:
803 data->fan_div[nr] = reg & 0x07;
804 break;
805 case 1:
806 data->fan_div[nr] = (reg >> 3) & 0x07;
807 break;
808 case 2:
809 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
810 break;
811 }
812 data->fan[nr][index] =
813 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
814 it87_write_value(data, IT87_REG_FAN_MIN[nr],
815 data->fan[nr][index]);
775 } 816 }
776 817
777 data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
778 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan_min[nr]);
779 mutex_unlock(&data->update_lock); 818 mutex_unlock(&data->update_lock);
780 return count; 819 return count;
781} 820}
821
782static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, 822static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
783 const char *buf, size_t count) 823 const char *buf, size_t count)
784{ 824{
@@ -797,7 +837,7 @@ static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
797 old = it87_read_value(data, IT87_REG_FAN_DIV); 837 old = it87_read_value(data, IT87_REG_FAN_DIV);
798 838
799 /* Save fan min limit */ 839 /* Save fan min limit */
800 min = FAN_FROM_REG(data->fan_min[nr], DIV_FROM_REG(data->fan_div[nr])); 840 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
801 841
802 switch (nr) { 842 switch (nr) {
803 case 0: 843 case 0:
@@ -818,8 +858,8 @@ static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
818 it87_write_value(data, IT87_REG_FAN_DIV, val); 858 it87_write_value(data, IT87_REG_FAN_DIV, val);
819 859
820 /* Restore fan min limit */ 860 /* Restore fan min limit */
821 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); 861 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
822 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan_min[nr]); 862 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
823 863
824 mutex_unlock(&data->update_lock); 864 mutex_unlock(&data->update_lock);
825 return count; 865 return count;
@@ -843,8 +883,8 @@ static int check_trip_points(struct device *dev, int nr)
843 } 883 }
844 884
845 if (err) { 885 if (err) {
846 dev_err(dev, "Inconsistent trip points, not switching to " 886 dev_err(dev,
847 "automatic mode\n"); 887 "Inconsistent trip points, not switching to automatic mode\n");
848 dev_err(dev, "Adjust the trip points and try again\n"); 888 dev_err(dev, "Adjust the trip points and try again\n");
849 } 889 }
850 return err; 890 return err;
@@ -1092,118 +1132,106 @@ static ssize_t set_auto_temp(struct device *dev,
1092 return count; 1132 return count;
1093} 1133}
1094 1134
1095#define show_fan_offset(offset) \ 1135static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1096static SENSOR_DEVICE_ATTR(fan##offset##_input, S_IRUGO, \ 1136static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1097 show_fan, NULL, offset - 1); \ 1137 0, 1);
1098static SENSOR_DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \ 1138static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1099 show_fan_min, set_fan_min, offset - 1); \ 1139 set_fan_div, 0);
1100static SENSOR_DEVICE_ATTR(fan##offset##_div, S_IRUGO | S_IWUSR, \ 1140
1101 show_fan_div, set_fan_div, offset - 1); 1141static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1102 1142static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1103show_fan_offset(1); 1143 1, 1);
1104show_fan_offset(2); 1144static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1105show_fan_offset(3); 1145 set_fan_div, 1);
1106 1146
1107#define show_pwm_offset(offset) \ 1147static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1108static SENSOR_DEVICE_ATTR(pwm##offset##_enable, S_IRUGO | S_IWUSR, \ 1148static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1109 show_pwm_enable, set_pwm_enable, offset - 1); \ 1149 2, 1);
1110static SENSOR_DEVICE_ATTR(pwm##offset, S_IRUGO | S_IWUSR, \ 1150static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1111 show_pwm, set_pwm, offset - 1); \ 1151 set_fan_div, 2);
1112static DEVICE_ATTR(pwm##offset##_freq, \ 1152
1113 (offset == 1 ? S_IRUGO | S_IWUSR : S_IRUGO), \ 1153static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1114 show_pwm_freq, (offset == 1 ? set_pwm_freq : NULL)); \ 1154static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1115static SENSOR_DEVICE_ATTR(pwm##offset##_auto_channels_temp, \ 1155 3, 1);
1116 S_IRUGO | S_IWUSR, show_pwm_temp_map, set_pwm_temp_map, \ 1156
1117 offset - 1); \ 1157static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1118static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point1_pwm, \ 1158static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1119 S_IRUGO | S_IWUSR, show_auto_pwm, set_auto_pwm, \ 1159 4, 1);
1120 offset - 1, 0); \ 1160
1121static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point2_pwm, \ 1161static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1122 S_IRUGO | S_IWUSR, show_auto_pwm, set_auto_pwm, \ 1162 show_pwm_enable, set_pwm_enable, 0);
1123 offset - 1, 1); \ 1163static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1124static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point3_pwm, \ 1164static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1125 S_IRUGO | S_IWUSR, show_auto_pwm, set_auto_pwm, \ 1165static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1126 offset - 1, 2); \ 1166 show_pwm_temp_map, set_pwm_temp_map, 0);
1127static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point4_pwm, \ 1167static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1128 S_IRUGO, show_auto_pwm, NULL, offset - 1, 3); \ 1168 show_auto_pwm, set_auto_pwm, 0, 0);
1129static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point1_temp, \ 1169static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1130 S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ 1170 show_auto_pwm, set_auto_pwm, 0, 1);
1131 offset - 1, 1); \ 1171static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1132static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point1_temp_hyst, \ 1172 show_auto_pwm, set_auto_pwm, 0, 2);
1133 S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ 1173static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1134 offset - 1, 0); \ 1174 show_auto_pwm, NULL, 0, 3);
1135static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point2_temp, \ 1175static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1136 S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ 1176 show_auto_temp, set_auto_temp, 0, 1);
1137 offset - 1, 2); \ 1177static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1138static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point3_temp, \ 1178 show_auto_temp, set_auto_temp, 0, 0);
1139 S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ 1179static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1140 offset - 1, 3); \ 1180 show_auto_temp, set_auto_temp, 0, 2);
1141static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point4_temp, \ 1181static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1142 S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ 1182 show_auto_temp, set_auto_temp, 0, 3);
1143 offset - 1, 4); 1183static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1144 1184 show_auto_temp, set_auto_temp, 0, 4);
1145show_pwm_offset(1); 1185
1146show_pwm_offset(2); 1186static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1147show_pwm_offset(3); 1187 show_pwm_enable, set_pwm_enable, 1);
1148 1188static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1149/* A different set of callbacks for 16-bit fans */ 1189static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1150static ssize_t show_fan16(struct device *dev, struct device_attribute *attr, 1190static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1151 char *buf) 1191 show_pwm_temp_map, set_pwm_temp_map, 1);
1152{ 1192static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1153 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1193 show_auto_pwm, set_auto_pwm, 1, 0);
1154 int nr = sensor_attr->index; 1194static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1155 struct it87_data *data = it87_update_device(dev); 1195 show_auto_pwm, set_auto_pwm, 1, 1);
1156 return sprintf(buf, "%d\n", FAN16_FROM_REG(data->fan[nr])); 1196static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1157} 1197 show_auto_pwm, set_auto_pwm, 1, 2);
1158 1198static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1159static ssize_t show_fan16_min(struct device *dev, struct device_attribute *attr, 1199 show_auto_pwm, NULL, 1, 3);
1160 char *buf) 1200static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1161{ 1201 show_auto_temp, set_auto_temp, 1, 1);
1162 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1202static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1163 int nr = sensor_attr->index; 1203 show_auto_temp, set_auto_temp, 1, 0);
1164 struct it87_data *data = it87_update_device(dev); 1204static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1165 return sprintf(buf, "%d\n", FAN16_FROM_REG(data->fan_min[nr])); 1205 show_auto_temp, set_auto_temp, 1, 2);
1166} 1206static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1167 1207 show_auto_temp, set_auto_temp, 1, 3);
1168static ssize_t set_fan16_min(struct device *dev, struct device_attribute *attr, 1208static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1169 const char *buf, size_t count) 1209 show_auto_temp, set_auto_temp, 1, 4);
1170{ 1210
1171 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1211static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1172 int nr = sensor_attr->index; 1212 show_pwm_enable, set_pwm_enable, 2);
1173 struct it87_data *data = dev_get_drvdata(dev); 1213static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1174 long val; 1214static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1175 1215static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1176 if (kstrtol(buf, 10, &val) < 0) 1216 show_pwm_temp_map, set_pwm_temp_map, 2);
1177 return -EINVAL; 1217static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1178 1218 show_auto_pwm, set_auto_pwm, 2, 0);
1179 mutex_lock(&data->update_lock); 1219static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1180 data->fan_min[nr] = FAN16_TO_REG(val); 1220 show_auto_pwm, set_auto_pwm, 2, 1);
1181 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1221static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1182 data->fan_min[nr] & 0xff); 1222 show_auto_pwm, set_auto_pwm, 2, 2);
1183 it87_write_value(data, IT87_REG_FANX_MIN[nr], 1223static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1184 data->fan_min[nr] >> 8); 1224 show_auto_pwm, NULL, 2, 3);
1185 mutex_unlock(&data->update_lock); 1225static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1186 return count; 1226 show_auto_temp, set_auto_temp, 2, 1);
1187} 1227static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1188 1228 show_auto_temp, set_auto_temp, 2, 0);
1189/* 1229static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1190 * We want to use the same sysfs file names as 8-bit fans, but we need 1230 show_auto_temp, set_auto_temp, 2, 2);
1191 * different variable names, so we have to use SENSOR_ATTR instead of 1231static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1192 * SENSOR_DEVICE_ATTR. 1232 show_auto_temp, set_auto_temp, 2, 3);
1193 */ 1233static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1194#define show_fan16_offset(offset) \ 1234 show_auto_temp, set_auto_temp, 2, 4);
1195static struct sensor_device_attribute sensor_dev_attr_fan##offset##_input16 \
1196 = SENSOR_ATTR(fan##offset##_input, S_IRUGO, \
1197 show_fan16, NULL, offset - 1); \
1198static struct sensor_device_attribute sensor_dev_attr_fan##offset##_min16 \
1199 = SENSOR_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
1200 show_fan16_min, set_fan16_min, offset - 1)
1201
1202show_fan16_offset(1);
1203show_fan16_offset(2);
1204show_fan16_offset(3);
1205show_fan16_offset(4);
1206show_fan16_offset(5);
1207 1235
1208/* Alarms */ 1236/* Alarms */
1209static ssize_t show_alarms(struct device *dev, struct device_attribute *attr, 1237static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
@@ -1471,6 +1499,12 @@ static const struct attribute_group it87_group_temp[3] = {
1471 { .attrs = it87_attributes_temp[2] }, 1499 { .attrs = it87_attributes_temp[2] },
1472}; 1500};
1473 1501
1502static struct attribute *it87_attributes_temp_offset[] = {
1503 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1504 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1505 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1506};
1507
1474static struct attribute *it87_attributes[] = { 1508static struct attribute *it87_attributes[] = {
1475 &dev_attr_alarms.attr, 1509 &dev_attr_alarms.attr,
1476 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, 1510 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
@@ -1500,73 +1534,47 @@ static struct attribute *it87_attributes_temp_beep[] = {
1500 &sensor_dev_attr_temp3_beep.dev_attr.attr, 1534 &sensor_dev_attr_temp3_beep.dev_attr.attr,
1501}; 1535};
1502 1536
1503static struct attribute *it87_attributes_fan16[5][3+1] = { { 1537static struct attribute *it87_attributes_fan[5][3+1] = { {
1504 &sensor_dev_attr_fan1_input16.dev_attr.attr, 1538 &sensor_dev_attr_fan1_input.dev_attr.attr,
1505 &sensor_dev_attr_fan1_min16.dev_attr.attr, 1539 &sensor_dev_attr_fan1_min.dev_attr.attr,
1506 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 1540 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1507 NULL 1541 NULL
1508}, { 1542}, {
1509 &sensor_dev_attr_fan2_input16.dev_attr.attr, 1543 &sensor_dev_attr_fan2_input.dev_attr.attr,
1510 &sensor_dev_attr_fan2_min16.dev_attr.attr, 1544 &sensor_dev_attr_fan2_min.dev_attr.attr,
1511 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 1545 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1512 NULL 1546 NULL
1513}, { 1547}, {
1514 &sensor_dev_attr_fan3_input16.dev_attr.attr, 1548 &sensor_dev_attr_fan3_input.dev_attr.attr,
1515 &sensor_dev_attr_fan3_min16.dev_attr.attr, 1549 &sensor_dev_attr_fan3_min.dev_attr.attr,
1516 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 1550 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1517 NULL 1551 NULL
1518}, { 1552}, {
1519 &sensor_dev_attr_fan4_input16.dev_attr.attr, 1553 &sensor_dev_attr_fan4_input.dev_attr.attr,
1520 &sensor_dev_attr_fan4_min16.dev_attr.attr, 1554 &sensor_dev_attr_fan4_min.dev_attr.attr,
1521 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 1555 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1522 NULL 1556 NULL
1523}, { 1557}, {
1524 &sensor_dev_attr_fan5_input16.dev_attr.attr, 1558 &sensor_dev_attr_fan5_input.dev_attr.attr,
1525 &sensor_dev_attr_fan5_min16.dev_attr.attr, 1559 &sensor_dev_attr_fan5_min.dev_attr.attr,
1526 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 1560 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1527 NULL 1561 NULL
1528} }; 1562} };
1529 1563
1530static const struct attribute_group it87_group_fan16[5] = { 1564static const struct attribute_group it87_group_fan[5] = {
1531 { .attrs = it87_attributes_fan16[0] }, 1565 { .attrs = it87_attributes_fan[0] },
1532 { .attrs = it87_attributes_fan16[1] }, 1566 { .attrs = it87_attributes_fan[1] },
1533 { .attrs = it87_attributes_fan16[2] }, 1567 { .attrs = it87_attributes_fan[2] },
1534 { .attrs = it87_attributes_fan16[3] }, 1568 { .attrs = it87_attributes_fan[3] },
1535 { .attrs = it87_attributes_fan16[4] }, 1569 { .attrs = it87_attributes_fan[4] },
1536}; 1570};
1537 1571
1538static struct attribute *it87_attributes_fan[3][4+1] = { { 1572static const struct attribute *it87_attributes_fan_div[] = {
1539 &sensor_dev_attr_fan1_input.dev_attr.attr,
1540 &sensor_dev_attr_fan1_min.dev_attr.attr,
1541 &sensor_dev_attr_fan1_div.dev_attr.attr, 1573 &sensor_dev_attr_fan1_div.dev_attr.attr,
1542 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1543 NULL
1544}, {
1545 &sensor_dev_attr_fan2_input.dev_attr.attr,
1546 &sensor_dev_attr_fan2_min.dev_attr.attr,
1547 &sensor_dev_attr_fan2_div.dev_attr.attr, 1574 &sensor_dev_attr_fan2_div.dev_attr.attr,
1548 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1549 NULL
1550}, {
1551 &sensor_dev_attr_fan3_input.dev_attr.attr,
1552 &sensor_dev_attr_fan3_min.dev_attr.attr,
1553 &sensor_dev_attr_fan3_div.dev_attr.attr, 1575 &sensor_dev_attr_fan3_div.dev_attr.attr,
1554 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1555 NULL
1556} };
1557
1558static const struct attribute_group it87_group_fan[3] = {
1559 { .attrs = it87_attributes_fan[0] },
1560 { .attrs = it87_attributes_fan[1] },
1561 { .attrs = it87_attributes_fan[2] },
1562}; 1576};
1563 1577
1564static const struct attribute_group *
1565it87_get_fan_group(const struct it87_data *data)
1566{
1567 return has_16bit_fans(data) ? it87_group_fan16 : it87_group_fan;
1568}
1569
1570static struct attribute *it87_attributes_pwm[3][4+1] = { { 1578static struct attribute *it87_attributes_pwm[3][4+1] = { {
1571 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1579 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1572 &sensor_dev_attr_pwm1.dev_attr.attr, 1580 &sensor_dev_attr_pwm1.dev_attr.attr,
@@ -1925,7 +1933,6 @@ static void it87_remove_files(struct device *dev)
1925{ 1933{
1926 struct it87_data *data = platform_get_drvdata(pdev); 1934 struct it87_data *data = platform_get_drvdata(pdev);
1927 struct it87_sio_data *sio_data = dev->platform_data; 1935 struct it87_sio_data *sio_data = dev->platform_data;
1928 const struct attribute_group *fan_group = it87_get_fan_group(data);
1929 int i; 1936 int i;
1930 1937
1931 sysfs_remove_group(&dev->kobj, &it87_group); 1938 sysfs_remove_group(&dev->kobj, &it87_group);
@@ -1941,6 +1948,9 @@ static void it87_remove_files(struct device *dev)
1941 if (!(data->has_temp & (1 << i))) 1948 if (!(data->has_temp & (1 << i)))
1942 continue; 1949 continue;
1943 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]); 1950 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
1951 if (has_temp_offset(data))
1952 sysfs_remove_file(&dev->kobj,
1953 it87_attributes_temp_offset[i]);
1944 if (sio_data->beep_pin) 1954 if (sio_data->beep_pin)
1945 sysfs_remove_file(&dev->kobj, 1955 sysfs_remove_file(&dev->kobj,
1946 it87_attributes_temp_beep[i]); 1956 it87_attributes_temp_beep[i]);
@@ -1948,10 +1958,13 @@ static void it87_remove_files(struct device *dev)
1948 for (i = 0; i < 5; i++) { 1958 for (i = 0; i < 5; i++) {
1949 if (!(data->has_fan & (1 << i))) 1959 if (!(data->has_fan & (1 << i)))
1950 continue; 1960 continue;
1951 sysfs_remove_group(&dev->kobj, &fan_group[i]); 1961 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
1952 if (sio_data->beep_pin) 1962 if (sio_data->beep_pin)
1953 sysfs_remove_file(&dev->kobj, 1963 sysfs_remove_file(&dev->kobj,
1954 it87_attributes_fan_beep[i]); 1964 it87_attributes_fan_beep[i]);
1965 if (i < 3 && !has_16bit_fans(data))
1966 sysfs_remove_file(&dev->kobj,
1967 it87_attributes_fan_div[i]);
1955 } 1968 }
1956 for (i = 0; i < 3; i++) { 1969 for (i = 0; i < 3; i++) {
1957 if (sio_data->skip_pwm & (1 << 0)) 1970 if (sio_data->skip_pwm & (1 << 0))
@@ -1972,21 +1985,9 @@ static int it87_probe(struct platform_device *pdev)
1972 struct resource *res; 1985 struct resource *res;
1973 struct device *dev = &pdev->dev; 1986 struct device *dev = &pdev->dev;
1974 struct it87_sio_data *sio_data = dev->platform_data; 1987 struct it87_sio_data *sio_data = dev->platform_data;
1975 const struct attribute_group *fan_group;
1976 int err = 0, i; 1988 int err = 0, i;
1977 int enable_pwm_interface; 1989 int enable_pwm_interface;
1978 int fan_beep_need_rw; 1990 int fan_beep_need_rw;
1979 static const char * const names[] = {
1980 "it87",
1981 "it8712",
1982 "it8716",
1983 "it8718",
1984 "it8720",
1985 "it8721",
1986 "it8728",
1987 "it8782",
1988 "it8783",
1989 };
1990 1991
1991 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 1992 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1992 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, 1993 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
@@ -2003,8 +2004,31 @@ static int it87_probe(struct platform_device *pdev)
2003 2004
2004 data->addr = res->start; 2005 data->addr = res->start;
2005 data->type = sio_data->type; 2006 data->type = sio_data->type;
2006 data->revision = sio_data->revision; 2007 data->features = it87_devices[sio_data->type].features;
2007 data->name = names[sio_data->type]; 2008 data->peci_mask = it87_devices[sio_data->type].peci_mask;
2009 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
2010 data->name = it87_devices[sio_data->type].name;
2011 /*
2012 * IT8705F Datasheet 0.4.1, 3h == Version G.
2013 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2014 * These are the first revisions with 16-bit tachometer support.
2015 */
2016 switch (data->type) {
2017 case it87:
2018 if (sio_data->revision >= 0x03) {
2019 data->features &= ~FEAT_OLD_AUTOPWM;
2020 data->features |= FEAT_16BIT_FANS;
2021 }
2022 break;
2023 case it8712:
2024 if (sio_data->revision >= 0x08) {
2025 data->features &= ~FEAT_OLD_AUTOPWM;
2026 data->features |= FEAT_16BIT_FANS;
2027 }
2028 break;
2029 default:
2030 break;
2031 }
2008 2032
2009 /* Now, we do the remaining detection. */ 2033 /* Now, we do the remaining detection. */
2010 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) 2034 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
@@ -2068,6 +2092,12 @@ static int it87_probe(struct platform_device *pdev)
2068 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]); 2092 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
2069 if (err) 2093 if (err)
2070 goto error; 2094 goto error;
2095 if (has_temp_offset(data)) {
2096 err = sysfs_create_file(&dev->kobj,
2097 it87_attributes_temp_offset[i]);
2098 if (err)
2099 goto error;
2100 }
2071 if (sio_data->beep_pin) { 2101 if (sio_data->beep_pin) {
2072 err = sysfs_create_file(&dev->kobj, 2102 err = sysfs_create_file(&dev->kobj,
2073 it87_attributes_temp_beep[i]); 2103 it87_attributes_temp_beep[i]);
@@ -2077,15 +2107,21 @@ static int it87_probe(struct platform_device *pdev)
2077 } 2107 }
2078 2108
2079 /* Do not create fan files for disabled fans */ 2109 /* Do not create fan files for disabled fans */
2080 fan_group = it87_get_fan_group(data);
2081 fan_beep_need_rw = 1; 2110 fan_beep_need_rw = 1;
2082 for (i = 0; i < 5; i++) { 2111 for (i = 0; i < 5; i++) {
2083 if (!(data->has_fan & (1 << i))) 2112 if (!(data->has_fan & (1 << i)))
2084 continue; 2113 continue;
2085 err = sysfs_create_group(&dev->kobj, &fan_group[i]); 2114 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
2086 if (err) 2115 if (err)
2087 goto error; 2116 goto error;
2088 2117
2118 if (i < 3 && !has_16bit_fans(data)) {
2119 err = sysfs_create_file(&dev->kobj,
2120 it87_attributes_fan_div[i]);
2121 if (err)
2122 goto error;
2123 }
2124
2089 if (sio_data->beep_pin) { 2125 if (sio_data->beep_pin) {
2090 err = sysfs_create_file(&dev->kobj, 2126 err = sysfs_create_file(&dev->kobj,
2091 it87_attributes_fan_beep[i]); 2127 it87_attributes_fan_beep[i]);
@@ -2221,8 +2257,8 @@ static int it87_check_pwm(struct device *dev)
2221 * PWM interface). 2257 * PWM interface).
2222 */ 2258 */
2223 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { 2259 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2224 dev_info(dev, "Reconfiguring PWM to " 2260 dev_info(dev,
2225 "active high polarity\n"); 2261 "Reconfiguring PWM to active high polarity\n");
2226 it87_write_value(data, IT87_REG_FAN_CTL, 2262 it87_write_value(data, IT87_REG_FAN_CTL,
2227 tmp | 0x87); 2263 tmp | 0x87);
2228 for (i = 0; i < 3; i++) 2264 for (i = 0; i < 3; i++)
@@ -2232,16 +2268,16 @@ static int it87_check_pwm(struct device *dev)
2232 return 1; 2268 return 1;
2233 } 2269 }
2234 2270
2235 dev_info(dev, "PWM configuration is " 2271 dev_info(dev,
2236 "too broken to be fixed\n"); 2272 "PWM configuration is too broken to be fixed\n");
2237 } 2273 }
2238 2274
2239 dev_info(dev, "Detected broken BIOS " 2275 dev_info(dev,
2240 "defaults, disabling PWM interface\n"); 2276 "Detected broken BIOS defaults, disabling PWM interface\n");
2241 return 0; 2277 return 0;
2242 } else if (fix_pwm_polarity) { 2278 } else if (fix_pwm_polarity) {
2243 dev_info(dev, "PWM configuration looks " 2279 dev_info(dev,
2244 "sane, won't touch\n"); 2280 "PWM configuration looks sane, won't touch\n");
2245 } 2281 }
2246 2282
2247 return 1; 2283 return 1;
@@ -2389,42 +2425,46 @@ static struct it87_data *it87_update_device(struct device *dev)
2389 it87_read_value(data, IT87_REG_CONFIG) | 0x40); 2425 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
2390 } 2426 }
2391 for (i = 0; i <= 7; i++) { 2427 for (i = 0; i <= 7; i++) {
2392 data->in[i] = 2428 data->in[i][0] =
2393 it87_read_value(data, IT87_REG_VIN(i)); 2429 it87_read_value(data, IT87_REG_VIN(i));
2394 data->in_min[i] = 2430 data->in[i][1] =
2395 it87_read_value(data, IT87_REG_VIN_MIN(i)); 2431 it87_read_value(data, IT87_REG_VIN_MIN(i));
2396 data->in_max[i] = 2432 data->in[i][2] =
2397 it87_read_value(data, IT87_REG_VIN_MAX(i)); 2433 it87_read_value(data, IT87_REG_VIN_MAX(i));
2398 } 2434 }
2399 /* in8 (battery) has no limit registers */ 2435 /* in8 (battery) has no limit registers */
2400 data->in[8] = it87_read_value(data, IT87_REG_VIN(8)); 2436 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
2401 2437
2402 for (i = 0; i < 5; i++) { 2438 for (i = 0; i < 5; i++) {
2403 /* Skip disabled fans */ 2439 /* Skip disabled fans */
2404 if (!(data->has_fan & (1 << i))) 2440 if (!(data->has_fan & (1 << i)))
2405 continue; 2441 continue;
2406 2442
2407 data->fan_min[i] = 2443 data->fan[i][1] =
2408 it87_read_value(data, IT87_REG_FAN_MIN[i]); 2444 it87_read_value(data, IT87_REG_FAN_MIN[i]);
2409 data->fan[i] = it87_read_value(data, 2445 data->fan[i][0] = it87_read_value(data,
2410 IT87_REG_FAN[i]); 2446 IT87_REG_FAN[i]);
2411 /* Add high byte if in 16-bit mode */ 2447 /* Add high byte if in 16-bit mode */
2412 if (has_16bit_fans(data)) { 2448 if (has_16bit_fans(data)) {
2413 data->fan[i] |= it87_read_value(data, 2449 data->fan[i][0] |= it87_read_value(data,
2414 IT87_REG_FANX[i]) << 8; 2450 IT87_REG_FANX[i]) << 8;
2415 data->fan_min[i] |= it87_read_value(data, 2451 data->fan[i][1] |= it87_read_value(data,
2416 IT87_REG_FANX_MIN[i]) << 8; 2452 IT87_REG_FANX_MIN[i]) << 8;
2417 } 2453 }
2418 } 2454 }
2419 for (i = 0; i < 3; i++) { 2455 for (i = 0; i < 3; i++) {
2420 if (!(data->has_temp & (1 << i))) 2456 if (!(data->has_temp & (1 << i)))
2421 continue; 2457 continue;
2422 data->temp[i] = 2458 data->temp[i][0] =
2423 it87_read_value(data, IT87_REG_TEMP(i)); 2459 it87_read_value(data, IT87_REG_TEMP(i));
2424 data->temp_high[i] = 2460 data->temp[i][1] =
2425 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2426 data->temp_low[i] =
2427 it87_read_value(data, IT87_REG_TEMP_LOW(i)); 2461 it87_read_value(data, IT87_REG_TEMP_LOW(i));
2462 data->temp[i][2] =
2463 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2464 if (has_temp_offset(data))
2465 data->temp[i][3] =
2466 it87_read_value(data,
2467 IT87_REG_TEMP_OFFSET[i]);
2428 } 2468 }
2429 2469
2430 /* Newer chips don't have clock dividers */ 2470 /* Newer chips don't have clock dividers */
@@ -2448,6 +2488,7 @@ static struct it87_data *it87_update_device(struct device *dev)
2448 it87_update_pwm_ctrl(data, i); 2488 it87_update_pwm_ctrl(data, i);
2449 2489
2450 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); 2490 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
2491 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
2451 /* 2492 /*
2452 * The IT8705F does not have VID capability. 2493 * The IT8705F does not have VID capability.
2453 * The IT8718F and later don't use IT87_REG_VID for the 2494 * The IT8718F and later don't use IT87_REG_VID for the
@@ -2549,8 +2590,7 @@ static void __exit sm_it87_exit(void)
2549} 2590}
2550 2591
2551 2592
2552MODULE_AUTHOR("Chris Gauthron, " 2593MODULE_AUTHOR("Chris Gauthron, Jean Delvare <khali@linux-fr.org>");
2553 "Jean Delvare <khali@linux-fr.org>");
2554MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); 2594MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
2555module_param(update_vbat, bool, 0); 2595module_param(update_vbat, bool, 0);
2556MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); 2596MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
diff --git a/drivers/hwmon/w83627ehf.c b/drivers/hwmon/w83627ehf.c
index 55ac41c05561..0e8ffd6059a0 100644
--- a/drivers/hwmon/w83627ehf.c
+++ b/drivers/hwmon/w83627ehf.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * w83627ehf - Driver for the hardware monitoring functionality of 2 * w83627ehf - Driver for the hardware monitoring functionality of
3 * the Winbond W83627EHF Super-I/O chip 3 * the Winbond W83627EHF Super-I/O chip
4 * Copyright (C) 2005-2011 Jean Delvare <khali@linux-fr.org> 4 * Copyright (C) 2005-2012 Jean Delvare <khali@linux-fr.org>
5 * Copyright (C) 2006 Yuan Mu (Winbond), 5 * Copyright (C) 2006 Yuan Mu (Winbond),
6 * Rudolf Marek <r.marek@assembler.cz> 6 * Rudolf Marek <r.marek@assembler.cz>
7 * David Hubbard <david.c.hubbard@gmail.com> 7 * David Hubbard <david.c.hubbard@gmail.com>
@@ -502,6 +502,13 @@ struct w83627ehf_data {
502 u16 have_temp_offset; 502 u16 have_temp_offset;
503 u8 in6_skip:1; 503 u8 in6_skip:1;
504 u8 temp3_val_only:1; 504 u8 temp3_val_only:1;
505
506#ifdef CONFIG_PM
507 /* Remember extra register values over suspend/resume */
508 u8 vbat;
509 u8 fandiv1;
510 u8 fandiv2;
511#endif
505}; 512};
506 513
507struct w83627ehf_sio_data { 514struct w83627ehf_sio_data {
@@ -898,6 +905,8 @@ static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
898 data->temp_max_hyst[i] 905 data->temp_max_hyst[i]
899 = w83627ehf_read_temp(data, 906 = w83627ehf_read_temp(data,
900 data->reg_temp_hyst[i]); 907 data->reg_temp_hyst[i]);
908 if (i > 2)
909 continue;
901 if (data->have_temp_offset & (1 << i)) 910 if (data->have_temp_offset & (1 << i))
902 data->temp_offset[i] 911 data->temp_offset[i]
903 = w83627ehf_read_value(data, 912 = w83627ehf_read_value(data,
@@ -2608,10 +2617,98 @@ static int w83627ehf_remove(struct platform_device *pdev)
2608 return 0; 2617 return 0;
2609} 2618}
2610 2619
2620#ifdef CONFIG_PM
2621static int w83627ehf_suspend(struct device *dev)
2622{
2623 struct w83627ehf_data *data = w83627ehf_update_device(dev);
2624 struct w83627ehf_sio_data *sio_data = dev->platform_data;
2625
2626 mutex_lock(&data->update_lock);
2627 data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
2628 if (sio_data->kind == nct6775) {
2629 data->fandiv1 = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
2630 data->fandiv2 = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
2631 }
2632 mutex_unlock(&data->update_lock);
2633
2634 return 0;
2635}
2636
2637static int w83627ehf_resume(struct device *dev)
2638{
2639 struct w83627ehf_data *data = dev_get_drvdata(dev);
2640 struct w83627ehf_sio_data *sio_data = dev->platform_data;
2641 int i;
2642
2643 mutex_lock(&data->update_lock);
2644 data->bank = 0xff; /* Force initial bank selection */
2645
2646 /* Restore limits */
2647 for (i = 0; i < data->in_num; i++) {
2648 if ((i == 6) && data->in6_skip)
2649 continue;
2650
2651 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
2652 data->in_min[i]);
2653 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2654 data->in_max[i]);
2655 }
2656
2657 for (i = 0; i < 5; i++) {
2658 if (!(data->has_fan_min & (1 << i)))
2659 continue;
2660
2661 w83627ehf_write_value(data, data->REG_FAN_MIN[i],
2662 data->fan_min[i]);
2663 }
2664
2665 for (i = 0; i < NUM_REG_TEMP; i++) {
2666 if (!(data->have_temp & (1 << i)))
2667 continue;
2668
2669 if (data->reg_temp_over[i])
2670 w83627ehf_write_temp(data, data->reg_temp_over[i],
2671 data->temp_max[i]);
2672 if (data->reg_temp_hyst[i])
2673 w83627ehf_write_temp(data, data->reg_temp_hyst[i],
2674 data->temp_max_hyst[i]);
2675 if (i > 2)
2676 continue;
2677 if (data->have_temp_offset & (1 << i))
2678 w83627ehf_write_value(data,
2679 W83627EHF_REG_TEMP_OFFSET[i],
2680 data->temp_offset[i]);
2681 }
2682
2683 /* Restore other settings */
2684 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
2685 if (sio_data->kind == nct6775) {
2686 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
2687 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
2688 }
2689
2690 /* Force re-reading all values */
2691 data->valid = 0;
2692 mutex_unlock(&data->update_lock);
2693
2694 return 0;
2695}
2696
2697static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
2698 .suspend = w83627ehf_suspend,
2699 .resume = w83627ehf_resume,
2700};
2701
2702#define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
2703#else
2704#define W83627EHF_DEV_PM_OPS NULL
2705#endif /* CONFIG_PM */
2706
2611static struct platform_driver w83627ehf_driver = { 2707static struct platform_driver w83627ehf_driver = {
2612 .driver = { 2708 .driver = {
2613 .owner = THIS_MODULE, 2709 .owner = THIS_MODULE,
2614 .name = DRVNAME, 2710 .name = DRVNAME,
2711 .pm = W83627EHF_DEV_PM_OPS,
2615 }, 2712 },
2616 .probe = w83627ehf_probe, 2713 .probe = w83627ehf_probe,
2617 .remove = w83627ehf_remove, 2714 .remove = w83627ehf_remove,
diff --git a/drivers/hwmon/w83627hf.c b/drivers/hwmon/w83627hf.c
index 7f68b8309d10..81f486520cea 100644
--- a/drivers/hwmon/w83627hf.c
+++ b/drivers/hwmon/w83627hf.c
@@ -5,7 +5,7 @@
5 * Philip Edelbrock <phil@netroedge.com>, 5 * Philip Edelbrock <phil@netroedge.com>,
6 * and Mark Studebaker <mdsxyz123@yahoo.com> 6 * and Mark Studebaker <mdsxyz123@yahoo.com>
7 * Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org> 7 * Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org>
8 * Copyright (c) 2007 Jean Delvare <khali@linux-fr.org> 8 * Copyright (c) 2007 - 1012 Jean Delvare <khali@linux-fr.org>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
@@ -389,6 +389,12 @@ struct w83627hf_data {
389 */ 389 */
390 u8 vrm; 390 u8 vrm;
391 u8 vrm_ovt; /* Register value, 627THF/637HF/687THF only */ 391 u8 vrm_ovt; /* Register value, 627THF/637HF/687THF only */
392
393#ifdef CONFIG_PM
394 /* Remember extra register values over suspend/resume */
395 u8 scfg1;
396 u8 scfg2;
397#endif
392}; 398};
393 399
394 400
@@ -401,10 +407,77 @@ static void w83627hf_update_fan_div(struct w83627hf_data *data);
401static struct w83627hf_data *w83627hf_update_device(struct device *dev); 407static struct w83627hf_data *w83627hf_update_device(struct device *dev);
402static void w83627hf_init_device(struct platform_device *pdev); 408static void w83627hf_init_device(struct platform_device *pdev);
403 409
410#ifdef CONFIG_PM
411static int w83627hf_suspend(struct device *dev)
412{
413 struct w83627hf_data *data = w83627hf_update_device(dev);
414
415 mutex_lock(&data->update_lock);
416 data->scfg1 = w83627hf_read_value(data, W83781D_REG_SCFG1);
417 data->scfg2 = w83627hf_read_value(data, W83781D_REG_SCFG2);
418 mutex_unlock(&data->update_lock);
419
420 return 0;
421}
422
423static int w83627hf_resume(struct device *dev)
424{
425 struct w83627hf_data *data = dev_get_drvdata(dev);
426 int i, num_temps = (data->type == w83697hf) ? 2 : 3;
427
428 /* Restore limits */
429 mutex_lock(&data->update_lock);
430 for (i = 0; i <= 8; i++) {
431 /* skip missing sensors */
432 if (((data->type == w83697hf) && (i == 1)) ||
433 ((data->type != w83627hf && data->type != w83697hf)
434 && (i == 5 || i == 6)))
435 continue;
436 w83627hf_write_value(data, W83781D_REG_IN_MAX(i),
437 data->in_max[i]);
438 w83627hf_write_value(data, W83781D_REG_IN_MIN(i),
439 data->in_min[i]);
440 }
441 for (i = 0; i <= 2; i++)
442 w83627hf_write_value(data, W83627HF_REG_FAN_MIN(i),
443 data->fan_min[i]);
444 for (i = 0; i < num_temps; i++) {
445 w83627hf_write_value(data, w83627hf_reg_temp_over[i],
446 data->temp_max[i]);
447 w83627hf_write_value(data, w83627hf_reg_temp_hyst[i],
448 data->temp_max_hyst[i]);
449 }
450
451 /* Fixup BIOS bugs */
452 if (data->type == w83627thf || data->type == w83637hf ||
453 data->type == w83687thf)
454 w83627hf_write_value(data, W83627THF_REG_VRM_OVT_CFG,
455 data->vrm_ovt);
456 w83627hf_write_value(data, W83781D_REG_SCFG1, data->scfg1);
457 w83627hf_write_value(data, W83781D_REG_SCFG2, data->scfg2);
458
459 /* Force re-reading all values */
460 data->valid = 0;
461 mutex_unlock(&data->update_lock);
462
463 return 0;
464}
465
466static const struct dev_pm_ops w83627hf_dev_pm_ops = {
467 .suspend = w83627hf_suspend,
468 .resume = w83627hf_resume,
469};
470
471#define W83627HF_DEV_PM_OPS (&w83627hf_dev_pm_ops)
472#else
473#define W83627HF_DEV_PM_OPS NULL
474#endif /* CONFIG_PM */
475
404static struct platform_driver w83627hf_driver = { 476static struct platform_driver w83627hf_driver = {
405 .driver = { 477 .driver = {
406 .owner = THIS_MODULE, 478 .owner = THIS_MODULE,
407 .name = DRVNAME, 479 .name = DRVNAME,
480 .pm = W83627HF_DEV_PM_OPS,
408 }, 481 },
409 .probe = w83627hf_probe, 482 .probe = w83627hf_probe,
410 .remove = w83627hf_remove, 483 .remove = w83627hf_remove,
@@ -1659,8 +1732,10 @@ static void w83627hf_init_device(struct platform_device *pdev)
1659 /* Minimize conflicts with other winbond i2c-only clients... */ 1732 /* Minimize conflicts with other winbond i2c-only clients... */
1660 /* disable i2c subclients... how to disable main i2c client?? */ 1733 /* disable i2c subclients... how to disable main i2c client?? */
1661 /* force i2c address to relatively uncommon address */ 1734 /* force i2c address to relatively uncommon address */
1662 w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89); 1735 if (type == w83627hf) {
1663 w83627hf_write_value(data, W83781D_REG_I2C_ADDR, force_i2c); 1736 w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89);
1737 w83627hf_write_value(data, W83781D_REG_I2C_ADDR, force_i2c);
1738 }
1664 1739
1665 /* Read VID only once */ 1740 /* Read VID only once */
1666 if (type == w83627hf || type == w83637hf) { 1741 if (type == w83627hf || type == w83637hf) {
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 770a0d01e0b9..05164d7f054b 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -25,7 +25,6 @@
25#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
26#include <linux/spinlock.h> 26#include <linux/spinlock.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <plat/cpu.h>
29#include <linux/platform_device.h> 28#include <linux/platform_device.h>
30#include <linux/platform_data/usb-omap.h> 29#include <linux/platform_data/usb-omap.h>
31#include <linux/pm_runtime.h> 30#include <linux/pm_runtime.h>
@@ -384,7 +383,7 @@ static void omap_usbhs_init(struct device *dev)
384 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; 383 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
385 384
386 /* Bypass the TLL module for PHY mode operation */ 385 /* Bypass the TLL module for PHY mode operation */
387 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { 386 if (pdata->single_ulpi_bypass) {
388 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); 387 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
389 if (is_ehci_phy_mode(pdata->port_mode[0]) || 388 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
390 is_ehci_phy_mode(pdata->port_mode[1]) || 389 is_ehci_phy_mode(pdata->port_mode[1]) ||
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 23f797eb7a28..57d6b29c039c 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -41,8 +41,7 @@
41#include <linux/of.h> 41#include <linux/of.h>
42#include <linux/gpio.h> 42#include <linux/gpio.h>
43#include <linux/pinctrl/consumer.h> 43#include <linux/pinctrl/consumer.h>
44 44#include <linux/platform_data/serial-omap.h>
45#include <plat/omap-serial.h>
46 45
47#define OMAP_MAX_HSUART_PORTS 6 46#define OMAP_MAX_HSUART_PORTS 6
48 47
diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
index eb48f3816df9..bd2e52ccc4f2 100644
--- a/include/linux/dma-buf.h
+++ b/include/linux/dma-buf.h
@@ -156,7 +156,6 @@ static inline void get_dma_buf(struct dma_buf *dmabuf)
156 get_file(dmabuf->file); 156 get_file(dmabuf->file);
157} 157}
158 158
159#ifdef CONFIG_DMA_SHARED_BUFFER
160struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, 159struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
161 struct device *dev); 160 struct device *dev);
162void dma_buf_detach(struct dma_buf *dmabuf, 161void dma_buf_detach(struct dma_buf *dmabuf,
@@ -184,103 +183,5 @@ int dma_buf_mmap(struct dma_buf *, struct vm_area_struct *,
184 unsigned long); 183 unsigned long);
185void *dma_buf_vmap(struct dma_buf *); 184void *dma_buf_vmap(struct dma_buf *);
186void dma_buf_vunmap(struct dma_buf *, void *vaddr); 185void dma_buf_vunmap(struct dma_buf *, void *vaddr);
187#else
188
189static inline struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
190 struct device *dev)
191{
192 return ERR_PTR(-ENODEV);
193}
194
195static inline void dma_buf_detach(struct dma_buf *dmabuf,
196 struct dma_buf_attachment *dmabuf_attach)
197{
198 return;
199}
200
201static inline struct dma_buf *dma_buf_export(void *priv,
202 const struct dma_buf_ops *ops,
203 size_t size, int flags)
204{
205 return ERR_PTR(-ENODEV);
206}
207
208static inline int dma_buf_fd(struct dma_buf *dmabuf, int flags)
209{
210 return -ENODEV;
211}
212
213static inline struct dma_buf *dma_buf_get(int fd)
214{
215 return ERR_PTR(-ENODEV);
216}
217
218static inline void dma_buf_put(struct dma_buf *dmabuf)
219{
220 return;
221}
222
223static inline struct sg_table *dma_buf_map_attachment(
224 struct dma_buf_attachment *attach, enum dma_data_direction write)
225{
226 return ERR_PTR(-ENODEV);
227}
228
229static inline void dma_buf_unmap_attachment(struct dma_buf_attachment *attach,
230 struct sg_table *sg, enum dma_data_direction dir)
231{
232 return;
233}
234
235static inline int dma_buf_begin_cpu_access(struct dma_buf *dmabuf,
236 size_t start, size_t len,
237 enum dma_data_direction dir)
238{
239 return -ENODEV;
240}
241
242static inline void dma_buf_end_cpu_access(struct dma_buf *dmabuf,
243 size_t start, size_t len,
244 enum dma_data_direction dir)
245{
246}
247
248static inline void *dma_buf_kmap_atomic(struct dma_buf *dmabuf,
249 unsigned long pnum)
250{
251 return NULL;
252}
253
254static inline void dma_buf_kunmap_atomic(struct dma_buf *dmabuf,
255 unsigned long pnum, void *vaddr)
256{
257}
258
259static inline void *dma_buf_kmap(struct dma_buf *dmabuf, unsigned long pnum)
260{
261 return NULL;
262}
263
264static inline void dma_buf_kunmap(struct dma_buf *dmabuf,
265 unsigned long pnum, void *vaddr)
266{
267}
268
269static inline int dma_buf_mmap(struct dma_buf *dmabuf,
270 struct vm_area_struct *vma,
271 unsigned long pgoff)
272{
273 return -ENODEV;
274}
275
276static inline void *dma_buf_vmap(struct dma_buf *dmabuf)
277{
278 return NULL;
279}
280
281static inline void dma_buf_vunmap(struct dma_buf *dmabuf, void *vaddr)
282{
283}
284#endif /* CONFIG_DMA_SHARED_BUFFER */
285 186
286#endif /* __DMA_BUF_H__ */ 187#endif /* __DMA_BUF_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/include/linux/platform_data/serial-omap.h
index ff9b0aab5281..ff9b0aab5281 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/include/linux/platform_data/serial-omap.h
diff --git a/include/linux/platform_data/usb-omap.h b/include/linux/platform_data/usb-omap.h
index 8570bcfe6311..ef65b67c56c3 100644
--- a/include/linux/platform_data/usb-omap.h
+++ b/include/linux/platform_data/usb-omap.h
@@ -59,6 +59,9 @@ struct usbhs_omap_platform_data {
59 59
60 struct ehci_hcd_omap_platform_data *ehci_data; 60 struct ehci_hcd_omap_platform_data *ehci_data;
61 struct ohci_hcd_omap_platform_data *ohci_data; 61 struct ohci_hcd_omap_platform_data *ohci_data;
62
63 /* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
64 unsigned single_ulpi_bypass:1;
62}; 65};
63 66
64/*-------------------------------------------------------------------------*/ 67/*-------------------------------------------------------------------------*/
diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h
index 68c31d79c571..aef35e48bc7e 100644
--- a/include/video/omap-panel-tfp410.h
+++ b/include/video/omap-panel-tfp410.h
@@ -28,7 +28,7 @@ struct omap_dss_device;
28 * @power_down_gpio: gpio number for PD pin (or -1 if not available) 28 * @power_down_gpio: gpio number for PD pin (or -1 if not available)
29 */ 29 */
30struct tfp410_platform_data { 30struct tfp410_platform_data {
31 u16 i2c_bus_num; 31 int i2c_bus_num;
32 int power_down_gpio; 32 int power_down_gpio;
33}; 33};
34 34
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 4603d6cb9e25..5eea8707234a 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -793,8 +793,11 @@ unsigned int sysctl_numa_balancing_scan_delay = 1000;
793 793
794static void task_numa_placement(struct task_struct *p) 794static void task_numa_placement(struct task_struct *p)
795{ 795{
796 int seq = ACCESS_ONCE(p->mm->numa_scan_seq); 796 int seq;
797 797
798 if (!p->mm) /* for example, ksmd faulting in a user's mm */
799 return;
800 seq = ACCESS_ONCE(p->mm->numa_scan_seq);
798 if (p->numa_scan_seq == seq) 801 if (p->numa_scan_seq == seq)
799 return; 802 return;
800 p->numa_scan_seq = seq; 803 p->numa_scan_seq = seq;
diff --git a/mm/ksm.c b/mm/ksm.c
index 82dfb4b54321..51573858938d 100644
--- a/mm/ksm.c
+++ b/mm/ksm.c
@@ -1624,7 +1624,7 @@ again:
1624 struct anon_vma_chain *vmac; 1624 struct anon_vma_chain *vmac;
1625 struct vm_area_struct *vma; 1625 struct vm_area_struct *vma;
1626 1626
1627 anon_vma_lock_write(anon_vma); 1627 anon_vma_lock_read(anon_vma);
1628 anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root, 1628 anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root,
1629 0, ULONG_MAX) { 1629 0, ULONG_MAX) {
1630 vma = vmac->vma; 1630 vma = vmac->vma;
@@ -1648,7 +1648,7 @@ again:
1648 if (!search_new_forks || !mapcount) 1648 if (!search_new_forks || !mapcount)
1649 break; 1649 break;
1650 } 1650 }
1651 anon_vma_unlock(anon_vma); 1651 anon_vma_unlock_read(anon_vma);
1652 if (!mapcount) 1652 if (!mapcount)
1653 goto out; 1653 goto out;
1654 } 1654 }
@@ -1678,7 +1678,7 @@ again:
1678 struct anon_vma_chain *vmac; 1678 struct anon_vma_chain *vmac;
1679 struct vm_area_struct *vma; 1679 struct vm_area_struct *vma;
1680 1680
1681 anon_vma_lock_write(anon_vma); 1681 anon_vma_lock_read(anon_vma);
1682 anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root, 1682 anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root,
1683 0, ULONG_MAX) { 1683 0, ULONG_MAX) {
1684 vma = vmac->vma; 1684 vma = vmac->vma;
@@ -1697,11 +1697,11 @@ again:
1697 ret = try_to_unmap_one(page, vma, 1697 ret = try_to_unmap_one(page, vma,
1698 rmap_item->address, flags); 1698 rmap_item->address, flags);
1699 if (ret != SWAP_AGAIN || !page_mapped(page)) { 1699 if (ret != SWAP_AGAIN || !page_mapped(page)) {
1700 anon_vma_unlock(anon_vma); 1700 anon_vma_unlock_read(anon_vma);
1701 goto out; 1701 goto out;
1702 } 1702 }
1703 } 1703 }
1704 anon_vma_unlock(anon_vma); 1704 anon_vma_unlock_read(anon_vma);
1705 } 1705 }
1706 if (!search_new_forks++) 1706 if (!search_new_forks++)
1707 goto again; 1707 goto again;
@@ -1731,7 +1731,7 @@ again:
1731 struct anon_vma_chain *vmac; 1731 struct anon_vma_chain *vmac;
1732 struct vm_area_struct *vma; 1732 struct vm_area_struct *vma;
1733 1733
1734 anon_vma_lock_write(anon_vma); 1734 anon_vma_lock_read(anon_vma);
1735 anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root, 1735 anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root,
1736 0, ULONG_MAX) { 1736 0, ULONG_MAX) {
1737 vma = vmac->vma; 1737 vma = vmac->vma;
@@ -1749,11 +1749,11 @@ again:
1749 1749
1750 ret = rmap_one(page, vma, rmap_item->address, arg); 1750 ret = rmap_one(page, vma, rmap_item->address, arg);
1751 if (ret != SWAP_AGAIN) { 1751 if (ret != SWAP_AGAIN) {
1752 anon_vma_unlock(anon_vma); 1752 anon_vma_unlock_read(anon_vma);
1753 goto out; 1753 goto out;
1754 } 1754 }
1755 } 1755 }
1756 anon_vma_unlock(anon_vma); 1756 anon_vma_unlock_read(anon_vma);
1757 } 1757 }
1758 if (!search_new_forks++) 1758 if (!search_new_forks++)
1759 goto again; 1759 goto again;
diff --git a/mm/vmscan.c b/mm/vmscan.c
index 828530e2794a..adc7e9058181 100644
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -2570,7 +2570,7 @@ static bool prepare_kswapd_sleep(pg_data_t *pgdat, int order, long remaining,
2570static unsigned long balance_pgdat(pg_data_t *pgdat, int order, 2570static unsigned long balance_pgdat(pg_data_t *pgdat, int order,
2571 int *classzone_idx) 2571 int *classzone_idx)
2572{ 2572{
2573 int all_zones_ok; 2573 struct zone *unbalanced_zone;
2574 unsigned long balanced; 2574 unsigned long balanced;
2575 int i; 2575 int i;
2576 int end_zone = 0; /* Inclusive. 0 = ZONE_DMA */ 2576 int end_zone = 0; /* Inclusive. 0 = ZONE_DMA */
@@ -2604,7 +2604,7 @@ loop_again:
2604 unsigned long lru_pages = 0; 2604 unsigned long lru_pages = 0;
2605 int has_under_min_watermark_zone = 0; 2605 int has_under_min_watermark_zone = 0;
2606 2606
2607 all_zones_ok = 1; 2607 unbalanced_zone = NULL;
2608 balanced = 0; 2608 balanced = 0;
2609 2609
2610 /* 2610 /*
@@ -2743,7 +2743,7 @@ loop_again:
2743 } 2743 }
2744 2744
2745 if (!zone_balanced(zone, testorder, 0, end_zone)) { 2745 if (!zone_balanced(zone, testorder, 0, end_zone)) {
2746 all_zones_ok = 0; 2746 unbalanced_zone = zone;
2747 /* 2747 /*
2748 * We are still under min water mark. This 2748 * We are still under min water mark. This
2749 * means that we have a GFP_ATOMIC allocation 2749 * means that we have a GFP_ATOMIC allocation
@@ -2776,7 +2776,7 @@ loop_again:
2776 pfmemalloc_watermark_ok(pgdat)) 2776 pfmemalloc_watermark_ok(pgdat))
2777 wake_up(&pgdat->pfmemalloc_wait); 2777 wake_up(&pgdat->pfmemalloc_wait);
2778 2778
2779 if (all_zones_ok || (order && pgdat_balanced(pgdat, balanced, *classzone_idx))) 2779 if (!unbalanced_zone || (order && pgdat_balanced(pgdat, balanced, *classzone_idx)))
2780 break; /* kswapd: all done */ 2780 break; /* kswapd: all done */
2781 /* 2781 /*
2782 * OK, kswapd is getting into trouble. Take a nap, then take 2782 * OK, kswapd is getting into trouble. Take a nap, then take
@@ -2786,7 +2786,7 @@ loop_again:
2786 if (has_under_min_watermark_zone) 2786 if (has_under_min_watermark_zone)
2787 count_vm_event(KSWAPD_SKIP_CONGESTION_WAIT); 2787 count_vm_event(KSWAPD_SKIP_CONGESTION_WAIT);
2788 else 2788 else
2789 congestion_wait(BLK_RW_ASYNC, HZ/10); 2789 wait_iff_congested(unbalanced_zone, BLK_RW_ASYNC, HZ/10);
2790 } 2790 }
2791 2791
2792 /* 2792 /*
@@ -2805,7 +2805,7 @@ out:
2805 * high-order: Balanced zones must make up at least 25% of the node 2805 * high-order: Balanced zones must make up at least 25% of the node
2806 * for the node to be balanced 2806 * for the node to be balanced
2807 */ 2807 */
2808 if (!(all_zones_ok || (order && pgdat_balanced(pgdat, balanced, *classzone_idx)))) { 2808 if (unbalanced_zone && (!order || !pgdat_balanced(pgdat, balanced, *classzone_idx))) {
2809 cond_resched(); 2809 cond_resched();
2810 2810
2811 try_to_freeze(); 2811 try_to_freeze();
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-10 10:22:47 -0400