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-rw-r--r--Documentation/arm/Samsung/Overview.txt2
-rw-r--r--arch/arm/Kconfig22
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/s5p64x0_defconfig68
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig102
-rw-r--r--arch/arm/mach-s5p64x0/Makefile36
-rw-r--r--arch/arm/mach-s5p64x0/Makefile.boot2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c632
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c701
-rw-r--r--arch/arm/mach-s5p64x0/clock.c236
-rw-r--r--arch/arm/mach-s5p64x0/clock.h38
-rw-r--r--arch/arm/mach-s5p64x0/common.c490
-rw-r--r--arch/arm/mach-s5p64x0/common.h56
-rw-r--r--arch/arm/mach-s5p64x0/dev-audio.c176
-rw-r--r--arch/arm/mach-s5p64x0/dma.c128
-rw-r--r--arch/arm/mach-s5p64x0/i2c.h16
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/debug-macro.S32
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/gpio.h132
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h148
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h96
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/pm-core.h119
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-clock.h98
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h68
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-irq.h18
-rw-r--r--arch/arm/mach-s5p64x0/irq-pm.c98
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c280
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c299
-rw-r--r--arch/arm/mach-s5p64x0/pm.c202
-rw-r--r--arch/arm/mach-s5p64x0/setup-fb-24bpp.c29
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c0.c38
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c1.c38
-rw-r--r--arch/arm/mach-s5p64x0/setup-sdhci-gpio.c104
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c38
-rw-r--r--arch/arm/plat-samsung/Kconfig14
-rw-r--r--arch/arm/plat-samsung/adc.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h19
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h9
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h43
41 files changed, 8 insertions, 4673 deletions
diff --git a/Documentation/arm/Samsung/Overview.txt b/Documentation/arm/Samsung/Overview.txt
index 658abb258cef..66edb1e8101a 100644
--- a/Documentation/arm/Samsung/Overview.txt
+++ b/Documentation/arm/Samsung/Overview.txt
@@ -13,7 +13,6 @@ Introduction
13 13
14 - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list 14 - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list
15 - S3C64XX: S3C6400 and S3C6410 15 - S3C64XX: S3C6400 and S3C6410
16 - S5P6440
17 - S5PC100 16 - S5PC100
18 - S5PC110 / S5PV210 17 - S5PC110 / S5PV210
19 18
@@ -34,7 +33,6 @@ Configuration
34 A number of configurations are supplied, as there is no current way of 33 A number of configurations are supplied, as there is no current way of
35 unifying all the SoCs into one kernel. 34 unifying all the SoCs into one kernel.
36 35
37 s5p6440_defconfig - S5P6440 specific default configuration
38 s5pc100_defconfig - S5PC100 specific default configuration 36 s5pc100_defconfig - S5PC100 specific default configuration
39 s5pc110_defconfig - S5PC110 specific default configuration 37 s5pc110_defconfig - S5PC110 specific default configuration
40 s5pv210_defconfig - S5PV210 specific default configuration 38 s5pv210_defconfig - S5PV210 specific default configuration
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 245058b3b0ef..48be04bb3baf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -758,24 +758,6 @@ config ARCH_S3C64XX
758 help 758 help
759 Samsung S3C64XX series based systems 759 Samsung S3C64XX series based systems
760 760
761config ARCH_S5P64X0
762 bool "Samsung S5P6440 S5P6450"
763 select ATAGS
764 select CLKDEV_LOOKUP
765 select CLKSRC_SAMSUNG_PWM
766 select CPU_V6
767 select GENERIC_CLOCKEVENTS
768 select GPIO_SAMSUNG
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_S3C_RTC if RTC_CLASS
772 select NEED_MACH_GPIO_H
773 select SAMSUNG_ATAGS
774 select SAMSUNG_WDT_RESET
775 help
776 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
777 SMDK6450.
778
779config ARCH_S5PC100 761config ARCH_S5PC100
780 bool "Samsung S5PC100" 762 bool "Samsung S5PC100"
781 select ARCH_REQUIRE_GPIOLIB 763 select ARCH_REQUIRE_GPIOLIB
@@ -1004,8 +986,6 @@ source "arch/arm/mach-s3c24xx/Kconfig"
1004 986
1005source "arch/arm/mach-s3c64xx/Kconfig" 987source "arch/arm/mach-s3c64xx/Kconfig"
1006 988
1007source "arch/arm/mach-s5p64x0/Kconfig"
1008
1009source "arch/arm/mach-s5pc100/Kconfig" 989source "arch/arm/mach-s5pc100/Kconfig"
1010 990
1011source "arch/arm/mach-s5pv210/Kconfig" 991source "arch/arm/mach-s5pv210/Kconfig"
@@ -1569,7 +1549,7 @@ source kernel/Kconfig.preempt
1569 1549
1570config HZ_FIXED 1550config HZ_FIXED
1571 int 1551 int
1572 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1552 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1573 ARCH_S5PV210 || ARCH_EXYNOS4 1553 ARCH_S5PV210 || ARCH_EXYNOS4
1574 default AT91_TIMER_HZ if ARCH_AT91 1554 default AT91_TIMER_HZ if ARCH_AT91
1575 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY 1555 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6721fab13734..826b26289be6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -187,7 +187,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
187machine-$(CONFIG_ARCH_RPC) += rpc 187machine-$(CONFIG_ARCH_RPC) += rpc
188machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx 188machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
189machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx 189machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
190machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0
191machine-$(CONFIG_ARCH_S5PC100) += s5pc100 190machine-$(CONFIG_ARCH_S5PC100) += s5pc100
192machine-$(CONFIG_ARCH_S5PV210) += s5pv210 191machine-$(CONFIG_ARCH_S5PV210) += s5pv210
193machine-$(CONFIG_ARCH_SA1100) += sa1100 192machine-$(CONFIG_ARCH_SA1100) += sa1100
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
deleted file mode 100644
index ad6b61b0bd11..000000000000
--- a/arch/arm/configs/s5p64x0_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSFS_DEPRECATED_V2=y
3CONFIG_BLK_DEV_INITRD=y
4CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5P64X0=y
9CONFIG_S3C_BOOT_ERROR_RESET=y
10CONFIG_S3C_LOWLEVEL_UART_PORT=1
11CONFIG_MACH_SMDK6440=y
12CONFIG_MACH_SMDK6450=y
13CONFIG_NO_HZ=y
14CONFIG_HIGH_RES_TIMERS=y
15CONFIG_CPU_32v6K=y
16CONFIG_AEABI=y
17CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
18CONFIG_FPE_NWFPE=y
19CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
20# CONFIG_PREVENT_FIRMWARE_BUILD is not set
21CONFIG_BLK_DEV_RAM=y
22CONFIG_BLK_DEV_RAM_SIZE=8192
23# CONFIG_MISC_DEVICES is not set
24CONFIG_SCSI=y
25CONFIG_BLK_DEV_SD=y
26CONFIG_CHR_DEV_SG=y
27CONFIG_INPUT_EVDEV=y
28CONFIG_INPUT_TOUCHSCREEN=y
29CONFIG_SERIAL_8250=y
30CONFIG_SERIAL_8250_NR_UARTS=3
31CONFIG_SERIAL_SAMSUNG=y
32CONFIG_SERIAL_SAMSUNG_CONSOLE=y
33CONFIG_HW_RANDOM=y
34# CONFIG_HWMON is not set
35CONFIG_DISPLAY_SUPPORT=y
36# CONFIG_VGA_CONSOLE is not set
37# CONFIG_HID_SUPPORT is not set
38# CONFIG_USB_SUPPORT is not set
39CONFIG_EXT2_FS=y
40CONFIG_EXT3_FS=y
41CONFIG_EXT3_FS_POSIX_ACL=y
42CONFIG_EXT3_FS_SECURITY=y
43CONFIG_INOTIFY=y
44CONFIG_MSDOS_FS=y
45CONFIG_VFAT_FS=y
46CONFIG_TMPFS=y
47CONFIG_TMPFS_POSIX_ACL=y
48CONFIG_CRAMFS=y
49CONFIG_ROMFS_FS=y
50CONFIG_NLS_CODEPAGE_437=y
51CONFIG_NLS_ASCII=y
52CONFIG_NLS_ISO8859_1=y
53CONFIG_MAGIC_SYSRQ=y
54CONFIG_DEBUG_KERNEL=y
55CONFIG_DEBUG_RT_MUTEXES=y
56CONFIG_DEBUG_SPINLOCK=y
57CONFIG_DEBUG_MUTEXES=y
58CONFIG_DEBUG_SPINLOCK_SLEEP=y
59CONFIG_DEBUG_INFO=y
60# CONFIG_RCU_CPU_STALL_DETECTOR is not set
61CONFIG_SYSCTL_SYSCALL_CHECK=y
62CONFIG_DEBUG_USER=y
63CONFIG_DEBUG_ERRORS=y
64CONFIG_DEBUG_LL=y
65CONFIG_DEBUG_S3C_UART=1
66CONFIG_CRYPTO=y
67# CONFIG_CRYPTO_ANSI_CPRNG is not set
68CONFIG_CRC_CCITT=y
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
deleted file mode 100644
index 26003e23796d..000000000000
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ /dev/null
@@ -1,102 +0,0 @@
1# arch/arm/mach-s5p64x0/Kconfig
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P64X0
9
10config CPU_S5P6440
11 bool
12 select ARM_AMBA
13 select PL330_DMA if DMADEVICES
14 select S5P_SLEEP if PM
15 select SAMSUNG_WAKEMASK if PM
16 help
17 Enable S5P6440 CPU support
18
19config CPU_S5P6450
20 bool
21 select ARM_AMBA
22 select PL330_DMA if DMADEVICES
23 select S5P_SLEEP if PM
24 select SAMSUNG_WAKEMASK if PM
25 help
26 Enable S5P6450 CPU support
27
28config S5P64X0_SETUP_FB_24BPP
29 bool
30 help
31 Common setup code for S5P64X0 based boards with a LCD display
32 through RGB interface.
33
34config S5P64X0_SETUP_I2C1
35 bool
36 help
37 Common setup code for i2c bus 1.
38
39config S5P64X0_SETUP_SPI
40 bool
41 help
42 Common setup code for SPI GPIO configurations
43
44config S5P64X0_SETUP_SDHCI_GPIO
45 bool
46 help
47 Common setup code for SDHCI gpio.
48
49# machine support
50
51config MACH_SMDK6440
52 bool "SMDK6440"
53 select CPU_S5P6440
54 select S3C_DEV_FB
55 select S3C_DEV_HSMMC
56 select S3C_DEV_HSMMC1
57 select S3C_DEV_HSMMC2
58 select S3C_DEV_I2C1
59 select S3C_DEV_RTC
60 select S3C_DEV_WDT
61 select S5P64X0_SETUP_FB_24BPP
62 select S5P64X0_SETUP_I2C1
63 select S5P64X0_SETUP_SDHCI_GPIO
64 select SAMSUNG_DEV_ADC
65 select SAMSUNG_DEV_BACKLIGHT
66 select SAMSUNG_DEV_PWM
67 select SAMSUNG_DEV_TS
68 help
69 Machine support for the Samsung SMDK6440
70
71config MACH_SMDK6450
72 bool "SMDK6450"
73 select CPU_S5P6450
74 select S3C_DEV_FB
75 select S3C_DEV_HSMMC
76 select S3C_DEV_HSMMC1
77 select S3C_DEV_HSMMC2
78 select S3C_DEV_I2C1
79 select S3C_DEV_RTC
80 select S3C_DEV_WDT
81 select S5P64X0_SETUP_FB_24BPP
82 select S5P64X0_SETUP_I2C1
83 select S5P64X0_SETUP_SDHCI_GPIO
84 select SAMSUNG_DEV_ADC
85 select SAMSUNG_DEV_BACKLIGHT
86 select SAMSUNG_DEV_PWM
87 select SAMSUNG_DEV_TS
88 help
89 Machine support for the Samsung SMDK6450
90
91menu "Use 8-bit SDHCI bus width"
92
93config S5P64X0_SD_CH1_8BIT
94 bool "SDHCI Channel 1 (Slot 1)"
95 depends on MACH_SMDK6450 || MACH_SMDK6440
96 help
97 Support SDHCI Channel 1 8-bit bus.
98 If selected, Channel 2 is disabled.
99
100endmenu
101
102endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
deleted file mode 100644
index 12bb951187a4..000000000000
--- a/arch/arm/mach-s5p64x0/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
1# arch/arm/mach-s5p64x0/Makefile
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core
14
15obj-y += common.o clock.o
16obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
17obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
18
19obj-$(CONFIG_PM) += pm.o irq-pm.o
20
21obj-y += dma.o
22
23# machine support
24
25obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
26obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
27
28# device support
29
30obj-y += dev-audio.o
31
32obj-y += setup-i2c0.o
33obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
34obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
35obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
36obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5p64x0/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
deleted file mode 100644
index ae34a1d5e10a..000000000000
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ /dev/null
@@ -1,632 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33
34#include "clock.h"
35#include "common.h"
36
37static u32 epll_div[][5] = {
38 { 36000000, 0, 48, 1, 4 },
39 { 48000000, 0, 32, 1, 3 },
40 { 60000000, 0, 40, 1, 3 },
41 { 72000000, 0, 48, 1, 3 },
42 { 84000000, 0, 28, 1, 2 },
43 { 96000000, 0, 32, 1, 2 },
44 { 32768000, 45264, 43, 1, 4 },
45 { 45158000, 6903, 30, 1, 3 },
46 { 49152000, 50332, 32, 1, 3 },
47 { 67738000, 10398, 45, 1, 3 },
48 { 73728000, 9961, 49, 1, 3 }
49};
50
51static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
52{
53 unsigned int epll_con, epll_con_k;
54 unsigned int i;
55
56 if (clk->rate == rate) /* Return if nothing changed */
57 return 0;
58
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
71 break;
72 }
73 }
74
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
77 return -EINVAL;
78 }
79
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
84 clk->rate, rate);
85
86 clk->rate = rate;
87
88 return 0;
89}
90
91static struct clk_ops s5p6440_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6440_epll_set_rate,
94};
95
96static struct clksrc_clk clk_hclk = {
97 .clk = {
98 .name = "clk_hclk",
99 .parent = &clk_armclk.clk,
100 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
102};
103
104static struct clksrc_clk clk_pclk = {
105 .clk = {
106 .name = "clk_pclk",
107 .parent = &clk_hclk.clk,
108 },
109 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
110};
111static struct clksrc_clk clk_hclk_low = {
112 .clk = {
113 .name = "clk_hclk_low",
114 },
115 .sources = &clkset_hclk_low,
116 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
117 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
118};
119
120static struct clksrc_clk clk_pclk_low = {
121 .clk = {
122 .name = "clk_pclk_low",
123 .parent = &clk_hclk_low.clk,
124 },
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
126};
127
128/*
129 * The following clocks will be disabled during clock initialization. It is
130 * recommended to keep the following clocks disabled until the driver requests
131 * for enabling the clock.
132 */
133static struct clk init_clocks_off[] = {
134 {
135 .name = "nand",
136 .parent = &clk_hclk.clk,
137 .enable = s5p64x0_mem_ctrl,
138 .ctrlbit = (1 << 2),
139 }, {
140 .name = "post",
141 .parent = &clk_hclk_low.clk,
142 .enable = s5p64x0_hclk0_ctrl,
143 .ctrlbit = (1 << 5)
144 }, {
145 .name = "2d",
146 .parent = &clk_hclk.clk,
147 .enable = s5p64x0_hclk0_ctrl,
148 .ctrlbit = (1 << 8),
149 }, {
150 .name = "dma",
151 .devname = "dma-pl330",
152 .parent = &clk_hclk_low.clk,
153 .enable = s5p64x0_hclk0_ctrl,
154 .ctrlbit = (1 << 12),
155 }, {
156 .name = "hsmmc",
157 .devname = "s3c-sdhci.0",
158 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 17),
161 }, {
162 .name = "hsmmc",
163 .devname = "s3c-sdhci.1",
164 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 18),
167 }, {
168 .name = "hsmmc",
169 .devname = "s3c-sdhci.2",
170 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 19),
173 }, {
174 .name = "otg",
175 .parent = &clk_hclk_low.clk,
176 .enable = s5p64x0_hclk0_ctrl,
177 .ctrlbit = (1 << 20)
178 }, {
179 .name = "irom",
180 .parent = &clk_hclk.clk,
181 .enable = s5p64x0_hclk0_ctrl,
182 .ctrlbit = (1 << 25),
183 }, {
184 .name = "lcd",
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk1_ctrl,
187 .ctrlbit = (1 << 1),
188 }, {
189 .name = "hclk_fimgvg",
190 .parent = &clk_hclk.clk,
191 .enable = s5p64x0_hclk1_ctrl,
192 .ctrlbit = (1 << 2),
193 }, {
194 .name = "tsi",
195 .parent = &clk_hclk_low.clk,
196 .enable = s5p64x0_hclk1_ctrl,
197 .ctrlbit = (1 << 0),
198 }, {
199 .name = "watchdog",
200 .parent = &clk_pclk_low.clk,
201 .enable = s5p64x0_pclk_ctrl,
202 .ctrlbit = (1 << 5),
203 }, {
204 .name = "rtc",
205 .parent = &clk_pclk_low.clk,
206 .enable = s5p64x0_pclk_ctrl,
207 .ctrlbit = (1 << 6),
208 }, {
209 .name = "timers",
210 .parent = &clk_pclk_low.clk,
211 .enable = s5p64x0_pclk_ctrl,
212 .ctrlbit = (1 << 7),
213 }, {
214 .name = "pcm",
215 .parent = &clk_pclk_low.clk,
216 .enable = s5p64x0_pclk_ctrl,
217 .ctrlbit = (1 << 8),
218 }, {
219 .name = "adc",
220 .parent = &clk_pclk_low.clk,
221 .enable = s5p64x0_pclk_ctrl,
222 .ctrlbit = (1 << 12),
223 }, {
224 .name = "i2c",
225 .parent = &clk_pclk_low.clk,
226 .enable = s5p64x0_pclk_ctrl,
227 .ctrlbit = (1 << 17),
228 }, {
229 .name = "spi",
230 .devname = "s5p64x0-spi.0",
231 .parent = &clk_pclk_low.clk,
232 .enable = s5p64x0_pclk_ctrl,
233 .ctrlbit = (1 << 21),
234 }, {
235 .name = "spi",
236 .devname = "s5p64x0-spi.1",
237 .parent = &clk_pclk_low.clk,
238 .enable = s5p64x0_pclk_ctrl,
239 .ctrlbit = (1 << 22),
240 }, {
241 .name = "gps",
242 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 25),
245 }, {
246 .name = "dsim",
247 .parent = &clk_pclk_low.clk,
248 .enable = s5p64x0_pclk_ctrl,
249 .ctrlbit = (1 << 28),
250 }, {
251 .name = "etm",
252 .parent = &clk_pclk.clk,
253 .enable = s5p64x0_pclk_ctrl,
254 .ctrlbit = (1 << 29),
255 }, {
256 .name = "dmc0",
257 .parent = &clk_pclk.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 30),
260 }, {
261 .name = "pclk_fimgvg",
262 .parent = &clk_pclk.clk,
263 .enable = s5p64x0_pclk_ctrl,
264 .ctrlbit = (1 << 31),
265 }, {
266 .name = "mmc_48m",
267 .devname = "s3c-sdhci.0",
268 .parent = &clk_48m,
269 .enable = s5p64x0_sclk_ctrl,
270 .ctrlbit = (1 << 27),
271 }, {
272 .name = "mmc_48m",
273 .devname = "s3c-sdhci.1",
274 .parent = &clk_48m,
275 .enable = s5p64x0_sclk_ctrl,
276 .ctrlbit = (1 << 28),
277 }, {
278 .name = "mmc_48m",
279 .devname = "s3c-sdhci.2",
280 .parent = &clk_48m,
281 .enable = s5p64x0_sclk_ctrl,
282 .ctrlbit = (1 << 29),
283 },
284};
285
286/*
287 * The following clocks will be enabled during clock initialization.
288 */
289static struct clk init_clocks[] = {
290 {
291 .name = "intc",
292 .parent = &clk_hclk.clk,
293 .enable = s5p64x0_hclk0_ctrl,
294 .ctrlbit = (1 << 1),
295 }, {
296 .name = "mem",
297 .parent = &clk_hclk.clk,
298 .enable = s5p64x0_hclk0_ctrl,
299 .ctrlbit = (1 << 21),
300 }, {
301 .name = "uart",
302 .devname = "s3c6400-uart.0",
303 .parent = &clk_pclk_low.clk,
304 .enable = s5p64x0_pclk_ctrl,
305 .ctrlbit = (1 << 1),
306 }, {
307 .name = "uart",
308 .devname = "s3c6400-uart.1",
309 .parent = &clk_pclk_low.clk,
310 .enable = s5p64x0_pclk_ctrl,
311 .ctrlbit = (1 << 2),
312 }, {
313 .name = "uart",
314 .devname = "s3c6400-uart.2",
315 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl,
317 .ctrlbit = (1 << 3),
318 }, {
319 .name = "uart",
320 .devname = "s3c6400-uart.3",
321 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl,
323 .ctrlbit = (1 << 4),
324 }, {
325 .name = "gpio",
326 .parent = &clk_pclk_low.clk,
327 .enable = s5p64x0_pclk_ctrl,
328 .ctrlbit = (1 << 18),
329 },
330};
331
332static struct clk clk_iis_cd_v40 = {
333 .name = "iis_cdclk_v40",
334};
335
336static struct clk clk_pcm_cd = {
337 .name = "pcm_cdclk",
338};
339
340static struct clk *clkset_group1_list[] = {
341 &clk_mout_epll.clk,
342 &clk_dout_mpll.clk,
343 &clk_fin_epll,
344};
345
346static struct clksrc_sources clkset_group1 = {
347 .sources = clkset_group1_list,
348 .nr_sources = ARRAY_SIZE(clkset_group1_list),
349};
350
351static struct clk *clkset_uart_list[] = {
352 &clk_mout_epll.clk,
353 &clk_dout_mpll.clk,
354};
355
356static struct clksrc_sources clkset_uart = {
357 .sources = clkset_uart_list,
358 .nr_sources = ARRAY_SIZE(clkset_uart_list),
359};
360
361static struct clk *clkset_audio_list[] = {
362 &clk_mout_epll.clk,
363 &clk_dout_mpll.clk,
364 &clk_fin_epll,
365 &clk_iis_cd_v40,
366 &clk_pcm_cd,
367};
368
369static struct clksrc_sources clkset_audio = {
370 .sources = clkset_audio_list,
371 .nr_sources = ARRAY_SIZE(clkset_audio_list),
372};
373
374static struct clksrc_clk clksrcs[] = {
375 {
376 .clk = {
377 .name = "sclk_post",
378 .ctrlbit = (1 << 10),
379 .enable = s5p64x0_sclk_ctrl,
380 },
381 .sources = &clkset_group1,
382 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
383 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
384 }, {
385 .clk = {
386 .name = "sclk_dispcon",
387 .ctrlbit = (1 << 1),
388 .enable = s5p64x0_sclk1_ctrl,
389 },
390 .sources = &clkset_group1,
391 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
392 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
393 }, {
394 .clk = {
395 .name = "sclk_fimgvg",
396 .ctrlbit = (1 << 2),
397 .enable = s5p64x0_sclk1_ctrl,
398 },
399 .sources = &clkset_group1,
400 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
401 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
402 },
403};
404
405static struct clksrc_clk clk_sclk_mmc0 = {
406 .clk = {
407 .name = "sclk_mmc",
408 .devname = "s3c-sdhci.0",
409 .ctrlbit = (1 << 24),
410 .enable = s5p64x0_sclk_ctrl,
411 },
412 .sources = &clkset_group1,
413 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
414 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
415};
416
417static struct clksrc_clk clk_sclk_mmc1 = {
418 .clk = {
419 .name = "sclk_mmc",
420 .devname = "s3c-sdhci.1",
421 .ctrlbit = (1 << 25),
422 .enable = s5p64x0_sclk_ctrl,
423 },
424 .sources = &clkset_group1,
425 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
426 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
427};
428
429static struct clksrc_clk clk_sclk_mmc2 = {
430 .clk = {
431 .name = "sclk_mmc",
432 .devname = "s3c-sdhci.2",
433 .ctrlbit = (1 << 26),
434 .enable = s5p64x0_sclk_ctrl,
435 },
436 .sources = &clkset_group1,
437 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
438 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
439};
440
441static struct clksrc_clk clk_sclk_uclk = {
442 .clk = {
443 .name = "uclk1",
444 .ctrlbit = (1 << 5),
445 .enable = s5p64x0_sclk_ctrl,
446 },
447 .sources = &clkset_uart,
448 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
449 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
450};
451
452static struct clk clk_i2s0 = {
453 .name = "iis",
454 .devname = "samsung-i2s.0",
455 .parent = &clk_pclk_low.clk,
456 .enable = s5p64x0_pclk_ctrl,
457 .ctrlbit = (1 << 26),
458};
459
460static struct clksrc_clk clk_audio_bus2 = {
461 .clk = {
462 .name = "sclk_audio2",
463 .devname = "samsung-i2s.0",
464 .ctrlbit = (1 << 11),
465 .enable = s5p64x0_sclk_ctrl,
466 },
467 .sources = &clkset_audio,
468 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
470};
471
472static struct clksrc_clk clk_sclk_spi0 = {
473 .clk = {
474 .name = "sclk_spi",
475 .devname = "s5p64x0-spi.0",
476 .ctrlbit = (1 << 20),
477 .enable = s5p64x0_sclk_ctrl,
478 },
479 .sources = &clkset_group1,
480 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
481 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
482};
483
484static struct clksrc_clk clk_sclk_spi1 = {
485 .clk = {
486 .name = "sclk_spi",
487 .devname = "s5p64x0-spi.1",
488 .ctrlbit = (1 << 21),
489 .enable = s5p64x0_sclk_ctrl,
490 },
491 .sources = &clkset_group1,
492 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
493 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
494};
495
496/* Clock initialization code */
497static struct clksrc_clk *sysclks[] = {
498 &clk_mout_apll,
499 &clk_mout_epll,
500 &clk_mout_mpll,
501 &clk_dout_mpll,
502 &clk_armclk,
503 &clk_hclk,
504 &clk_pclk,
505 &clk_hclk_low,
506 &clk_pclk_low,
507};
508
509static struct clk dummy_apb_pclk = {
510 .name = "apb_pclk",
511 .id = -1,
512};
513
514static struct clk *clk_cdev[] = {
515 &clk_i2s0,
516};
517
518static struct clksrc_clk *clksrc_cdev[] = {
519 &clk_sclk_uclk,
520 &clk_sclk_spi0,
521 &clk_sclk_spi1,
522 &clk_sclk_mmc0,
523 &clk_sclk_mmc1,
524 &clk_sclk_mmc2,
525 &clk_audio_bus2,
526};
527
528static struct clk_lookup s5p6440_clk_lookup[] = {
529 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
530 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
531 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
532 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
533 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
534 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
535 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
536 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
537 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
538 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus2.clk),
539};
540
541void __init_or_cpufreq s5p6440_setup_clocks(void)
542{
543 struct clk *xtal_clk;
544
545 unsigned long xtal;
546 unsigned long fclk;
547 unsigned long hclk;
548 unsigned long hclk_low;
549 unsigned long pclk;
550 unsigned long pclk_low;
551
552 unsigned long apll;
553 unsigned long mpll;
554 unsigned long epll;
555 unsigned int ptr;
556
557 /* Set S5P6440 functions for clk_fout_epll */
558
559 clk_fout_epll.enable = s5p_epll_enable;
560 clk_fout_epll.ops = &s5p6440_epll_ops;
561
562 clk_48m.enable = s5p64x0_clk48m_ctrl;
563
564 xtal_clk = clk_get(NULL, "ext_xtal");
565 BUG_ON(IS_ERR(xtal_clk));
566
567 xtal = clk_get_rate(xtal_clk);
568 clk_put(xtal_clk);
569
570 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
571 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
572 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
573 __raw_readl(S5P64X0_EPLL_CON_K));
574
575 clk_fout_apll.rate = apll;
576 clk_fout_mpll.rate = mpll;
577 clk_fout_epll.rate = epll;
578
579 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
580 " E=%ld.%ldMHz\n",
581 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
582
583 fclk = clk_get_rate(&clk_armclk.clk);
584 hclk = clk_get_rate(&clk_hclk.clk);
585 pclk = clk_get_rate(&clk_pclk.clk);
586 hclk_low = clk_get_rate(&clk_hclk_low.clk);
587 pclk_low = clk_get_rate(&clk_pclk_low.clk);
588
589 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
590 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
591 print_mhz(hclk), print_mhz(hclk_low),
592 print_mhz(pclk), print_mhz(pclk_low));
593
594 clk_f.rate = fclk;
595 clk_h.rate = hclk;
596 clk_p.rate = pclk;
597
598 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
599 s3c_set_clksrc(&clksrcs[ptr], true);
600}
601
602static struct clk *clks[] __initdata = {
603 &clk_ext,
604 &clk_iis_cd_v40,
605 &clk_pcm_cd,
606};
607
608void __init s5p6440_register_clocks(void)
609{
610 int ptr;
611 unsigned int cnt;
612
613 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
614
615 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
616 s3c_register_clksrc(sysclks[ptr], 1);
617
618 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
619 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
620 s3c_disable_clocks(clk_cdev[cnt], 1);
621
622 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
623 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
624 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
625 s3c_register_clksrc(clksrc_cdev[ptr], 1);
626
627 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
628 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
629 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
630
631 s3c24xx_register_clock(&dummy_apb_pclk);
632}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
deleted file mode 100644
index 0b3ca2ed53e9..000000000000
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ /dev/null
@@ -1,701 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6450 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33
34#include "clock.h"
35#include "common.h"
36
37static struct clksrc_clk clk_mout_dpll = {
38 .clk = {
39 .name = "mout_dpll",
40 },
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
43};
44
45static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
49};
50
51static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
52{
53 unsigned int epll_con, epll_con_k;
54 unsigned int i;
55
56 if (clk->rate == rate) /* Return if nothing changed */
57 return 0;
58
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
71 break;
72 }
73 }
74
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
77 return -EINVAL;
78 }
79
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
84 clk->rate, rate);
85
86 clk->rate = rate;
87
88 return 0;
89}
90
91static struct clk_ops s5p6450_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6450_epll_set_rate,
94};
95
96static struct clksrc_clk clk_dout_epll = {
97 .clk = {
98 .name = "dout_epll",
99 .parent = &clk_mout_epll.clk,
100 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
102};
103
104static struct clksrc_clk clk_mout_hclk_sel = {
105 .clk = {
106 .name = "mout_hclk_sel",
107 },
108 .sources = &clkset_hclk_low,
109 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
110};
111
112static struct clk *clkset_hclk_list[] = {
113 &clk_mout_hclk_sel.clk,
114 &clk_armclk.clk,
115};
116
117static struct clksrc_sources clkset_hclk = {
118 .sources = clkset_hclk_list,
119 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
120};
121
122static struct clksrc_clk clk_hclk = {
123 .clk = {
124 .name = "clk_hclk",
125 },
126 .sources = &clkset_hclk,
127 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
129};
130
131static struct clksrc_clk clk_pclk = {
132 .clk = {
133 .name = "clk_pclk",
134 .parent = &clk_hclk.clk,
135 },
136 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
137};
138static struct clksrc_clk clk_dout_pwm_ratio0 = {
139 .clk = {
140 .name = "clk_dout_pwm_ratio0",
141 .parent = &clk_mout_hclk_sel.clk,
142 },
143 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
144};
145
146static struct clksrc_clk clk_pclk_to_wdt_pwm = {
147 .clk = {
148 .name = "clk_pclk_to_wdt_pwm",
149 .parent = &clk_dout_pwm_ratio0.clk,
150 },
151 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
152};
153
154static struct clksrc_clk clk_hclk_low = {
155 .clk = {
156 .name = "clk_hclk_low",
157 },
158 .sources = &clkset_hclk_low,
159 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
160 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
161};
162
163static struct clksrc_clk clk_pclk_low = {
164 .clk = {
165 .name = "clk_pclk_low",
166 .parent = &clk_hclk_low.clk,
167 },
168 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
169};
170
171/*
172 * The following clocks will be disabled during clock initialization. It is
173 * recommended to keep the following clocks disabled until the driver requests
174 * for enabling the clock.
175 */
176static struct clk init_clocks_off[] = {
177 {
178 .name = "usbhost",
179 .parent = &clk_hclk_low.clk,
180 .enable = s5p64x0_hclk0_ctrl,
181 .ctrlbit = (1 << 3),
182 }, {
183 .name = "dma",
184 .devname = "dma-pl330",
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk0_ctrl,
187 .ctrlbit = (1 << 12),
188 }, {
189 .name = "hsmmc",
190 .devname = "s3c-sdhci.0",
191 .parent = &clk_hclk_low.clk,
192 .enable = s5p64x0_hclk0_ctrl,
193 .ctrlbit = (1 << 17),
194 }, {
195 .name = "hsmmc",
196 .devname = "s3c-sdhci.1",
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk0_ctrl,
199 .ctrlbit = (1 << 18),
200 }, {
201 .name = "hsmmc",
202 .devname = "s3c-sdhci.2",
203 .parent = &clk_hclk_low.clk,
204 .enable = s5p64x0_hclk0_ctrl,
205 .ctrlbit = (1 << 19),
206 }, {
207 .name = "usbotg",
208 .parent = &clk_hclk_low.clk,
209 .enable = s5p64x0_hclk0_ctrl,
210 .ctrlbit = (1 << 20),
211 }, {
212 .name = "lcd",
213 .parent = &clk_h,
214 .enable = s5p64x0_hclk1_ctrl,
215 .ctrlbit = (1 << 1),
216 }, {
217 .name = "watchdog",
218 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl,
220 .ctrlbit = (1 << 5),
221 }, {
222 .name = "rtc",
223 .parent = &clk_pclk_low.clk,
224 .enable = s5p64x0_pclk_ctrl,
225 .ctrlbit = (1 << 6),
226 }, {
227 .name = "adc",
228 .parent = &clk_pclk_low.clk,
229 .enable = s5p64x0_pclk_ctrl,
230 .ctrlbit = (1 << 12),
231 }, {
232 .name = "i2c",
233 .devname = "s3c2440-i2c.0",
234 .parent = &clk_pclk_low.clk,
235 .enable = s5p64x0_pclk_ctrl,
236 .ctrlbit = (1 << 17),
237 }, {
238 .name = "spi",
239 .devname = "s5p64x0-spi.0",
240 .parent = &clk_pclk_low.clk,
241 .enable = s5p64x0_pclk_ctrl,
242 .ctrlbit = (1 << 21),
243 }, {
244 .name = "spi",
245 .devname = "s5p64x0-spi.1",
246 .parent = &clk_pclk_low.clk,
247 .enable = s5p64x0_pclk_ctrl,
248 .ctrlbit = (1 << 22),
249 }, {
250 .name = "i2c",
251 .devname = "s3c2440-i2c.1",
252 .parent = &clk_pclk_low.clk,
253 .enable = s5p64x0_pclk_ctrl,
254 .ctrlbit = (1 << 27),
255 }, {
256 .name = "dmc0",
257 .parent = &clk_pclk.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 30),
260 }
261};
262
263/*
264 * The following clocks will be enabled during clock initialization.
265 */
266static struct clk init_clocks[] = {
267 {
268 .name = "intc",
269 .parent = &clk_hclk.clk,
270 .enable = s5p64x0_hclk0_ctrl,
271 .ctrlbit = (1 << 1),
272 }, {
273 .name = "mem",
274 .parent = &clk_hclk.clk,
275 .enable = s5p64x0_hclk0_ctrl,
276 .ctrlbit = (1 << 21),
277 }, {
278 .name = "uart",
279 .devname = "s3c6400-uart.0",
280 .parent = &clk_pclk_low.clk,
281 .enable = s5p64x0_pclk_ctrl,
282 .ctrlbit = (1 << 1),
283 }, {
284 .name = "uart",
285 .devname = "s3c6400-uart.1",
286 .parent = &clk_pclk_low.clk,
287 .enable = s5p64x0_pclk_ctrl,
288 .ctrlbit = (1 << 2),
289 }, {
290 .name = "uart",
291 .devname = "s3c6400-uart.2",
292 .parent = &clk_pclk_low.clk,
293 .enable = s5p64x0_pclk_ctrl,
294 .ctrlbit = (1 << 3),
295 }, {
296 .name = "uart",
297 .devname = "s3c6400-uart.3",
298 .parent = &clk_pclk_low.clk,
299 .enable = s5p64x0_pclk_ctrl,
300 .ctrlbit = (1 << 4),
301 }, {
302 .name = "timers",
303 .parent = &clk_pclk_to_wdt_pwm.clk,
304 .enable = s5p64x0_pclk_ctrl,
305 .ctrlbit = (1 << 7),
306 }, {
307 .name = "gpio",
308 .parent = &clk_pclk_low.clk,
309 .enable = s5p64x0_pclk_ctrl,
310 .ctrlbit = (1 << 18),
311 },
312};
313
314static struct clk *clkset_uart_list[] = {
315 &clk_dout_epll.clk,
316 &clk_dout_mpll.clk,
317};
318
319static struct clksrc_sources clkset_uart = {
320 .sources = clkset_uart_list,
321 .nr_sources = ARRAY_SIZE(clkset_uart_list),
322};
323
324static struct clk *clkset_mali_list[] = {
325 &clk_mout_epll.clk,
326 &clk_mout_apll.clk,
327 &clk_mout_mpll.clk,
328};
329
330static struct clksrc_sources clkset_mali = {
331 .sources = clkset_mali_list,
332 .nr_sources = ARRAY_SIZE(clkset_mali_list),
333};
334
335static struct clk *clkset_group2_list[] = {
336 &clk_dout_epll.clk,
337 &clk_dout_mpll.clk,
338 &clk_ext_xtal_mux,
339};
340
341static struct clksrc_sources clkset_group2 = {
342 .sources = clkset_group2_list,
343 .nr_sources = ARRAY_SIZE(clkset_group2_list),
344};
345
346static struct clk *clkset_dispcon_list[] = {
347 &clk_dout_epll.clk,
348 &clk_dout_mpll.clk,
349 &clk_ext_xtal_mux,
350 &clk_mout_dpll.clk,
351};
352
353static struct clksrc_sources clkset_dispcon = {
354 .sources = clkset_dispcon_list,
355 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
356};
357
358static struct clk *clkset_hsmmc44_list[] = {
359 &clk_dout_epll.clk,
360 &clk_dout_mpll.clk,
361 &clk_ext_xtal_mux,
362 &s5p_clk_27m,
363 &clk_48m,
364};
365
366static struct clksrc_sources clkset_hsmmc44 = {
367 .sources = clkset_hsmmc44_list,
368 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
369};
370
371static struct clk *clkset_sclk_audio0_list[] = {
372 [0] = &clk_dout_epll.clk,
373 [1] = &clk_dout_mpll.clk,
374 [2] = &clk_ext_xtal_mux,
375 [3] = NULL,
376 [4] = NULL,
377};
378
379static struct clksrc_sources clkset_sclk_audio0 = {
380 .sources = clkset_sclk_audio0_list,
381 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
382};
383
384static struct clksrc_clk clk_sclk_audio0 = {
385 .clk = {
386 .name = "audio-bus",
387 .devname = "samsung-i2s.0",
388 .enable = s5p64x0_sclk_ctrl,
389 .ctrlbit = (1 << 8),
390 .parent = &clk_dout_epll.clk,
391 },
392 .sources = &clkset_sclk_audio0,
393 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
394 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
395};
396
397static struct clksrc_clk clksrcs[] = {
398 {
399 .clk = {
400 .name = "sclk_fimc",
401 .ctrlbit = (1 << 10),
402 .enable = s5p64x0_sclk_ctrl,
403 },
404 .sources = &clkset_group2,
405 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
406 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
407 }, {
408 .clk = {
409 .name = "aclk_mali",
410 .ctrlbit = (1 << 2),
411 .enable = s5p64x0_sclk1_ctrl,
412 },
413 .sources = &clkset_mali,
414 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
415 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
416 }, {
417 .clk = {
418 .name = "sclk_2d",
419 .ctrlbit = (1 << 12),
420 .enable = s5p64x0_sclk_ctrl,
421 },
422 .sources = &clkset_mali,
423 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
424 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
425 }, {
426 .clk = {
427 .name = "sclk_usi",
428 .ctrlbit = (1 << 7),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_camif",
437 .ctrlbit = (1 << 6),
438 .enable = s5p64x0_sclk_ctrl,
439 },
440 .sources = &clkset_group2,
441 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
442 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
443 }, {
444 .clk = {
445 .name = "sclk_dispcon",
446 .ctrlbit = (1 << 1),
447 .enable = s5p64x0_sclk1_ctrl,
448 },
449 .sources = &clkset_dispcon,
450 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
451 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
452 }, {
453 .clk = {
454 .name = "sclk_hsmmc44",
455 .ctrlbit = (1 << 30),
456 .enable = s5p64x0_sclk_ctrl,
457 },
458 .sources = &clkset_hsmmc44,
459 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
460 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
461 },
462};
463
464static struct clksrc_clk clk_sclk_mmc0 = {
465 .clk = {
466 .name = "sclk_mmc",
467 .devname = "s3c-sdhci.0",
468 .ctrlbit = (1 << 24),
469 .enable = s5p64x0_sclk_ctrl,
470 },
471 .sources = &clkset_group2,
472 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
473 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
474};
475
476static struct clksrc_clk clk_sclk_mmc1 = {
477 .clk = {
478 .name = "sclk_mmc",
479 .devname = "s3c-sdhci.1",
480 .ctrlbit = (1 << 25),
481 .enable = s5p64x0_sclk_ctrl,
482 },
483 .sources = &clkset_group2,
484 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
485 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
486};
487
488static struct clksrc_clk clk_sclk_mmc2 = {
489 .clk = {
490 .name = "sclk_mmc",
491 .devname = "s3c-sdhci.2",
492 .ctrlbit = (1 << 26),
493 .enable = s5p64x0_sclk_ctrl,
494 },
495 .sources = &clkset_group2,
496 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
497 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
498};
499
500static struct clksrc_clk clk_sclk_uclk = {
501 .clk = {
502 .name = "uclk1",
503 .ctrlbit = (1 << 5),
504 .enable = s5p64x0_sclk_ctrl,
505 },
506 .sources = &clkset_uart,
507 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
508 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
509};
510
511static struct clksrc_clk clk_sclk_spi0 = {
512 .clk = {
513 .name = "sclk_spi",
514 .devname = "s5p64x0-spi.0",
515 .ctrlbit = (1 << 20),
516 .enable = s5p64x0_sclk_ctrl,
517 },
518 .sources = &clkset_group2,
519 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
520 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
521};
522
523static struct clksrc_clk clk_sclk_spi1 = {
524 .clk = {
525 .name = "sclk_spi",
526 .devname = "s5p64x0-spi.1",
527 .ctrlbit = (1 << 21),
528 .enable = s5p64x0_sclk_ctrl,
529 },
530 .sources = &clkset_group2,
531 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
532 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
533};
534
535static struct clk clk_i2s0 = {
536 .name = "iis",
537 .devname = "samsung-i2s.0",
538 .parent = &clk_pclk_low.clk,
539 .enable = s5p64x0_pclk_ctrl,
540 .ctrlbit = (1 << 26),
541};
542
543static struct clk clk_i2s1 = {
544 .name = "iis",
545 .devname = "samsung-i2s.1",
546 .parent = &clk_pclk_low.clk,
547 .enable = s5p64x0_pclk_ctrl,
548 .ctrlbit = (1 << 15),
549};
550
551static struct clk clk_i2s2 = {
552 .name = "iis",
553 .devname = "samsung-i2s.2",
554 .parent = &clk_pclk_low.clk,
555 .enable = s5p64x0_pclk_ctrl,
556 .ctrlbit = (1 << 16),
557};
558
559static struct clk *clk_cdev[] = {
560 &clk_i2s0,
561 &clk_i2s1,
562 &clk_i2s2,
563};
564
565static struct clksrc_clk *clksrc_cdev[] = {
566 &clk_sclk_uclk,
567 &clk_sclk_spi0,
568 &clk_sclk_spi1,
569 &clk_sclk_mmc0,
570 &clk_sclk_mmc1,
571 &clk_sclk_mmc2,
572 &clk_sclk_audio0,
573};
574
575static struct clk_lookup s5p6450_clk_lookup[] = {
576 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
577 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
578 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
579 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
580 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
581 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
582 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
583 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
584 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
585 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_sclk_audio0.clk),
586 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
587 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
588};
589
590/* Clock initialization code */
591static struct clksrc_clk *sysclks[] = {
592 &clk_mout_apll,
593 &clk_mout_epll,
594 &clk_dout_epll,
595 &clk_mout_mpll,
596 &clk_dout_mpll,
597 &clk_armclk,
598 &clk_mout_hclk_sel,
599 &clk_dout_pwm_ratio0,
600 &clk_pclk_to_wdt_pwm,
601 &clk_hclk,
602 &clk_pclk,
603 &clk_hclk_low,
604 &clk_pclk_low,
605};
606
607static struct clk dummy_apb_pclk = {
608 .name = "apb_pclk",
609 .id = -1,
610};
611
612void __init_or_cpufreq s5p6450_setup_clocks(void)
613{
614 struct clk *xtal_clk;
615
616 unsigned long xtal;
617 unsigned long fclk;
618 unsigned long hclk;
619 unsigned long hclk_low;
620 unsigned long pclk;
621 unsigned long pclk_low;
622
623 unsigned long apll;
624 unsigned long mpll;
625 unsigned long epll;
626 unsigned long dpll;
627 unsigned int ptr;
628
629 /* Set S5P6450 functions for clk_fout_epll */
630
631 clk_fout_epll.enable = s5p_epll_enable;
632 clk_fout_epll.ops = &s5p6450_epll_ops;
633
634 clk_48m.enable = s5p64x0_clk48m_ctrl;
635
636 xtal_clk = clk_get(NULL, "ext_xtal");
637 BUG_ON(IS_ERR(xtal_clk));
638
639 xtal = clk_get_rate(xtal_clk);
640 clk_put(xtal_clk);
641
642 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
643 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
644 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
645 __raw_readl(S5P64X0_EPLL_CON_K));
646 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
647 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
648
649 clk_fout_apll.rate = apll;
650 clk_fout_mpll.rate = mpll;
651 clk_fout_epll.rate = epll;
652 clk_fout_dpll.rate = dpll;
653
654 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
655 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
656 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
657 print_mhz(dpll));
658
659 fclk = clk_get_rate(&clk_armclk.clk);
660 hclk = clk_get_rate(&clk_hclk.clk);
661 pclk = clk_get_rate(&clk_pclk.clk);
662 hclk_low = clk_get_rate(&clk_hclk_low.clk);
663 pclk_low = clk_get_rate(&clk_pclk_low.clk);
664
665 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
666 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
667 print_mhz(hclk), print_mhz(hclk_low),
668 print_mhz(pclk), print_mhz(pclk_low));
669
670 clk_f.rate = fclk;
671 clk_h.rate = hclk;
672 clk_p.rate = pclk;
673
674 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
675 s3c_set_clksrc(&clksrcs[ptr], true);
676}
677
678void __init s5p6450_register_clocks(void)
679{
680 int ptr;
681 unsigned int cnt;
682
683 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
684 s3c_register_clksrc(sysclks[ptr], 1);
685
686
687 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
688 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
689 s3c_disable_clocks(clk_cdev[cnt], 1);
690
691 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
692 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
693 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
694 s3c_register_clksrc(clksrc_cdev[ptr], 1);
695
696 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
697 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
698 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
699
700 s3c24xx_register_clock(&dummy_apb_pclk);
701}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
deleted file mode 100644
index 57e718957ef3..000000000000
--- a/arch/arm/mach-s5p64x0/clock.c
+++ /dev/null
@@ -1,236 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33
34#include "common.h"
35
36struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45struct clksrc_clk clk_mout_mpll = {
46 .clk = {
47 .name = "mout_mpll",
48 .id = -1,
49 },
50 .sources = &clk_src_mpll,
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
52};
53
54struct clksrc_clk clk_mout_epll = {
55 .clk = {
56 .name = "mout_epll",
57 .id = -1,
58 },
59 .sources = &clk_src_epll,
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
61};
62
63enum perf_level {
64 L0 = 532*1000,
65 L1 = 266*1000,
66 L2 = 133*1000,
67};
68
69static const u32 clock_table[][3] = {
70 /*{ARM_CLK, DIVarm, DIVhclk}*/
71 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
72 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
74};
75
76static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
77{
78 unsigned long rate = clk_get_rate(clk->parent);
79 u32 clkdiv;
80
81 /* divisor mask starts at bit0, so no need to shift */
82 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
83
84 return rate / (clkdiv + 1);
85}
86
87static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
88 unsigned long rate)
89{
90 u32 iter;
91
92 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
93 if (rate > clock_table[iter][0])
94 return clock_table[iter-1][0];
95 }
96
97 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
98}
99
100static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
101{
102 u32 round_tmp;
103 u32 iter;
104 u32 clk_div0_tmp;
105 u32 cur_rate = clk->ops->get_rate(clk);
106 unsigned long flags;
107
108 round_tmp = clk->ops->round_rate(clk, rate);
109 if (round_tmp == cur_rate)
110 return 0;
111
112
113 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
114 if (round_tmp == clock_table[iter][0])
115 break;
116 }
117
118 if (iter >= ARRAY_SIZE(clock_table))
119 iter = ARRAY_SIZE(clock_table) - 1;
120
121 local_irq_save(flags);
122 if (cur_rate > round_tmp) {
123 /* Frequency Down */
124 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
125 clk_div0_tmp |= clock_table[iter][1];
126 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
127
128 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
129 ~(S5P64X0_CLKDIV0_HCLK_MASK);
130 clk_div0_tmp |= clock_table[iter][2];
131 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
132
133
134 } else {
135 /* Frequency Up */
136 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
137 ~(S5P64X0_CLKDIV0_HCLK_MASK);
138 clk_div0_tmp |= clock_table[iter][2];
139 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
140
141 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
142 clk_div0_tmp |= clock_table[iter][1];
143 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
144 }
145 local_irq_restore(flags);
146
147 clk->rate = clock_table[iter][0];
148
149 return 0;
150}
151
152static struct clk_ops s5p64x0_clkarm_ops = {
153 .get_rate = s5p64x0_armclk_get_rate,
154 .set_rate = s5p64x0_armclk_set_rate,
155 .round_rate = s5p64x0_armclk_round_rate,
156};
157
158struct clksrc_clk clk_armclk = {
159 .clk = {
160 .name = "armclk",
161 .id = 1,
162 .parent = &clk_mout_apll.clk,
163 .ops = &s5p64x0_clkarm_ops,
164 },
165 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
166};
167
168struct clksrc_clk clk_dout_mpll = {
169 .clk = {
170 .name = "dout_mpll",
171 .id = -1,
172 .parent = &clk_mout_mpll.clk,
173 },
174 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
175};
176
177static struct clk *clkset_hclk_low_list[] = {
178 &clk_mout_apll.clk,
179 &clk_mout_mpll.clk,
180};
181
182struct clksrc_sources clkset_hclk_low = {
183 .sources = clkset_hclk_low_list,
184 .nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
185};
186
187int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
188{
189 return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
190}
191
192int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
193{
194 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
195}
196
197int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
198{
199 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
200}
201
202int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
203{
204 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
205}
206
207int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
208{
209 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
210}
211
212int s5p64x0_mem_ctrl(struct clk *clk, int enable)
213{
214 return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
215}
216
217int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
218{
219 unsigned long flags;
220 u32 val;
221
222 /* can't rely on clock lock, this register has other usages */
223 local_irq_save(flags);
224
225 val = __raw_readl(S5P64X0_OTHERS);
226 if (enable)
227 val |= S5P64X0_OTHERS_USB_SIG_MASK;
228 else
229 val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
230
231 __raw_writel(val, S5P64X0_OTHERS);
232
233 local_irq_restore(flags);
234
235 return 0;
236}
diff --git a/arch/arm/mach-s5p64x0/clock.h b/arch/arm/mach-s5p64x0/clock.h
deleted file mode 100644
index 28b8e3c6bd24..000000000000
--- a/arch/arm/mach-s5p64x0/clock.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Header file for s5p64x0 clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __MACH_S5P64X0_CLOCK_H
13#define __MACH_S5P64X0_CLOCK_H __FILE__
14
15#include <linux/clk.h>
16
17extern struct clksrc_clk clk_mout_apll;
18extern struct clksrc_clk clk_mout_mpll;
19extern struct clksrc_clk clk_mout_epll;
20
21extern int s5p64x0_epll_enable(struct clk *clk, int enable);
22extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
23
24extern struct clksrc_clk clk_armclk;
25extern struct clksrc_clk clk_dout_mpll;
26
27extern struct clksrc_sources clkset_hclk_low;
28
29extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
30extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
31extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
32extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
33extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
34extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
35
36extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
37
38#endif /* __MACH_S5P64X0_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
deleted file mode 100644
index 9a43be002d78..000000000000
--- a/arch/arm/mach-s5p64x0/common.c
+++ /dev/null
@@ -1,490 +0,0 @@
1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for S5P64X0 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/device.h>
21#include <linux/serial_core.h>
22#include <linux/serial_s3c.h>
23#include <clocksource/samsung_pwm.h>
24#include <linux/platform_device.h>
25#include <linux/sched.h>
26#include <linux/dma-mapping.h>
27#include <linux/gpio.h>
28#include <linux/irq.h>
29#include <linux/reboot.h>
30
31#include <asm/irq.h>
32#include <asm/proc-fns.h>
33#include <asm/system_misc.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/map.h>
39#include <mach/hardware.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/cpu.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/pm.h>
47#include <plat/sdhci.h>
48#include <plat/adc-core.h>
49#include <plat/fb-core.h>
50#include <plat/spi-core.h>
51#include <plat/gpio-cfg.h>
52#include <plat/pwm-core.h>
53#include <plat/regs-irqtype.h>
54#include <plat/watchdog-reset.h>
55
56#include "common.h"
57
58static const char name_s5p6440[] = "S5P6440";
59static const char name_s5p6450[] = "S5P6450";
60
61static struct cpu_table cpu_ids[] __initdata = {
62 {
63 .idcode = S5P6440_CPU_ID,
64 .idmask = S5P64XX_CPU_MASK,
65 .map_io = s5p6440_map_io,
66 .init_clocks = s5p6440_init_clocks,
67 .init_uarts = s5p6440_init_uarts,
68 .init = s5p64x0_init,
69 .name = name_s5p6440,
70 }, {
71 .idcode = S5P6450_CPU_ID,
72 .idmask = S5P64XX_CPU_MASK,
73 .map_io = s5p6450_map_io,
74 .init_clocks = s5p6450_init_clocks,
75 .init_uarts = s5p6450_init_uarts,
76 .init = s5p64x0_init,
77 .name = name_s5p6450,
78 },
79};
80
81/* Initial IO mappings */
82
83static struct map_desc s5p64x0_iodesc[] __initdata = {
84 {
85 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
92 .length = SZ_64K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S3C_VA_TIMER,
96 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S3C_VA_WATCHDOG,
101 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_SROMC,
106 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)S5P_VA_GPIO,
111 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)VA_VIC0,
116 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
117 .length = SZ_16K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)VA_VIC1,
121 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
122 .length = SZ_16K,
123 .type = MT_DEVICE,
124 },
125};
126
127static struct map_desc s5p6440_iodesc[] __initdata = {
128 {
129 .virtual = (unsigned long)S3C_VA_UART,
130 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
131 .length = SZ_4K,
132 .type = MT_DEVICE,
133 },
134};
135
136static struct map_desc s5p6450_iodesc[] __initdata = {
137 {
138 .virtual = (unsigned long)S3C_VA_UART,
139 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
140 .length = SZ_512K,
141 .type = MT_DEVICE,
142 }, {
143 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
144 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
145 .length = SZ_4K,
146 .type = MT_DEVICE,
147 },
148};
149
150static void s5p64x0_idle(void)
151{
152 unsigned long val;
153
154 val = __raw_readl(S5P64X0_PWR_CFG);
155 val &= ~(0x3 << 5);
156 val |= (0x1 << 5);
157 __raw_writel(val, S5P64X0_PWR_CFG);
158
159 cpu_do_idle();
160}
161
162static struct samsung_pwm_variant s5p64x0_pwm_variant = {
163 .bits = 32,
164 .div_base = 0,
165 .has_tint_cstat = true,
166 .tclk_mask = 0,
167};
168
169void __init samsung_set_timer_source(unsigned int event, unsigned int source)
170{
171 s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
172 s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
173}
174
175void __init samsung_timer_init(void)
176{
177 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
178 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
179 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
180 };
181
182 samsung_pwm_clocksource_init(S3C_VA_TIMER,
183 timer_irqs, &s5p64x0_pwm_variant);
184}
185
186/*
187 * s5p64x0_map_io
188 *
189 * register the standard CPU IO areas
190 */
191
192void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
193{
194 /* initialize the io descriptors we need for initialization */
195 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
196 if (mach_desc)
197 iotable_init(mach_desc, size);
198
199 /* detect cpu id and rev. */
200 s5p_init_cpu(S5P64X0_SYS_ID);
201
202 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
203 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
204
205 samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
206}
207
208#ifdef CONFIG_CPU_S5P6440
209void __init s5p6440_map_io(void)
210{
211 /* initialize any device information early */
212 s3c_adc_setname("s3c64xx-adc");
213 s3c_fb_setname("s5p64x0-fb");
214 s3c64xx_spi_setname("s5p64x0-spi");
215
216 s5p64x0_default_sdhci0();
217 s5p64x0_default_sdhci1();
218 s5p6440_default_sdhci2();
219
220 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
221}
222#endif
223
224#ifdef CONFIG_CPU_S5P6450
225void __init s5p6450_map_io(void)
226{
227 /* initialize any device information early */
228 s3c_adc_setname("s3c64xx-adc");
229 s3c_fb_setname("s5p64x0-fb");
230 s3c64xx_spi_setname("s5p64x0-spi");
231
232 s5p64x0_default_sdhci0();
233 s5p64x0_default_sdhci1();
234 s5p6450_default_sdhci2();
235
236 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
237}
238#endif
239
240/*
241 * s5p64x0_init_clocks
242 *
243 * register and setup the CPU clocks
244 */
245#ifdef CONFIG_CPU_S5P6440
246void __init s5p6440_init_clocks(int xtal)
247{
248 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
249
250 s3c24xx_register_baseclocks(xtal);
251 s5p_register_clocks(xtal);
252 s5p6440_register_clocks();
253 s5p6440_setup_clocks();
254}
255#endif
256
257#ifdef CONFIG_CPU_S5P6450
258void __init s5p6450_init_clocks(int xtal)
259{
260 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
261
262 s3c24xx_register_baseclocks(xtal);
263 s5p_register_clocks(xtal);
264 s5p6450_register_clocks();
265 s5p6450_setup_clocks();
266}
267#endif
268
269/*
270 * s5p64x0_init_irq
271 *
272 * register the CPU interrupts
273 */
274#ifdef CONFIG_CPU_S5P6440
275void __init s5p6440_init_irq(void)
276{
277 /* S5P6440 supports 2 VIC */
278 u32 vic[2];
279
280 /*
281 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
282 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
283 */
284 vic[0] = 0xff800ae7;
285 vic[1] = 0xffbf23e5;
286
287 s5p_init_irq(vic, ARRAY_SIZE(vic));
288}
289#endif
290
291#ifdef CONFIG_CPU_S5P6450
292void __init s5p6450_init_irq(void)
293{
294 /* S5P6450 supports only 2 VIC */
295 u32 vic[2];
296
297 /*
298 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
299 * VIC1 is missing IRQ VIC1[12, 14, 23]
300 */
301 vic[0] = 0xff9f1fff;
302 vic[1] = 0xff7fafff;
303
304 s5p_init_irq(vic, ARRAY_SIZE(vic));
305}
306#endif
307
308struct bus_type s5p64x0_subsys = {
309 .name = "s5p64x0-core",
310 .dev_name = "s5p64x0-core",
311};
312
313static struct device s5p64x0_dev = {
314 .bus = &s5p64x0_subsys,
315};
316
317static int __init s5p64x0_core_init(void)
318{
319 return subsys_system_register(&s5p64x0_subsys, NULL);
320}
321core_initcall(s5p64x0_core_init);
322
323int __init s5p64x0_init(void)
324{
325 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
326
327 /* set idle function */
328 arm_pm_idle = s5p64x0_idle;
329
330 return device_register(&s5p64x0_dev);
331}
332
333/* uart registration process */
334#ifdef CONFIG_CPU_S5P6440
335void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
336{
337 int uart;
338
339 for (uart = 0; uart < no; uart++) {
340 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
341 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
342 }
343
344 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
345}
346#endif
347
348#ifdef CONFIG_CPU_S5P6450
349void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
350{
351 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
352}
353#endif
354
355#define eint_offset(irq) ((irq) - IRQ_EINT(0))
356
357static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
358{
359 int offs = eint_offset(data->irq);
360 int shift;
361 u32 ctrl, mask;
362 u32 newvalue = 0;
363
364 if (offs > 15)
365 return -EINVAL;
366
367 switch (type) {
368 case IRQ_TYPE_NONE:
369 printk(KERN_WARNING "No edge setting!\n");
370 break;
371 case IRQ_TYPE_EDGE_RISING:
372 newvalue = S3C2410_EXTINT_RISEEDGE;
373 break;
374 case IRQ_TYPE_EDGE_FALLING:
375 newvalue = S3C2410_EXTINT_FALLEDGE;
376 break;
377 case IRQ_TYPE_EDGE_BOTH:
378 newvalue = S3C2410_EXTINT_BOTHEDGE;
379 break;
380 case IRQ_TYPE_LEVEL_LOW:
381 newvalue = S3C2410_EXTINT_LOWLEV;
382 break;
383 case IRQ_TYPE_LEVEL_HIGH:
384 newvalue = S3C2410_EXTINT_HILEV;
385 break;
386 default:
387 printk(KERN_ERR "No such irq type %d", type);
388 return -EINVAL;
389 }
390
391 shift = (offs / 2) * 4;
392 mask = 0x7 << shift;
393
394 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
395 ctrl |= newvalue << shift;
396 __raw_writel(ctrl, S5P64X0_EINT0CON0);
397
398 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
399 if (soc_is_s5p6450())
400 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
401 else
402 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
403
404 return 0;
405}
406
407/*
408 * s5p64x0_irq_demux_eint
409 *
410 * This function demuxes the IRQ from the group0 external interrupts,
411 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
412 * the specific handlers s5p64x0_irq_demux_eintX_Y.
413 */
414static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
415{
416 u32 status = __raw_readl(S5P64X0_EINT0PEND);
417 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
418 unsigned int irq;
419
420 status &= ~mask;
421 status >>= start;
422 status &= (1 << (end - start + 1)) - 1;
423
424 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
425 if (status & 1)
426 generic_handle_irq(irq);
427 status >>= 1;
428 }
429}
430
431static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
432{
433 s5p64x0_irq_demux_eint(0, 3);
434}
435
436static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
437{
438 s5p64x0_irq_demux_eint(4, 11);
439}
440
441static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
442 struct irq_desc *desc)
443{
444 s5p64x0_irq_demux_eint(12, 15);
445}
446
447static int s5p64x0_alloc_gc(void)
448{
449 struct irq_chip_generic *gc;
450 struct irq_chip_type *ct;
451
452 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
453 S5P_VA_GPIO, handle_level_irq);
454 if (!gc) {
455 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
456 "external interrupts failed\n", __func__);
457 return -EINVAL;
458 }
459
460 ct = gc->chip_types;
461 ct->chip.irq_ack = irq_gc_ack_set_bit;
462 ct->chip.irq_mask = irq_gc_mask_set_bit;
463 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
464 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
465 ct->chip.irq_set_wake = s3c_irqext_wake;
466 ct->regs.ack = EINT0PEND_OFFSET;
467 ct->regs.mask = EINT0MASK_OFFSET;
468 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
469 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
470 return 0;
471}
472
473static int __init s5p64x0_init_irq_eint(void)
474{
475 int ret = s5p64x0_alloc_gc();
476 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
477 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
478 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
479
480 return ret;
481}
482arch_initcall(s5p64x0_init_irq_eint);
483
484void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
485{
486 if (mode != REBOOT_SOFT)
487 samsung_wdt_reset();
488
489 soft_restart(0);
490}
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
deleted file mode 100644
index cbe7f3d731d0..000000000000
--- a/arch/arm/mach-s5p64x0/common.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for S5P64X0 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
13#define __ARCH_ARM_MACH_S5P64X0_COMMON_H
14
15#include <linux/reboot.h>
16
17void s5p6440_init_irq(void);
18void s5p6450_init_irq(void);
19void s5p64x0_init_io(struct map_desc *mach_desc, int size);
20
21void s5p6440_register_clocks(void);
22void s5p6440_setup_clocks(void);
23
24void s5p6450_register_clocks(void);
25void s5p6450_setup_clocks(void);
26
27void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
28extern int s5p64x0_init(void);
29
30#ifdef CONFIG_CPU_S5P6440
31
32extern void s5p6440_map_io(void);
33extern void s5p6440_init_clocks(int xtal);
34
35extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36
37#else
38#define s5p6440_init_clocks NULL
39#define s5p6440_init_uarts NULL
40#define s5p6440_map_io NULL
41#endif
42
43#ifdef CONFIG_CPU_S5P6450
44
45extern void s5p6450_map_io(void);
46extern void s5p6450_init_clocks(int xtal);
47
48extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
49
50#else
51#define s5p6450_init_clocks NULL
52#define s5p6450_init_uarts NULL
53#define s5p6450_map_io NULL
54#endif
55
56#endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
deleted file mode 100644
index 723d4773c323..000000000000
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <linux/platform_data/asoc-s3c.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 switch (pdev->id) {
25 case 0:
26 s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5));
27 s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5));
29 break;
30 default:
31 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
32 return -EINVAL;
33 }
34
35 return 0;
36}
37
38static struct s3c_audio_pdata s5p6440_i2s_pdata = {
39 .cfg_gpio = s5p6440_cfg_i2s,
40 .type = {
41 .i2s = {
42 .quirks = QUIRK_PRI_6CHAN,
43 },
44 },
45};
46
47static struct resource s5p64x0_i2s0_resource[] = {
48 [0] = DEFINE_RES_MEM(S5P64X0_PA_I2S, SZ_256),
49 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
50 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
51};
52
53struct platform_device s5p6440_device_iis = {
54 .name = "samsung-i2s",
55 .id = 0,
56 .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource),
57 .resource = s5p64x0_i2s0_resource,
58 .dev = {
59 .platform_data = &s5p6440_i2s_pdata,
60 },
61};
62
63static int s5p6450_cfg_i2s(struct platform_device *pdev)
64{
65 switch (pdev->id) {
66 case 0:
67 s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
68 s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
69 break;
70 case 1:
71 s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5));
72 s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5));
73 break;
74 case 2:
75 s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5));
76 break;
77 default:
78 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
79 return -EINVAL;
80 }
81
82 return 0;
83}
84
85static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
86 .cfg_gpio = s5p6450_cfg_i2s,
87 .type = {
88 .i2s = {
89 .quirks = QUIRK_PRI_6CHAN,
90 },
91 },
92};
93
94struct platform_device s5p6450_device_iis0 = {
95 .name = "samsung-i2s",
96 .id = 0,
97 .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource),
98 .resource = s5p64x0_i2s0_resource,
99 .dev = {
100 .platform_data = &s5p6450_i2s0_pdata,
101 },
102};
103
104static struct s3c_audio_pdata s5p6450_i2s_pdata = {
105 .cfg_gpio = s5p6450_cfg_i2s,
106};
107
108static struct resource s5p6450_i2s1_resource[] = {
109 [0] = DEFINE_RES_MEM(S5P6450_PA_I2S1, SZ_256),
110 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
111 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
112};
113
114struct platform_device s5p6450_device_iis1 = {
115 .name = "samsung-i2s",
116 .id = 1,
117 .num_resources = ARRAY_SIZE(s5p6450_i2s1_resource),
118 .resource = s5p6450_i2s1_resource,
119 .dev = {
120 .platform_data = &s5p6450_i2s_pdata,
121 },
122};
123
124static struct resource s5p6450_i2s2_resource[] = {
125 [0] = DEFINE_RES_MEM(S5P6450_PA_I2S2, SZ_256),
126 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
127 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
128};
129
130struct platform_device s5p6450_device_iis2 = {
131 .name = "samsung-i2s",
132 .id = 2,
133 .num_resources = ARRAY_SIZE(s5p6450_i2s2_resource),
134 .resource = s5p6450_i2s2_resource,
135 .dev = {
136 .platform_data = &s5p6450_i2s_pdata,
137 },
138};
139
140/* PCM Controller platform_devices */
141
142static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
143{
144 switch (pdev->id) {
145 case 0:
146 s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));
147 s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));
148 break;
149
150 default:
151 printk(KERN_DEBUG "Invalid PCM Controller number!");
152 return -EINVAL;
153 }
154
155 return 0;
156}
157
158static struct s3c_audio_pdata s5p6440_pcm_pdata = {
159 .cfg_gpio = s5p6440_pcm_cfg_gpio,
160};
161
162static struct resource s5p6440_pcm0_resource[] = {
163 [0] = DEFINE_RES_MEM(S5P64X0_PA_PCM, SZ_256),
164 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
165 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
166};
167
168struct platform_device s5p6440_device_pcm = {
169 .name = "samsung-pcm",
170 .id = 0,
171 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
172 .resource = s5p6440_pcm0_resource,
173 .dev = {
174 .platform_data = &s5p6440_pcm_pdata,
175 },
176};
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
deleted file mode 100644
index 9c4ce085f585..000000000000
--- a/arch/arm/mach-s5p64x0/dma.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dma.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
29
30#include <mach/map.h>
31#include <mach/irqs.h>
32#include <mach/regs-clock.h>
33#include <mach/dma.h>
34
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/irqs.h>
38
39static u8 s5p6440_pdma_peri[] = {
40 DMACH_UART0_RX,
41 DMACH_UART0_TX,
42 DMACH_UART1_RX,
43 DMACH_UART1_TX,
44 DMACH_UART2_RX,
45 DMACH_UART2_TX,
46 DMACH_UART3_RX,
47 DMACH_UART3_TX,
48 DMACH_MAX,
49 DMACH_MAX,
50 DMACH_PCM0_TX,
51 DMACH_PCM0_RX,
52 DMACH_I2S0_TX,
53 DMACH_I2S0_RX,
54 DMACH_SPI0_TX,
55 DMACH_SPI0_RX,
56 DMACH_MAX,
57 DMACH_MAX,
58 DMACH_MAX,
59 DMACH_MAX,
60 DMACH_SPI1_TX,
61 DMACH_SPI1_RX,
62};
63
64static struct dma_pl330_platdata s5p6440_pdma_pdata = {
65 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
66 .peri_id = s5p6440_pdma_peri,
67};
68
69static u8 s5p6450_pdma_peri[] = {
70 DMACH_UART0_RX,
71 DMACH_UART0_TX,
72 DMACH_UART1_RX,
73 DMACH_UART1_TX,
74 DMACH_UART2_RX,
75 DMACH_UART2_TX,
76 DMACH_UART3_RX,
77 DMACH_UART3_TX,
78 DMACH_UART4_RX,
79 DMACH_UART4_TX,
80 DMACH_PCM0_TX,
81 DMACH_PCM0_RX,
82 DMACH_I2S0_TX,
83 DMACH_I2S0_RX,
84 DMACH_SPI0_TX,
85 DMACH_SPI0_RX,
86 DMACH_PCM1_TX,
87 DMACH_PCM1_RX,
88 DMACH_PCM2_TX,
89 DMACH_PCM2_RX,
90 DMACH_SPI1_TX,
91 DMACH_SPI1_RX,
92 DMACH_USI_TX,
93 DMACH_USI_RX,
94 DMACH_MAX,
95 DMACH_I2S1_TX,
96 DMACH_I2S1_RX,
97 DMACH_I2S2_TX,
98 DMACH_I2S2_RX,
99 DMACH_PWM,
100 DMACH_UART5_RX,
101 DMACH_UART5_TX,
102};
103
104static struct dma_pl330_platdata s5p6450_pdma_pdata = {
105 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
106 .peri_id = s5p6450_pdma_peri,
107};
108
109static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
110 S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
111
112static int __init s5p64x0_dma_init(void)
113{
114 if (soc_is_s5p6450()) {
115 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
116 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
117 s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata;
118 } else {
119 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
120 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
121 s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata;
122 }
123
124 amba_device_register(&s5p64x0_pdma_device, &iomem_resource);
125
126 return 0;
127}
128arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p64x0/i2c.h b/arch/arm/mach-s5p64x0/i2c.h
deleted file mode 100644
index 1e5bb4ea200d..000000000000
--- a/arch/arm/mach-s5p64x0/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P64X0 I2C configuration
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
13extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
14
15extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
16extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
deleted file mode 100644
index 8759e7882bcb..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <linux/serial_s3c.h>
14#include <plat/map-base.h>
15#include <plat/map-s5p.h>
16
17 .macro addruart, rp, rv, tmp
18 mov \rp, #0xE0000000
19 orr \rp, \rp, #0x00100000
20 ldr \rp, [\rp, #0x118 ]
21 and \rp, \rp, #0xff000
22 teq \rp, #0x50000 @@ S5P6450
23 ldreq \rp, =0xEC800000
24 movne \rp, #0xEC000000 @@ S5P6440
25 ldrne \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
deleted file mode 100644
index 5a622af461d7..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
deleted file mode 100644
index 06cd3c9b16ac..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/gpio.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16/* GPIO bank sizes */
17
18#define S5P6440_GPIO_A_NR (6)
19#define S5P6440_GPIO_B_NR (7)
20#define S5P6440_GPIO_C_NR (8)
21#define S5P6440_GPIO_F_NR (16)
22#define S5P6440_GPIO_G_NR (7)
23#define S5P6440_GPIO_H_NR (10)
24#define S5P6440_GPIO_I_NR (16)
25#define S5P6440_GPIO_J_NR (12)
26#define S5P6440_GPIO_N_NR (16)
27#define S5P6440_GPIO_P_NR (8)
28#define S5P6440_GPIO_R_NR (15)
29
30#define S5P6450_GPIO_A_NR (6)
31#define S5P6450_GPIO_B_NR (7)
32#define S5P6450_GPIO_C_NR (8)
33#define S5P6450_GPIO_D_NR (8)
34#define S5P6450_GPIO_F_NR (16)
35#define S5P6450_GPIO_G_NR (14)
36#define S5P6450_GPIO_H_NR (10)
37#define S5P6450_GPIO_I_NR (16)
38#define S5P6450_GPIO_J_NR (12)
39#define S5P6450_GPIO_K_NR (5)
40#define S5P6450_GPIO_N_NR (16)
41#define S5P6450_GPIO_P_NR (11)
42#define S5P6450_GPIO_Q_NR (14)
43#define S5P6450_GPIO_R_NR (15)
44#define S5P6450_GPIO_S_NR (8)
45
46/* GPIO bank numbers */
47
48/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
49 * space for debugging purposes so that any accidental
50 * change from one gpio bank to another can be caught.
51*/
52
53#define S5P64X0_GPIO_NEXT(__gpio) \
54 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
55
56enum s5p6440_gpio_number {
57 S5P6440_GPIO_A_START = 0,
58 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
59 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
60 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
61 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
62 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
63 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
64 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
65 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
66 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
67 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
68};
69
70enum s5p6450_gpio_number {
71 S5P6450_GPIO_A_START = 0,
72 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
73 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
74 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
75 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
76 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
77 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
78 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
79 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
80 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
81 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
82 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
83 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
84 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
85 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
86};
87
88/* GPIO number definitions */
89
90#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
91#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
92#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
93#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
94#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
95#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
96#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
97#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
98#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
99#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
100#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
101
102#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
103#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
104#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
105#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
106#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
107#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
108#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
109#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
110#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
111#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
112#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
113#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
114#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
115#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
116#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
117
118/* the end of the S5P64X0 specific gpios */
119
120#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
121#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
122
123#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
124 S5P6440_GPIO_END : S5P6450_GPIO_END)
125
126#define S3C_GPIO_END S5P64X0_GPIO_END
127
128/* define the number of gpios we need to the one after the last GPIO range */
129
130#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
131
132#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
deleted file mode 100644
index d3e87996dd9a..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
deleted file mode 100644
index 53982db9d259..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
2 *
3 * Copyright 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
24#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
25#define IRQ_IIC1 S5P_IRQ_VIC0(5)
26#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
27#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
28
29#define IRQ_2D S5P_IRQ_VIC0(11)
30#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
31#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
32#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
33#define IRQ_WDT S5P_IRQ_VIC0(26)
34#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
35#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
36#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
37#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
38#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
39
40/* VIC1 */
41
42#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
43#define IRQ_PCM0 S5P_IRQ_VIC1(2)
44#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
45#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
46#define IRQ_UART0 S5P_IRQ_VIC1(5)
47#define IRQ_UART1 S5P_IRQ_VIC1(6)
48#define IRQ_UART2 S5P_IRQ_VIC1(7)
49#define IRQ_UART3 S5P_IRQ_VIC1(8)
50#define IRQ_DMA0 S5P_IRQ_VIC1(9)
51#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
52#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
53#define IRQ_NFC S5P_IRQ_VIC1(13)
54#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
55#define IRQ_SPI0 S5P_IRQ_VIC1(16)
56#define IRQ_SPI1 S5P_IRQ_VIC1(17)
57#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
58#define IRQ_IIC S5P_IRQ_VIC1(18)
59#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
60#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
61#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
62#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
63#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
64#define IRQ_OTG S5P_IRQ_VIC1(26)
65#define IRQ_DSI S5P_IRQ_VIC1(27)
66#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
67#define IRQ_TSI S5P_IRQ_VIC1(29)
68#define IRQ_PENDN S5P_IRQ_VIC1(30)
69#define IRQ_TC IRQ_PENDN
70#define IRQ_ADC S5P_IRQ_VIC1(31)
71
72/* UART interrupts, S5P6450 has 5 UARTs */
73#define IRQ_S5P_UART_BASE4 (96)
74#define IRQ_S5P_UART_BASE5 (100)
75
76#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
77#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
78#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
79
80#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
81#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
82#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
83
84/* S3C compatibilty defines */
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87
88#define IRQ_I2S0 IRQ_I2SV40
89
90#define IRQ_LCD_FIFO IRQ_DISPCON0
91#define IRQ_LCD_VSYNC IRQ_DISPCON1
92#define IRQ_LCD_SYSTEM IRQ_DISPCON2
93
94/* S5P6450 EINT feature will be added */
95
96/*
97 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
98 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
99 * after the pair of VICs.
100 */
101
102#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
103
104#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
105
106#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
107/*
108 * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
109 * to wake up from sleep. If request is beyond this range, by mistake, a large
110 * return value for an irq number should be indication of something amiss.
111 */
112#define S5P_EINT_BASE2 (0xf0000000)
113
114/*
115 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
116 * that they are sourced from the GPIO pins but with a different scheme for
117 * priority and source indication.
118 *
119 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
120 * interrupts, but for historical reasons they are kept apart from these
121 * next interrupts.
122 *
123 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
124 * machine specific support files.
125 */
126
127/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
128#define IRQ_EINT_GROUP1_NR (15)
129#define IRQ_EINT_GROUP2_NR (8)
130#define IRQ_EINT_GROUP5_NR (7)
131#define IRQ_EINT_GROUP6_NR (10)
132/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
133#define IRQ_EINT_GROUP8_NR (11)
134
135#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
136#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
137#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
138#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
139#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
140#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143
144/* Set the default NR_IRQS */
145
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
147
148#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
deleted file mode 100644
index 50a6e96d6389..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P64X0_PA_SDRAM 0x20000000
20
21#define S5P64X0_PA_CHIPID 0xE0000000
22
23#define S5P64X0_PA_SYSCON 0xE0100000
24
25#define S5P64X0_PA_GPIO 0xE0308000
26
27#define S5P64X0_PA_VIC0 0xE4000000
28#define S5P64X0_PA_VIC1 0xE4100000
29
30#define S5P64X0_PA_SROMC 0xE7000000
31
32#define S5P64X0_PA_PDMA 0xE9000000
33
34#define S5P64X0_PA_TIMER 0xEA000000
35#define S5P64X0_PA_RTC 0xEA100000
36#define S5P64X0_PA_WDT 0xEA200000
37
38#define S5P6440_PA_IIC0 0xEC104000
39#define S5P6440_PA_IIC1 0xEC20F000
40#define S5P6450_PA_IIC0 0xEC100000
41#define S5P6450_PA_IIC1 0xEC200000
42
43#define S5P64X0_PA_SPI0 0xEC400000
44#define S5P64X0_PA_SPI1 0xEC500000
45
46#define S5P64X0_PA_HSOTG 0xED100000
47
48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
49
50#define S5P64X0_PA_FB 0xEE000000
51
52#define S5P64X0_PA_I2S 0xF2000000
53#define S5P6450_PA_I2S1 0xF2800000
54#define S5P6450_PA_I2S2 0xF2900000
55
56#define S5P64X0_PA_PCM 0xF2100000
57
58#define S5P64X0_PA_ADC 0xF3000000
59
60/* Compatibiltiy Defines */
61
62#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
63#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
64#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
65#define S3C_PA_IIC S5P6440_PA_IIC0
66#define S3C_PA_IIC1 S5P6440_PA_IIC1
67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
72
73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
74#define S5P_PA_SROMC S5P64X0_PA_SROMC
75#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
76#define S5P_PA_TIMER S5P64X0_PA_TIMER
77
78#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
79#define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER
80
81/* UART */
82
83#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
84#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
85
86#define S5P_PA_UART0 S5P6450_PA_UART(0)
87#define S5P_PA_UART1 S5P6450_PA_UART(1)
88#define S5P_PA_UART2 S5P6450_PA_UART(2)
89#define S5P_PA_UART3 S5P6450_PA_UART(3)
90#define S5P_PA_UART4 S5P6450_PA_UART(4)
91#define S5P_PA_UART5 S5P6450_PA_UART(5)
92
93#define S5P_SZ_UART SZ_256
94#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
95
96#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
deleted file mode 100644
index 1e0eb65b2b82..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
7 *
8 * Based on PM core support for S3C64XX by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/serial_s3c.h>
16
17#include <mach/regs-gpio.h>
18
19static inline void s3c_pm_debug_init_uart(void)
20{
21 u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
22
23 /*
24 * As a note, since the S5P64X0 UARTs generally have multiple
25 * clock sources, we simply enable PCLK at the moment and hope
26 * that the resume settings for the UART are suitable for the
27 * use with PCLK.
28 */
29 tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
30 tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
31 tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
32 tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
33
34 __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
35 udelay(10);
36}
37
38static inline void s3c_pm_arch_prepare_irqs(void)
39{
40 /* VIC should have already been taken care of */
41
42 /* clear any pending EINT0 interrupts */
43 __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
44}
45
46static inline void s3c_pm_arch_stop_clocks(void) { }
47static inline void s3c_pm_arch_show_resume_irqs(void) { }
48
49/*
50 * make these defines, we currently do not have any need to change
51 * the IRQ wake controls depending on the CPU we are running on
52 */
53#define s3c_irqwake_eintallow ((1 << 16) - 1)
54#define s3c_irqwake_intallow (~0)
55
56static inline void s3c_pm_arch_update_uart(void __iomem *regs,
57 struct pm_uart_save *save)
58{
59 u32 ucon = __raw_readl(regs + S3C2410_UCON);
60 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
61 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
62 u32 new_ucon;
63 u32 delta;
64
65 /*
66 * S5P64X0 UART blocks only support level interrupts, so ensure that
67 * when we restore unused UART blocks we force the level interrupt
68 * settings.
69 */
70 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
71
72 /*
73 * We have a constraint on changing the clock type of the UART
74 * between UCLKx and PCLK, so ensure that when we restore UCON
75 * that the CLK field is correctly modified if the bootloader
76 * has changed anything.
77 */
78 if (ucon_clk != save_clk) {
79 new_ucon = save->ucon;
80 delta = ucon_clk ^ save_clk;
81
82 /*
83 * change from UCLKx => wrong PCLK,
84 * either UCLK can be tested for by a bit-test
85 * with UCLK0
86 */
87 if (ucon_clk & S3C6400_UCON_UCLK0 &&
88 !(save_clk & S3C6400_UCON_UCLK0) &&
89 delta & S3C6400_UCON_PCLK2) {
90 new_ucon &= ~S3C6400_UCON_UCLK0;
91 } else if (delta == S3C6400_UCON_PCLK2) {
92 /*
93 * as a precaution, don't change from
94 * PCLK2 => PCLK or vice-versa
95 */
96 new_ucon ^= S3C6400_UCON_PCLK2;
97 }
98
99 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
100 ucon, new_ucon, save->ucon);
101 save->ucon = new_ucon;
102 }
103}
104
105static inline void s3c_pm_restored_gpios(void)
106{
107 /* ensure sleep mode has been cleared from the system */
108 __raw_writel(0, S5P64X0_SLPEN);
109}
110
111static inline void samsung_pm_saved_gpios(void)
112{
113 /*
114 * turn on the sleep mode and keep it there, as it seems that during
115 * suspend the xCON registers get re-set and thus you can end up with
116 * problems between going to sleep and resuming.
117 */
118 __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
119}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
deleted file mode 100644
index bd91112c813c..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
21#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
22#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
23#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
24
25#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
26
27#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
28#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
29#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
30
31#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
32#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
33#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
34#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
35
36#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
37
38#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
39#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
40
41#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
42#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
43
44#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
45#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
46
47#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
48#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
49
50#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
51#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
52#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
53#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
54
55#define S5P64X0_OTHERS S5P_CLKREG(0x900)
56#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
57
58#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
59
60#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
61#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
62
63/* HCLK GATE Registers */
64#define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2)
65#define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2)
66
67/* PCLK GATE Registers */
68#define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4)
69#define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3)
70#define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2)
71#define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1)
72
73#define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15)
74#define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14)
75#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11)
76#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10)
77#define S5P64X0_PWR_CFG_WFI_MASK (3 << 5)
78#define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5)
79
80#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
81
82#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
83
84#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
85#define S5P64X0_OTHERS_RET_UART (1 << 26)
86#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
87#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
88#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
89
90/* Compatibility defines */
91
92#define ARM_CLK_DIV S5P64X0_CLK_DIV0
93#define ARM_DIV_RATIO_SHIFT 0
94#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
95
96#define S5P_EPLL_CON S5P64X0_EPLL_CON
97
98#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
deleted file mode 100644
index cfdfa4fdadf2..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18/* Base addresses for each of the banks */
19
20#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000)
21#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020)
22#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040)
23#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0)
24#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0)
25#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0)
26#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100)
27#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120)
28#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830)
29#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160)
30#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290)
31
32#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060)
33#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140)
34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
36
37#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
38#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0)
39#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0)
40#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
41
42#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
43#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
44#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
45#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
46
47#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
48#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
49#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
50
51/* External interrupt control registers for group0 */
52
53#define EINT0CON0_OFFSET (0x900)
54#define EINT0FLTCON0_OFFSET (0x910)
55#define EINT0FLTCON1_OFFSET (0x914)
56#define EINT0MASK_OFFSET (0x920)
57#define EINT0PEND_OFFSET (0x924)
58
59#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
60#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
61#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
62#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
63#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
64
65#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
66#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
67
68#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
deleted file mode 100644
index d60397d1ff40..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
deleted file mode 100644
index 2ed921e095dc..000000000000
--- a/arch/arm/mach-s5p64x0/irq-pm.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/irq-pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Interrupt handling Power Management
7 *
8 * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/syscore_ops.h>
16#include <linux/serial_core.h>
17#include <linux/serial_s3c.h>
18#include <linux/io.h>
19
20#include <plat/pm.h>
21
22#include <mach/regs-gpio.h>
23
24static struct sleep_save irq_save[] = {
25 SAVE_ITEM(S5P64X0_EINT0CON0),
26 SAVE_ITEM(S5P64X0_EINT0FLTCON0),
27 SAVE_ITEM(S5P64X0_EINT0FLTCON1),
28 SAVE_ITEM(S5P64X0_EINT0MASK),
29};
30
31static struct irq_grp_save {
32 u32 con;
33 u32 fltcon;
34 u32 mask;
35} eint_grp_save[4];
36
37#ifdef CONFIG_SERIAL_SAMSUNG
38static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
39#endif
40
41static int s5p64x0_irq_pm_suspend(void)
42{
43 struct irq_grp_save *grp = eint_grp_save;
44 int i;
45
46 S3C_PMDBG("%s: suspending IRQs\n", __func__);
47
48 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
49
50#ifdef CONFIG_SERIAL_SAMSUNG
51 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
52 irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
53#endif
54
55 for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
56 grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
57 grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
58 grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
59 }
60
61 return 0;
62}
63
64static void s5p64x0_irq_pm_resume(void)
65{
66 struct irq_grp_save *grp = eint_grp_save;
67 int i;
68
69 S3C_PMDBG("%s: resuming IRQs\n", __func__);
70
71 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
72
73#ifdef CONFIG_SERIAL_SAMSUNG
74 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
75 __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
76#endif
77
78 for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
79 __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
80 __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
81 __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
82 }
83
84 S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
85}
86
87static struct syscore_ops s5p64x0_irq_syscore_ops = {
88 .suspend = s5p64x0_irq_pm_suspend,
89 .resume = s5p64x0_irq_pm_resume,
90};
91
92static int __init s5p64x0_syscore_init(void)
93{
94 register_syscore_ops(&s5p64x0_irq_syscore_ops);
95
96 return 0;
97}
98core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
deleted file mode 100644
index 6840e197cb2d..000000000000
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ /dev/null
@@ -1,280 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/serial_s3c.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25#include <linux/gpio.h>
26#include <linux/pwm_backlight.h>
27#include <linux/fb.h>
28#include <linux/mmc/host.h>
29
30#include <video/platform_lcd.h>
31#include <video/samsung_fimd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37
38#include <mach/hardware.h>
39#include <mach/map.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/gpio-cfg.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47#include <linux/platform_data/i2c-s3c2410.h>
48#include <plat/pll.h>
49#include <plat/adc.h>
50#include <linux/platform_data/touchscreen-s3c2410.h>
51#include <plat/samsung-time.h>
52#include <plat/backlight.h>
53#include <plat/fb.h>
54#include <plat/sdhci.h>
55
56#include "common.h"
57#include "i2c.h"
58
59#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8
67
68#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S3C2440_UFCON_TXTRIG16 | \
70 S3C2410_UFCON_RXTRIG8)
71
72static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = SMDK6440_UCON_DEFAULT,
77 .ulcon = SMDK6440_ULCON_DEFAULT,
78 .ufcon = SMDK6440_UFCON_DEFAULT,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = SMDK6440_UCON_DEFAULT,
84 .ulcon = SMDK6440_ULCON_DEFAULT,
85 .ufcon = SMDK6440_UFCON_DEFAULT,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = SMDK6440_UCON_DEFAULT,
91 .ulcon = SMDK6440_ULCON_DEFAULT,
92 .ufcon = SMDK6440_UFCON_DEFAULT,
93 },
94 [3] = {
95 .hwport = 3,
96 .flags = 0,
97 .ucon = SMDK6440_UCON_DEFAULT,
98 .ulcon = SMDK6440_ULCON_DEFAULT,
99 .ufcon = SMDK6440_UFCON_DEFAULT,
100 },
101};
102
103/* Frame Buffer */
104static struct s3c_fb_pd_win smdk6440_fb_win0 = {
105 .max_bpp = 32,
106 .default_bpp = 24,
107 .xres = 800,
108 .yres = 480,
109};
110
111static struct fb_videomode smdk6440_lcd_timing = {
112 .left_margin = 8,
113 .right_margin = 13,
114 .upper_margin = 7,
115 .lower_margin = 5,
116 .hsync_len = 3,
117 .vsync_len = 1,
118 .xres = 800,
119 .yres = 480,
120};
121
122static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
123 .win[0] = &smdk6440_fb_win0,
124 .vtiming = &smdk6440_lcd_timing,
125 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
126 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
127 .setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
128};
129
130/* LCD power controller */
131static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
132 unsigned int power)
133{
134 int err;
135
136 if (power) {
137 err = gpio_request(S5P6440_GPN(5), "GPN");
138 if (err) {
139 printk(KERN_ERR "failed to request GPN for lcd reset\n");
140 return;
141 }
142
143 gpio_direction_output(S5P6440_GPN(5), 1);
144 gpio_set_value(S5P6440_GPN(5), 0);
145 gpio_set_value(S5P6440_GPN(5), 1);
146 gpio_free(S5P6440_GPN(5));
147 }
148}
149
150static struct plat_lcd_data smdk6440_lcd_power_data = {
151 .set_power = smdk6440_lte480_reset_power,
152};
153
154static struct platform_device smdk6440_lcd_lte480wv = {
155 .name = "platform-lcd",
156 .dev.parent = &s3c_device_fb.dev,
157 .dev.platform_data = &smdk6440_lcd_power_data,
158};
159
160static struct platform_device *smdk6440_devices[] __initdata = {
161 &s3c_device_adc,
162 &s3c_device_rtc,
163 &s3c_device_i2c0,
164 &s3c_device_i2c1,
165 &samsung_device_pwm,
166 &s3c_device_ts,
167 &s3c_device_wdt,
168 &s5p6440_device_iis,
169 &s3c_device_fb,
170 &smdk6440_lcd_lte480wv,
171 &s3c_device_hsmmc0,
172 &s3c_device_hsmmc1,
173 &s3c_device_hsmmc2,
174};
175
176static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
177 .cd_type = S3C_SDHCI_CD_NONE,
178};
179
180static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
181 .cd_type = S3C_SDHCI_CD_INTERNAL,
182#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
183 .max_width = 8,
184 .host_caps = MMC_CAP_8_BIT_DATA,
185#endif
186};
187
188static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
189 .cd_type = S3C_SDHCI_CD_NONE,
190};
191
192static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
193 .flags = 0,
194 .slave_addr = 0x10,
195 .frequency = 100*1000,
196 .sda_delay = 100,
197 .cfg_gpio = s5p6440_i2c0_cfg_gpio,
198};
199
200static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
201 .flags = 0,
202 .bus_num = 1,
203 .slave_addr = 0x10,
204 .frequency = 100*1000,
205 .sda_delay = 100,
206 .cfg_gpio = s5p6440_i2c1_cfg_gpio,
207};
208
209static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
210 { I2C_BOARD_INFO("24c08", 0x50), },
211 { I2C_BOARD_INFO("wm8580", 0x1b), },
212};
213
214static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
215 /* To be populated */
216};
217
218/* LCD Backlight data */
219static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
220 .no = S5P6440_GPF(15),
221 .func = S3C_GPIO_SFN(2),
222};
223
224static struct platform_pwm_backlight_data smdk6440_bl_data = {
225 .pwm_id = 1,
226 .enable_gpio = -1,
227};
228
229static void __init smdk6440_map_io(void)
230{
231 s5p64x0_init_io(NULL, 0);
232 s3c24xx_init_clocks(12000000);
233 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
234 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
235}
236
237static void s5p6440_set_lcd_interface(void)
238{
239 unsigned int cfg;
240
241 /* select TFT LCD type (RGB I/F) */
242 cfg = __raw_readl(S5P64X0_SPCON0);
243 cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
244 cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
245 __raw_writel(cfg, S5P64X0_SPCON0);
246}
247
248static void __init smdk6440_machine_init(void)
249{
250 s3c24xx_ts_set_platdata(NULL);
251
252 s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
253 s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
254 i2c_register_board_info(0, smdk6440_i2c_devs0,
255 ARRAY_SIZE(smdk6440_i2c_devs0));
256 i2c_register_board_info(1, smdk6440_i2c_devs1,
257 ARRAY_SIZE(smdk6440_i2c_devs1));
258
259 s5p6440_set_lcd_interface();
260 s3c_fb_set_platdata(&smdk6440_lcd_pdata);
261
262 s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
263 s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
264 s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
265
266 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
267
268 samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
269}
270
271MACHINE_START(SMDK6440, "SMDK6440")
272 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
273 .atag_offset = 0x100,
274
275 .init_irq = s5p6440_init_irq,
276 .map_io = smdk6440_map_io,
277 .init_machine = smdk6440_machine_init,
278 .init_time = samsung_timer_init,
279 .restart = s5p64x0_restart,
280MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
deleted file mode 100644
index fa1341c074ca..000000000000
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/serial_s3c.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25#include <linux/gpio.h>
26#include <linux/pwm_backlight.h>
27#include <linux/fb.h>
28#include <linux/mmc/host.h>
29
30#include <video/platform_lcd.h>
31#include <video/samsung_fimd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37
38#include <mach/hardware.h>
39#include <mach/map.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/gpio-cfg.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47#include <linux/platform_data/i2c-s3c2410.h>
48#include <plat/pll.h>
49#include <plat/adc.h>
50#include <linux/platform_data/touchscreen-s3c2410.h>
51#include <plat/samsung-time.h>
52#include <plat/backlight.h>
53#include <plat/fb.h>
54#include <plat/sdhci.h>
55
56#include "common.h"
57#include "i2c.h"
58
59#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66#define SMDK6450_ULCON_DEFAULT S3C2410_LCON_CS8
67
68#define SMDK6450_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S3C2440_UFCON_TXTRIG16 | \
70 S3C2410_UFCON_RXTRIG8)
71
72static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = SMDK6450_UCON_DEFAULT,
77 .ulcon = SMDK6450_ULCON_DEFAULT,
78 .ufcon = SMDK6450_UFCON_DEFAULT,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = SMDK6450_UCON_DEFAULT,
84 .ulcon = SMDK6450_ULCON_DEFAULT,
85 .ufcon = SMDK6450_UFCON_DEFAULT,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = SMDK6450_UCON_DEFAULT,
91 .ulcon = SMDK6450_ULCON_DEFAULT,
92 .ufcon = SMDK6450_UFCON_DEFAULT,
93 },
94 [3] = {
95 .hwport = 3,
96 .flags = 0,
97 .ucon = SMDK6450_UCON_DEFAULT,
98 .ulcon = SMDK6450_ULCON_DEFAULT,
99 .ufcon = SMDK6450_UFCON_DEFAULT,
100 },
101#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
102 [4] = {
103 .hwport = 4,
104 .flags = 0,
105 .ucon = SMDK6450_UCON_DEFAULT,
106 .ulcon = SMDK6450_ULCON_DEFAULT,
107 .ufcon = SMDK6450_UFCON_DEFAULT,
108 },
109#endif
110#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
111 [5] = {
112 .hwport = 5,
113 .flags = 0,
114 .ucon = SMDK6450_UCON_DEFAULT,
115 .ulcon = SMDK6450_ULCON_DEFAULT,
116 .ufcon = SMDK6450_UFCON_DEFAULT,
117 },
118#endif
119};
120
121/* Frame Buffer */
122static struct s3c_fb_pd_win smdk6450_fb_win0 = {
123 .max_bpp = 32,
124 .default_bpp = 24,
125 .xres = 800,
126 .yres = 480,
127};
128
129static struct fb_videomode smdk6450_lcd_timing = {
130 .left_margin = 8,
131 .right_margin = 13,
132 .upper_margin = 7,
133 .lower_margin = 5,
134 .hsync_len = 3,
135 .vsync_len = 1,
136 .xres = 800,
137 .yres = 480,
138};
139
140static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
141 .win[0] = &smdk6450_fb_win0,
142 .vtiming = &smdk6450_lcd_timing,
143 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
144 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
145 .setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
146};
147
148/* LCD power controller */
149static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
150 unsigned int power)
151{
152 int err;
153
154 if (power) {
155 err = gpio_request(S5P6450_GPN(5), "GPN");
156 if (err) {
157 printk(KERN_ERR "failed to request GPN for lcd reset\n");
158 return;
159 }
160
161 gpio_direction_output(S5P6450_GPN(5), 1);
162 gpio_set_value(S5P6450_GPN(5), 0);
163 gpio_set_value(S5P6450_GPN(5), 1);
164 gpio_free(S5P6450_GPN(5));
165 }
166}
167
168static struct plat_lcd_data smdk6450_lcd_power_data = {
169 .set_power = smdk6450_lte480_reset_power,
170};
171
172static struct platform_device smdk6450_lcd_lte480wv = {
173 .name = "platform-lcd",
174 .dev.parent = &s3c_device_fb.dev,
175 .dev.platform_data = &smdk6450_lcd_power_data,
176};
177
178static struct platform_device *smdk6450_devices[] __initdata = {
179 &s3c_device_adc,
180 &s3c_device_rtc,
181 &s3c_device_i2c0,
182 &s3c_device_i2c1,
183 &samsung_device_pwm,
184 &s3c_device_ts,
185 &s3c_device_wdt,
186 &s5p6450_device_iis0,
187 &s3c_device_fb,
188 &smdk6450_lcd_lte480wv,
189 &s3c_device_hsmmc0,
190 &s3c_device_hsmmc1,
191 &s3c_device_hsmmc2,
192 /* s5p6450_device_spi0 will be added */
193};
194
195static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
196 .cd_type = S3C_SDHCI_CD_NONE,
197};
198
199static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
200 .cd_type = S3C_SDHCI_CD_NONE,
201#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
202 .max_width = 8,
203 .host_caps = MMC_CAP_8_BIT_DATA,
204#endif
205};
206
207static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
208 .cd_type = S3C_SDHCI_CD_NONE,
209};
210
211static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
212 .flags = 0,
213 .slave_addr = 0x10,
214 .frequency = 100*1000,
215 .sda_delay = 100,
216 .cfg_gpio = s5p6450_i2c0_cfg_gpio,
217};
218
219static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
220 .flags = 0,
221 .bus_num = 1,
222 .slave_addr = 0x10,
223 .frequency = 100*1000,
224 .sda_delay = 100,
225 .cfg_gpio = s5p6450_i2c1_cfg_gpio,
226};
227
228static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
229 { I2C_BOARD_INFO("wm8580", 0x1b), },
230 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */
231};
232
233static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
234 { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
235};
236
237/* LCD Backlight data */
238static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
239 .no = S5P6450_GPF(15),
240 .func = S3C_GPIO_SFN(2),
241};
242
243static struct platform_pwm_backlight_data smdk6450_bl_data = {
244 .pwm_id = 1,
245 .enable_gpio = -1,
246};
247
248static void __init smdk6450_map_io(void)
249{
250 s5p64x0_init_io(NULL, 0);
251 s3c24xx_init_clocks(19200000);
252 s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
253 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
254}
255
256static void s5p6450_set_lcd_interface(void)
257{
258 unsigned int cfg;
259
260 /* select TFT LCD type (RGB I/F) */
261 cfg = __raw_readl(S5P64X0_SPCON0);
262 cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
263 cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
264 __raw_writel(cfg, S5P64X0_SPCON0);
265}
266
267static void __init smdk6450_machine_init(void)
268{
269 s3c24xx_ts_set_platdata(NULL);
270
271 s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
272 s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
273 i2c_register_board_info(0, smdk6450_i2c_devs0,
274 ARRAY_SIZE(smdk6450_i2c_devs0));
275 i2c_register_board_info(1, smdk6450_i2c_devs1,
276 ARRAY_SIZE(smdk6450_i2c_devs1));
277
278 s5p6450_set_lcd_interface();
279 s3c_fb_set_platdata(&smdk6450_lcd_pdata);
280
281 s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
282 s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
283 s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
284
285 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
286
287 samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
288}
289
290MACHINE_START(SMDK6450, "SMDK6450")
291 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
292 .atag_offset = 0x100,
293
294 .init_irq = s5p6450_init_irq,
295 .map_io = smdk6450_map_io,
296 .init_machine = smdk6450_machine_init,
297 .init_time = samsung_timer_init,
298 .restart = s5p64x0_restart,
299MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
deleted file mode 100644
index ec8229cee716..000000000000
--- a/arch/arm/mach-s5p64x0/pm.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 Power Management Support
7 *
8 * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/suspend.h>
16#include <linux/syscore_ops.h>
17#include <linux/io.h>
18
19#include <plat/cpu.h>
20#include <plat/pm.h>
21#include <plat/wakeup-mask.h>
22
23#include <mach/regs-clock.h>
24#include <mach/regs-gpio.h>
25
26static struct sleep_save s5p64x0_core_save[] = {
27 SAVE_ITEM(S5P64X0_APLL_CON),
28 SAVE_ITEM(S5P64X0_MPLL_CON),
29 SAVE_ITEM(S5P64X0_EPLL_CON),
30 SAVE_ITEM(S5P64X0_EPLL_CON_K),
31 SAVE_ITEM(S5P64X0_CLK_SRC0),
32 SAVE_ITEM(S5P64X0_CLK_SRC1),
33 SAVE_ITEM(S5P64X0_CLK_DIV0),
34 SAVE_ITEM(S5P64X0_CLK_DIV1),
35 SAVE_ITEM(S5P64X0_CLK_DIV2),
36 SAVE_ITEM(S5P64X0_CLK_DIV3),
37 SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
38 SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
39 SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
40};
41
42static struct sleep_save s5p64x0_misc_save[] = {
43 SAVE_ITEM(S5P64X0_AHB_CON0),
44 SAVE_ITEM(S5P64X0_SPCON0),
45 SAVE_ITEM(S5P64X0_SPCON1),
46 SAVE_ITEM(S5P64X0_MEM0CONSLP0),
47 SAVE_ITEM(S5P64X0_MEM0CONSLP1),
48 SAVE_ITEM(S5P64X0_MEM0DRVCON),
49 SAVE_ITEM(S5P64X0_MEM1DRVCON),
50};
51
52/* DPLL is present only in S5P6450 */
53static struct sleep_save s5p6450_core_save[] = {
54 SAVE_ITEM(S5P6450_DPLL_CON),
55 SAVE_ITEM(S5P6450_DPLL_CON_K),
56};
57
58void s3c_pm_configure_extint(void)
59{
60 __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
61}
62
63void s3c_pm_restore_core(void)
64{
65 __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
66
67 s3c_pm_do_restore_core(s5p64x0_core_save,
68 ARRAY_SIZE(s5p64x0_core_save));
69
70 if (soc_is_s5p6450())
71 s3c_pm_do_restore_core(s5p6450_core_save,
72 ARRAY_SIZE(s5p6450_core_save));
73
74 s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
75}
76
77void s3c_pm_save_core(void)
78{
79 s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
80
81 if (soc_is_s5p6450())
82 s3c_pm_do_save(s5p6450_core_save,
83 ARRAY_SIZE(s5p6450_core_save));
84
85 s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
86}
87
88static int s5p64x0_cpu_suspend(unsigned long arg)
89{
90 unsigned long tmp = 0;
91
92 /*
93 * Issue the standby signal into the pm unit. Note, we
94 * issue a write-buffer drain just in case.
95 */
96 asm("b 1f\n\t"
97 ".align 5\n\t"
98 "1:\n\t"
99 "mcr p15, 0, %0, c7, c10, 5\n\t"
100 "mcr p15, 0, %0, c7, c10, 4\n\t"
101 "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
102
103 pr_info("Failed to suspend the system\n");
104 return 1; /* Aborting suspend */
105}
106
107/* mapping of interrupts to parts of the wakeup mask */
108static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
109 { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
110 { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
111 { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
112 { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
113};
114
115static void s5p64x0_pm_prepare(void)
116{
117 u32 tmp;
118
119 samsung_sync_wakemask(S5P64X0_PWR_CFG,
120 s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
121
122 /* store the resume address in INFORM0 register */
123 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
124
125 /* setup clock gating for FIMGVG block */
126 __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
127 (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
128 __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
129 (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
130
131 /* Configure the stabilization counter with wait time required */
132 __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
133
134 /* set WFI to SLEEP mode configuration */
135 tmp = __raw_readl(S5P64X0_SLEEP_CFG);
136 tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
137 __raw_writel(tmp, S5P64X0_SLEEP_CFG);
138
139 tmp = __raw_readl(S5P64X0_PWR_CFG);
140 tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
141 tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
142 __raw_writel(tmp, S5P64X0_PWR_CFG);
143
144 /*
145 * set OTHERS register to disable interrupt before going to
146 * sleep. This bit is present only in S5P6450, it is reserved
147 * in S5P6440.
148 */
149 if (soc_is_s5p6450()) {
150 tmp = __raw_readl(S5P64X0_OTHERS);
151 tmp |= S5P6450_OTHERS_DISABLE_INT;
152 __raw_writel(tmp, S5P64X0_OTHERS);
153 }
154
155 /* ensure previous wakeup state is cleared before sleeping */
156 __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
157
158}
159
160static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
161{
162 pm_cpu_prep = s5p64x0_pm_prepare;
163 pm_cpu_sleep = s5p64x0_cpu_suspend;
164
165 return 0;
166}
167
168static struct subsys_interface s5p64x0_pm_interface = {
169 .name = "s5p64x0_pm",
170 .subsys = &s5p64x0_subsys,
171 .add_dev = s5p64x0_pm_add,
172};
173
174static __init int s5p64x0_pm_drvinit(void)
175{
176 s3c_pm_init();
177
178 return subsys_interface_register(&s5p64x0_pm_interface);
179}
180arch_initcall(s5p64x0_pm_drvinit);
181
182static void s5p64x0_pm_resume(void)
183{
184 u32 tmp;
185
186 tmp = __raw_readl(S5P64X0_OTHERS);
187 tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
188 S5P64X0_OTHERS_RET_UART);
189 __raw_writel(tmp , S5P64X0_OTHERS);
190}
191
192static struct syscore_ops s5p64x0_pm_syscore_ops = {
193 .resume = s5p64x0_pm_resume,
194};
195
196static __init int s5p64x0_pm_syscore_init(void)
197{
198 register_syscore_ops(&s5p64x0_pm_syscore_ops);
199
200 return 0;
201}
202arch_initcall(s5p64x0_pm_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
deleted file mode 100644
index f346ee4af54d..000000000000
--- a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Base S5P64X0 GPIO setup information for LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/fb.h>
14#include <linux/gpio.h>
15
16#include <plat/cpu.h>
17#include <plat/fb.h>
18#include <plat/gpio-cfg.h>
19
20void s5p64x0_fb_gpio_setup_24bpp(void)
21{
22 if (soc_is_s5p6440()) {
23 s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
24 s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
25 } else if (soc_is_s5p6450()) {
26 s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
28 }
29}
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
deleted file mode 100644
index 569b76ac98cb..000000000000
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64x0/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <plat/gpio-cfg.h>
22#include <linux/platform_data/i2c-s3c2410.h>
23
24#include "i2c.h"
25
26void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
27{
28 s3c_gpio_cfgall_range(S5P6440_GPB(5), 2,
29 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
30}
31
32void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
33{
34 s3c_gpio_cfgall_range(S5P6450_GPB(5), 2,
35 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
36}
37
38void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
deleted file mode 100644
index 867374e6d0bc..000000000000
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * I2C1 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <plat/gpio-cfg.h>
22#include <linux/platform_data/i2c-s3c2410.h>
23
24#include "i2c.h"
25
26void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
27{
28 s3c_gpio_cfgall_range(S5P6440_GPR(9), 2,
29 S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
30}
31
32void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
33{
34 s3c_gpio_cfgall_range(S5P6450_GPR(9), 2,
35 S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
36}
37
38void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
deleted file mode 100644
index 8410af0d12bf..000000000000
--- a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16
17#include <mach/regs-gpio.h>
18#include <mach/regs-clock.h>
19
20#include <plat/gpio-cfg.h>
21#include <plat/sdhci.h>
22#include <plat/cpu.h>
23
24void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27
28 /* Set all the necessary GPG pins to special-function 2 */
29 if (soc_is_s5p6450())
30 s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
31 S3C_GPIO_SFN(2));
32 else
33 s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
34 S3C_GPIO_SFN(2));
35
36 /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
37 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
38 if (soc_is_s5p6450()) {
39 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
40 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
41 } else {
42 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
43 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
44 }
45 }
46}
47
48void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
49{
50 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
51
52 /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
53 if (soc_is_s5p6450())
54 s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
55 else
56 s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
57
58 switch (width) {
59 case 8:
60 /* Set data pins GPH[6:9] special-function 2 */
61 if (soc_is_s5p6450())
62 s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
63 S3C_GPIO_SFN(2));
64 else
65 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
66 S3C_GPIO_SFN(2));
67 case 4:
68 /* set data pins GPH[2:5] special-function 2 */
69 if (soc_is_s5p6450())
70 s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
71 S3C_GPIO_SFN(2));
72 else
73 s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
74 S3C_GPIO_SFN(2));
75 default:
76 break;
77 }
78
79 /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
80 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
81 if (soc_is_s5p6450()) {
82 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
83 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
84 } else {
85 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
86 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
87 }
88 }
89}
90
91void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
92{
93 /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
94 s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
95
96 /* Set data pins GPH[6:9] pins to special-function 3 */
97 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
98}
99
100void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
101{
102 /* Set all the necessary GPG pins to special-function 3 */
103 s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
104}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
deleted file mode 100644
index 7664356720ca..000000000000
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 if (soc_is_s5p6450())
18 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
19 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
20 else
21 s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23 return 0;
24}
25#endif
26
27#ifdef CONFIG_S3C64XX_DEV_SPI1
28int s3c64xx_spi1_cfg_gpio(void)
29{
30 if (soc_is_s5p6450())
31 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
32 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
33 else
34 s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
35 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
36 return 0;
37}
38#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 301b892d97d9..d2d375b3db2d 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -15,7 +15,7 @@ config PLAT_SAMSUNG
15 15
16config PLAT_S5P 16config PLAT_S5P
17 bool 17 bool
18 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 18 depends on (ARCH_S5PC100 || ARCH_S5PV210)
19 default y 19 default y
20 select ARCH_REQUIRE_GPIOLIB 20 select ARCH_REQUIRE_GPIOLIB
21 select ARM_VIC 21 select ARM_VIC
@@ -29,7 +29,7 @@ config PLAT_S5P
29 29
30config SAMSUNG_PM 30config SAMSUNG_PM
31 bool 31 bool
32 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM) 32 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
33 default y 33 default y
34 help 34 help
35 Base platform power management code for samsung code 35 Base platform power management code for samsung code
@@ -78,14 +78,14 @@ config SAMSUNG_CLKSRC
78 used by newer systems such as the S3C64XX. 78 used by newer systems such as the S3C64XX.
79 79
80config S5P_CLOCK 80config S5P_CLOCK
81 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 81 def_bool (ARCH_S5PC100 || ARCH_S5PV210)
82 help 82 help
83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs 83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
84 84
85# options for IRQ support 85# options for IRQ support
86 86
87config S5P_IRQ 87config S5P_IRQ
88 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 88 def_bool (ARCH_S5PC100 || ARCH_S5PV210)
89 help 89 help
90 Support common interrupt part for ARCH_S5P SoCs 90 Support common interrupt part for ARCH_S5P SoCs
91 91
@@ -93,7 +93,6 @@ config S5P_EXT_INT
93 bool 93 bool
94 help 94 help
95 Use the external interrupts (other than GPIO interrupts.) 95 Use the external interrupts (other than GPIO interrupts.)
96 Note: Do not choose this for S5P6440 and S5P6450.
97 96
98config S5P_GPIO_INT 97config S5P_GPIO_INT
99 bool 98 bool
@@ -143,7 +142,7 @@ config S3C_GPIO_TRACK
143 142
144config S5P_DEV_UART 143config S5P_DEV_UART
145 def_bool y 144 def_bool y
146 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 145 depends on (ARCH_S5PC100 || ARCH_S5PV210)
147 146
148# ADC driver 147# ADC driver
149 148
@@ -397,7 +396,7 @@ config SAMSUNG_PM_GPIO
397 396
398config SAMSUNG_DMADEV 397config SAMSUNG_DMADEV
399 bool "Use legacy Samsung DMA abstraction" 398 bool "Use legacy Samsung DMA abstraction"
400 depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S5P64X0 || ARCH_S3C64XX 399 depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S3C64XX
401 select DMADEVICES 400 select DMADEVICES
402 default y 401 default y
403 help 402 help
@@ -474,7 +473,6 @@ config S5P_PM
474 bool 473 bool
475 help 474 help
476 Common code for power management support on S5P and newer SoCs 475 Common code for power management support on S5P and newer SoCs
477 Note: Do not select this for S5P6440 and S5P6450.
478 476
479config S5P_SLEEP 477config S5P_SLEEP
480 bool 478 bool
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 79690f2f6d3f..8033561f6200 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -43,7 +43,7 @@ enum s3c_cpu_type {
43 TYPE_ADCV1, /* S3C24XX */ 43 TYPE_ADCV1, /* S3C24XX */
44 TYPE_ADCV11, /* S3C2443 */ 44 TYPE_ADCV11, /* S3C2443 */
45 TYPE_ADCV12, /* S3C2416, S3C2450 */ 45 TYPE_ADCV12, /* S3C2416, S3C2450 */
46 TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */ 46 TYPE_ADCV2, /* S3C64XX, S5PC100 */
47 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ 47 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
48}; 48};
49 49
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5a237db9f9eb..18e4365b0d26 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -33,10 +33,6 @@ extern unsigned long samsung_cpu_id;
33#define S3C6410_CPU_ID 0x36410000 33#define S3C6410_CPU_ID 0x36410000
34#define S3C64XX_CPU_MASK 0xFFFFF000 34#define S3C64XX_CPU_MASK 0xFFFFF000
35 35
36#define S5P6440_CPU_ID 0x56440000
37#define S5P6450_CPU_ID 0x36450000
38#define S5P64XX_CPU_MASK 0xFFFFF000
39
40#define S5PC100_CPU_ID 0x43100000 36#define S5PC100_CPU_ID 0x43100000
41#define S5PC100_CPU_MASK 0xFFFFF000 37#define S5PC100_CPU_MASK 0xFFFFF000
42 38
@@ -54,8 +50,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
54IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) 50IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
55IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) 51IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
56IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) 52IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
57IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
58IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
59IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) 53IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
60IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) 54IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
61 55
@@ -86,18 +80,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
86# define soc_is_s3c64xx() 0 80# define soc_is_s3c64xx() 0
87#endif 81#endif
88 82
89#if defined(CONFIG_CPU_S5P6440)
90# define soc_is_s5p6440() is_samsung_s5p6440()
91#else
92# define soc_is_s5p6440() 0
93#endif
94
95#if defined(CONFIG_CPU_S5P6450)
96# define soc_is_s5p6450() is_samsung_s5p6450()
97#else
98# define soc_is_s5p6450() 0
99#endif
100
101#if defined(CONFIG_CPU_S5PC100) 83#if defined(CONFIG_CPU_S5PC100)
102# define soc_is_s5pc100() is_samsung_s5pc100() 84# define soc_is_s5pc100() is_samsung_s5pc100()
103#else 85#else
@@ -177,7 +159,6 @@ extern struct bus_type s3c2440_subsys;
177extern struct bus_type s3c2442_subsys; 159extern struct bus_type s3c2442_subsys;
178extern struct bus_type s3c2443_subsys; 160extern struct bus_type s3c2443_subsys;
179extern struct bus_type s3c6410_subsys; 161extern struct bus_type s3c6410_subsys;
180extern struct bus_type s5p64x0_subsys;
181extern struct bus_type s5pv210_subsys; 162extern struct bus_type s5pv210_subsys;
182 163
183extern void (*s5pc1xx_idle)(void); 164extern void (*s5pc1xx_idle)(void);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index eece188ed188..ca66f5137f4b 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -94,15 +94,6 @@ extern struct platform_device s5p_device_mixer;
94extern struct platform_device s5p_device_onenand; 94extern struct platform_device s5p_device_onenand;
95extern struct platform_device s5p_device_sdo; 95extern struct platform_device s5p_device_sdo;
96 96
97extern struct platform_device s5p6440_device_iis;
98extern struct platform_device s5p6440_device_pcm;
99
100extern struct platform_device s5p6450_device_iis0;
101extern struct platform_device s5p6450_device_iis1;
102extern struct platform_device s5p6450_device_iis2;
103extern struct platform_device s5p6450_device_pcm0;
104
105
106extern struct platform_device s5pc100_device_ac97; 97extern struct platform_device s5pc100_device_ac97;
107extern struct platform_device s5pc100_device_iis0; 98extern struct platform_device s5pc100_device_iis0;
108extern struct platform_device s5pc100_device_iis1; 99extern struct platform_device s5pc100_device_iis1;
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 9ae507270785..a400464c7a6d 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -61,11 +61,4 @@ extern void s5pv210_fb_gpio_setup_24bpp(void);
61 */ 61 */
62extern void exynos4_fimd0_gpio_setup_24bpp(void); 62extern void exynos4_fimd0_gpio_setup_24bpp(void);
63 63
64/**
65 * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD
66 *
67 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
68 */
69extern void s5p64x0_fb_gpio_setup_24bpp(void);
70
71#endif /* __PLAT_S3C_FB_H */ 64#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index bf650218b40e..7b2332fc7ac6 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -68,10 +68,6 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
68extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 68extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
69extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 69extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
70extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 70extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
71extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
72extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
73extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
74extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
75 71
76/* S3C2416 SDHCI setup */ 72/* S3C2416 SDHCI setup */
77 73
@@ -151,45 +147,6 @@ static inline void s3c6400_default_sdhci2(void) { }
151 147
152#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 148#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
153 149
154/* S5P64X0 SDHCI setup */
155
156#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
157static inline void s5p64x0_default_sdhci0(void)
158{
159#ifdef CONFIG_S3C_DEV_HSMMC
160 s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio;
161#endif
162}
163
164static inline void s5p64x0_default_sdhci1(void)
165{
166#ifdef CONFIG_S3C_DEV_HSMMC1
167 s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio;
168#endif
169}
170
171static inline void s5p6440_default_sdhci2(void)
172{
173#ifdef CONFIG_S3C_DEV_HSMMC2
174 s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
175#endif
176}
177
178static inline void s5p6450_default_sdhci2(void)
179{
180#ifdef CONFIG_S3C_DEV_HSMMC2
181 s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
182#endif
183}
184
185#else
186static inline void s5p64x0_default_sdhci0(void) { }
187static inline void s5p64x0_default_sdhci1(void) { }
188static inline void s5p6440_default_sdhci2(void) { }
189static inline void s5p6450_default_sdhci2(void) { }
190
191#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
192
193/* S5PC100 SDHCI setup */ 150/* S5PC100 SDHCI setup */
194 151
195#ifdef CONFIG_S5PC100_SETUP_SDHCI 152#ifdef CONFIG_S5PC100_SETUP_SDHCI
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 10:39:09 -0400