3 files changed, 84 insertions, 11 deletions

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index bae0d87a38b2..5573c08d3180 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -50,6 +50,11 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+                  connected from the peripherals, but are routed dynamically
+                  by a crossbar/multiplexer preceding the GIC. The GIC irq
+                  input line is assigned dynamically when the corresponding
+                  peripheral's crossbar line is mapped.
 Example:
 
         intc: interrupt-controller@fff11000 {
@@ -57,6 +62,7 @@ Example:
                 #interrupt-cells = <3>;
                 #address-cells = <1>;
                 interrupt-controller;
+                arm,routable-irqs = <160>;
                 reg = <0xfff11000 0x1000>,
                       <0xfff10100 0x100>;
         };
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 341c6016812d..07a7050841ec 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -824,16 +824,25 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
                 irq_set_chip_and_handler(irq, &gic_chip,
                                          handle_fasteoi_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+                gic_routable_irq_domain_ops->map(d, irq, hw);
         }
         irq_set_chip_data(irq, d->host_data);
         return 0;
 }
 
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+        gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
 static int gic_irq_domain_xlate(struct irq_domain *d,
                                 struct device_node *controller,
                                 const u32 *intspec, unsigned int intsize,
                                 unsigned long *out_hwirq, unsigned int *out_type)
 {
+        unsigned long ret = 0;
+
         if (d->of_node != controller)
                 return -EINVAL;
         if (intsize < 3)
@@ -843,11 +852,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
         *out_hwirq = intspec[1] + 16;
 
         /* For SPIs, we need to add 16 more to get the GIC irq ID number */
-        if (!intspec[0])
-                *out_hwirq += 16;
+        if (!intspec[0]) {
+                ret = gic_routable_irq_domain_ops->xlate(d, controller,
+                                                         intspec,
+                                                         intsize,
+                                                         out_hwirq,
+                                                         out_type);
+
+                if (IS_ERR_VALUE(ret))
+                        return ret;
+        }
 
         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
-        return 0;
+
+        return ret;
 }
 
 #ifdef CONFIG_SMP
@@ -871,9 +889,41 @@ static struct notifier_block gic_cpu_notifier = {
 
 const struct irq_domain_ops gic_irq_domain_ops = {
         .map = gic_irq_domain_map,
+        .unmap = gic_irq_domain_unmap,
         .xlate = gic_irq_domain_xlate,
 };
 
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                              irq_hw_number_t hw)
+{
+        return 0;
+}
+
+static void gic_routable_irq_domain_unmap(struct irq_domain *d,
+                                          unsigned int irq)
+{
+}
+
+static int gic_routable_irq_domain_xlate(struct irq_domain *d,
+                                struct device_node *controller,
+                                const u32 *intspec, unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
+{
+        *out_hwirq += 16;
+        return 0;
+}
+
+const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
+        .map = gic_routable_irq_domain_map,
+        .unmap = gic_routable_irq_domain_unmap,
+        .xlate = gic_routable_irq_domain_xlate,
+};
+
+const struct irq_domain_ops *gic_routable_irq_domain_ops =
+                                        &gic_default_routable_irq_domain_ops;
+
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                            void __iomem *dist_base, void __iomem *cpu_base,
                            u32 percpu_offset, struct device_node *node)
@@ -881,6 +931,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
         irq_hw_number_t hwirq_base;
         struct gic_chip_data *gic;
         int gic_irqs, irq_base, i;
+        int nr_routable_irqs;
 
         BUG_ON(gic_nr >= MAX_GIC_NR);
 
@@ -946,14 +997,25 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
         gic->gic_irqs = gic_irqs;
 
         gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
-        irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
-        if (IS_ERR_VALUE(irq_base)) {
-                WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-                     irq_start);
-                irq_base = irq_start;
+
+        if (of_property_read_u32(node, "arm,routable-irqs",
+                                 &nr_routable_irqs)) {
+                irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
+                                           numa_node_id());
+                if (IS_ERR_VALUE(irq_base)) {
+                        WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+                             irq_start);
+                        irq_base = irq_start;
+                }
+
+                gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
+                                        hwirq_base, &gic_irq_domain_ops, gic);
+        } else {
+                gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
+                                                    &gic_irq_domain_ops,
+                                                    gic);
         }
-        gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
-                                    hwirq_base, &gic_irq_domain_ops, gic);
+
         if (WARN_ON(!gic->domain))
                 return;
 
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 0ceb389dba6c..7ed92d0560d5 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -93,6 +93,11 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
+extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
+static inline void __init register_routable_domain_ops
+                                        (const struct irq_domain_ops *ops)
+{
+        gic_routable_irq_domain_ops = ops;
+}
 #endif /* __ASSEMBLY */
-
 #endif