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-rw-r--r--arch/blackfin/mach-common/ints-priority.c86
1 files changed, 39 insertions, 47 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 01926e5948ba..766e9f6d0627 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -19,9 +19,6 @@
19#ifdef CONFIG_IPIPE 19#ifdef CONFIG_IPIPE
20#include <linux/ipipe.h> 20#include <linux/ipipe.h>
21#endif 21#endif
22#ifdef CONFIG_KGDB
23#include <linux/kgdb.h>
24#endif
25#include <asm/traps.h> 22#include <asm/traps.h>
26#include <asm/blackfin.h> 23#include <asm/blackfin.h>
27#include <asm/gpio.h> 24#include <asm/gpio.h>
@@ -153,24 +150,22 @@ static void bfin_core_unmask_irq(struct irq_data *d)
153 150
154static void bfin_internal_mask_irq(unsigned int irq) 151static void bfin_internal_mask_irq(unsigned int irq)
155{ 152{
156 unsigned long flags; 153 unsigned long flags = hard_local_irq_save();
157 154
158#ifdef CONFIG_BF53x 155#ifdef SIC_IMASK0
159 flags = hard_local_irq_save(); 156 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
160 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 157 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
161 ~(1 << SIC_SYSIRQ(irq)));
162#else
163 unsigned mask_bank, mask_bit;
164 flags = hard_local_irq_save();
165 mask_bank = SIC_SYSIRQ(irq) / 32;
166 mask_bit = SIC_SYSIRQ(irq) % 32;
167 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 158 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
168 ~(1 << mask_bit)); 159 ~(1 << mask_bit));
169#ifdef CONFIG_SMP 160# ifdef CONFIG_SMP
170 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & 161 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
171 ~(1 << mask_bit)); 162 ~(1 << mask_bit));
163# endif
164#else
165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
166 ~(1 << SIC_SYSIRQ(irq)));
172#endif 167#endif
173#endif 168
174 hard_local_irq_restore(flags); 169 hard_local_irq_restore(flags);
175} 170}
176 171
@@ -186,30 +181,28 @@ static void bfin_internal_unmask_irq_affinity(unsigned int irq,
186static void bfin_internal_unmask_irq(unsigned int irq) 181static void bfin_internal_unmask_irq(unsigned int irq)
187#endif 182#endif
188{ 183{
189 unsigned long flags; 184 unsigned long flags = hard_local_irq_save();
190 185
191#ifdef CONFIG_BF53x 186#ifdef SIC_IMASK0
192 flags = hard_local_irq_save(); 187 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
193 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 188 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
194 (1 << SIC_SYSIRQ(irq))); 189# ifdef CONFIG_SMP
195#else
196 unsigned mask_bank, mask_bit;
197 flags = hard_local_irq_save();
198 mask_bank = SIC_SYSIRQ(irq) / 32;
199 mask_bit = SIC_SYSIRQ(irq) % 32;
200#ifdef CONFIG_SMP
201 if (cpumask_test_cpu(0, affinity)) 190 if (cpumask_test_cpu(0, affinity))
202#endif 191# endif
203 bfin_write_SIC_IMASK(mask_bank, 192 bfin_write_SIC_IMASK(mask_bank,
204 bfin_read_SIC_IMASK(mask_bank) | 193 bfin_read_SIC_IMASK(mask_bank) |
205 (1 << mask_bit)); 194 (1 << mask_bit));
206#ifdef CONFIG_SMP 195# ifdef CONFIG_SMP
207 if (cpumask_test_cpu(1, affinity)) 196 if (cpumask_test_cpu(1, affinity))
208 bfin_write_SICB_IMASK(mask_bank, 197 bfin_write_SICB_IMASK(mask_bank,
209 bfin_read_SICB_IMASK(mask_bank) | 198 bfin_read_SICB_IMASK(mask_bank) |
210 (1 << mask_bit)); 199 (1 << mask_bit));
200# endif
201#else
202 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
203 (1 << SIC_SYSIRQ(irq)));
211#endif 204#endif
212#endif 205
213 hard_local_irq_restore(flags); 206 hard_local_irq_restore(flags);
214} 207}
215 208
@@ -292,6 +285,8 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
292{ 285{
293 return bfin_internal_set_wake(d->irq, state); 286 return bfin_internal_set_wake(d->irq, state);
294} 287}
288#else
289# define bfin_internal_set_wake_chip NULL
295#endif 290#endif
296 291
297static struct irq_chip bfin_core_irqchip = { 292static struct irq_chip bfin_core_irqchip = {
@@ -312,9 +307,7 @@ static struct irq_chip bfin_internal_irqchip = {
312#ifdef CONFIG_SMP 307#ifdef CONFIG_SMP
313 .irq_set_affinity = bfin_internal_set_affinity, 308 .irq_set_affinity = bfin_internal_set_affinity,
314#endif 309#endif
315#ifdef CONFIG_PM
316 .irq_set_wake = bfin_internal_set_wake_chip, 310 .irq_set_wake = bfin_internal_set_wake_chip,
317#endif
318}; 311};
319 312
320static void bfin_handle_irq(unsigned irq) 313static void bfin_handle_irq(unsigned irq)
@@ -508,6 +501,8 @@ int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
508 return bfin_internal_set_wake(IRQ_MAC_ERROR, state); 501 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
509#endif 502#endif
510} 503}
504#else
505# define bfin_mac_status_set_wake NULL
511#endif 506#endif
512 507
513static struct irq_chip bfin_mac_status_irqchip = { 508static struct irq_chip bfin_mac_status_irqchip = {
@@ -516,9 +511,7 @@ static struct irq_chip bfin_mac_status_irqchip = {
516 .irq_mask_ack = bfin_mac_status_mask_irq, 511 .irq_mask_ack = bfin_mac_status_mask_irq,
517 .irq_mask = bfin_mac_status_mask_irq, 512 .irq_mask = bfin_mac_status_mask_irq,
518 .irq_unmask = bfin_mac_status_unmask_irq, 513 .irq_unmask = bfin_mac_status_unmask_irq,
519#ifdef CONFIG_PM
520 .irq_set_wake = bfin_mac_status_set_wake, 514 .irq_set_wake = bfin_mac_status_set_wake,
521#endif
522}; 515};
523 516
524static void bfin_demux_mac_status_irq(unsigned int int_err_irq, 517static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
@@ -681,6 +674,8 @@ int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
681{ 674{
682 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); 675 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
683} 676}
677#else
678# define bfin_gpio_set_wake NULL
684#endif 679#endif
685 680
686static void bfin_demux_gpio_irq(unsigned int inta_irq, 681static void bfin_demux_gpio_irq(unsigned int inta_irq,
@@ -699,7 +694,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
699 irq = IRQ_PH0; 694 irq = IRQ_PH0;
700 break; 695 break;
701# endif 696# endif
702#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 697#elif defined(BF538_FAMILY)
703 case IRQ_PORTF_INTA: 698 case IRQ_PORTF_INTA:
704 irq = IRQ_PF0; 699 irq = IRQ_PF0;
705 break; 700 break;
@@ -1036,6 +1031,8 @@ void bfin_pm_restore(void)
1036 } 1031 }
1037 } 1032 }
1038} 1033}
1034#else
1035# define bfin_gpio_set_wake NULL
1039#endif 1036#endif
1040 1037
1041static void bfin_demux_gpio_irq(unsigned int inta_irq, 1038static void bfin_demux_gpio_irq(unsigned int inta_irq,
@@ -1088,9 +1085,7 @@ static struct irq_chip bfin_gpio_irqchip = {
1088 .irq_set_type = bfin_gpio_irq_type, 1085 .irq_set_type = bfin_gpio_irq_type,
1089 .irq_startup = bfin_gpio_irq_startup, 1086 .irq_startup = bfin_gpio_irq_startup,
1090 .irq_shutdown = bfin_gpio_irq_shutdown, 1087 .irq_shutdown = bfin_gpio_irq_shutdown,
1091#ifdef CONFIG_PM
1092 .irq_set_wake = bfin_gpio_set_wake, 1088 .irq_set_wake = bfin_gpio_set_wake,
1093#endif
1094}; 1089};
1095 1090
1096void __cpuinit init_exception_vectors(void) 1091void __cpuinit init_exception_vectors(void)
@@ -1124,12 +1119,12 @@ int __init init_arch_irq(void)
1124{ 1119{
1125 int irq; 1120 int irq;
1126 unsigned long ilat = 0; 1121 unsigned long ilat = 0;
1122
1127 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 1123 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1128#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ 1124#ifdef SIC_IMASK0
1129 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1130 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 1125 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1131 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 1126 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1132# ifdef CONFIG_BF54x 1127# ifdef SIC_IMASK2
1133 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 1128 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1134# endif 1129# endif
1135# ifdef CONFIG_SMP 1130# ifdef CONFIG_SMP
@@ -1183,7 +1178,7 @@ int __init init_arch_irq(void)
1183 case IRQ_PROG0_INTA: 1178 case IRQ_PROG0_INTA:
1184 case IRQ_PROG1_INTA: 1179 case IRQ_PROG1_INTA:
1185 case IRQ_PROG2_INTA: 1180 case IRQ_PROG2_INTA:
1186#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 1181#elif defined(BF538_FAMILY)
1187 case IRQ_PORTF_INTA: 1182 case IRQ_PORTF_INTA:
1188#endif 1183#endif
1189 irq_set_chained_handler(irq, bfin_demux_gpio_irq); 1184 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
@@ -1210,11 +1205,10 @@ int __init init_arch_irq(void)
1210 case IRQ_CORETMR: 1205 case IRQ_CORETMR:
1211# ifdef CONFIG_SMP 1206# ifdef CONFIG_SMP
1212 irq_set_handler(irq, handle_percpu_irq); 1207 irq_set_handler(irq, handle_percpu_irq);
1213 break;
1214# else 1208# else
1215 irq_set_handler(irq, handle_simple_irq); 1209 irq_set_handler(irq, handle_simple_irq);
1216 break;
1217# endif 1210# endif
1211 break;
1218#endif 1212#endif
1219 1213
1220#ifdef CONFIG_TICKSOURCE_GPTMR0 1214#ifdef CONFIG_TICKSOURCE_GPTMR0
@@ -1223,15 +1217,13 @@ int __init init_arch_irq(void)
1223 break; 1217 break;
1224#endif 1218#endif
1225 1219
1226#ifdef CONFIG_IPIPE
1227 default: 1220 default:
1221#ifdef CONFIG_IPIPE
1228 irq_set_handler(irq, handle_level_irq); 1222 irq_set_handler(irq, handle_level_irq);
1229 break; 1223#else
1230#else /* !CONFIG_IPIPE */
1231 default:
1232 irq_set_handler(irq, handle_simple_irq); 1224 irq_set_handler(irq, handle_simple_irq);
1225#endif
1233 break; 1226 break;
1234#endif /* !CONFIG_IPIPE */
1235 } 1227 }
1236 } 1228 }
1237 1229