5 files changed, 576 insertions, 2 deletions

diff --git a/arch/sh/include/asm/perf_event.h b/arch/sh/include/asm/perf_event.h
index 11a302297ab7..3d0c9f36d150 100644
--- a/arch/sh/include/asm/perf_event.h
+++ b/arch/sh/include/asm/perf_event.h
@@ -1,8 +1,35 @@
 #ifndef __ASM_SH_PERF_EVENT_H
 #define __ASM_SH_PERF_EVENT_H
 
-/* SH only supports software events through this interface. */
-static inline void set_perf_event_pending(void) {}
+struct hw_perf_event;
+
+#define MAX_HWEVENTS    2
+
+struct sh_pmu {
+        const char      *name;
+        unsigned int    num_events;
+        void            (*disable_all)(void);
+        void            (*enable_all)(void);
+        void            (*enable)(struct hw_perf_event *, int);
+        void            (*disable)(struct hw_perf_event *, int);
+        u64             (*read)(int);
+        int             (*event_map)(int);
+        unsigned int    max_events;
+        unsigned long   raw_event_mask;
+        const int       (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
+                                       [PERF_COUNT_HW_CACHE_OP_MAX]
+                                       [PERF_COUNT_HW_CACHE_RESULT_MAX];
+};
+
+/* arch/sh/kernel/perf_event.c */
+extern int register_sh_pmu(struct sh_pmu *);
+extern int reserve_pmc_hardware(void);
+extern void release_pmc_hardware(void);
+
+static inline void set_perf_event_pending(void)
+{
+        /* Nothing to see here, move along. */
+}
 
 #define PERF_EVENT_INDEX_OFFSET 0
 
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 097ae5ceb0e3..0a67bafce425 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
 obj-$(CONFIG_DUMP_CODE)         += disassemble.o
 obj-$(CONFIG_HIBERNATION)       += swsusp.o
 obj-$(CONFIG_DWARF_UNWINDER)    += dwarf.o
+obj-$(CONFIG_PERF_EVENTS)       += perf_event.o
 
 obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += localtimer.o
 
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 490d5dc9e372..33bab477d2e2 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -44,3 +44,4 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)	:= pinmux-sh7786.o
 obj-y                           += $(clock-y)
 obj-$(CONFIG_SMP)               += $(smp-y)
 obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
+obj-$(CONFIG_PERF_EVENTS)       += perf_event.o
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
new file mode 100644
index 000000000000..d0938345799f
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -0,0 +1,231 @@
+/*
+ * Performance events support for SH-4A performance counters
+ *
+ *  Copyright (C) 2009  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/perf_event.h>
+#include <asm/processor.h>
+
+#define PPC_CCBR(idx)   (0xff200800 + (sizeof(u32) * idx))
+#define PPC_PMCTR(idx)  (0xfc100000 + (sizeof(u32) * idx))
+
+#define CCBR_CIT_MASK   (0x7ff << 6)
+#define CCBR_DUC        (1 << 3)
+#define CCBR_CMDS       (1 << 1)
+#define CCBR_PPCE       (1 << 0)
+
+#define PPC_PMCAT       0xfc100080
+
+#define PMCAT_OVF3      (1 << 27)
+#define PMCAT_CNN3      (1 << 26)
+#define PMCAT_CLR3      (1 << 25)
+#define PMCAT_OVF2      (1 << 19)
+#define PMCAT_CLR2      (1 << 17)
+#define PMCAT_OVF1      (1 << 11)
+#define PMCAT_CNN1      (1 << 10)
+#define PMCAT_CLR1      (1 << 9)
+#define PMCAT_OVF0      (1 << 3)
+#define PMCAT_CLR0      (1 << 1)
+
+static struct sh_pmu sh4a_pmu;
+
+/*
+ * Special reserved bits used by hardware emulators, read values will
+ * vary, but writes must always be 0.
+ */
+#define PMCAT_EMU_CLR_MASK      ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
+
+static const int sh4a_general_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x0000,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x0202,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x0029,       /* I-cache */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x002a,       /* I-cache */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x0204,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = -1,
+        [PERF_COUNT_HW_BUS_CYCLES]              = -1,
+};
+
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+
+static const int sh4a_cache_events
+                        [PERF_COUNT_HW_CACHE_MAX]
+                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                        [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+        [ C(L1D) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0031,
+                        [ C(RESULT_MISS)   ] = 0x0032,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0039,
+                        [ C(RESULT_MISS)   ] = 0x003a,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(L1I) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0029,
+                        [ C(RESULT_MISS)   ] = 0x002a,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(LL) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0030,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0038,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(DTLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0222,
+                        [ C(RESULT_MISS)   ] = 0x0220,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(ITLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0x02a0,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+
+        [ C(BPU) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+};
+
+static int sh4a_event_map(int event)
+{
+        return sh4a_general_events[event];
+}
+
+static u64 sh4a_pmu_read(int idx)
+{
+        return __raw_readl(PPC_PMCTR(idx));
+}
+
+static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(PPC_CCBR(idx));
+        tmp &= ~(CCBR_CIT_MASK | CCBR_DUC);
+        __raw_writel(tmp, PPC_CCBR(idx));
+}
+
+static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(PPC_PMCAT);
+        tmp &= ~PMCAT_EMU_CLR_MASK;
+        tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0;
+        __raw_writel(tmp, PPC_PMCAT);
+
+        tmp = __raw_readl(PPC_CCBR(idx));
+        tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE;
+        __raw_writel(tmp, PPC_CCBR(idx));
+
+        __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
+}
+
+static void sh4a_pmu_disable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_pmu.num_events; i++)
+                __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
+}
+
+static void sh4a_pmu_enable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_pmu.num_events; i++)
+                __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
+}
+
+static struct sh_pmu sh4a_pmu = {
+        .name           = "SH-4A",
+        .num_events     = 2,
+        .event_map      = sh4a_event_map,
+        .max_events     = ARRAY_SIZE(sh4a_general_events),
+        .raw_event_mask = 0x3ff,
+        .cache_events   = &sh4a_cache_events,
+        .read           = sh4a_pmu_read,
+        .disable        = sh4a_pmu_disable,
+        .enable         = sh4a_pmu_enable,
+        .disable_all    = sh4a_pmu_disable_all,
+        .enable_all     = sh4a_pmu_enable_all,
+};
+
+static int __init sh4a_pmu_init(void)
+{
+        /*
+         * Make sure this CPU actually has perf counters.
+         */
+        if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
+                pr_notice("HW perf events unsupported, software events only.\n");
+                return -ENODEV;
+        }
+
+        return register_sh_pmu(&sh4a_pmu);
+}
+arch_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
new file mode 100644
index 000000000000..d1510702f201
--- /dev/null
+++ b/arch/sh/kernel/perf_event.c
@@ -0,0 +1,314 @@
+/*
+ * Performance event support framework for SuperH hardware counters.
+ *
+ *  Copyright (C) 2009  Paul Mundt
+ *
+ * Heavily based on the x86 and PowerPC implementations.
+ *
+ * x86:
+ *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
+ *  Copyright (C) 2009 Jaswinder Singh Rajput
+ *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
+ *
+ * ppc:
+ *  Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/perf_event.h>
+#include <asm/processor.h>
+
+struct cpu_hw_events {
+        struct perf_event       *events[MAX_HWEVENTS];
+        unsigned long           used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
+        unsigned long           active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
+};
+
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+
+static struct sh_pmu *sh_pmu __read_mostly;
+
+/* Number of perf_events counting hardware events */
+static atomic_t num_events;
+/* Used to avoid races in calling reserve/release_pmc_hardware */
+static DEFINE_MUTEX(pmc_reserve_mutex);
+
+/*
+ * Stub these out for now, do something more profound later.
+ */
+int reserve_pmc_hardware(void)
+{
+        return 0;
+}
+
+void release_pmc_hardware(void)
+{
+}
+
+static inline int sh_pmu_initialized(void)
+{
+        return !!sh_pmu;
+}
+
+/*
+ * Release the PMU if this is the last perf_event.
+ */
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+        if (!atomic_add_unless(&num_events, -1, 1)) {
+                mutex_lock(&pmc_reserve_mutex);
+                if (atomic_dec_return(&num_events) == 0)
+                        release_pmc_hardware();
+                mutex_unlock(&pmc_reserve_mutex);
+        }
+}
+
+static int hw_perf_cache_event(int config, int *evp)
+{
+        unsigned long type, op, result;
+        int ev;
+
+        if (!sh_pmu->cache_events)
+                return -EINVAL;
+
+        /* unpack config */
+        type = config & 0xff;
+        op = (config >> 8) & 0xff;
+        result = (config >> 16) & 0xff;
+
+        if (type >= PERF_COUNT_HW_CACHE_MAX ||
+            op >= PERF_COUNT_HW_CACHE_OP_MAX ||
+            result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return -EINVAL;
+
+        ev = (*sh_pmu->cache_events)[type][op][result];
+        if (ev == 0)
+                return -EOPNOTSUPP;
+        if (ev == -1)
+                return -EINVAL;
+        *evp = ev;
+        return 0;
+}
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+        struct perf_event_attr *attr = &event->attr;
+        struct hw_perf_event *hwc = &event->hw;
+        int config;
+        int err;
+
+        if (!sh_pmu_initialized())
+                return -ENODEV;
+
+        /*
+         * All of the on-chip counters are "limited", in that they have
+         * no interrupts, and are therefore unable to do sampling without
+         * further work and timer assistance.
+         */
+        if (hwc->sample_period)
+                return -EINVAL;
+
+        /*
+         * See if we need to reserve the counter.
+         *
+         * If no events are currently in use, then we have to take a
+         * mutex to ensure that we don't race with another task doing
+         * reserve_pmc_hardware or release_pmc_hardware.
+         */
+        err = 0;
+        if (!atomic_inc_not_zero(&num_events)) {
+                mutex_lock(&pmc_reserve_mutex);
+                if (atomic_read(&num_events) == 0 &&
+                    reserve_pmc_hardware())
+                        err = -EBUSY;
+                else
+                        atomic_inc(&num_events);
+                mutex_unlock(&pmc_reserve_mutex);
+        }
+
+        if (err)
+                return err;
+
+        event->destroy = hw_perf_event_destroy;
+
+        switch (attr->type) {
+        case PERF_TYPE_RAW:
+                config = attr->config & sh_pmu->raw_event_mask;
+                break;
+        case PERF_TYPE_HW_CACHE:
+                err = hw_perf_cache_event(attr->config, &config);
+                if (err)
+                        return err;
+                break;
+        case PERF_TYPE_HARDWARE:
+                if (attr->config >= sh_pmu->max_events)
+                        return -EINVAL;
+
+                config = sh_pmu->event_map(attr->config);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (config == -1)
+                return -EINVAL;
+
+        hwc->config |= config;
+
+        return 0;
+}
+
+static void sh_perf_event_update(struct perf_event *event,
+                                   struct hw_perf_event *hwc, int idx)
+{
+        u64 prev_raw_count, new_raw_count;
+        s64 delta;
+        int shift = 0;
+
+        /*
+         * Depending on the counter configuration, they may or may not
+         * be chained, in which case the previous counter value can be
+         * updated underneath us if the lower-half overflows.
+         *
+         * Our tactic to handle this is to first atomically read and
+         * exchange a new raw count - then add that new-prev delta
+         * count to the generic counter atomically.
+         *
+         * As there is no interrupt associated with the overflow events,
+         * this is the simplest approach for maintaining consistency.
+         */
+again:
+        prev_raw_count = atomic64_read(&hwc->prev_count);
+        new_raw_count = sh_pmu->read(idx);
+
+        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                             new_raw_count) != prev_raw_count)
+                goto again;
+
+        /*
+         * Now we have the new raw value and have updated the prev
+         * timestamp already. We can now calculate the elapsed delta
+         * (counter-)time and add that to the generic counter.
+         *
+         * Careful, not all hw sign-extends above the physical width
+         * of the count.
+         */
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+
+        atomic64_add(delta, &event->count);
+}
+
+static void sh_pmu_disable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        clear_bit(idx, cpuc->active_mask);
+        sh_pmu->disable(hwc, idx);
+
+        barrier();
+
+        sh_perf_event_update(event, &event->hw, idx);
+
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
+static int sh_pmu_enable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        if (test_and_set_bit(idx, cpuc->used_mask)) {
+                idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
+                if (idx == sh_pmu->num_events)
+                        return -EAGAIN;
+
+                set_bit(idx, cpuc->used_mask);
+                hwc->idx = idx;
+        }
+
+        sh_pmu->disable(hwc, idx);
+
+        cpuc->events[idx] = event;
+        set_bit(idx, cpuc->active_mask);
+
+        sh_pmu->enable(hwc, idx);
+
+        perf_event_update_userpage(event);
+
+        return 0;
+}
+
+static void sh_pmu_read(struct perf_event *event)
+{
+        sh_perf_event_update(event, &event->hw, event->hw.idx);
+}
+
+static const struct pmu pmu = {
+        .enable         = sh_pmu_enable,
+        .disable        = sh_pmu_disable,
+        .read           = sh_pmu_read,
+};
+
+const struct pmu *hw_perf_event_init(struct perf_event *event)
+{
+        int err = __hw_perf_event_init(event);
+        if (unlikely(err)) {
+                if (event->destroy)
+                        event->destroy(event);
+                return ERR_PTR(err);
+        }
+
+        return &pmu;
+}
+
+void hw_perf_event_setup(int cpu)
+{
+        struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
+
+        memset(cpuhw, 0, sizeof(struct cpu_hw_events));
+}
+
+void hw_perf_enable(void)
+{
+        if (!sh_pmu_initialized())
+                return;
+
+        sh_pmu->enable_all();
+}
+
+void hw_perf_disable(void)
+{
+        if (!sh_pmu_initialized())
+                return;
+
+        sh_pmu->disable_all();
+}
+
+int register_sh_pmu(struct sh_pmu *pmu)
+{
+        if (sh_pmu)
+                return -EBUSY;
+        sh_pmu = pmu;
+
+        pr_info("Performance Events: %s support registered\n", pmu->name);
+
+        WARN_ON(pmu->num_events >= MAX_HWEVENTS);
+
+        return 0;
+}