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-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S44
-rw-r--r--arch/arm/mach-omap2/io.c22
2 files changed, 37 insertions, 29 deletions
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1fc28a..60329411a636 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -38,41 +38,27 @@
38 */ 38 */
39 39
40#ifdef MULTI_OMAP2 40#ifdef MULTI_OMAP2
41
42/*
43 * We use __glue to avoid errors with multiple definitions of
44 * .globl omap_irq_base as it's included from entry-armv.S but not
45 * from entry-common.S.
46 */
47#ifdef __glue
41 .pushsection .data 48 .pushsection .data
42omap_irq_base: .word 0 49 .globl omap_irq_base
50omap_irq_base:
51 .word 0
43 .popsection 52 .popsection
53#endif
44 54
45 /* Configure the interrupt base on the first interrupt */ 55 /*
56 * Configure the interrupt base on the first interrupt.
57 * See also omap_irq_base_init for setting omap_irq_base.
58 */
46 .macro get_irqnr_preamble, base, tmp 59 .macro get_irqnr_preamble, base, tmp
479:
48 ldr \base, =omap_irq_base @ irq base address 60 ldr \base, =omap_irq_base @ irq base address
49 ldr \base, [\base, #0] @ irq base value 61 ldr \base, [\base, #0] @ irq base value
50 cmp \base, #0 @ already configured?
51 bne 9997f @ nothing to do
52
53 mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
54 and \tmp, \tmp, #0x000f0000 @ only check architecture
55 cmp \tmp, #0x00070000 @ is v6?
56 beq 2400f @ found v6 so it's omap24xx
57 mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
58 and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
59 cmp \tmp, #0x00000080 @ cortex A-8?
60 beq 3400f @ found A-8 so it's omap34xx
61 cmp \tmp, #0x00000090 @ cortex A-9?
62 beq 4400f @ found A-9 so it's omap44xx
632400: ldr \base, =OMAP2_IRQ_BASE
64 ldr \tmp, =omap_irq_base
65 str \base, [\tmp, #0]
66 b 9b
673400: ldr \base, =OMAP3_IRQ_BASE
68 ldr \tmp, =omap_irq_base
69 str \base, [\tmp, #0]
70 b 9b
714400: ldr \base, =OMAP4_IRQ_BASE
72 ldr \tmp, =omap_irq_base
73 str \base, [\tmp, #0]
74 b 9b
759997:
76 .endm 62 .endm
77 63
78 /* Check the pending interrupts. Note that base already set */ 64 /* Check the pending interrupts. Note that base already set */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 40562ddd3ee4..3d1834906293 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -46,6 +46,7 @@
46#include "clockdomains.h" 46#include "clockdomains.h"
47 47
48#include <plat/omap_hwmod.h> 48#include <plat/omap_hwmod.h>
49#include <plat/multi.h>
49 50
50/* 51/*
51 * The machine specific code may provide the extra mapping besides the 52 * The machine specific code may provide the extra mapping besides the
@@ -311,6 +312,25 @@ static int __init _omap2_init_reprogram_sdrc(void)
311 return v; 312 return v;
312} 313}
313 314
315/*
316 * Initialize asm_irq_base for entry-macro.S
317 */
318static inline void omap_irq_base_init(void)
319{
320 extern void __iomem *omap_irq_base;
321
322#ifdef MULTI_OMAP2
323 if (cpu_is_omap242x())
324 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
325 else if (cpu_is_omap34xx())
326 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
327 else if (cpu_is_omap44xx())
328 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
329 else
330 pr_err("Could not initialize omap_irq_base\n");
331#endif
332}
333
314void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, 334void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
315 struct omap_sdrc_params *sdrc_cs1) 335 struct omap_sdrc_params *sdrc_cs1)
316{ 336{
@@ -352,4 +372,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
352 _omap2_init_reprogram_sdrc(); 372 _omap2_init_reprogram_sdrc();
353 } 373 }
354 gpmc_init(); 374 gpmc_init();
375
376 omap_irq_base_init();
355} 377}