diff options
-rw-r--r-- | arch/arm/mm/context.c | 11 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 10 |
2 files changed, 10 insertions, 11 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index b0ee9ba3cfab..0d86298c7279 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c | |||
@@ -24,9 +24,7 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm); | |||
24 | 24 | ||
25 | /* | 25 | /* |
26 | * We fork()ed a process, and we need a new context for the child | 26 | * We fork()ed a process, and we need a new context for the child |
27 | * to run in. We reserve version 0 for initial tasks so we will | 27 | * to run in. |
28 | * always allocate an ASID. The ASID 0 is reserved for the TTBR | ||
29 | * register changing sequence. | ||
30 | */ | 28 | */ |
31 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) | 29 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
32 | { | 30 | { |
@@ -36,8 +34,11 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) | |||
36 | 34 | ||
37 | static void flush_context(void) | 35 | static void flush_context(void) |
38 | { | 36 | { |
39 | /* set the reserved ASID before flushing the TLB */ | 37 | u32 ttb; |
40 | asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); | 38 | /* Copy TTBR1 into TTBR0 */ |
39 | asm volatile("mrc p15, 0, %0, c2, c0, 1\n" | ||
40 | "mcr p15, 0, %0, c2, c0, 0" | ||
41 | : "=r" (ttb)); | ||
41 | isb(); | 42 | isb(); |
42 | local_flush_tlb_all(); | 43 | local_flush_tlb_all(); |
43 | if (icache_is_vivt_asid_tagged()) { | 44 | if (icache_is_vivt_asid_tagged()) { |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3c3867850a30..b3b566ec83d3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -108,18 +108,16 @@ ENTRY(cpu_v7_switch_mm) | |||
108 | #ifdef CONFIG_ARM_ERRATA_430973 | 108 | #ifdef CONFIG_ARM_ERRATA_430973 |
109 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB | 109 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
110 | #endif | 110 | #endif |
111 | #ifdef CONFIG_ARM_ERRATA_754322 | 111 | mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 |
112 | dsb | 112 | mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 |
113 | #endif | ||
114 | mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID | ||
115 | isb | ||
116 | 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | ||
117 | isb | 113 | isb |
118 | #ifdef CONFIG_ARM_ERRATA_754322 | 114 | #ifdef CONFIG_ARM_ERRATA_754322 |
119 | dsb | 115 | dsb |
120 | #endif | 116 | #endif |
121 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | 117 | mcr p15, 0, r1, c13, c0, 1 @ set context ID |
122 | isb | 118 | isb |
119 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | ||
120 | isb | ||
123 | #endif | 121 | #endif |
124 | mov pc, lr | 122 | mov pc, lr |
125 | ENDPROC(cpu_v7_switch_mm) | 123 | ENDPROC(cpu_v7_switch_mm) |