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-rw-r--r--drivers/edac/amd64_edac.c3
-rw-r--r--drivers/edac/amd64_edac.h8
2 files changed, 5 insertions, 6 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8d9def57232b..e6adc73e70ca 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -621,7 +621,6 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
621 BUG_ON(node_id > 7); 621 BUG_ON(node_id > 7);
622 622
623 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); 623 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
624
625 if (intlv_shift == 0) { 624 if (intlv_shift == 0) {
626 debugf1(" InputAddr 0x%lx translates to DramAddr of " 625 debugf1(" InputAddr 0x%lx translates to DramAddr of "
627 "same value\n", (unsigned long)input_addr); 626 "same value\n", (unsigned long)input_addr);
@@ -1192,7 +1191,7 @@ static void read_dram_ctl_register(struct amd64_pvt *pvt)
1192static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, 1191static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1193 bool hi_range_sel, u8 intlv_en) 1192 bool hi_range_sel, u8 intlv_en)
1194{ 1193{
1195 u32 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; 1194 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1196 1195
1197 if (dct_ganging_enabled(pvt)) 1196 if (dct_ganging_enabled(pvt))
1198 return 0; 1197 return 0;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 6220baeb3f1a..11be36a311eb 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -180,10 +180,10 @@
180#define DRAM_BASE_LO 0x40 180#define DRAM_BASE_LO 0x40
181#define DRAM_LIMIT_LO 0x44 181#define DRAM_LIMIT_LO 0x44
182 182
183#define dram_intlv_en(pvt, i) ((pvt->ranges[i].base.lo >> 8) & 0x7) 183#define dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
184#define dram_rw(pvt, i) (pvt->ranges[i].base.lo & 0x3) 184#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
185#define dram_intlv_sel(pvt, i) ((pvt->ranges[i].lim.lo >> 8) & 0x7) 185#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
186#define dram_dst_node(pvt, i) (pvt->ranges[i].lim.lo & 0x7) 186#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
187 187
188#define DHAR 0xf0 188#define DHAR 0xf0
189#define dhar_valid(pvt) ((pvt)->dhar & BIT(0)) 189#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))