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-rw-r--r--arch/sh/Kconfig13
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/boards/mpc1211/Makefile8
-rw-r--r--arch/sh/boards/mpc1211/pci.c295
-rw-r--r--arch/sh/boards/mpc1211/rtc.c136
-rw-r--r--arch/sh/boards/mpc1211/setup.c347
-rw-r--r--arch/sh/tools/mach-types1
-rw-r--r--drivers/mtd/maps/Kconfig7
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/mpc1211.c80
-rw-r--r--include/asm-sh/keyboard.h13
-rw-r--r--include/asm-sh/mpc1211/dma.h303
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h60
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h38
18 files changed, 2 insertions, 1547 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 563f8af08508..8a68160079a9 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -448,14 +448,6 @@ config SH_DREAMCAST
448 Select Dreamcast if configuring for a SEGA Dreamcast. 448 Select Dreamcast if configuring for a SEGA Dreamcast.
449 More information at <http://www.linux-sh.org> 449 More information at <http://www.linux-sh.org>
450 450
451config SH_MPC1211
452 bool "Interface MPC1211"
453 depends on CPU_SUBTYPE_SH7751 && BROKEN
454 help
455 CTP/PCI-SH02 is a CPU module computer that is produced
456 by Interface Corporation.
457 More information at <http://www.interface.co.jp>
458
459config SH_SH03 451config SH_SH03
460 bool "Interface CTP/PCI-SH03" 452 bool "Interface CTP/PCI-SH03"
461 depends on CPU_SUBTYPE_SH7751 453 depends on CPU_SUBTYPE_SH7751
@@ -657,8 +649,7 @@ source "arch/sh/drivers/Kconfig"
657endmenu 649endmenu
658 650
659config ISA_DMA_API 651config ISA_DMA_API
660 def_bool y 652 bool
661 depends on SH_MPC1211
662 653
663menu "Kernel features" 654menu "Kernel features"
664 655
@@ -763,7 +754,7 @@ menu "Boot options"
763 754
764config ZERO_PAGE_OFFSET 755config ZERO_PAGE_OFFSET
765 hex "Zero page offset" 756 hex "Zero page offset"
766 default "0x00004000" if SH_MPC1211 || SH_SH03 757 default "0x00004000" if SH_SH03
767 default "0x00010000" if PAGE_SIZE_64KB 758 default "0x00010000" if PAGE_SIZE_64KB
768 default "0x00002000" if PAGE_SIZE_8KB 759 default "0x00002000" if PAGE_SIZE_8KB
769 default "0x00001000" 760 default "0x00001000"
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index bb06f83e6239..8050b03d51fc 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -110,7 +110,6 @@ machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) += se/7343
110machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += se/7721 110machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += se/7721
111machdir-$(CONFIG_SH_HP6XX) += hp6xx 111machdir-$(CONFIG_SH_HP6XX) += hp6xx
112machdir-$(CONFIG_SH_DREAMCAST) += dreamcast 112machdir-$(CONFIG_SH_DREAMCAST) += dreamcast
113machdir-$(CONFIG_SH_MPC1211) += mpc1211
114machdir-$(CONFIG_SH_SH03) += sh03 113machdir-$(CONFIG_SH_SH03) += sh03
115machdir-$(CONFIG_SH_SECUREEDGE5410) += snapgear 114machdir-$(CONFIG_SH_SECUREEDGE5410) += snapgear
116machdir-$(CONFIG_SH_RTS7751R2D) += renesas/rts7751r2d 115machdir-$(CONFIG_SH_RTS7751R2D) += renesas/rts7751r2d
diff --git a/arch/sh/boards/mpc1211/Makefile b/arch/sh/boards/mpc1211/Makefile
deleted file mode 100644
index 8cd31b5d200b..000000000000
--- a/arch/sh/boards/mpc1211/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the Interface (CTP/PCI/MPC-SH02) specific parts of the kernel
3#
4
5obj-y := setup.o rtc.o
6
7obj-$(CONFIG_PCI) += pci.o
8
diff --git a/arch/sh/boards/mpc1211/pci.c b/arch/sh/boards/mpc1211/pci.c
deleted file mode 100644
index 23849f70f133..000000000000
--- a/arch/sh/boards/mpc1211/pci.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * Low-Level PCI Support for the MPC-1211(CTP/PCI/MPC-SH02)
3 *
4 * (c) 2002-2003 Saito.K & Jeanne
5 *
6 * Dustin McIntire (dustin@sensoria.com)
7 * Derived from arch/i386/kernel/pci-*.c which bore the message:
8 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 */
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/ioport.h>
21#include <linux/errno.h>
22#include <linux/irq.h>
23#include <linux/interrupt.h>
24
25#include <asm/machvec.h>
26#include <asm/io.h>
27#include <asm/mpc1211/pci.h>
28
29static struct resource mpcpci_io_resource = {
30 "MPCPCI IO",
31 0x00000000,
32 0xffffffff,
33 IORESOURCE_IO
34};
35
36static struct resource mpcpci_mem_resource = {
37 "MPCPCI mem",
38 0x00000000,
39 0xffffffff,
40 IORESOURCE_MEM
41};
42
43static struct pci_ops pci_direct_conf1;
44struct pci_channel board_pci_channels[] = {
45 {&pci_direct_conf1, &mpcpci_io_resource, &mpcpci_mem_resource, 0, 256},
46 {NULL, NULL, NULL, 0, 0},
47};
48
49/*
50 * Direct access to PCI hardware...
51 */
52
53
54#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
55
56/*
57 * Functions for accessing PCI configuration space with type 1 accesses
58 */
59static int pci_conf1_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
60{
61 u32 word;
62 unsigned long flags;
63
64 /*
65 * PCIPDR may only be accessed as 32 bit words,
66 * so we must do byte alignment by hand
67 */
68 local_irq_save(flags);
69 writel(CONFIG_CMD(bus,devfn,where), PCIPAR);
70 word = readl(PCIPDR);
71 local_irq_restore(flags);
72
73 switch (size) {
74 case 1:
75 switch (where & 0x3) {
76 case 3:
77 *value = (u8)(word >> 24);
78 break;
79 case 2:
80 *value = (u8)(word >> 16);
81 break;
82 case 1:
83 *value = (u8)(word >> 8);
84 break;
85 default:
86 *value = (u8)word;
87 break;
88 }
89 break;
90 case 2:
91 switch (where & 0x3) {
92 case 3:
93 *value = (u16)(word >> 24);
94 local_irq_save(flags);
95 writel(CONFIG_CMD(bus,devfn,(where+1)), PCIPAR);
96 word = readl(PCIPDR);
97 local_irq_restore(flags);
98 *value |= ((word & 0xff) << 8);
99 break;
100 case 2:
101 *value = (u16)(word >> 16);
102 break;
103 case 1:
104 *value = (u16)(word >> 8);
105 break;
106 default:
107 *value = (u16)word;
108 break;
109 }
110 break;
111 case 4:
112 *value = word;
113 break;
114 }
115 PCIDBG(4,"pci_conf1_read@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),*value);
116 return PCIBIOS_SUCCESSFUL;
117}
118
119/*
120 * Since MPC-1211 only does 32bit access we'll have to do a read,mask,write operation.
121 * We'll allow an odd byte offset, though it should be illegal.
122 */
123static int pci_conf1_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
124{
125 u32 word,mask = 0;
126 unsigned long flags;
127 u32 shift = (where & 3) * 8;
128
129 if(size == 1) {
130 mask = ((1 << 8) - 1) << shift; // create the byte mask
131 } else if(size == 2){
132 if(shift == 24)
133 return PCIBIOS_BAD_REGISTER_NUMBER;
134 mask = ((1 << 16) - 1) << shift; // create the word mask
135 }
136 local_irq_save(flags);
137 writel(CONFIG_CMD(bus,devfn,where), PCIPAR);
138 if(size == 4){
139 writel(value, PCIPDR);
140 local_irq_restore(flags);
141 PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),value);
142 return PCIBIOS_SUCCESSFUL;
143 }
144 word = readl(PCIPDR);
145 word &= ~mask;
146 word |= ((value << shift) & mask);
147 writel(word, PCIPDR);
148 local_irq_restore(flags);
149 PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),word);
150 return PCIBIOS_SUCCESSFUL;
151}
152
153#undef CONFIG_CMD
154
155static struct pci_ops pci_direct_conf1 = {
156 .read = pci_conf1_read,
157 .write = pci_conf1_write,
158};
159
160static void __devinit quirk_ali_ide_ports(struct pci_dev *dev)
161{
162 dev->resource[0].start = 0x1f0;
163 dev->resource[0].end = 0x1f7;
164 dev->resource[0].flags = IORESOURCE_IO;
165 dev->resource[1].start = 0x3f6;
166 dev->resource[1].end = 0x3f6;
167 dev->resource[1].flags = IORESOURCE_IO;
168 dev->resource[2].start = 0x170;
169 dev->resource[2].end = 0x177;
170 dev->resource[2].flags = IORESOURCE_IO;
171 dev->resource[3].start = 0x376;
172 dev->resource[3].end = 0x376;
173 dev->resource[3].flags = IORESOURCE_IO;
174 dev->resource[4].start = 0xf000;
175 dev->resource[4].end = 0xf00f;
176 dev->resource[4].flags = IORESOURCE_IO;
177}
178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, quirk_ali_ide_ports);
179
180char * __devinit pcibios_setup(char *str)
181{
182 return str;
183}
184
185/*
186 * Called after each bus is probed, but before its children
187 * are examined.
188 */
189
190void __devinit pcibios_fixup_bus(struct pci_bus *b)
191{
192 pci_read_bridge_bases(b);
193}
194
195/*
196 * IRQ functions
197 */
198static inline u8 bridge_swizzle(u8 pin, u8 slot)
199{
200 return (((pin-1) + slot) % 4) + 1;
201}
202
203static inline u8 bridge_swizzle_pci_1(u8 pin, u8 slot)
204{
205 return (((pin-1) - slot) & 3) + 1;
206}
207
208static u8 __init mpc1211_swizzle(struct pci_dev *dev, u8 *pinp)
209{
210 unsigned long flags;
211 u8 pin = *pinp;
212 u32 word;
213
214 for ( ; dev->bus->self; dev = dev->bus->self) {
215 if (!pin)
216 continue;
217
218 if (dev->bus->number == 1) {
219 local_irq_save(flags);
220 writel(0x80000000 | 0x2c, PCIPAR);
221 word = readl(PCIPDR);
222 local_irq_restore(flags);
223 word >>= 16;
224
225 if (word == 0x0001)
226 pin = bridge_swizzle_pci_1(pin, PCI_SLOT(dev->devfn));
227 else
228 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
229 } else
230 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
231 }
232
233 *pinp = pin;
234
235 return PCI_SLOT(dev->devfn);
236}
237
238static int __init map_mpc1211_irq(struct pci_dev *dev, u8 slot, u8 pin)
239{
240 int irq = -1;
241
242 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
243 if (dev->bus->number == 0) {
244 switch (slot) {
245 case 13: irq = 9; break; /* USB */
246 case 22: irq = 10; break; /* LAN */
247 default: irq = 0; break;
248 }
249 } else {
250 switch (pin) {
251 case 0: irq = 0; break;
252 case 1: irq = 7; break;
253 case 2: irq = 9; break;
254 case 3: irq = 10; break;
255 case 4: irq = 11; break;
256 }
257 }
258
259 if( irq < 0 ) {
260 PCIDBG(3, "PCI: Error mapping IRQ on device %s\n", pci_name(dev));
261 return irq;
262 }
263
264 PCIDBG(2, "Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
265
266 return irq;
267}
268
269void __init pcibios_fixup_irqs(void)
270{
271 pci_fixup_irqs(mpc1211_swizzle, map_mpc1211_irq);
272}
273
274void pcibios_align_resource(void *data, struct resource *res,
275 resource_size_t size, resource_size_t align)
276{
277 resource_size_t start = res->start;
278
279 if (res->flags & IORESOURCE_IO) {
280 if (start >= 0x10000UL) {
281 if ((start & 0xffffUL) < 0x4000UL) {
282 start = (start & 0xffff0000UL) + 0x4000UL;
283 } else if ((start & 0xffffUL) >= 0xf000UL) {
284 start = (start & 0xffff0000UL) + 0x10000UL;
285 }
286 res->start = start;
287 } else {
288 if (start & 0x300) {
289 start = (start + 0x3ff) & ~0x3ff;
290 res->start = start;
291 }
292 }
293 }
294}
295
diff --git a/arch/sh/boards/mpc1211/rtc.c b/arch/sh/boards/mpc1211/rtc.c
deleted file mode 100644
index 03b123a4bba4..000000000000
--- a/arch/sh/boards/mpc1211/rtc.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * linux/arch/sh/kernel/rtc-mpc1211.c -- MPC-1211 on-chip RTC support
3 *
4 * Copyright (C) 2002 Saito.K & Jeanne
5 *
6 */
7
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/time.h>
12#include <linux/bcd.h>
13#include <linux/mc146818rtc.h>
14
15unsigned long get_cmos_time(void)
16{
17 unsigned int year, mon, day, hour, min, sec;
18
19 spin_lock(&rtc_lock);
20
21 do {
22 sec = CMOS_READ(RTC_SECONDS);
23 min = CMOS_READ(RTC_MINUTES);
24 hour = CMOS_READ(RTC_HOURS);
25 day = CMOS_READ(RTC_DAY_OF_MONTH);
26 mon = CMOS_READ(RTC_MONTH);
27 year = CMOS_READ(RTC_YEAR);
28 } while (sec != CMOS_READ(RTC_SECONDS));
29
30 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
31 BCD_TO_BIN(sec);
32 BCD_TO_BIN(min);
33 BCD_TO_BIN(hour);
34 BCD_TO_BIN(day);
35 BCD_TO_BIN(mon);
36 BCD_TO_BIN(year);
37 }
38
39 spin_unlock(&rtc_lock);
40
41 year += 1900;
42 if (year < 1970)
43 year += 100;
44
45 return mktime(year, mon, day, hour, min, sec);
46}
47
48void mpc1211_rtc_gettimeofday(struct timeval *tv)
49{
50
51 tv->tv_sec = get_cmos_time();
52 tv->tv_usec = 0;
53}
54
55/* arc/i386/kernel/time.c */
56/*
57 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
58 * called 500 ms after the second nowtime has started, because when
59 * nowtime is written into the registers of the CMOS clock, it will
60 * jump to the next second precisely 500 ms later. Check the Motorola
61 * MC146818A or Dallas DS12887 data sheet for details.
62 *
63 * BUG: This routine does not handle hour overflow properly; it just
64 * sets the minutes. Usually you'll only notice that after reboot!
65 */
66static int set_rtc_mmss(unsigned long nowtime)
67{
68 int retval = 0;
69 int real_seconds, real_minutes, cmos_minutes;
70 unsigned char save_control, save_freq_select;
71
72 /* gets recalled with irq locally disabled */
73 spin_lock(&rtc_lock);
74 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
75 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
76
77 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
78 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
79
80 cmos_minutes = CMOS_READ(RTC_MINUTES);
81 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
82 BCD_TO_BIN(cmos_minutes);
83
84 /*
85 * since we're only adjusting minutes and seconds,
86 * don't interfere with hour overflow. This avoids
87 * messing with unknown time zones but requires your
88 * RTC not to be off by more than 15 minutes
89 */
90 real_seconds = nowtime % 60;
91 real_minutes = nowtime / 60;
92 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
93 real_minutes += 30; /* correct for half hour time zone */
94 real_minutes %= 60;
95
96 if (abs(real_minutes - cmos_minutes) < 30) {
97 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
98 BIN_TO_BCD(real_seconds);
99 BIN_TO_BCD(real_minutes);
100 }
101 CMOS_WRITE(real_seconds,RTC_SECONDS);
102 CMOS_WRITE(real_minutes,RTC_MINUTES);
103 } else {
104 printk(KERN_WARNING
105 "set_rtc_mmss: can't update from %d to %d\n",
106 cmos_minutes, real_minutes);
107 retval = -1;
108 }
109
110 /* The following flags have to be released exactly in this order,
111 * otherwise the DS12887 (popular MC146818A clone with integrated
112 * battery and quartz) will not reset the oscillator and will not
113 * update precisely 500 ms later. You won't find this mentioned in
114 * the Dallas Semiconductor data sheets, but who believes data
115 * sheets anyway ... -- Markus Kuhn
116 */
117 CMOS_WRITE(save_control, RTC_CONTROL);
118 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
119 spin_unlock(&rtc_lock);
120
121 return retval;
122}
123
124int mpc1211_rtc_settimeofday(const struct timeval *tv)
125{
126 unsigned long nowtime = tv->tv_sec;
127
128 return set_rtc_mmss(nowtime);
129}
130
131void mpc1211_time_init(void)
132{
133 rtc_sh_get_time = mpc1211_rtc_gettimeofday;
134 rtc_sh_set_time = mpc1211_rtc_settimeofday;
135}
136
diff --git a/arch/sh/boards/mpc1211/setup.c b/arch/sh/boards/mpc1211/setup.c
deleted file mode 100644
index fede36361dc7..000000000000
--- a/arch/sh/boards/mpc1211/setup.c
+++ /dev/null
@@ -1,347 +0,0 @@
1/*
2 * linux/arch/sh/boards/mpc1211/setup.c
3 *
4 * Copyright (C) 2002 Saito.K & Jeanne, Fujii.Y
5 *
6 */
7
8#include <linux/init.h>
9#include <linux/irq.h>
10#include <linux/hdreg.h>
11#include <linux/ide.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <asm/io.h>
15#include <asm/machvec.h>
16#include <asm/mpc1211/mpc1211.h>
17#include <asm/mpc1211/pci.h>
18#include <asm/mpc1211/m1543c.h>
19
20/* ALI15X3 SMBus address offsets */
21#define SMBHSTSTS (0 + 0x3100)
22#define SMBHSTCNT (1 + 0x3100)
23#define SMBHSTSTART (2 + 0x3100)
24#define SMBHSTCMD (7 + 0x3100)
25#define SMBHSTADD (3 + 0x3100)
26#define SMBHSTDAT0 (4 + 0x3100)
27#define SMBHSTDAT1 (5 + 0x3100)
28#define SMBBLKDAT (6 + 0x3100)
29
30/* Other settings */
31#define MAX_TIMEOUT 500 /* times 1/100 sec */
32
33/* ALI15X3 command constants */
34#define ALI15X3_ABORT 0x04
35#define ALI15X3_T_OUT 0x08
36#define ALI15X3_QUICK 0x00
37#define ALI15X3_BYTE 0x10
38#define ALI15X3_BYTE_DATA 0x20
39#define ALI15X3_WORD_DATA 0x30
40#define ALI15X3_BLOCK_DATA 0x40
41#define ALI15X3_BLOCK_CLR 0x80
42
43/* ALI15X3 status register bits */
44#define ALI15X3_STS_IDLE 0x04
45#define ALI15X3_STS_BUSY 0x08
46#define ALI15X3_STS_DONE 0x10
47#define ALI15X3_STS_DEV 0x20 /* device error */
48#define ALI15X3_STS_COLL 0x40 /* collision or no response */
49#define ALI15X3_STS_TERM 0x80 /* terminated by abort */
50#define ALI15X3_STS_ERR 0xE0 /* all the bad error bits */
51
52static void __init pci_write_config(unsigned long busNo,
53 unsigned long devNo,
54 unsigned long fncNo,
55 unsigned long cnfAdd,
56 unsigned long cnfData)
57{
58 ctrl_outl((0x80000000
59 + ((busNo & 0xff) << 16)
60 + ((devNo & 0x1f) << 11)
61 + ((fncNo & 0x07) << 8)
62 + (cnfAdd & 0xfc)), PCIPAR);
63
64 ctrl_outl(cnfData, PCIPDR);
65}
66
67/*
68 Initialize IRQ setting
69*/
70
71static unsigned char m_irq_mask = 0xfb;
72static unsigned char s_irq_mask = 0xff;
73
74static void disable_mpc1211_irq(unsigned int irq)
75{
76 if( irq < 8) {
77 m_irq_mask |= (1 << irq);
78 outb(m_irq_mask,I8259_M_MR);
79 } else {
80 s_irq_mask |= (1 << (irq - 8));
81 outb(s_irq_mask,I8259_S_MR);
82 }
83
84}
85
86static void enable_mpc1211_irq(unsigned int irq)
87{
88 if( irq < 8) {
89 m_irq_mask &= ~(1 << irq);
90 outb(m_irq_mask,I8259_M_MR);
91 } else {
92 s_irq_mask &= ~(1 << (irq - 8));
93 outb(s_irq_mask,I8259_S_MR);
94 }
95}
96
97static inline int mpc1211_irq_real(unsigned int irq)
98{
99 int value;
100 int irqmask;
101
102 if ( irq < 8) {
103 irqmask = 1<<irq;
104 outb(0x0b,I8259_M_CR); /* ISR register */
105 value = inb(I8259_M_CR) & irqmask;
106 outb(0x0a,I8259_M_CR); /* back ro the IPR reg */
107 return value;
108 }
109 irqmask = 1<<(irq - 8);
110 outb(0x0b,I8259_S_CR); /* ISR register */
111 value = inb(I8259_S_CR) & irqmask;
112 outb(0x0a,I8259_S_CR); /* back ro the IPR reg */
113 return value;
114}
115
116static void mask_and_ack_mpc1211(unsigned int irq)
117{
118 if(irq < 8) {
119 if(m_irq_mask & (1<<irq)){
120 if(!mpc1211_irq_real(irq)){
121 atomic_inc(&irq_err_count)
122 printk("spurious 8259A interrupt: IRQ %x\n",irq);
123 }
124 } else {
125 m_irq_mask |= (1<<irq);
126 }
127 inb(I8259_M_MR); /* DUMMY */
128 outb(m_irq_mask,I8259_M_MR); /* disable */
129 outb(0x60+irq,I8259_M_CR); /* EOI */
130
131 } else {
132 if(s_irq_mask & (1<<(irq - 8))){
133 if(!mpc1211_irq_real(irq)){
134 atomic_inc(&irq_err_count);
135 printk("spurious 8259A interrupt: IRQ %x\n",irq);
136 }
137 } else {
138 s_irq_mask |= (1<<(irq - 8));
139 }
140 inb(I8259_S_MR); /* DUMMY */
141 outb(s_irq_mask,I8259_S_MR); /* disable */
142 outb(0x60+(irq-8),I8259_S_CR); /* EOI */
143 outb(0x60+2,I8259_M_CR);
144 }
145}
146
147static void end_mpc1211_irq(unsigned int irq)
148{
149 enable_mpc1211_irq(irq);
150}
151
152static unsigned int startup_mpc1211_irq(unsigned int irq)
153{
154 enable_mpc1211_irq(irq);
155 return 0;
156}
157
158static void shutdown_mpc1211_irq(unsigned int irq)
159{
160 disable_mpc1211_irq(irq);
161}
162
163static struct hw_interrupt_type mpc1211_irq_type = {
164 .typename = "MPC1211-IRQ",
165 .startup = startup_mpc1211_irq,
166 .shutdown = shutdown_mpc1211_irq,
167 .enable = enable_mpc1211_irq,
168 .disable = disable_mpc1211_irq,
169 .ack = mask_and_ack_mpc1211,
170 .end = end_mpc1211_irq
171};
172
173static void make_mpc1211_irq(unsigned int irq)
174{
175 irq_desc[irq].chip = &mpc1211_irq_type;
176 irq_desc[irq].status = IRQ_DISABLED;
177 irq_desc[irq].action = 0;
178 irq_desc[irq].depth = 1;
179 disable_mpc1211_irq(irq);
180}
181
182int mpc1211_irq_demux(int irq)
183{
184 unsigned int poll;
185
186 if( irq == 2 ) {
187 outb(0x0c,I8259_M_CR);
188 poll = inb(I8259_M_CR);
189 if(poll & 0x80) {
190 irq = (poll & 0x07);
191 }
192 if( irq == 2) {
193 outb(0x0c,I8259_S_CR);
194 poll = inb(I8259_S_CR);
195 irq = (poll & 0x07) + 8;
196 }
197 }
198 return irq;
199}
200
201static void __init init_mpc1211_IRQ(void)
202{
203 int i;
204 /*
205 * Super I/O (Just mimic PC):
206 * 1: keyboard
207 * 3: serial 1
208 * 4: serial 0
209 * 5: printer
210 * 6: floppy
211 * 8: rtc
212 * 10: lan
213 * 12: mouse
214 * 14: ide0
215 * 15: ide1
216 */
217
218 pci_write_config(0,0,0,0x54, 0xb0b0002d);
219 outb(0x11, I8259_M_CR); /* mater icw1 edge trigger */
220 outb(0x11, I8259_S_CR); /* slave icw1 edge trigger */
221 outb(0x20, I8259_M_MR); /* m icw2 base vec 0x08 */
222 outb(0x28, I8259_S_MR); /* s icw2 base vec 0x70 */
223 outb(0x04, I8259_M_MR); /* m icw3 slave irq2 */
224 outb(0x02, I8259_S_MR); /* s icw3 slave id */
225 outb(0x01, I8259_M_MR); /* m icw4 non buf normal eoi*/
226 outb(0x01, I8259_S_MR); /* s icw4 non buf normal eo1*/
227 outb(0xfb, I8259_M_MR); /* disable irq0--irq7 */
228 outb(0xff, I8259_S_MR); /* disable irq8--irq15 */
229
230 for ( i=0; i < 16; i++) {
231 if(i != 2) {
232 make_mpc1211_irq(i);
233 }
234 }
235}
236
237static void delay1000(void)
238{
239 int i;
240
241 for (i=0; i<1000; i++)
242 ctrl_delay();
243}
244
245static int put_smb_blk(unsigned char *p, int address, int command, int no)
246{
247 int temp;
248 int timeout;
249 int i;
250
251 outb(0xff, SMBHSTSTS);
252 temp = inb(SMBHSTSTS);
253 for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & ALI15X3_STS_IDLE); timeout++) {
254 delay1000();
255 temp = inb(SMBHSTSTS);
256 }
257 if (timeout >= MAX_TIMEOUT){
258 return -1;
259 }
260
261 outb(((address & 0x7f) << 1), SMBHSTADD);
262 outb(0xc0, SMBHSTCNT);
263 outb(command & 0xff, SMBHSTCMD);
264 outb(no & 0x1f, SMBHSTDAT0);
265
266 for(i = 1; i <= no; i++) {
267 outb(*p++, SMBBLKDAT);
268 }
269 outb(0xff, SMBHSTSTART);
270
271 temp = inb(SMBHSTSTS);
272 for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & (ALI15X3_STS_ERR | ALI15X3_STS_DONE)); timeout++) {
273 delay1000();
274 temp = inb(SMBHSTSTS);
275 }
276 if (timeout >= MAX_TIMEOUT) {
277 return -2;
278 }
279 if ( temp & ALI15X3_STS_ERR ){
280 return -3;
281 }
282 return 0;
283}
284
285static struct resource heartbeat_resources[] = {
286 [0] = {
287 .start = 0xa2000000,
288 .end = 0xa2000000,
289 .flags = IORESOURCE_MEM,
290 },
291};
292
293static struct platform_device heartbeat_device = {
294 .name = "heartbeat",
295 .id = -1,
296 .num_resources = ARRAY_SIZE(heartbeat_resources),
297 .resource = heartbeat_resources,
298};
299
300static struct platform_device *mpc1211_devices[] __initdata = {
301 &heartbeat_device,
302};
303
304static int __init mpc1211_devices_setup(void)
305{
306 return platform_add_devices(mpc1211_devices,
307 ARRAY_SIZE(mpc1211_devices));
308}
309__initcall(mpc1211_devices_setup);
310
311/* arch/sh/boards/mpc1211/rtc.c */
312void mpc1211_time_init(void);
313
314static void __init mpc1211_setup(char **cmdline_p)
315{
316 unsigned char spd_buf[128];
317
318 __set_io_port_base(PA_PCI_IO);
319
320 pci_write_config(0,0,0,0x54, 0xb0b00000);
321
322 do {
323 outb(ALI15X3_ABORT, SMBHSTCNT);
324 spd_buf[0] = 0x0c;
325 spd_buf[1] = 0x43;
326 spd_buf[2] = 0x7f;
327 spd_buf[3] = 0x03;
328 spd_buf[4] = 0x00;
329 spd_buf[5] = 0x03;
330 spd_buf[6] = 0x00;
331 } while (put_smb_blk(spd_buf, 0x69, 0, 7) < 0);
332
333 board_time_init = mpc1211_time_init;
334
335 return 0;
336}
337
338/*
339 * The Machine Vector
340 */
341static struct sh_machine_vector mv_mpc1211 __initmv = {
342 .mv_name = "Interface MPC-1211(CTP/PCI/MPC-SH02)",
343 .mv_setup = mpc1211_setup,
344 .mv_nr_irqs = 48,
345 .mv_irq_demux = mpc1211_irq_demux,
346 .mv_init_irq = init_mpc1211_IRQ,
347};
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 987c6682bf99..1bba7d36be90 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -28,7 +28,6 @@ HD64465 HD64465
287751SYSTEMH SH_7751_SYSTEMH 287751SYSTEMH SH_7751_SYSTEMH
29HP6XX SH_HP6XX 29HP6XX SH_HP6XX
30DREAMCAST SH_DREAMCAST 30DREAMCAST SH_DREAMCAST
31MPC1211 SH_MPC1211
32SNAPGEAR SH_SECUREEDGE5410 31SNAPGEAR SH_SECUREEDGE5410
33EDOSK7705 SH_EDOSK7705 32EDOSK7705 SH_EDOSK7705
34SH4202_MICRODEV SH_SH4202_MICRODEV 33SH4202_MICRODEV SH_SH4202_MICRODEV
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 1bd69aa9e22a..7b031ac904db 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -480,13 +480,6 @@ config MTD_H720X
480 This enables access to the flash chips on the Hynix evaluation boards. 480 This enables access to the flash chips on the Hynix evaluation boards.
481 If you have such a board, say 'Y'. 481 If you have such a board, say 'Y'.
482 482
483config MTD_MPC1211
484 tristate "CFI Flash device mapped on Interface MPC-1211"
485 depends on SH_MPC1211 && MTD_CFI
486 help
487 This enables access to the flash chips on the Interface MPC-1211(CTP/PCI/MPC-SH02).
488 If you have such a board, say 'Y'.
489
490config MTD_OMAP_NOR 483config MTD_OMAP_NOR
491 tristate "TI OMAP board mappings" 484 tristate "TI OMAP board mappings"
492 depends on MTD_CFI && ARCH_OMAP 485 depends on MTD_CFI && ARCH_OMAP
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index a9cbe80f99a0..957fb5f70f5e 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -58,7 +58,6 @@ obj-$(CONFIG_MTD_WALNUT) += walnut.o
58obj-$(CONFIG_MTD_H720X) += h720x-flash.o 58obj-$(CONFIG_MTD_H720X) += h720x-flash.o
59obj-$(CONFIG_MTD_SBC8240) += sbc8240.o 59obj-$(CONFIG_MTD_SBC8240) += sbc8240.o
60obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o 60obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o
61obj-$(CONFIG_MTD_MPC1211) += mpc1211.o
62obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o 61obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
63obj-$(CONFIG_MTD_IXP2000) += ixp2000.o 62obj-$(CONFIG_MTD_IXP2000) += ixp2000.o
64obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o 63obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
diff --git a/drivers/mtd/maps/mpc1211.c b/drivers/mtd/maps/mpc1211.c
deleted file mode 100644
index 45a00fac88ac..000000000000
--- a/drivers/mtd/maps/mpc1211.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Flash on MPC-1211
3 *
4 * $Id: mpc1211.c,v 1.4 2004/09/16 23:27:13 gleixner Exp $
5 *
6 * (C) 2002 Interface, Saito.K & Jeanne
7 *
8 * GPL'd
9 */
10
11#include <linux/module.h>
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <asm/io.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/map.h>
17#include <linux/mtd/partitions.h>
18
19static struct mtd_info *flash_mtd;
20static struct mtd_partition *parsed_parts;
21
22struct map_info mpc1211_flash_map = {
23 .name = "MPC-1211 FLASH",
24 .size = 0x80000,
25 .bankwidth = 1,
26};
27
28static struct mtd_partition mpc1211_partitions[] = {
29 {
30 .name = "IPL & ETH-BOOT",
31 .offset = 0x00000000,
32 .size = 0x10000,
33 },
34 {
35 .name = "Flash FS",
36 .offset = 0x00010000,
37 .size = MTDPART_SIZ_FULL,
38 }
39};
40
41static int __init init_mpc1211_maps(void)
42{
43 int nr_parts;
44
45 mpc1211_flash_map.phys = 0;
46 mpc1211_flash_map.virt = (void __iomem *)P2SEGADDR(0);
47
48 simple_map_init(&mpc1211_flash_map);
49
50 printk(KERN_NOTICE "Probing for flash chips at 0x00000000:\n");
51 flash_mtd = do_map_probe("jedec_probe", &mpc1211_flash_map);
52 if (!flash_mtd) {
53 printk(KERN_NOTICE "Flash chips not detected at either possible location.\n");
54 return -ENXIO;
55 }
56 printk(KERN_NOTICE "MPC-1211: Flash at 0x%08lx\n", mpc1211_flash_map.virt & 0x1fffffff);
57 flash_mtd->module = THIS_MODULE;
58
59 parsed_parts = mpc1211_partitions;
60 nr_parts = ARRAY_SIZE(mpc1211_partitions);
61
62 add_mtd_partitions(flash_mtd, parsed_parts, nr_parts);
63 return 0;
64}
65
66static void __exit cleanup_mpc1211_maps(void)
67{
68 if (parsed_parts)
69 del_mtd_partitions(flash_mtd);
70 else
71 del_mtd_device(flash_mtd);
72 map_destroy(flash_mtd);
73}
74
75module_init(init_mpc1211_maps);
76module_exit(cleanup_mpc1211_maps);
77
78MODULE_LICENSE("GPL");
79MODULE_AUTHOR("Saito.K & Jeanne <ksaito@interface.co.jp>");
80MODULE_DESCRIPTION("MTD map driver for MPC-1211 boards. Interface");
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
deleted file mode 100644
index 31dcc4fa5f28..000000000000
--- a/include/asm-sh/keyboard.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SH_KEYBOARD_H
2#define __ASM_SH_KEYBOARD_H
3/*
4 * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
5 */
6
7#include <linux/kd.h>
8#include <asm/machvec.h>
9
10#ifdef CONFIG_SH_MPC1211
11#include <asm/mpc1211/keyboard-mpc1211.h>
12#endif
13#endif
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
deleted file mode 100644
index e506d1aaa0d0..000000000000
--- a/include/asm-sh/mpc1211/dma.h
+++ /dev/null
@@ -1,303 +0,0 @@
1/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_MPC1211_DMA_H
9#define _ASM_MPC1211_DMA_H
10
11#include <linux/spinlock.h> /* And spinlocks */
12#include <asm/io.h> /* need byte IO */
13#include <linux/delay.h>
14
15
16#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
17#define dma_outb outb_p
18#else
19#define dma_outb outb
20#endif
21
22#define dma_inb inb
23
24/*
25 * NOTES about DMA transfers:
26 *
27 * controller 1: channels 0-3, byte operations, ports 00-1F
28 * controller 2: channels 4-7, word operations, ports C0-DF
29 *
30 * - ALL registers are 8 bits only, regardless of transfer size
31 * - channel 4 is not used - cascades 1 into 2.
32 * - channels 0-3 are byte - addresses/counts are for physical bytes
33 * - channels 5-7 are word - addresses/counts are for physical words
34 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
35 * - transfer count loaded to registers is 1 less than actual count
36 * - controller 2 offsets are all even (2x offsets for controller 1)
37 * - page registers for 5-7 don't use data bit 0, represent 128K pages
38 * - page registers for 0-3 use bit 0, represent 64K pages
39 *
40 * DMA transfers are limited to the lower 16MB of _physical_ memory.
41 * Note that addresses loaded into registers must be _physical_ addresses,
42 * not logical addresses (which may differ if paging is active).
43 *
44 * Address mapping for channels 0-3:
45 *
46 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
47 * | ... | | ... | | ... |
48 * | ... | | ... | | ... |
49 * | ... | | ... | | ... |
50 * P7 ... P0 A7 ... A0 A7 ... A0
51 * | Page | Addr MSB | Addr LSB | (DMA registers)
52 *
53 * Address mapping for channels 5-7:
54 *
55 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
56 * | ... | \ \ ... \ \ \ ... \ \
57 * | ... | \ \ ... \ \ \ ... \ (not used)
58 * | ... | \ \ ... \ \ \ ... \
59 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
60 * | Page | Addr MSB | Addr LSB | (DMA registers)
61 *
62 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
63 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
64 * the hardware level, so odd-byte transfers aren't possible).
65 *
66 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
67 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
68 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
69 *
70 */
71
72#define MAX_DMA_CHANNELS 8
73
74/* The maximum address that we can perform a DMA transfer to on this platform */
75#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
76
77/* 8237 DMA controllers */
78#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
79#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
80
81/* DMA controller registers */
82#define DMA1_CMD_REG 0x08 /* command register (w) */
83#define DMA1_STAT_REG 0x08 /* status register (r) */
84#define DMA1_REQ_REG 0x09 /* request register (w) */
85#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
86#define DMA1_MODE_REG 0x0B /* mode register (w) */
87#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
88#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
89#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
90#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
91#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
92
93#define DMA2_CMD_REG 0xD0 /* command register (w) */
94#define DMA2_STAT_REG 0xD0 /* status register (r) */
95#define DMA2_REQ_REG 0xD2 /* request register (w) */
96#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
97#define DMA2_MODE_REG 0xD6 /* mode register (w) */
98#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
99#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
100#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
101#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
102#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
103
104#define DMA_ADDR_0 0x00 /* DMA address registers */
105#define DMA_ADDR_1 0x02
106#define DMA_ADDR_2 0x04
107#define DMA_ADDR_3 0x06
108#define DMA_ADDR_4 0xC0
109#define DMA_ADDR_5 0xC4
110#define DMA_ADDR_6 0xC8
111#define DMA_ADDR_7 0xCC
112
113#define DMA_CNT_0 0x01 /* DMA count registers */
114#define DMA_CNT_1 0x03
115#define DMA_CNT_2 0x05
116#define DMA_CNT_3 0x07
117#define DMA_CNT_4 0xC2
118#define DMA_CNT_5 0xC6
119#define DMA_CNT_6 0xCA
120#define DMA_CNT_7 0xCE
121
122#define DMA_PAGE_0 0x87 /* DMA page registers */
123#define DMA_PAGE_1 0x83
124#define DMA_PAGE_2 0x81
125#define DMA_PAGE_3 0x82
126#define DMA_PAGE_5 0x8B
127#define DMA_PAGE_6 0x89
128#define DMA_PAGE_7 0x8A
129
130#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
131#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
132#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
133
134#define DMA_AUTOINIT 0x10
135
136
137extern spinlock_t dma_spin_lock;
138
139static __inline__ unsigned long claim_dma_lock(void)
140{
141 unsigned long flags;
142 spin_lock_irqsave(&dma_spin_lock, flags);
143 return flags;
144}
145
146static __inline__ void release_dma_lock(unsigned long flags)
147{
148 spin_unlock_irqrestore(&dma_spin_lock, flags);
149}
150
151/* enable/disable a specific DMA channel */
152static __inline__ void enable_dma(unsigned int dmanr)
153{
154 if (dmanr<=3)
155 dma_outb(dmanr, DMA1_MASK_REG);
156 else
157 dma_outb(dmanr & 3, DMA2_MASK_REG);
158}
159
160static __inline__ void disable_dma(unsigned int dmanr)
161{
162 if (dmanr<=3)
163 dma_outb(dmanr | 4, DMA1_MASK_REG);
164 else
165 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
166}
167
168/* Clear the 'DMA Pointer Flip Flop'.
169 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
170 * Use this once to initialize the FF to a known state.
171 * After that, keep track of it. :-)
172 * --- In order to do that, the DMA routines below should ---
173 * --- only be used while holding the DMA lock ! ---
174 */
175static __inline__ void clear_dma_ff(unsigned int dmanr)
176{
177 if (dmanr<=3)
178 dma_outb(0, DMA1_CLEAR_FF_REG);
179 else
180 dma_outb(0, DMA2_CLEAR_FF_REG);
181}
182
183/* set mode (above) for a specific DMA channel */
184static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
185{
186 if (dmanr<=3)
187 dma_outb(mode | dmanr, DMA1_MODE_REG);
188 else
189 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
190}
191
192/* Set only the page register bits of the transfer address.
193 * This is used for successive transfers when we know the contents of
194 * the lower 16 bits of the DMA current address register, but a 64k boundary
195 * may have been crossed.
196 */
197static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
198{
199 switch(dmanr) {
200 case 0:
201 dma_outb( pagenr & 0xff, DMA_PAGE_0);
202 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
203 break;
204 case 1:
205 dma_outb( pagenr & 0xff, DMA_PAGE_1);
206 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
207 break;
208 case 2:
209 dma_outb( pagenr & 0xff, DMA_PAGE_2);
210 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
211 break;
212 case 3:
213 dma_outb( pagenr & 0xff, DMA_PAGE_3);
214 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
215 break;
216 case 5:
217 dma_outb( pagenr & 0xfe, DMA_PAGE_5);
218 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
219 break;
220 case 6:
221 dma_outb( pagenr & 0xfe, DMA_PAGE_6);
222 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
223 break;
224 case 7:
225 dma_outb( pagenr & 0xfe, DMA_PAGE_7);
226 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
227 break;
228 }
229}
230
231
232/* Set transfer address & page bits for specific DMA channel.
233 * Assumes dma flipflop is clear.
234 */
235static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
236{
237 set_dma_page(dmanr, a>>16);
238 if (dmanr <= 3) {
239 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
240 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
241 } else {
242 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
243 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
244 }
245}
246
247
248/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
249 * a specific DMA channel.
250 * You must ensure the parameters are valid.
251 * NOTE: from a manual: "the number of transfers is one more
252 * than the initial word count"! This is taken into account.
253 * Assumes dma flip-flop is clear.
254 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
255 */
256static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
257{
258 count--;
259 if (dmanr <= 3) {
260 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
261 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
262 } else {
263 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
264 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
265 }
266}
267
268
269/* Get DMA residue count. After a DMA transfer, this
270 * should return zero. Reading this while a DMA transfer is
271 * still in progress will return unpredictable results.
272 * If called before the channel has been used, it may return 1.
273 * Otherwise, it returns the number of _bytes_ left to transfer.
274 *
275 * Assumes DMA flip-flop is clear.
276 */
277static __inline__ int get_dma_residue(unsigned int dmanr)
278{
279 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
280 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
281
282 /* using short to get 16-bit wrap around */
283 unsigned short count;
284
285 count = 1 + dma_inb(io_port);
286 count += dma_inb(io_port) << 8;
287 return (dmanr<=3)? count : (count<<1);
288}
289
290
291/* These are in kernel/dma.c: */
292extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
293extern void free_dma(unsigned int dmanr); /* release it again */
294
295/* From PCI */
296
297#ifdef CONFIG_PCI
298extern int isa_dma_bridge_buggy;
299#else
300#define isa_dma_bridge_buggy (0)
301#endif
302
303#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
deleted file mode 100644
index 6298370bec2d..000000000000
--- a/include/asm-sh/mpc1211/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-sh/mpc1211/io.h
3 *
4 * Copyright 2001 Saito.K & Jeanne
5 *
6 * IO functions for an Interface MPC-1211
7 */
8
9#ifndef _ASM_SH_IO_MPC1211_H
10#define _ASM_SH_IO_MPC1211_H
11
12#include <linux/time.h>
13
14extern int mpc1211_irq_demux(int irq);
15
16extern void init_mpc1211_IRQ(void);
17extern void heartbeat_mpc1211(void);
18
19extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
20extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
21
22#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
deleted file mode 100644
index 9020feee7b4c..000000000000
--- a/include/asm-sh/mpc1211/keyboard.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * MPC1211 specific keybord definitions
3 * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
4 * created 3 Nov 1996 by Geert Uytterhoeven.
5 */
6
7#ifdef __KERNEL__
8
9#include <linux/kernel.h>
10#include <linux/ioport.h>
11#include <linux/kd.h>
12#include <linux/pm.h>
13#include <asm/io.h>
14
15#define KEYBOARD_IRQ 1
16#define DISABLE_KBD_DURING_INTERRUPTS 0
17
18extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
19extern int pckbd_getkeycode(unsigned int scancode);
20extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
21 char raw_mode);
22extern char pckbd_unexpected_up(unsigned char keycode);
23extern void pckbd_leds(unsigned char leds);
24extern void pckbd_init_hw(void);
25extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
26extern pm_callback pm_kbd_request_override;
27
28#define kbd_setkeycode pckbd_setkeycode
29#define kbd_getkeycode pckbd_getkeycode
30#define kbd_translate pckbd_translate
31#define kbd_unexpected_up pckbd_unexpected_up
32#define kbd_leds pckbd_leds
33#define kbd_init_hw pckbd_init_hw
34
35/* resource allocation */
36#define kbd_request_region()
37#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
38 "keyboard", NULL)
39
40/* How to access the keyboard macros on this platform. */
41#define kbd_read_input() inb(KBD_DATA_REG)
42#define kbd_read_status() inb(KBD_STATUS_REG)
43#define kbd_write_output(val) outb(val, KBD_DATA_REG)
44#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
45
46/* Some stoneage hardware needs delays after some operations. */
47#define kbd_pause() do { } while(0)
48
49/*
50 * Machine specific bits for the PS/2 driver
51 */
52
53#define AUX_IRQ 12
54
55#define aux_request_irq(hand, dev_id) \
56 request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
57
58#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
59
60#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
deleted file mode 100644
index c95d13236c3b..000000000000
--- a/include/asm-sh/mpc1211/m1543c.h
+++ /dev/null
@@ -1,200 +0,0 @@
1#ifndef __ASM_SH_M1543C_H
2#define __ASM_SH_M1543C_H
3
4/*
5 * linux/include/asm-sh/m1543c.h
6 * Copyright (C) 2001 Nobuhiro Sakawa
7 * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
8 *
9 * from
10 *
11 * linux/include/asm-sh/smc37c93x.h
12 *
13 * Copyright (C) 2000 Kazumoto Kojima
14 *
15 * SMSC 37C93x Super IO Chip support
16 */
17
18/* Default base I/O address */
19#define FDC_PRIMARY_BASE 0x3f0
20#define IDE1_PRIMARY_BASE 0x1f0
21#define IDE1_SECONDARY_BASE 0x170
22#define PARPORT_PRIMARY_BASE 0x378
23#define COM1_PRIMARY_BASE 0x2f8
24#define COM2_PRIMARY_BASE 0x3f8
25#define COM3_PRIMARY_BASE 0x3e8
26#define RTC_PRIMARY_BASE 0x070
27#define KBC_PRIMARY_BASE 0x060
28#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
29#define I8259_M_CR 0x20
30#define I8259_M_MR 0x21
31#define I8259_S_CR 0xa0
32#define I8259_S_MR 0xa1
33
34/* Logical device number */
35#define LDN_FDC 0
36#define LDN_IDE1 1
37#define LDN_IDE2 2
38#define LDN_PARPORT 3
39#define LDN_COM1 4
40#define LDN_COM2 5
41#define LDN_COM3 11
42#define LDN_RTC 6
43#define LDN_KBC 7
44
45/* Configuration port and key */
46#define CONFIG_PORT 0x3f0
47#define INDEX_PORT CONFIG_PORT
48#define DATA_PORT 0x3f1
49#define CONFIG_ENTER1 0x51
50#define CONFIG_ENTER2 0x23
51#define CONFIG_EXIT 0xbb
52
53/* Configuration index */
54#define CURRENT_LDN_INDEX 0x07
55#define POWER_CONTROL_INDEX 0x22
56#define ACTIVATE_INDEX 0x30
57#define IO_BASE_HI_INDEX 0x60
58#define IO_BASE_LO_INDEX 0x61
59#define IRQ_SELECT_INDEX 0x70
60#define PS2_IRQ_INDEX 0x72
61#define DMA_SELECT_INDEX 0x74
62
63/* UART stuff. Only for debugging. */
64/* UART Register */
65
66#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
67#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
68#define UART_IER 0x2 /* Interrupt Enable Register */
69#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
70#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
71#define UART_LCR 0x6 /* Line Control Register */
72#define UART_MCR 0x8 /* MODEM Control Register */
73#define UART_LSR 0xa /* Line Status Register */
74#define UART_MSR 0xc /* MODEM Status Register */
75#define UART_SCR 0xe /* Scratch Register */
76#define UART_DLL 0x0 /* Divisor Latch (LS) */
77#define UART_DLM 0x2 /* Divisor Latch (MS) */
78
79#ifndef __ASSEMBLY__
80typedef struct uart_reg {
81 volatile __u16 rbr;
82 volatile __u16 ier;
83 volatile __u16 iir;
84 volatile __u16 lcr;
85 volatile __u16 mcr;
86 volatile __u16 lsr;
87 volatile __u16 msr;
88 volatile __u16 scr;
89} uart_reg;
90#endif /* ! __ASSEMBLY__ */
91
92/* Alias for Write Only Register */
93
94#define thr rbr
95#define tcr iir
96
97/* Alias for Divisor Latch Register */
98
99#define dll rbr
100#define dlm ier
101#define fcr iir
102
103/* Interrupt Enable Register */
104
105#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
106#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
107#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
108#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
109
110/* Interrupt Ident Register */
111
112#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
113#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
114#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
115#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
116#define IIR_FIFO 0xc000 /* FIFOs enabled */
117
118/* FIFO Control Register */
119
120#define FCR_FEN 0x0100 /* FIFO enable */
121#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
122#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
123#define FCR_DMA 0x0800 /* DMA mode select */
124#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
125#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
126
127/* Line Control Register */
128
129#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
130#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
131#define LCR_STB 0x0400 /* Number of Stop Bits */
132#define LCR_PEN 0x0800 /* Parity Enable */
133#define LCR_EPS 0x1000 /* Even Parity Select */
134#define LCR_SP 0x2000 /* Stick Parity */
135#define LCR_SB 0x4000 /* Set Break */
136#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
137
138/* MODEM Control Register */
139
140#define MCR_DTR 0x0100 /* Data Terminal Ready */
141#define MCR_RTS 0x0200 /* Request to Send */
142#define MCR_OUT1 0x0400 /* Out 1 */
143#define MCR_IRQEN 0x0800 /* IRQ Enable */
144#define MCR_LOOP 0x1000 /* Loop */
145
146/* Line Status Register */
147
148#define LSR_DR 0x0100 /* Data Ready */
149#define LSR_OE 0x0200 /* Overrun Error */
150#define LSR_PE 0x0400 /* Parity Error */
151#define LSR_FE 0x0800 /* Framing Error */
152#define LSR_BI 0x1000 /* Break Interrupt */
153#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
154#define LSR_TEMT 0x4000 /* Transmitter Empty */
155#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
156
157/* MODEM Status Register */
158
159#define MSR_DCTS 0x0100 /* Delta Clear to Send */
160#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
161#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
162#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
163#define MSR_CTS 0x1000 /* Clear to Send */
164#define MSR_DSR 0x2000 /* Data Set Ready */
165#define MSR_RI 0x4000 /* Ring Indicator */
166#define MSR_DCD 0x8000 /* Data Carrier Detect */
167
168/* Baud Rate Divisor */
169
170#define UART_CLK (1843200) /* 1.8432 MHz */
171#define UART_BAUD(x) (UART_CLK / (16 * (x)))
172
173/* RTC register definition */
174#define RTC_SECONDS 0
175#define RTC_SECONDS_ALARM 1
176#define RTC_MINUTES 2
177#define RTC_MINUTES_ALARM 3
178#define RTC_HOURS 4
179#define RTC_HOURS_ALARM 5
180#define RTC_DAY_OF_WEEK 6
181#define RTC_DAY_OF_MONTH 7
182#define RTC_MONTH 8
183#define RTC_YEAR 9
184#define RTC_FREQ_SELECT 10
185# define RTC_UIP 0x80
186# define RTC_DIV_CTL 0x70
187/* This RTC can work under 32.768KHz clock only. */
188# define RTC_OSC_ENABLE 0x20
189# define RTC_OSC_DISABLE 0x00
190#define RTC_CONTROL 11
191# define RTC_SET 0x80
192# define RTC_PIE 0x40
193# define RTC_AIE 0x20
194# define RTC_UIE 0x10
195# define RTC_SQWE 0x08
196# define RTC_DM_BINARY 0x04
197# define RTC_24H 0x02
198# define RTC_DST_EN 0x01
199
200#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
deleted file mode 100644
index e245f2a3cd78..000000000000
--- a/include/asm-sh/mpc1211/mc146818rtc.h
+++ /dev/null
@@ -1,6 +0,0 @@
1/*
2 * MPC1211 uses PC/AT style RTC definitions.
3 */
4#include <asm-x86/mc146818rtc_32.h>
5
6
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
deleted file mode 100644
index fa456c3e4e01..000000000000
--- a/include/asm-sh/mpc1211/mpc1211.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef __ASM_SH_MPC1211_H
2#define __ASM_SH_MPC1211_H
3
4/*
5 * linux/include/asm-sh/mpc1211.h
6 *
7 * Copyright (C) 2001 Saito.K & Jeanne
8 *
9 * Interface MPC-1211 support
10 */
11
12#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
13#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
deleted file mode 100644
index d9162c5ed76a..000000000000
--- a/include/asm-sh/mpc1211/pci.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Low-Level PCI Support for MPC-1211
3 *
4 * (c) 2002 Saito.K & Jeanne
5 *
6 */
7
8#ifndef _PCI_MPC1211_H_
9#define _PCI_MPC1211_H_
10
11#include <linux/pci.h>
12
13/* set debug level 4=verbose...1=terse */
14//#define DEBUG_PCI 3
15#undef DEBUG_PCI
16
17#ifdef DEBUG_PCI
18#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
19#else
20#define PCIDBG(n, x...)
21#endif
22
23/* startup values */
24#define PCI_PROBE_BIOS 1
25#define PCI_PROBE_CONF1 2
26#define PCI_PROBE_CONF2 4
27#define PCI_NO_CHECKS 0x400
28#define PCI_ASSIGN_ROMS 0x1000
29#define PCI_BIOS_IRQ_SCAN 0x2000
30
31/* MPC-1211 Specific Values */
32#define PCIPAR (0xa4000cf8) /* PCI Config address */
33#define PCIPDR (0xa4000cfc) /* PCI Config data */
34
35#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
36#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
37
38#endif /* _PCI_MPC1211_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 14:38:55 -0500