diff options
-rw-r--r-- | drivers/ieee1394/ohci1394.c | 126 |
1 files changed, 48 insertions, 78 deletions
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c index b98b9934b92d..a12802553b4b 100644 --- a/drivers/ieee1394/ohci1394.c +++ b/drivers/ieee1394/ohci1394.c | |||
@@ -3529,108 +3529,40 @@ static void ohci1394_pci_remove(struct pci_dev *pdev) | |||
3529 | } | 3529 | } |
3530 | 3530 | ||
3531 | #ifdef CONFIG_PM | 3531 | #ifdef CONFIG_PM |
3532 | static int ohci1394_pci_resume (struct pci_dev *pdev) | 3532 | static int ohci1394_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
3533 | { | 3533 | { |
3534 | int err; | 3534 | int err; |
3535 | struct ti_ohci *ohci; | 3535 | struct ti_ohci *ohci = pci_get_drvdata(pdev); |
3536 | |||
3537 | /* PowerMac resume code comes first */ | ||
3538 | #ifdef CONFIG_PPC_PMAC | ||
3539 | if (machine_is(powermac)) { | ||
3540 | struct device_node *of_node; | ||
3541 | |||
3542 | /* Re-enable 1394 */ | ||
3543 | of_node = pci_device_to_OF_node (pdev); | ||
3544 | if (of_node) | ||
3545 | pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1); | ||
3546 | } | ||
3547 | #endif /* CONFIG_PPC_PMAC */ | ||
3548 | |||
3549 | pci_set_power_state(pdev, PCI_D0); | ||
3550 | pci_restore_state(pdev); | ||
3551 | err = pci_enable_device(pdev); | ||
3552 | if (err) | ||
3553 | return err; | ||
3554 | |||
3555 | ohci = pci_get_drvdata(pdev); | ||
3556 | if (!ohci) | ||
3557 | return -1; /* or which exit status to use? */ | ||
3558 | |||
3559 | PRINT(KERN_DEBUG, "resume called"); | ||
3560 | |||
3561 | /* The following lines are copied from ohci1394_pci_probe(): */ | ||
3562 | |||
3563 | /* Start off with a soft reset, to clear everything to a sane | ||
3564 | * state. */ | ||
3565 | ohci_soft_reset(ohci); | ||
3566 | |||
3567 | /* Now enable LPS, which we need in order to start accessing | ||
3568 | * most of the registers. In fact, on some cards (ALI M5251), | ||
3569 | * accessing registers in the SClk domain without LPS enabled | ||
3570 | * will lock up the machine. Wait 50msec to make sure we have | ||
3571 | * full link enabled. */ | ||
3572 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); | ||
3573 | |||
3574 | /* Disable and clear interrupts */ | ||
3575 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | ||
3576 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | ||
3577 | |||
3578 | mdelay(50); | ||
3579 | |||
3580 | ohci_initialize(ohci); | ||
3581 | |||
3582 | return 0; | ||
3583 | } | ||
3584 | |||
3585 | static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state) | ||
3586 | { | ||
3587 | int err; | ||
3588 | struct ti_ohci *ohci; | ||
3589 | |||
3590 | ohci = pci_get_drvdata(pdev); | ||
3591 | if (!ohci) | ||
3592 | return -1; /* Not sure if this is the correct return code */ | ||
3593 | 3536 | ||
3594 | PRINT(KERN_DEBUG, "suspend called"); | 3537 | PRINT(KERN_DEBUG, "suspend called"); |
3538 | if (!ohci) | ||
3539 | return -ENXIO; | ||
3595 | 3540 | ||
3596 | /* clear the async DMA contexts and stop using the controller: */ | 3541 | /* Clear the async DMA contexts and stop using the controller */ |
3597 | hpsb_bus_reset(ohci->host); | 3542 | hpsb_bus_reset(ohci->host); |
3598 | 3543 | ||
3599 | /* The following calls are from ohci1394_pci_remove(): */ | 3544 | /* See ohci1394_pci_remove() for comments on this sequence */ |
3600 | |||
3601 | /* Clear out BUS Options */ | ||
3602 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | 3545 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); |
3603 | reg_write(ohci, OHCI1394_BusOptions, | 3546 | reg_write(ohci, OHCI1394_BusOptions, |
3604 | (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) | | 3547 | (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) | |
3605 | 0x00ff0000); | 3548 | 0x00ff0000); |
3606 | |||
3607 | /* Clear interrupt registers */ | ||
3608 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | 3549 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); |
3609 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | 3550 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); |
3610 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); | 3551 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); |
3611 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); | 3552 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); |
3612 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); | 3553 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); |
3613 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); | 3554 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); |
3614 | |||
3615 | /* Disable IRM Contender */ | ||
3616 | set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4)); | 3555 | set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4)); |
3617 | |||
3618 | /* Clear link control register */ | ||
3619 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); | 3556 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); |
3620 | |||
3621 | /* Let all other nodes know to ignore us */ | ||
3622 | ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); | 3557 | ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); |
3623 | |||
3624 | /* This stops all DMA contexts, disables interrupts, | ||
3625 | * and clears linkEnable and LPS: */ | ||
3626 | ohci_soft_reset(ohci); | 3558 | ohci_soft_reset(ohci); |
3627 | 3559 | ||
3628 | err = pci_save_state(pdev); | 3560 | err = pci_save_state(pdev); |
3629 | if (err) | 3561 | if (err) |
3630 | goto out; | 3562 | return err; |
3631 | err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); | 3563 | err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
3632 | if (err) | 3564 | if (err) |
3633 | goto out; | 3565 | return err; |
3634 | 3566 | ||
3635 | /* PowerMac suspend code comes last */ | 3567 | /* PowerMac suspend code comes last */ |
3636 | #ifdef CONFIG_PPC_PMAC | 3568 | #ifdef CONFIG_PPC_PMAC |
@@ -3643,8 +3575,46 @@ static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state) | |||
3643 | pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0); | 3575 | pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0); |
3644 | } | 3576 | } |
3645 | #endif /* CONFIG_PPC_PMAC */ | 3577 | #endif /* CONFIG_PPC_PMAC */ |
3646 | out: | 3578 | |
3647 | return err; | 3579 | return 0; |
3580 | } | ||
3581 | |||
3582 | static int ohci1394_pci_resume(struct pci_dev *pdev) | ||
3583 | { | ||
3584 | int err; | ||
3585 | struct ti_ohci *ohci = pci_get_drvdata(pdev); | ||
3586 | |||
3587 | PRINT(KERN_DEBUG, "resume called"); | ||
3588 | if (!ohci) | ||
3589 | return -ENXIO; | ||
3590 | |||
3591 | /* PowerMac resume code comes first */ | ||
3592 | #ifdef CONFIG_PPC_PMAC | ||
3593 | if (machine_is(powermac)) { | ||
3594 | struct device_node *of_node; | ||
3595 | |||
3596 | /* Re-enable 1394 */ | ||
3597 | of_node = pci_device_to_OF_node (pdev); | ||
3598 | if (of_node) | ||
3599 | pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1); | ||
3600 | } | ||
3601 | #endif /* CONFIG_PPC_PMAC */ | ||
3602 | |||
3603 | pci_set_power_state(pdev, PCI_D0); | ||
3604 | pci_restore_state(pdev); | ||
3605 | err = pci_enable_device(pdev); | ||
3606 | if (err) | ||
3607 | return err; | ||
3608 | |||
3609 | /* See ohci1394_pci_probe() for comments on this sequence */ | ||
3610 | ohci_soft_reset(ohci); | ||
3611 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); | ||
3612 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | ||
3613 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | ||
3614 | mdelay(50); | ||
3615 | ohci_initialize(ohci); | ||
3616 | |||
3617 | return 0; | ||
3648 | } | 3618 | } |
3649 | #endif /* CONFIG_PM */ | 3619 | #endif /* CONFIG_PM */ |
3650 | 3620 | ||