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-rw-r--r--MAINTAINERS6
-rw-r--r--arch/blackfin/Kconfig131
-rw-r--r--arch/blackfin/Makefile12
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig17
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig17
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig39
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig50
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig90
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig32
-rw-r--r--arch/blackfin/kernel/Makefile2
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c4
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c171
-rw-r--r--arch/blackfin/kernel/cplb-mpu/Makefile8
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cacheinit.c62
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinfo.c144
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c91
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c338
-rw-r--r--arch/blackfin/kernel/cplb-nompu/Makefile8
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cacheinit.c (renamed from arch/blackfin/kernel/cacheinit.c)2
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbhdlr.S (renamed from arch/blackfin/mach-common/cplbhdlr.S)0
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinfo.c (renamed from arch/blackfin/mach-common/cplbinfo.c)0
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c (renamed from arch/blackfin/kernel/cplbinit.c)0
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbmgr.S (renamed from arch/blackfin/mach-common/cplbmgr.S)37
-rw-r--r--arch/blackfin/kernel/early_printk.c4
-rw-r--r--arch/blackfin/kernel/process.c32
-rw-r--r--arch/blackfin/kernel/reboot.c13
-rw-r--r--arch/blackfin/kernel/setup.c13
-rw-r--r--arch/blackfin/kernel/time.c70
-rw-r--r--arch/blackfin/kernel/traps.c212
-rw-r--r--arch/blackfin/lib/memcpy.S8
-rw-r--r--arch/blackfin/mach-bf527/Kconfig2
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c107
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c83
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c52
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c103
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig6
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c11
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c11
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c317
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c9
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c80
-rw-r--r--arch/blackfin/mach-bf548/Kconfig2
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c96
-rw-r--r--arch/blackfin/mach-bf548/head.S55
-rw-r--r--arch/blackfin/mach-bf548/ints-priority.c4
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c11
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c96
-rw-r--r--arch/blackfin/mach-bf561/coreb.c12
-rw-r--r--arch/blackfin/mach-common/Makefile3
-rw-r--r--arch/blackfin/mach-common/dpmc.S74
-rw-r--r--arch/blackfin/mach-common/entry.S26
-rw-r--r--arch/blackfin/mach-common/interrupt.S48
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c10
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c84
-rw-r--r--arch/blackfin/mach-common/irqpanic.c50
-rw-r--r--arch/blackfin/mach-common/pm.c16
-rw-r--r--arch/blackfin/mm/init.c33
-rw-r--r--drivers/serial/bfin_5xx.c6
-rw-r--r--drivers/video/bf54x-lq043fb.c6
-rw-r--r--include/asm-blackfin/bfin-global.h2
-rw-r--r--include/asm-blackfin/cplb-mpu.h61
-rw-r--r--include/asm-blackfin/cplb.h4
-rw-r--r--include/asm-blackfin/cplbinit.h8
-rw-r--r--include/asm-blackfin/dma.h6
-rw-r--r--include/asm-blackfin/gpio.h84
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf527/portmux.h2
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h12
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf533/portmux.h2
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h14
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf537/portmux.h2
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h54
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h33
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h4
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h4
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h31
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h62
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h2
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h18
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf561/portmux.h2
-rw-r--r--include/asm-blackfin/mmu.h4
-rw-r--r--include/asm-blackfin/mmu_context.h62
-rw-r--r--include/asm-blackfin/traps.h4
-rw-r--r--include/asm-blackfin/uaccess.h2
-rw-r--r--include/asm-blackfin/unistd.h3
91 files changed, 2763 insertions, 760 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 59db481c77de..29371226f682 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -758,22 +758,20 @@ S: Supported
758 758
759BLACKFIN RTC DRIVER 759BLACKFIN RTC DRIVER
760P: Mike Frysinger 760P: Mike Frysinger
761M: michael.frysinger@analog.com
762M: vapier.adi@gmail.com 761M: vapier.adi@gmail.com
763L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) 762L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
764W: http://blackfin.uclinux.org 763W: http://blackfin.uclinux.org
765S: Supported 764S: Supported
766 765
767BLACKFIN SERIAL DRIVER 766BLACKFIN SERIAL DRIVER
768P: Aubrey Li 767P: Sonic Zhang
769M: aubrey.li@analog.com 768M: sonic.zhang@analog.com
770L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) 769L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
771W: http://blackfin.uclinux.org 770W: http://blackfin.uclinux.org
772S: Supported 771S: Supported
773 772
774BLACKFIN WATCHDOG DRIVER 773BLACKFIN WATCHDOG DRIVER
775P: Mike Frysinger 774P: Mike Frysinger
776M: michael.frysinger@analog.com
777M: vapier.adi@gmail.com 775M: vapier.adi@gmail.com
778L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) 776L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
779W: http://blackfin.uclinux.org 777W: http://blackfin.uclinux.org
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 25232ba08119..fc7ca86ac8bf 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -85,11 +85,26 @@ config BF522
85 help 85 help
86 BF522 Processor Support. 86 BF522 Processor Support.
87 87
88config BF523
89 bool "BF523"
90 help
91 BF523 Processor Support.
92
93config BF524
94 bool "BF524"
95 help
96 BF524 Processor Support.
97
88config BF525 98config BF525
89 bool "BF525" 99 bool "BF525"
90 help 100 help
91 BF525 Processor Support. 101 BF525 Processor Support.
92 102
103config BF526
104 bool "BF526"
105 help
106 BF526 Processor Support.
107
93config BF527 108config BF527
94 bool "BF527" 109 bool "BF527"
95 help 110 help
@@ -198,7 +213,7 @@ endchoice
198 213
199config BF52x 214config BF52x
200 bool 215 bool
201 depends on (BF522 || BF525 || BF527) 216 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
202 default y 217 default y
203 218
204config BF53x 219config BF53x
@@ -253,11 +268,6 @@ config MEM_MT48LC32M16A2TG_75
253 depends on (BFIN527_EZKIT) 268 depends on (BFIN527_EZKIT)
254 default y 269 default y
255 270
256config BFIN_SHARED_FLASH_ENET
257 bool
258 depends on (BFIN533_STAMP)
259 default y
260
261source "arch/blackfin/mach-bf527/Kconfig" 271source "arch/blackfin/mach-bf527/Kconfig"
262source "arch/blackfin/mach-bf533/Kconfig" 272source "arch/blackfin/mach-bf533/Kconfig"
263source "arch/blackfin/mach-bf561/Kconfig" 273source "arch/blackfin/mach-bf561/Kconfig"
@@ -317,7 +327,7 @@ config VCO_MULT
317 range 1 64 327 range 1 64
318 default "22" if BFIN533_EZKIT 328 default "22" if BFIN533_EZKIT
319 default "45" if BFIN533_STAMP 329 default "45" if BFIN533_STAMP
320 default "20" if (BFIN537_STAMP || BFIN527_EZKIT) 330 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
321 default "22" if BFIN533_BLUETECHNIX_CM 331 default "22" if BFIN533_BLUETECHNIX_CM
322 default "20" if BFIN537_BLUETECHNIX_CM 332 default "20" if BFIN537_BLUETECHNIX_CM
323 default "20" if BFIN561_BLUETECHNIX_CM 333 default "20" if BFIN561_BLUETECHNIX_CM
@@ -354,7 +364,7 @@ config SCLK_DIV
354 range 1 15 364 range 1 15
355 default 5 if BFIN533_EZKIT 365 default 5 if BFIN533_EZKIT
356 default 5 if BFIN533_STAMP 366 default 5 if BFIN533_STAMP
357 default 4 if (BFIN537_STAMP || BFIN527_EZKIT) 367 default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
358 default 5 if BFIN533_BLUETECHNIX_CM 368 default 5 if BFIN533_BLUETECHNIX_CM
359 default 4 if BFIN537_BLUETECHNIX_CM 369 default 4 if BFIN537_BLUETECHNIX_CM
360 default 4 if BFIN561_BLUETECHNIX_CM 370 default 4 if BFIN561_BLUETECHNIX_CM
@@ -371,7 +381,10 @@ config SCLK_DIV
371config MAX_VCO_HZ 381config MAX_VCO_HZ
372 int 382 int
373 default 600000000 if BF522 383 default 600000000 if BF522
384 default 400000000 if BF523
385 default 400000000 if BF524
374 default 600000000 if BF525 386 default 600000000 if BF525
387 default 400000000 if BF526
375 default 600000000 if BF527 388 default 600000000 if BF527
376 default 400000000 if BF531 389 default 400000000 if BF531
377 default 400000000 if BF532 390 default 400000000 if BF532
@@ -383,6 +396,8 @@ config MAX_VCO_HZ
383 default 533333333 if BF539 396 default 533333333 if BF539
384 default 600000000 if BF542 397 default 600000000 if BF542
385 default 533333333 if BF544 398 default 533333333 if BF544
399 default 600000000 if BF547
400 default 600000000 if BF548
386 default 533333333 if BF549 401 default 533333333 if BF549
387 default 600000000 if BF561 402 default 600000000 if BF561
388 403
@@ -409,6 +424,7 @@ config MEM_SIZE
409 default 32 if BFIN533_EZKIT 424 default 32 if BFIN533_EZKIT
410 default 64 if BFIN527_EZKIT 425 default 64 if BFIN527_EZKIT
411 default 64 if BFIN537_STAMP 426 default 64 if BFIN537_STAMP
427 default 64 if BFIN548_EZKIT
412 default 64 if BFIN561_EZKIT 428 default 64 if BFIN561_EZKIT
413 default 128 if BFIN533_STAMP 429 default 128 if BFIN533_STAMP
414 default 64 if PNAV10 430 default 64 if PNAV10
@@ -416,6 +432,7 @@ config MEM_SIZE
416 432
417config MEM_ADD_WIDTH 433config MEM_ADD_WIDTH
418 int "SDRAM Memory Address Width" 434 int "SDRAM Memory Address Width"
435 depends on (!BF54x)
419 default 9 if BFIN533_EZKIT 436 default 9 if BFIN533_EZKIT
420 default 9 if BFIN561_EZKIT 437 default 9 if BFIN561_EZKIT
421 default 9 if H8606_HVSISTEMAS 438 default 9 if H8606_HVSISTEMAS
@@ -424,6 +441,19 @@ config MEM_ADD_WIDTH
424 default 11 if BFIN533_STAMP 441 default 11 if BFIN533_STAMP
425 default 10 if PNAV10 442 default 10 if PNAV10
426 443
444
445choice
446 prompt "DDR SDRAM Chip Type"
447 depends on BFIN548_EZKIT
448 default MEM_MT46V32M16_5B
449
450config MEM_MT46V32M16_6T
451 bool "MT46V32M16_6T"
452
453config MEM_MT46V32M16_5B
454 bool "MT46V32M16_5B"
455endchoice
456
427config ENET_FLASH_PIN 457config ENET_FLASH_PIN
428 int "PF port/pin used for flash and ethernet sharing" 458 int "PF port/pin used for flash and ethernet sharing"
429 depends on (BFIN533_STAMP) 459 depends on (BFIN533_STAMP)
@@ -448,40 +478,6 @@ config BOOT_LOAD
448 memory region is used to capture NULL pointer references as well 478 memory region is used to capture NULL pointer references as well
449 as some core kernel functions. 479 as some core kernel functions.
450 480
451comment "LED Status Indicators"
452 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
453
454config BFIN_ALIVE_LED
455 bool "Enable Board Alive"
456 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
457 default n
458 help
459 Blink the LEDs you select when the kernel is running. Helps detect
460 a hung kernel.
461
462config BFIN_ALIVE_LED_NUM
463 int "LED"
464 depends on BFIN_ALIVE_LED
465 range 1 3 if BFIN533_STAMP
466 default "3" if BFIN533_STAMP
467 help
468 Select the LED (marked on the board) for you to blink.
469
470config BFIN_IDLE_LED
471 bool "Enable System Load/Idle LED"
472 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
473 default n
474 help
475 Blinks the LED you select when to determine kernel load.
476
477config BFIN_IDLE_LED_NUM
478 int "LED"
479 depends on BFIN_IDLE_LED
480 range 1 3 if BFIN533_STAMP
481 default "2" if BFIN533_STAMP
482 help
483 Select the LED (marked on the board) for you to blink.
484
485choice 481choice
486 prompt "Blackfin Exception Scratch Register" 482 prompt "Blackfin Exception Scratch Register"
487 default BFIN_SCRATCH_REG_RETN 483 default BFIN_SCRATCH_REG_RETN
@@ -528,41 +524,6 @@ config BFIN_SCRATCH_REG_CYCLES
528 524
529endchoice 525endchoice
530 526
531#
532# Sorry - but you need to put the hex address here -
533#
534
535# Flag Data register
536config BFIN_ALIVE_LED_PORT
537 hex
538 default 0xFFC00700 if (BFIN533_STAMP)
539
540# Peripheral Flag Direction Register
541config BFIN_ALIVE_LED_DPORT
542 hex
543 default 0xFFC00730 if (BFIN533_STAMP)
544
545config BFIN_ALIVE_LED_PIN
546 hex
547 default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
548 default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
549 default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
550
551config BFIN_IDLE_LED_PORT
552 hex
553 default 0xFFC00700 if (BFIN533_STAMP)
554
555# Peripheral Flag Direction Register
556config BFIN_IDLE_LED_DPORT
557 hex
558 default 0xFFC00730 if (BFIN533_STAMP)
559
560config BFIN_IDLE_LED_PIN
561 hex
562 default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
563 default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
564 default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
565
566endmenu 527endmenu
567 528
568 529
@@ -799,6 +760,15 @@ config L1_MAX_PIECE
799 Set the max memory pieces for the L1 SRAM allocation algorithm. 760 Set the max memory pieces for the L1 SRAM allocation algorithm.
800 Min value is 16. Max value is 1024. 761 Min value is 16. Max value is 1024.
801 762
763
764config MPU
765 bool "Enable the memory protection unit (EXPERIMENTAL)"
766 default n
767 help
768 Use the processor's MPU to protect applications from accessing
769 memory they do not own. This comes at a performance penalty
770 and is recommended only for debugging.
771
802comment "Asynchonous Memory Configuration" 772comment "Asynchonous Memory Configuration"
803 773
804menu "EBIU_AMGCTL Global Control" 774menu "EBIU_AMGCTL Global Control"
@@ -808,7 +778,6 @@ config C_AMCKEN
808 778
809config C_CDPRIO 779config C_CDPRIO
810 bool "DMA has priority over core for ext. accesses" 780 bool "DMA has priority over core for ext. accesses"
811 depends on !BF54x
812 default n 781 default n
813 782
814config C_B0PEN 783config C_B0PEN
@@ -949,8 +918,10 @@ endchoice
949config PM_WAKEUP_SIC_IWR 918config PM_WAKEUP_SIC_IWR
950 hex "Wakeup Events (SIC_IWR)" 919 hex "Wakeup Events (SIC_IWR)"
951 depends on PM_WAKEUP_GPIO_BY_SIC_IWR 920 depends on PM_WAKEUP_GPIO_BY_SIC_IWR
952 default 0x80000000 if (BF537 || BF536 || BF534) 921 default 0x8 if (BF537 || BF536 || BF534)
953 default 0x100000 if (BF533 || BF532 || BF531) 922 default 0x80 if (BF533 || BF532 || BF531)
923 default 0x80 if (BF54x)
924 default 0x80 if (BF52x)
954 925
955config PM_WAKEUP_GPIO_NUMBER 926config PM_WAKEUP_GPIO_NUMBER
956 int "Wakeup GPIO number" 927 int "Wakeup GPIO number"
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index c47e000f8324..0edc402fef54 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -21,7 +21,10 @@ KBUILD_DEFCONFIG := BF537-STAMP_defconfig
21 21
22# setup the machine name and the machine dependent settings 22# setup the machine name and the machine dependent settings
23machine-$(CONFIG_BF522) := bf527 23machine-$(CONFIG_BF522) := bf527
24machine-$(CONFIG_BF523) := bf527
25machine-$(CONFIG_BF524) := bf527
24machine-$(CONFIG_BF525) := bf527 26machine-$(CONFIG_BF525) := bf527
27machine-$(CONFIG_BF526) := bf527
25machine-$(CONFIG_BF527) := bf527 28machine-$(CONFIG_BF527) := bf527
26machine-$(CONFIG_BF531) := bf533 29machine-$(CONFIG_BF531) := bf533
27machine-$(CONFIG_BF532) := bf533 30machine-$(CONFIG_BF532) := bf533
@@ -39,7 +42,10 @@ MACHINE := $(machine-y)
39export MACHINE 42export MACHINE
40 43
41cpu-$(CONFIG_BF522) := bf522 44cpu-$(CONFIG_BF522) := bf522
45cpu-$(CONFIG_BF523) := bf523
46cpu-$(CONFIG_BF524) := bf524
42cpu-$(CONFIG_BF525) := bf525 47cpu-$(CONFIG_BF525) := bf525
48cpu-$(CONFIG_BF526) := bf526
43cpu-$(CONFIG_BF527) := bf527 49cpu-$(CONFIG_BF527) := bf527
44cpu-$(CONFIG_BF531) := bf531 50cpu-$(CONFIG_BF531) := bf531
45cpu-$(CONFIG_BF532) := bf532 51cpu-$(CONFIG_BF532) := bf532
@@ -76,6 +82,12 @@ core-y += arch/$(ARCH)/mach-$(MACHINE)/
76core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/ 82core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/
77endif 83endif
78 84
85ifeq ($(CONFIG_MPU),y)
86core-y += arch/$(ARCH)/kernel/cplb-mpu/
87else
88core-y += arch/$(ARCH)/kernel/cplb-nompu/
89endif
90
79libs-y += arch/$(ARCH)/lib/ 91libs-y += arch/$(ARCH)/lib/
80 92
81drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ 93drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index fa6eb4e00fae..d59ee1530bd4 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -1,6 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.14
4# Thu Nov 29 17:32:47 2007
4# 5#
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
@@ -153,8 +154,8 @@ CONFIG_BFIN527_EZKIT=y
153CONFIG_BF527_SPORT0_PORTG=y 154CONFIG_BF527_SPORT0_PORTG=y
154CONFIG_BF527_SPORT0_TSCLK_PG10=y 155CONFIG_BF527_SPORT0_TSCLK_PG10=y
155# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set 156# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
156# CONFIG_BF527_UART1_PORTF is not set 157CONFIG_BF527_UART1_PORTF=y
157CONFIG_BF527_UART1_PORTG=y 158# CONFIG_BF527_UART1_PORTG is not set
158# CONFIG_BF527_NAND_D_PORTF is not set 159# CONFIG_BF527_NAND_D_PORTF is not set
159CONFIG_BF527_NAND_D_PORTH=y 160CONFIG_BF527_NAND_D_PORTH=y
160 161
@@ -232,7 +233,7 @@ CONFIG_CLKIN_HZ=25000000
232# CONFIG_BFIN_KERNEL_CLOCK is not set 233# CONFIG_BFIN_KERNEL_CLOCK is not set
233CONFIG_MAX_VCO_HZ=600000000 234CONFIG_MAX_VCO_HZ=600000000
234CONFIG_MIN_VCO_HZ=50000000 235CONFIG_MIN_VCO_HZ=50000000
235CONFIG_MAX_SCLK_HZ=133000000 236CONFIG_MAX_SCLK_HZ=133333333
236CONFIG_MIN_SCLK_HZ=27000000 237CONFIG_MIN_SCLK_HZ=27000000
237 238
238# 239#
@@ -626,8 +627,8 @@ CONFIG_BFIN_MAC_RMII=y
626# CONFIG_SMSC911X is not set 627# CONFIG_SMSC911X is not set
627# CONFIG_DM9000 is not set 628# CONFIG_DM9000 is not set
628CONFIG_NETDEV_1000=y 629CONFIG_NETDEV_1000=y
629CONFIG_NETDEV_10000=y
630# CONFIG_AX88180 is not set 630# CONFIG_AX88180 is not set
631CONFIG_NETDEV_10000=y
631 632
632# 633#
633# Wireless LAN 634# Wireless LAN
@@ -1183,7 +1184,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1183# 1184#
1184# CONFIG_PRINTK_TIME is not set 1185# CONFIG_PRINTK_TIME is not set
1185CONFIG_ENABLE_MUST_CHECK=y 1186CONFIG_ENABLE_MUST_CHECK=y
1186CONFIG_MAGIC_SYSRQ=y 1187# CONFIG_MAGIC_SYSRQ is not set
1187# CONFIG_UNUSED_SYMBOLS is not set 1188# CONFIG_UNUSED_SYMBOLS is not set
1188CONFIG_DEBUG_FS=y 1189CONFIG_DEBUG_FS=y
1189# CONFIG_HEADERS_CHECK is not set 1190# CONFIG_HEADERS_CHECK is not set
@@ -1208,7 +1209,7 @@ CONFIG_ACCESS_CHECK=y
1208# CONFIG_KEYS is not set 1209# CONFIG_KEYS is not set
1209CONFIG_SECURITY=y 1210CONFIG_SECURITY=y
1210# CONFIG_SECURITY_NETWORK is not set 1211# CONFIG_SECURITY_NETWORK is not set
1211CONFIG_SECURITY_CAPABILITIES=y 1212CONFIG_SECURITY_CAPABILITIES=m
1212 1213
1213# 1214#
1214# Cryptographic options 1215# Cryptographic options
@@ -1219,7 +1220,7 @@ CONFIG_SECURITY_CAPABILITIES=y
1219# Library routines 1220# Library routines
1220# 1221#
1221CONFIG_BITREVERSE=y 1222CONFIG_BITREVERSE=y
1222# CONFIG_CRC_CCITT is not set 1223CONFIG_CRC_CCITT=m
1223# CONFIG_CRC16 is not set 1224# CONFIG_CRC16 is not set
1224# CONFIG_CRC_ITU_T is not set 1225# CONFIG_CRC_ITU_T is not set
1225CONFIG_CRC32=y 1226CONFIG_CRC32=y
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 4fdb49362ba3..811711f59a25 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -1,6 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.16
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
115# Processor and Board Settings 115# Processor and Board Settings
116# 116#
117# CONFIG_BF522 is not set 117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
118# CONFIG_BF525 is not set 120# CONFIG_BF525 is not set
121# CONFIG_BF526 is not set
119# CONFIG_BF527 is not set 122# CONFIG_BF527 is not set
120# CONFIG_BF531 is not set 123# CONFIG_BF531 is not set
121# CONFIG_BF532 is not set 124# CONFIG_BF532 is not set
@@ -194,7 +197,7 @@ CONFIG_CLKIN_HZ=27000000
194# CONFIG_BFIN_KERNEL_CLOCK is not set 197# CONFIG_BFIN_KERNEL_CLOCK is not set
195CONFIG_MAX_VCO_HZ=750000000 198CONFIG_MAX_VCO_HZ=750000000
196CONFIG_MIN_VCO_HZ=50000000 199CONFIG_MIN_VCO_HZ=50000000
197CONFIG_MAX_SCLK_HZ=133000000 200CONFIG_MAX_SCLK_HZ=133333333
198CONFIG_MIN_SCLK_HZ=27000000 201CONFIG_MIN_SCLK_HZ=27000000
199 202
200# 203#
@@ -267,6 +270,7 @@ CONFIG_BFIN_DCACHE=y
267# CONFIG_BFIN_WB is not set 270# CONFIG_BFIN_WB is not set
268CONFIG_BFIN_WT=y 271CONFIG_BFIN_WT=y
269CONFIG_L1_MAX_PIECE=16 272CONFIG_L1_MAX_PIECE=16
273# CONFIG_MPU is not set
270 274
271# 275#
272# Asynchonous Memory Configuration 276# Asynchonous Memory Configuration
@@ -321,7 +325,7 @@ CONFIG_PM=y
321CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y 325CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y
322# CONFIG_PM_WAKEUP_BY_GPIO is not set 326# CONFIG_PM_WAKEUP_BY_GPIO is not set
323# CONFIG_PM_WAKEUP_GPIO_API is not set 327# CONFIG_PM_WAKEUP_GPIO_API is not set
324CONFIG_PM_WAKEUP_SIC_IWR=0x100000 328CONFIG_PM_WAKEUP_SIC_IWR=0x80
325 329
326# 330#
327# CPU Frequency scaling 331# CPU Frequency scaling
@@ -510,7 +514,6 @@ CONFIG_MTD_CFI_I2=y
510# CONFIG_MTD_CFI_INTELEXT is not set 514# CONFIG_MTD_CFI_INTELEXT is not set
511# CONFIG_MTD_CFI_AMDSTD is not set 515# CONFIG_MTD_CFI_AMDSTD is not set
512# CONFIG_MTD_CFI_STAA is not set 516# CONFIG_MTD_CFI_STAA is not set
513CONFIG_MTD_MW320D=m
514CONFIG_MTD_RAM=y 517CONFIG_MTD_RAM=y
515CONFIG_MTD_ROM=m 518CONFIG_MTD_ROM=m
516# CONFIG_MTD_ABSENT is not set 519# CONFIG_MTD_ABSENT is not set
@@ -520,9 +523,6 @@ CONFIG_MTD_ROM=m
520# 523#
521CONFIG_MTD_COMPLEX_MAPPINGS=y 524CONFIG_MTD_COMPLEX_MAPPINGS=y
522# CONFIG_MTD_PHYSMAP is not set 525# CONFIG_MTD_PHYSMAP is not set
523CONFIG_MTD_BF5xx=m
524CONFIG_BFIN_FLASH_SIZE=0x400000
525CONFIG_EBIU_FLASH_BASE=0x20000000
526# CONFIG_MTD_UCLINUX is not set 526# CONFIG_MTD_UCLINUX is not set
527# CONFIG_MTD_PLATRAM is not set 527# CONFIG_MTD_PLATRAM is not set
528 528
@@ -610,8 +610,8 @@ CONFIG_SMC91X=y
610# CONFIG_SMSC911X is not set 610# CONFIG_SMSC911X is not set
611# CONFIG_DM9000 is not set 611# CONFIG_DM9000 is not set
612CONFIG_NETDEV_1000=y 612CONFIG_NETDEV_1000=y
613CONFIG_NETDEV_10000=y
614# CONFIG_AX88180 is not set 613# CONFIG_AX88180 is not set
614CONFIG_NETDEV_10000=y
615 615
616# 616#
617# Wireless LAN 617# Wireless LAN
@@ -680,7 +680,6 @@ CONFIG_INPUT_EVDEV=m
680CONFIG_BFIN_SPORT=y 680CONFIG_BFIN_SPORT=y
681# CONFIG_BFIN_TIMER_LATENCY is not set 681# CONFIG_BFIN_TIMER_LATENCY is not set
682# CONFIG_AD5304 is not set 682# CONFIG_AD5304 is not set
683# CONFIG_BF5xx_FBDMA is not set
684# CONFIG_VT is not set 683# CONFIG_VT is not set
685# CONFIG_SERIAL_NONSTANDARD is not set 684# CONFIG_SERIAL_NONSTANDARD is not set
686 685
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index b04e8e533e9a..9b7123cf27a3 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -1,6 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.16
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
115# Processor and Board Settings 115# Processor and Board Settings
116# 116#
117# CONFIG_BF522 is not set 117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
118# CONFIG_BF525 is not set 120# CONFIG_BF525 is not set
121# CONFIG_BF526 is not set
119# CONFIG_BF527 is not set 122# CONFIG_BF527 is not set
120# CONFIG_BF531 is not set 123# CONFIG_BF531 is not set
121# CONFIG_BF532 is not set 124# CONFIG_BF532 is not set
@@ -140,7 +143,6 @@ CONFIG_BF_REV_0_3=y
140CONFIG_BF53x=y 143CONFIG_BF53x=y
141CONFIG_BFIN_SINGLE_CORE=y 144CONFIG_BFIN_SINGLE_CORE=y
142CONFIG_MEM_MT48LC64M4A2FB_7E=y 145CONFIG_MEM_MT48LC64M4A2FB_7E=y
143CONFIG_BFIN_SHARED_FLASH_ENET=y
144# CONFIG_BFIN533_EZKIT is not set 146# CONFIG_BFIN533_EZKIT is not set
145CONFIG_BFIN533_STAMP=y 147CONFIG_BFIN533_STAMP=y
146# CONFIG_BFIN533_BLUETECHNIX_CM is not set 148# CONFIG_BFIN533_BLUETECHNIX_CM is not set
@@ -195,7 +197,7 @@ CONFIG_CLKIN_HZ=11059200
195# CONFIG_BFIN_KERNEL_CLOCK is not set 197# CONFIG_BFIN_KERNEL_CLOCK is not set
196CONFIG_MAX_VCO_HZ=750000000 198CONFIG_MAX_VCO_HZ=750000000
197CONFIG_MIN_VCO_HZ=50000000 199CONFIG_MIN_VCO_HZ=50000000
198CONFIG_MAX_SCLK_HZ=133000000 200CONFIG_MAX_SCLK_HZ=133333333
199CONFIG_MIN_SCLK_HZ=27000000 201CONFIG_MIN_SCLK_HZ=27000000
200 202
201# 203#
@@ -215,18 +217,10 @@ CONFIG_MEM_ADD_WIDTH=11
215CONFIG_ENET_FLASH_PIN=0 217CONFIG_ENET_FLASH_PIN=0
216CONFIG_BOOT_LOAD=0x1000 218CONFIG_BOOT_LOAD=0x1000
217 219
218# 220
219# LED Status Indicators
220#
221# CONFIG_BFIN_ALIVE_LED is not set
222# CONFIG_BFIN_IDLE_LED is not set
223CONFIG_BFIN_SCRATCH_REG_RETN=y 221CONFIG_BFIN_SCRATCH_REG_RETN=y
224# CONFIG_BFIN_SCRATCH_REG_RETE is not set 222# CONFIG_BFIN_SCRATCH_REG_RETE is not set
225# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set 223# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
226CONFIG_BFIN_ALIVE_LED_PORT=0xFFC00700
227CONFIG_BFIN_ALIVE_LED_DPORT=0xFFC00730
228CONFIG_BFIN_IDLE_LED_PORT=0xFFC00700
229CONFIG_BFIN_IDLE_LED_DPORT=0xFFC00730
230 224
231# 225#
232# Blackfin Kernel Optimizations 226# Blackfin Kernel Optimizations
@@ -279,6 +273,7 @@ CONFIG_BFIN_DCACHE=y
279# CONFIG_BFIN_WB is not set 273# CONFIG_BFIN_WB is not set
280CONFIG_BFIN_WT=y 274CONFIG_BFIN_WT=y
281CONFIG_L1_MAX_PIECE=16 275CONFIG_L1_MAX_PIECE=16
276# CONFIG_MPU is not set
282 277
283# 278#
284# Asynchonous Memory Configuration 279# Asynchonous Memory Configuration
@@ -333,7 +328,7 @@ CONFIG_PM=y
333CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y 328CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y
334# CONFIG_PM_WAKEUP_BY_GPIO is not set 329# CONFIG_PM_WAKEUP_BY_GPIO is not set
335# CONFIG_PM_WAKEUP_GPIO_API is not set 330# CONFIG_PM_WAKEUP_GPIO_API is not set
336CONFIG_PM_WAKEUP_SIC_IWR=0x100000 331CONFIG_PM_WAKEUP_SIC_IWR=0x80
337 332
338# 333#
339# CPU Frequency scaling 334# CPU Frequency scaling
@@ -522,7 +517,6 @@ CONFIG_MTD_CFI_I2=y
522# CONFIG_MTD_CFI_INTELEXT is not set 517# CONFIG_MTD_CFI_INTELEXT is not set
523# CONFIG_MTD_CFI_AMDSTD is not set 518# CONFIG_MTD_CFI_AMDSTD is not set
524# CONFIG_MTD_CFI_STAA is not set 519# CONFIG_MTD_CFI_STAA is not set
525CONFIG_MTD_MW320D=m
526CONFIG_MTD_RAM=y 520CONFIG_MTD_RAM=y
527CONFIG_MTD_ROM=m 521CONFIG_MTD_ROM=m
528# CONFIG_MTD_ABSENT is not set 522# CONFIG_MTD_ABSENT is not set
@@ -532,17 +526,6 @@ CONFIG_MTD_ROM=m
532# 526#
533CONFIG_MTD_COMPLEX_MAPPINGS=y 527CONFIG_MTD_COMPLEX_MAPPINGS=y
534# CONFIG_MTD_PHYSMAP is not set 528# CONFIG_MTD_PHYSMAP is not set
535CONFIG_MTD_BF5xx=m
536CONFIG_BFIN_FLASH_SIZE=0x400000
537CONFIG_EBIU_FLASH_BASE=0x20000000
538
539#
540# FLASH_EBIU_AMBCTL Control
541#
542CONFIG_BFIN_FLASH_BANK_0=0x7BB0
543CONFIG_BFIN_FLASH_BANK_1=0x7BB0
544CONFIG_BFIN_FLASH_BANK_2=0x7BB0
545CONFIG_BFIN_FLASH_BANK_3=0x7BB0
546# CONFIG_MTD_UCLINUX is not set 529# CONFIG_MTD_UCLINUX is not set
547# CONFIG_MTD_PLATRAM is not set 530# CONFIG_MTD_PLATRAM is not set
548 531
@@ -630,8 +613,8 @@ CONFIG_SMC91X=y
630# CONFIG_SMSC911X is not set 613# CONFIG_SMSC911X is not set
631# CONFIG_DM9000 is not set 614# CONFIG_DM9000 is not set
632CONFIG_NETDEV_1000=y 615CONFIG_NETDEV_1000=y
633CONFIG_NETDEV_10000=y
634# CONFIG_AX88180 is not set 616# CONFIG_AX88180 is not set
617CONFIG_NETDEV_10000=y
635 618
636# 619#
637# Wireless LAN 620# Wireless LAN
@@ -687,7 +670,6 @@ CONFIG_INPUT_MISC=y
687# CONFIG_INPUT_POWERMATE is not set 670# CONFIG_INPUT_POWERMATE is not set
688# CONFIG_INPUT_YEALINK is not set 671# CONFIG_INPUT_YEALINK is not set
689# CONFIG_INPUT_UINPUT is not set 672# CONFIG_INPUT_UINPUT is not set
690# CONFIG_BF53X_PFBUTTONS is not set
691CONFIG_TWI_KEYPAD=m 673CONFIG_TWI_KEYPAD=m
692CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=39 674CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=39
693 675
@@ -711,8 +693,6 @@ CONFIG_BFIN_SPORT=y
711CONFIG_TWI_LCD=m 693CONFIG_TWI_LCD=m
712CONFIG_TWI_LCD_SLAVE_ADDR=34 694CONFIG_TWI_LCD_SLAVE_ADDR=34
713# CONFIG_AD5304 is not set 695# CONFIG_AD5304 is not set
714# CONFIG_BF5xx_TEA5764 is not set
715# CONFIG_BF5xx_FBDMA is not set
716# CONFIG_VT is not set 696# CONFIG_VT is not set
717# CONFIG_SERIAL_NONSTANDARD is not set 697# CONFIG_SERIAL_NONSTANDARD is not set
718 698
@@ -778,7 +758,6 @@ CONFIG_I2C_ALGOBIT=m
778# 758#
779# I2C Hardware Bus support 759# I2C Hardware Bus support
780# 760#
781# CONFIG_I2C_BLACKFIN_GPIO is not set
782# CONFIG_I2C_GPIO is not set 761# CONFIG_I2C_GPIO is not set
783# CONFIG_I2C_OCORES is not set 762# CONFIG_I2C_OCORES is not set
784# CONFIG_I2C_PARPORT_LIGHT is not set 763# CONFIG_I2C_PARPORT_LIGHT is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index f812b66318b9..b37ccc681e7a 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -1,6 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.16
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
115# Processor and Board Settings 115# Processor and Board Settings
116# 116#
117# CONFIG_BF522 is not set 117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
118# CONFIG_BF525 is not set 120# CONFIG_BF525 is not set
121# CONFIG_BF526 is not set
119# CONFIG_BF527 is not set 122# CONFIG_BF527 is not set
120# CONFIG_BF531 is not set 123# CONFIG_BF531 is not set
121# CONFIG_BF532 is not set 124# CONFIG_BF532 is not set
@@ -170,6 +173,7 @@ CONFIG_IRQ_WATCH=13
170CONFIG_BFIN537_STAMP=y 173CONFIG_BFIN537_STAMP=y
171# CONFIG_BFIN537_BLUETECHNIX_CM is not set 174# CONFIG_BFIN537_BLUETECHNIX_CM is not set
172# CONFIG_PNAV10 is not set 175# CONFIG_PNAV10 is not set
176# CONFIG_CAMSIG_MINOTAUR is not set
173# CONFIG_GENERIC_BF537_BOARD is not set 177# CONFIG_GENERIC_BF537_BOARD is not set
174 178
175# 179#
@@ -201,7 +205,7 @@ CONFIG_CLKIN_HZ=25000000
201# CONFIG_BFIN_KERNEL_CLOCK is not set 205# CONFIG_BFIN_KERNEL_CLOCK is not set
202CONFIG_MAX_VCO_HZ=600000000 206CONFIG_MAX_VCO_HZ=600000000
203CONFIG_MIN_VCO_HZ=50000000 207CONFIG_MIN_VCO_HZ=50000000
204CONFIG_MAX_SCLK_HZ=133000000 208CONFIG_MAX_SCLK_HZ=133333333
205CONFIG_MIN_SCLK_HZ=27000000 209CONFIG_MIN_SCLK_HZ=27000000
206 210
207# 211#
@@ -274,6 +278,7 @@ CONFIG_BFIN_DCACHE=y
274# CONFIG_BFIN_WB is not set 278# CONFIG_BFIN_WB is not set
275CONFIG_BFIN_WT=y 279CONFIG_BFIN_WT=y
276CONFIG_L1_MAX_PIECE=16 280CONFIG_L1_MAX_PIECE=16
281# CONFIG_MPU is not set
277 282
278# 283#
279# Asynchonous Memory Configuration 284# Asynchonous Memory Configuration
@@ -328,7 +333,7 @@ CONFIG_PM=y
328CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y 333CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y
329# CONFIG_PM_WAKEUP_BY_GPIO is not set 334# CONFIG_PM_WAKEUP_BY_GPIO is not set
330# CONFIG_PM_WAKEUP_GPIO_API is not set 335# CONFIG_PM_WAKEUP_GPIO_API is not set
331CONFIG_PM_WAKEUP_SIC_IWR=0x80000000 336CONFIG_PM_WAKEUP_SIC_IWR=0x8
332 337
333# 338#
334# CPU Frequency scaling 339# CPU Frequency scaling
@@ -483,7 +488,7 @@ CONFIG_MTD=y
483# CONFIG_MTD_CONCAT is not set 488# CONFIG_MTD_CONCAT is not set
484CONFIG_MTD_PARTITIONS=y 489CONFIG_MTD_PARTITIONS=y
485# CONFIG_MTD_REDBOOT_PARTS is not set 490# CONFIG_MTD_REDBOOT_PARTS is not set
486# CONFIG_MTD_CMDLINE_PARTS is not set 491CONFIG_MTD_CMDLINE_PARTS=y
487 492
488# 493#
489# User Modules And Translation Layers 494# User Modules And Translation Layers
@@ -500,8 +505,8 @@ CONFIG_MTD_BLOCK=y
500# 505#
501# RAM/ROM/Flash chip drivers 506# RAM/ROM/Flash chip drivers
502# 507#
503# CONFIG_MTD_CFI is not set 508CONFIG_MTD_CFI=m
504CONFIG_MTD_JEDECPROBE=m 509# CONFIG_MTD_JEDECPROBE is not set
505CONFIG_MTD_GEN_PROBE=m 510CONFIG_MTD_GEN_PROBE=m
506# CONFIG_MTD_CFI_ADV_OPTIONS is not set 511# CONFIG_MTD_CFI_ADV_OPTIONS is not set
507CONFIG_MTD_MAP_BANK_WIDTH_1=y 512CONFIG_MTD_MAP_BANK_WIDTH_1=y
@@ -515,9 +520,9 @@ CONFIG_MTD_CFI_I2=y
515# CONFIG_MTD_CFI_I4 is not set 520# CONFIG_MTD_CFI_I4 is not set
516# CONFIG_MTD_CFI_I8 is not set 521# CONFIG_MTD_CFI_I8 is not set
517# CONFIG_MTD_CFI_INTELEXT is not set 522# CONFIG_MTD_CFI_INTELEXT is not set
518# CONFIG_MTD_CFI_AMDSTD is not set 523CONFIG_MTD_CFI_AMDSTD=m
519# CONFIG_MTD_CFI_STAA is not set 524# CONFIG_MTD_CFI_STAA is not set
520CONFIG_MTD_MW320D=m 525CONFIG_MTD_CFI_UTIL=m
521CONFIG_MTD_RAM=y 526CONFIG_MTD_RAM=y
522CONFIG_MTD_ROM=m 527CONFIG_MTD_ROM=m
523# CONFIG_MTD_ABSENT is not set 528# CONFIG_MTD_ABSENT is not set
@@ -525,11 +530,11 @@ CONFIG_MTD_ROM=m
525# 530#
526# Mapping drivers for chip access 531# Mapping drivers for chip access
527# 532#
528CONFIG_MTD_COMPLEX_MAPPINGS=y 533# CONFIG_MTD_COMPLEX_MAPPINGS is not set
529# CONFIG_MTD_PHYSMAP is not set 534CONFIG_MTD_PHYSMAP=m
530CONFIG_MTD_BF5xx=m 535CONFIG_MTD_PHYSMAP_START=0x20000000
531CONFIG_BFIN_FLASH_SIZE=0x400000 536CONFIG_MTD_PHYSMAP_LEN=0x0
532CONFIG_EBIU_FLASH_BASE=0x20000000 537CONFIG_MTD_PHYSMAP_BANKWIDTH=2
533# CONFIG_MTD_UCLINUX is not set 538# CONFIG_MTD_UCLINUX is not set
534# CONFIG_MTD_PLATRAM is not set 539# CONFIG_MTD_PLATRAM is not set
535 540
@@ -647,8 +652,8 @@ CONFIG_BFIN_RX_DESC_NUM=20
647# CONFIG_SMSC911X is not set 652# CONFIG_SMSC911X is not set
648# CONFIG_DM9000 is not set 653# CONFIG_DM9000 is not set
649CONFIG_NETDEV_1000=y 654CONFIG_NETDEV_1000=y
650CONFIG_NETDEV_10000=y
651# CONFIG_AX88180 is not set 655# CONFIG_AX88180 is not set
656CONFIG_NETDEV_10000=y
652 657
653# 658#
654# Wireless LAN 659# Wireless LAN
@@ -704,7 +709,6 @@ CONFIG_INPUT_MISC=y
704# CONFIG_INPUT_POWERMATE is not set 709# CONFIG_INPUT_POWERMATE is not set
705# CONFIG_INPUT_YEALINK is not set 710# CONFIG_INPUT_YEALINK is not set
706# CONFIG_INPUT_UINPUT is not set 711# CONFIG_INPUT_UINPUT is not set
707# CONFIG_BF53X_PFBUTTONS is not set
708CONFIG_TWI_KEYPAD=m 712CONFIG_TWI_KEYPAD=m
709CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=72 713CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=72
710 714
@@ -728,8 +732,6 @@ CONFIG_BFIN_SPORT=y
728CONFIG_TWI_LCD=m 732CONFIG_TWI_LCD=m
729CONFIG_TWI_LCD_SLAVE_ADDR=34 733CONFIG_TWI_LCD_SLAVE_ADDR=34
730# CONFIG_AD5304 is not set 734# CONFIG_AD5304 is not set
731# CONFIG_BF5xx_TEA5764 is not set
732# CONFIG_BF5xx_FBDMA is not set
733# CONFIG_VT is not set 735# CONFIG_VT is not set
734# CONFIG_SERIAL_NONSTANDARD is not set 736# CONFIG_SERIAL_NONSTANDARD is not set
735 737
@@ -802,7 +804,6 @@ CONFIG_I2C_CHARDEV=m
802# 804#
803# I2C Hardware Bus support 805# I2C Hardware Bus support
804# 806#
805# CONFIG_I2C_BLACKFIN_GPIO is not set
806CONFIG_I2C_BLACKFIN_TWI=m 807CONFIG_I2C_BLACKFIN_TWI=m
807CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 808CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
808# CONFIG_I2C_GPIO is not set 809# CONFIG_I2C_GPIO is not set
@@ -957,6 +958,7 @@ CONFIG_LQ035_SLAVE_ADDR=0x58
957# CONFIG_FB_BFIN_LANDSCAPE is not set 958# CONFIG_FB_BFIN_LANDSCAPE is not set
958# CONFIG_FB_BFIN_BGR is not set 959# CONFIG_FB_BFIN_BGR is not set
959# CONFIG_FB_BFIN_T350MCQB is not set 960# CONFIG_FB_BFIN_T350MCQB is not set
961# CONFIG_FB_HITACHI_TX09 is not set
960# CONFIG_FB_S1D13XXX is not set 962# CONFIG_FB_S1D13XXX is not set
961# CONFIG_FB_VIRTUAL is not set 963# CONFIG_FB_VIRTUAL is not set
962# CONFIG_LOGO is not set 964# CONFIG_LOGO is not set
@@ -1008,12 +1010,22 @@ CONFIG_SND_BFIN_AD73311_SE=4
1008# 1010#
1009# System on Chip audio support 1011# System on Chip audio support
1010# 1012#
1011# CONFIG_SND_SOC is not set 1013CONFIG_SND_SOC_AC97_BUS=y
1014CONFIG_SND_SOC=m
1015CONFIG_SND_BF5XX_SOC=m
1016CONFIG_SND_BF5XX_SOC_AC97=m
1017# CONFIG_SND_BF5XX_SOC_WM8750 is not set
1018# CONFIG_SND_BF5XX_SOC_WM8731 is not set
1019CONFIG_SND_BF5XX_SOC_BF5xx=m
1020CONFIG_SND_BF5XX_SPORT_NUM=0
1021# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
1022CONFIG_SND_SOC_AD1980=m
1012 1023
1013# 1024#
1014# Open Sound System 1025# Open Sound System
1015# 1026#
1016# CONFIG_SOUND_PRIME is not set 1027# CONFIG_SOUND_PRIME is not set
1028CONFIG_AC97_BUS=m
1017 1029
1018# 1030#
1019# HID Devices 1031# HID Devices
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 48367cc9fe35..fd702161ef59 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,6 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.16
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
115# Processor and Board Settings 115# Processor and Board Settings
116# 116#
117# CONFIG_BF522 is not set 117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
118# CONFIG_BF525 is not set 120# CONFIG_BF525 is not set
121# CONFIG_BF526 is not set
119# CONFIG_BF527 is not set 122# CONFIG_BF527 is not set
120# CONFIG_BF531 is not set 123# CONFIG_BF531 is not set
121# CONFIG_BF532 is not set 124# CONFIG_BF532 is not set
@@ -126,8 +129,8 @@ CONFIG_PREEMPT_VOLUNTARY=y
126# CONFIG_BF542 is not set 129# CONFIG_BF542 is not set
127# CONFIG_BF544 is not set 130# CONFIG_BF544 is not set
128# CONFIG_BF547 is not set 131# CONFIG_BF547 is not set
129# CONFIG_BF548 is not set 132CONFIG_BF548=y
130CONFIG_BF549=y 133# CONFIG_BF549 is not set
131# CONFIG_BF561 is not set 134# CONFIG_BF561 is not set
132CONFIG_BF_REV_0_0=y 135CONFIG_BF_REV_0_0=y
133# CONFIG_BF_REV_0_1 is not set 136# CONFIG_BF_REV_0_1 is not set
@@ -265,9 +268,9 @@ CONFIG_PINT3_ASSIGN=0x02020303
265# 268#
266CONFIG_CLKIN_HZ=25000000 269CONFIG_CLKIN_HZ=25000000
267# CONFIG_BFIN_KERNEL_CLOCK is not set 270# CONFIG_BFIN_KERNEL_CLOCK is not set
268CONFIG_MAX_VCO_HZ=533000000 271CONFIG_MAX_VCO_HZ=600000000
269CONFIG_MIN_VCO_HZ=50000000 272CONFIG_MIN_VCO_HZ=50000000
270CONFIG_MAX_SCLK_HZ=133000000 273CONFIG_MAX_SCLK_HZ=133333333
271CONFIG_MIN_SCLK_HZ=27000000 274CONFIG_MIN_SCLK_HZ=27000000
272 275
273# 276#
@@ -283,7 +286,8 @@ CONFIG_HZ=250
283# Memory Setup 286# Memory Setup
284# 287#
285CONFIG_MEM_SIZE=64 288CONFIG_MEM_SIZE=64
286CONFIG_MEM_ADD_WIDTH=10 289# CONFIG_MEM_MT46V32M16_6T is not set
290CONFIG_MEM_MT46V32M16_5B=y
287CONFIG_BOOT_LOAD=0x1000 291CONFIG_BOOT_LOAD=0x1000
288CONFIG_BFIN_SCRATCH_REG_RETN=y 292CONFIG_BFIN_SCRATCH_REG_RETN=y
289# CONFIG_BFIN_SCRATCH_REG_RETE is not set 293# CONFIG_BFIN_SCRATCH_REG_RETE is not set
@@ -340,6 +344,7 @@ CONFIG_BFIN_DCACHE=y
340# CONFIG_BFIN_WB is not set 344# CONFIG_BFIN_WB is not set
341CONFIG_BFIN_WT=y 345CONFIG_BFIN_WT=y
342CONFIG_L1_MAX_PIECE=16 346CONFIG_L1_MAX_PIECE=16
347# CONFIG_MPU is not set
343 348
344# 349#
345# Asynchonous Memory Configuration 350# Asynchonous Memory Configuration
@@ -349,6 +354,7 @@ CONFIG_L1_MAX_PIECE=16
349# EBIU_AMGCTL Global Control 354# EBIU_AMGCTL Global Control
350# 355#
351CONFIG_C_AMCKEN=y 356CONFIG_C_AMCKEN=y
357# CONFIG_C_CDPRIO is not set
352# CONFIG_C_AMBEN is not set 358# CONFIG_C_AMBEN is not set
353# CONFIG_C_AMBEN_B0 is not set 359# CONFIG_C_AMBEN_B0 is not set
354# CONFIG_C_AMBEN_B0_B1 is not set 360# CONFIG_C_AMBEN_B0_B1 is not set
@@ -362,9 +368,9 @@ CONFIG_BANK_0=0x7BB0
362CONFIG_BANK_1=0x5554 368CONFIG_BANK_1=0x5554
363CONFIG_BANK_2=0x7BB0 369CONFIG_BANK_2=0x7BB0
364CONFIG_BANK_3=0x99B3 370CONFIG_BANK_3=0x99B3
365CONFIG_EBUI_MBSCTLVAL=0x0 371CONFIG_EBIU_MBSCTLVAL=0x0
366CONFIG_EBUI_MODEVAL=0x1 372CONFIG_EBIU_MODEVAL=0x1
367CONFIG_EBUI_FCTLVAL=0x6 373CONFIG_EBIU_FCTLVAL=0x6
368 374
369# 375#
370# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 376# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
@@ -537,7 +543,6 @@ CONFIG_MTD_CFI_I2=y
537CONFIG_MTD_CFI_INTELEXT=y 543CONFIG_MTD_CFI_INTELEXT=y
538# CONFIG_MTD_CFI_AMDSTD is not set 544# CONFIG_MTD_CFI_AMDSTD is not set
539# CONFIG_MTD_CFI_STAA is not set 545# CONFIG_MTD_CFI_STAA is not set
540# CONFIG_MTD_MW320D is not set
541CONFIG_MTD_CFI_UTIL=y 546CONFIG_MTD_CFI_UTIL=y
542CONFIG_MTD_RAM=y 547CONFIG_MTD_RAM=y
543# CONFIG_MTD_ROM is not set 548# CONFIG_MTD_ROM is not set
@@ -549,9 +554,8 @@ CONFIG_MTD_RAM=y
549CONFIG_MTD_COMPLEX_MAPPINGS=y 554CONFIG_MTD_COMPLEX_MAPPINGS=y
550CONFIG_MTD_PHYSMAP=y 555CONFIG_MTD_PHYSMAP=y
551CONFIG_MTD_PHYSMAP_START=0x20000000 556CONFIG_MTD_PHYSMAP_START=0x20000000
552CONFIG_MTD_PHYSMAP_LEN=0x400000 557CONFIG_MTD_PHYSMAP_LEN=0
553CONFIG_MTD_PHYSMAP_BANKWIDTH=2 558CONFIG_MTD_PHYSMAP_BANKWIDTH=2
554# CONFIG_MTD_BF5xx is not set
555# CONFIG_MTD_UCLINUX is not set 559# CONFIG_MTD_UCLINUX is not set
556# CONFIG_MTD_PLATRAM is not set 560# CONFIG_MTD_PLATRAM is not set
557 561
@@ -690,8 +694,8 @@ CONFIG_MII=y
690CONFIG_SMSC911X=y 694CONFIG_SMSC911X=y
691# CONFIG_DM9000 is not set 695# CONFIG_DM9000 is not set
692CONFIG_NETDEV_1000=y 696CONFIG_NETDEV_1000=y
693CONFIG_NETDEV_10000=y
694# CONFIG_AX88180 is not set 697# CONFIG_AX88180 is not set
698CONFIG_NETDEV_10000=y
695 699
696# 700#
697# Wireless LAN 701# Wireless LAN
@@ -719,7 +723,7 @@ CONFIG_NETDEV_10000=y
719# 723#
720# Input device support 724# Input device support
721# 725#
722CONFIG_INPUT=m 726CONFIG_INPUT=y
723# CONFIG_INPUT_FF_MEMLESS is not set 727# CONFIG_INPUT_FF_MEMLESS is not set
724# CONFIG_INPUT_POLLDEV is not set 728# CONFIG_INPUT_POLLDEV is not set
725 729
@@ -745,7 +749,8 @@ CONFIG_INPUT_KEYBOARD=y
745# CONFIG_KEYBOARD_NEWTON is not set 749# CONFIG_KEYBOARD_NEWTON is not set
746# CONFIG_KEYBOARD_STOWAWAY is not set 750# CONFIG_KEYBOARD_STOWAWAY is not set
747# CONFIG_KEYBOARD_GPIO is not set 751# CONFIG_KEYBOARD_GPIO is not set
748CONFIG_KEYBOARD_BFIN=m 752CONFIG_KEYBOARD_BFIN=y
753# CONFIG_KEYBOARD_OPENCORES is not set
749# CONFIG_INPUT_MOUSE is not set 754# CONFIG_INPUT_MOUSE is not set
750# CONFIG_INPUT_JOYSTICK is not set 755# CONFIG_INPUT_JOYSTICK is not set
751# CONFIG_INPUT_TABLET is not set 756# CONFIG_INPUT_TABLET is not set
@@ -768,7 +773,6 @@ CONFIG_INPUT_MISC=y
768# CONFIG_INPUT_POWERMATE is not set 773# CONFIG_INPUT_POWERMATE is not set
769# CONFIG_INPUT_YEALINK is not set 774# CONFIG_INPUT_YEALINK is not set
770# CONFIG_INPUT_UINPUT is not set 775# CONFIG_INPUT_UINPUT is not set
771# CONFIG_BF53X_PFBUTTONS is not set
772# CONFIG_TWI_KEYPAD is not set 776# CONFIG_TWI_KEYPAD is not set
773 777
774# 778#
@@ -786,13 +790,16 @@ CONFIG_INPUT_MISC=y
786# CONFIG_BF5xx_PPIFCD is not set 790# CONFIG_BF5xx_PPIFCD is not set
787# CONFIG_BFIN_SIMPLE_TIMER is not set 791# CONFIG_BFIN_SIMPLE_TIMER is not set
788# CONFIG_BF5xx_PPI is not set 792# CONFIG_BF5xx_PPI is not set
793CONFIG_BFIN_OTP=y
794# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
789# CONFIG_BFIN_SPORT is not set 795# CONFIG_BFIN_SPORT is not set
790# CONFIG_BFIN_TIMER_LATENCY is not set 796# CONFIG_BFIN_TIMER_LATENCY is not set
791# CONFIG_TWI_LCD is not set 797# CONFIG_TWI_LCD is not set
792# CONFIG_AD5304 is not set 798# CONFIG_AD5304 is not set
793# CONFIG_BF5xx_TEA5764 is not set 799CONFIG_VT=y
794# CONFIG_BF5xx_FBDMA is not set 800CONFIG_VT_CONSOLE=y
795# CONFIG_VT is not set 801CONFIG_HW_CONSOLE=y
802# CONFIG_VT_HW_CONSOLE_BINDING is not set
796# CONFIG_SERIAL_NONSTANDARD is not set 803# CONFIG_SERIAL_NONSTANDARD is not set
797 804
798# 805#
@@ -858,7 +865,6 @@ CONFIG_I2C_CHARDEV=y
858# 865#
859# I2C Hardware Bus support 866# I2C Hardware Bus support
860# 867#
861# CONFIG_I2C_BLACKFIN_GPIO is not set
862CONFIG_I2C_BLACKFIN_TWI=y 868CONFIG_I2C_BLACKFIN_TWI=y
863CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 869CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
864# CONFIG_I2C_GPIO is not set 870# CONFIG_I2C_GPIO is not set
@@ -976,12 +982,12 @@ CONFIG_DAB=y
976# 982#
977# CONFIG_DISPLAY_SUPPORT is not set 983# CONFIG_DISPLAY_SUPPORT is not set
978# CONFIG_VGASTATE is not set 984# CONFIG_VGASTATE is not set
979CONFIG_FB=m 985CONFIG_FB=y
980CONFIG_FIRMWARE_EDID=y 986CONFIG_FIRMWARE_EDID=y
981# CONFIG_FB_DDC is not set 987# CONFIG_FB_DDC is not set
982CONFIG_FB_CFB_FILLRECT=m 988CONFIG_FB_CFB_FILLRECT=y
983CONFIG_FB_CFB_COPYAREA=m 989CONFIG_FB_CFB_COPYAREA=y
984CONFIG_FB_CFB_IMAGEBLIT=m 990CONFIG_FB_CFB_IMAGEBLIT=y
985# CONFIG_FB_SYS_FILLRECT is not set 991# CONFIG_FB_SYS_FILLRECT is not set
986# CONFIG_FB_SYS_COPYAREA is not set 992# CONFIG_FB_SYS_COPYAREA is not set
987# CONFIG_FB_SYS_IMAGEBLIT is not set 993# CONFIG_FB_SYS_IMAGEBLIT is not set
@@ -998,11 +1004,34 @@ CONFIG_FB_DEFERRED_IO=y
998# 1004#
999# CONFIG_FB_BFIN_7171 is not set 1005# CONFIG_FB_BFIN_7171 is not set
1000# CONFIG_FB_BFIN_7393 is not set 1006# CONFIG_FB_BFIN_7393 is not set
1001CONFIG_FB_BF54X_LQ043=m 1007CONFIG_FB_BF54X_LQ043=y
1002# CONFIG_FB_BFIN_T350MCQB is not set 1008# CONFIG_FB_BFIN_T350MCQB is not set
1003# CONFIG_FB_S1D13XXX is not set 1009# CONFIG_FB_S1D13XXX is not set
1004# CONFIG_FB_VIRTUAL is not set 1010# CONFIG_FB_VIRTUAL is not set
1005# CONFIG_LOGO is not set 1011
1012#
1013# Console display driver support
1014#
1015CONFIG_DUMMY_CONSOLE=y
1016CONFIG_FRAMEBUFFER_CONSOLE=y
1017# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1018CONFIG_FONTS=y
1019# CONFIG_FONT_8x8 is not set
1020# CONFIG_FONT_8x16 is not set
1021CONFIG_FONT_6x11=y
1022# CONFIG_FONT_7x14 is not set
1023# CONFIG_FONT_PEARL_8x8 is not set
1024# CONFIG_FONT_ACORN_8x8 is not set
1025# CONFIG_FONT_MINI_4x6 is not set
1026# CONFIG_FONT_SUN8x16 is not set
1027# CONFIG_FONT_SUN12x22 is not set
1028# CONFIG_FONT_10x18 is not set
1029CONFIG_LOGO=y
1030# CONFIG_LOGO_LINUX_MONO is not set
1031# CONFIG_LOGO_LINUX_VGA16 is not set
1032# CONFIG_LOGO_LINUX_CLUT224 is not set
1033# CONFIG_LOGO_BLACKFIN_VGA16 is not set
1034CONFIG_LOGO_BLACKFIN_CLUT224=y
1006 1035
1007# 1036#
1008# Sound 1037# Sound
@@ -1051,7 +1080,8 @@ CONFIG_SND_BF5XX_SOC_BF548_EZKIT=y
1051# CONFIG_SND_BF5XX_SOC_WM8750 is not set 1080# CONFIG_SND_BF5XX_SOC_WM8750 is not set
1052# CONFIG_SND_BF5XX_SOC_WM8731 is not set 1081# CONFIG_SND_BF5XX_SOC_WM8731 is not set
1053CONFIG_SND_BF5XX_SPORT_NUM=0 1082CONFIG_SND_BF5XX_SPORT_NUM=0
1054# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set 1083CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
1084CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
1055CONFIG_SND_SOC_AD1980=y 1085CONFIG_SND_SOC_AD1980=y
1056 1086
1057# 1087#
@@ -1403,7 +1433,7 @@ CONFIG_NLS_UTF8=m
1403# 1433#
1404# CONFIG_PRINTK_TIME is not set 1434# CONFIG_PRINTK_TIME is not set
1405CONFIG_ENABLE_MUST_CHECK=y 1435CONFIG_ENABLE_MUST_CHECK=y
1406CONFIG_MAGIC_SYSRQ=y 1436# CONFIG_MAGIC_SYSRQ is not set
1407# CONFIG_UNUSED_SYMBOLS is not set 1437# CONFIG_UNUSED_SYMBOLS is not set
1408CONFIG_DEBUG_FS=y 1438CONFIG_DEBUG_FS=y
1409# CONFIG_HEADERS_CHECK is not set 1439# CONFIG_HEADERS_CHECK is not set
@@ -1428,7 +1458,7 @@ CONFIG_ACCESS_CHECK=y
1428# CONFIG_KEYS is not set 1458# CONFIG_KEYS is not set
1429CONFIG_SECURITY=y 1459CONFIG_SECURITY=y
1430# CONFIG_SECURITY_NETWORK is not set 1460# CONFIG_SECURITY_NETWORK is not set
1431CONFIG_SECURITY_CAPABILITIES=y 1461CONFIG_SECURITY_CAPABILITIES=m
1432 1462
1433# 1463#
1434# Cryptographic options 1464# Cryptographic options
@@ -1439,7 +1469,7 @@ CONFIG_SECURITY_CAPABILITIES=y
1439# Library routines 1469# Library routines
1440# 1470#
1441CONFIG_BITREVERSE=y 1471CONFIG_BITREVERSE=y
1442# CONFIG_CRC_CCITT is not set 1472CONFIG_CRC_CCITT=m
1443# CONFIG_CRC16 is not set 1473# CONFIG_CRC16 is not set
1444# CONFIG_CRC_ITU_T is not set 1474# CONFIG_CRC_ITU_T is not set
1445CONFIG_CRC32=y 1475CONFIG_CRC32=y
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index e9f100b45eb1..8546994939fb 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,6 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.16
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
115# Processor and Board Settings 115# Processor and Board Settings
116# 116#
117# CONFIG_BF522 is not set 117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
118# CONFIG_BF525 is not set 120# CONFIG_BF525 is not set
121# CONFIG_BF526 is not set
119# CONFIG_BF527 is not set 122# CONFIG_BF527 is not set
120# CONFIG_BF531 is not set 123# CONFIG_BF531 is not set
121# CONFIG_BF532 is not set 124# CONFIG_BF532 is not set
@@ -238,7 +241,7 @@ CONFIG_CLKIN_HZ=30000000
238# CONFIG_BFIN_KERNEL_CLOCK is not set 241# CONFIG_BFIN_KERNEL_CLOCK is not set
239CONFIG_MAX_VCO_HZ=600000000 242CONFIG_MAX_VCO_HZ=600000000
240CONFIG_MIN_VCO_HZ=50000000 243CONFIG_MIN_VCO_HZ=50000000
241CONFIG_MAX_SCLK_HZ=133000000 244CONFIG_MAX_SCLK_HZ=133333333
242CONFIG_MIN_SCLK_HZ=27000000 245CONFIG_MIN_SCLK_HZ=27000000
243 246
244# 247#
@@ -311,6 +314,7 @@ CONFIG_BFIN_DCACHE=y
311# CONFIG_BFIN_WB is not set 314# CONFIG_BFIN_WB is not set
312CONFIG_BFIN_WT=y 315CONFIG_BFIN_WT=y
313CONFIG_L1_MAX_PIECE=16 316CONFIG_L1_MAX_PIECE=16
317# CONFIG_MPU is not set
314 318
315# 319#
316# Asynchonous Memory Configuration 320# Asynchonous Memory Configuration
@@ -512,7 +516,7 @@ CONFIG_MTD=y
512# CONFIG_MTD_CONCAT is not set 516# CONFIG_MTD_CONCAT is not set
513CONFIG_MTD_PARTITIONS=y 517CONFIG_MTD_PARTITIONS=y
514# CONFIG_MTD_REDBOOT_PARTS is not set 518# CONFIG_MTD_REDBOOT_PARTS is not set
515# CONFIG_MTD_CMDLINE_PARTS is not set 519CONFIG_MTD_CMDLINE_PARTS=y
516 520
517# 521#
518# User Modules And Translation Layers 522# User Modules And Translation Layers
@@ -529,8 +533,8 @@ CONFIG_MTD_BLOCK=y
529# 533#
530# RAM/ROM/Flash chip drivers 534# RAM/ROM/Flash chip drivers
531# 535#
532# CONFIG_MTD_CFI is not set 536CONFIG_MTD_CFI=m
533CONFIG_MTD_JEDECPROBE=m 537# CONFIG_MTD_JEDECPROBE is not set
534CONFIG_MTD_GEN_PROBE=m 538CONFIG_MTD_GEN_PROBE=m
535# CONFIG_MTD_CFI_ADV_OPTIONS is not set 539# CONFIG_MTD_CFI_ADV_OPTIONS is not set
536CONFIG_MTD_MAP_BANK_WIDTH_1=y 540CONFIG_MTD_MAP_BANK_WIDTH_1=y
@@ -544,9 +548,9 @@ CONFIG_MTD_CFI_I2=y
544# CONFIG_MTD_CFI_I4 is not set 548# CONFIG_MTD_CFI_I4 is not set
545# CONFIG_MTD_CFI_I8 is not set 549# CONFIG_MTD_CFI_I8 is not set
546# CONFIG_MTD_CFI_INTELEXT is not set 550# CONFIG_MTD_CFI_INTELEXT is not set
547# CONFIG_MTD_CFI_AMDSTD is not set 551CONFIG_MTD_CFI_AMDSTD=m
548# CONFIG_MTD_CFI_STAA is not set 552# CONFIG_MTD_CFI_STAA is not set
549CONFIG_MTD_MW320D=m 553CONFIG_MTD_CFI_UTIL=m
550CONFIG_MTD_RAM=y 554CONFIG_MTD_RAM=y
551CONFIG_MTD_ROM=m 555CONFIG_MTD_ROM=m
552# CONFIG_MTD_ABSENT is not set 556# CONFIG_MTD_ABSENT is not set
@@ -554,12 +558,11 @@ CONFIG_MTD_ROM=m
554# 558#
555# Mapping drivers for chip access 559# Mapping drivers for chip access
556# 560#
557CONFIG_MTD_COMPLEX_MAPPINGS=y 561# CONFIG_MTD_COMPLEX_MAPPINGS is not set
558# CONFIG_MTD_PHYSMAP is not set 562CONFIG_MTD_PHYSMAP=m
559# CONFIG_MTD_EZKIT561 is not set 563CONFIG_MTD_PHYSMAP_START=0x20000000
560CONFIG_MTD_BF5xx=m 564CONFIG_MTD_PHYSMAP_LEN=0x0
561CONFIG_BFIN_FLASH_SIZE=0x0400000 565CONFIG_MTD_PHYSMAP_BANKWIDTH=2
562CONFIG_EBIU_FLASH_BASE=0x20000000
563# CONFIG_MTD_UCLINUX is not set 566# CONFIG_MTD_UCLINUX is not set
564# CONFIG_MTD_PLATRAM is not set 567# CONFIG_MTD_PLATRAM is not set
565 568
@@ -647,8 +650,8 @@ CONFIG_SMC91X=y
647# CONFIG_SMSC911X is not set 650# CONFIG_SMSC911X is not set
648# CONFIG_DM9000 is not set 651# CONFIG_DM9000 is not set
649CONFIG_NETDEV_1000=y 652CONFIG_NETDEV_1000=y
650CONFIG_NETDEV_10000=y
651# CONFIG_AX88180 is not set 653# CONFIG_AX88180 is not set
654CONFIG_NETDEV_10000=y
652 655
653# 656#
654# Wireless LAN 657# Wireless LAN
@@ -717,7 +720,6 @@ CONFIG_INPUT_EVDEV=m
717# CONFIG_BFIN_SPORT is not set 720# CONFIG_BFIN_SPORT is not set
718# CONFIG_BFIN_TIMER_LATENCY is not set 721# CONFIG_BFIN_TIMER_LATENCY is not set
719# CONFIG_AD5304 is not set 722# CONFIG_AD5304 is not set
720# CONFIG_BF5xx_FBDMA is not set
721# CONFIG_VT is not set 723# CONFIG_VT is not set
722# CONFIG_SERIAL_NONSTANDARD is not set 724# CONFIG_SERIAL_NONSTANDARD is not set
723 725
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 8a4cfb293b27..318b9b692a48 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \ 9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
10 fixed_code.o cplbinit.o cacheinit.o reboot.o bfin_gpio.o 10 fixed_code.o reboot.o bfin_gpio.o
11 11
12obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 12obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
13obj-$(CONFIG_MODULES) += module.o 13obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index b54446055a43..fa9debe8d5f4 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -339,13 +339,13 @@ EXPORT_SYMBOL(set_dma_config);
339 339
340unsigned short 340unsigned short
341set_bfin_dma_config(char direction, char flow_mode, 341set_bfin_dma_config(char direction, char flow_mode,
342 char intr_mode, char dma_mode, char width) 342 char intr_mode, char dma_mode, char width, char syncmode)
343{ 343{
344 unsigned short config; 344 unsigned short config;
345 345
346 config = 346 config =
347 ((direction << 1) | (width << 2) | (dma_mode << 4) | 347 ((direction << 1) | (width << 2) | (dma_mode << 4) |
348 (intr_mode << 6) | (flow_mode << 12) | RESTART); 348 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5));
349 return config; 349 return config;
350} 350}
351EXPORT_SYMBOL(set_bfin_dma_config); 351EXPORT_SYMBOL(set_bfin_dma_config);
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index ce85d4bf34ca..6bbe0a2fccb8 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -7,7 +7,7 @@
7 * Description: GPIO Abstraction Layer 7 * Description: GPIO Abstraction Layer
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2007 Analog Devices Inc. 10 * Copyright 2008 Analog Devices Inc.
11 * 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * 13 *
@@ -83,6 +83,7 @@
83#include <linux/delay.h> 83#include <linux/delay.h>
84#include <linux/module.h> 84#include <linux/module.h>
85#include <linux/err.h> 85#include <linux/err.h>
86#include <linux/proc_fs.h>
86#include <asm/blackfin.h> 87#include <asm/blackfin.h>
87#include <asm/gpio.h> 88#include <asm/gpio.h>
88#include <asm/portmux.h> 89#include <asm/portmux.h>
@@ -136,7 +137,6 @@ static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
136 (unsigned short *) PORTG_FER, 137 (unsigned short *) PORTG_FER,
137 (unsigned short *) PORTH_FER, 138 (unsigned short *) PORTH_FER,
138}; 139};
139
140#endif 140#endif
141 141
142#ifdef BF527_FAMILY 142#ifdef BF527_FAMILY
@@ -178,15 +178,13 @@ static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
178#endif 178#endif
179 179
180static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; 180static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
181static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)]; 181static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
182 182
183#define MAX_RESOURCES 256
184#define RESOURCE_LABEL_SIZE 16 183#define RESOURCE_LABEL_SIZE 16
185 184
186struct str_ident { 185static struct str_ident {
187 char name[RESOURCE_LABEL_SIZE]; 186 char name[RESOURCE_LABEL_SIZE];
188} *str_ident; 187} str_ident[MAX_RESOURCES];
189
190 188
191#ifdef CONFIG_PM 189#ifdef CONFIG_PM
192static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; 190static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -212,7 +210,7 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INT
212#endif /* CONFIG_PM */ 210#endif /* CONFIG_PM */
213 211
214#if defined(BF548_FAMILY) 212#if defined(BF548_FAMILY)
215inline int check_gpio(unsigned short gpio) 213inline int check_gpio(unsigned gpio)
216{ 214{
217 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 215 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
218 || gpio == GPIO_PH14 || gpio == GPIO_PH15 216 || gpio == GPIO_PH14 || gpio == GPIO_PH15
@@ -222,7 +220,7 @@ inline int check_gpio(unsigned short gpio)
222 return 0; 220 return 0;
223} 221}
224#else 222#else
225inline int check_gpio(unsigned short gpio) 223inline int check_gpio(unsigned gpio)
226{ 224{
227 if (gpio >= MAX_BLACKFIN_GPIOS) 225 if (gpio >= MAX_BLACKFIN_GPIOS)
228 return -EINVAL; 226 return -EINVAL;
@@ -230,9 +228,13 @@ inline int check_gpio(unsigned short gpio)
230} 228}
231#endif 229#endif
232 230
233static void set_label(unsigned short ident, const char *label) 231void gpio_error(unsigned gpio)
234{ 232{
233 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
234}
235 235
236static void set_label(unsigned short ident, const char *label)
237{
236 if (label && str_ident) { 238 if (label && str_ident) {
237 strncpy(str_ident[ident].name, label, 239 strncpy(str_ident[ident].name, label,
238 RESOURCE_LABEL_SIZE); 240 RESOURCE_LABEL_SIZE);
@@ -250,6 +252,11 @@ static char *get_label(unsigned short ident)
250 252
251static int cmp_label(unsigned short ident, const char *label) 253static int cmp_label(unsigned short ident, const char *label)
252{ 254{
255 if (label == NULL) {
256 dump_stack();
257 printk(KERN_ERR "Please provide none-null label\n");
258 }
259
253 if (label && str_ident) 260 if (label && str_ident)
254 return strncmp(str_ident[ident].name, 261 return strncmp(str_ident[ident].name,
255 label, strlen(label)); 262 label, strlen(label));
@@ -258,7 +265,7 @@ static int cmp_label(unsigned short ident, const char *label)
258} 265}
259 266
260#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 267#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
261static void port_setup(unsigned short gpio, unsigned short usage) 268static void port_setup(unsigned gpio, unsigned short usage)
262{ 269{
263 if (!check_gpio(gpio)) { 270 if (!check_gpio(gpio)) {
264 if (usage == GPIO_USAGE) 271 if (usage == GPIO_USAGE)
@@ -269,7 +276,7 @@ static void port_setup(unsigned short gpio, unsigned short usage)
269 } 276 }
270} 277}
271#elif defined(BF548_FAMILY) 278#elif defined(BF548_FAMILY)
272static void port_setup(unsigned short gpio, unsigned short usage) 279static void port_setup(unsigned gpio, unsigned short usage)
273{ 280{
274 if (usage == GPIO_USAGE) 281 if (usage == GPIO_USAGE)
275 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); 282 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
@@ -390,7 +397,7 @@ inline void portmux_setup(unsigned short portno, unsigned short function)
390#endif 397#endif
391 398
392#ifndef BF548_FAMILY 399#ifndef BF548_FAMILY
393static void default_gpio(unsigned short gpio) 400static void default_gpio(unsigned gpio)
394{ 401{
395 unsigned short bank, bitmask; 402 unsigned short bank, bitmask;
396 unsigned long flags; 403 unsigned long flags;
@@ -410,7 +417,6 @@ static void default_gpio(unsigned short gpio)
410 gpio_bankb[bank]->edge &= ~bitmask; 417 gpio_bankb[bank]->edge &= ~bitmask;
411 AWA_DUMMY_READ(edge); 418 AWA_DUMMY_READ(edge);
412 local_irq_restore(flags); 419 local_irq_restore(flags);
413
414} 420}
415#else 421#else
416# define default_gpio(...) do { } while (0) 422# define default_gpio(...) do { } while (0)
@@ -418,12 +424,6 @@ static void default_gpio(unsigned short gpio)
418 424
419static int __init bfin_gpio_init(void) 425static int __init bfin_gpio_init(void)
420{ 426{
421 str_ident = kcalloc(MAX_RESOURCES,
422 sizeof(struct str_ident), GFP_KERNEL);
423 if (str_ident == NULL)
424 return -ENOMEM;
425
426 memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident));
427 427
428 printk(KERN_INFO "Blackfin GPIO Controller\n"); 428 printk(KERN_INFO "Blackfin GPIO Controller\n");
429 429
@@ -454,10 +454,9 @@ arch_initcall(bfin_gpio_init);
454/* Set a specific bit */ 454/* Set a specific bit */
455 455
456#define SET_GPIO(name) \ 456#define SET_GPIO(name) \
457void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ 457void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
458{ \ 458{ \
459 unsigned long flags; \ 459 unsigned long flags; \
460 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
461 local_irq_save(flags); \ 460 local_irq_save(flags); \
462 if (arg) \ 461 if (arg) \
463 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ 462 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
@@ -477,10 +476,9 @@ SET_GPIO(both)
477 476
478#if ANOMALY_05000311 || ANOMALY_05000323 477#if ANOMALY_05000311 || ANOMALY_05000323
479#define SET_GPIO_SC(name) \ 478#define SET_GPIO_SC(name) \
480void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ 479void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
481{ \ 480{ \
482 unsigned long flags; \ 481 unsigned long flags; \
483 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
484 local_irq_save(flags); \ 482 local_irq_save(flags); \
485 if (arg) \ 483 if (arg) \
486 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ 484 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
@@ -492,9 +490,8 @@ void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
492EXPORT_SYMBOL(set_gpio_ ## name); 490EXPORT_SYMBOL(set_gpio_ ## name);
493#else 491#else
494#define SET_GPIO_SC(name) \ 492#define SET_GPIO_SC(name) \
495void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ 493void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
496{ \ 494{ \
497 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
498 if (arg) \ 495 if (arg) \
499 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ 496 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
500 else \ 497 else \
@@ -508,19 +505,17 @@ SET_GPIO_SC(maskb)
508SET_GPIO_SC(data) 505SET_GPIO_SC(data)
509 506
510#if ANOMALY_05000311 || ANOMALY_05000323 507#if ANOMALY_05000311 || ANOMALY_05000323
511void set_gpio_toggle(unsigned short gpio) 508void set_gpio_toggle(unsigned gpio)
512{ 509{
513 unsigned long flags; 510 unsigned long flags;
514 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
515 local_irq_save(flags); 511 local_irq_save(flags);
516 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); 512 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
517 AWA_DUMMY_READ(toggle); 513 AWA_DUMMY_READ(toggle);
518 local_irq_restore(flags); 514 local_irq_restore(flags);
519} 515}
520#else 516#else
521void set_gpio_toggle(unsigned short gpio) 517void set_gpio_toggle(unsigned gpio)
522{ 518{
523 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
524 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); 519 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
525} 520}
526#endif 521#endif
@@ -531,7 +526,7 @@ EXPORT_SYMBOL(set_gpio_toggle);
531 526
532#if ANOMALY_05000311 || ANOMALY_05000323 527#if ANOMALY_05000311 || ANOMALY_05000323
533#define SET_GPIO_P(name) \ 528#define SET_GPIO_P(name) \
534void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \ 529void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
535{ \ 530{ \
536 unsigned long flags; \ 531 unsigned long flags; \
537 local_irq_save(flags); \ 532 local_irq_save(flags); \
@@ -542,7 +537,7 @@ void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
542EXPORT_SYMBOL(set_gpiop_ ## name); 537EXPORT_SYMBOL(set_gpiop_ ## name);
543#else 538#else
544#define SET_GPIO_P(name) \ 539#define SET_GPIO_P(name) \
545void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \ 540void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
546{ \ 541{ \
547 gpio_bankb[gpio_bank(gpio)]->name = arg; \ 542 gpio_bankb[gpio_bank(gpio)]->name = arg; \
548} \ 543} \
@@ -558,11 +553,10 @@ SET_GPIO_P(both)
558SET_GPIO_P(maska) 553SET_GPIO_P(maska)
559SET_GPIO_P(maskb) 554SET_GPIO_P(maskb)
560 555
561
562/* Get a specific bit */ 556/* Get a specific bit */
563#if ANOMALY_05000311 || ANOMALY_05000323 557#if ANOMALY_05000311 || ANOMALY_05000323
564#define GET_GPIO(name) \ 558#define GET_GPIO(name) \
565unsigned short get_gpio_ ## name(unsigned short gpio) \ 559unsigned short get_gpio_ ## name(unsigned gpio) \
566{ \ 560{ \
567 unsigned long flags; \ 561 unsigned long flags; \
568 unsigned short ret; \ 562 unsigned short ret; \
@@ -575,7 +569,7 @@ unsigned short get_gpio_ ## name(unsigned short gpio) \
575EXPORT_SYMBOL(get_gpio_ ## name); 569EXPORT_SYMBOL(get_gpio_ ## name);
576#else 570#else
577#define GET_GPIO(name) \ 571#define GET_GPIO(name) \
578unsigned short get_gpio_ ## name(unsigned short gpio) \ 572unsigned short get_gpio_ ## name(unsigned gpio) \
579{ \ 573{ \
580 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \ 574 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
581} \ 575} \
@@ -595,7 +589,7 @@ GET_GPIO(maskb)
595 589
596#if ANOMALY_05000311 || ANOMALY_05000323 590#if ANOMALY_05000311 || ANOMALY_05000323
597#define GET_GPIO_P(name) \ 591#define GET_GPIO_P(name) \
598unsigned short get_gpiop_ ## name(unsigned short gpio) \ 592unsigned short get_gpiop_ ## name(unsigned gpio) \
599{ \ 593{ \
600 unsigned long flags; \ 594 unsigned long flags; \
601 unsigned short ret; \ 595 unsigned short ret; \
@@ -608,7 +602,7 @@ unsigned short get_gpiop_ ## name(unsigned short gpio) \
608EXPORT_SYMBOL(get_gpiop_ ## name); 602EXPORT_SYMBOL(get_gpiop_ ## name);
609#else 603#else
610#define GET_GPIO_P(name) \ 604#define GET_GPIO_P(name) \
611unsigned short get_gpiop_ ## name(unsigned short gpio) \ 605unsigned short get_gpiop_ ## name(unsigned gpio) \
612{ \ 606{ \
613 return (gpio_bankb[gpio_bank(gpio)]->name);\ 607 return (gpio_bankb[gpio_bank(gpio)]->name);\
614} \ 608} \
@@ -645,7 +639,7 @@ GET_GPIO_P(maskb)
645************************************************************* 639*************************************************************
646* MODIFICATION HISTORY : 640* MODIFICATION HISTORY :
647**************************************************************/ 641**************************************************************/
648int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type) 642int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
649{ 643{
650 unsigned long flags; 644 unsigned long flags;
651 645
@@ -653,7 +647,6 @@ int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type)
653 return -EINVAL; 647 return -EINVAL;
654 648
655 local_irq_save(flags); 649 local_irq_save(flags);
656
657 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); 650 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
658 wakeup_flags_map[gpio] = type; 651 wakeup_flags_map[gpio] = type;
659 local_irq_restore(flags); 652 local_irq_restore(flags);
@@ -662,7 +655,7 @@ int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type)
662} 655}
663EXPORT_SYMBOL(gpio_pm_wakeup_request); 656EXPORT_SYMBOL(gpio_pm_wakeup_request);
664 657
665void gpio_pm_wakeup_free(unsigned short gpio) 658void gpio_pm_wakeup_free(unsigned gpio)
666{ 659{
667 unsigned long flags; 660 unsigned long flags;
668 661
@@ -677,7 +670,7 @@ void gpio_pm_wakeup_free(unsigned short gpio)
677} 670}
678EXPORT_SYMBOL(gpio_pm_wakeup_free); 671EXPORT_SYMBOL(gpio_pm_wakeup_free);
679 672
680static int bfin_gpio_wakeup_type(unsigned short gpio, unsigned char type) 673static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
681{ 674{
682 port_setup(gpio, GPIO_USAGE); 675 port_setup(gpio, GPIO_USAGE);
683 set_gpio_dir(gpio, 0); 676 set_gpio_dir(gpio, 0);
@@ -784,6 +777,14 @@ void gpio_pm_restore(void)
784} 777}
785 778
786#endif 779#endif
780#else /* BF548_FAMILY */
781
782unsigned short get_gpio_dir(unsigned gpio)
783{
784 return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio)));
785}
786EXPORT_SYMBOL(get_gpio_dir);
787
787#endif /* BF548_FAMILY */ 788#endif /* BF548_FAMILY */
788 789
789/*********************************************************** 790/***********************************************************
@@ -1028,7 +1029,7 @@ EXPORT_SYMBOL(peripheral_free_list);
1028* MODIFICATION HISTORY : 1029* MODIFICATION HISTORY :
1029**************************************************************/ 1030**************************************************************/
1030 1031
1031int gpio_request(unsigned short gpio, const char *label) 1032int gpio_request(unsigned gpio, const char *label)
1032{ 1033{
1033 unsigned long flags; 1034 unsigned long flags;
1034 1035
@@ -1075,7 +1076,7 @@ int gpio_request(unsigned short gpio, const char *label)
1075} 1076}
1076EXPORT_SYMBOL(gpio_request); 1077EXPORT_SYMBOL(gpio_request);
1077 1078
1078void gpio_free(unsigned short gpio) 1079void gpio_free(unsigned gpio)
1079{ 1080{
1080 unsigned long flags; 1081 unsigned long flags;
1081 1082
@@ -1085,7 +1086,7 @@ void gpio_free(unsigned short gpio)
1085 local_irq_save(flags); 1086 local_irq_save(flags);
1086 1087
1087 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 1088 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1088 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio); 1089 gpio_error(gpio);
1089 dump_stack(); 1090 dump_stack();
1090 local_irq_restore(flags); 1091 local_irq_restore(flags);
1091 return; 1092 return;
@@ -1101,44 +1102,55 @@ void gpio_free(unsigned short gpio)
1101} 1102}
1102EXPORT_SYMBOL(gpio_free); 1103EXPORT_SYMBOL(gpio_free);
1103 1104
1105
1104#ifdef BF548_FAMILY 1106#ifdef BF548_FAMILY
1105void gpio_direction_input(unsigned short gpio) 1107int gpio_direction_input(unsigned gpio)
1106{ 1108{
1107 unsigned long flags; 1109 unsigned long flags;
1108 1110
1109 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); 1111 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1112 gpio_error(gpio);
1113 return -EINVAL;
1114 }
1110 1115
1111 local_irq_save(flags); 1116 local_irq_save(flags);
1112 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); 1117 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1113 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); 1118 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1114 local_irq_restore(flags); 1119 local_irq_restore(flags);
1120
1121 return 0;
1115} 1122}
1116EXPORT_SYMBOL(gpio_direction_input); 1123EXPORT_SYMBOL(gpio_direction_input);
1117 1124
1118void gpio_direction_output(unsigned short gpio) 1125int gpio_direction_output(unsigned gpio, int value)
1119{ 1126{
1120 unsigned long flags; 1127 unsigned long flags;
1121 1128
1122 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); 1129 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1130 gpio_error(gpio);
1131 return -EINVAL;
1132 }
1123 1133
1124 local_irq_save(flags); 1134 local_irq_save(flags);
1125 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); 1135 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
1136 gpio_set_value(gpio, value);
1126 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio); 1137 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1127 local_irq_restore(flags); 1138 local_irq_restore(flags);
1139
1140 return 0;
1128} 1141}
1129EXPORT_SYMBOL(gpio_direction_output); 1142EXPORT_SYMBOL(gpio_direction_output);
1130 1143
1131void gpio_set_value(unsigned short gpio, unsigned short arg) 1144void gpio_set_value(unsigned gpio, int arg)
1132{ 1145{
1133 if (arg) 1146 if (arg)
1134 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio); 1147 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1135 else 1148 else
1136 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio); 1149 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
1137
1138} 1150}
1139EXPORT_SYMBOL(gpio_set_value); 1151EXPORT_SYMBOL(gpio_set_value);
1140 1152
1141unsigned short gpio_get_value(unsigned short gpio) 1153int gpio_get_value(unsigned gpio)
1142{ 1154{
1143 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio))); 1155 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1144} 1156}
@@ -1146,31 +1158,47 @@ EXPORT_SYMBOL(gpio_get_value);
1146 1158
1147#else 1159#else
1148 1160
1149void gpio_direction_input(unsigned short gpio) 1161int gpio_direction_input(unsigned gpio)
1150{ 1162{
1151 unsigned long flags; 1163 unsigned long flags;
1152 1164
1153 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); 1165 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1166 gpio_error(gpio);
1167 return -EINVAL;
1168 }
1154 1169
1155 local_irq_save(flags); 1170 local_irq_save(flags);
1156 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); 1171 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1157 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio); 1172 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1158 AWA_DUMMY_READ(inen); 1173 AWA_DUMMY_READ(inen);
1159 local_irq_restore(flags); 1174 local_irq_restore(flags);
1175
1176 return 0;
1160} 1177}
1161EXPORT_SYMBOL(gpio_direction_input); 1178EXPORT_SYMBOL(gpio_direction_input);
1162 1179
1163void gpio_direction_output(unsigned short gpio) 1180int gpio_direction_output(unsigned gpio, int value)
1164{ 1181{
1165 unsigned long flags; 1182 unsigned long flags;
1166 1183
1167 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); 1184 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1185 gpio_error(gpio);
1186 return -EINVAL;
1187 }
1168 1188
1169 local_irq_save(flags); 1189 local_irq_save(flags);
1170 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); 1190 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1191
1192 if (value)
1193 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
1194 else
1195 gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
1196
1171 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio); 1197 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1172 AWA_DUMMY_READ(dir); 1198 AWA_DUMMY_READ(dir);
1173 local_irq_restore(flags); 1199 local_irq_restore(flags);
1200
1201 return 0;
1174} 1202}
1175EXPORT_SYMBOL(gpio_direction_output); 1203EXPORT_SYMBOL(gpio_direction_output);
1176 1204
@@ -1190,7 +1218,40 @@ void bfin_gpio_reset_spi0_ssel1(void)
1190 1218
1191 port_setup(gpio, GPIO_USAGE); 1219 port_setup(gpio, GPIO_USAGE);
1192 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio); 1220 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
1221 AWA_DUMMY_READ(data_set);
1193 udelay(1); 1222 udelay(1);
1194} 1223}
1195 1224
1196#endif /*BF548_FAMILY */ 1225#endif /*BF548_FAMILY */
1226
1227#if defined(CONFIG_PROC_FS)
1228static int gpio_proc_read(char *buf, char **start, off_t offset,
1229 int len, int *unused_i, void *unused_v)
1230{
1231 int c, outlen = 0;
1232
1233 for (c = 0; c < MAX_RESOURCES; c++) {
1234 if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
1235 len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c,
1236 get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1237 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
1238 len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c));
1239 else
1240 continue;
1241 buf += len;
1242 outlen += len;
1243 }
1244 return outlen;
1245}
1246
1247static __init int gpio_register_proc(void)
1248{
1249 struct proc_dir_entry *proc_gpio;
1250
1251 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1252 if (proc_gpio)
1253 proc_gpio->read_proc = gpio_proc_read;
1254 return proc_gpio != NULL;
1255}
1256__initcall(gpio_register_proc);
1257#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
new file mode 100644
index 000000000000..286b69357f97
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/Makefile
@@ -0,0 +1,8 @@
1#
2# arch/blackfin/kernel/cplb-nompu/Makefile
3#
4
5obj-y := cplbinit.o cacheinit.o cplbmgr.o
6
7obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
8
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
new file mode 100644
index 000000000000..9eecfa403187
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2004-2007 Analog Devices Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see the file COPYING, or write
16 * to the Free Software Foundation, Inc.,
17 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/cpu.h>
21
22#include <asm/cacheflush.h>
23#include <asm/blackfin.h>
24#include <asm/cplb.h>
25#include <asm/cplbinit.h>
26
27#if defined(CONFIG_BFIN_ICACHE)
28void bfin_icache_init(void)
29{
30 unsigned long ctrl;
31 int i;
32
33 SSYNC();
34 for (i = 0; i < MAX_CPLBS; i++) {
35 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
36 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
37 }
38 ctrl = bfin_read_IMEM_CONTROL();
39 ctrl |= IMC | ENICPLB;
40 bfin_write_IMEM_CONTROL(ctrl);
41 SSYNC();
42}
43#endif
44
45#if defined(CONFIG_BFIN_DCACHE)
46void bfin_dcache_init(void)
47{
48 unsigned long ctrl;
49 int i;
50
51 SSYNC();
52 for (i = 0; i < MAX_CPLBS; i++) {
53 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
54 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
55 }
56
57 ctrl = bfin_read_DMEM_CONTROL();
58 ctrl |= DMEM_CNTR;
59 bfin_write_DMEM_CONTROL(ctrl);
60 SSYNC();
61}
62#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c
new file mode 100644
index 000000000000..bd072299f7f2
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c
@@ -0,0 +1,144 @@
1/*
2 * File: arch/blackfin/mach-common/cplbinfo.c
3 * Based on:
4 * Author: Sonic Zhang <sonic.zhang@analog.com>
5 *
6 * Created: Jan. 2005
7 * Description: Display CPLB status
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/proc_fs.h>
34#include <linux/uaccess.h>
35
36#include <asm/current.h>
37#include <asm/system.h>
38#include <asm/cplb.h>
39#include <asm/cplbinit.h>
40#include <asm/blackfin.h>
41
42#define CPLB_I 1
43#define CPLB_D 2
44
45#define SYNC_SYS SSYNC()
46#define SYNC_CORE CSYNC()
47
48#define CPLB_BIT_PAGESIZE 0x30000
49
50static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" };
51
52static char *cplb_print_entry(char *buf, struct cplb_entry *tbl, int switched)
53{
54 int i;
55 buf += sprintf(buf, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
56 for (i = 0; i < MAX_CPLBS; i++) {
57 unsigned long data = tbl[i].data;
58 unsigned long addr = tbl[i].addr;
59 if (!(data & CPLB_VALID))
60 continue;
61
62 buf +=
63 sprintf(buf,
64 "%d\t0x%08lx\t%06lx\t%s\t%c\t%c\t%c\t%c\n",
65 i, addr, data,
66 page_size_string_table[(data & 0x30000) >> 16],
67 (data & CPLB_USER_RD) ? 'Y' : 'N',
68 (data & CPLB_USER_WR) ? 'Y' : 'N',
69 (data & CPLB_SUPV_WR) ? 'Y' : 'N',
70 i < switched ? 'N' : 'Y');
71 }
72 buf += sprintf(buf, "\n");
73
74 return buf;
75}
76
77int cplbinfo_proc_output(char *buf)
78{
79 char *p;
80
81 p = buf;
82
83 p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
84
85 if (bfin_read_IMEM_CONTROL() & ENICPLB) {
86 p += sprintf(p, "Instruction CPLB entry:\n");
87 p = cplb_print_entry(p, icplb_tbl, first_switched_icplb);
88 } else
89 p += sprintf(p, "Instruction CPLB is disabled.\n\n");
90
91 if (1 || bfin_read_DMEM_CONTROL() & ENDCPLB) {
92 p += sprintf(p, "Data CPLB entry:\n");
93 p = cplb_print_entry(p, dcplb_tbl, first_switched_dcplb);
94 } else
95 p += sprintf(p, "Data CPLB is disabled.\n");
96
97 p += sprintf(p, "ICPLB miss: %d\nICPLB supervisor miss: %d\n",
98 nr_icplb_miss, nr_icplb_supv_miss);
99 p += sprintf(p, "DCPLB miss: %d\nDCPLB protection fault:%d\n",
100 nr_dcplb_miss, nr_dcplb_prot);
101 p += sprintf(p, "CPLB flushes: %d\n",
102 nr_cplb_flush);
103
104 return p - buf;
105}
106
107static int cplbinfo_read_proc(char *page, char **start, off_t off,
108 int count, int *eof, void *data)
109{
110 int len;
111
112 len = cplbinfo_proc_output(page);
113 if (len <= off + count)
114 *eof = 1;
115 *start = page + off;
116 len -= off;
117 if (len > count)
118 len = count;
119 if (len < 0)
120 len = 0;
121 return len;
122}
123
124static int __init cplbinfo_init(void)
125{
126 struct proc_dir_entry *entry;
127
128 entry = create_proc_entry("cplbinfo", 0, NULL);
129 if (!entry)
130 return -ENOMEM;
131
132 entry->read_proc = cplbinfo_read_proc;
133 entry->data = NULL;
134
135 return 0;
136}
137
138static void __exit cplbinfo_exit(void)
139{
140 remove_proc_entry("cplbinfo", NULL);
141}
142
143module_init(cplbinfo_init);
144module_exit(cplbinfo_exit);
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
new file mode 100644
index 000000000000..e2e2b5079f5b
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -0,0 +1,91 @@
1/*
2 * Blackfin CPLB initialization
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23#include <linux/module.h>
24
25#include <asm/blackfin.h>
26#include <asm/cplb.h>
27#include <asm/cplbinit.h>
28
29struct cplb_entry icplb_tbl[MAX_CPLBS];
30struct cplb_entry dcplb_tbl[MAX_CPLBS];
31
32int first_switched_icplb, first_switched_dcplb;
33int first_mask_dcplb;
34
35void __init generate_cpl_tables(void)
36{
37 int i_d, i_i;
38 unsigned long addr;
39 unsigned long d_data, i_data;
40 unsigned long d_cache = 0, i_cache = 0;
41
42#ifdef CONFIG_BFIN_ICACHE
43 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
44#endif
45
46#ifdef CONFIG_BFIN_DCACHE
47 d_cache = CPLB_L1_CHBL;
48#ifdef CONFIG_BLKFIN_WT
49 d_cache |= CPLB_L1_AOW | CPLB_WT;
50#endif
51#endif
52 i_d = i_i = 0;
53
54 /* Set up the zero page. */
55 dcplb_tbl[i_d].addr = 0;
56 dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
57
58#if 0
59 icplb_tbl[i_i].addr = 0;
60 icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
61#endif
62
63 /* Cover kernel memory with 4M pages. */
64 addr = 0;
65 d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
66 i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
67
68 for (; addr < memory_start; addr += 4 * 1024 * 1024) {
69 dcplb_tbl[i_d].addr = addr;
70 dcplb_tbl[i_d++].data = d_data;
71 icplb_tbl[i_i].addr = addr;
72 icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
73 }
74
75 /* Cover L1 memory. One 4M area for code and data each is enough. */
76#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
77 dcplb_tbl[i_d].addr = L1_DATA_A_START;
78 dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
79#endif
80 icplb_tbl[i_i].addr = L1_CODE_START;
81 icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
82
83 first_mask_dcplb = i_d;
84 first_switched_dcplb = i_d + (1 << page_mask_order);
85 first_switched_icplb = i_i;
86
87 while (i_d < MAX_CPLBS)
88 dcplb_tbl[i_d++].data = 0;
89 while (i_i < MAX_CPLBS)
90 icplb_tbl[i_i++].data = 0;
91}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
new file mode 100644
index 000000000000..c426a22f9907
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -0,0 +1,338 @@
1/*
2 * Blackfin CPLB exception handling.
3 * Copyright 2004-2007 Analog Devices Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see the file COPYING, or write
17 * to the Free Software Foundation, Inc.,
18 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/module.h>
21#include <linux/mm.h>
22
23#include <asm/blackfin.h>
24#include <asm/cplbinit.h>
25#include <asm/mmu_context.h>
26
27#ifdef CONFIG_BFIN_ICACHE
28
29#define FAULT_RW (1 << 16)
30#define FAULT_USERSUPV (1 << 17)
31
32int page_mask_nelts;
33int page_mask_order;
34unsigned long *current_rwx_mask;
35
36int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
37int nr_cplb_flush;
38
39static inline void disable_dcplb(void)
40{
41 unsigned long ctrl;
42 SSYNC();
43 ctrl = bfin_read_DMEM_CONTROL();
44 ctrl &= ~ENDCPLB;
45 bfin_write_DMEM_CONTROL(ctrl);
46 SSYNC();
47}
48
49static inline void enable_dcplb(void)
50{
51 unsigned long ctrl;
52 SSYNC();
53 ctrl = bfin_read_DMEM_CONTROL();
54 ctrl |= ENDCPLB;
55 bfin_write_DMEM_CONTROL(ctrl);
56 SSYNC();
57}
58
59static inline void disable_icplb(void)
60{
61 unsigned long ctrl;
62 SSYNC();
63 ctrl = bfin_read_IMEM_CONTROL();
64 ctrl &= ~ENICPLB;
65 bfin_write_IMEM_CONTROL(ctrl);
66 SSYNC();
67}
68
69static inline void enable_icplb(void)
70{
71 unsigned long ctrl;
72 SSYNC();
73 ctrl = bfin_read_IMEM_CONTROL();
74 ctrl |= ENICPLB;
75 bfin_write_IMEM_CONTROL(ctrl);
76 SSYNC();
77}
78
79/*
80 * Given the contents of the status register, return the index of the
81 * CPLB that caused the fault.
82 */
83static inline int faulting_cplb_index(int status)
84{
85 int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
86 return 30 - signbits;
87}
88
89/*
90 * Given the contents of the status register and the DCPLB_DATA contents,
91 * return true if a write access should be permitted.
92 */
93static inline int write_permitted(int status, unsigned long data)
94{
95 if (status & FAULT_USERSUPV)
96 return !!(data & CPLB_SUPV_WR);
97 else
98 return !!(data & CPLB_USER_WR);
99}
100
101/* Counters to implement round-robin replacement. */
102static int icplb_rr_index, dcplb_rr_index;
103
104/*
105 * Find an ICPLB entry to be evicted and return its index.
106 */
107static int evict_one_icplb(void)
108{
109 int i;
110 for (i = first_switched_icplb; i < MAX_CPLBS; i++)
111 if ((icplb_tbl[i].data & CPLB_VALID) == 0)
112 return i;
113 i = first_switched_icplb + icplb_rr_index;
114 if (i >= MAX_CPLBS) {
115 i -= MAX_CPLBS - first_switched_icplb;
116 icplb_rr_index -= MAX_CPLBS - first_switched_icplb;
117 }
118 icplb_rr_index++;
119 return i;
120}
121
122static int evict_one_dcplb(void)
123{
124 int i;
125 for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
126 if ((dcplb_tbl[i].data & CPLB_VALID) == 0)
127 return i;
128 i = first_switched_dcplb + dcplb_rr_index;
129 if (i >= MAX_CPLBS) {
130 i -= MAX_CPLBS - first_switched_dcplb;
131 dcplb_rr_index -= MAX_CPLBS - first_switched_dcplb;
132 }
133 dcplb_rr_index++;
134 return i;
135}
136
137static noinline int dcplb_miss(void)
138{
139 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
140 int status = bfin_read_DCPLB_STATUS();
141 unsigned long *mask;
142 int idx;
143 unsigned long d_data;
144
145 nr_dcplb_miss++;
146 if (addr >= _ramend)
147 return CPLB_PROT_VIOL;
148
149 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
150#ifdef CONFIG_BFIN_DCACHE
151 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
152#ifdef CONFIG_BLKFIN_WT
153 d_data |= CPLB_L1_AOW | CPLB_WT;
154#endif
155#endif
156 mask = current_rwx_mask;
157 if (mask) {
158 int page = addr >> PAGE_SHIFT;
159 int offs = page >> 5;
160 int bit = 1 << (page & 31);
161
162 if (mask[offs] & bit)
163 d_data |= CPLB_USER_RD;
164
165 mask += page_mask_nelts;
166 if (mask[offs] & bit)
167 d_data |= CPLB_USER_WR;
168 }
169
170 idx = evict_one_dcplb();
171
172 addr &= PAGE_MASK;
173 dcplb_tbl[idx].addr = addr;
174 dcplb_tbl[idx].data = d_data;
175
176 disable_dcplb();
177 bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
178 bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
179 enable_dcplb();
180
181 return 0;
182}
183
184static noinline int icplb_miss(void)
185{
186 unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
187 int status = bfin_read_ICPLB_STATUS();
188 int idx;
189 unsigned long i_data;
190
191 nr_icplb_miss++;
192 if (status & FAULT_USERSUPV)
193 nr_icplb_supv_miss++;
194
195 if (addr >= _ramend)
196 return CPLB_PROT_VIOL;
197
198 /*
199 * First, try to find a CPLB that matches this address. If we
200 * find one, then the fact that we're in the miss handler means
201 * that the instruction crosses a page boundary.
202 */
203 for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
204 if (icplb_tbl[idx].data & CPLB_VALID) {
205 unsigned long this_addr = icplb_tbl[idx].addr;
206 if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
207 addr += PAGE_SIZE;
208 break;
209 }
210 }
211 }
212
213 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
214#ifdef CONFIG_BFIN_ICACHE
215 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
216#endif
217
218 /*
219 * Two cases to distinguish - a supervisor access must necessarily
220 * be for a module page; we grant it unconditionally (could do better
221 * here in the future). Otherwise, check the x bitmap of the current
222 * process.
223 */
224 if (!(status & FAULT_USERSUPV)) {
225 unsigned long *mask = current_rwx_mask;
226
227 if (mask) {
228 int page = addr >> PAGE_SHIFT;
229 int offs = page >> 5;
230 int bit = 1 << (page & 31);
231
232 mask += 2 * page_mask_nelts;
233 if (mask[offs] & bit)
234 i_data |= CPLB_USER_RD;
235 }
236 }
237
238 idx = evict_one_icplb();
239 addr &= PAGE_MASK;
240 icplb_tbl[idx].addr = addr;
241 icplb_tbl[idx].data = i_data;
242
243 disable_icplb();
244 bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
245 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
246 enable_icplb();
247
248 return 0;
249}
250
251static noinline int dcplb_protection_fault(void)
252{
253 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
254 int status = bfin_read_DCPLB_STATUS();
255
256 nr_dcplb_prot++;
257
258 if (status & FAULT_RW) {
259 int idx = faulting_cplb_index(status);
260 unsigned long data = dcplb_tbl[idx].data;
261 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
262 write_permitted(status, data)) {
263 data |= CPLB_DIRTY;
264 dcplb_tbl[idx].data = data;
265 bfin_write32(DCPLB_DATA0 + idx * 4, data);
266 return 0;
267 }
268 }
269 return CPLB_PROT_VIOL;
270}
271
272int cplb_hdr(int seqstat, struct pt_regs *regs)
273{
274 int cause = seqstat & 0x3f;
275 switch (cause) {
276 case 0x23:
277 return dcplb_protection_fault();
278 case 0x2C:
279 return icplb_miss();
280 case 0x26:
281 return dcplb_miss();
282 default:
283 return 1;
284 panic_cplb_error(seqstat, regs);
285 }
286}
287
288void flush_switched_cplbs(void)
289{
290 int i;
291
292 nr_cplb_flush++;
293
294 disable_icplb();
295 for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
296 icplb_tbl[i].data = 0;
297 bfin_write32(ICPLB_DATA0 + i * 4, 0);
298 }
299 enable_icplb();
300
301 disable_dcplb();
302 for (i = first_mask_dcplb; i < MAX_CPLBS; i++) {
303 dcplb_tbl[i].data = 0;
304 bfin_write32(DCPLB_DATA0 + i * 4, 0);
305 }
306 enable_dcplb();
307}
308
309void set_mask_dcplbs(unsigned long *masks)
310{
311 int i;
312 unsigned long addr = (unsigned long)masks;
313 unsigned long d_data;
314 current_rwx_mask = masks;
315
316 if (!masks)
317 return;
318
319 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
320#ifdef CONFIG_BFIN_DCACHE
321 d_data |= CPLB_L1_CHBL;
322#ifdef CONFIG_BLKFIN_WT
323 d_data |= CPLB_L1_AOW | CPLB_WT;
324#endif
325#endif
326
327 disable_dcplb();
328 for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
329 dcplb_tbl[i].addr = addr;
330 dcplb_tbl[i].data = d_data;
331 bfin_write32(DCPLB_DATA0 + i * 4, d_data);
332 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
333 addr += PAGE_SIZE;
334 }
335 enable_dcplb();
336}
337
338#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
new file mode 100644
index 000000000000..d36ea9b5382e
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/Makefile
@@ -0,0 +1,8 @@
1#
2# arch/blackfin/kernel/cplb-nompu/Makefile
3#
4
5obj-y := cplbinit.o cacheinit.o cplbhdlr.o cplbmgr.o
6
7obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
8
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
index 62cbba7364b0..8a18399f6072 100644
--- a/arch/blackfin/kernel/cacheinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
@@ -42,6 +42,7 @@ void bfin_icache_init(void)
42 ctrl = bfin_read_IMEM_CONTROL(); 42 ctrl = bfin_read_IMEM_CONTROL();
43 ctrl |= IMC | ENICPLB; 43 ctrl |= IMC | ENICPLB;
44 bfin_write_IMEM_CONTROL(ctrl); 44 bfin_write_IMEM_CONTROL(ctrl);
45 SSYNC();
45} 46}
46#endif 47#endif
47 48
@@ -63,5 +64,6 @@ void bfin_dcache_init(void)
63 ctrl = bfin_read_DMEM_CONTROL(); 64 ctrl = bfin_read_DMEM_CONTROL();
64 ctrl |= DMEM_CNTR; 65 ctrl |= DMEM_CNTR;
65 bfin_write_DMEM_CONTROL(ctrl); 66 bfin_write_DMEM_CONTROL(ctrl);
67 SSYNC();
66} 68}
67#endif 69#endif
diff --git a/arch/blackfin/mach-common/cplbhdlr.S b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
index 2788532de72b..2788532de72b 100644
--- a/arch/blackfin/mach-common/cplbhdlr.S
+++ b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
index a4f0b428a34d..a4f0b428a34d 100644
--- a/arch/blackfin/mach-common/cplbinfo.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 6320bc45fbba..6320bc45fbba 100644
--- a/arch/blackfin/kernel/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
index 6f909cbfac7b..f5cf3accef37 100644
--- a/arch/blackfin/mach-common/cplbmgr.S
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
@@ -75,6 +75,15 @@ ENTRY(_cplb_mgr)
75 * from the configuration table. 75 * from the configuration table.
76 */ 76 */
77 77
78 /* A multi-word instruction can cross a page boundary. This means the
79 * first part of the instruction can be in a valid page, but the
80 * second part is not, and hence generates the instruction miss.
81 * However, the fault address is for the start of the instruction,
82 * not the part that's in the bad page. Therefore, we have to check
83 * whether the fault address applies to a page that is already present
84 * in the table.
85 */
86
78 P4.L = LO(ICPLB_FAULT_ADDR); 87 P4.L = LO(ICPLB_FAULT_ADDR);
79 P4.H = HI(ICPLB_FAULT_ADDR); 88 P4.H = HI(ICPLB_FAULT_ADDR);
80 89
@@ -87,7 +96,7 @@ ENTRY(_cplb_mgr)
87 R4 = [P4]; /* Get faulting address*/ 96 R4 = [P4]; /* Get faulting address*/
88 R6 = 64; /* Advance past the fault address, which*/ 97 R6 = 64; /* Advance past the fault address, which*/
89 R6 = R6 + R4; /* we'll use if we find a match*/ 98 R6 = R6 + R4; /* we'll use if we find a match*/
90 R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/ 99 R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */
91 100
92 R5 = 0; 101 R5 = 0;
93.Lisearch: 102.Lisearch:
@@ -125,7 +134,9 @@ ENTRY(_cplb_mgr)
125 P4.L = LO(IMEM_CONTROL); 134 P4.L = LO(IMEM_CONTROL);
126 P4.H = HI(IMEM_CONTROL); 135 P4.H = HI(IMEM_CONTROL);
127 136
128 /* disable cplbs */ 137 /* Turn off CPLBs while we work, necessary according to HRM before
138 * modifying CPLB descriptors
139 */
129 R5 = [P4]; /* Control Register*/ 140 R5 = [P4]; /* Control Register*/
130 BITCLR(R5,ENICPLB_P); 141 BITCLR(R5,ENICPLB_P);
131 CLI R1; 142 CLI R1;
@@ -179,7 +190,14 @@ ENTRY(_cplb_mgr)
179 [P0 - 4] = R0; 190 [P0 - 4] = R0;
180 R0 = [P0 - 0x100]; 191 R0 = [P0 - 0x100];
181 [P0-0x104] = R0; 192 [P0-0x104] = R0;
182.Lie_move:P0+=4; 193.Lie_move:
194 P0+=4;
195
196 /* Clear ICPLB_DATA15, in case we don't find a replacement
197 * otherwise, we would have a duplicate entry, and will crash
198 */
199 R0 = 0;
200 [P0 - 4] = R0;
183 201
184 /* We've made space in the ICPLB table, so that ICPLB15 202 /* We've made space in the ICPLB table, so that ICPLB15
185 * is now free to be overwritten. Next, we have to determine 203 * is now free to be overwritten. Next, we have to determine
@@ -504,14 +522,23 @@ ENTRY(_cplb_mgr)
504 R0 = [P0++]; /* move data */ 522 R0 = [P0++]; /* move data */
505 [P0 - 8] = R0; 523 [P0 - 8] = R0;
506 R0 = [P0-0x104] /* move address */ 524 R0 = [P0-0x104] /* move address */
507.Lde_move: [P0-0x108] = R0; 525.Lde_move:
526 [P0-0x108] = R0;
527
528.Lde_moved:
529 NOP;
530
531 /* Clear DCPLB_DATA15, in case we don't find a replacement
532 * otherwise, we would have a duplicate entry, and will crash
533 */
534 R0 = 0;
535 [P0 - 0x4] = R0;
508 536
509 /* We've now made space in DCPLB15 for the new CPLB to be 537 /* We've now made space in DCPLB15 for the new CPLB to be
510 * installed. The next stage is to locate a CPLB in the 538 * installed. The next stage is to locate a CPLB in the
511 * config table that covers the faulting address. 539 * config table that covers the faulting address.
512 */ 540 */
513 541
514.Lde_moved:NOP;
515 R0 = I0; /* Our faulting address */ 542 R0 = I0; /* Our faulting address */
516 543
517 P2.L = _dpdt_table; 544 P2.L = _dpdt_table;
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
index 724f4a5a1d46..60f67f90fe35 100644
--- a/arch/blackfin/kernel/early_printk.c
+++ b/arch/blackfin/kernel/early_printk.c
@@ -187,7 +187,7 @@ asmlinkage void __init init_early_exception_vectors(void)
187 bfin_write_EVT15(early_trap); 187 bfin_write_EVT15(early_trap);
188 CSYNC(); 188 CSYNC();
189 189
190 /* Set all the return from interupt, exception, NMI to a known place 190 /* Set all the return from interrupt, exception, NMI to a known place
191 * so if we do a RETI, RETX or RETN by mistake - we go somewhere known 191 * so if we do a RETI, RETX or RETN by mistake - we go somewhere known
192 * Note - don't change RETS - we are in a subroutine, or 192 * Note - don't change RETS - we are in a subroutine, or
193 * RETE - since it might screw up if emulator is attached 193 * RETE - since it might screw up if emulator is attached
@@ -205,7 +205,7 @@ asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
205 if (likely(early_console == NULL)) 205 if (likely(early_console == NULL))
206 setup_early_printk(DEFAULT_EARLY_PORT); 206 setup_early_printk(DEFAULT_EARLY_PORT);
207 207
208 dump_bfin_mem((void *)fp->retx); 208 dump_bfin_mem(fp);
209 show_regs(fp); 209 show_regs(fp);
210 dump_bfin_trace_buffer(); 210 dump_bfin_trace_buffer();
211 211
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 5bf15125f0d6..023dc80af187 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -39,9 +39,6 @@
39#include <asm/blackfin.h> 39#include <asm/blackfin.h>
40#include <asm/fixed_code.h> 40#include <asm/fixed_code.h>
41 41
42#define LED_ON 0
43#define LED_OFF 1
44
45asmlinkage void ret_from_fork(void); 42asmlinkage void ret_from_fork(void);
46 43
47/* Points to the SDRAM backup memory for the stack that is currently in 44/* Points to the SDRAM backup memory for the stack that is currently in
@@ -70,32 +67,6 @@ void (*pm_power_off)(void) = NULL;
70EXPORT_SYMBOL(pm_power_off); 67EXPORT_SYMBOL(pm_power_off);
71 68
72/* 69/*
73 * We are using a different LED from the one used to indicate timer interrupt.
74 */
75#if defined(CONFIG_BFIN_IDLE_LED)
76static inline void leds_switch(int flag)
77{
78 unsigned short tmp = 0;
79
80 tmp = bfin_read_CONFIG_BFIN_IDLE_LED_PORT();
81 SSYNC();
82
83 if (flag == LED_ON)
84 tmp &= ~CONFIG_BFIN_IDLE_LED_PIN; /* light on */
85 else
86 tmp |= CONFIG_BFIN_IDLE_LED_PIN; /* light off */
87
88 bfin_write_CONFIG_BFIN_IDLE_LED_PORT(tmp);
89 SSYNC();
90
91}
92#else
93static inline void leds_switch(int flag)
94{
95}
96#endif
97
98/*
99 * The idle loop on BFIN 70 * The idle loop on BFIN
100 */ 71 */
101#ifdef CONFIG_IDLE_L1 72#ifdef CONFIG_IDLE_L1
@@ -106,12 +77,10 @@ void cpu_idle(void)__attribute__((l1_text));
106void default_idle(void) 77void default_idle(void)
107{ 78{
108 while (!need_resched()) { 79 while (!need_resched()) {
109 leds_switch(LED_OFF);
110 local_irq_disable(); 80 local_irq_disable();
111 if (likely(!need_resched())) 81 if (likely(!need_resched()))
112 idle_with_irq_disabled(); 82 idle_with_irq_disabled();
113 local_irq_enable(); 83 local_irq_enable();
114 leds_switch(LED_ON);
115 } 84 }
116} 85}
117 86
@@ -327,6 +296,7 @@ void finish_atomic_sections (struct pt_regs *regs)
327} 296}
328 297
329#if defined(CONFIG_ACCESS_CHECK) 298#if defined(CONFIG_ACCESS_CHECK)
299/* Return 1 if access to memory range is OK, 0 otherwise */
330int _access_ok(unsigned long addr, unsigned long size) 300int _access_ok(unsigned long addr, unsigned long size)
331{ 301{
332 if (size == 0) 302 if (size == 0)
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index ae28aac6fec1..483f93dfc1b5 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -19,6 +19,11 @@
19#define SYSCR_VAL 0x10 19#define SYSCR_VAL 0x10
20#endif 20#endif
21 21
22/*
23 * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15)
24 */
25#define SWRST_DELAY (5 * 15)
26
22/* A system soft reset makes external memory unusable 27/* A system soft reset makes external memory unusable
23 * so force this function into L1. 28 * so force this function into L1.
24 */ 29 */
@@ -34,7 +39,13 @@ void bfin_reset(void)
34 while (1) { 39 while (1) {
35 /* initiate system soft reset with magic 0x7 */ 40 /* initiate system soft reset with magic 0x7 */
36 bfin_write_SWRST(0x7); 41 bfin_write_SWRST(0x7);
37 asm("ssync;"); 42
43 /* Wait for System reset to actually reset, needs to be 5 SCLKs, */
44 /* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */
45
46 asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n"
47 : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0");
48
38 /* clear system soft reset */ 49 /* clear system soft reset */
39 bfin_write_SWRST(0); 50 bfin_write_SWRST(0);
40 asm("ssync;"); 51 asm("ssync;");
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index d2822010b7ce..462cae893757 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -238,7 +238,13 @@ void __init setup_arch(char **cmdline_p)
238 memory_end = _ramend - DMA_UNCACHED_REGION; 238 memory_end = _ramend - DMA_UNCACHED_REGION;
239 239
240 _ramstart = (unsigned long)__bss_stop; 240 _ramstart = (unsigned long)__bss_stop;
241 _rambase = (unsigned long)_stext;
242#ifdef CONFIG_MPU
243 /* Round up to multiple of 4MB. */
244 memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
245#else
241 memory_start = PAGE_ALIGN(_ramstart); 246 memory_start = PAGE_ALIGN(_ramstart);
247#endif
242 248
243#if defined(CONFIG_MTD_UCLINUX) 249#if defined(CONFIG_MTD_UCLINUX)
244 /* generic memory mapped MTD driver */ 250 /* generic memory mapped MTD driver */
@@ -307,6 +313,11 @@ void __init setup_arch(char **cmdline_p)
307 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20); 313 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
308#endif /* ANOMALY_05000263 */ 314#endif /* ANOMALY_05000263 */
309 315
316#ifdef CONFIG_MPU
317 page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
318 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
319#endif
320
310#if !defined(CONFIG_MTD_UCLINUX) 321#if !defined(CONFIG_MTD_UCLINUX)
311 memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ 322 memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
312#endif 323#endif
@@ -315,8 +326,6 @@ void __init setup_arch(char **cmdline_p)
315 init_mm.end_data = (unsigned long)_edata; 326 init_mm.end_data = (unsigned long)_edata;
316 init_mm.brk = (unsigned long)0; 327 init_mm.brk = (unsigned long)0;
317 328
318 init_leds();
319
320 _bfin_swrst = bfin_read_SWRST(); 329 _bfin_swrst = bfin_read_SWRST();
321 330
322 if (_bfin_swrst & RESET_DOUBLE) 331 if (_bfin_swrst & RESET_DOUBLE)
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index beef057bd1dc..5bd64e341df3 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -42,75 +42,6 @@
42static void time_sched_init(irqreturn_t(*timer_routine) 42static void time_sched_init(irqreturn_t(*timer_routine)
43 (int, void *)); 43 (int, void *));
44static unsigned long gettimeoffset(void); 44static unsigned long gettimeoffset(void);
45static inline void do_leds(void);
46
47#if (defined(CONFIG_BFIN_ALIVE_LED) || defined(CONFIG_BFIN_IDLE_LED))
48void __init init_leds(void)
49{
50 unsigned int tmp = 0;
51
52#if defined(CONFIG_BFIN_ALIVE_LED)
53 /* config pins as output. */
54 tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_DPORT();
55 SSYNC();
56 bfin_write_CONFIG_BFIN_ALIVE_LED_DPORT(tmp | CONFIG_BFIN_ALIVE_LED_PIN);
57 SSYNC();
58
59 /* First set led be off */
60 tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_PORT();
61 SSYNC();
62 bfin_write_CONFIG_BFIN_ALIVE_LED_PORT(tmp | CONFIG_BFIN_ALIVE_LED_PIN); /* light off */
63 SSYNC();
64#endif
65
66#if defined(CONFIG_BFIN_IDLE_LED)
67 /* config pins as output. */
68 tmp = bfin_read_CONFIG_BFIN_IDLE_LED_DPORT();
69 SSYNC();
70 bfin_write_CONFIG_BFIN_IDLE_LED_DPORT(tmp | CONFIG_BFIN_IDLE_LED_PIN);
71 SSYNC();
72
73 /* First set led be off */
74 tmp = bfin_read_CONFIG_BFIN_IDLE_LED_PORT();
75 SSYNC();
76 bfin_write_CONFIG_BFIN_IDLE_LED_PORT(tmp | CONFIG_BFIN_IDLE_LED_PIN); /* light off */
77 SSYNC();
78#endif
79}
80#else
81void __init init_leds(void)
82{
83}
84#endif
85
86#if defined(CONFIG_BFIN_ALIVE_LED)
87static inline void do_leds(void)
88{
89 static unsigned int count = 50;
90 static int flag;
91 unsigned short tmp = 0;
92
93 if (--count == 0) {
94 count = 50;
95 flag = ~flag;
96 }
97 tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_PORT();
98 SSYNC();
99
100 if (flag)
101 tmp &= ~CONFIG_BFIN_ALIVE_LED_PIN; /* light on */
102 else
103 tmp |= CONFIG_BFIN_ALIVE_LED_PIN; /* light off */
104
105 bfin_write_CONFIG_BFIN_ALIVE_LED_PORT(tmp);
106 SSYNC();
107
108}
109#else
110static inline void do_leds(void)
111{
112}
113#endif
114 45
115static struct irqaction bfin_timer_irq = { 46static struct irqaction bfin_timer_irq = {
116 .name = "BFIN Timer Tick", 47 .name = "BFIN Timer Tick",
@@ -205,7 +136,6 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
205 write_seqlock(&xtime_lock); 136 write_seqlock(&xtime_lock);
206 137
207 do_timer(1); 138 do_timer(1);
208 do_leds();
209 139
210#ifndef CONFIG_SMP 140#ifndef CONFIG_SMP
211 update_process_times(user_mode(get_irq_regs())); 141 update_process_times(user_mode(get_irq_regs()));
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 21a55ef19cbd..66b5f3e3ae2a 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -36,8 +36,10 @@
36#include <asm/cacheflush.h> 36#include <asm/cacheflush.h>
37#include <asm/blackfin.h> 37#include <asm/blackfin.h>
38#include <asm/irq_handler.h> 38#include <asm/irq_handler.h>
39#include <linux/irq.h>
39#include <asm/trace.h> 40#include <asm/trace.h>
40#include <asm/fixed_code.h> 41#include <asm/fixed_code.h>
42#include <asm/dma.h>
41 43
42#ifdef CONFIG_KGDB 44#ifdef CONFIG_KGDB
43# include <linux/debugger.h> 45# include <linux/debugger.h>
@@ -170,7 +172,7 @@ asmlinkage void double_fault_c(struct pt_regs *fp)
170 oops_in_progress = 1; 172 oops_in_progress = 1;
171 printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n"); 173 printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n");
172 dump_bfin_process(fp); 174 dump_bfin_process(fp);
173 dump_bfin_mem((void *)fp->retx); 175 dump_bfin_mem(fp);
174 show_regs(fp); 176 show_regs(fp);
175 panic("Double Fault - unrecoverable event\n"); 177 panic("Double Fault - unrecoverable event\n");
176 178
@@ -195,9 +197,13 @@ asmlinkage void trap_c(struct pt_regs *fp)
195 * we will kernel panic, so the system reboots. 197 * we will kernel panic, so the system reboots.
196 * If KGDB is enabled, don't set this for kernel breakpoints 198 * If KGDB is enabled, don't set this for kernel breakpoints
197 */ 199 */
198 if ((bfin_read_IPEND() & 0xFFC0) 200
201 /* TODO: check to see if we are in some sort of deferred HWERR
202 * that we should be able to recover from, not kernel panic
203 */
204 if ((bfin_read_IPEND() & 0xFFC0) && (trapnr != VEC_STEP)
199#ifdef CONFIG_KGDB 205#ifdef CONFIG_KGDB
200 && trapnr != VEC_EXCPT02 206 && (trapnr != VEC_EXCPT02)
201#endif 207#endif
202 ){ 208 ){
203 console_verbose(); 209 console_verbose();
@@ -433,6 +439,36 @@ asmlinkage void trap_c(struct pt_regs *fp)
433 /* 0x3D - Reserved, Caught by default */ 439 /* 0x3D - Reserved, Caught by default */
434 /* 0x3E - Reserved, Caught by default */ 440 /* 0x3E - Reserved, Caught by default */
435 /* 0x3F - Reserved, Caught by default */ 441 /* 0x3F - Reserved, Caught by default */
442 case VEC_HWERR:
443 info.si_code = BUS_ADRALN;
444 sig = SIGBUS;
445 switch (fp->seqstat & SEQSTAT_HWERRCAUSE) {
446 /* System MMR Error */
447 case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
448 info.si_code = BUS_ADRALN;
449 sig = SIGBUS;
450 printk(KERN_NOTICE HWC_x2(KERN_NOTICE));
451 break;
452 /* External Memory Addressing Error */
453 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
454 info.si_code = BUS_ADRERR;
455 sig = SIGBUS;
456 printk(KERN_NOTICE HWC_x3(KERN_NOTICE));
457 break;
458 /* Performance Monitor Overflow */
459 case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
460 printk(KERN_NOTICE HWC_x12(KERN_NOTICE));
461 break;
462 /* RAISE 5 instruction */
463 case (SEQSTAT_HWERRCAUSE_RAISE_5):
464 printk(KERN_NOTICE HWC_x18(KERN_NOTICE));
465 break;
466 default: /* Reserved */
467 printk(KERN_NOTICE HWC_default(KERN_NOTICE));
468 break;
469 }
470 CHK_DEBUGGER_TRAP();
471 break;
436 default: 472 default:
437 info.si_code = TRAP_ILLTRAP; 473 info.si_code = TRAP_ILLTRAP;
438 sig = SIGTRAP; 474 sig = SIGTRAP;
@@ -447,7 +483,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
447 if (sig != SIGTRAP) { 483 if (sig != SIGTRAP) {
448 unsigned long stack; 484 unsigned long stack;
449 dump_bfin_process(fp); 485 dump_bfin_process(fp);
450 dump_bfin_mem((void *)fp->retx); 486 dump_bfin_mem(fp);
451 show_regs(fp); 487 show_regs(fp);
452 488
453 /* Print out the trace buffer if it makes sense */ 489 /* Print out the trace buffer if it makes sense */
@@ -461,6 +497,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
461 dump_bfin_trace_buffer(); 497 dump_bfin_trace_buffer();
462 show_stack(current, &stack); 498 show_stack(current, &stack);
463 if (oops_in_progress) { 499 if (oops_in_progress) {
500 print_modules();
464#ifndef CONFIG_ACCESS_CHECK 501#ifndef CONFIG_ACCESS_CHECK
465 printk(KERN_EMERG "Please turn on " 502 printk(KERN_EMERG "Please turn on "
466 "CONFIG_ACCESS_CHECK\n"); 503 "CONFIG_ACCESS_CHECK\n");
@@ -474,13 +511,6 @@ asmlinkage void trap_c(struct pt_regs *fp)
474 info.si_addr = (void *)fp->pc; 511 info.si_addr = (void *)fp->pc;
475 force_sig_info(sig, &info, current); 512 force_sig_info(sig, &info, current);
476 513
477 /* Ensure that bad return addresses don't end up in an infinite
478 * loop, due to speculative loads/reads. This needs to be done after
479 * the signal has been sent.
480 */
481 if (trapnr == VEC_CPLB_I_M && sig != SIGTRAP)
482 fp->pc = SAFE_USER_INSTRUCTION;
483
484 trace_buffer_restore(j); 514 trace_buffer_restore(j);
485 return; 515 return;
486} 516}
@@ -616,8 +646,10 @@ void dump_bfin_process(struct pt_regs *fp)
616 if (oops_in_progress) 646 if (oops_in_progress)
617 printk(KERN_EMERG "Kernel OOPS in progress\n"); 647 printk(KERN_EMERG "Kernel OOPS in progress\n");
618 648
619 if (context & 0x0020) 649 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
620 printk(KERN_NOTICE "Deferred excecption or HW Error context\n"); 650 printk(KERN_NOTICE "HW Error context\n");
651 else if (context & 0x0020)
652 printk(KERN_NOTICE "Defered Exception context\n");
621 else if (context & 0x3FC0) 653 else if (context & 0x3FC0)
622 printk(KERN_NOTICE "Interrupt context\n"); 654 printk(KERN_NOTICE "Interrupt context\n");
623 else if (context & 0x4000) 655 else if (context & 0x4000)
@@ -645,59 +677,124 @@ void dump_bfin_process(struct pt_regs *fp)
645 "No Valid process in current context\n"); 677 "No Valid process in current context\n");
646} 678}
647 679
648void dump_bfin_mem(void *retaddr) 680void dump_bfin_mem(struct pt_regs *fp)
649{ 681{
682 unsigned short *addr, *erraddr, val = 0, err = 0;
683 char sti = 0, buf[6];
650 684
651 if (retaddr >= (void *)FIXED_CODE_START && retaddr < (void *)physical_mem_end 685 if (unlikely((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR))
652#if L1_CODE_LENGTH != 0 686 erraddr = (void *)fp->pc;
653 /* FIXME: Copy the code out of L1 Instruction SRAM through dma 687 else
654 memcpy. */ 688 erraddr = (void *)fp->retx;
655 && !(retaddr >= (void *)L1_CODE_START 689
656 && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH)) 690 printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
657#endif 691
658 ) { 692 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
659 int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32; 693 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
660 unsigned short x = 0; 694 addr++) {
661 printk(KERN_NOTICE "return address: [0x%p]; contents of:", retaddr); 695 if (!((unsigned long)addr & 0xF))
662 for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) { 696 printk("\n" KERN_NOTICE "0x%p: ", addr);
663 if (!(i & 0xF)) 697
664 printk("\n" KERN_NOTICE "0x%08x: ", i); 698 if (get_user(val, addr)) {
665 699 if (addr >= (unsigned short *)L1_CODE_START &&
666 if (get_user(x, (unsigned short *)i)) 700 addr < (unsigned short *)(L1_CODE_START + L1_CODE_LENGTH)) {
667 break; 701 dma_memcpy(&val, addr, sizeof(val));
702 sprintf(buf, "%04x", val);
703 } else if (addr >= (unsigned short *)FIXED_CODE_START &&
704 addr <= (unsigned short *)memory_start) {
705 val = bfin_read16(addr);
706 sprintf(buf, "%04x", val);
707 } else {
708 val = 0;
709 sprintf(buf, "????");
710 }
711 } else
712 sprintf(buf, "%04x", val);
713
714 if (addr == erraddr) {
715 printk("[%s]", buf);
716 err = val;
717 } else
718 printk(" %s ", buf);
719
720 /* Do any previous instructions turn on interrupts? */
721 if (addr <= erraddr && /* in the past */
722 ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
723 val == 0x017b)) /* [SP++] = RETI */
724 sti = 1;
725 }
726
727 printk("\n");
728
729 /* Hardware error interrupts can be deferred */
730 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
731 oops_in_progress)){
732 printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
668#ifndef CONFIG_DEBUG_HWERR 733#ifndef CONFIG_DEBUG_HWERR
669 /* If one of the last few instructions was a STI 734 printk(KERN_NOTICE "The remaining message may be meaningless\n"
670 * it is likely that the error occured awhile ago 735 KERN_NOTICE "You should enable CONFIG_DEBUG_HWERR to get a"
671 * and we just noticed. This only happens in kernel 736 " better idea where it came from\n");
672 * context, which should mean an oops is happening 737#else
673 */ 738 /* If we are handling only one peripheral interrupt
674 if (oops_in_progress && x >= 0x0040 && x <= 0x0047 && i <= 0) 739 * and current mm and pid are valid, and the last error
675 panic("\n\nWARNING : You should reconfigure" 740 * was in that user space process's text area
676 " the kernel to turn on\n" 741 * print it out - because that is where the problem exists
677 " 'Hardware error interrupt" 742 */
678 " debugging'\n" 743 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
679 " The rest of this error" 744 (current->pid && current->mm)) {
680 " is meanless\n"); 745 /* And the last RETI points to the current userspace context */
681#endif 746 if ((fp + 1)->pc >= current->mm->start_code &&
682 if (i == (unsigned int)retaddr) 747 (fp + 1)->pc <= current->mm->end_code) {
683 printk("[%04x]", x); 748 printk(KERN_NOTICE "It might be better to look around here : \n");
684 else 749 printk(KERN_NOTICE "-------------------------------------------\n");
685 printk(" %04x ", x); 750 show_regs(fp + 1);
751 printk(KERN_NOTICE "-------------------------------------------\n");
752 }
686 } 753 }
687 printk("\n"); 754#endif
688 } else 755 }
689 printk("\n" KERN_NOTICE
690 "Cannot look at the [PC] <%p> for it is"
691 " in unreadable memory - sorry\n", retaddr);
692} 756}
693 757
694void show_regs(struct pt_regs *fp) 758void show_regs(struct pt_regs *fp)
695{ 759{
696 char buf [150]; 760 char buf [150];
761 struct irqaction *action;
762 unsigned int i;
763 unsigned long flags;
697 764
698 printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\n"); 765 printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
699 printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", 766 printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
700 (long)fp->seqstat, fp->ipend, fp->syscfg); 767 (long)fp->seqstat, fp->ipend, fp->syscfg);
768 printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
769 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
770 printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
771 fp->seqstat & SEQSTAT_EXCAUSE);
772 for (i = 6; i <= 15 ; i++) {
773 if (fp->ipend & (1 << i)) {
774 decode_address(buf, bfin_read32(EVT0 + 4*i));
775 printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
776 }
777 }
778
779 /* if no interrupts are going off, don't print this out */
780 if (fp->ipend & ~0x3F) {
781 for (i = 0; i < (NR_IRQS - 1); i++) {
782 spin_lock_irqsave(&irq_desc[i].lock, flags);
783 action = irq_desc[i].action;
784 if (!action)
785 goto unlock;
786
787 decode_address(buf, (unsigned int)action->handler);
788 printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
789 for (action = action->next; action; action = action->next) {
790 decode_address(buf, (unsigned int)action->handler);
791 printk(", %s", buf);
792 }
793 printk("\n");
794unlock:
795 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
796 }
797 }
701 798
702 decode_address(buf, fp->rete); 799 decode_address(buf, fp->rete);
703 printk(KERN_NOTICE " RETE: %s\n", buf); 800 printk(KERN_NOTICE " RETE: %s\n", buf);
@@ -708,9 +805,10 @@ void show_regs(struct pt_regs *fp)
708 decode_address(buf, fp->rets); 805 decode_address(buf, fp->rets);
709 printk(KERN_NOTICE " RETS: %s\n", buf); 806 printk(KERN_NOTICE " RETS: %s\n", buf);
710 decode_address(buf, fp->pc); 807 decode_address(buf, fp->pc);
711 printk(KERN_NOTICE " PC: %s\n", buf); 808 printk(KERN_NOTICE " PC : %s\n", buf);
712 809
713 if ((long)fp->seqstat & SEQSTAT_EXCAUSE) { 810 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
811 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
714 decode_address(buf, bfin_read_DCPLB_FAULT_ADDR()); 812 decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
715 printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); 813 printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
716 decode_address(buf, bfin_read_ICPLB_FAULT_ADDR()); 814 decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
@@ -824,7 +922,7 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
824 printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR()); 922 printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR());
825 printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR()); 923 printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR());
826 dump_bfin_process(fp); 924 dump_bfin_process(fp);
827 dump_bfin_mem((void *)fp->retx); 925 dump_bfin_mem(fp);
828 show_regs(fp); 926 show_regs(fp);
829 dump_stack(); 927 dump_stack();
830 panic("Unrecoverable event\n"); 928 panic("Unrecoverable event\n");
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
index 2e6336492b4b..e654a18a0754 100644
--- a/arch/blackfin/lib/memcpy.S
+++ b/arch/blackfin/lib/memcpy.S
@@ -70,8 +70,8 @@ ENTRY(_memcpy)
70 /* Check for aligned data.*/ 70 /* Check for aligned data.*/
71 71
72 R3 = R1 | R0; 72 R3 = R1 | R0;
73 R0 = 0x3; 73 R1 = 0x3;
74 R3 = R3 & R0; 74 R3 = R3 & R1;
75 CC = R3; /* low bits set on either address? */ 75 CC = R3; /* low bits set on either address? */
76 IF CC JUMP .Lnot_aligned; 76 IF CC JUMP .Lnot_aligned;
77 77
@@ -83,7 +83,6 @@ ENTRY(_memcpy)
83 /* less than eight bytes... */ 83 /* less than eight bytes... */
84 P2 = R2; 84 P2 = R2;
85 LSETUP(.Lthree_start, .Lthree_end) LC0=P2; 85 LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
86 R0 = R1; /* setup src address for return */
87.Lthree_start: 86.Lthree_start:
88 R3 = B[P1++] (X); 87 R3 = B[P1++] (X);
89.Lthree_end: 88.Lthree_end:
@@ -95,7 +94,6 @@ ENTRY(_memcpy)
95 /* There's at least eight bytes to copy. */ 94 /* There's at least eight bytes to copy. */
96 P2 += -1; /* because we unroll one iteration */ 95 P2 += -1; /* because we unroll one iteration */
97 LSETUP(.Lword_loops, .Lword_loope) LC0=P2; 96 LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
98 R0 = R1;
99 I1 = P1; 97 I1 = P1;
100 R3 = [I1++]; 98 R3 = [I1++];
101#if ANOMALY_05000202 99#if ANOMALY_05000202
@@ -120,7 +118,6 @@ ENTRY(_memcpy)
120.Lnot_aligned: 118.Lnot_aligned:
121 /* From here, we're copying byte-by-byte. */ 119 /* From here, we're copying byte-by-byte. */
122 LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2; 120 LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
123 R0 = R1; /* Save src address for return */
124.Lbyte_start: 121.Lbyte_start:
125 R1 = B[P1++] (X); 122 R1 = B[P1++] (X);
126.Lbyte_end: 123.Lbyte_end:
@@ -135,7 +132,6 @@ ENTRY(_memcpy)
135 * Don't bother to work out alignment for 132 * Don't bother to work out alignment for
136 * the reverse case. 133 * the reverse case.
137 */ 134 */
138 R0 = R1; /* save src for later. */
139 P0 = P0 + P2; 135 P0 = P0 + P2;
140 P0 += -1; 136 P0 += -1;
141 P1 = P1 + P2; 137 P1 = P1 + P2;
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 5c736837d4bf..3cde4beeb214 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -43,7 +43,7 @@ endchoice
43 43
44choice 44choice
45 prompt "UART1" 45 prompt "UART1"
46 default BF527_UART1_PORTG 46 default BF527_UART1_PORTF
47 help 47 help
48 Select PORT used for UART1. See Hardware Reference Manual 48 Select PORT used for UART1. See Hardware Reference Manual
49 49
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 003e2ac654d8..f8c411a24af7 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -8,7 +8,7 @@
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA) 10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc. 11 * Copyright 2004-2008 Analog Devices Inc.
12 * 12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * 14 *
@@ -41,6 +41,7 @@
41#include <linux/irq.h> 41#include <linux/irq.h>
42#include <linux/interrupt.h> 42#include <linux/interrupt.h>
43#include <linux/usb/sl811.h> 43#include <linux/usb/sl811.h>
44#include <linux/usb/musb.h>
44#include <asm/cplb.h> 45#include <asm/cplb.h>
45#include <asm/dma.h> 46#include <asm/dma.h>
46#include <asm/bfin5xx_spi.h> 47#include <asm/bfin5xx_spi.h>
@@ -105,6 +106,69 @@ void __exit bfin_isp1761_exit(void)
105arch_initcall(bfin_isp1761_init); 106arch_initcall(bfin_isp1761_init);
106#endif 107#endif
107 108
109#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
110static struct resource musb_resources[] = {
111 [0] = {
112 .start = 0xffc03800,
113 .end = 0xffc03cff,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = { /* general IRQ */
117 .start = IRQ_USB_INT0,
118 .end = IRQ_USB_INT0,
119 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
120 },
121 [2] = { /* DMA IRQ */
122 .start = IRQ_USB_DMA,
123 .end = IRQ_USB_DMA,
124 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
125 },
126};
127
128static struct musb_hdrc_platform_data musb_plat = {
129#if defined(CONFIG_USB_MUSB_OTG)
130 .mode = MUSB_OTG,
131#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
132 .mode = MUSB_HOST,
133#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
134 .mode = MUSB_PERIPHERAL,
135#endif
136 .multipoint = 0,
137};
138
139static u64 musb_dmamask = ~(u32)0;
140
141static struct platform_device musb_device = {
142 .name = "musb_hdrc",
143 .id = 0,
144 .dev = {
145 .dma_mask = &musb_dmamask,
146 .coherent_dma_mask = 0xffffffff,
147 .platform_data = &musb_plat,
148 },
149 .num_resources = ARRAY_SIZE(musb_resources),
150 .resource = musb_resources,
151};
152#endif
153
154#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
155
156static struct resource bf52x_t350mcqb_resources[] = {
157 {
158 .start = IRQ_PPI_ERROR,
159 .end = IRQ_PPI_ERROR,
160 .flags = IORESOURCE_IRQ,
161 },
162};
163
164static struct platform_device bf52x_t350mcqb_device = {
165 .name = "bfin-t350mcqb",
166 .id = -1,
167 .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
168 .resource = bf52x_t350mcqb_resources,
169};
170#endif
171
108#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 172#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
109static struct mtd_partition partition_info[] = { 173static struct mtd_partition partition_info[] = {
110 { 174 {
@@ -253,12 +317,7 @@ static struct resource sl811_hcd_resources[] = {
253void sl811_port_power(struct device *dev, int is_on) 317void sl811_port_power(struct device *dev, int is_on)
254{ 318{
255 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); 319 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
256 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); 320 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
257
258 if (is_on)
259 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
260 else
261 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
262} 321}
263#endif 322#endif
264 323
@@ -718,6 +777,28 @@ static struct platform_device bfin_pata_device = {
718}; 777};
719#endif 778#endif
720 779
780#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
781#include <linux/input.h>
782#include <linux/gpio_keys.h>
783
784static struct gpio_keys_button bfin_gpio_keys_table[] = {
785 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
786 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
787};
788
789static struct gpio_keys_platform_data bfin_gpio_keys_data = {
790 .buttons = bfin_gpio_keys_table,
791 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
792};
793
794static struct platform_device bfin_device_gpiokeys = {
795 .name = "gpio-keys",
796 .dev = {
797 .platform_data = &bfin_gpio_keys_data,
798 },
799};
800#endif
801
721static struct platform_device *stamp_devices[] __initdata = { 802static struct platform_device *stamp_devices[] __initdata = {
722#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 803#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
723 &bf5xx_nand_device, 804 &bf5xx_nand_device,
@@ -739,6 +820,10 @@ static struct platform_device *stamp_devices[] __initdata = {
739 &isp1362_hcd_device, 820 &isp1362_hcd_device,
740#endif 821#endif
741 822
823#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
824 &musb_device,
825#endif
826
742#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 827#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
743 &smc91x_device, 828 &smc91x_device,
744#endif 829#endif
@@ -763,6 +848,10 @@ static struct platform_device *stamp_devices[] __initdata = {
763 &bfin_fb_device, 848 &bfin_fb_device,
764#endif 849#endif
765 850
851#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
852 &bf52x_t350mcqb_device,
853#endif
854
766#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) 855#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
767 &bfin_fb_adv7393_device, 856 &bfin_fb_adv7393_device,
768#endif 857#endif
@@ -783,6 +872,10 @@ static struct platform_device *stamp_devices[] __initdata = {
783#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 872#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
784 &bfin_pata_device, 873 &bfin_pata_device,
785#endif 874#endif
875
876#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
877 &bfin_device_gpiokeys,
878#endif
786}; 879};
787 880
788static int __init stamp_init(void) 881static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 6bcf4047f89c..a72c7a620fa1 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -40,6 +40,7 @@
40#endif 40#endif
41#include <linux/pata_platform.h> 41#include <linux/pata_platform.h>
42#include <linux/irq.h> 42#include <linux/irq.h>
43
43#include <asm/dma.h> 44#include <asm/dma.h>
44#include <asm/bfin5xx_spi.h> 45#include <asm/bfin5xx_spi.h>
45#include <asm/reboot.h> 46#include <asm/reboot.h>
@@ -303,7 +304,77 @@ static struct platform_device bfin_uart_device = {
303}; 304};
304#endif 305#endif
305 306
306static struct platform_device *stamp_devices[] __initdata = { 307#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
308
309#include <linux/serial_8250.h>
310#include <linux/serial.h>
311
312/*
313 * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
314 * running at half system clock, both with interrupt output or-ed to PF8. Change to
315 * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
316 */
317
318static struct plat_serial8250_port serial8250_platform_data [] = {
319 {
320 .membase = 0x20200000,
321 .mapbase = 0x20200000,
322 .irq = IRQ_PF8,
323 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
324 .iotype = UPIO_MEM,
325 .regshift = 1,
326 .uartclk = 66666667,
327 }, {
328 .membase = 0x20200010,
329 .mapbase = 0x20200010,
330 .irq = IRQ_PF8,
331 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
332 .iotype = UPIO_MEM,
333 .regshift = 1,
334 .uartclk = 66666667,
335 }, {
336 }
337};
338
339static struct platform_device serial8250_device = {
340 .id = PLAT8250_DEV_PLATFORM,
341 .name = "serial8250",
342 .dev = {
343 .platform_data = serial8250_platform_data,
344 },
345};
346
347#endif
348
349#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
350
351/*
352 * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
353 * interrupt output wired to PF9. Change to suit different FPGA configuration
354 */
355
356static struct resource opencores_kbd_resources[] = {
357 [0] = {
358 .start = 0x20200030,
359 .end = 0x20300030 + 2,
360 .flags = IORESOURCE_MEM,
361 },
362 [1] = {
363 .start = IRQ_PF9,
364 .end = IRQ_PF9,
365 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
366 },
367};
368
369static struct platform_device opencores_kbd_device = {
370 .id = -1,
371 .name = "opencores-kbd",
372 .resource = opencores_kbd_resources,
373 .num_resources = ARRAY_SIZE(opencores_kbd_resources),
374};
375#endif
376
377static struct platform_device *h8606_devices[] __initdata = {
307#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 378#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
308 &rtc_device, 379 &rtc_device,
309#endif 380#endif
@@ -327,13 +398,21 @@ static struct platform_device *stamp_devices[] __initdata = {
327#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 398#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
328 &bfin_uart_device, 399 &bfin_uart_device,
329#endif 400#endif
401
402#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
403 &serial8250_device,
404#endif
405
406#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
407 &opencores_kbd_device,
408#endif
330}; 409};
331 410
332static int __init H8606_init(void) 411static int __init H8606_init(void)
333{ 412{
334 printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); 413 printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
335 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); 414 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
336 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); 415 platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
337#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 416#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
338 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 417 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
339#endif 418#endif
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index be852034a68b..c37dd45c8803 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -256,6 +256,50 @@ static struct platform_device bfin_pata_device = {
256}; 256};
257#endif 257#endif
258 258
259#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
260#include <linux/input.h>
261#include <linux/gpio_keys.h>
262
263static struct gpio_keys_button bfin_gpio_keys_table[] = {
264 {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"},
265 {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"},
266 {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"},
267 {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"},
268};
269
270static struct gpio_keys_platform_data bfin_gpio_keys_data = {
271 .buttons = bfin_gpio_keys_table,
272 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
273};
274
275static struct platform_device bfin_device_gpiokeys = {
276 .name = "gpio-keys",
277 .dev = {
278 .platform_data = &bfin_gpio_keys_data,
279 },
280};
281#endif
282
283#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
284#include <linux/i2c-gpio.h>
285
286static struct i2c_gpio_platform_data i2c_gpio_data = {
287 .sda_pin = 1,
288 .scl_pin = 0,
289 .sda_is_open_drain = 0,
290 .scl_is_open_drain = 0,
291 .udelay = 40,
292};
293
294static struct platform_device i2c_gpio_device = {
295 .name = "i2c-gpio",
296 .id = 0,
297 .dev = {
298 .platform_data = &i2c_gpio_data,
299 },
300};
301#endif
302
259static struct platform_device *ezkit_devices[] __initdata = { 303static struct platform_device *ezkit_devices[] __initdata = {
260#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 304#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
261 &smc91x_device, 305 &smc91x_device,
@@ -280,6 +324,14 @@ static struct platform_device *ezkit_devices[] __initdata = {
280#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 324#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
281 &bfin_pata_device, 325 &bfin_pata_device,
282#endif 326#endif
327
328#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
329 &bfin_device_gpiokeys,
330#endif
331
332#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
333 &i2c_gpio_device,
334#endif
283}; 335};
284 336
285static int __init ezkit_init(void) 337static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 8fde8d832850..ac52b040b336 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -32,6 +32,7 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 37#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -108,6 +109,50 @@ static struct platform_device net2272_bfin_device = {
108}; 109};
109#endif 110#endif
110 111
112static struct mtd_partition stamp_partitions[] = {
113 {
114 .name = "Bootloader",
115 .size = 0x20000,
116 .offset = 0,
117 }, {
118 .name = "Kernel",
119 .size = 0xE0000,
120 .offset = MTDPART_OFS_APPEND,
121 }, {
122 .name = "RootFS",
123 .size = MTDPART_SIZ_FULL,
124 .offset = MTDPART_OFS_APPEND,
125 }
126};
127
128static struct physmap_flash_data stamp_flash_data = {
129 .width = 2,
130 .parts = stamp_partitions,
131 .nr_parts = ARRAY_SIZE(stamp_partitions),
132};
133
134static struct resource stamp_flash_resource[] = {
135 {
136 .name = "cfi_probe",
137 .start = 0x20000000,
138 .end = 0x203fffff,
139 .flags = IORESOURCE_MEM,
140 }, {
141 .start = CONFIG_ENET_FLASH_PIN,
142 .flags = IORESOURCE_IRQ,
143 }
144};
145
146static struct platform_device stamp_flash_device = {
147 .name = "BF5xx-Flash",
148 .id = 0,
149 .dev = {
150 .platform_data = &stamp_flash_data,
151 },
152 .num_resources = ARRAY_SIZE(stamp_flash_resource),
153 .resource = stamp_flash_resource,
154};
155
111#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 156#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
112/* all SPI peripherals info goes here */ 157/* all SPI peripherals info goes here */
113 158
@@ -373,6 +418,49 @@ static struct platform_device bfin_pata_device = {
373}; 418};
374#endif 419#endif
375 420
421#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
422#include <linux/input.h>
423#include <linux/gpio_keys.h>
424
425static struct gpio_keys_button bfin_gpio_keys_table[] = {
426 {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
427 {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
428 {BTN_2, GPIO_PF8, 1, "gpio-keys: BTN2"},
429};
430
431static struct gpio_keys_platform_data bfin_gpio_keys_data = {
432 .buttons = bfin_gpio_keys_table,
433 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
434};
435
436static struct platform_device bfin_device_gpiokeys = {
437 .name = "gpio-keys",
438 .dev = {
439 .platform_data = &bfin_gpio_keys_data,
440 },
441};
442#endif
443
444#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
445#include <linux/i2c-gpio.h>
446
447static struct i2c_gpio_platform_data i2c_gpio_data = {
448 .sda_pin = 2,
449 .scl_pin = 3,
450 .sda_is_open_drain = 0,
451 .scl_is_open_drain = 0,
452 .udelay = 40,
453};
454
455static struct platform_device i2c_gpio_device = {
456 .name = "i2c-gpio",
457 .id = 0,
458 .dev = {
459 .platform_data = &i2c_gpio_data,
460 },
461};
462#endif
463
376static struct platform_device *stamp_devices[] __initdata = { 464static struct platform_device *stamp_devices[] __initdata = {
377#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 465#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
378 &rtc_device, 466 &rtc_device,
@@ -406,6 +494,15 @@ static struct platform_device *stamp_devices[] __initdata = {
406#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 494#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
407 &bfin_pata_device, 495 &bfin_pata_device,
408#endif 496#endif
497
498#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
499 &bfin_device_gpiokeys,
500#endif
501
502#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
503 &i2c_gpio_device,
504#endif
505 &stamp_flash_device,
409}; 506};
410 507
411static int __init stamp_init(void) 508static int __init stamp_init(void)
@@ -418,12 +515,10 @@ static int __init stamp_init(void)
418 return ret; 515 return ret;
419 516
420#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 517#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
421# if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
422 /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */ 518 /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
423 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1 << CONFIG_ENET_FLASH_PIN)); 519 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1 << CONFIG_ENET_FLASH_PIN));
424 bfin_write_FIO_FLAG_S(1 << CONFIG_ENET_FLASH_PIN); 520 bfin_write_FIO_FLAG_S(1 << CONFIG_ENET_FLASH_PIN);
425 SSYNC(); 521 SSYNC();
426# endif
427#endif 522#endif
428 523
429#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 524#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@@ -440,10 +535,8 @@ arch_initcall(stamp_init);
440 535
441void native_machine_restart(char *cmd) 536void native_machine_restart(char *cmd)
442{ 537{
443#if defined(CONFIG_BFIN_SHARED_FLASH_ENET) 538#define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
444# define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
445 bfin_write_FIO_INEN(~BIT_TO_SET); 539 bfin_write_FIO_INEN(~BIT_TO_SET);
446 bfin_write_FIO_DIR(BIT_TO_SET); 540 bfin_write_FIO_DIR(BIT_TO_SET);
447 bfin_write_FIO_FLAG_C(BIT_TO_SET); 541 bfin_write_FIO_FLAG_C(BIT_TO_SET);
448#endif
449} 542}
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 96a15196e416..7e789dbef036 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -21,6 +21,12 @@ config PNAV10
21 help 21 help
22 PNAV board support. 22 PNAV board support.
23 23
24config CAMSIG_MINOTAUR
25 bool "Cambridge Signal Processing LTD Minotaur"
26 depends on (BF537)
27 help
28 Board supply package for CSP Minotaur
29
24config GENERIC_BF537_BOARD 30config GENERIC_BF537_BOARD
25 bool "Generic" 31 bool "Generic"
26 help 32 help
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 94a85174283a..87e450f29e37 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN537_STAMP) += stamp.o led.o 6obj-$(CONFIG_BFIN537_STAMP) += stamp.o led.o
7obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o 7obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
8obj-$(CONFIG_PNAV10) += pnav10.o 8obj-$(CONFIG_PNAV10) += pnav10.o
9obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index c0fb06dbc42e..8703b67d5ec6 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -29,6 +29,7 @@
29 */ 29 */
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/etherdevice.h>
32#include <linux/platform_device.h> 33#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 34#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 35#include <linux/mtd/partitions.h>
@@ -216,6 +217,12 @@ static struct platform_device rtc_device = {
216}; 217};
217#endif 218#endif
218 219
220#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
221static struct platform_device hitachi_fb_device = {
222 .name = "hitachi-tx09",
223};
224#endif
225
219#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 226#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
220static struct resource smc91x_resources[] = { 227static struct resource smc91x_resources[] = {
221 { 228 {
@@ -374,6 +381,10 @@ static struct platform_device bfin_pata_device = {
374#endif 381#endif
375 382
376static struct platform_device *cm_bf537_devices[] __initdata = { 383static struct platform_device *cm_bf537_devices[] __initdata = {
384#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
385 &hitachi_fb_device,
386#endif
387
377#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 388#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
378 &rtc_device, 389 &rtc_device,
379#endif 390#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index 09f4bfbd2350..3e52f3f5bd58 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -8,7 +8,7 @@
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA) 10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc. 11 * Copyright 2004-2008 Analog Devices Inc.
12 * 12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * 14 *
@@ -29,6 +29,7 @@
29 */ 29 */
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/etherdevice.h>
32#include <linux/platform_device.h> 33#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 34#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 35#include <linux/mtd/partitions.h>
@@ -204,12 +205,8 @@ static struct resource sl811_hcd_resources[] = {
204void sl811_port_power(struct device *dev, int is_on) 205void sl811_port_power(struct device *dev, int is_on)
205{ 206{
206 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); 207 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
207 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); 208 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
208 209
209 if (is_on)
210 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
211 else
212 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
213} 210}
214#endif 211#endif
215 212
@@ -733,9 +730,11 @@ void native_machine_restart(char *cmd)
733 bfin_gpio_reset_spi0_ssel1(); 730 bfin_gpio_reset_spi0_ssel1();
734} 731}
735 732
733#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
736void bfin_get_ether_addr(char *addr) 734void bfin_get_ether_addr(char *addr)
737{ 735{
738 random_ether_addr(addr); 736 random_ether_addr(addr);
739 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); 737 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
740} 738}
741EXPORT_SYMBOL(bfin_get_ether_addr); 739EXPORT_SYMBOL(bfin_get_ether_addr);
740#endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
new file mode 100644
index 000000000000..b8bbba85af53
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -0,0 +1,317 @@
1/*
2 */
3
4#include <linux/device.h>
5#include <linux/platform_device.h>
6#include <linux/mtd/mtd.h>
7#include <linux/mtd/partitions.h>
8#include <linux/spi/spi.h>
9#include <linux/spi/flash.h>
10#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
11#include <linux/usb_isp1362.h>
12#endif
13#include <linux/pata_platform.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/usb_sl811.h>
17#include <asm/dma.h>
18#include <asm/bfin5xx_spi.h>
19#include <asm/reboot.h>
20#include <linux/spi/ad7877.h>
21
22/*
23 * Name the Board for the /proc/cpuinfo
24 */
25char *bfin_board_name = "CamSig Minotaur BF537";
26
27#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
28static struct resource bfin_pcmcia_cf_resources[] = {
29 {
30 .start = 0x20310000, /* IO PORT */
31 .end = 0x20312000,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = 0x20311000, /* Attribute Memory */
35 .end = 0x20311FFF,
36 .flags = IORESOURCE_MEM,
37 }, {
38 .start = IRQ_PF4,
39 .end = IRQ_PF4,
40 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
41 }, {
42 .start = IRQ_PF6, /* Card Detect PF6 */
43 .end = IRQ_PF6,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48static struct platform_device bfin_pcmcia_cf_device = {
49 .name = "bfin_cf_pcmcia",
50 .id = -1,
51 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
52 .resource = bfin_pcmcia_cf_resources,
53};
54#endif
55
56#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
57static struct platform_device rtc_device = {
58 .name = "rtc-bfin",
59 .id = -1,
60};
61#endif
62
63#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
64static struct platform_device bfin_mac_device = {
65 .name = "bfin_mac",
66};
67#endif
68
69#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
70static struct resource net2272_bfin_resources[] = {
71 {
72 .start = 0x20300000,
73 .end = 0x20300000 + 0x100,
74 .flags = IORESOURCE_MEM,
75 }, {
76 .start = IRQ_PF7,
77 .end = IRQ_PF7,
78 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
79 },
80};
81
82static struct platform_device net2272_bfin_device = {
83 .name = "net2272",
84 .id = -1,
85 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
86 .resource = net2272_bfin_resources,
87};
88#endif
89
90#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
91/* all SPI peripherals info goes here */
92
93#if defined(CONFIG_MTD_M25P80) \
94 || defined(CONFIG_MTD_M25P80_MODULE)
95
96/* Partition sizes */
97#define FLASH_SIZE 0x00400000
98#define PSIZE_UBOOT 0x00030000
99#define PSIZE_INITRAMFS 0x00240000
100
101static struct mtd_partition bfin_spi_flash_partitions[] = {
102 {
103 .name = "uboot",
104 .size = PSIZE_UBOOT,
105 .offset = 0x000000,
106 .mask_flags = MTD_CAP_ROM
107 }, {
108 .name = "initramfs",
109 .size = PSIZE_INITRAMFS,
110 .offset = PSIZE_UBOOT
111 }, {
112 .name = "opt",
113 .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
114 .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
115 }
116};
117
118static struct flash_platform_data bfin_spi_flash_data = {
119 .name = "m25p80",
120 .parts = bfin_spi_flash_partitions,
121 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
122 .type = "m25p64",
123};
124
125/* SPI flash chip (m25p64) */
126static struct bfin5xx_spi_chip spi_flash_chip_info = {
127 .enable_dma = 0, /* use dma transfer with this chip*/
128 .bits_per_word = 8,
129};
130#endif
131
132#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
133static struct bfin5xx_spi_chip spi_mmc_chip_info = {
134 .enable_dma = 1,
135 .bits_per_word = 8,
136};
137#endif
138
139static struct spi_board_info bfin_spi_board_info[] __initdata = {
140#if defined(CONFIG_MTD_M25P80) \
141 || defined(CONFIG_MTD_M25P80_MODULE)
142 {
143 /* the modalias must be the same as spi device driver name */
144 .modalias = "m25p80", /* Name of spi_driver for this device */
145 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
146 .bus_num = 0, /* Framework bus number */
147 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
148 .platform_data = &bfin_spi_flash_data,
149 .controller_data = &spi_flash_chip_info,
150 .mode = SPI_MODE_3,
151 },
152#endif
153
154#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
155 {
156 .modalias = "spi_mmc_dummy",
157 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
158 .bus_num = 0,
159 .chip_select = 0,
160 .platform_data = NULL,
161 .controller_data = &spi_mmc_chip_info,
162 .mode = SPI_MODE_3,
163 },
164 {
165 .modalias = "spi_mmc",
166 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173#endif
174};
175
176/* SPI controller data */
177static struct bfin5xx_spi_master bfin_spi0_info = {
178 .num_chipselect = 8,
179 .enable_dma = 1, /* master has the ability to do dma transfer */
180};
181
182/* SPI (0) */
183static struct resource bfin_spi0_resource[] = {
184 [0] = {
185 .start = SPI0_REGBASE,
186 .end = SPI0_REGBASE + 0xFF,
187 .flags = IORESOURCE_MEM,
188 },
189 [1] = {
190 .start = CH_SPI,
191 .end = CH_SPI,
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196static struct platform_device bfin_spi0_device = {
197 .name = "bfin-spi",
198 .id = 0, /* Bus number */
199 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
200 .resource = bfin_spi0_resource,
201 .dev = {
202 .platform_data = &bfin_spi0_info, /* Passed to driver */
203 },
204};
205#endif /* spi master and devices */
206
207#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
208static struct resource bfin_uart_resources[] = {
209 {
210 .start = 0xFFC00400,
211 .end = 0xFFC004FF,
212 .flags = IORESOURCE_MEM,
213 }, {
214 .start = 0xFFC02000,
215 .end = 0xFFC020FF,
216 .flags = IORESOURCE_MEM,
217 },
218};
219
220static struct platform_device bfin_uart_device = {
221 .name = "bfin-uart",
222 .id = 1,
223 .num_resources = ARRAY_SIZE(bfin_uart_resources),
224 .resource = bfin_uart_resources,
225};
226#endif
227
228#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
229static struct resource bfin_twi0_resource[] = {
230 [0] = {
231 .start = TWI0_REGBASE,
232 .end = TWI0_REGBASE + 0xFF,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = IRQ_TWI,
237 .end = IRQ_TWI,
238 .flags = IORESOURCE_IRQ,
239 },
240};
241
242static struct platform_device i2c_bfin_twi_device = {
243 .name = "i2c-bfin-twi",
244 .id = 0,
245 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
246 .resource = bfin_twi0_resource,
247};
248#endif
249
250#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
251static struct platform_device bfin_sport0_uart_device = {
252 .name = "bfin-sport-uart",
253 .id = 0,
254};
255
256static struct platform_device bfin_sport1_uart_device = {
257 .name = "bfin-sport-uart",
258 .id = 1,
259};
260#endif
261
262static struct platform_device *minotaur_devices[] __initdata = {
263#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
264 &bfin_pcmcia_cf_device,
265#endif
266
267#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
268 &rtc_device,
269#endif
270
271#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
272 &bfin_mac_device,
273#endif
274
275#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
276 &net2272_bfin_device,
277#endif
278
279#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
280 &bfin_spi0_device,
281#endif
282
283#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
284 &bfin_uart_device,
285#endif
286
287#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
288 &i2c_bfin_twi_device,
289#endif
290
291#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
292 &bfin_sport0_uart_device,
293 &bfin_sport1_uart_device,
294#endif
295
296};
297
298static int __init minotaur_init(void)
299{
300 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
301 platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
302#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
303 spi_register_board_info(bfin_spi_board_info,
304 ARRAY_SIZE(bfin_spi_board_info));
305#endif
306
307 return 0;
308}
309
310arch_initcall(minotaur_init);
311
312void native_machine_restart(char *cmd)
313{
314 /* workaround reboot hang when booting from SPI */
315 if ((bfin_read_SYSCR() & 0x7) == 0x3)
316 bfin_gpio_reset_spi0_ssel1();
317}
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index fd5f4a6f08e4..509a8a236fd0 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -8,7 +8,7 @@
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA) 10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc. 11 * Copyright 2004-2008 Analog Devices Inc.
12 * 12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * 14 *
@@ -29,6 +29,7 @@
29 */ 29 */
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/etherdevice.h>
32#include <linux/platform_device.h> 33#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 34#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 35#include <linux/mtd/partitions.h>
@@ -133,12 +134,8 @@ static struct resource sl811_hcd_resources[] = {
133void sl811_port_power(struct device *dev, int is_on) 134void sl811_port_power(struct device *dev, int is_on)
134{ 135{
135 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); 136 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
136 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); 137 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
137 138
138 if (is_on)
139 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
140 else
141 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
142} 139}
143#endif 140#endif
144 141
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 07b0dc273d2f..772541548b76 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -32,6 +32,7 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 37#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -103,6 +104,30 @@ void __exit bfin_isp1761_exit(void)
103arch_initcall(bfin_isp1761_init); 104arch_initcall(bfin_isp1761_init);
104#endif 105#endif
105 106
107#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
108#include <linux/input.h>
109#include <linux/gpio_keys.h>
110
111static struct gpio_keys_button bfin_gpio_keys_table[] = {
112 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
113 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
114 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
115 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
116};
117
118static struct gpio_keys_platform_data bfin_gpio_keys_data = {
119 .buttons = bfin_gpio_keys_table,
120 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
121};
122
123static struct platform_device bfin_device_gpiokeys = {
124 .name = "gpio-keys",
125 .dev = {
126 .platform_data = &bfin_gpio_keys_data,
127 },
128};
129#endif
130
106#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 131#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
107static struct resource bfin_pcmcia_cf_resources[] = { 132static struct resource bfin_pcmcia_cf_resources[] = {
108 { 133 {
@@ -226,12 +251,7 @@ static struct resource sl811_hcd_resources[] = {
226void sl811_port_power(struct device *dev, int is_on) 251void sl811_port_power(struct device *dev, int is_on)
227{ 252{
228 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); 253 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
229 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); 254 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
230
231 if (is_on)
232 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
233 else
234 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
235} 255}
236#endif 256#endif
237 257
@@ -320,6 +340,49 @@ static struct platform_device net2272_bfin_device = {
320}; 340};
321#endif 341#endif
322 342
343static struct mtd_partition stamp_partitions[] = {
344 {
345 .name = "Bootloader",
346 .size = 0x20000,
347 .offset = 0,
348 }, {
349 .name = "Kernel",
350 .size = 0xE0000,
351 .offset = MTDPART_OFS_APPEND,
352 }, {
353 .name = "RootFS",
354 .size = 0x400000 - 0x20000 - 0xE0000 - 0x10000,
355 .offset = MTDPART_OFS_APPEND,
356 }, {
357 .name = "MAC Address",
358 .size = MTDPART_SIZ_FULL,
359 .offset = 0x3F0000,
360 .mask_flags = MTD_WRITEABLE,
361 }
362};
363
364static struct physmap_flash_data stamp_flash_data = {
365 .width = 2,
366 .parts = stamp_partitions,
367 .nr_parts = ARRAY_SIZE(stamp_partitions),
368};
369
370static struct resource stamp_flash_resource = {
371 .start = 0x20000000,
372 .end = 0x203fffff,
373 .flags = IORESOURCE_MEM,
374};
375
376static struct platform_device stamp_flash_device = {
377 .name = "physmap-flash",
378 .id = 0,
379 .dev = {
380 .platform_data = &stamp_flash_data,
381 },
382 .num_resources = 1,
383 .resource = &stamp_flash_resource,
384};
385
323#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 386#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
324/* all SPI peripherals info goes here */ 387/* all SPI peripherals info goes here */
325 388
@@ -738,6 +801,11 @@ static struct platform_device *stamp_devices[] __initdata = {
738#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 801#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
739 &bfin_pata_device, 802 &bfin_pata_device,
740#endif 803#endif
804
805#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
806 &bfin_device_gpiokeys,
807#endif
808 &stamp_flash_device,
741}; 809};
742 810
743static int __init stamp_init(void) 811static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index d8bd3b49f150..1bfcd8f646ab 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -7,7 +7,7 @@ menu "BF548 Specific Configuration"
7config DEB_DMA_URGENT 7config DEB_DMA_URGENT
8 bool "DMA has priority over core for ext. accesses" 8 bool "DMA has priority over core for ext. accesses"
9 depends on BF54x 9 depends on BF54x
10 default n 10 default y
11 help 11 help
12 Treat any DEB1, DEB2 and DEB3 request as Urgent 12 Treat any DEB1, DEB2 and DEB3 request as Urgent
13 13
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index d37d6653c4bc..14860f04d1bd 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -32,6 +32,7 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 37#include <linux/spi/flash.h>
37#include <linux/irq.h> 38#include <linux/irq.h>
@@ -206,23 +207,6 @@ static struct platform_device smsc911x_device = {
206}; 207};
207#endif 208#endif
208 209
209#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE)
210static struct resource bf54x_hcd_resources[] = {
211 {
212 .start = 0xFFC03C00,
213 .end = 0xFFC040FF,
214 .flags = IORESOURCE_MEM,
215 },
216};
217
218static struct platform_device bf54x_hcd = {
219 .name = "bf54x-hcd",
220 .id = 0,
221 .num_resources = ARRAY_SIZE(bf54x_hcd_resources),
222 .resource = bf54x_hcd_resources,
223};
224#endif
225
226#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 210#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
227static struct resource musb_resources[] = { 211static struct resource musb_resources[] = {
228 [0] = { 212 [0] = {
@@ -243,14 +227,14 @@ static struct resource musb_resources[] = {
243}; 227};
244 228
245static struct musb_hdrc_platform_data musb_plat = { 229static struct musb_hdrc_platform_data musb_plat = {
246#ifdef CONFIG_USB_MUSB_OTG 230#if defined(CONFIG_USB_MUSB_OTG)
247 .mode = MUSB_OTG, 231 .mode = MUSB_OTG,
248#elif CONFIG_USB_MUSB_HDRC_HCD 232#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
249 .mode = MUSB_HOST, 233 .mode = MUSB_HOST,
250#elif CONFIG_USB_GADGET_MUSB_HDRC 234#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
251 .mode = MUSB_PERIPHERAL, 235 .mode = MUSB_PERIPHERAL,
252#endif 236#endif
253 .multipoint = 1, 237 .multipoint = 0,
254}; 238};
255 239
256static u64 musb_dmamask = ~(u32)0; 240static u64 musb_dmamask = ~(u32)0;
@@ -344,6 +328,44 @@ static struct platform_device bf54x_sdh_device = {
344}; 328};
345#endif 329#endif
346 330
331static struct mtd_partition ezkit_partitions[] = {
332 {
333 .name = "Bootloader",
334 .size = 0x20000,
335 .offset = 0,
336 }, {
337 .name = "Kernel",
338 .size = 0xE0000,
339 .offset = MTDPART_OFS_APPEND,
340 }, {
341 .name = "RootFS",
342 .size = MTDPART_SIZ_FULL,
343 .offset = MTDPART_OFS_APPEND,
344 }
345};
346
347static struct physmap_flash_data ezkit_flash_data = {
348 .width = 2,
349 .parts = ezkit_partitions,
350 .nr_parts = ARRAY_SIZE(ezkit_partitions),
351};
352
353static struct resource ezkit_flash_resource = {
354 .start = 0x20000000,
355 .end = 0x20ffffff,
356 .flags = IORESOURCE_MEM,
357};
358
359static struct platform_device ezkit_flash_device = {
360 .name = "physmap-flash",
361 .id = 0,
362 .dev = {
363 .platform_data = &ezkit_flash_data,
364 },
365 .num_resources = 1,
366 .resource = &ezkit_flash_resource,
367};
368
347#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 369#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
348/* all SPI peripherals info goes here */ 370/* all SPI peripherals info goes here */
349#if defined(CONFIG_MTD_M25P80) \ 371#if defined(CONFIG_MTD_M25P80) \
@@ -531,6 +553,29 @@ static struct platform_device i2c_bfin_twi1_device = {
531#endif 553#endif
532#endif 554#endif
533 555
556#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
557#include <linux/gpio_keys.h>
558
559static struct gpio_keys_button bfin_gpio_keys_table[] = {
560 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
561 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
562 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
563 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
564};
565
566static struct gpio_keys_platform_data bfin_gpio_keys_data = {
567 .buttons = bfin_gpio_keys_table,
568 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
569};
570
571static struct platform_device bfin_device_gpiokeys = {
572 .name = "gpio-keys",
573 .dev = {
574 .platform_data = &bfin_gpio_keys_data,
575 },
576};
577#endif
578
534static struct platform_device *ezkit_devices[] __initdata = { 579static struct platform_device *ezkit_devices[] __initdata = {
535#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 580#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
536 &rtc_device, 581 &rtc_device,
@@ -548,10 +593,6 @@ static struct platform_device *ezkit_devices[] __initdata = {
548 &smsc911x_device, 593 &smsc911x_device,
549#endif 594#endif
550 595
551#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE)
552 &bf54x_hcd,
553#endif
554
555#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 596#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
556 &musb_device, 597 &musb_device,
557#endif 598#endif
@@ -583,6 +624,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
583 &i2c_bfin_twi1_device, 624 &i2c_bfin_twi1_device,
584#endif 625#endif
585#endif 626#endif
627
628#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
629 &bfin_device_gpiokeys,
630#endif
631 &ezkit_flash_device,
586}; 632};
587 633
588static int __init stamp_init(void) 634static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 74b34c7f3629..74fe258421a5 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -298,8 +298,8 @@ ENTRY(_start_dma_code)
298 w[p0] = r0.l; 298 w[p0] = r0.l;
299 ssync; 299 ssync;
300 300
301 p0.h = hi(SIC_IWR); 301 p0.h = hi(SIC_IWR0);
302 p0.l = lo(SIC_IWR); 302 p0.l = lo(SIC_IWR0);
303 r0.l = 0x1; 303 r0.l = 0x1;
304 r0.h = 0x0; 304 r0.h = 0x0;
305 [p0] = r0; 305 [p0] = r0;
@@ -324,12 +324,25 @@ ENTRY(_start_dma_code)
324 w[p0] = r0.l; 324 w[p0] = r0.l;
325 ssync; 325 ssync;
326 326
327#if defined(CONFIG_BF54x)
328 P2.H = hi(EBIU_RSTCTL);
329 P2.L = lo(EBIU_RSTCTL);
330 R0 = [P2];
331 BITSET (R0, 3);
332#else
327 P2.H = hi(EBIU_SDGCTL); 333 P2.H = hi(EBIU_SDGCTL);
328 P2.L = lo(EBIU_SDGCTL); 334 P2.L = lo(EBIU_SDGCTL);
329 R0 = [P2]; 335 R0 = [P2];
330 BITSET (R0, 24); 336 BITSET (R0, 24);
337#endif
331 [P2] = R0; 338 [P2] = R0;
332 SSYNC; 339 SSYNC;
340#if defined(CONFIG_BF54x)
341.LSRR_MODE:
342 R0 = [P2];
343 CC = BITTST(R0, 4);
344 if !CC JUMP .LSRR_MODE;
345#endif
333 346
334 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ 347 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
335 r0 = r0 << 9; /* Shift it over, */ 348 r0 = r0 << 9; /* Shift it over, */
@@ -361,6 +374,39 @@ ENTRY(_start_dma_code)
361 w[p0] = r0.l; 374 w[p0] = r0.l;
362 ssync; 375 ssync;
363 376
377#if defined(CONFIG_BF54x)
378 P2.H = hi(EBIU_RSTCTL);
379 P2.L = lo(EBIU_RSTCTL);
380 R0 = [P2];
381 CC = BITTST(R0, 0);
382 if CC jump .Lskipddrrst;
383 BITSET (R0, 0);
384.Lskipddrrst:
385 BITCLR (R0, 3);
386 [P2] = R0;
387 SSYNC;
388
389 p0.l = lo(EBIU_DDRCTL0);
390 p0.h = hi(EBIU_DDRCTL0);
391 r0.l = lo(mem_DDRCTL0);
392 r0.h = hi(mem_DDRCTL0);
393 [p0] = r0;
394 ssync;
395
396 p0.l = lo(EBIU_DDRCTL1);
397 p0.h = hi(EBIU_DDRCTL1);
398 r0.l = lo(mem_DDRCTL1);
399 r0.h = hi(mem_DDRCTL1);
400 [p0] = r0;
401 ssync;
402
403 p0.l = lo(EBIU_DDRCTL2);
404 p0.h = hi(EBIU_DDRCTL2);
405 r0.l = lo(mem_DDRCTL2);
406 r0.h = hi(mem_DDRCTL2);
407 [p0] = r0;
408 ssync;
409#else
364 p0.l = lo(EBIU_SDRRC); 410 p0.l = lo(EBIU_SDRRC);
365 p0.h = hi(EBIU_SDRRC); 411 p0.h = hi(EBIU_SDRRC);
366 r0 = mem_SDRRC; 412 r0 = mem_SDRRC;
@@ -394,9 +440,10 @@ ENTRY(_start_dma_code)
394 R1 = R1 | R0; 440 R1 = R1 | R0;
395 [P2] = R1; 441 [P2] = R1;
396 SSYNC; 442 SSYNC;
443#endif
397 444
398 p0.h = hi(SIC_IWR); 445 p0.h = hi(SIC_IWR0);
399 p0.l = lo(SIC_IWR); 446 p0.l = lo(SIC_IWR0);
400 r0.l = lo(IWR_ENABLE_ALL); 447 r0.l = lo(IWR_ENABLE_ALL);
401 r0.h = hi(IWR_ENABLE_ALL); 448 r0.h = hi(IWR_ENABLE_ALL);
402 [p0] = r0; 449 [p0] = r0;
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
index cb0ebac53c79..2665653cee37 100644
--- a/arch/blackfin/mach-bf548/ints-priority.c
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -4,7 +4,7 @@
4 * Author: Michael Hennerich 4 * Author: Michael Hennerich
5 * 5 *
6 * Created: 6 * Created:
7 * Description: Set up the interupt priorities 7 * Description: Set up the interrupt priorities
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc. 10 * Copyright 2004-2006 Analog Devices Inc.
@@ -58,7 +58,7 @@ void program_IAR(void)
58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) | 58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) | 59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) | 60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS)); 61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
62 62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) | 63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) | 64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index c19cd29b948a..3a79a9061bdc 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -198,6 +198,13 @@ static struct platform_device bfin_spi0_device = {
198#endif /* spi master and devices */ 198#endif /* spi master and devices */
199 199
200 200
201#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
202static struct platform_device hitachi_fb_device = {
203 .name = "hitachi-tx09",
204};
205#endif
206
207
201#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 208#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
202 209
203static struct resource smc91x_resources[] = { 210static struct resource smc91x_resources[] = {
@@ -315,6 +322,10 @@ static struct platform_device bfin_pata_device = {
315 322
316static struct platform_device *cm_bf561_devices[] __initdata = { 323static struct platform_device *cm_bf561_devices[] __initdata = {
317 324
325#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
326 &hitachi_fb_device,
327#endif
328
318#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 329#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
319 &bfin_uart_device, 330 &bfin_uart_device,
320#endif 331#endif
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 4ff8f6e7a11f..7601c3be1b5c 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -29,6 +29,9 @@
29 29
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/mtd/mtd.h>
33#include <linux/mtd/partitions.h>
34#include <linux/mtd/physmap.h>
32#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
33#include <linux/irq.h> 36#include <linux/irq.h>
34#include <linux/interrupt.h> 37#include <linux/interrupt.h>
@@ -155,6 +158,44 @@ static struct platform_device bfin_uart_device = {
155}; 158};
156#endif 159#endif
157 160
161static struct mtd_partition ezkit_partitions[] = {
162 {
163 .name = "Bootloader",
164 .size = 0x20000,
165 .offset = 0,
166 }, {
167 .name = "Kernel",
168 .size = 0xE0000,
169 .offset = MTDPART_OFS_APPEND,
170 }, {
171 .name = "RootFS",
172 .size = MTDPART_SIZ_FULL,
173 .offset = MTDPART_OFS_APPEND,
174 }
175};
176
177static struct physmap_flash_data ezkit_flash_data = {
178 .width = 2,
179 .parts = ezkit_partitions,
180 .nr_parts = ARRAY_SIZE(ezkit_partitions),
181};
182
183static struct resource ezkit_flash_resource = {
184 .start = 0x20000000,
185 .end = 0x207fffff,
186 .flags = IORESOURCE_MEM,
187};
188
189static struct platform_device ezkit_flash_device = {
190 .name = "physmap-flash",
191 .id = 0,
192 .dev = {
193 .platform_data = &ezkit_flash_data,
194 },
195 .num_resources = 1,
196 .resource = &ezkit_flash_resource,
197};
198
158#ifdef CONFIG_SPI_BFIN 199#ifdef CONFIG_SPI_BFIN
159#if defined(CONFIG_SND_BLACKFIN_AD1836) \ 200#if defined(CONFIG_SND_BLACKFIN_AD1836) \
160 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) 201 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
@@ -246,6 +287,50 @@ static struct platform_device bfin_pata_device = {
246}; 287};
247#endif 288#endif
248 289
290#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
291#include <linux/input.h>
292#include <linux/gpio_keys.h>
293
294static struct gpio_keys_button bfin_gpio_keys_table[] = {
295 {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
296 {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
297 {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
298 {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
299};
300
301static struct gpio_keys_platform_data bfin_gpio_keys_data = {
302 .buttons = bfin_gpio_keys_table,
303 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
304};
305
306static struct platform_device bfin_device_gpiokeys = {
307 .name = "gpio-keys",
308 .dev = {
309 .platform_data = &bfin_gpio_keys_data,
310 },
311};
312#endif
313
314#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
315#include <linux/i2c-gpio.h>
316
317static struct i2c_gpio_platform_data i2c_gpio_data = {
318 .sda_pin = 1,
319 .scl_pin = 0,
320 .sda_is_open_drain = 0,
321 .scl_is_open_drain = 0,
322 .udelay = 40,
323};
324
325static struct platform_device i2c_gpio_device = {
326 .name = "i2c-gpio",
327 .id = 0,
328 .dev = {
329 .platform_data = &i2c_gpio_data,
330 },
331};
332#endif
333
249static struct platform_device *ezkit_devices[] __initdata = { 334static struct platform_device *ezkit_devices[] __initdata = {
250#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 335#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
251 &smc91x_device, 336 &smc91x_device,
@@ -258,12 +343,23 @@ static struct platform_device *ezkit_devices[] __initdata = {
258#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 343#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
259 &bfin_spi0_device, 344 &bfin_spi0_device,
260#endif 345#endif
346
261#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 347#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
262 &bfin_uart_device, 348 &bfin_uart_device,
263#endif 349#endif
350
264#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 351#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
265 &bfin_pata_device, 352 &bfin_pata_device,
266#endif 353#endif
354
355#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
356 &bfin_device_gpiokeys,
357#endif
358
359#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
360 &i2c_gpio_device,
361#endif
362 &ezkit_flash_device,
267}; 363};
268 364
269static int __init ezkit_init(void) 365static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index 5d1d21b4c2a7..1b44e9e6dc3b 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -33,7 +33,9 @@
33#include <linux/ioport.h> 33#include <linux/ioport.h>
34#include <linux/module.h> 34#include <linux/module.h>
35#include <linux/uaccess.h> 35#include <linux/uaccess.h>
36#include <linux/fs.h>
36#include <asm/dma.h> 37#include <asm/dma.h>
38#include <asm/cacheflush.h>
37 39
38#define MODULE_VER "v0.1" 40#define MODULE_VER "v0.1"
39 41
@@ -90,11 +92,12 @@ static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
90 92
91 coreb_dma_done = 0; 93 coreb_dma_done = 0;
92 94
95 flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
93 /* Source Channel */ 96 /* Source Channel */
94 set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf); 97 set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
95 set_dma_x_count(CH_MEM_STREAM2_SRC, len); 98 set_dma_x_count(CH_MEM_STREAM2_SRC, len);
96 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); 99 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
97 set_dma_config(CH_MEM_STREAM2_SRC, RESTART); 100 set_dma_config(CH_MEM_STREAM2_SRC, 0);
98 /* Destination Channel */ 101 /* Destination Channel */
99 set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p); 102 set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
100 set_dma_x_count(CH_MEM_STREAM2_DEST, len); 103 set_dma_x_count(CH_MEM_STREAM2_DEST, len);
@@ -135,11 +138,12 @@ static ssize_t coreb_read(struct file *file, char *buf, size_t count,
135 138
136 coreb_dma_done = 0; 139 coreb_dma_done = 0;
137 140
141 invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
138 /* Source Channel */ 142 /* Source Channel */
139 set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p); 143 set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
140 set_dma_x_count(CH_MEM_STREAM2_SRC, len); 144 set_dma_x_count(CH_MEM_STREAM2_SRC, len);
141 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); 145 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
142 set_dma_config(CH_MEM_STREAM2_SRC, RESTART); 146 set_dma_config(CH_MEM_STREAM2_SRC, 0);
143 /* Destination Channel */ 147 /* Destination Channel */
144 set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf); 148 set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
145 set_dma_x_count(CH_MEM_STREAM2_DEST, len); 149 set_dma_x_count(CH_MEM_STREAM2_DEST, len);
@@ -266,7 +270,7 @@ static int coreb_ioctl(struct inode *inode, struct file *file,
266 coreb_status |= COREB_IS_RUNNING; 270 coreb_status |= COREB_IS_RUNNING;
267 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); 271 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
268 SSYNC(); 272 SSYNC();
269 spin_lock_irq(&coreb_lock); 273 spin_unlock_irq(&coreb_lock);
270 break; 274 break;
271#if defined(CONFIG_BF561_COREB_RESET) 275#if defined(CONFIG_BF561_COREB_RESET)
272 case CMD_COREB_STOP: 276 case CMD_COREB_STOP:
@@ -275,7 +279,7 @@ static int coreb_ioctl(struct inode *inode, struct file *file,
275 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); 279 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
276 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); 280 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
277 coreb_status &= ~COREB_IS_RUNNING; 281 coreb_status &= ~COREB_IS_RUNNING;
278 spin_lock_irq(&coreb_lock); 282 spin_unlock_irq(&coreb_lock);
279 break; 283 break;
280 case CMD_COREB_RESET: 284 case CMD_COREB_RESET:
281 printk(KERN_INFO "Resetting Core B\n"); 285 printk(KERN_INFO "Resetting Core B\n");
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 4d7733dfd5de..8636d4284bdb 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -3,10 +3,9 @@
3# 3#
4 4
5obj-y := \ 5obj-y := \
6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ 6 cache.o cacheinit.o entry.o \
7 interrupt.o lock.o irqpanic.o arch_checks.o 7 interrupt.o lock.o irqpanic.o arch_checks.o
8 8
9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o 9obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
11obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o 10obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
12obj-$(CONFIG_PM) += pm.o dpmc.o 11obj-$(CONFIG_PM) += pm.o dpmc.o
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 39fbc2861107..b82c096e1980 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -38,6 +38,9 @@ ENTRY(_unmask_wdog_wakeup_evt)
38#if defined(CONFIG_BF561) 38#if defined(CONFIG_BF561)
39 P0.H = hi(SICA_IWR1); 39 P0.H = hi(SICA_IWR1);
40 P0.L = lo(SICA_IWR1); 40 P0.L = lo(SICA_IWR1);
41#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
42 P0.h = HI(SIC_IWR0);
43 P0.l = LO(SIC_IWR0);
41#else 44#else
42 P0.h = HI(SIC_IWR); 45 P0.h = HI(SIC_IWR);
43 P0.l = LO(SIC_IWR); 46 P0.l = LO(SIC_IWR);
@@ -172,7 +175,7 @@ ENTRY(_sleep_mode)
172 call _set_sic_iwr; 175 call _set_sic_iwr;
173 176
174 R0 = 0xFFFF (Z); 177 R0 = 0xFFFF (Z);
175 call _set_rtc_istat 178 call _set_rtc_istat;
176 179
177 P0.H = hi(PLL_CTL); 180 P0.H = hi(PLL_CTL);
178 P0.L = lo(PLL_CTL); 181 P0.L = lo(PLL_CTL);
@@ -210,7 +213,7 @@ ENTRY(_hibernate_mode)
210 call _set_sic_iwr; 213 call _set_sic_iwr;
211 214
212 R0 = 0xFFFF (Z); 215 R0 = 0xFFFF (Z);
213 call _set_rtc_istat 216 call _set_rtc_istat;
214 217
215 P0.H = hi(VR_CTL); 218 P0.H = hi(VR_CTL);
216 P0.L = lo(VR_CTL); 219 P0.L = lo(VR_CTL);
@@ -236,7 +239,7 @@ ENTRY(_deep_sleep)
236 239
237 call _set_sic_iwr; 240 call _set_sic_iwr;
238 241
239 call _set_sdram_srfs; 242 call _set_dram_srfs;
240 243
241 /* Clear all the interrupts,bits sticky */ 244 /* Clear all the interrupts,bits sticky */
242 R0 = 0xFFFF (Z); 245 R0 = 0xFFFF (Z);
@@ -253,7 +256,7 @@ ENTRY(_deep_sleep)
253 SSYNC; 256 SSYNC;
254 IDLE; 257 IDLE;
255 258
256 call _unset_sdram_srfs; 259 call _unset_dram_srfs;
257 260
258 call _test_pll_locked; 261 call _test_pll_locked;
259 262
@@ -285,23 +288,22 @@ ENTRY(_sleep_deeper)
285 P3 = R0; 288 P3 = R0;
286 R0 = IWR_ENABLE(0); 289 R0 = IWR_ENABLE(0);
287 call _set_sic_iwr; 290 call _set_sic_iwr;
288 call _set_sdram_srfs; 291 call _set_dram_srfs; /* Set SDRAM Self Refresh */
289 292
290 /* Clear all the interrupts,bits sticky */ 293 /* Clear all the interrupts,bits sticky */
291 R0 = 0xFFFF (Z); 294 R0 = 0xFFFF (Z);
292 call _set_rtc_istat 295 call _set_rtc_istat;
293
294 P0.H = hi(PLL_DIV); 296 P0.H = hi(PLL_DIV);
295 P0.L = lo(PLL_DIV); 297 P0.L = lo(PLL_DIV);
296 R6 = W[P0](z); 298 R6 = W[P0](z);
297 R0.L = 0xF; 299 R0.L = 0xF;
298 W[P0] = R0.l; 300 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
299 301
300 P0.H = hi(PLL_CTL); 302 P0.H = hi(PLL_CTL);
301 P0.L = lo(PLL_CTL); 303 P0.L = lo(PLL_CTL);
302 R5 = W[P0](z); 304 R5 = W[P0](z);
303 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; 305 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
304 W[P0] = R0.l; 306 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
305 307
306 SSYNC; 308 SSYNC;
307 IDLE; 309 IDLE;
@@ -317,29 +319,28 @@ ENTRY(_sleep_deeper)
317 R1 = R1|R2; 319 R1 = R1|R2;
318 320
319 R2 = DEPOSIT(R7, R1); 321 R2 = DEPOSIT(R7, R1);
320 W[P0] = R2; 322 W[P0] = R2; /* Set Min Core Voltage */
321 323
322 SSYNC; 324 SSYNC;
323 IDLE; 325 IDLE;
324 326
325 call _test_pll_locked; 327 call _test_pll_locked;
326 328
329 R0 = P3;
330 call _set_sic_iwr; /* Set Awake from IDLE */
331
327 P0.H = hi(PLL_CTL); 332 P0.H = hi(PLL_CTL);
328 P0.L = lo(PLL_CTL); 333 P0.L = lo(PLL_CTL);
329 R0 = W[P0](z); 334 R0 = W[P0](z);
330 BITSET (R0, 3); 335 BITSET (R0, 3);
331 W[P0] = R0.L; 336 W[P0] = R0.L; /* Turn CCLK OFF */
332
333 R0 = P3;
334 call _set_sic_iwr;
335
336 SSYNC; 337 SSYNC;
337 IDLE; 338 IDLE;
338 339
339 call _test_pll_locked; 340 call _test_pll_locked;
340 341
341 R0 = IWR_ENABLE(0); 342 R0 = IWR_ENABLE(0);
342 call _set_sic_iwr; 343 call _set_sic_iwr; /* Set Awake from IDLE PLL */
343 344
344 P0.H = hi(VR_CTL); 345 P0.H = hi(VR_CTL);
345 P0.L = lo(VR_CTL); 346 P0.L = lo(VR_CTL);
@@ -352,15 +353,15 @@ ENTRY(_sleep_deeper)
352 353
353 P0.H = hi(PLL_DIV); 354 P0.H = hi(PLL_DIV);
354 P0.L = lo(PLL_DIV); 355 P0.L = lo(PLL_DIV);
355 W[P0]= R6; 356 W[P0]= R6; /* Restore CCLK and SCLK divider */
356 357
357 P0.H = hi(PLL_CTL); 358 P0.H = hi(PLL_CTL);
358 P0.L = lo(PLL_CTL); 359 P0.L = lo(PLL_CTL);
359 w[p0] = R5; 360 w[p0] = R5; /* Restore VCO multiplier */
360 IDLE; 361 IDLE;
361 call _test_pll_locked; 362 call _test_pll_locked;
362 363
363 call _unset_sdram_srfs; 364 call _unset_dram_srfs; /* SDRAM Self Refresh Off */
364 365
365 STI R4; 366 STI R4;
366 367
@@ -368,25 +369,47 @@ ENTRY(_sleep_deeper)
368 ( R7:0, P5:0 ) = [SP++]; 369 ( R7:0, P5:0 ) = [SP++];
369 RTS; 370 RTS;
370 371
371ENTRY(_set_sdram_srfs) 372ENTRY(_set_dram_srfs)
372 /* set the sdram to self refresh mode */ 373 /* set the dram to self refresh mode */
374#if defined(CONFIG_BF54x)
375 P0.H = hi(EBIU_RSTCTL);
376 P0.L = lo(EBIU_RSTCTL);
377 R2 = [P0];
378 R3.H = hi(SRREQ);
379 R3.L = lo(SRREQ);
380#else
373 P0.H = hi(EBIU_SDGCTL); 381 P0.H = hi(EBIU_SDGCTL);
374 P0.L = lo(EBIU_SDGCTL); 382 P0.L = lo(EBIU_SDGCTL);
375 R2 = [P0]; 383 R2 = [P0];
376 R3.H = hi(SRFS); 384 R3.H = hi(SRFS);
377 R3.L = lo(SRFS); 385 R3.L = lo(SRFS);
386#endif
378 R2 = R2|R3; 387 R2 = R2|R3;
379 [P0] = R2; 388 [P0] = R2;
380 ssync; 389 ssync;
390#if defined(CONFIG_BF54x)
391.LSRR_MODE:
392 R2 = [P0];
393 CC = BITTST(R2, 4);
394 if !CC JUMP .LSRR_MODE;
395#endif
381 RTS; 396 RTS;
382 397
383ENTRY(_unset_sdram_srfs) 398ENTRY(_unset_dram_srfs)
384 /* set the sdram out of self refresh mode */ 399 /* set the dram out of self refresh mode */
400#if defined(CONFIG_BF54x)
401 P0.H = hi(EBIU_RSTCTL);
402 P0.L = lo(EBIU_RSTCTL);
403 R2 = [P0];
404 R3.H = hi(SRREQ);
405 R3.L = lo(SRREQ);
406#else
385 P0.H = hi(EBIU_SDGCTL); 407 P0.H = hi(EBIU_SDGCTL);
386 P0.L = lo(EBIU_SDGCTL); 408 P0.L = lo(EBIU_SDGCTL);
387 R2 = [P0]; 409 R2 = [P0];
388 R3.H = hi(SRFS); 410 R3.H = hi(SRFS);
389 R3.L = lo(SRFS); 411 R3.L = lo(SRFS);
412#endif
390 R3 = ~R3; 413 R3 = ~R3;
391 R2 = R2&R3; 414 R2 = R2&R3;
392 [P0] = R2; 415 [P0] = R2;
@@ -394,8 +417,13 @@ ENTRY(_unset_sdram_srfs)
394 RTS; 417 RTS;
395 418
396ENTRY(_set_sic_iwr) 419ENTRY(_set_sic_iwr)
420#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
421 P0.H = hi(SIC_IWR0);
422 P0.L = lo(SIC_IWR0);
423#else
397 P0.H = hi(SIC_IWR); 424 P0.H = hi(SIC_IWR);
398 P0.L = lo(SIC_IWR); 425 P0.L = lo(SIC_IWR);
426#endif
399 [P0] = R0; 427 [P0] = R0;
400 SSYNC; 428 SSYNC;
401 RTS; 429 RTS;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index dc9d3ee2e691..56ff51bc8c21 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -95,6 +95,9 @@ ENTRY(_ex_workaround_261)
95 R6 = 0x26; /* Data CPLB Miss */ 95 R6 = 0x26; /* Data CPLB Miss */
96 cc = R6 == R7; 96 cc = R6 == R7;
97 if cc jump _ex_dcplb_miss (BP); 97 if cc jump _ex_dcplb_miss (BP);
98 R6 = 0x23; /* Data CPLB Miss */
99 cc = R6 == R7;
100 if cc jump _ex_dcplb_viol (BP);
98 /* Handle 0x23 Data CPLB Protection Violation 101 /* Handle 0x23 Data CPLB Protection Violation
99 * and Data CPLB Multiple Hits - Linux Trap Zero 102 * and Data CPLB Multiple Hits - Linux Trap Zero
100 */ 103 */
@@ -102,17 +105,33 @@ ENTRY(_ex_workaround_261)
102ENDPROC(_ex_workaround_261) 105ENDPROC(_ex_workaround_261)
103 106
104#else 107#else
108#ifdef CONFIG_MPU
109#define _ex_dviol _ex_dcplb_viol
110#else
105#define _ex_dviol _ex_trap_c 111#define _ex_dviol _ex_trap_c
112#endif
106#define _ex_dmiss _ex_dcplb_miss 113#define _ex_dmiss _ex_dcplb_miss
107#define _ex_dmult _ex_trap_c 114#define _ex_dmult _ex_trap_c
108#endif 115#endif
109 116
117
118ENTRY(_ex_dcplb_viol)
110ENTRY(_ex_dcplb_miss) 119ENTRY(_ex_dcplb_miss)
111ENTRY(_ex_icplb_miss) 120ENTRY(_ex_icplb_miss)
112 (R7:6,P5:4) = [sp++]; 121 (R7:6,P5:4) = [sp++];
113 ASTAT = [sp++]; 122 ASTAT = [sp++];
114 SAVE_ALL_SYS 123 SAVE_ALL_SYS
124#ifdef CONFIG_MPU
125 R0 = SEQSTAT;
126 R1 = SP;
127 sp += -12;
128 call _cplb_hdr;
129 sp += 12;
130 CC = R0 == 0;
131 IF !CC JUMP _handle_bad_cplb;
132#else
115 call __cplb_hdr; 133 call __cplb_hdr;
134#endif
116 DEBUG_START_HWTRACE(p5, r7) 135 DEBUG_START_HWTRACE(p5, r7)
117 RESTORE_ALL_SYS 136 RESTORE_ALL_SYS
118 SP = EX_SCRATCH_REG; 137 SP = EX_SCRATCH_REG;
@@ -329,7 +348,7 @@ ENTRY(_exception_to_level5)
329 R7 = R7 + R6; 348 R7 = R7 + R6;
330 P5 = R7; 349 P5 = R7;
331 R1 = [P5]; 350 R1 = [P5];
332 [SP + 8] = r1; 351 [SP + PT_SEQSTAT] = r1;
333 352
334 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ 353 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
335 SP += -12; 354 SP += -12;
@@ -633,9 +652,7 @@ ENTRY(_ret_from_exception)
633 [sp + PT_IPEND] = r0; 652 [sp + PT_IPEND] = r0;
634 653
6351: 6541:
636 r1 = 0x37(Z); 655 r2 = LO(~0x37) (Z);
637 r2 = ~r1;
638 r2.h = 0;
639 r0 = r2 & r0; 656 r0 = r2 & r0;
640 cc = r0 == 0; 657 cc = r0 == 0;
641 if !cc jump 4f; /* if not return to user mode, get out */ 658 if !cc jump 4f; /* if not return to user mode, get out */
@@ -1364,6 +1381,7 @@ ENTRY(_sys_call_table)
1364 .long _sys_set_robust_list 1381 .long _sys_set_robust_list
1365 .long _sys_get_robust_list /* 355 */ 1382 .long _sys_get_robust_list /* 355 */
1366 .long _sys_fallocate 1383 .long _sys_fallocate
1384 .long _sys_semtimedop
1367 .rept NR_syscalls-(.-_sys_call_table)/4 1385 .rept NR_syscalls-(.-_sys_call_table)/4
1368 .long _sys_ni_syscall 1386 .long _sys_ni_syscall
1369 .endr 1387 .endr
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 4de376418a18..7f752c87fe46 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -34,9 +34,13 @@
34#include <asm/entry.h> 34#include <asm/entry.h>
35#include <asm/asm-offsets.h> 35#include <asm/asm-offsets.h>
36#include <asm/trace.h> 36#include <asm/trace.h>
37#include <asm/traps.h>
38#include <asm/thread_info.h>
37 39
38#include <asm/mach-common/context.S> 40#include <asm/mach-common/context.S>
39 41
42.extern _ret_from_exception
43
40#ifdef CONFIG_I_ENTRY_L1 44#ifdef CONFIG_I_ENTRY_L1
41.section .l1.text 45.section .l1.text
42#else 46#else
@@ -117,8 +121,8 @@ __common_int_entry:
117 121
118#if ANOMALY_05000283 || ANOMALY_05000315 122#if ANOMALY_05000283 || ANOMALY_05000315
119 cc = r7 == r7; 123 cc = r7 == r7;
120 p5.h = 0xffc0; 124 p5.h = HI(CHIPID);
121 p5.l = 0x0014; 125 p5.l = LO(CHIPID);
122 if cc jump 1f; 126 if cc jump 1f;
123 r7.l = W[p5]; 127 r7.l = W[p5];
1241: 1281:
@@ -134,26 +138,22 @@ __common_int_entry:
134 138
135/* interrupt routine for ivhw - 5 */ 139/* interrupt routine for ivhw - 5 */
136ENTRY(_evt_ivhw) 140ENTRY(_evt_ivhw)
137 SAVE_CONTEXT 141 SAVE_ALL_SYS
138#ifdef CONFIG_FRAME_POINTER 142#ifdef CONFIG_FRAME_POINTER
139 fp = 0; 143 fp = 0;
140#endif 144#endif
145
141#if ANOMALY_05000283 146#if ANOMALY_05000283
142 cc = r7 == r7; 147 cc = r7 == r7;
143 p5.h = 0xffc0; 148 p5.h = HI(CHIPID);
144 p5.l = 0x0014; 149 p5.l = LO(CHIPID);
145 if cc jump 1f; 150 if cc jump 1f;
146 r7.l = W[p5]; 151 r7.l = W[p5];
1471: 1521:
148#endif 153#endif
149 154
150 trace_buffer_stop(p0, r0);
151
152 r0 = IRQ_HWERR;
153 r1 = sp;
154
155#ifdef CONFIG_HARDWARE_PM 155#ifdef CONFIG_HARDWARE_PM
156 r7 = SEQSTAT; 156 r7 = [sp + PT_SEQSTAT];
157 r7 = r7 >>> 0xe; 157 r7 = r7 >>> 0xe;
158 r6 = 0x1F; 158 r6 = 0x1F;
159 r7 = r7 & r6; 159 r7 = r7 & r6;
@@ -161,11 +161,29 @@ ENTRY(_evt_ivhw)
161 cc = r7 == r5; 161 cc = r7 == r5;
162 if cc jump .Lcall_do_ovf; /* deal with performance counter overflow */ 162 if cc jump .Lcall_do_ovf; /* deal with performance counter overflow */
163#endif 163#endif
164 164 # We are going to dump something out, so make sure we print IPEND properly
165 p2.l = lo(IPEND);
166 p2.h = hi(IPEND);
167 r0 = [p2];
168 [sp + PT_IPEND] = r0;
169
170 /* set the EXCAUSE to HWERR for trap_c */
171 r0 = [sp + PT_SEQSTAT];
172 R1.L = LO(VEC_HWERR);
173 R1.H = HI(VEC_HWERR);
174 R0 = R0 | R1;
175 [sp + PT_SEQSTAT] = R0;
176
177 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
165 SP += -12; 178 SP += -12;
166 call _irq_panic; 179 call _trap_c;
167 SP += 12; 180 SP += 12;
181
182 call _ret_from_exception;
183.Lcommon_restore_all_sys:
184 RESTORE_ALL_SYS
168 rti; 185 rti;
186
169#ifdef CONFIG_HARDWARE_PM 187#ifdef CONFIG_HARDWARE_PM
170.Lcall_do_ovf: 188.Lcall_do_ovf:
171 189
@@ -173,9 +191,11 @@ ENTRY(_evt_ivhw)
173 call _pm_overflow; 191 call _pm_overflow;
174 SP += 12; 192 SP += 12;
175 193
176 jump .Lcommon_restore_context; 194 jump .Lcommon_restore_all_sys;
177#endif 195#endif
178 196
197ENDPROC(_evt_ivhw)
198
179/* Interrupt routine for evt2 (NMI). 199/* Interrupt routine for evt2 (NMI).
180 * We don't actually use this, so just return. 200 * We don't actually use this, so just return.
181 * For inner circle type details, please see: 201 * For inner circle type details, please see:
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 4882f0e801a9..8d18d6b163bb 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -222,11 +222,12 @@ static void bf561_gpio_unmask_irq(unsigned int irq)
222static unsigned int bf561_gpio_irq_startup(unsigned int irq) 222static unsigned int bf561_gpio_irq_startup(unsigned int irq)
223{ 223{
224 unsigned int ret; 224 unsigned int ret;
225 char buf[8];
225 u16 gpionr = irq - IRQ_PF0; 226 u16 gpionr = irq - IRQ_PF0;
226 227
227 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 228 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
228 229 snprintf(buf, sizeof buf, "IRQ %d", irq);
229 ret = gpio_request(gpionr, "IRQ"); 230 ret = gpio_request(gpionr, buf);
230 if (ret) 231 if (ret)
231 return ret; 232 return ret;
232 233
@@ -250,6 +251,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
250{ 251{
251 252
252 unsigned int ret; 253 unsigned int ret;
254 char buf[8];
253 u16 gpionr = irq - IRQ_PF0; 255 u16 gpionr = irq - IRQ_PF0;
254 256
255 257
@@ -265,8 +267,8 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
265 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 267 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
266 268
267 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 269 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
268 270 snprintf(buf, sizeof buf, "IRQ %d", irq);
269 ret = gpio_request(gpionr, "IRQ"); 271 ret = gpio_request(gpionr, buf);
270 if (ret) 272 if (ret)
271 return ret; 273 return ret;
272 274
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 147f0731087a..dec42acb5de0 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -313,6 +313,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
313static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; 313static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
314static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; 314static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
315 315
316
316static void bfin_gpio_ack_irq(unsigned int irq) 317static void bfin_gpio_ack_irq(unsigned int irq)
317{ 318{
318 u16 gpionr = irq - IRQ_PF0; 319 u16 gpionr = irq - IRQ_PF0;
@@ -352,9 +353,11 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
352{ 353{
353 unsigned int ret; 354 unsigned int ret;
354 u16 gpionr = irq - IRQ_PF0; 355 u16 gpionr = irq - IRQ_PF0;
356 char buf[8];
355 357
356 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 358 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
357 ret = gpio_request(gpionr, "IRQ"); 359 snprintf(buf, sizeof buf, "IRQ %d", irq);
360 ret = gpio_request(gpionr, buf);
358 if (ret) 361 if (ret)
359 return ret; 362 return ret;
360 } 363 }
@@ -376,6 +379,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
376{ 379{
377 380
378 unsigned int ret; 381 unsigned int ret;
382 char buf[8];
379 u16 gpionr = irq - IRQ_PF0; 383 u16 gpionr = irq - IRQ_PF0;
380 384
381 if (type == IRQ_TYPE_PROBE) { 385 if (type == IRQ_TYPE_PROBE) {
@@ -388,7 +392,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 392 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
389 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 393 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
390 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 394 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
391 ret = gpio_request(gpionr, "IRQ"); 395 snprintf(buf, sizeof buf, "IRQ %d", irq);
396 ret = gpio_request(gpionr, buf);
392 if (ret) 397 if (ret)
393 return ret; 398 return ret;
394 } 399 }
@@ -478,6 +483,10 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
478static unsigned char irq2pint_lut[NR_PINTS]; 483static unsigned char irq2pint_lut[NR_PINTS];
479static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; 484static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
480 485
486static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
487static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
488
489
481struct pin_int_t { 490struct pin_int_t {
482 unsigned int mask_set; 491 unsigned int mask_set;
483 unsigned int mask_clear; 492 unsigned int mask_clear;
@@ -544,13 +553,20 @@ void init_pint_lut(void)
544 553
545} 554}
546 555
547static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
548
549static void bfin_gpio_ack_irq(unsigned int irq) 556static void bfin_gpio_ack_irq(unsigned int irq)
550{ 557{
551 u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; 558 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
559 u32 pintbit = PINT_BIT(pint_val);
560 u8 bank = PINT_2_BANK(pint_val);
561
562 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
563 if (pint[bank]->invert_set & pintbit)
564 pint[bank]->invert_clear = pintbit;
565 else
566 pint[bank]->invert_set = pintbit;
567 }
568 pint[bank]->request = pintbit;
552 569
553 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
554 SSYNC(); 570 SSYNC();
555} 571}
556 572
@@ -560,6 +576,13 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq)
560 u32 pintbit = PINT_BIT(pint_val); 576 u32 pintbit = PINT_BIT(pint_val);
561 u8 bank = PINT_2_BANK(pint_val); 577 u8 bank = PINT_2_BANK(pint_val);
562 578
579 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
580 if (pint[bank]->invert_set & pintbit)
581 pint[bank]->invert_clear = pintbit;
582 else
583 pint[bank]->invert_set = pintbit;
584 }
585
563 pint[bank]->request = pintbit; 586 pint[bank]->request = pintbit;
564 pint[bank]->mask_clear = pintbit; 587 pint[bank]->mask_clear = pintbit;
565 SSYNC(); 588 SSYNC();
@@ -587,7 +610,8 @@ static void bfin_gpio_unmask_irq(unsigned int irq)
587static unsigned int bfin_gpio_irq_startup(unsigned int irq) 610static unsigned int bfin_gpio_irq_startup(unsigned int irq)
588{ 611{
589 unsigned int ret; 612 unsigned int ret;
590 u16 gpionr = irq - IRQ_PA0; 613 char buf[8];
614 u16 gpionr = irq_to_gpio(irq);
591 u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; 615 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
592 616
593 if (pint_val == IRQ_NOT_AVAIL) { 617 if (pint_val == IRQ_NOT_AVAIL) {
@@ -598,7 +622,8 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
598 } 622 }
599 623
600 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 624 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
601 ret = gpio_request(gpionr, "IRQ"); 625 snprintf(buf, sizeof buf, "IRQ %d", irq);
626 ret = gpio_request(gpionr, buf);
602 if (ret) 627 if (ret)
603 return ret; 628 return ret;
604 } 629 }
@@ -611,16 +636,19 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
611 636
612static void bfin_gpio_irq_shutdown(unsigned int irq) 637static void bfin_gpio_irq_shutdown(unsigned int irq)
613{ 638{
639 u16 gpionr = irq_to_gpio(irq);
640
614 bfin_gpio_mask_irq(irq); 641 bfin_gpio_mask_irq(irq);
615 gpio_free(irq - IRQ_PA0); 642 gpio_free(gpionr);
616 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0); 643 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
617} 644}
618 645
619static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) 646static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
620{ 647{
621 648
622 unsigned int ret; 649 unsigned int ret;
623 u16 gpionr = irq - IRQ_PA0; 650 char buf[8];
651 u16 gpionr = irq_to_gpio(irq);
624 u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; 652 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
625 u32 pintbit = PINT_BIT(pint_val); 653 u32 pintbit = PINT_BIT(pint_val);
626 u8 bank = PINT_2_BANK(pint_val); 654 u8 bank = PINT_2_BANK(pint_val);
@@ -638,7 +666,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
638 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 666 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
639 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 667 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
640 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 668 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
641 ret = gpio_request(gpionr, "IRQ"); 669 snprintf(buf, sizeof buf, "IRQ %d", irq);
670 ret = gpio_request(gpionr, buf);
642 if (ret) 671 if (ret)
643 return ret; 672 return ret;
644 } 673 }
@@ -651,28 +680,33 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
651 680
652 gpio_direction_input(gpionr); 681 gpio_direction_input(gpionr);
653 682
654 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
655 pint[bank]->edge_set = pintbit;
656 } else {
657 pint[bank]->edge_clear = pintbit;
658 }
659
660 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) 683 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
661 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ 684 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
662 else 685 else
663 pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */ 686 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
664 687
665 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 688 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
666 pint[bank]->invert_set = pintbit; 689 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
667 else
668 pint[bank]->invert_set = pintbit;
669 690
670 SSYNC(); 691 gpio_both_edge_triggered[bank] |= pintbit;
671 692
672 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 693 if (gpio_get_value(gpionr))
694 pint[bank]->invert_set = pintbit;
695 else
696 pint[bank]->invert_clear = pintbit;
697 } else {
698 gpio_both_edge_triggered[bank] &= ~pintbit;
699 }
700
701 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
702 pint[bank]->edge_set = pintbit;
673 set_irq_handler(irq, handle_edge_irq); 703 set_irq_handler(irq, handle_edge_irq);
674 else 704 } else {
705 pint[bank]->edge_clear = pintbit;
675 set_irq_handler(irq, handle_level_irq); 706 set_irq_handler(irq, handle_level_irq);
707 }
708
709 SSYNC();
676 710
677 return 0; 711 return 0;
678} 712}
diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c
index b22959b197e5..606ded9ff4e1 100644
--- a/arch/blackfin/mach-common/irqpanic.c
+++ b/arch/blackfin/mach-common/irqpanic.c
@@ -46,9 +46,6 @@ void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text));
46 */ 46 */
47asmlinkage void irq_panic(int reason, struct pt_regs *regs) 47asmlinkage void irq_panic(int reason, struct pt_regs *regs)
48{ 48{
49 int sig = 0;
50 siginfo_t info;
51
52#ifdef CONFIG_DEBUG_ICACHE_CHECK 49#ifdef CONFIG_DEBUG_ICACHE_CHECK
53 unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa; 50 unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
54 unsigned short i, j, die; 51 unsigned short i, j, die;
@@ -136,53 +133,6 @@ asmlinkage void irq_panic(int reason, struct pt_regs *regs)
136 } 133 }
137#endif 134#endif
138 135
139 printk(KERN_EMERG "\n");
140 printk(KERN_EMERG "Exception: IRQ 0x%x entered\n", reason);
141 printk(KERN_EMERG " code=[0x%08lx], stack frame=0x%08lx, "
142 " bad PC=0x%08lx\n",
143 (unsigned long)regs->seqstat,
144 (unsigned long)regs,
145 (unsigned long)regs->pc);
146 if (reason == 0x5) {
147 printk(KERN_EMERG "----------- HARDWARE ERROR -----------\n");
148
149 /* There is only need to check for Hardware Errors, since other
150 * EXCEPTIONS are handled in TRAPS.c (MH)
151 */
152 switch (regs->seqstat & SEQSTAT_HWERRCAUSE) {
153 case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): /* System MMR Error */
154 info.si_code = BUS_ADRALN;
155 sig = SIGBUS;
156 printk(KERN_EMERG HWC_x2(KERN_EMERG));
157 break;
158 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): /* External Memory Addressing Error */
159 info.si_code = BUS_ADRERR;
160 sig = SIGBUS;
161 printk(KERN_EMERG HWC_x3(KERN_EMERG));
162 break;
163 case (SEQSTAT_HWERRCAUSE_PERF_FLOW): /* Performance Monitor Overflow */
164 printk(KERN_EMERG HWC_x12(KERN_EMERG));
165 break;
166 case (SEQSTAT_HWERRCAUSE_RAISE_5): /* RAISE 5 instruction */
167 printk(KERN_EMERG HWC_x18(KERN_EMERG));
168 break;
169 default: /* Reserved */
170 printk(KERN_EMERG HWC_default(KERN_EMERG));
171 break;
172 }
173 }
174
175 regs->ipend = bfin_read_IPEND();
176 dump_bfin_process(regs);
177 dump_bfin_mem((void *)regs->pc);
178 show_regs(regs);
179 if (0 == (info.si_signo = sig) || 0 == user_mode(regs)) /* in kernelspace */
180 panic("Unhandled IRQ or exceptions!\n");
181 else { /* in userspace */
182 info.si_errno = 0;
183 info.si_addr = (void *)regs->pc;
184 force_sig_info(sig, &info, current);
185 }
186} 136}
187 137
188#ifdef CONFIG_HARDWARE_PM 138#ifdef CONFIG_HARDWARE_PM
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index dac51fb06f22..81930f7d06f1 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -77,7 +77,15 @@ void bfin_pm_suspend_standby_enter(void)
77 77
78 gpio_pm_restore(); 78 gpio_pm_restore();
79 79
80#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
81 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
82 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
83# ifdef CONFIG_BF54x
84 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
85# endif
86#else
80 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 87 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
88#endif
81 89
82 local_irq_restore(flags); 90 local_irq_restore(flags);
83 } 91 }
@@ -85,7 +93,15 @@ void bfin_pm_suspend_standby_enter(void)
85 93
86#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR) 94#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)
87 sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR); 95 sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
96# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
97 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
98 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
99# ifdef CONFIG_BF54x
100 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
101# endif
102# else
88 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 103 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
104# endif
89#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */ 105#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */
90} 106}
91 107
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index e97ea8fc8dc4..eb1a12ac9e33 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -128,8 +128,8 @@ void __init paging_init(void)
128void __init mem_init(void) 128void __init mem_init(void)
129{ 129{
130 unsigned int codek = 0, datak = 0, initk = 0; 130 unsigned int codek = 0, datak = 0, initk = 0;
131 unsigned int reservedpages = 0, freepages = 0;
131 unsigned long tmp; 132 unsigned long tmp;
132 unsigned int len = _ramend - _rambase;
133 unsigned long start_mem = memory_start; 133 unsigned long start_mem = memory_start;
134 unsigned long end_mem = memory_end; 134 unsigned long end_mem = memory_end;
135 135
@@ -138,19 +138,36 @@ void __init mem_init(void)
138 138
139 start_mem = PAGE_ALIGN(start_mem); 139 start_mem = PAGE_ALIGN(start_mem);
140 max_mapnr = num_physpages = MAP_NR(high_memory); 140 max_mapnr = num_physpages = MAP_NR(high_memory);
141 printk(KERN_INFO "Physical pages: %lx\n", num_physpages); 141 printk(KERN_INFO "Kernel managed physical pages: %lu\n",
142 num_physpages);
142 143
143 /* This will put all memory onto the freelists. */ 144 /* This will put all memory onto the freelists. */
144 totalram_pages = free_all_bootmem(); 145 totalram_pages = free_all_bootmem();
145 146
147 reservedpages = 0;
148 for (tmp = 0; tmp < max_mapnr; tmp++)
149 if (PageReserved(pfn_to_page(tmp)))
150 reservedpages++;
151 freepages = max_mapnr - reservedpages;
152
153 /* do not count in kernel image between _rambase and _ramstart */
154 reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
155#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
156 reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >>
157 PAGE_SHIFT;
158#endif
159
146 codek = (_etext - _stext) >> 10; 160 codek = (_etext - _stext) >> 10;
147 datak = (__bss_stop - __bss_start) >> 10;
148 initk = (__init_end - __init_begin) >> 10; 161 initk = (__init_end - __init_begin) >> 10;
162 datak = ((_ramstart - _rambase) >> 10) - codek - initk;
149 163
150 tmp = nr_free_pages() << PAGE_SHIFT;
151 printk(KERN_INFO 164 printk(KERN_INFO
152 "Memory available: %luk/%uk RAM, (%uk init code, %uk kernel code, %uk data, %uk dma)\n", 165 "Memory available: %luk/%luk RAM, "
153 tmp >> 10, len >> 10, initk, codek, datak, DMA_UNCACHED_REGION >> 10); 166 "(%uk init code, %uk kernel code, "
167 "%uk data, %uk dma, %uk reserved)\n",
168 (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
169 initk, codek, datak, DMA_UNCACHED_REGION >> 10,
170 (reservedpages << (PAGE_SHIFT-10)));
154 171
155 /* Initialize the blackfin L1 Memory. */ 172 /* Initialize the blackfin L1 Memory. */
156 l1sram_init(); 173 l1sram_init();
@@ -184,13 +201,15 @@ static __init void free_init_pages(const char *what, unsigned long begin, unsign
184#ifdef CONFIG_BLK_DEV_INITRD 201#ifdef CONFIG_BLK_DEV_INITRD
185void __init free_initrd_mem(unsigned long start, unsigned long end) 202void __init free_initrd_mem(unsigned long start, unsigned long end)
186{ 203{
204#ifndef CONFIG_MPU
187 free_init_pages("initrd memory", start, end); 205 free_init_pages("initrd memory", start, end);
206#endif
188} 207}
189#endif 208#endif
190 209
191void __init free_initmem(void) 210void __init free_initmem(void)
192{ 211{
193#ifdef CONFIG_RAMKERNEL 212#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
194 free_init_pages("unused kernel memory", 213 free_init_pages("unused kernel memory",
195 (unsigned long)(&__init_begin), 214 (unsigned long)(&__init_begin),
196 (unsigned long)(&__init_end)); 215 (unsigned long)(&__init_end));
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 6f475b609864..ac2a3ef28d55 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -442,7 +442,8 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
442 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, 442 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
443 INTR_ON_BUF, 443 INTR_ON_BUF,
444 DIMENSION_LINEAR, 444 DIMENSION_LINEAR,
445 DATA_SIZE_8)); 445 DATA_SIZE_8,
446 DMA_SYNC_RESTART));
446 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); 447 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
447 set_dma_x_count(uart->tx_dma_channel, uart->tx_count); 448 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
448 set_dma_x_modify(uart->tx_dma_channel, 1); 449 set_dma_x_modify(uart->tx_dma_channel, 1);
@@ -689,7 +690,8 @@ static int bfin_serial_startup(struct uart_port *port)
689 set_dma_config(uart->rx_dma_channel, 690 set_dma_config(uart->rx_dma_channel,
690 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, 691 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
691 INTR_ON_ROW, DIMENSION_2D, 692 INTR_ON_ROW, DIMENSION_2D,
692 DATA_SIZE_8)); 693 DATA_SIZE_8,
694 DMA_SYNC_RESTART));
693 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); 695 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
694 set_dma_x_modify(uart->rx_dma_channel, 1); 696 set_dma_x_modify(uart->rx_dma_channel, 1);
695 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); 697 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c
index 74d11c318987..c8e7427a0bc8 100644
--- a/drivers/video/bf54x-lq043fb.c
+++ b/drivers/video/bf54x-lq043fb.c
@@ -224,7 +224,8 @@ static int config_dma(struct bfin_bf54xfb_info *fbi)
224 set_dma_config(CH_EPPI0, 224 set_dma_config(CH_EPPI0,
225 set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, 225 set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
226 INTR_DISABLE, DIMENSION_2D, 226 INTR_DISABLE, DIMENSION_2D,
227 DATA_SIZE_32)); 227 DATA_SIZE_32,
228 DMA_NOSYNC_KEEP_DMA_BUF));
228 set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); 229 set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
229 set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8); 230 set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8);
230 set_dma_y_count(CH_EPPI0, LCD_Y_RES); 231 set_dma_y_count(CH_EPPI0, LCD_Y_RES);
@@ -263,8 +264,7 @@ static int request_ports(struct bfin_bf54xfb_info *fbi)
263 } 264 }
264 } 265 }
265 266
266 gpio_direction_output(disp); 267 gpio_direction_output(disp, 1);
267 gpio_set_value(disp, 1);
268 268
269 return 0; 269 return 0;
270} 270}
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 39bdd86871cf..6ae0619d7696 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -51,7 +51,7 @@ extern unsigned long sclk_to_usecs(unsigned long sclk);
51extern unsigned long usecs_to_sclk(unsigned long usecs); 51extern unsigned long usecs_to_sclk(unsigned long usecs);
52 52
53extern void dump_bfin_process(struct pt_regs *regs); 53extern void dump_bfin_process(struct pt_regs *regs);
54extern void dump_bfin_mem(void *retaddr); 54extern void dump_bfin_mem(struct pt_regs *regs);
55extern void dump_bfin_trace_buffer(void); 55extern void dump_bfin_trace_buffer(void);
56 56
57extern int init_arch_irq(void); 57extern int init_arch_irq(void);
diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h
new file mode 100644
index 000000000000..75c67b99d607
--- /dev/null
+++ b/include/asm-blackfin/cplb-mpu.h
@@ -0,0 +1,61 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#ifndef __ASM_BFIN_CPLB_MPU_H
30#define __ASM_BFIN_CPLB_MPU_H
31
32struct cplb_entry {
33 unsigned long data, addr;
34};
35
36struct mem_region {
37 unsigned long start, end;
38 unsigned long dcplb_data;
39 unsigned long icplb_data;
40};
41
42extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
43extern struct cplb_entry icplb_tbl[MAX_CPLBS];
44extern int first_switched_icplb;
45extern int first_mask_dcplb;
46extern int first_switched_dcplb;
47
48extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
49extern int nr_cplb_flush;
50
51extern int page_mask_order;
52extern int page_mask_nelts;
53
54extern unsigned long *current_rwx_mask;
55
56extern void flush_switched_cplbs(void);
57extern void set_mask_dcplbs(unsigned long *);
58
59extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
60
61#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 06828d77a58f..654375c2b746 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -65,7 +65,11 @@
65#define SIZE_1M 0x00100000 /* 1M */ 65#define SIZE_1M 0x00100000 /* 1M */
66#define SIZE_4M 0x00400000 /* 4M */ 66#define SIZE_4M 0x00400000 /* 4M */
67 67
68#ifdef CONFIG_MPU
69#define MAX_CPLBS 16
70#else
68#define MAX_CPLBS (16 * 2) 71#define MAX_CPLBS (16 * 2)
72#endif
69 73
70#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ 74#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
71 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) 75 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index c4d0596e8e9f..0eb1c1b685a7 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -33,6 +33,12 @@
33#include <asm/blackfin.h> 33#include <asm/blackfin.h>
34#include <asm/cplb.h> 34#include <asm/cplb.h>
35 35
36#ifdef CONFIG_MPU
37
38#include <asm/cplb-mpu.h>
39
40#else
41
36#define INITIAL_T 0x1 42#define INITIAL_T 0x1
37#define SWITCH_T 0x2 43#define SWITCH_T 0x2
38#define I_CPLB 0x4 44#define I_CPLB 0x4
@@ -79,6 +85,8 @@ extern u_long ipdt_swapcount_table[];
79extern u_long dpdt_swapcount_table[]; 85extern u_long dpdt_swapcount_table[];
80#endif 86#endif
81 87
88#endif /* CONFIG_MPU */
89
82extern unsigned long reserved_mem_dcache_on; 90extern unsigned long reserved_mem_dcache_on;
83extern unsigned long reserved_mem_icache_on; 91extern unsigned long reserved_mem_icache_on;
84 92
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index b469505af364..5abaa2cee8db 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -76,6 +76,9 @@ enum dma_chan_status {
76#define INTR_ON_BUF 2 76#define INTR_ON_BUF 2
77#define INTR_ON_ROW 3 77#define INTR_ON_ROW 3
78 78
79#define DMA_NOSYNC_KEEP_DMA_BUF 0
80#define DMA_SYNC_RESTART 1
81
79struct dmasg { 82struct dmasg {
80 unsigned long next_desc_addr; 83 unsigned long next_desc_addr;
81 unsigned long start_addr; 84 unsigned long start_addr;
@@ -157,7 +160,8 @@ void set_dma_y_count(unsigned int channel, unsigned short y_count);
157void set_dma_y_modify(unsigned int channel, short y_modify); 160void set_dma_y_modify(unsigned int channel, short y_modify);
158void set_dma_config(unsigned int channel, unsigned short config); 161void set_dma_config(unsigned int channel, unsigned short config);
159unsigned short set_bfin_dma_config(char direction, char flow_mode, 162unsigned short set_bfin_dma_config(char direction, char flow_mode,
160 char intr_mode, char dma_mode, char width); 163 char intr_mode, char dma_mode, char width,
164 char syncmode);
161void set_dma_curr_addr(unsigned int channel, unsigned long addr); 165void set_dma_curr_addr(unsigned int channel, unsigned long addr);
162 166
163/* get curr status for polling */ 167/* get curr status for polling */
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index 33ce98ef7e0f..d0426c108262 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -7,7 +7,7 @@
7 * Description: 7 * Description:
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc. 10 * Copyright 2004-2008 Analog Devices Inc.
11 * 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * 13 *
@@ -304,39 +304,39 @@
304**************************************************************/ 304**************************************************************/
305 305
306#ifndef BF548_FAMILY 306#ifndef BF548_FAMILY
307void set_gpio_dir(unsigned short, unsigned short); 307void set_gpio_dir(unsigned, unsigned short);
308void set_gpio_inen(unsigned short, unsigned short); 308void set_gpio_inen(unsigned, unsigned short);
309void set_gpio_polar(unsigned short, unsigned short); 309void set_gpio_polar(unsigned, unsigned short);
310void set_gpio_edge(unsigned short, unsigned short); 310void set_gpio_edge(unsigned, unsigned short);
311void set_gpio_both(unsigned short, unsigned short); 311void set_gpio_both(unsigned, unsigned short);
312void set_gpio_data(unsigned short, unsigned short); 312void set_gpio_data(unsigned, unsigned short);
313void set_gpio_maska(unsigned short, unsigned short); 313void set_gpio_maska(unsigned, unsigned short);
314void set_gpio_maskb(unsigned short, unsigned short); 314void set_gpio_maskb(unsigned, unsigned short);
315void set_gpio_toggle(unsigned short); 315void set_gpio_toggle(unsigned);
316void set_gpiop_dir(unsigned short, unsigned short); 316void set_gpiop_dir(unsigned, unsigned short);
317void set_gpiop_inen(unsigned short, unsigned short); 317void set_gpiop_inen(unsigned, unsigned short);
318void set_gpiop_polar(unsigned short, unsigned short); 318void set_gpiop_polar(unsigned, unsigned short);
319void set_gpiop_edge(unsigned short, unsigned short); 319void set_gpiop_edge(unsigned, unsigned short);
320void set_gpiop_both(unsigned short, unsigned short); 320void set_gpiop_both(unsigned, unsigned short);
321void set_gpiop_data(unsigned short, unsigned short); 321void set_gpiop_data(unsigned, unsigned short);
322void set_gpiop_maska(unsigned short, unsigned short); 322void set_gpiop_maska(unsigned, unsigned short);
323void set_gpiop_maskb(unsigned short, unsigned short); 323void set_gpiop_maskb(unsigned, unsigned short);
324unsigned short get_gpio_dir(unsigned short); 324unsigned short get_gpio_dir(unsigned);
325unsigned short get_gpio_inen(unsigned short); 325unsigned short get_gpio_inen(unsigned);
326unsigned short get_gpio_polar(unsigned short); 326unsigned short get_gpio_polar(unsigned);
327unsigned short get_gpio_edge(unsigned short); 327unsigned short get_gpio_edge(unsigned);
328unsigned short get_gpio_both(unsigned short); 328unsigned short get_gpio_both(unsigned);
329unsigned short get_gpio_maska(unsigned short); 329unsigned short get_gpio_maska(unsigned);
330unsigned short get_gpio_maskb(unsigned short); 330unsigned short get_gpio_maskb(unsigned);
331unsigned short get_gpio_data(unsigned short); 331unsigned short get_gpio_data(unsigned);
332unsigned short get_gpiop_dir(unsigned short); 332unsigned short get_gpiop_dir(unsigned);
333unsigned short get_gpiop_inen(unsigned short); 333unsigned short get_gpiop_inen(unsigned);
334unsigned short get_gpiop_polar(unsigned short); 334unsigned short get_gpiop_polar(unsigned);
335unsigned short get_gpiop_edge(unsigned short); 335unsigned short get_gpiop_edge(unsigned);
336unsigned short get_gpiop_both(unsigned short); 336unsigned short get_gpiop_both(unsigned);
337unsigned short get_gpiop_maska(unsigned short); 337unsigned short get_gpiop_maska(unsigned);
338unsigned short get_gpiop_maskb(unsigned short); 338unsigned short get_gpiop_maskb(unsigned);
339unsigned short get_gpiop_data(unsigned short); 339unsigned short get_gpiop_data(unsigned);
340 340
341struct gpio_port_t { 341struct gpio_port_t {
342 unsigned short data; 342 unsigned short data;
@@ -382,8 +382,8 @@ struct gpio_port_t {
382#define PM_WAKE_LOW 0x8 382#define PM_WAKE_LOW 0x8
383#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) 383#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
384 384
385int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type); 385int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
386void gpio_pm_wakeup_free(unsigned short gpio); 386void gpio_pm_wakeup_free(unsigned gpio);
387unsigned int gpio_pm_setup(void); 387unsigned int gpio_pm_setup(void);
388void gpio_pm_restore(void); 388void gpio_pm_restore(void);
389 389
@@ -426,19 +426,19 @@ struct gpio_port_s {
426* MODIFICATION HISTORY : 426* MODIFICATION HISTORY :
427**************************************************************/ 427**************************************************************/
428 428
429int gpio_request(unsigned short, const char *); 429int gpio_request(unsigned, const char *);
430void gpio_free(unsigned short); 430void gpio_free(unsigned);
431 431
432void gpio_set_value(unsigned short gpio, unsigned short arg); 432void gpio_set_value(unsigned gpio, int arg);
433unsigned short gpio_get_value(unsigned short gpio); 433int gpio_get_value(unsigned gpio);
434 434
435#ifndef BF548_FAMILY 435#ifndef BF548_FAMILY
436#define gpio_get_value(gpio) get_gpio_data(gpio) 436#define gpio_get_value(gpio) get_gpio_data(gpio)
437#define gpio_set_value(gpio, value) set_gpio_data(gpio, value) 437#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
438#endif 438#endif
439 439
440void gpio_direction_input(unsigned short gpio); 440int gpio_direction_input(unsigned gpio);
441void gpio_direction_output(unsigned short gpio); 441int gpio_direction_output(unsigned gpio, int value);
442 442
443#include <asm-generic/gpio.h> /* cansleep wrappers */ 443#include <asm-generic/gpio.h> /* cansleep wrappers */
444#include <asm/irq.h> 444#include <asm/irq.h>
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index 0b867e6a76c4..15dbc21eed8b 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
146 146
147 if (uart->rts_pin >= 0) { 147 if (uart->rts_pin >= 0) {
148 gpio_request(uart->rts_pin, DRIVER_NAME); 148 gpio_request(uart->rts_pin, DRIVER_NAME);
149 gpio_direction_output(uart->rts_pin); 149 gpio_direction_output(uart->rts_pin, 0);
150 } 150 }
151#endif 151#endif
152} 152}
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
index dcf001adc63c..ae4d205bfcf5 100644
--- a/include/asm-blackfin/mach-bf527/portmux.h
+++ b/include/asm-blackfin/mach-bf527/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 6#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 7#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) 8#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index f36ff5af1b91..98209d40abba 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,9 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List 10 * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
12 * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
13 */ 11 */
14 12
15#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
17 15
18/* We do not support 0.1 or 0.2 silicon - sorry */ 16/* We do not support 0.1 or 0.2 silicon - sorry */
19#if __SILICON_REVISION__ < 3 17#if __SILICON_REVISION__ < 3
20# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 18# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
21#endif 19#endif
22 20
23#if defined(__ADSPBF531__) 21#if defined(__ADSPBF531__)
@@ -251,6 +249,12 @@
251#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 249#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
252/* Internal Voltage Regulator may not start up */ 250/* Internal Voltage Regulator may not start up */
253#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 251#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
252/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
253#define ANOMALY_05000357 (1)
254/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
255#define ANOMALY_05000366 (1)
256/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
257#define ANOMALY_05000371 (1)
254 258
255/* Anomalies that don't exist on this proc */ 259/* Anomalies that don't exist on this proc */
256#define ANOMALY_05000266 (0) 260#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 69b9f8e120e9..7871d4313f49 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
111 } 111 }
112 if (uart->rts_pin >= 0) { 112 if (uart->rts_pin >= 0) {
113 gpio_request(uart->rts_pin, DRIVER_NAME); 113 gpio_request(uart->rts_pin, DRIVER_NAME);
114 gpio_direction_input(uart->rts_pin); 114 gpio_direction_input(uart->rts_pin, 0);
115 } 115 }
116#endif 116#endif
117} 117}
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
index 137f4884acfe..685a2651dcda 100644
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_PPI0_CLK (P_DONTCARE) 6#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE) 7#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE) 8#define P_PPI0_FS2 (P_DONTCARE)
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 2b66ecf489f7..746a794b3119 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,9 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
13 */ 11 */
14 12
15#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
17 15
18/* We do not support 0.1 silicon - sorry */ 16/* We do not support 0.1 silicon - sorry */
19#if __SILICON_REVISION__ < 2 17#if __SILICON_REVISION__ < 2
20# error Kernel will not work on BF537 silicon version 0.0 or 0.1 18# error will not work on BF537 silicon version 0.0 or 0.1
21#endif 19#endif
22 20
23#if defined(__ADSPBF534__) 21#if defined(__ADSPBF534__)
@@ -44,6 +42,8 @@
44#define ANOMALY_05000122 (1) 42#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) 44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
46#define ANOMALY_05000167 (1)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ 47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1) 48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */ 49/* Instruction Cache Is Not Functional */
@@ -130,6 +130,12 @@
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) 130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ 131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1) 132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
136#define ANOMALY_05000357 (1)
137/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
138#define ANOMALY_05000359 (1)
133 139
134/* Anomalies that don't exist on this proc */ 140/* Anomalies that don't exist on this proc */
135#define ANOMALY_05000125 (0) 141#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 6fb328f5186a..86e45c379838 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
146 146
147 if (uart->rts_pin >= 0) { 147 if (uart->rts_pin >= 0) {
148 gpio_request(uart->rts_pin, DRIVER_NAME); 148 gpio_request(uart->rts_pin, DRIVER_NAME);
149 gpio_direction_output(uart->rts_pin); 149 gpio_direction_output(uart->rts_pin, 0);
150 } 150 }
151#endif 151#endif
152} 152}
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
index 5a3f7d3bf73d..78fee6e0f237 100644
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
5
4#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 6#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 7#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) 8#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index c5b63759cdee..850dc12eb7f2 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List 10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -26,47 +26,59 @@
26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
27#define ANOMALY_05000272 (1) 27#define ANOMALY_05000272 (1)
28/* False Hardware Error Exception when ISR context is not restored */ 28/* False Hardware Error Exception when ISR context is not restored */
29#define ANOMALY_05000281 (1) 29#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (1) 31#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1) 33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
35#define ANOMALY_05000312 (1) 35#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
36/* TWI Slave Boot Mode Is Not Functional */ 36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (1) 37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */ 38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (1) 39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (1) 41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */ 42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (1) 43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */ 44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (1) 45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */ 46/* Host DMA Boot Mode Is Not Functional */
47#define ANOMALY_05000330 (1) 47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ 48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (1) 49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
50/* Inadequate Rotary Debounce Logic Duration */ 50/* Inadequate Rotary Debounce Logic Duration */
51#define ANOMALY_05000335 (1) 51#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ 52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
53#define ANOMALY_05000336 (1) 53#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
55#define ANOMALY_05000337 (1) 55#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ 56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (1) 57#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ 58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (1) 59#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ 60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (1) 61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */ 62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (1) 63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ 64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (1) 65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */ 66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (1) 67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */ 68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (1) 69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1)
78/* Mobile DDR Operation Not Functional */
79#define ANOMALY_05000377 (1)
80/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
81#define ANOMALY_05000378 (1)
70 82
71/* Anomalies that don't exist on this proc */ 83/* Anomalies that don't exist on this proc */
72#define ANOMALY_05000125 (0) 84#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index f21a1620e6bd..3770aa38ee9f 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
186 186
187 if (uart->rts_pin >= 0) { 187 if (uart->rts_pin >= 0) {
188 gpio_request(uart->rts_pin, DRIVER_NAME); 188 gpio_request(uart->rts_pin, DRIVER_NAME);
189 gpio_direction_output(uart->rts_pin); 189 gpio_direction_output(uart->rts_pin, 0);
190 } 190 }
191#endif 191#endif
192} 192}
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index aefab3f618c1..19ddcd83c71f 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) 244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) 245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246 246
247#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
248#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
249#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
250#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
251#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
252#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
253#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
254#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
255#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
256#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
257#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
258#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
259#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
260#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
261#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
262#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
263#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
264#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
265#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
266#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
267#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
268#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
269#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
270#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
271#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
272#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
273#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
274#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
275#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
276#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
277#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
278#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
279
280/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ 247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
281 248
282/* SPORT1 Registers */ 249/* SPORT1 Registers */
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index 32d07130200c..a7c809f29ede 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -432,8 +432,8 @@
432 432
433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
435#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 435#define CMD_TIME_OUT 0x4 /* CMD Time Out */
436#define DAT_TIMEOUT 0x8 /* Data Time Out */ 436#define DAT_TIME_OUT 0x8 /* Data Time Out */
437#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
438#define RX_OVERRUN 0x20 /* Receive Overrun */ 438#define RX_OVERRUN 0x20 /* Receive Overrun */
439#define CMD_RESP_END 0x40 /* CMD Response End */ 439#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index ecbca952985c..e46f56891e6a 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1095,8 +1095,8 @@
1095 1095
1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1098#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 1098#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1099#define DAT_TIMEOUT 0x8 /* Data Time Out */ 1099#define DAT_TIME_OUT 0x8 /* Data Time Out */
1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1101#define RX_OVERRUN 0x20 /* Receive Overrun */ 1101#define RX_OVERRUN 0x20 /* Receive Overrun */
1102#define CMD_RESP_END 0x40 /* CMD Response End */ 1102#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 319a48590c9c..08f90c21fe8a 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1772,17 +1772,36 @@
1772#define TRP 0x3c0000 /* Pre charge-to-active command period */ 1772#define TRP 0x3c0000 /* Pre charge-to-active command period */
1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */ 1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1774#define TRC 0x3c000000 /* Active-to-active time */ 1774#define TRC 0x3c000000 /* Active-to-active time */
1775#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
1776#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
1777#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
1778#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
1779#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
1775 1780
1776/* Bit masks for EBIU_DDRCTL1 */ 1781/* Bit masks for EBIU_DDRCTL1 */
1777 1782
1778#define TRCD 0xf /* Active-to-Read/write delay */ 1783#define TRCD 0xf /* Active-to-Read/write delay */
1779#define MRD 0xf0 /* Mode register set to active */ 1784#define TMRD 0xf0 /* Mode register set to active */
1780#define TWR 0x300 /* Write Recovery time */ 1785#define TWR 0x300 /* Write Recovery time */
1781#define DDRDATWIDTH 0x3000 /* DDR data width */ 1786#define DDRDATWIDTH 0x3000 /* DDR data width */
1782#define EXTBANKS 0xc000 /* External banks */ 1787#define EXTBANKS 0xc000 /* External banks */
1783#define DDRDEVWIDTH 0x30000 /* DDR device width */ 1788#define DDRDEVWIDTH 0x30000 /* DDR device width */
1784#define DDRDEVSIZE 0xc0000 /* DDR device size */ 1789#define DDRDEVSIZE 0xc0000 /* DDR device size */
1785#define TWWTR 0xf0000000 /* Write-to-read delay */ 1790#define TWTR 0xf0000000 /* Write-to-read delay */
1791#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
1792#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
1793#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
1794#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
1795#define DDR_DATWIDTH 0x2000 /* DDR data width */
1796#define EXTBANK_1 0 /* 1 external bank */
1797#define EXTBANK_2 0x4000 /* 2 external banks */
1798#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
1799#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
1800#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
1801#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
1802#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
1803#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
1804#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
1786 1805
1787/* Bit masks for EBIU_DDRCTL2 */ 1806/* Bit masks for EBIU_DDRCTL2 */
1788 1807
@@ -1790,6 +1809,10 @@
1790#define CASLATENCY 0x70 /* CAS latency */ 1809#define CASLATENCY 0x70 /* CAS latency */
1791#define DLLRESET 0x100 /* DLL Reset */ 1810#define DLLRESET 0x100 /* DLL Reset */
1792#define REGE 0x1000 /* Register mode enable */ 1811#define REGE 0x1000 /* Register mode enable */
1812#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
1813#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
1814#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
1815#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
1793 1816
1794/* Bit masks for EBIU_DDRCTL3 */ 1817/* Bit masks for EBIU_DDRCTL3 */
1795 1818
@@ -2257,6 +2280,10 @@
2257 2280
2258#define CSEL 0x30 /* Core Select */ 2281#define CSEL 0x30 /* Core Select */
2259#define SSEL 0xf /* System Select */ 2282#define SSEL 0xf /* System Select */
2283#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2284#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2285#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2286#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2260 2287
2261/* Bit masks for PLL_CTL */ 2288/* Bit masks for PLL_CTL */
2262 2289
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 9fb7bc5399a8..c34507a3f1df 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@ Events (highest priority) EMU 0
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ 88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ 89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ 90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ 91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ 92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ 93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ 94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@@ -406,7 +406,7 @@ Events (highest priority) EMU 0
406#define IRQ_PINT1_POS 16 406#define IRQ_PINT1_POS 16
407#define IRQ_MDMAS0_POS 20 407#define IRQ_MDMAS0_POS 20
408#define IRQ_MDMAS1_POS 24 408#define IRQ_MDMAS1_POS 24
409#define IRQ_WATCHDOG_POS 28 409#define IRQ_WATCH_POS 28
410 410
411/* IAR3 BIT FIELDS */ 411/* IAR3 BIT FIELDS */
412#define IRQ_DMAC1_ERR_POS 0 412#define IRQ_DMAC1_ERR_POS 0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e973d7..befc2903d5a5 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -28,8 +28,68 @@
28 * If not, write to the Free Software Foundation, 28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32
33#if (CONFIG_MEM_MT46V32M16_6T)
34#define DDR_SIZE DEVSZ_512
35#define DDR_WIDTH DEVWD_16
36
37#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
38#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
39#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
40#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
41#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
42
43#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
44#define DDR_tWTR DDR_TWTR(1)
45#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
46#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
47#endif
48
49#if (CONFIG_MEM_MT46V32M16_5B)
50#define DDR_SIZE DEVSZ_512
51#define DDR_WIDTH DEVWD_16
52
53#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
54#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
55#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
56#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
57#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
58
59#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
60#define DDR_tWTR DDR_TWTR(2)
61#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
62#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
63#endif
64
65#if (CONFIG_MEM_GENERIC_BOARD)
66#define DDR_SIZE DEVSZ_512
67#define DDR_WIDTH DEVWD_16
68
69#define DDR_tRCD DDR_TRCD(3)
70#define DDR_tWTR DDR_TWTR(2)
71#define DDR_tWR DDR_TWR(2)
72#define DDR_tMRD DDR_TMRD(2)
73#define DDR_tRP DDR_TRP(3)
74#define DDR_tRAS DDR_TRAS(7)
75#define DDR_tRC DDR_TRC(10)
76#define DDR_tRFC DDR_TRFC(12)
77#define DDR_tREFI DDR_TREFI(1288)
78#endif
79
80#if (CONFIG_SCLK_HZ <= 133333333)
81#define DDR_CL CL_2
82#elif (CONFIG_SCLK_HZ <= 166666666)
83#define DDR_CL CL_2_5
84#else
85#define DDR_CL CL_3
86#endif
87
88#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
89#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
90 | DDR_tMRD | DDR_tWR | DDR_tRCD)
91#define mem_DDRCTL2 DDR_CL
31 92
32#if (CONFIG_MEM_MT46V32M16)
33 93
34#if defined CONFIG_CLKIN_HALF 94#if defined CONFIG_CLKIN_HALF
35#define CLKIN_HALF 1 95#define CLKIN_HALF 1
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
index 6b485120015f..8177a567dcdb 100644
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 6#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
5#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 7#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
6#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) 8#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index bed956456884..0c1d46193939 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List 10 * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -15,7 +15,7 @@
15 15
16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ 16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif 19#endif
20 20
21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
@@ -208,6 +208,8 @@
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) 208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) 210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
211/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
212#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
213/* False Hardware Error Exception When ISR Context Is Not Restored */ 215/* False Hardware Error Exception When ISR Context Is Not Restored */
@@ -246,6 +248,18 @@
246#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) 248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
247/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ 249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1)
259/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
260#define ANOMALY_05000366 (1)
261/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
262#define ANOMALY_05000371 (1)
249 263
250/* Anomalies that don't exist on this proc */ 264/* Anomalies that don't exist on this proc */
251#define ANOMALY_05000158 (0) 265#define ANOMALY_05000158 (0)
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 69b9f8e120e9..7871d4313f49 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
111 } 111 }
112 if (uart->rts_pin >= 0) { 112 if (uart->rts_pin >= 0) {
113 gpio_request(uart->rts_pin, DRIVER_NAME); 113 gpio_request(uart->rts_pin, DRIVER_NAME);
114 gpio_direction_input(uart->rts_pin); 114 gpio_direction_input(uart->rts_pin, 0);
115 } 115 }
116#endif 116#endif
117} 117}
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
index 132ad31665e3..a6ee8206efb6 100644
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_PPI0_CLK (P_DONTCARE) 6#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE) 7#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE) 8#define P_PPI0_FS2 (P_DONTCARE)
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
index 11d52f1167d0..757e43906ed4 100644
--- a/include/asm-blackfin/mmu.h
+++ b/include/asm-blackfin/mmu.h
@@ -24,7 +24,9 @@ typedef struct {
24 unsigned long exec_fdpic_loadmap; 24 unsigned long exec_fdpic_loadmap;
25 unsigned long interp_fdpic_loadmap; 25 unsigned long interp_fdpic_loadmap;
26#endif 26#endif
27 27#ifdef CONFIG_MPU
28 unsigned long *page_rwx_mask;
29#endif
28} mm_context_t; 30} mm_context_t;
29 31
30#endif 32#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
index c5c71a6aaf19..b5eb67596ad5 100644
--- a/include/asm-blackfin/mmu_context.h
+++ b/include/asm-blackfin/mmu_context.h
@@ -30,9 +30,12 @@
30#ifndef __BLACKFIN_MMU_CONTEXT_H__ 30#ifndef __BLACKFIN_MMU_CONTEXT_H__
31#define __BLACKFIN_MMU_CONTEXT_H__ 31#define __BLACKFIN_MMU_CONTEXT_H__
32 32
33#include <linux/gfp.h>
34#include <linux/sched.h>
33#include <asm/setup.h> 35#include <asm/setup.h>
34#include <asm/page.h> 36#include <asm/page.h>
35#include <asm/pgalloc.h> 37#include <asm/pgalloc.h>
38#include <asm/cplbinit.h>
36 39
37extern void *current_l1_stack_save; 40extern void *current_l1_stack_save;
38extern int nr_l1stack_tasks; 41extern int nr_l1stack_tasks;
@@ -50,6 +53,12 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
50static inline int 53static inline int
51init_new_context(struct task_struct *tsk, struct mm_struct *mm) 54init_new_context(struct task_struct *tsk, struct mm_struct *mm)
52{ 55{
56#ifdef CONFIG_MPU
57 unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
58 mm->context.page_rwx_mask = (unsigned long *)p;
59 memset(mm->context.page_rwx_mask, 0,
60 page_mask_nelts * 3 * sizeof(long));
61#endif
53 return 0; 62 return 0;
54} 63}
55 64
@@ -73,6 +82,11 @@ static inline void destroy_context(struct mm_struct *mm)
73 sram_free(tmp->addr); 82 sram_free(tmp->addr);
74 kfree(tmp); 83 kfree(tmp);
75 } 84 }
85#ifdef CONFIG_MPU
86 if (current_rwx_mask == mm->context.page_rwx_mask)
87 current_rwx_mask = NULL;
88 free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
89#endif
76} 90}
77 91
78static inline unsigned long 92static inline unsigned long
@@ -106,9 +120,21 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
106 120
107#define deactivate_mm(tsk,mm) do { } while (0) 121#define deactivate_mm(tsk,mm) do { } while (0)
108 122
109static inline void activate_mm(struct mm_struct *prev_mm, 123#define activate_mm(prev, next) switch_mm(prev, next, NULL)
110 struct mm_struct *next_mm) 124
125static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
126 struct task_struct *tsk)
111{ 127{
128 if (prev_mm == next_mm)
129 return;
130#ifdef CONFIG_MPU
131 if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
132 flush_switched_cplbs();
133 set_mask_dcplbs(next_mm->context.page_rwx_mask);
134 }
135#endif
136
137 /* L1 stack switching. */
112 if (!next_mm->context.l1_stack_save) 138 if (!next_mm->context.l1_stack_save)
113 return; 139 return;
114 if (next_mm->context.l1_stack_save == current_l1_stack_save) 140 if (next_mm->context.l1_stack_save == current_l1_stack_save)
@@ -120,10 +146,36 @@ static inline void activate_mm(struct mm_struct *prev_mm,
120 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); 146 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
121} 147}
122 148
123static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 149#ifdef CONFIG_MPU
124 struct task_struct *tsk) 150static inline void protect_page(struct mm_struct *mm, unsigned long addr,
151 unsigned long flags)
152{
153 unsigned long *mask = mm->context.page_rwx_mask;
154 unsigned long page = addr >> 12;
155 unsigned long idx = page >> 5;
156 unsigned long bit = 1 << (page & 31);
157
158 if (flags & VM_MAYREAD)
159 mask[idx] |= bit;
160 else
161 mask[idx] &= ~bit;
162 mask += page_mask_nelts;
163 if (flags & VM_MAYWRITE)
164 mask[idx] |= bit;
165 else
166 mask[idx] &= ~bit;
167 mask += page_mask_nelts;
168 if (flags & VM_MAYEXEC)
169 mask[idx] |= bit;
170 else
171 mask[idx] &= ~bit;
172}
173
174static inline void update_protections(struct mm_struct *mm)
125{ 175{
126 activate_mm(prev, next); 176 flush_switched_cplbs();
177 set_mask_dcplbs(mm->context.page_rwx_mask);
127} 178}
179#endif
128 180
129#endif 181#endif
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index ee1cbf73a9ab..f0e5f940d9ca 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -45,6 +45,10 @@
45#define VEC_CPLB_I_M (44) 45#define VEC_CPLB_I_M (44)
46#define VEC_CPLB_I_MHIT (45) 46#define VEC_CPLB_I_MHIT (45)
47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ 47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
48/* The hardware reserves (63) for future use - we use it to tell our
49 * normal exception handling code we have a hardware error
50 */
51#define VEC_HWERR (63)
48 52
49#ifndef __ASSEMBLY__ 53#ifndef __ASSEMBLY__
50 54
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 2233f8f9314d..22a410b8003b 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -31,7 +31,7 @@ static inline void set_fs(mm_segment_t fs)
31#define VERIFY_READ 0 31#define VERIFY_READ 0
32#define VERIFY_WRITE 1 32#define VERIFY_WRITE 1
33 33
34#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) 34#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
35 35
36static inline int is_in_rom(unsigned long addr) 36static inline int is_in_rom(unsigned long addr)
37{ 37{
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index 07ffe8b718c5..e98167358d26 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -369,8 +369,9 @@
369#define __NR_set_robust_list 354 369#define __NR_set_robust_list 354
370#define __NR_get_robust_list 355 370#define __NR_get_robust_list 355
371#define __NR_fallocate 356 371#define __NR_fallocate 356
372#define __NR_semtimedop 357
372 373
373#define __NR_syscall 357 374#define __NR_syscall 358
374#define NR_syscalls __NR_syscall 375#define NR_syscalls __NR_syscall
375 376
376/* Old optional stuff no one actually uses */ 377/* Old optional stuff no one actually uses */