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-rw-r--r--arch/arm/mach-pxa/cpu-pxa.c1
-rw-r--r--arch/arm/mach-pxa/lpd270.c1
-rw-r--r--arch/arm/mach-pxa/lubbock.c1
-rw-r--r--arch/arm/mach-pxa/mainstone.c1
-rw-r--r--arch/arm/mach-pxa/pxa27x.c1
-rw-r--r--arch/arm/mach-pxa/sleep.S1
-rw-r--r--drivers/pcmcia/pxa2xx_base.c1
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h63
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h84
9 files changed, 91 insertions, 63 deletions
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 18d042bdf243..cbc583beedc8 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -39,6 +39,7 @@
39 39
40#include <asm/hardware.h> 40#include <asm/hardware.h>
41#include <asm/arch/pxa-regs.h> 41#include <asm/arch/pxa-regs.h>
42#include <asm/arch/pxa2xx-regs.h>
42 43
43#ifdef DEBUG 44#ifdef DEBUG
44static unsigned int freq_debug; 45static unsigned int freq_debug;
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 78ebad063cba..afa62ffe3ad5 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -38,6 +38,7 @@
38#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
39 39
40#include <asm/arch/pxa-regs.h> 40#include <asm/arch/pxa-regs.h>
41#include <asm/arch/pxa2xx-regs.h>
41#include <asm/arch/lpd270.h> 42#include <asm/arch/lpd270.h>
42#include <asm/arch/audio.h> 43#include <asm/arch/audio.h>
43#include <asm/arch/pxafb.h> 44#include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 1b9290c0ed5e..a75594bf68b5 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -41,6 +41,7 @@
41#include <asm/hardware/sa1111.h> 41#include <asm/hardware/sa1111.h>
42 42
43#include <asm/arch/pxa-regs.h> 43#include <asm/arch/pxa-regs.h>
44#include <asm/arch/pxa2xx-regs.h>
44#include <asm/arch/lubbock.h> 45#include <asm/arch/lubbock.h>
45#include <asm/arch/udc.h> 46#include <asm/arch/udc.h>
46#include <asm/arch/irda.h> 47#include <asm/arch/irda.h>
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 237459bf67c6..06e13608a2c9 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -39,6 +39,7 @@
39#include <asm/mach/flash.h> 39#include <asm/mach/flash.h>
40 40
41#include <asm/arch/pxa-regs.h> 41#include <asm/arch/pxa-regs.h>
42#include <asm/arch/pxa2xx-regs.h>
42#include <asm/arch/mainstone.h> 43#include <asm/arch/mainstone.h>
43#include <asm/arch/audio.h> 44#include <asm/arch/audio.h>
44#include <asm/arch/pxafb.h> 45#include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index ec7597b1cb54..b9fa5ec0a954 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -21,6 +21,7 @@
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <asm/arch/irqs.h> 22#include <asm/arch/irqs.h>
23#include <asm/arch/pxa-regs.h> 23#include <asm/arch/pxa-regs.h>
24#include <asm/arch/pxa2xx-regs.h>
24#include <asm/arch/ohci.h> 25#include <asm/arch/ohci.h>
25#include <asm/arch/pm.h> 26#include <asm/arch/pm.h>
26#include <asm/arch/dma.h> 27#include <asm/arch/dma.h>
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index d0447723b73a..f33d0c4a96d6 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -16,6 +16,7 @@
16#include <asm/hardware.h> 16#include <asm/hardware.h>
17 17
18#include <asm/arch/pxa-regs.h> 18#include <asm/arch/pxa-regs.h>
19#include <asm/arch/pxa2xx-regs.h>
19 20
20#define MDREFR_KDIV 0x200a4000 // all banks 21#define MDREFR_KDIV 0x200a4000 // all banks
21#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 22#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index 874923fcb2f9..e439044d88f2 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -29,6 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32 33
33#include <pcmcia/cs_types.h> 34#include <pcmcia/cs_types.h>
34#include <pcmcia/ss.h> 35#include <pcmcia/ss.h>
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index f7809ea77396..442494d71f12 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1848,71 +1848,8 @@
1848 1848
1849#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 1849#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1850 1850
1851/*
1852 * Memory controller
1853 */
1854
1855#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
1856#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
1857#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
1858#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
1859#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
1860#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
1861#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
1862#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
1863#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
1864#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
1865#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
1866#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
1867#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
1868#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
1869#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
1870#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
1871#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
1872
1873/*
1874 * More handy macros for PCMCIA
1875 *
1876 * Arg is socket number
1877 */
1878#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
1879#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
1880#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
1881
1882/* MECR register defines */
1883#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
1884#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
1885
1886#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
1887#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
1888#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
1889#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
1890#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
1891#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
1892#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
1893#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
1894#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
1895#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
1896#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
1897#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
1898#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
1899#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
1900
1901
1902#ifdef CONFIG_PXA27x 1851#ifdef CONFIG_PXA27x
1903 1852
1904#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
1905
1906#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
1907#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
1908#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
1909#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
1910#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
1911#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
1912#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
1913#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
1914#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
1915
1916/* 1853/*
1917 * Keypad 1854 * Keypad
1918 */ 1855 */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
new file mode 100644
index 000000000000..9553b54fa5bc
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -0,0 +1,84 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
3 *
4 * Taken from pxa-regs.h by Russell King
5 *
6 * Author: Nicolas Pitre
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H
16
17/*
18 * Memory controller
19 */
20
21#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
22#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
23#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
24#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
25#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
26#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
27#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
28#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
29#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
30#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
31#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
32#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
33#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
34#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
35#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
36#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
37#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
38
39/*
40 * More handy macros for PCMCIA
41 *
42 * Arg is socket number
43 */
44#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
45#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
46#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
47
48/* MECR register defines */
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
55#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
56#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
57#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
58#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
59#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
60#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
61#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
62#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
63#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
64#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
65#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
66
67
68#ifdef CONFIG_PXA27x
69
70#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
71
72#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
73#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
74#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
75#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
76#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
77#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
78#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
79#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
80#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
81
82#endif
83
84#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 06:51:46 -0500