diff options
-rw-r--r-- | arch/mips/txx9/generic/irq_tx4927.c | 11 | ||||
-rw-r--r-- | arch/mips/txx9/generic/irq_tx4938.c | 11 | ||||
-rw-r--r-- | include/asm-mips/txx9/tx4927.h | 11 |
3 files changed, 33 insertions, 0 deletions
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index cbea1fdde82b..ad2870def8f1 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c | |||
@@ -30,8 +30,19 @@ | |||
30 | 30 | ||
31 | void __init tx4927_irq_init(void) | 31 | void __init tx4927_irq_init(void) |
32 | { | 32 | { |
33 | int i; | ||
34 | |||
33 | mips_cpu_irq_init(); | 35 | mips_cpu_irq_init(); |
34 | txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); | 36 | txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); |
35 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, | 37 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, |
36 | handle_simple_irq); | 38 | handle_simple_irq); |
39 | /* raise priority for errors, timers, SIO */ | ||
40 | txx9_irq_set_pri(TX4927_IR_ECCERR, 7); | ||
41 | txx9_irq_set_pri(TX4927_IR_WTOERR, 7); | ||
42 | txx9_irq_set_pri(TX4927_IR_PCIERR, 7); | ||
43 | txx9_irq_set_pri(TX4927_IR_PCIPME, 7); | ||
44 | for (i = 0; i < TX4927_NUM_IR_TMR; i++) | ||
45 | txx9_irq_set_pri(TX4927_IR_TMR(i), 6); | ||
46 | for (i = 0; i < TX4927_NUM_IR_SIO; i++) | ||
47 | txx9_irq_set_pri(TX4927_IR_SIO(i), 5); | ||
37 | } | 48 | } |
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index 6eac684bf190..025ae11359a8 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c | |||
@@ -18,8 +18,19 @@ | |||
18 | 18 | ||
19 | void __init tx4938_irq_init(void) | 19 | void __init tx4938_irq_init(void) |
20 | { | 20 | { |
21 | int i; | ||
22 | |||
21 | mips_cpu_irq_init(); | 23 | mips_cpu_irq_init(); |
22 | txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); | 24 | txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); |
23 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, | 25 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, |
24 | handle_simple_irq); | 26 | handle_simple_irq); |
27 | /* raise priority for errors, timers, SIO */ | ||
28 | txx9_irq_set_pri(TX4938_IR_ECCERR, 7); | ||
29 | txx9_irq_set_pri(TX4938_IR_WTOERR, 7); | ||
30 | txx9_irq_set_pri(TX4938_IR_PCIERR, 7); | ||
31 | txx9_irq_set_pri(TX4938_IR_PCIPME, 7); | ||
32 | for (i = 0; i < TX4938_NUM_IR_TMR; i++) | ||
33 | txx9_irq_set_pri(TX4938_IR_TMR(i), 6); | ||
34 | for (i = 0; i < TX4938_NUM_IR_SIO; i++) | ||
35 | txx9_irq_set_pri(TX4938_IR_SIO(i), 5); | ||
25 | } | 36 | } |
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index 36a9241b0cac..7d813f1cb98d 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h | |||
@@ -50,12 +50,23 @@ | |||
50 | #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) | 50 | #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) |
51 | #define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) | 51 | #define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) |
52 | 52 | ||
53 | #define TX4927_IR_ECCERR 0 | ||
54 | #define TX4927_IR_WTOERR 1 | ||
55 | #define TX4927_NUM_IR_INT 6 | ||
53 | #define TX4927_IR_INT(n) (2 + (n)) | 56 | #define TX4927_IR_INT(n) (2 + (n)) |
57 | #define TX4927_NUM_IR_SIO 2 | ||
54 | #define TX4927_IR_SIO(n) (8 + (n)) | 58 | #define TX4927_IR_SIO(n) (8 + (n)) |
59 | #define TX4927_NUM_IR_DMA 4 | ||
60 | #define TX4927_IR_DMA(n) (10 + (n)) | ||
61 | #define TX4927_IR_PIO 14 | ||
62 | #define TX4927_IR_PDMAC 15 | ||
55 | #define TX4927_IR_PCIC 16 | 63 | #define TX4927_IR_PCIC 16 |
56 | #define TX4927_NUM_IR_TMR 3 | 64 | #define TX4927_NUM_IR_TMR 3 |
57 | #define TX4927_IR_TMR(n) (17 + (n)) | 65 | #define TX4927_IR_TMR(n) (17 + (n)) |
58 | #define TX4927_IR_PCIERR 22 | 66 | #define TX4927_IR_PCIERR 22 |
67 | #define TX4927_IR_PCIPME 23 | ||
68 | #define TX4927_IR_ACLC 24 | ||
69 | #define TX4927_IR_ACLCPME 25 | ||
59 | #define TX4927_NUM_IR 32 | 70 | #define TX4927_NUM_IR 32 |
60 | 71 | ||
61 | #define TX4927_IRC_INT 2 /* IP[2] in Status register */ | 72 | #define TX4927_IRC_INT 2 /* IP[2] in Status register */ |