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-rw-r--r--arch/arm/mach-omap2/Makefile36
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c1
-rw-r--r--arch/arm/mach-omap2/clock.c12
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock34xx.c260
-rw-r--r--arch/arm/mach-omap2/clock34xx.h27
-rw-r--r--arch/arm/mach-omap2/clock3517.c124
-rw-r--r--arch/arm/mach-omap2/clock3517.h14
-rw-r--r--arch/arm/mach-omap2/clock36xx.c72
-rw-r--r--arch/arm/mach-omap2/clock36xx.h13
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c145
-rw-r--r--arch/arm/mach-omap2/clock3xxx.h21
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c (renamed from arch/arm/mach-omap2/clock34xx_data.c)16
-rw-r--r--arch/arm/mach-omap2/clock44xx.c19
-rw-r--r--arch/arm/mach-omap2/clock44xx.h6
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c12
-rw-r--r--arch/arm/mach-omap2/io.c2
17 files changed, 450 insertions, 332 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3ebd0b6525df..5f10d32f1184 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -7,22 +7,14 @@ obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
7 7
8omap-2-3-common = irq.o sdrc.o omap_hwmod.o \ 8omap-2-3-common = irq.o sdrc.o omap_hwmod.o \
9 omap_hwmod_common_data.o 9 omap_hwmod_common_data.o
10omap-3-4-common = dpll3xxx.o
11prcm-common = prcm.o powerdomain.o 10prcm-common = prcm.o powerdomain.o
12clock-common = clock.o clock_common_data.o \ 11clock-common = clock.o clock_common_data.o \
13 clockdomain.o clkt_dpll.o \ 12 clockdomain.o clkt_dpll.o \
14 clkt_clksel.o 13 clkt_clksel.o
15clock-omap2xxx = clkt2xxx_dpllcore.o \ 14
16 clkt2xxx_virt_prcm_set.o \ 15obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common)
17 clkt2xxx_apll.o clkt2xxx_osc.o \ 16obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common)
18 clkt2xxx_sys.o 17obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common)
19clock-omap3xxx = clkt34xx_dpll3m2.o
20
21obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
22 $(clock-omap2xxx)
23obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
24 $(omap-3-4-common) $(clock-omap3xxx)
25obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common)
26 18
27obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 19obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
28 20
@@ -64,14 +56,24 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
64obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o 56obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
65 57
66# Clock framework 58# Clock framework
67obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o 59obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
60 clock2xxx_data.o clkt2xxx_sys.o \
61 clkt2xxx_dpllcore.o \
62 clkt2xxx_virt_prcm_set.o \
63 clkt2xxx_apll.o clkt2xxx_osc.o
64obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
65 clock34xx.o clkt34xx_dpll3m2.o \
66 clock3517.o clock36xx.o \
67 dpll3xxx.o clock3xxx_data.o
68obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
69 dpll3xxx.o
70
71# OMAP2 clock rate set data (old "OPP" data)
68obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o 72obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
69obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
70obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o 73obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
71obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o
72 74
73# EMU peripherals 75# EMU peripherals
74obj-$(CONFIG_OMAP3_EMU) += emu.o 76obj-$(CONFIG_OMAP3_EMU) += emu.o
75 77
76obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 78obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
77mailbox_mach-objs := mailbox.o 79mailbox_mach-objs := mailbox.o
@@ -127,7 +129,7 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
127 hsmmc.o 129 hsmmc.o
128obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o 130obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
129 131
130obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 132obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
131 133
132# Platform specific device init code 134# Platform specific device init code
133obj-y += usb-musb.o 135obj-y += usb-musb.o
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 8716a01d1f5b..b2b1e37bb6bb 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -26,6 +26,7 @@
26#include <plat/sdrc.h> 26#include <plat/sdrc.h>
27 27
28#include "clock.h" 28#include "clock.h"
29#include "clock3xxx.h"
29#include "clock34xx.h" 30#include "clock34xx.h"
30#include "sdrc.h" 31#include "sdrc.h"
31 32
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 9df5937999cb..82b17ef17dbe 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -336,6 +336,18 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
336 return omap2_clksel_set_parent(clk, new_parent); 336 return omap2_clksel_set_parent(clk, new_parent);
337} 337}
338 338
339/* OMAP3/4 non-CORE DPLL clkops */
340
341#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
342
343const struct clkops clkops_omap3_noncore_dpll_ops = {
344 .enable = omap3_noncore_dpll_enable,
345 .disable = omap3_noncore_dpll_disable,
346};
347
348#endif
349
350
339/*------------------------------------------------------------------------- 351/*-------------------------------------------------------------------------
340 * Omap2 clock reset and init functions 352 * Omap2 clock reset and init functions
341 *-------------------------------------------------------------------------*/ 353 *-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 0b0f52083121..f98dd0407e7e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -141,4 +141,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
141#define omap2_clk_exit_cpufreq_table 0 141#define omap2_clk_exit_cpufreq_table 0
142#endif 142#endif
143 143
144extern const struct clkops clkops_omap3_noncore_dpll_ops;
145
144#endif 146#endif
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 9039e8cbe487..6febd5f11e85 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -8,7 +8,8 @@
8 * Jouni Högander 8 * Jouni Högander
9 * 9 *
10 * Parts of this code are based on code written by 10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu 11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
12 * Russell King
12 * 13 *
13 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as 15 * it under the terms of the GNU General Public License version 2 as
@@ -17,42 +18,16 @@
17#undef DEBUG 18#undef DEBUG
18 19
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/clk.h> 21#include <linux/clk.h>
23#include <linux/io.h> 22#include <linux/io.h>
24#include <linux/err.h>
25 23
26#include <plat/cpu.h>
27#include <plat/clock.h> 24#include <plat/clock.h>
28 25
29#include "clock.h" 26#include "clock.h"
30#include "clock34xx.h" 27#include "clock34xx.h"
31#include "prm.h"
32#include "prm-regbits-34xx.h"
33#include "cm.h" 28#include "cm.h"
34#include "cm-regbits-34xx.h" 29#include "cm-regbits-34xx.h"
35 30
36/*
37 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
38 * that are sourced by DPLL5, and both of these require this clock
39 * to be at 120 MHz for proper operation.
40 */
41#define DPLL5_FREQ_FOR_USBHOST 120000000
42
43/*
44 * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
45 * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
46 * at an offset of 4 from ICK enable bit.
47 */
48#define AM35XX_IPSS_ICK_MASK 0xF
49#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
50#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
51#define AM35XX_IPSS_CLK_IDLEST_VAL 0
52
53/* needed by omap3_core_dpll_m2_set_rate() */
54struct clk *sdrc_ick_p, *arm_fck_p;
55
56/** 31/**
57 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI 32 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
58 * @clk: struct clk * being enabled 33 * @clk: struct clk * being enabled
@@ -149,234 +124,3 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
149 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, 124 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
150 .find_companion = omap2_clk_dflt_find_companion, 125 .find_companion = omap2_clk_dflt_find_companion,
151}; 126};
152
153/**
154 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
155 * from HSDivider PWRDN problem Implements Errata ID: i556.
156 * @clk: DPLL output struct clk
157 *
158 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
159 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
160 * valueafter their respective PWRDN bits are set. Any dummy write
161 * (Any other value different from the Read value) to the
162 * corresponding CM_CLKSEL register will refresh the dividers.
163 */
164static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
165{
166 u32 dummy_v, orig_v, clksel_shift;
167 int ret;
168
169 /* Clear PWRDN bit of HSDIVIDER */
170 ret = omap2_dflt_clk_enable(clk);
171
172 /* Restore the dividers */
173 if (!ret) {
174 clksel_shift = __ffs(clk->parent->clksel_mask);
175 orig_v = __raw_readl(clk->parent->clksel_reg);
176 dummy_v = orig_v;
177
178 /* Write any other value different from the Read value */
179 dummy_v ^= (1 << clksel_shift);
180 __raw_writel(dummy_v, clk->parent->clksel_reg);
181
182 /* Write the original divider */
183 __raw_writel(orig_v, clk->parent->clksel_reg);
184 }
185
186 return ret;
187}
188
189const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
190 .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
191 .disable = omap2_dflt_clk_disable,
192 .find_companion = omap2_clk_dflt_find_companion,
193 .find_idlest = omap2_clk_dflt_find_idlest,
194};
195
196const struct clkops omap3_clkops_noncore_dpll_ops = {
197 .enable = omap3_noncore_dpll_enable,
198 .disable = omap3_noncore_dpll_disable,
199};
200
201/**
202 * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
203 * @clk: struct clk * being enabled
204 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
205 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
206 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
207 *
208 * The interface clocks on AM35xx IPSS reflects the clock idle status
209 * in the enable register itsel at a bit offset of 4 from the enable
210 * bit. A value of 1 indicates that clock is enabled.
211 */
212static void am35xx_clk_find_idlest(struct clk *clk,
213 void __iomem **idlest_reg,
214 u8 *idlest_bit,
215 u8 *idlest_val)
216{
217 *idlest_reg = (__force void __iomem *)(clk->enable_reg);
218 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
219 *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
220}
221
222/**
223 * am35xx_clk_find_companion - find companion clock to @clk
224 * @clk: struct clk * to find the companion clock of
225 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
226 * @other_bit: u8 ** to return the companion clock bit shift in
227 *
228 * Some clocks don't have companion clocks. For example, modules with
229 * only an interface clock (such as HECC) don't have a companion
230 * clock. Right now, this code relies on the hardware exporting a bit
231 * in the correct companion register that indicates that the
232 * nonexistent 'companion clock' is active. Future patches will
233 * associate this type of code with per-module data structures to
234 * avoid this issue, and remove the casts. No return value.
235 */
236static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
237 u8 *other_bit)
238{
239 *other_reg = (__force void __iomem *)(clk->enable_reg);
240 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
241 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
242 else
243 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
244}
245
246const struct clkops clkops_am35xx_ipss_module_wait = {
247 .enable = omap2_dflt_clk_enable,
248 .disable = omap2_dflt_clk_disable,
249 .find_idlest = am35xx_clk_find_idlest,
250 .find_companion = am35xx_clk_find_companion,
251};
252
253/**
254 * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
255 * @clk: struct clk * being enabled
256 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
257 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
258 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
259 *
260 * The IPSS target CM_IDLEST bit is at a different shift from the
261 * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
262 * and @idlest_bit. No return value.
263 */
264static void am35xx_clk_ipss_find_idlest(struct clk *clk,
265 void __iomem **idlest_reg,
266 u8 *idlest_bit,
267 u8 *idlest_val)
268{
269 u32 r;
270
271 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
272 *idlest_reg = (__force void __iomem *)r;
273 *idlest_bit = AM35XX_ST_IPSS_SHIFT;
274 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
275}
276
277const struct clkops clkops_am35xx_ipss_wait = {
278 .enable = omap2_dflt_clk_enable,
279 .disable = omap2_dflt_clk_disable,
280 .find_idlest = am35xx_clk_ipss_find_idlest,
281 .find_companion = omap2_clk_dflt_find_companion,
282};
283
284int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
285{
286 /*
287 * According to the 12-5 CDP code from TI, "Limitation 2.5"
288 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
289 * on DPLL4.
290 */
291 if (omap_rev() == OMAP3430_REV_ES1_0) {
292 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
293 "silicon 'Limitation 2.5' on 3430ES1.\n");
294 return -EINVAL;
295 }
296 return omap3_noncore_dpll_set_rate(clk, rate);
297}
298
299void __init omap3_clk_lock_dpll5(void)
300{
301 struct clk *dpll5_clk;
302 struct clk *dpll5_m2_clk;
303
304 dpll5_clk = clk_get(NULL, "dpll5_ck");
305 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
306 clk_enable(dpll5_clk);
307
308 /* Enable autoidle to allow it to enter low power bypass */
309 omap3_dpll_allow_idle(dpll5_clk);
310
311 /* Program dpll5_m2_clk divider for no division */
312 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
313 clk_enable(dpll5_m2_clk);
314 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
315
316 clk_disable(dpll5_m2_clk);
317 clk_disable(dpll5_clk);
318 return;
319}
320
321/* Common clock code */
322
323/* REVISIT: Move this init stuff out into clock.c */
324
325/*
326 * Switch the MPU rate if specified on cmdline.
327 * We cannot do this early until cmdline is parsed.
328 */
329static int __init omap3xxx_clk_arch_init(void)
330{
331 struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
332 unsigned long osc_sys_rate;
333 bool err = 0;
334
335 if (!cpu_is_omap34xx())
336 return 0;
337
338 if (!mpurate)
339 return -EINVAL;
340
341 /* XXX test these for success */
342 dpll1_ck = clk_get(NULL, "dpll1_ck");
343 if (WARN(IS_ERR(dpll1_ck), "Failed to get dpll1_ck.\n"))
344 err = 1;
345
346 arm_fck = clk_get(NULL, "arm_fck");
347 if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))
348 err = 1;
349
350 core_ck = clk_get(NULL, "core_ck");
351 if (WARN(IS_ERR(core_ck), "Failed to get core_ck.\n"))
352 err = 1;
353
354 osc_sys_ck = clk_get(NULL, "osc_sys_ck");
355 if (WARN(IS_ERR(osc_sys_ck), "Failed to get osc_sys_ck.\n"))
356 err = 1;
357
358 if (err)
359 return -ENOENT;
360
361 /* REVISIT: not yet ready for 343x */
362 if (clk_set_rate(dpll1_ck, mpurate))
363 printk(KERN_ERR "*** Unable to set MPU rate\n");
364
365 recalculate_root_clocks();
366
367 osc_sys_rate = clk_get_rate(osc_sys_ck);
368
369 pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
370 "%ld.%01ld/%ld/%ld MHz\n",
371 (osc_sys_rate / 1000000),
372 ((osc_sys_rate / 100000) % 10),
373 (clk_get_rate(core_ck) / 1000000),
374 (clk_get_rate(arm_fck) / 1000000));
375
376 calibrate_delay();
377
378 return 0;
379}
380arch_initcall(omap3xxx_clk_arch_init);
381
382
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 720091ddced1..628e8de57680 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,32 +1,15 @@
1/* 1/*
2 * OMAP3 clock function prototypes and macros 2 * OMAP34xx clock function prototypes and macros
3 * 3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2010 Nokia Corporation
6 */ 6 */
7 7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
10 10
11int omap3xxx_clk_init(void);
12int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
13int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
14void omap3_clk_lock_dpll5(void);
15
16extern struct clk *sdrc_ick_p;
17extern struct clk *arm_fck_p;
18
19/* OMAP34xx-specific clkops */
20extern const struct clkops clkops_omap3430es2_ssi_wait; 11extern const struct clkops clkops_omap3430es2_ssi_wait;
21extern const struct clkops clkops_omap3430es2_hsotgusb_wait; 12extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
22extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; 13extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
23extern const struct clkops omap3_clkops_noncore_dpll_ops;
24
25/* AM35xx-specific clkops */
26extern const struct clkops clkops_am35xx_ipss_module_wait;
27extern const struct clkops clkops_am35xx_ipss_wait;
28
29/* OMAP36xx-specific clkops */
30extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
31 14
32#endif 15#endif
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
new file mode 100644
index 000000000000..b496a9305e1c
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -0,0 +1,124 @@
1/*
2 * OMAP3517/3505-specific clock framework functions
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Ranjith Lohithakshan
8 * Paul Walmsley
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
12 * Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
24#include <plat/clock.h>
25
26#include "clock.h"
27#include "clock3517.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30
31/*
32 * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
33 * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
34 * at an offset of 4 from ICK enable bit.
35 */
36#define AM35XX_IPSS_ICK_MASK 0xF
37#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
38#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
39#define AM35XX_IPSS_CLK_IDLEST_VAL 0
40
41/**
42 * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
43 * @clk: struct clk * being enabled
44 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
45 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
46 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
47 *
48 * The interface clocks on AM35xx IPSS reflects the clock idle status
49 * in the enable register itsel at a bit offset of 4 from the enable
50 * bit. A value of 1 indicates that clock is enabled.
51 */
52static void am35xx_clk_find_idlest(struct clk *clk,
53 void __iomem **idlest_reg,
54 u8 *idlest_bit,
55 u8 *idlest_val)
56{
57 *idlest_reg = (__force void __iomem *)(clk->enable_reg);
58 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
59 *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
60}
61
62/**
63 * am35xx_clk_find_companion - find companion clock to @clk
64 * @clk: struct clk * to find the companion clock of
65 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
66 * @other_bit: u8 ** to return the companion clock bit shift in
67 *
68 * Some clocks don't have companion clocks. For example, modules with
69 * only an interface clock (such as HECC) don't have a companion
70 * clock. Right now, this code relies on the hardware exporting a bit
71 * in the correct companion register that indicates that the
72 * nonexistent 'companion clock' is active. Future patches will
73 * associate this type of code with per-module data structures to
74 * avoid this issue, and remove the casts. No return value.
75 */
76static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
77 u8 *other_bit)
78{
79 *other_reg = (__force void __iomem *)(clk->enable_reg);
80 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
81 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
82 else
83 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
84}
85
86const struct clkops clkops_am35xx_ipss_module_wait = {
87 .enable = omap2_dflt_clk_enable,
88 .disable = omap2_dflt_clk_disable,
89 .find_idlest = am35xx_clk_find_idlest,
90 .find_companion = am35xx_clk_find_companion,
91};
92
93/**
94 * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
95 * @clk: struct clk * being enabled
96 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
97 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
98 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
99 *
100 * The IPSS target CM_IDLEST bit is at a different shift from the
101 * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
102 * and @idlest_bit. No return value.
103 */
104static void am35xx_clk_ipss_find_idlest(struct clk *clk,
105 void __iomem **idlest_reg,
106 u8 *idlest_bit,
107 u8 *idlest_val)
108{
109 u32 r;
110
111 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
112 *idlest_reg = (__force void __iomem *)r;
113 *idlest_bit = AM35XX_ST_IPSS_SHIFT;
114 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
115}
116
117const struct clkops clkops_am35xx_ipss_wait = {
118 .enable = omap2_dflt_clk_enable,
119 .disable = omap2_dflt_clk_disable,
120 .find_idlest = am35xx_clk_ipss_find_idlest,
121 .find_companion = omap2_clk_dflt_find_companion,
122};
123
124
diff --git a/arch/arm/mach-omap2/clock3517.h b/arch/arm/mach-omap2/clock3517.h
new file mode 100644
index 000000000000..ca5e5a64c2e2
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3517.h
@@ -0,0 +1,14 @@
1/*
2 * OMAP3517/3505 clock function prototypes and macros
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 */
7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3517_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK3517_H
10
11extern const struct clkops clkops_am35xx_ipss_module_wait;
12extern const struct clkops clkops_am35xx_ipss_wait;
13
14#endif
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
new file mode 100644
index 000000000000..0c5e25ed8879
--- /dev/null
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -0,0 +1,72 @@
1/*
2 * OMAP36xx-specific clkops
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Mike Turquette
8 * Vijaykumar GN
9 * Paul Walmsley
10 *
11 * Parts of this code are based on code written by
12 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
13 * Russell King
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19#undef DEBUG
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <plat/clock.h>
26
27#include "clock.h"
28#include "clock36xx.h"
29
30
31/**
32 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
33 * from HSDivider PWRDN problem Implements Errata ID: i556.
34 * @clk: DPLL output struct clk
35 *
36 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
37 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
38 * valueafter their respective PWRDN bits are set. Any dummy write
39 * (Any other value different from the Read value) to the
40 * corresponding CM_CLKSEL register will refresh the dividers.
41 */
42static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
43{
44 u32 dummy_v, orig_v, clksel_shift;
45 int ret;
46
47 /* Clear PWRDN bit of HSDIVIDER */
48 ret = omap2_dflt_clk_enable(clk);
49
50 /* Restore the dividers */
51 if (!ret) {
52 clksel_shift = __ffs(clk->parent->clksel_mask);
53 orig_v = __raw_readl(clk->parent->clksel_reg);
54 dummy_v = orig_v;
55
56 /* Write any other value different from the Read value */
57 dummy_v ^= (1 << clksel_shift);
58 __raw_writel(dummy_v, clk->parent->clksel_reg);
59
60 /* Write the original divider */
61 __raw_writel(orig_v, clk->parent->clksel_reg);
62 }
63
64 return ret;
65}
66
67const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
68 .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
69 .disable = omap2_dflt_clk_disable,
70 .find_companion = omap2_clk_dflt_find_companion,
71 .find_idlest = omap2_clk_dflt_find_idlest,
72};
diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h
new file mode 100644
index 000000000000..a7dee5bc6364
--- /dev/null
+++ b/arch/arm/mach-omap2/clock36xx.h
@@ -0,0 +1,13 @@
1/*
2 * OMAP36xx clock function prototypes and macros
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 */
7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
10
11extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
12
13#endif
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
new file mode 100644
index 000000000000..d142457cd041
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -0,0 +1,145 @@
1/*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/err.h>
25
26#include <plat/cpu.h>
27#include <plat/clock.h>
28
29#include "clock.h"
30#include "clock3xxx.h"
31#include "prm.h"
32#include "prm-regbits-34xx.h"
33#include "cm.h"
34#include "cm-regbits-34xx.h"
35
36/*
37 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
38 * that are sourced by DPLL5, and both of these require this clock
39 * to be at 120 MHz for proper operation.
40 */
41#define DPLL5_FREQ_FOR_USBHOST 120000000
42
43/* needed by omap3_core_dpll_m2_set_rate() */
44struct clk *sdrc_ick_p, *arm_fck_p;
45
46int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
47{
48 /*
49 * According to the 12-5 CDP code from TI, "Limitation 2.5"
50 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
51 * on DPLL4.
52 */
53 if (omap_rev() == OMAP3430_REV_ES1_0) {
54 pr_err("clock: DPLL4 cannot change rate due to "
55 "silicon 'Limitation 2.5' on 3430ES1.\n");
56 return -EINVAL;
57 }
58
59 return omap3_noncore_dpll_set_rate(clk, rate);
60}
61
62void __init omap3_clk_lock_dpll5(void)
63{
64 struct clk *dpll5_clk;
65 struct clk *dpll5_m2_clk;
66
67 dpll5_clk = clk_get(NULL, "dpll5_ck");
68 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
69 clk_enable(dpll5_clk);
70
71 /* Enable autoidle to allow it to enter low power bypass */
72 omap3_dpll_allow_idle(dpll5_clk);
73
74 /* Program dpll5_m2_clk divider for no division */
75 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
76 clk_enable(dpll5_m2_clk);
77 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
78
79 clk_disable(dpll5_m2_clk);
80 clk_disable(dpll5_clk);
81 return;
82}
83
84/* Common clock code */
85
86/* REVISIT: Move this init stuff out into clock.c */
87
88/*
89 * Switch the MPU rate if specified on cmdline.
90 * We cannot do this early until cmdline is parsed.
91 */
92static int __init omap3xxx_clk_arch_init(void)
93{
94 struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
95 unsigned long osc_sys_rate;
96 bool err = 0;
97
98 if (!cpu_is_omap34xx())
99 return 0;
100
101 if (!mpurate)
102 return -EINVAL;
103
104 /* XXX test these for success */
105 dpll1_ck = clk_get(NULL, "dpll1_ck");
106 if (WARN(IS_ERR(dpll1_ck), "Failed to get dpll1_ck.\n"))
107 err = 1;
108
109 arm_fck = clk_get(NULL, "arm_fck");
110 if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))
111 err = 1;
112
113 core_ck = clk_get(NULL, "core_ck");
114 if (WARN(IS_ERR(core_ck), "Failed to get core_ck.\n"))
115 err = 1;
116
117 osc_sys_ck = clk_get(NULL, "osc_sys_ck");
118 if (WARN(IS_ERR(osc_sys_ck), "Failed to get osc_sys_ck.\n"))
119 err = 1;
120
121 if (err)
122 return -ENOENT;
123
124 /* REVISIT: not yet ready for 343x */
125 if (clk_set_rate(dpll1_ck, mpurate))
126 printk(KERN_ERR "*** Unable to set MPU rate\n");
127
128 recalculate_root_clocks();
129
130 osc_sys_rate = clk_get_rate(osc_sys_ck);
131
132 pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
133 "%ld.%01ld/%ld/%ld MHz\n",
134 (osc_sys_rate / 1000000),
135 ((osc_sys_rate / 100000) % 10),
136 (clk_get_rate(core_ck) / 1000000),
137 (clk_get_rate(arm_fck) / 1000000));
138
139 calibrate_delay();
140
141 return 0;
142}
143arch_initcall(omap3xxx_clk_arch_init);
144
145
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
new file mode 100644
index 000000000000..8bbeeaf399e2
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -0,0 +1,21 @@
1/*
2 * OMAP3-common clock function prototypes and macros
3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 */
7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
10
11int omap3xxx_clk_init(void);
12int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
13int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
14void omap3_clk_lock_dpll5(void);
15
16extern struct clk *sdrc_ick_p;
17extern struct clk *arm_fck_p;
18
19extern const struct clkops clkops_noncore_dpll_ops;
20
21#endif
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 995d5d4c897d..f23790297003 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -24,7 +24,11 @@
24#include <plat/clkdev_omap.h> 24#include <plat/clkdev_omap.h>
25 25
26#include "clock.h" 26#include "clock.h"
27#include "clock3xxx.h"
27#include "clock34xx.h" 28#include "clock34xx.h"
29#include "clock36xx.h"
30#include "clock3517.h"
31
28#include "cm.h" 32#include "cm.h"
29#include "cm-regbits-34xx.h" 33#include "cm-regbits-34xx.h"
30#include "prm.h" 34#include "prm.h"
@@ -374,7 +378,7 @@ static struct dpll_data dpll2_dd = {
374 378
375static struct clk dpll2_ck = { 379static struct clk dpll2_ck = {
376 .name = "dpll2_ck", 380 .name = "dpll2_ck",
377 .ops = &omap3_clkops_noncore_dpll_ops, 381 .ops = &clkops_omap3_noncore_dpll_ops,
378 .parent = &sys_ck, 382 .parent = &sys_ck,
379 .dpll_data = &dpll2_dd, 383 .dpll_data = &dpll2_dd,
380 .round_rate = &omap2_dpll_round_rate, 384 .round_rate = &omap2_dpll_round_rate,
@@ -615,7 +619,7 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
615 619
616static struct clk dpll4_ck = { 620static struct clk dpll4_ck = {
617 .name = "dpll4_ck", 621 .name = "dpll4_ck",
618 .ops = &omap3_clkops_noncore_dpll_ops, 622 .ops = &clkops_omap3_noncore_dpll_ops,
619 .parent = &sys_ck, 623 .parent = &sys_ck,
620 .dpll_data = &dpll4_dd, 624 .dpll_data = &dpll4_dd,
621 .round_rate = &omap2_dpll_round_rate, 625 .round_rate = &omap2_dpll_round_rate,
@@ -1023,7 +1027,7 @@ static struct dpll_data dpll5_dd = {
1023 1027
1024static struct clk dpll5_ck = { 1028static struct clk dpll5_ck = {
1025 .name = "dpll5_ck", 1029 .name = "dpll5_ck",
1026 .ops = &omap3_clkops_noncore_dpll_ops, 1030 .ops = &clkops_omap3_noncore_dpll_ops,
1027 .parent = &sys_ck, 1031 .parent = &sys_ck,
1028 .dpll_data = &dpll5_dd, 1032 .dpll_data = &dpll5_dd,
1029 .round_rate = &omap2_dpll_round_rate, 1033 .round_rate = &omap2_dpll_round_rate,
@@ -3567,10 +3571,12 @@ int __init omap3xxx_clk_init(void)
3567 3571
3568 clk_init(&omap2_clk_functions); 3572 clk_init(&omap2_clk_functions);
3569 3573
3570 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) 3574 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3575 c++)
3571 clk_preinit(c->lk.clk); 3576 clk_preinit(c->lk.clk);
3572 3577
3573 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) 3578 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3579 c++)
3574 if (c->cpu & cpu_clkflg) { 3580 if (c->cpu & cpu_clkflg) {
3575 clkdev_add(&c->lk); 3581 clkdev_add(&c->lk);
3576 clk_register(c->lk.clk); 3582 clk_register(c->lk.clk);
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c
deleted file mode 100644
index 84ee6b0c7995..000000000000
--- a/arch/arm/mach-omap2/clock44xx.c
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * OMAP4-specific clock framework functions
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Rajendra Nayak (rnayak@ti.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/errno.h>
14#include "clock.h"
15
16const struct clkops omap4_clkops_noncore_dpll_ops = {
17 .enable = &omap3_noncore_dpll_enable,
18 .disable = &omap3_noncore_dpll_disable,
19};
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 0c739726703d..6be1095936db 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -5,8 +5,8 @@
5 * Copyright (C) 2010 Nokia Corporation 5 * Copyright (C) 2010 Nokia Corporation
6 */ 6 */
7 7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
10 10
11/* 11/*
12 * XXX Missing values for the OMAP4 DPLL_USB 12 * XXX Missing values for the OMAP4 DPLL_USB
@@ -17,6 +17,4 @@
17 17
18int omap4xxx_clk_init(void); 18int omap4xxx_clk_init(void);
19 19
20extern const struct clkops omap4_clkops_noncore_dpll_ops;
21
22#endif 20#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c7ab76bc70c..022f1a75286a 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -277,7 +277,7 @@ static struct clk dpll_abe_ck = {
277 .parent = &abe_dpll_refclk_mux_ck, 277 .parent = &abe_dpll_refclk_mux_ck,
278 .dpll_data = &dpll_abe_dd, 278 .dpll_data = &dpll_abe_dd,
279 .init = &omap2_init_dpll_parent, 279 .init = &omap2_init_dpll_parent,
280 .ops = &omap4_clkops_noncore_dpll_ops, 280 .ops = &clkops_omap3_noncore_dpll_ops,
281 .recalc = &omap3_dpll_recalc, 281 .recalc = &omap3_dpll_recalc,
282 .round_rate = &omap2_dpll_round_rate, 282 .round_rate = &omap2_dpll_round_rate,
283 .set_rate = &omap3_noncore_dpll_set_rate, 283 .set_rate = &omap3_noncore_dpll_set_rate,
@@ -644,7 +644,7 @@ static struct clk dpll_iva_ck = {
644 .parent = &dpll_sys_ref_clk, 644 .parent = &dpll_sys_ref_clk,
645 .dpll_data = &dpll_iva_dd, 645 .dpll_data = &dpll_iva_dd,
646 .init = &omap2_init_dpll_parent, 646 .init = &omap2_init_dpll_parent,
647 .ops = &omap4_clkops_noncore_dpll_ops, 647 .ops = &clkops_omap3_noncore_dpll_ops,
648 .recalc = &omap3_dpll_recalc, 648 .recalc = &omap3_dpll_recalc,
649 .round_rate = &omap2_dpll_round_rate, 649 .round_rate = &omap2_dpll_round_rate,
650 .set_rate = &omap3_noncore_dpll_set_rate, 650 .set_rate = &omap3_noncore_dpll_set_rate,
@@ -704,7 +704,7 @@ static struct clk dpll_mpu_ck = {
704 .parent = &dpll_sys_ref_clk, 704 .parent = &dpll_sys_ref_clk,
705 .dpll_data = &dpll_mpu_dd, 705 .dpll_data = &dpll_mpu_dd,
706 .init = &omap2_init_dpll_parent, 706 .init = &omap2_init_dpll_parent,
707 .ops = &omap4_clkops_noncore_dpll_ops, 707 .ops = &clkops_omap3_noncore_dpll_ops,
708 .recalc = &omap3_dpll_recalc, 708 .recalc = &omap3_dpll_recalc,
709 .round_rate = &omap2_dpll_round_rate, 709 .round_rate = &omap2_dpll_round_rate,
710 .set_rate = &omap3_noncore_dpll_set_rate, 710 .set_rate = &omap3_noncore_dpll_set_rate,
@@ -776,7 +776,7 @@ static struct clk dpll_per_ck = {
776 .parent = &dpll_sys_ref_clk, 776 .parent = &dpll_sys_ref_clk,
777 .dpll_data = &dpll_per_dd, 777 .dpll_data = &dpll_per_dd,
778 .init = &omap2_init_dpll_parent, 778 .init = &omap2_init_dpll_parent,
779 .ops = &omap4_clkops_noncore_dpll_ops, 779 .ops = &clkops_omap3_noncore_dpll_ops,
780 .recalc = &omap3_dpll_recalc, 780 .recalc = &omap3_dpll_recalc,
781 .round_rate = &omap2_dpll_round_rate, 781 .round_rate = &omap2_dpll_round_rate,
782 .set_rate = &omap3_noncore_dpll_set_rate, 782 .set_rate = &omap3_noncore_dpll_set_rate,
@@ -891,7 +891,7 @@ static struct clk dpll_unipro_ck = {
891 .parent = &dpll_sys_ref_clk, 891 .parent = &dpll_sys_ref_clk,
892 .dpll_data = &dpll_unipro_dd, 892 .dpll_data = &dpll_unipro_dd,
893 .init = &omap2_init_dpll_parent, 893 .init = &omap2_init_dpll_parent,
894 .ops = &omap4_clkops_noncore_dpll_ops, 894 .ops = &clkops_omap3_noncore_dpll_ops,
895 .recalc = &omap3_dpll_recalc, 895 .recalc = &omap3_dpll_recalc,
896 .round_rate = &omap2_dpll_round_rate, 896 .round_rate = &omap2_dpll_round_rate,
897 .set_rate = &omap3_noncore_dpll_set_rate, 897 .set_rate = &omap3_noncore_dpll_set_rate,
@@ -947,7 +947,7 @@ static struct clk dpll_usb_ck = {
947 .parent = &dpll_sys_ref_clk, 947 .parent = &dpll_sys_ref_clk,
948 .dpll_data = &dpll_usb_dd, 948 .dpll_data = &dpll_usb_dd,
949 .init = &omap2_init_dpll_parent, 949 .init = &omap2_init_dpll_parent,
950 .ops = &omap4_clkops_noncore_dpll_ops, 950 .ops = &clkops_omap3_noncore_dpll_ops,
951 .recalc = &omap3_dpll_recalc, 951 .recalc = &omap3_dpll_recalc,
952 .round_rate = &omap2_dpll_round_rate, 952 .round_rate = &omap2_dpll_round_rate,
953 .set_rate = &omap3_noncore_dpll_set_rate, 953 .set_rate = &omap3_noncore_dpll_set_rate,
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5a3d6f9107e4..2c5185474972 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -36,7 +36,7 @@
36#include <plat/vram.h> 36#include <plat/vram.h>
37 37
38#include "clock2xxx.h" 38#include "clock2xxx.h"
39#include "clock34xx.h" 39#include "clock3xxx.h"
40#include "clock44xx.h" 40#include "clock44xx.h"
41 41
42#include <plat/omap-pm.h> 42#include <plat/omap-pm.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 09:57:13 -0500