diff options
-rw-r--r-- | arch/blackfin/mach-bf527/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf548/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-common/dpmc_modes.S | 56 | ||||
-rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-common/pm.c | 8 | ||||
-rw-r--r-- | include/asm-blackfin/dpmc.h | 1 |
8 files changed, 8 insertions, 93 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index af20183d0d94..2cc46f8fa9a7 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S | |||
@@ -183,13 +183,6 @@ ENTRY(_start_dma_code) | |||
183 | [P2] = R1; | 183 | [P2] = R1; |
184 | SSYNC; | 184 | SSYNC; |
185 | 185 | ||
186 | p0.h = hi(SIC_IWR0); | ||
187 | p0.l = lo(SIC_IWR0); | ||
188 | r0.l = lo(IWR_ENABLE_ALL); | ||
189 | r0.h = hi(IWR_ENABLE_ALL); | ||
190 | [p0] = r0; | ||
191 | SSYNC; | ||
192 | |||
193 | RTS; | 186 | RTS; |
194 | ENDPROC(_start_dma_code) | 187 | ENDPROC(_start_dma_code) |
195 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 188 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 6603967367ec..184296bee3c9 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S | |||
@@ -177,13 +177,6 @@ ENTRY(_start_dma_code) | |||
177 | [P2] = R1; | 177 | [P2] = R1; |
178 | SSYNC; | 178 | SSYNC; |
179 | 179 | ||
180 | p0.h = hi(SIC_IWR); | ||
181 | p0.l = lo(SIC_IWR); | ||
182 | r0.l = lo(IWR_ENABLE_ALL); | ||
183 | r0.h = hi(IWR_ENABLE_ALL); | ||
184 | [p0] = r0; | ||
185 | SSYNC; | ||
186 | |||
187 | RTS; | 180 | RTS; |
188 | ENDPROC(_start_dma_code) | 181 | ENDPROC(_start_dma_code) |
189 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 182 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 6a02e472587a..c02c8ce2d96f 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S | |||
@@ -197,13 +197,6 @@ ENTRY(_start_dma_code) | |||
197 | [P2] = R1; | 197 | [P2] = R1; |
198 | SSYNC; | 198 | SSYNC; |
199 | 199 | ||
200 | p0.h = hi(SIC_IWR); | ||
201 | p0.l = lo(SIC_IWR); | ||
202 | r0.l = lo(IWR_ENABLE_ALL); | ||
203 | r0.h = hi(IWR_ENABLE_ALL); | ||
204 | [p0] = r0; | ||
205 | SSYNC; | ||
206 | |||
207 | RTS; | 200 | RTS; |
208 | ENDPROC(_start_dma_code) | 201 | ENDPROC(_start_dma_code) |
209 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 202 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index cf94e1e222b8..0b18196df869 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S | |||
@@ -201,13 +201,6 @@ ENTRY(_start_dma_code) | |||
201 | SSYNC; | 201 | SSYNC; |
202 | #endif | 202 | #endif |
203 | 203 | ||
204 | p0.h = hi(SIC_IWR0); | ||
205 | p0.l = lo(SIC_IWR0); | ||
206 | r0.l = lo(IWR_ENABLE_ALL); | ||
207 | r0.h = hi(IWR_ENABLE_ALL); | ||
208 | [p0] = r0; | ||
209 | SSYNC; | ||
210 | |||
211 | RTS; | 204 | RTS; |
212 | ENDPROC(_start_dma_code) | 205 | ENDPROC(_start_dma_code) |
213 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 206 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 5e3f1d8a4fb8..838b0b2ce9a5 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S | |||
@@ -78,62 +78,6 @@ ENTRY(_hibernate_mode) | |||
78 | jump .Lforever; | 78 | jump .Lforever; |
79 | ENDPROC(_hibernate_mode) | 79 | ENDPROC(_hibernate_mode) |
80 | 80 | ||
81 | ENTRY(_deep_sleep) | ||
82 | [--SP] = ( R7:0, P5:0 ); | ||
83 | [--SP] = RETS; | ||
84 | |||
85 | CLI R4; | ||
86 | |||
87 | R0 = IWR_ENABLE(0); | ||
88 | R1 = IWR_DISABLE_ALL; | ||
89 | R2 = IWR_DISABLE_ALL; | ||
90 | |||
91 | call _set_sic_iwr; | ||
92 | |||
93 | call _set_dram_srfs; | ||
94 | |||
95 | /* Clear all the interrupts,bits sticky */ | ||
96 | R0 = 0xFFFF (Z); | ||
97 | call _set_rtc_istat | ||
98 | |||
99 | P0.H = hi(PLL_CTL); | ||
100 | P0.L = lo(PLL_CTL); | ||
101 | R0 = W[P0](z); | ||
102 | BITSET (R0, 5); | ||
103 | W[P0] = R0.L; | ||
104 | |||
105 | call _test_pll_locked; | ||
106 | |||
107 | SSYNC; | ||
108 | IDLE; | ||
109 | |||
110 | call _unset_dram_srfs; | ||
111 | |||
112 | call _test_pll_locked; | ||
113 | |||
114 | R0 = IWR_ENABLE(0); | ||
115 | R1 = IWR_DISABLE_ALL; | ||
116 | R2 = IWR_DISABLE_ALL; | ||
117 | |||
118 | call _set_sic_iwr; | ||
119 | |||
120 | P0.H = hi(PLL_CTL); | ||
121 | P0.L = lo(PLL_CTL); | ||
122 | R0 = w[p0](z); | ||
123 | BITCLR (R0, 3); | ||
124 | BITCLR (R0, 5); | ||
125 | BITCLR (R0, 8); | ||
126 | w[p0] = R0; | ||
127 | IDLE; | ||
128 | call _test_pll_locked; | ||
129 | |||
130 | STI R4; | ||
131 | |||
132 | RETS = [SP++]; | ||
133 | ( R7:0, P5:0 ) = [SP++]; | ||
134 | RTS; | ||
135 | ENDPROC(_deep_sleep) | ||
136 | |||
137 | ENTRY(_sleep_deeper) | 81 | ENTRY(_sleep_deeper) |
138 | [--SP] = ( R7:0, P5:0 ); | 82 | [--SP] = ( R7:0, P5:0 ); |
139 | [--SP] = RETS; | 83 | [--SP] = RETS; |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index e713b9db867d..4271ef3f201a 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -1068,13 +1068,13 @@ int __init init_arch_irq(void) | |||
1068 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | 1068 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
1069 | 1069 | ||
1070 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 1070 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
1071 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); | 1071 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
1072 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); | 1072 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
1073 | # ifdef CONFIG_BF54x | 1073 | # ifdef CONFIG_BF54x |
1074 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); | 1074 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
1075 | # endif | 1075 | # endif |
1076 | #else | 1076 | #else |
1077 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); | 1077 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
1078 | #endif | 1078 | #endif |
1079 | 1079 | ||
1080 | return 0; | 1080 | return 0; |
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 143134b852ea..a17ace3e0e41 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
@@ -83,13 +83,13 @@ void bfin_pm_suspend_standby_enter(void) | |||
83 | bfin_pm_standby_restore(); | 83 | bfin_pm_standby_restore(); |
84 | 84 | ||
85 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 85 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
86 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); | 86 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
87 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); | 87 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
88 | # ifdef CONFIG_BF54x | 88 | # ifdef CONFIG_BF54x |
89 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); | 89 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
90 | # endif | 90 | # endif |
91 | #else | 91 | #else |
92 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); | 92 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
93 | #endif | 93 | #endif |
94 | 94 | ||
95 | local_irq_restore(flags); | 95 | local_irq_restore(flags); |
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h index de28e6e018b3..96e8208f929a 100644 --- a/include/asm-blackfin/dpmc.h +++ b/include/asm-blackfin/dpmc.h | |||
@@ -11,7 +11,6 @@ | |||
11 | #ifndef __ASSEMBLY__ | 11 | #ifndef __ASSEMBLY__ |
12 | 12 | ||
13 | void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); | 13 | void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
14 | void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); | ||
15 | void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); | 14 | void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
16 | void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); | 15 | void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
17 | void do_hibernate(int wakeup); | 16 | void do_hibernate(int wakeup); |