4 files changed, 304 insertions, 1 deletions

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 111eaa64258f..7a8edd6cd198 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,8 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o
+obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
+         serial.o gpmc.o
 
 obj-$(CONFIG_OMAP_MPU_TIMER)            += timer-gp.o
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
new file mode 100644
index 000000000000..4aeaa4e79585
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -0,0 +1,209 @@
+/*
+ * GPMC support functions
+ *
+ * Copyright (C) 2005-2006 Nokia Corporation
+ *
+ * Author: Juha Yrjola
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#include <asm/arch/gpmc.h>
+
+#undef DEBUG
+
+#define GPMC_BASE               0x6800a000
+#define GPMC_REVISION           0x00
+#define GPMC_SYSCONFIG          0x10
+#define GPMC_SYSSTATUS          0x14
+#define GPMC_IRQSTATUS          0x18
+#define GPMC_IRQENABLE          0x1c
+#define GPMC_TIMEOUT_CONTROL    0x40
+#define GPMC_ERR_ADDRESS        0x44
+#define GPMC_ERR_TYPE           0x48
+#define GPMC_CONFIG             0x50
+#define GPMC_STATUS             0x54
+#define GPMC_PREFETCH_CONFIG1   0x1e0
+#define GPMC_PREFETCH_CONFIG2   0x1e4
+#define GPMC_PREFETCH_CONTROL   0x1e8
+#define GPMC_PREFETCH_STATUS    0x1f0
+#define GPMC_ECC_CONFIG         0x1f4
+#define GPMC_ECC_CONTROL        0x1f8
+#define GPMC_ECC_SIZE_CONFIG    0x1fc
+
+#define GPMC_CS0                0x60
+#define GPMC_CS_SIZE            0x30
+
+static void __iomem *gpmc_base =
+        (void __iomem *) IO_ADDRESS(GPMC_BASE);
+static void __iomem *gpmc_cs_base =
+        (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
+
+static struct clk *gpmc_l3_clk;
+
+static void gpmc_write_reg(int idx, u32 val)
+{
+        __raw_writel(val, gpmc_base + idx);
+}
+
+static u32 gpmc_read_reg(int idx)
+{
+        return __raw_readl(gpmc_base + idx);
+}
+
+void gpmc_cs_write_reg(int cs, int idx, u32 val)
+{
+        void __iomem *reg_addr;
+
+        reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
+        __raw_writel(val, reg_addr);
+}
+
+u32 gpmc_cs_read_reg(int cs, int idx)
+{
+        return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
+}
+
+/* TODO: Add support for gpmc_fck to clock framework and use it */
+static unsigned long gpmc_get_fclk_period(void)
+{
+        /* In picoseconds */
+        return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
+}
+
+unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+{
+        unsigned long tick_ps;
+
+        /* Calculate in picosecs to yield more exact results */
+        tick_ps = gpmc_get_fclk_period();
+
+        return (time_ns * 1000 + tick_ps - 1) / tick_ps;
+}
+
+#ifdef DEBUG
+static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+                               int time, int div, const char *name)
+#else
+static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+                               int time)
+#endif
+{
+        u32 l;
+        int ticks, mask, nr_bits;
+
+        if (time == 0)
+                ticks = 0;
+        else
+                ticks = gpmc_ns_to_ticks(time);
+        nr_bits = end_bit - st_bit + 1;
+        if (ticks >= 1 << nr_bits)
+                return -1;
+
+        mask = (1 << nr_bits) - 1;
+        l = gpmc_cs_read_reg(cs, reg);
+#ifdef DEBUG
+        printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
+               cs, name, ticks, gpmc_get_clk_period(div) * ticks / 1000,
+               (l >> st_bit) & mask);
+#endif
+        l &= ~(mask << st_bit);
+        l |= ticks << st_bit;
+        gpmc_cs_write_reg(cs, reg, l);
+
+        return 0;
+}
+
+#ifdef DEBUG
+#define GPMC_SET_ONE(reg, st, end, field) \
+        if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
+                        t->field, #field) < 0)                  \
+                return -1
+#else
+#define GPMC_SET_ONE(reg, st, end, field) \
+        if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
+                return -1
+#endif
+
+int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
+{
+        int div;
+        u32 l;
+
+        l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
+        div = l / gpmc_get_fclk_period();
+        if (div > 4)
+                return -1;
+        if (div < 0)
+                div = 1;
+
+        return div;
+}
+
+int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
+{
+        int div;
+        u32 l;
+
+        div = gpmc_cs_calc_divider(cs, t->sync_clk);
+        if (div < 0)
+                return -1;
+
+        GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
+        GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
+        GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
+
+        GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
+        GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
+        GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
+
+        GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
+        GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
+        GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
+        GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
+
+        GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
+        GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
+        GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
+
+        GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+
+#ifdef DEBUG
+        printk(KERN_INFO "GPMC CLK period is %d (div %d)\n",
+               cs, get_gpmc_clk_period(div), div);
+#endif
+
+        l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+        l &= ~0x03;
+        l |= (div - 1);
+
+        return 0;
+}
+
+unsigned long gpmc_cs_get_base_addr(int cs)
+{
+        return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24;
+}
+
+void __init gpmc_init(void)
+{
+        u32 l;
+
+        gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
+        BUG_ON(IS_ERR(gpmc_l3_clk));
+
+        l = gpmc_read_reg(GPMC_REVISION);
+        printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+        /* Set smart idle mode and automatic L3 clock gating */
+        l = gpmc_read_reg(GPMC_SYSCONFIG);
+        l &= 0x03 << 3;
+        l |= (0x02 << 3) | (1 << 0);
+        gpmc_write_reg(GPMC_SYSCONFIG, l);
+}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 7d5711611f2f..68456b79a0a8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -27,6 +27,7 @@
 extern void omap_sram_init(void);
 extern int omap2_clk_init(void);
 extern void omap2_check_revision(void);
+extern void gpmc_init(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -67,4 +68,5 @@ void __init omap2_init_common_hw(void)
 {
         omap2_mux_init();
         omap2_clk_init();
+        gpmc_init();
 }
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
new file mode 100644
index 000000000000..1a0a5207822d
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -0,0 +1,91 @@
+/*
+ * General-Purpose Memory Controller for OMAP2
+ *
+ * Copyright (C) 2005-2006 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP2_GPMC_H
+#define __OMAP2_GPMC_H
+
+#define GPMC_CS_CONFIG1         0x00
+#define GPMC_CS_CONFIG2         0x04
+#define GPMC_CS_CONFIG3         0x08
+#define GPMC_CS_CONFIG4         0x0c
+#define GPMC_CS_CONFIG5         0x10
+#define GPMC_CS_CONFIG6         0x14
+#define GPMC_CS_CONFIG7         0x18
+#define GPMC_CS_NAND_COMMAND    0x1c
+#define GPMC_CS_NAND_ADDRESS    0x20
+#define GPMC_CS_NAND_DATA       0x24
+
+#define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
+#define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 20)
+#define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
+#define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
+#define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
+#define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
+#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
+#define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
+#define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
+#define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
+#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
+#define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
+#define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
+#define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
+#define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
+#define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
+#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(1)
+#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
+#define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
+#define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
+#define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
+#define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
+
+/*
+ * Note that all values in this struct are in nanoseconds, while
+ * the register values are in gpmc_fck cycles.
+ */
+struct gpmc_timings {
+        /* Minimum clock period for synchronous mode */
+        u16 sync_clk;
+
+        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
+        u16 cs_on;              /* Assertion time */
+        u16 cs_rd_off;          /* Read deassertion time */
+        u16 cs_wr_off;          /* Write deassertion time */
+
+        /* ADV signal timings corresponding to GPMC_CONFIG3 */
+        u16 adv_on;             /* Assertion time */
+        u16 adv_rd_off;         /* Read deassertion time */
+        u16 adv_wr_off;         /* Write deassertion time */
+
+        /* WE signals timings corresponding to GPMC_CONFIG4 */
+        u16 we_on;              /* WE assertion time */
+        u16 we_off;             /* WE deassertion time */
+
+        /* OE signals timings corresponding to GPMC_CONFIG4 */
+        u16 oe_on;              /* OE assertion time */
+        u16 oe_off;             /* OE deassertion time */
+
+        /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
+        u16 page_burst_access;  /* Multiple access word delay */
+        u16 access;             /* Start-cycle to first data valid delay */
+        u16 rd_cycle;           /* Total read cycle time */
+        u16 wr_cycle;           /* Total write cycle time */
+};
+
+extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
+
+extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
+extern u32 gpmc_cs_read_reg(int cs, int idx);
+extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
+extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern unsigned long gpmc_cs_get_base_addr(int cs);
+
+
+#endif