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-rw-r--r--arch/sparc/kernel/irq.c2
-rw-r--r--arch/sparc/kernel/irq.h48
-rw-r--r--arch/sparc/kernel/pcic.c1
-rw-r--r--arch/sparc/kernel/smp.c2
-rw-r--r--arch/sparc/kernel/sun4c_irq.c15
-rw-r--r--arch/sparc/kernel/sun4d_irq.c2
-rw-r--r--arch/sparc/kernel/sun4d_smp.c1
-rw-r--r--arch/sparc/kernel/sun4m_irq.c74
-rw-r--r--arch/sparc/kernel/sun4m_smp.c2
-rw-r--r--arch/sparc/kernel/tick14.c2
-rw-r--r--arch/sparc/kernel/time.c2
-rw-r--r--include/asm-sparc/irq.h136
12 files changed, 151 insertions, 136 deletions
diff --git a/arch/sparc/kernel/irq.c b/arch/sparc/kernel/irq.c
index f257a67bcf93..5e9af3073acf 100644
--- a/arch/sparc/kernel/irq.c
+++ b/arch/sparc/kernel/irq.c
@@ -47,6 +47,8 @@
47#include <asm/cacheflush.h> 47#include <asm/cacheflush.h>
48#include <asm/irq_regs.h> 48#include <asm/irq_regs.h>
49 49
50#include "irq.h"
51
50#ifdef CONFIG_SMP 52#ifdef CONFIG_SMP
51#define SMP_NOP2 "nop; nop;\n\t" 53#define SMP_NOP2 "nop; nop;\n\t"
52#define SMP_NOP3 "nop; nop; nop;\n\t" 54#define SMP_NOP3 "nop; nop; nop;\n\t"
diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h
new file mode 100644
index 000000000000..8254a86d97d0
--- /dev/null
+++ b/arch/sparc/kernel/irq.h
@@ -0,0 +1,48 @@
1#include <asm/btfixup.h>
2
3BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
4BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
5BTFIXUPDEF_CALL(void, clear_clock_irq, void)
6BTFIXUPDEF_CALL(void, clear_profile_irq, int)
7BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
8
9static inline void disable_pil_irq(unsigned int irq)
10{
11 BTFIXUP_CALL(disable_pil_irq)(irq);
12}
13
14static inline void enable_pil_irq(unsigned int irq)
15{
16 BTFIXUP_CALL(enable_pil_irq)(irq);
17}
18
19static inline void clear_clock_irq(void)
20{
21 BTFIXUP_CALL(clear_clock_irq)();
22}
23
24static inline void clear_profile_irq(int irq)
25{
26 BTFIXUP_CALL(clear_profile_irq)(irq);
27}
28
29static inline void load_profile_irq(int cpu, int limit)
30{
31 BTFIXUP_CALL(load_profile_irq)(cpu, limit);
32}
33
34extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);
35
36extern void claim_ticker14(irq_handler_t irq_handler,
37 int irq,
38 unsigned int timeout);
39
40#ifdef CONFIG_SMP
41BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
42BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
43BTFIXUPDEF_CALL(void, set_irq_udt, int)
44
45#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
46#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
47#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
48#endif
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 791771196905..f2eae457fc9a 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -36,6 +36,7 @@
36#include <asm/uaccess.h> 36#include <asm/uaccess.h>
37#include <asm/irq_regs.h> 37#include <asm/irq_regs.h>
38 38
39#include "irq.h"
39 40
40/* 41/*
41 * I studied different documents and many live PROMs both from 2.30 42 * I studied different documents and many live PROMs both from 2.30
diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c
index 4fea3ac7bff0..6724ab90f82b 100644
--- a/arch/sparc/kernel/smp.c
+++ b/arch/sparc/kernel/smp.c
@@ -33,6 +33,8 @@
33#include <asm/tlbflush.h> 33#include <asm/tlbflush.h>
34#include <asm/cpudata.h> 34#include <asm/cpudata.h>
35 35
36#include "irq.h"
37
36int smp_num_cpus = 1; 38int smp_num_cpus = 1;
37volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,}; 39volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};
38unsigned char boot_cpu_id = 0; 40unsigned char boot_cpu_id = 0;
diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c
index 009e891a4329..c6ac9fc52563 100644
--- a/arch/sparc/kernel/sun4c_irq.c
+++ b/arch/sparc/kernel/sun4c_irq.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include "irq.h"
21 22
22#include <asm/ptrace.h> 23#include <asm/ptrace.h>
23#include <asm/processor.h> 24#include <asm/processor.h>
@@ -40,6 +41,20 @@ static struct resource sun4c_timer_eb = { "sun4c_timer" };
40static struct resource sun4c_intr_eb = { "sun4c_intr" }; 41static struct resource sun4c_intr_eb = { "sun4c_intr" };
41#endif 42#endif
42 43
44/*
45 * Bit field defines for the interrupt registers on various
46 * Sparc machines.
47 */
48
49/* The sun4c interrupt register. */
50#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
51#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
52#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
53#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
54#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
55#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
56#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
57
43/* Pointer to the interrupt enable byte 58/* Pointer to the interrupt enable byte
44 * 59 *
45 * Dave Redman (djhr@tadpole.co.uk) 60 * Dave Redman (djhr@tadpole.co.uk)
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
index 396797e20c39..7a09186a432e 100644
--- a/arch/sparc/kernel/sun4d_irq.c
+++ b/arch/sparc/kernel/sun4d_irq.c
@@ -39,6 +39,8 @@
39#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
40#include <asm/irq_regs.h> 40#include <asm/irq_regs.h>
41 41
42#include "irq.h"
43
42/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */ 44/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */
43/* #define DISTRIBUTE_IRQS */ 45/* #define DISTRIBUTE_IRQS */
44 46
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 098c94f1a322..89a6de95070c 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -36,6 +36,7 @@
36#include <asm/cacheflush.h> 36#include <asm/cacheflush.h>
37#include <asm/cpudata.h> 37#include <asm/cpudata.h>
38 38
39#include "irq.h"
39#define IRQ_CROSS_CALL 15 40#define IRQ_CROSS_CALL 15
40 41
41extern ctxd_t *srmmu_ctx_table_phys; 42extern ctxd_t *srmmu_ctx_table_phys;
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index 91a803ea88be..b92d6d2d5b04 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -38,11 +38,85 @@
38#include <asm/sbus.h> 38#include <asm/sbus.h>
39#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
40 40
41#include "irq.h"
42
43/* On the sun4m, just like the timers, we have both per-cpu and master
44 * interrupt registers.
45 */
46
47/* These registers are used for sending/receiving irqs from/to
48 * different cpu's.
49 */
50struct sun4m_intreg_percpu {
51 unsigned int tbt; /* Interrupts still pending for this cpu. */
52
53 /* These next two registers are WRITE-ONLY and are only
54 * "on bit" sensitive, "off bits" written have NO affect.
55 */
56 unsigned int clear; /* Clear this cpus irqs here. */
57 unsigned int set; /* Set this cpus irqs here. */
58 unsigned char space[PAGE_SIZE - 12];
59};
60
61/*
62 * djhr
63 * Actually the clear and set fields in this struct are misleading..
64 * according to the SLAVIO manual (and the same applies for the SEC)
65 * the clear field clears bits in the mask which will ENABLE that IRQ
66 * the set field sets bits in the mask to DISABLE the IRQ.
67 *
68 * Also the undirected_xx address in the SLAVIO is defined as
69 * RESERVED and write only..
70 *
71 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
72 * sun4m machines, for MP the layout makes more sense.
73 */
74struct sun4m_intregs {
75 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
76 unsigned int tbt; /* IRQ's that are still pending. */
77 unsigned int irqs; /* Master IRQ bits. */
78
79 /* Again, like the above, two these registers are WRITE-ONLY. */
80 unsigned int clear; /* Clear master IRQ's by setting bits here. */
81 unsigned int set; /* Set master IRQ's by setting bits here. */
82
83 /* This register is both READ and WRITE. */
84 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
85};
86
41static unsigned long dummy; 87static unsigned long dummy;
42 88
43struct sun4m_intregs *sun4m_interrupts; 89struct sun4m_intregs *sun4m_interrupts;
44unsigned long *irq_rcvreg = &dummy; 90unsigned long *irq_rcvreg = &dummy;
45 91
92/* Dave Redman (djhr@tadpole.co.uk)
93 * The sun4m interrupt registers.
94 */
95#define SUN4M_INT_ENABLE 0x80000000
96#define SUN4M_INT_E14 0x00000080
97#define SUN4M_INT_E10 0x00080000
98
99#define SUN4M_HARD_INT(x) (0x000000001 << (x))
100#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
101
102#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
103#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
104#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
105#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
106#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
107#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
108#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
109#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
110#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
111#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
112#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
113#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
114#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
115#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
116
117#define SUN4M_INT_SBUS(x) (1 << (x+7))
118#define SUN4M_INT_VME(x) (1 << (x))
119
46/* These tables only apply for interrupts greater than 15.. 120/* These tables only apply for interrupts greater than 15..
47 * 121 *
48 * any intr value below 0x10 is considered to be a soft-int 122 * any intr value below 0x10 is considered to be a soft-int
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index 63ed19bfd028..730eb5796f8e 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -31,6 +31,8 @@
31#include <asm/oplib.h> 31#include <asm/oplib.h>
32#include <asm/cpudata.h> 32#include <asm/cpudata.h>
33 33
34#include "irq.h"
35
34#define IRQ_RESCHEDULE 13 36#define IRQ_RESCHEDULE 13
35#define IRQ_STOP_CPU 14 37#define IRQ_STOP_CPU 14
36#define IRQ_CROSS_CALL 15 38#define IRQ_CROSS_CALL 15
diff --git a/arch/sparc/kernel/tick14.c b/arch/sparc/kernel/tick14.c
index f1a7bd19e04f..a55f0463b929 100644
--- a/arch/sparc/kernel/tick14.c
+++ b/arch/sparc/kernel/tick14.c
@@ -25,6 +25,8 @@
25#include <asm/irq.h> 25#include <asm/irq.h>
26#include <asm/io.h> 26#include <asm/io.h>
27 27
28#include "irq.h"
29
28extern unsigned long lvl14_save[5]; 30extern unsigned long lvl14_save[5];
29static unsigned long *linux_lvl14 = NULL; 31static unsigned long *linux_lvl14 = NULL;
30static unsigned long obp_lvl14[4]; 32static unsigned long obp_lvl14[4];
diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c
index f2fdbb3664d3..6a2513321620 100644
--- a/arch/sparc/kernel/time.c
+++ b/arch/sparc/kernel/time.c
@@ -44,6 +44,8 @@
44#include <asm/of_device.h> 44#include <asm/of_device.h>
45#include <asm/irq_regs.h> 45#include <asm/irq_regs.h>
46 46
47#include "irq.h"
48
47DEFINE_SPINLOCK(rtc_lock); 49DEFINE_SPINLOCK(rtc_lock);
48enum sparc_clock_type sp_clock_typ; 50enum sparc_clock_type sp_clock_typ;
49DEFINE_SPINLOCK(mostek_lock); 51DEFINE_SPINLOCK(mostek_lock);
diff --git a/include/asm-sparc/irq.h b/include/asm-sparc/irq.h
index ff520ea97473..45827934f7bc 100644
--- a/include/asm-sparc/irq.h
+++ b/include/asm-sparc/irq.h
@@ -14,9 +14,6 @@
14#include <asm/system.h> /* For SUN4M_NCPUS */ 14#include <asm/system.h> /* For SUN4M_NCPUS */
15#include <asm/btfixup.h> 15#include <asm/btfixup.h>
16 16
17#define __irq_ino(irq) irq
18#define __irq_pil(irq) irq
19
20#define NR_IRQS 16 17#define NR_IRQS 16
21 18
22#define irq_canonicalize(irq) (irq) 19#define irq_canonicalize(irq) (irq)
@@ -30,11 +27,6 @@
30 */ 27 */
31BTFIXUPDEF_CALL(void, disable_irq, unsigned int) 28BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
32BTFIXUPDEF_CALL(void, enable_irq, unsigned int) 29BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
33BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
34BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
35BTFIXUPDEF_CALL(void, clear_clock_irq, void)
36BTFIXUPDEF_CALL(void, clear_profile_irq, int)
37BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
38 30
39static inline void disable_irq_nosync(unsigned int irq) 31static inline void disable_irq_nosync(unsigned int irq)
40{ 32{
@@ -51,134 +43,6 @@ static inline void enable_irq(unsigned int irq)
51 BTFIXUP_CALL(enable_irq)(irq); 43 BTFIXUP_CALL(enable_irq)(irq);
52} 44}
53 45
54static inline void disable_pil_irq(unsigned int irq)
55{
56 BTFIXUP_CALL(disable_pil_irq)(irq);
57}
58
59static inline void enable_pil_irq(unsigned int irq)
60{
61 BTFIXUP_CALL(enable_pil_irq)(irq);
62}
63
64static inline void clear_clock_irq(void)
65{
66 BTFIXUP_CALL(clear_clock_irq)();
67}
68
69static inline void clear_profile_irq(int irq)
70{
71 BTFIXUP_CALL(clear_profile_irq)(irq);
72}
73
74static inline void load_profile_irq(int cpu, int limit)
75{
76 BTFIXUP_CALL(load_profile_irq)(cpu, limit);
77}
78
79extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);
80extern void claim_ticker14(irq_handler_t irq_handler,
81 int irq,
82 unsigned int timeout);
83
84#ifdef CONFIG_SMP
85BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
86BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
87BTFIXUPDEF_CALL(void, set_irq_udt, int)
88
89#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
90#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
91#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
92#endif
93
94extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname); 46extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname);
95 47
96/* On the sun4m, just like the timers, we have both per-cpu and master
97 * interrupt registers.
98 */
99
100/* These registers are used for sending/receiving irqs from/to
101 * different cpu's.
102 */
103struct sun4m_intreg_percpu {
104 unsigned int tbt; /* Interrupts still pending for this cpu. */
105
106 /* These next two registers are WRITE-ONLY and are only
107 * "on bit" sensitive, "off bits" written have NO affect.
108 */
109 unsigned int clear; /* Clear this cpus irqs here. */
110 unsigned int set; /* Set this cpus irqs here. */
111 unsigned char space[PAGE_SIZE - 12];
112};
113
114/*
115 * djhr
116 * Actually the clear and set fields in this struct are misleading..
117 * according to the SLAVIO manual (and the same applies for the SEC)
118 * the clear field clears bits in the mask which will ENABLE that IRQ
119 * the set field sets bits in the mask to DISABLE the IRQ.
120 *
121 * Also the undirected_xx address in the SLAVIO is defined as
122 * RESERVED and write only..
123 *
124 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
125 * sun4m machines, for MP the layout makes more sense.
126 */
127struct sun4m_intregs {
128 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
129 unsigned int tbt; /* IRQ's that are still pending. */
130 unsigned int irqs; /* Master IRQ bits. */
131
132 /* Again, like the above, two these registers are WRITE-ONLY. */
133 unsigned int clear; /* Clear master IRQ's by setting bits here. */
134 unsigned int set; /* Set master IRQ's by setting bits here. */
135
136 /* This register is both READ and WRITE. */
137 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
138};
139
140extern struct sun4m_intregs *sun4m_interrupts;
141
142/*
143 * Bit field defines for the interrupt registers on various
144 * Sparc machines.
145 */
146
147/* The sun4c interrupt register. */
148#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
149#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
150#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
151#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
152#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
153#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
154#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
155
156/* Dave Redman (djhr@tadpole.co.uk)
157 * The sun4m interrupt registers.
158 */
159#define SUN4M_INT_ENABLE 0x80000000
160#define SUN4M_INT_E14 0x00000080
161#define SUN4M_INT_E10 0x00080000
162
163#define SUN4M_HARD_INT(x) (0x000000001 << (x))
164#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
165
166#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
167#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
168#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
169#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
170#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
171#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
172#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
173#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
174#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
175#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
176#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
177#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
178#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
179#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
180
181#define SUN4M_INT_SBUS(x) (1 << (x+7))
182#define SUN4M_INT_VME(x) (1 << (x))
183
184#endif 48#endif
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