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-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/boards/renesas/rts7751r2d/irq.c4
-rw-r--r--arch/sh/boards/renesas/rts7751r2d/setup.c73
-rw-r--r--arch/sh/cchips/voyagergx/Makefile9
-rw-r--r--arch/sh/cchips/voyagergx/consistent.c121
-rw-r--r--arch/sh/cchips/voyagergx/irq.c101
-rw-r--r--arch/sh/cchips/voyagergx/setup.c37
-rw-r--r--include/asm-sh/voyagergx.h341
8 files changed, 39 insertions, 648 deletions
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 292d8618248d..e04b19293652 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -138,7 +138,6 @@ endif
138 138
139# Companion chips 139# Companion chips
140core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/ 140core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
141core-$(CONFIG_MFD_SM501) += arch/sh/cchips/voyagergx/
142 141
143cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2 142cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2
144cpuincdir-$(CONFIG_CPU_SH2A) := cpu-sh2a 143cpuincdir-$(CONFIG_CPU_SH2A) := cpu-sh2a
diff --git a/arch/sh/boards/renesas/rts7751r2d/irq.c b/arch/sh/boards/renesas/rts7751r2d/irq.c
index 3fecd49e0d2a..8e49f6e51247 100644
--- a/arch/sh/boards/renesas/rts7751r2d/irq.c
+++ b/arch/sh/boards/renesas/rts7751r2d/irq.c
@@ -13,7 +13,6 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/voyagergx.h>
17#include <asm/rts7751r2d.h> 16#include <asm/rts7751r2d.h>
18 17
19#define R2D_NR_IRL 13 18#define R2D_NR_IRL 13
@@ -153,7 +152,4 @@ void __init init_rts7751r2d_IRQ(void)
153 } 152 }
154 153
155 register_intc_controller(d); 154 register_intc_controller(d);
156#ifdef CONFIG_MFD_SM501
157 setup_voyagergx_irq();
158#endif
159} 155}
diff --git a/arch/sh/boards/renesas/rts7751r2d/setup.c b/arch/sh/boards/renesas/rts7751r2d/setup.c
index dc143c10cd18..8cb496617073 100644
--- a/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ b/arch/sh/boards/renesas/rts7751r2d/setup.c
@@ -13,36 +13,13 @@
13#include <linux/pata_platform.h> 13#include <linux/pata_platform.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/sm501.h> 15#include <linux/sm501.h>
16#include <linux/sm501-regs.h>
16#include <linux/pm.h> 17#include <linux/pm.h>
17#include <linux/fb.h> 18#include <linux/fb.h>
18#include <asm/machvec.h> 19#include <asm/machvec.h>
19#include <asm/rts7751r2d.h> 20#include <asm/rts7751r2d.h>
20#include <asm/voyagergx.h>
21#include <asm/io.h> 21#include <asm/io.h>
22 22
23static void __init voyagergx_serial_init(void)
24{
25 unsigned long val;
26
27 /*
28 * GPIO Control
29 */
30 val = readl((void __iomem *)GPIO_MUX_HIGH);
31 val |= 0x00001fe0;
32 writel(val, (void __iomem *)GPIO_MUX_HIGH);
33
34 /*
35 * Power Mode Gate
36 */
37 val = readl((void __iomem *)POWER_MODE0_GATE);
38 val |= (POWER_MODE0_GATE_U0 | POWER_MODE0_GATE_U1);
39 writel(val, (void __iomem *)POWER_MODE0_GATE);
40
41 val = readl((void __iomem *)POWER_MODE1_GATE);
42 val |= (POWER_MODE1_GATE_U0 | POWER_MODE1_GATE_U1);
43 writel(val, (void __iomem *)POWER_MODE1_GATE);
44}
45
46static struct resource cf_ide_resources[] = { 23static struct resource cf_ide_resources[] = {
47 [0] = { 24 [0] = {
48 .start = PA_AREA5_IO + 0x1000, 25 .start = PA_AREA5_IO + 0x1000,
@@ -94,11 +71,11 @@ static struct platform_device heartbeat_device = {
94#ifdef CONFIG_MFD_SM501 71#ifdef CONFIG_MFD_SM501
95static struct plat_serial8250_port uart_platform_data[] = { 72static struct plat_serial8250_port uart_platform_data[] = {
96 { 73 {
97 .membase = (void __iomem *)VOYAGER_UART_BASE, 74 .membase = (void __iomem *)0xb3e30000,
98 .mapbase = VOYAGER_UART_BASE, 75 .mapbase = 0xb3e30000,
99 .iotype = UPIO_MEM, 76 .iotype = UPIO_MEM,
100 .irq = IRQ_SM501_U0, 77 .irq = IRQ_VOYAGER,
101 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 78 .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
102 .regshift = 2, 79 .regshift = 2,
103 .uartclk = (9600 * 16), 80 .uartclk = (9600 * 16),
104 }, 81 },
@@ -125,7 +102,7 @@ static struct resource sm501_resources[] = {
125 .flags = IORESOURCE_MEM, 102 .flags = IORESOURCE_MEM,
126 }, 103 },
127 [2] = { 104 [2] = {
128 .start = IRQ_SM501_CV, 105 .start = IRQ_VOYAGER,
129 .flags = IORESOURCE_IRQ, 106 .flags = IORESOURCE_IRQ,
130 }, 107 },
131}; 108};
@@ -167,7 +144,15 @@ static struct sm501_platdata_fb sm501_fb_pdata = {
167 .flags = SM501_FBPD_SWAP_FB_ENDIAN, 144 .flags = SM501_FBPD_SWAP_FB_ENDIAN,
168}; 145};
169 146
147static struct sm501_initdata sm501_initdata = {
148 .gpio_high = {
149 .set = 0x00001fe0,
150 .mask = 0x0,
151 },
152};
153
170static struct sm501_platdata sm501_platform_data = { 154static struct sm501_platdata sm501_platform_data = {
155 .init = &sm501_initdata,
171 .fb = &sm501_fb_pdata, 156 .fb = &sm501_fb_pdata,
172}; 157};
173 158
@@ -237,6 +222,7 @@ u8 rts7751r2d_readb(void __iomem *addr)
237 */ 222 */
238static void __init rts7751r2d_setup(char **cmdline_p) 223static void __init rts7751r2d_setup(char **cmdline_p)
239{ 224{
225 void __iomem *sm501_reg;
240 u16 ver = ctrl_inw(PA_VERREG); 226 u16 ver = ctrl_inw(PA_VERREG);
241 227
242 printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n"); 228 printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n");
@@ -247,7 +233,30 @@ static void __init rts7751r2d_setup(char **cmdline_p)
247 ctrl_outw(0x0000, PA_OUTPORT); 233 ctrl_outw(0x0000, PA_OUTPORT);
248 pm_power_off = rts7751r2d_power_off; 234 pm_power_off = rts7751r2d_power_off;
249 235
250 voyagergx_serial_init(); 236 /* sm501 dram configuration:
237 * ColSizeX = 11 - External Memory Column Size: 256 words.
238 * APX = 1 - External Memory Active to Pre-Charge Delay: 7 clocks.
239 * RstX = 1 - External Memory Reset: Normal.
240 * Rfsh = 1 - Local Memory Refresh to Command Delay: 12 clocks.
241 * BwC = 1 - Local Memory Block Write Cycle Time: 2 clocks.
242 * BwP = 1 - Local Memory Block Write to Pre-Charge Delay: 1 clock.
243 * AP = 1 - Internal Memory Active to Pre-Charge Delay: 7 clocks.
244 * Rst = 1 - Internal Memory Reset: Normal.
245 * RA = 1 - Internal Memory Remain in Active State: Do not remain.
246 */
247
248 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
249 writel(readl(sm501_reg) | 0x00f107c0, sm501_reg);
250
251 /*
252 * Power Mode Gate - Enable UART0
253 */
254
255 sm501_reg = (void __iomem *)0xb3e00000 + SM501_POWER_MODE_0_GATE;
256 writel(readl(sm501_reg) | (1 << SM501_GATE_UART0), sm501_reg);
257
258 sm501_reg = (void __iomem *)0xb3e00000 + SM501_POWER_MODE_1_GATE;
259 writel(readl(sm501_reg) | (1 << SM501_GATE_UART0), sm501_reg);
251} 260}
252 261
253/* 262/*
@@ -260,8 +269,4 @@ static struct sh_machine_vector mv_rts7751r2d __initmv = {
260 .mv_irq_demux = rts7751r2d_irq_demux, 269 .mv_irq_demux = rts7751r2d_irq_demux,
261 .mv_writeb = rts7751r2d_writeb, 270 .mv_writeb = rts7751r2d_writeb,
262 .mv_readb = rts7751r2d_readb, 271 .mv_readb = rts7751r2d_readb,
263#if defined(CONFIG_MFD_SM501) && defined(CONFIG_USB_OHCI_HCD)
264 .mv_consistent_alloc = voyagergx_consistent_alloc,
265 .mv_consistent_free = voyagergx_consistent_free,
266#endif
267}; 272};
diff --git a/arch/sh/cchips/voyagergx/Makefile b/arch/sh/cchips/voyagergx/Makefile
deleted file mode 100644
index f73963cb3744..000000000000
--- a/arch/sh/cchips/voyagergx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Makefile for VoyagerGX
3#
4
5obj-y := irq.o setup.o
6
7obj-$(CONFIG_USB_OHCI_HCD) += consistent.o
8
9EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/cchips/voyagergx/consistent.c b/arch/sh/cchips/voyagergx/consistent.c
deleted file mode 100644
index 07e8b9c5a531..000000000000
--- a/arch/sh/cchips/voyagergx/consistent.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * arch/sh/cchips/voyagergx/consistent.c
3 *
4 * Copyright (C) 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/mm.h>
11#include <linux/dma-mapping.h>
12#include <linux/slab.h>
13#include <linux/list.h>
14#include <linux/types.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <asm/io.h>
18
19
20struct voya_alloc_entry {
21 struct list_head list;
22 unsigned long ofs;
23 unsigned long len;
24};
25
26static DEFINE_SPINLOCK(voya_list_lock);
27static LIST_HEAD(voya_alloc_list);
28
29#define OHCI_SRAM_START 0xb0000000
30#define OHCI_HCCA_SIZE 0x100
31#define OHCI_SRAM_SIZE 0x10000
32
33#define VOYAGER_OHCI_NAME "voyager-ohci"
34
35void *voyagergx_consistent_alloc(struct device *dev, size_t size,
36 dma_addr_t *handle, gfp_t flag)
37{
38 struct list_head *list = &voya_alloc_list;
39 struct voya_alloc_entry *entry;
40 unsigned long start, end;
41 unsigned long flags;
42
43 /*
44 * The SM501 contains an integrated 8051 with its own SRAM.
45 * Devices within the cchip can all hook into the 8051 SRAM.
46 * We presently use this for the OHCI.
47 *
48 * Everything else goes through consistent_alloc().
49 */
50 if (!dev || strcmp(dev->driver->name, VOYAGER_OHCI_NAME))
51 return NULL;
52
53 start = OHCI_SRAM_START + OHCI_HCCA_SIZE;
54
55 entry = kmalloc(sizeof(struct voya_alloc_entry), GFP_ATOMIC);
56 if (!entry)
57 return ERR_PTR(-ENOMEM);
58
59 entry->len = (size + 15) & ~15;
60
61 /*
62 * The basis for this allocator is dwmw2's malloc.. the
63 * Matrox allocator :-)
64 */
65 spin_lock_irqsave(&voya_list_lock, flags);
66 list_for_each(list, &voya_alloc_list) {
67 struct voya_alloc_entry *p;
68
69 p = list_entry(list, struct voya_alloc_entry, list);
70
71 if (p->ofs - start >= size)
72 goto out;
73
74 start = p->ofs + p->len;
75 }
76
77 end = start + (OHCI_SRAM_SIZE - OHCI_HCCA_SIZE);
78 list = &voya_alloc_list;
79
80 if (end - start >= size) {
81out:
82 entry->ofs = start;
83 list_add_tail(&entry->list, list);
84 spin_unlock_irqrestore(&voya_list_lock, flags);
85
86 *handle = start;
87 return (void *)start;
88 }
89
90 kfree(entry);
91 spin_unlock_irqrestore(&voya_list_lock, flags);
92
93 return ERR_PTR(-EINVAL);
94}
95
96int voyagergx_consistent_free(struct device *dev, size_t size,
97 void *vaddr, dma_addr_t handle)
98{
99 struct voya_alloc_entry *entry;
100 unsigned long flags;
101
102 if (!dev || strcmp(dev->driver->name, VOYAGER_OHCI_NAME))
103 return -EINVAL;
104
105 spin_lock_irqsave(&voya_list_lock, flags);
106 list_for_each_entry(entry, &voya_alloc_list, list) {
107 if (entry->ofs != handle)
108 continue;
109
110 list_del(&entry->list);
111 kfree(entry);
112
113 break;
114 }
115 spin_unlock_irqrestore(&voya_list_lock, flags);
116
117 return 0;
118}
119
120EXPORT_SYMBOL(voyagergx_consistent_alloc);
121EXPORT_SYMBOL(voyagergx_consistent_free);
diff --git a/arch/sh/cchips/voyagergx/irq.c b/arch/sh/cchips/voyagergx/irq.c
deleted file mode 100644
index e7e78c612fad..000000000000
--- a/arch/sh/cchips/voyagergx/irq.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/* -------------------------------------------------------------------- */
2/* setup_voyagergx.c: */
3/* -------------------------------------------------------------------- */
4/* This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 Copyright 2003 (c) Lineo uSolutions,Inc.
19*/
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <asm/voyagergx.h>
24#include <asm/rts7751r2d.h>
25
26enum {
27 UNUSED = 0,
28
29 /* voyager specific interrupt sources */
30 UP, G54, G53, G52, G51, G50, G49, G48,
31 I2C, PW, DMA, PCI, I2S, AC, US,
32 U1, U0, CV, MC, S1, S0,
33 UH, TWOD, ZD, PV, CI,
34};
35
36static struct intc_vect vectors[] __initdata = {
37 INTC_IRQ(UP, IRQ_SM501_UP), INTC_IRQ(G54, IRQ_SM501_G54),
38 INTC_IRQ(G53, IRQ_SM501_G53), INTC_IRQ(G52, IRQ_SM501_G52),
39 INTC_IRQ(G51, IRQ_SM501_G51), INTC_IRQ(G50, IRQ_SM501_G50),
40 INTC_IRQ(G49, IRQ_SM501_G49), INTC_IRQ(G48, IRQ_SM501_G48),
41 INTC_IRQ(I2C, IRQ_SM501_I2C), INTC_IRQ(PW, IRQ_SM501_PW),
42 INTC_IRQ(DMA, IRQ_SM501_DMA), INTC_IRQ(PCI, IRQ_SM501_PCI),
43 INTC_IRQ(I2S, IRQ_SM501_I2S), INTC_IRQ(AC, IRQ_SM501_AC),
44 INTC_IRQ(US, IRQ_SM501_US), INTC_IRQ(U1, IRQ_SM501_U1),
45 INTC_IRQ(U0, IRQ_SM501_U0), INTC_IRQ(CV, IRQ_SM501_CV),
46 INTC_IRQ(MC, IRQ_SM501_MC), INTC_IRQ(S1, IRQ_SM501_S1),
47 INTC_IRQ(S0, IRQ_SM501_S0), INTC_IRQ(UH, IRQ_SM501_UH),
48 INTC_IRQ(TWOD, IRQ_SM501_2D), INTC_IRQ(ZD, IRQ_SM501_ZD),
49 INTC_IRQ(PV, IRQ_SM501_PV), INTC_IRQ(CI, IRQ_SM501_CI),
50};
51
52static struct intc_mask_reg mask_registers[] __initdata = {
53 { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
54 { UP, G54, G53, G52, G51, G50, G49, G48,
55 I2C, PW, 0, DMA, PCI, I2S, AC, US,
56 0, 0, U1, U0, CV, MC, S1, S0,
57 0, UH, 0, 0, TWOD, ZD, PV, CI } },
58};
59
60static DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
61 NULL, mask_registers, NULL, NULL);
62
63static unsigned int voyagergx_stat2irq[32] = {
64 IRQ_SM501_CI, IRQ_SM501_PV, IRQ_SM501_ZD, IRQ_SM501_2D,
65 0, 0, IRQ_SM501_UH, 0,
66 IRQ_SM501_S0, IRQ_SM501_S1, IRQ_SM501_MC, IRQ_SM501_CV,
67 IRQ_SM501_U0, IRQ_SM501_U1, 0, 0,
68 IRQ_SM501_US, IRQ_SM501_AC, IRQ_SM501_I2S, IRQ_SM501_PCI,
69 IRQ_SM501_DMA, 0, IRQ_SM501_PW, IRQ_SM501_I2C,
70 IRQ_SM501_G48, IRQ_SM501_G49, IRQ_SM501_G50, IRQ_SM501_G51,
71 IRQ_SM501_G52, IRQ_SM501_G53, IRQ_SM501_G54, IRQ_SM501_UP
72};
73
74static void voyagergx_irq_demux(unsigned int irq, struct irq_desc *desc)
75{
76 unsigned long intv = ctrl_inl(INT_STATUS);
77 struct irq_desc *ext_desc;
78 unsigned int ext_irq;
79 unsigned int k = 0;
80
81 while (intv) {
82 ext_irq = voyagergx_stat2irq[k];
83 if (ext_irq && (intv & 1)) {
84 ext_desc = irq_desc + ext_irq;
85 handle_level_irq(ext_irq, ext_desc);
86 }
87 intv >>= 1;
88 k++;
89 }
90}
91
92void __init setup_voyagergx_irq(void)
93{
94 printk(KERN_INFO "VoyagerGX on irq %d (mapped into %d to %d)\n",
95 IRQ_VOYAGER,
96 VOYAGER_IRQ_BASE,
97 VOYAGER_IRQ_BASE + VOYAGER_IRQ_NUM - 1);
98
99 register_intc_controller(&intc_desc);
100 set_irq_chained_handler(IRQ_VOYAGER, voyagergx_irq_demux);
101}
diff --git a/arch/sh/cchips/voyagergx/setup.c b/arch/sh/cchips/voyagergx/setup.c
deleted file mode 100644
index 33f03027c193..000000000000
--- a/arch/sh/cchips/voyagergx/setup.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * arch/sh/cchips/voyagergx/setup.c
3 *
4 * Setup routines for VoyagerGX cchip.
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/module.h>
15#include <asm/io.h>
16#include <asm/voyagergx.h>
17
18static int __init setup_voyagergx(void)
19{
20 unsigned long val;
21
22 val = readl((void __iomem *)DRAM_CTRL);
23 val |= (DRAM_CTRL_CPU_COLUMN_SIZE_256 |
24 DRAM_CTRL_CPU_ACTIVE_PRECHARGE |
25 DRAM_CTRL_CPU_RESET |
26 DRAM_CTRL_REFRESH_COMMAND |
27 DRAM_CTRL_BLOCK_WRITE_TIME |
28 DRAM_CTRL_BLOCK_WRITE_PRECHARGE |
29 DRAM_CTRL_ACTIVE_PRECHARGE |
30 DRAM_CTRL_RESET |
31 DRAM_CTRL_REMAIN_ACTIVE);
32 writel(val, (void __iomem *)DRAM_CTRL);
33
34 return 0;
35}
36
37module_init(setup_voyagergx);
diff --git a/include/asm-sh/voyagergx.h b/include/asm-sh/voyagergx.h
deleted file mode 100644
index 45b4547c74ac..000000000000
--- a/include/asm-sh/voyagergx.h
+++ /dev/null
@@ -1,341 +0,0 @@
1/* -------------------------------------------------------------------- */
2/* voyagergx.h */
3/* -------------------------------------------------------------------- */
4/* This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 Copyright 2003 (c) Lineo uSolutions,Inc.
19*/
20/* -------------------------------------------------------------------- */
21
22#ifndef _VOYAGER_GX_REG_H
23#define _VOYAGER_GX_REG_H
24
25#define VOYAGER_BASE 0xb3e00000
26#define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE)
27#define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE)
28#define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE)
29
30#define VOYAGER_IRQ_NUM 26
31#define VOYAGER_IRQ_BASE 200
32
33#define IRQ_SM501_UP (VOYAGER_IRQ_BASE + 0)
34#define IRQ_SM501_G54 (VOYAGER_IRQ_BASE + 1)
35#define IRQ_SM501_G53 (VOYAGER_IRQ_BASE + 2)
36#define IRQ_SM501_G52 (VOYAGER_IRQ_BASE + 3)
37#define IRQ_SM501_G51 (VOYAGER_IRQ_BASE + 4)
38#define IRQ_SM501_G50 (VOYAGER_IRQ_BASE + 5)
39#define IRQ_SM501_G49 (VOYAGER_IRQ_BASE + 6)
40#define IRQ_SM501_G48 (VOYAGER_IRQ_BASE + 7)
41#define IRQ_SM501_I2C (VOYAGER_IRQ_BASE + 8)
42#define IRQ_SM501_PW (VOYAGER_IRQ_BASE + 9)
43#define IRQ_SM501_DMA (VOYAGER_IRQ_BASE + 10)
44#define IRQ_SM501_PCI (VOYAGER_IRQ_BASE + 11)
45#define IRQ_SM501_I2S (VOYAGER_IRQ_BASE + 12)
46#define IRQ_SM501_AC (VOYAGER_IRQ_BASE + 13)
47#define IRQ_SM501_US (VOYAGER_IRQ_BASE + 14)
48#define IRQ_SM501_U1 (VOYAGER_IRQ_BASE + 15)
49#define IRQ_SM501_U0 (VOYAGER_IRQ_BASE + 16)
50#define IRQ_SM501_CV (VOYAGER_IRQ_BASE + 17)
51#define IRQ_SM501_MC (VOYAGER_IRQ_BASE + 18)
52#define IRQ_SM501_S1 (VOYAGER_IRQ_BASE + 19)
53#define IRQ_SM501_S0 (VOYAGER_IRQ_BASE + 20)
54#define IRQ_SM501_UH (VOYAGER_IRQ_BASE + 21)
55#define IRQ_SM501_2D (VOYAGER_IRQ_BASE + 22)
56#define IRQ_SM501_ZD (VOYAGER_IRQ_BASE + 23)
57#define IRQ_SM501_PV (VOYAGER_IRQ_BASE + 24)
58#define IRQ_SM501_CI (VOYAGER_IRQ_BASE + 25)
59
60/* ----- MISC controle register ------------------------------ */
61#define MISC_CTRL (0x000004 + VOYAGER_BASE)
62#define MISC_CTRL_USBCLK_48 (3 << 28)
63#define MISC_CTRL_USBCLK_96 (2 << 28)
64#define MISC_CTRL_USBCLK_CRYSTAL (1 << 28)
65
66/* ----- GPIO[31:0] register --------------------------------- */
67#define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE)
68#define GPIO_MUX_LOW_AC97 0x1F000000
69#define GPIO_MUX_LOW_8051 0x0000ffff
70#define GPIO_MUX_LOW_PWM (1 << 29)
71
72/* ----- GPIO[63:32] register --------------------------------- */
73#define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE)
74
75/* ----- DRAM controle register ------------------------------- */
76#define DRAM_CTRL (0x000010 + VOYAGER_BASE)
77#define DRAM_CTRL_EMBEDDED (1 << 31)
78#define DRAM_CTRL_CPU_BURST_1 (0 << 28)
79#define DRAM_CTRL_CPU_BURST_2 (1 << 28)
80#define DRAM_CTRL_CPU_BURST_4 (2 << 28)
81#define DRAM_CTRL_CPU_BURST_8 (3 << 28)
82#define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27)
83#define DRAM_CTRL_CPU_SIZE_2 (0 << 24)
84#define DRAM_CTRL_CPU_SIZE_4 (1 << 24)
85#define DRAM_CTRL_CPU_SIZE_64 (4 << 24)
86#define DRAM_CTRL_CPU_SIZE_32 (5 << 24)
87#define DRAM_CTRL_CPU_SIZE_16 (6 << 24)
88#define DRAM_CTRL_CPU_SIZE_8 (7 << 24)
89#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22)
90#define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22)
91#define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22)
92#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21)
93#define DRAM_CTRL_CPU_RESET (1 << 20)
94#define DRAM_CTRL_CPU_BANKS (1 << 19)
95#define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18)
96#define DRAM_CTRL_BLOCK_WRITE (1 << 17)
97#define DRAM_CTRL_REFRESH_COMMAND (1 << 16)
98#define DRAM_CTRL_SIZE_4 (0 << 13)
99#define DRAM_CTRL_SIZE_8 (1 << 13)
100#define DRAM_CTRL_SIZE_16 (2 << 13)
101#define DRAM_CTRL_SIZE_32 (3 << 13)
102#define DRAM_CTRL_SIZE_64 (4 << 13)
103#define DRAM_CTRL_SIZE_2 (5 << 13)
104#define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11)
105#define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11)
106#define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11)
107#define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10)
108#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9)
109#define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8)
110#define DRAM_CTRL_RESET (1 << 7)
111#define DRAM_CTRL_REMAIN_ACTIVE (1 << 6)
112#define DRAM_CTRL_BANKS (1 << 1)
113#define DRAM_CTRL_WRITE_PRECHARGE (1 << 0)
114
115/* ----- Arvitration control register -------------------------- */
116#define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE)
117#define ARBITRATION_CTRL_CPUMEM (1 << 29)
118#define ARBITRATION_CTRL_INTMEM (1 << 28)
119#define ARBITRATION_CTRL_USB_OFF (0 << 24)
120#define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24)
121#define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24)
122#define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24)
123#define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24)
124#define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24)
125#define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24)
126#define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24)
127#define ARBITRATION_CTRL_PANEL_OFF (0 << 20)
128#define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20)
129#define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20)
130#define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20)
131#define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20)
132#define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20)
133#define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20)
134#define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20)
135#define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16)
136#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16)
137#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16)
138#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16)
139#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16)
140#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16)
141#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16)
142#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16)
143#define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12)
144#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12)
145#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12)
146#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12)
147#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12)
148#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12)
149#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12)
150#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12)
151#define ARBITRATION_CTRL_DMA_OFF (0 << 8)
152#define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8)
153#define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8)
154#define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8)
155#define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8)
156#define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8)
157#define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8)
158#define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8)
159#define ARBITRATION_CTRL_VIDEO_OFF (0 << 4)
160#define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4)
161#define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4)
162#define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4)
163#define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4)
164#define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4)
165#define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4)
166#define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4)
167#define ARBITRATION_CTRL_CRT_OFF (0 << 0)
168#define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0)
169#define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0)
170#define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0)
171#define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0)
172#define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0)
173#define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0)
174#define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0)
175
176/* ----- Command list status register -------------------------- */
177#define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE)
178
179/* ----- Interrupt status register ----------------------------- */
180#define INT_STATUS (0x00002c + VOYAGER_BASE)
181#define INT_STATUS_UH (1 << 6)
182#define INT_STATUS_MC (1 << 10)
183#define INT_STATUS_U0 (1 << 12)
184#define INT_STATUS_U1 (1 << 13)
185#define INT_STATUS_AC (1 << 17)
186
187/* ----- Interrupt mask register ------------------------------ */
188#define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE)
189#define VOYAGER_INT_MASK_AC (1 << 17)
190
191/* ----- Current Gate register ---------------------------------*/
192#define CURRENT_GATE (0x000038 + VOYAGER_BASE)
193
194/* ----- Power mode 0 gate register --------------------------- */
195#define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE)
196#define POWER_MODE0_GATE_G (1 << 6)
197#define POWER_MODE0_GATE_U0 (1 << 7)
198#define POWER_MODE0_GATE_U1 (1 << 8)
199#define POWER_MODE0_GATE_UH (1 << 11)
200#define POWER_MODE0_GATE_AC (1 << 18)
201
202/* ----- Power mode 1 gate register --------------------------- */
203#define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE)
204#define POWER_MODE1_GATE_G (1 << 6)
205#define POWER_MODE1_GATE_U0 (1 << 7)
206#define POWER_MODE1_GATE_U1 (1 << 8)
207#define POWER_MODE1_GATE_UH (1 << 11)
208#define POWER_MODE1_GATE_AC (1 << 18)
209
210/* ----- Power mode 0 clock register -------------------------- */
211#define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE)
212
213/* ----- Power mode 1 clock register -------------------------- */
214#define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE)
215
216/* ----- Power mode control register ------------------------- */
217#define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE)
218
219/* ----- Miscellaneous Timing register ------------------------ */
220#define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE)
221
222/* ----- PWM register ------------------------------------------*/
223#define PWM_0 (0x010020 + VOYAGER_BASE)
224#define PWM_0_HC(x) (((x)&0x0fff)<<20)
225#define PWM_0_LC(x) (((x)&0x0fff)<<8 )
226#define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 )
227#define PWM_0_EN (1<<0)
228
229/* ----- I2C register ----------------------------------------- */
230#define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE)
231#define I2C_CONTROL (0x010041 + VOYAGER_BASE)
232#define I2C_STATUS (0x010042 + VOYAGER_BASE)
233#define I2C_RESET (0x010042 + VOYAGER_BASE)
234#define I2C_SADDRESS (0x010043 + VOYAGER_BASE)
235#define I2C_DATA (0x010044 + VOYAGER_BASE)
236
237/* ----- Controle register bits ----------------------------------------- */
238#define I2C_CONTROL_E (1 << 0)
239#define I2C_CONTROL_MODE (1 << 1)
240#define I2C_CONTROL_STATUS (1 << 2)
241#define I2C_CONTROL_INT (1 << 4)
242#define I2C_CONTROL_INTACK (1 << 5)
243#define I2C_CONTROL_REPEAT (1 << 6)
244
245/* ----- Status register bits ----------------------------------------- */
246#define I2C_STATUS_BUSY (1 << 0)
247#define I2C_STATUS_ACK (1 << 1)
248#define I2C_STATUS_ERROR (1 << 2)
249#define I2C_STATUS_COMPLETE (1 << 3)
250
251/* ----- Reset register ---------------------------------------------- */
252#define I2C_RESET_ERROR (1 << 2)
253
254/* ----- transmission frequencies ------------------------------------- */
255#define I2C_SADDRESS_SELECT (1 << 0)
256
257/* ----- Display Controll register ----------------------------------------- */
258#define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE)
259#define PANEL_DISPLAY_CTRL_BIAS (1<<26)
260#define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE)
261#define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE)
262#define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE)
263#define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE)
264#define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE)
265#define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE)
266#define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE)
267#define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE)
268#define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE)
269#define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE)
270#define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE)
271#define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE)
272#define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE)
273#define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE)
274#define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE)
275#define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE)
276#define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE)
277#define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE)
278#define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE)
279#define VIDEO_SCALE (0x080058 + VOYAGER_BASE)
280#define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE)
281#define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE)
282#define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE)
283#define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE)
284#define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE)
285#define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE)
286#define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE)
287#define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE)
288#define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE)
289#define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE)
290#define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE)
291#define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE)
292#define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE)
293#define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE)
294#define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE)
295#define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE)
296#define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE)
297#define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE)
298#define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE)
299#define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE)
300#define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE)
301#define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE)
302#define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE)
303#define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE)
304#define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE)
305#define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE)
306#define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE)
307#define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE)
308#define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE)
309#define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE)
310#define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE)
311#define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE)
312#define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE)
313#define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE)
314#define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE)
315#define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE)
316#define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE)
317#define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE)
318#define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE)
319#define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE)
320
321/* ----- 8051 Controle register ----------------------------------------- */
322#define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE)
323#define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE)
324#define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE)
325#define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE)
326
327/* ----- AC97 Controle register ----------------------------------------- */
328#define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE)
329#define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE)
330#define AC97C_READ (1 << 19)
331#define AC97C_WD_BIT (1 << 2)
332#define AC97C_INDEX_MASK 0x7f
333
334/* arch/sh/cchips/voyagergx/consistent.c */
335void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t);
336int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t);
337
338/* arch/sh/cchips/voyagergx/irq.c */
339void setup_voyagergx_irq(void);
340
341#endif /* _VOYAGER_GX_REG_H */
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