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-rw-r--r--drivers/i2c/busses/Kconfig12
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-stu300.c1029
3 files changed, 1042 insertions, 0 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 0d04d3ebfc2d..0e0a39040835 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -513,6 +513,18 @@ config I2C_SIMTEC
513 This driver can also be built as a module. If so, the module 513 This driver can also be built as a module. If so, the module
514 will be called i2c-simtec. 514 will be called i2c-simtec.
515 515
516config I2C_STU300
517 tristate "ST Microelectronics DDC I2C interface"
518 default y if MACH_U300
519 help
520 If you say yes to this option, support will be included for the
521 I2C interface from ST Microelectronics simply called "DDC I2C"
522 supporting both I2C and DDC, used in e.g. the U300 series
523 mobile platforms.
524
525 This driver can also be built as a module. If so, the module
526 will be called i2c-stu300.
527
516config I2C_VERSATILE 528config I2C_VERSATILE
517 tristate "ARM Versatile/Realview I2C bus support" 529 tristate "ARM Versatile/Realview I2C bus support"
518 depends on ARCH_VERSATILE || ARCH_REALVIEW 530 depends on ARCH_VERSATILE || ARCH_REALVIEW
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 776acb6403a7..edeabf003106 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
48obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o 48obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
49obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o 49obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
50obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 50obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
51obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
51obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 52obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
52 53
53# External I2C/SMBus adapter drivers 54# External I2C/SMBus adapter drivers
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
new file mode 100644
index 000000000000..182e711318ba
--- /dev/null
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -0,0 +1,1029 @@
1/*
2 * Copyright (C) 2007-2009 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/spinlock.h>
14#include <linux/completion.h>
15#include <linux/err.h>
16#include <linux/interrupt.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19
20/* the name of this kernel module */
21#define NAME "stu300"
22
23/* CR (Control Register) 8bit (R/W) */
24#define I2C_CR (0x00000000)
25#define I2C_CR_RESET_VALUE (0x00)
26#define I2C_CR_RESET_UMASK (0x00)
27#define I2C_CR_DDC1_ENABLE (0x80)
28#define I2C_CR_TRANS_ENABLE (0x40)
29#define I2C_CR_PERIPHERAL_ENABLE (0x20)
30#define I2C_CR_DDC2B_ENABLE (0x10)
31#define I2C_CR_START_ENABLE (0x08)
32#define I2C_CR_ACK_ENABLE (0x04)
33#define I2C_CR_STOP_ENABLE (0x02)
34#define I2C_CR_INTERRUPT_ENABLE (0x01)
35/* SR1 (Status Register 1) 8bit (R/-) */
36#define I2C_SR1 (0x00000004)
37#define I2C_SR1_RESET_VALUE (0x00)
38#define I2C_SR1_RESET_UMASK (0x00)
39#define I2C_SR1_EVF_IND (0x80)
40#define I2C_SR1_ADD10_IND (0x40)
41#define I2C_SR1_TRA_IND (0x20)
42#define I2C_SR1_BUSY_IND (0x10)
43#define I2C_SR1_BTF_IND (0x08)
44#define I2C_SR1_ADSL_IND (0x04)
45#define I2C_SR1_MSL_IND (0x02)
46#define I2C_SR1_SB_IND (0x01)
47/* SR2 (Status Register 2) 8bit (R/-) */
48#define I2C_SR2 (0x00000008)
49#define I2C_SR2_RESET_VALUE (0x00)
50#define I2C_SR2_RESET_UMASK (0x40)
51#define I2C_SR2_MASK (0xBF)
52#define I2C_SR2_SCLFAL_IND (0x80)
53#define I2C_SR2_ENDAD_IND (0x20)
54#define I2C_SR2_AF_IND (0x10)
55#define I2C_SR2_STOPF_IND (0x08)
56#define I2C_SR2_ARLO_IND (0x04)
57#define I2C_SR2_BERR_IND (0x02)
58#define I2C_SR2_DDC2BF_IND (0x01)
59/* CCR (Clock Control Register) 8bit (R/W) */
60#define I2C_CCR (0x0000000C)
61#define I2C_CCR_RESET_VALUE (0x00)
62#define I2C_CCR_RESET_UMASK (0x00)
63#define I2C_CCR_MASK (0xFF)
64#define I2C_CCR_FMSM (0x80)
65#define I2C_CCR_CC_MASK (0x7F)
66/* OAR1 (Own Address Register 1) 8bit (R/W) */
67#define I2C_OAR1 (0x00000010)
68#define I2C_OAR1_RESET_VALUE (0x00)
69#define I2C_OAR1_RESET_UMASK (0x00)
70#define I2C_OAR1_ADD_MASK (0xFF)
71/* OAR2 (Own Address Register 2) 8bit (R/W) */
72#define I2C_OAR2 (0x00000014)
73#define I2C_OAR2_RESET_VALUE (0x40)
74#define I2C_OAR2_RESET_UMASK (0x19)
75#define I2C_OAR2_MASK (0xE6)
76#define I2C_OAR2_FR_25_10MHZ (0x00)
77#define I2C_OAR2_FR_10_1667MHZ (0x20)
78#define I2C_OAR2_FR_1667_2667MHZ (0x40)
79#define I2C_OAR2_FR_2667_40MHZ (0x60)
80#define I2C_OAR2_FR_40_5333MHZ (0x80)
81#define I2C_OAR2_FR_5333_66MHZ (0xA0)
82#define I2C_OAR2_FR_66_80MHZ (0xC0)
83#define I2C_OAR2_FR_80_100MHZ (0xE0)
84#define I2C_OAR2_FR_MASK (0xE0)
85#define I2C_OAR2_ADD_MASK (0x06)
86/* DR (Data Register) 8bit (R/W) */
87#define I2C_DR (0x00000018)
88#define I2C_DR_RESET_VALUE (0x00)
89#define I2C_DR_RESET_UMASK (0xFF)
90#define I2C_DR_D_MASK (0xFF)
91/* ECCR (Extended Clock Control Register) 8bit (R/W) */
92#define I2C_ECCR (0x0000001C)
93#define I2C_ECCR_RESET_VALUE (0x00)
94#define I2C_ECCR_RESET_UMASK (0xE0)
95#define I2C_ECCR_MASK (0x1F)
96#define I2C_ECCR_CC_MASK (0x1F)
97
98/*
99 * These events are more or less responses to commands
100 * sent into the hardware, presumably reflecting the state
101 * of an internal state machine.
102 */
103enum stu300_event {
104 STU300_EVENT_NONE = 0,
105 STU300_EVENT_1,
106 STU300_EVENT_2,
107 STU300_EVENT_3,
108 STU300_EVENT_4,
109 STU300_EVENT_5,
110 STU300_EVENT_6,
111 STU300_EVENT_7,
112 STU300_EVENT_8,
113 STU300_EVENT_9
114};
115
116enum stu300_error {
117 STU300_ERROR_NONE = 0,
118 STU300_ERROR_ACKNOWLEDGE_FAILURE,
119 STU300_ERROR_BUS_ERROR,
120 STU300_ERROR_ARBITRATION_LOST
121};
122
123/* timeout waiting for the controller to respond */
124#define STU300_TIMEOUT (msecs_to_jiffies(1000))
125
126/*
127 * The number of address send athemps tried before giving up.
128 * If the first one failes it seems like 5 to 8 attempts are required.
129 */
130#define NUM_ADDR_RESEND_ATTEMPTS 10
131
132/* I2C clock speed, in Hz 0-400kHz*/
133static unsigned int scl_frequency = 100000;
134module_param(scl_frequency, uint, 0644);
135
136/**
137 * struct stu300_dev - the stu300 driver state holder
138 * @pdev: parent platform device
139 * @adapter: corresponding I2C adapter
140 * @phybase: location of I/O area in memory
141 * @physize: size of I/O area in memory
142 * @clk: hardware block clock
143 * @irq: assigned interrupt line
144 * @cmd_issue_lock: this locks the following cmd_ variables
145 * @cmd_complete: acknowledge completion for an I2C command
146 * @cmd_event: expected event coming in as a response to a command
147 * @cmd_err: error code as response to a command
148 * @speed: current bus speed in Hz
149 * @msg_index: index of current message
150 * @msg_len: length of current message
151 */
152struct stu300_dev {
153 struct platform_device *pdev;
154 struct i2c_adapter adapter;
155 resource_size_t phybase;
156 resource_size_t physize;
157 void __iomem *virtbase;
158 struct clk *clk;
159 int irq;
160 spinlock_t cmd_issue_lock;
161 struct completion cmd_complete;
162 enum stu300_event cmd_event;
163 enum stu300_error cmd_err;
164 unsigned int speed;
165 int msg_index;
166 int msg_len;
167};
168
169/* Local forward function declarations */
170static int stu300_init_hw(struct stu300_dev *dev);
171
172/*
173 * The block needs writes in both MSW and LSW in order
174 * for all data lines to reach their destination.
175 */
176static inline void stu300_wr8(u32 value, void __iomem *address)
177{
178 writel((value << 16) | value, address);
179}
180
181/*
182 * This merely masks off the duplicates which appear
183 * in bytes 1-3. You _MUST_ use 32-bit bus access on this
184 * device, else it will not work.
185 */
186static inline u32 stu300_r8(void __iomem *address)
187{
188 return readl(address) & 0x000000FFU;
189}
190
191/*
192 * Tells whether a certain event or events occurred in
193 * response to a command. The events represent states in
194 * the internal state machine of the hardware. The events
195 * are not very well described in the hardware
196 * documentation and can only be treated as abstract state
197 * machine states.
198 *
199 * @ret 0 = event has not occurred, any other value means
200 * the event occurred.
201 */
202static int stu300_event_occurred(struct stu300_dev *dev,
203 enum stu300_event mr_event) {
204 u32 status1;
205 u32 status2;
206
207 /* What event happened? */
208 status1 = stu300_r8(dev->virtbase + I2C_SR1);
209 if (!(status1 & I2C_SR1_EVF_IND))
210 /* No event at all */
211 return 0;
212 status2 = stu300_r8(dev->virtbase + I2C_SR2);
213
214 switch (mr_event) {
215 case STU300_EVENT_1:
216 if (status1 & I2C_SR1_ADSL_IND)
217 return 1;
218 break;
219 case STU300_EVENT_2:
220 case STU300_EVENT_3:
221 case STU300_EVENT_7:
222 case STU300_EVENT_8:
223 if (status1 & I2C_SR1_BTF_IND) {
224 if (status2 & I2C_SR2_AF_IND)
225 dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
226 else if (status2 & I2C_SR2_BERR_IND)
227 dev->cmd_err = STU300_ERROR_BUS_ERROR;
228 return 1;
229 }
230 break;
231 case STU300_EVENT_4:
232 if (status2 & I2C_SR2_STOPF_IND)
233 return 1;
234 break;
235 case STU300_EVENT_5:
236 if (status1 & I2C_SR1_SB_IND)
237 /* Clear start bit */
238 return 1;
239 break;
240 case STU300_EVENT_6:
241 if (status2 & I2C_SR2_ENDAD_IND) {
242 /* First check for any errors */
243 if (status2 & I2C_SR2_AF_IND)
244 dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
245 return 1;
246 }
247 break;
248 case STU300_EVENT_9:
249 if (status1 & I2C_SR1_ADD10_IND)
250 return 1;
251 break;
252 default:
253 break;
254 }
255 if (status2 & I2C_SR2_ARLO_IND)
256 dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
257 return 0;
258}
259
260static irqreturn_t stu300_irh(int irq, void *data)
261{
262 struct stu300_dev *dev = data;
263 int res;
264
265 /* See if this was what we were waiting for */
266 spin_lock(&dev->cmd_issue_lock);
267 if (dev->cmd_event != STU300_EVENT_NONE) {
268 res = stu300_event_occurred(dev, dev->cmd_event);
269 if (res || dev->cmd_err != STU300_ERROR_NONE) {
270 u32 val;
271
272 complete(&dev->cmd_complete);
273 /* Block any multiple interrupts */
274 val = stu300_r8(dev->virtbase + I2C_CR);
275 val &= ~I2C_CR_INTERRUPT_ENABLE;
276 stu300_wr8(val, dev->virtbase + I2C_CR);
277 }
278 }
279 spin_unlock(&dev->cmd_issue_lock);
280 return IRQ_HANDLED;
281}
282
283/*
284 * Sends a command and then waits for the bits masked by *flagmask*
285 * to go high or low by IRQ awaiting.
286 */
287static int stu300_start_and_await_event(struct stu300_dev *dev,
288 u8 cr_value,
289 enum stu300_event mr_event)
290{
291 int ret;
292
293 if (unlikely(irqs_disabled())) {
294 /* TODO: implement polling for this case if need be. */
295 WARN(1, "irqs are disabled, cannot poll for event\n");
296 return -EIO;
297 }
298
299 /* Lock command issue, fill in an event we wait for */
300 spin_lock_irq(&dev->cmd_issue_lock);
301 init_completion(&dev->cmd_complete);
302 dev->cmd_err = STU300_ERROR_NONE;
303 dev->cmd_event = mr_event;
304 spin_unlock_irq(&dev->cmd_issue_lock);
305
306 /* Turn on interrupt, send command and wait. */
307 cr_value |= I2C_CR_INTERRUPT_ENABLE;
308 stu300_wr8(cr_value, dev->virtbase + I2C_CR);
309 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
310 STU300_TIMEOUT);
311
312 if (ret < 0) {
313 dev_err(&dev->pdev->dev,
314 "wait_for_completion_interruptible_timeout() "
315 "returned %d waiting for event %04x\n", ret, mr_event);
316 return ret;
317 }
318
319 if (ret == 0) {
320 dev_err(&dev->pdev->dev, "controller timed out "
321 "waiting for event %d, reinit hardware\n", mr_event);
322 (void) stu300_init_hw(dev);
323 return -ETIMEDOUT;
324 }
325
326 if (dev->cmd_err != STU300_ERROR_NONE) {
327 dev_err(&dev->pdev->dev, "controller (start) "
328 "error %d waiting for event %d, reinit hardware\n",
329 dev->cmd_err, mr_event);
330 (void) stu300_init_hw(dev);
331 return -EIO;
332 }
333
334 return 0;
335}
336
337/*
338 * This waits for a flag to be set, if it is not set on entry, an interrupt is
339 * configured to wait for the flag using a completion.
340 */
341static int stu300_await_event(struct stu300_dev *dev,
342 enum stu300_event mr_event)
343{
344 int ret;
345 u32 val;
346
347 if (unlikely(irqs_disabled())) {
348 /* TODO: implement polling for this case if need be. */
349 dev_err(&dev->pdev->dev, "irqs are disabled on this "
350 "system!\n");
351 return -EIO;
352 }
353
354 /* Is it already here? */
355 spin_lock_irq(&dev->cmd_issue_lock);
356 dev->cmd_err = STU300_ERROR_NONE;
357 if (stu300_event_occurred(dev, mr_event)) {
358 spin_unlock_irq(&dev->cmd_issue_lock);
359 goto exit_await_check_err;
360 }
361 init_completion(&dev->cmd_complete);
362 dev->cmd_err = STU300_ERROR_NONE;
363 dev->cmd_event = mr_event;
364
365 /* Turn on the I2C interrupt for current operation */
366 val = stu300_r8(dev->virtbase + I2C_CR);
367 val |= I2C_CR_INTERRUPT_ENABLE;
368 stu300_wr8(val, dev->virtbase + I2C_CR);
369
370 /* Twice paranoia (possible HW glitch) */
371 stu300_wr8(val, dev->virtbase + I2C_CR);
372
373 /* Check again: is it already here? */
374 if (unlikely(stu300_event_occurred(dev, mr_event))) {
375 /* Disable IRQ again. */
376 val &= ~I2C_CR_INTERRUPT_ENABLE;
377 stu300_wr8(val, dev->virtbase + I2C_CR);
378 spin_unlock_irq(&dev->cmd_issue_lock);
379 goto exit_await_check_err;
380 }
381
382 /* Unlock the command block and wait for the event to occur */
383 spin_unlock_irq(&dev->cmd_issue_lock);
384 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
385 STU300_TIMEOUT);
386
387 if (ret < 0) {
388 dev_err(&dev->pdev->dev,
389 "wait_for_completion_interruptible_timeout()"
390 "returned %d waiting for event %04x\n", ret, mr_event);
391 return ret;
392 }
393
394 if (ret == 0) {
395 if (mr_event != STU300_EVENT_6) {
396 dev_err(&dev->pdev->dev, "controller "
397 "timed out waiting for event %d, reinit "
398 "hardware\n", mr_event);
399 (void) stu300_init_hw(dev);
400 }
401 return -ETIMEDOUT;
402 }
403
404 exit_await_check_err:
405 if (dev->cmd_err != STU300_ERROR_NONE) {
406 if (mr_event != STU300_EVENT_6) {
407 dev_err(&dev->pdev->dev, "controller "
408 "error (await_event) %d waiting for event %d, "
409 "reinit hardware\n", dev->cmd_err, mr_event);
410 (void) stu300_init_hw(dev);
411 }
412 return -EIO;
413 }
414
415 return 0;
416}
417
418/*
419 * Waits for the busy bit to go low by repeated polling.
420 */
421#define BUSY_RELEASE_ATTEMPTS 10
422static int stu300_wait_while_busy(struct stu300_dev *dev)
423{
424 unsigned long timeout;
425 int i;
426
427 for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
428 timeout = jiffies + STU300_TIMEOUT;
429
430 while (!time_after(jiffies, timeout)) {
431 /* Is not busy? */
432 if ((stu300_r8(dev->virtbase + I2C_SR1) &
433 I2C_SR1_BUSY_IND) == 0)
434 return 0;
435 msleep(1);
436 }
437
438 dev_err(&dev->pdev->dev, "transaction timed out "
439 "waiting for device to be free (not busy). "
440 "Attempt: %d\n", i+1);
441
442 dev_err(&dev->pdev->dev, "base address = "
443 "0x%08x, reinit hardware\n", (u32) dev->virtbase);
444
445 (void) stu300_init_hw(dev);
446 }
447
448 dev_err(&dev->pdev->dev, "giving up after %d attempts "
449 "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS);
450
451 return -ETIMEDOUT;
452}
453
454struct stu300_clkset {
455 unsigned long rate;
456 u32 setting;
457};
458
459static const struct stu300_clkset stu300_clktable[] = {
460 { 0, 0xFFU },
461 { 2500000, I2C_OAR2_FR_25_10MHZ },
462 { 10000000, I2C_OAR2_FR_10_1667MHZ },
463 { 16670000, I2C_OAR2_FR_1667_2667MHZ },
464 { 26670000, I2C_OAR2_FR_2667_40MHZ },
465 { 40000000, I2C_OAR2_FR_40_5333MHZ },
466 { 53330000, I2C_OAR2_FR_5333_66MHZ },
467 { 66000000, I2C_OAR2_FR_66_80MHZ },
468 { 80000000, I2C_OAR2_FR_80_100MHZ },
469 { 100000000, 0xFFU },
470};
471
472static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
473{
474
475 u32 val;
476 int i = 0;
477
478 /* Locate the apropriate clock setting */
479 while (i < ARRAY_SIZE(stu300_clktable) &&
480 stu300_clktable[i].rate < clkrate)
481 i++;
482
483 if (stu300_clktable[i].setting == 0xFFU) {
484 dev_err(&dev->pdev->dev, "too %s clock rate requested "
485 "(%lu Hz).\n", i ? "high" : "low", clkrate);
486 return -EINVAL;
487 }
488
489 stu300_wr8(stu300_clktable[i].setting,
490 dev->virtbase + I2C_OAR2);
491
492 dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
493 "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
494
495 if (dev->speed > 100000)
496 /* Fast Mode I2C */
497 val = ((clkrate/dev->speed)-9)/3;
498 else
499 /* Standard Mode I2C */
500 val = ((clkrate/dev->speed)-7)/2;
501
502 /* According to spec the divider must be > 2 */
503 if (val < 0x002) {
504 dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
505 clkrate);
506 return -EINVAL;
507 }
508
509 /* We have 12 bits clock divider only! */
510 if (val & 0xFFFFF000U) {
511 dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
512 clkrate);
513 return -EINVAL;
514 }
515
516 if (dev->speed > 100000) {
517 /* CC6..CC0 */
518 stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
519 dev->virtbase + I2C_CCR);
520 dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
521 "Fast Mode I2C\n", val);
522 } else {
523 /* CC6..CC0 */
524 stu300_wr8((val & I2C_CCR_CC_MASK),
525 dev->virtbase + I2C_CCR);
526 dev_dbg(&dev->pdev->dev, "set clock divider to "
527 "0x%08x, Standard Mode I2C\n", val);
528 }
529
530 /* CC11..CC7 */
531 stu300_wr8(((val >> 7) & 0x1F),
532 dev->virtbase + I2C_ECCR);
533
534 return 0;
535}
536
537
538static int stu300_init_hw(struct stu300_dev *dev)
539{
540 u32 dummy;
541 unsigned long clkrate;
542 int ret;
543
544 /* Disable controller */
545 stu300_wr8(0x00, dev->virtbase + I2C_CR);
546 /*
547 * Set own address to some default value (0x00).
548 * We do not support slave mode anyway.
549 */
550 stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
551 /*
552 * The I2C controller only operates properly in 26 MHz but we
553 * program this driver as if we didn't know. This will also set the two
554 * high bits of the own address to zero as well.
555 * There is no known hardware issue with running in 13 MHz
556 * However, speeds over 200 kHz are not used.
557 */
558 clkrate = clk_get_rate(dev->clk);
559 ret = stu300_set_clk(dev, clkrate);
560 if (ret)
561 return ret;
562 /*
563 * Enable block, do it TWICE (hardware glitch)
564 * Setting bit 7 can enable DDC mode. (Not used currently.)
565 */
566 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
567 dev->virtbase + I2C_CR);
568 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
569 dev->virtbase + I2C_CR);
570 /* Make a dummy read of the status register SR1 & SR2 */
571 dummy = stu300_r8(dev->virtbase + I2C_SR2);
572 dummy = stu300_r8(dev->virtbase + I2C_SR1);
573
574 return 0;
575}
576
577
578
579/* Send slave address. */
580static int stu300_send_address(struct stu300_dev *dev,
581 struct i2c_msg *msg, int resend)
582{
583 u32 val;
584 int ret;
585
586 if (msg->flags & I2C_M_TEN)
587 /* This is probably how 10 bit addresses look */
588 val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
589 I2C_DR_D_MASK;
590 else
591 val = ((msg->addr << 1) & I2C_DR_D_MASK);
592
593 if (msg->flags & I2C_M_RD) {
594 /* This is the direction bit */
595 val |= 0x01;
596 if (resend)
597 dev_dbg(&dev->pdev->dev, "read resend\n");
598 } else if (resend)
599 dev_dbg(&dev->pdev->dev, "write resend\n");
600 stu300_wr8(val, dev->virtbase + I2C_DR);
601
602 /* For 10bit addressing, await 10bit request (EVENT 9) */
603 if (msg->flags & I2C_M_TEN) {
604 ret = stu300_await_event(dev, STU300_EVENT_9);
605 /*
606 * The slave device wants a 10bit address, send the rest
607 * of the bits (the LSBits)
608 */
609 val = msg->addr & I2C_DR_D_MASK;
610 /* This clears "event 9" */
611 stu300_wr8(val, dev->virtbase + I2C_DR);
612 if (ret != 0)
613 return ret;
614 }
615 /* FIXME: Why no else here? two events for 10bit?
616 * Await event 6 (normal) or event 9 (10bit)
617 */
618
619 if (resend)
620 dev_dbg(&dev->pdev->dev, "await event 6\n");
621 ret = stu300_await_event(dev, STU300_EVENT_6);
622
623 /*
624 * Clear any pending EVENT 6 no matter what happend during
625 * await_event.
626 */
627 val = stu300_r8(dev->virtbase + I2C_CR);
628 val |= I2C_CR_PERIPHERAL_ENABLE;
629 stu300_wr8(val, dev->virtbase + I2C_CR);
630
631 return ret;
632}
633
634static int stu300_xfer_msg(struct i2c_adapter *adap,
635 struct i2c_msg *msg, int stop)
636{
637 u32 cr;
638 u32 val;
639 u32 i;
640 int ret;
641 int attempts = 0;
642 struct stu300_dev *dev = i2c_get_adapdata(adap);
643
644
645 clk_enable(dev->clk);
646
647 /* Remove this if (0) to trace each and every message. */
648 if (0) {
649 dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
650 "flags: 0x%04x, stop: %d\n",
651 msg->addr, msg->len, msg->flags, stop);
652 }
653
654 /* Zero-length messages are not supported by this hardware */
655 if (msg->len == 0) {
656 ret = -EINVAL;
657 goto exit_disable;
658 }
659
660 /*
661 * For some reason, sending the address sometimes fails when running
662 * on the 13 MHz clock. No interrupt arrives. This is a work around,
663 * which tries to restart and send the address up to 10 times before
664 * really giving up. Usually 5 to 8 attempts are enough.
665 */
666 do {
667 if (attempts)
668 dev_dbg(&dev->pdev->dev, "wait while busy\n");
669 /* Check that the bus is free, or wait until some timeout */
670 ret = stu300_wait_while_busy(dev);
671 if (ret != 0)
672 goto exit_disable;
673
674 if (attempts)
675 dev_dbg(&dev->pdev->dev, "re-int hw\n");
676 /*
677 * According to ST, there is no problem if the clock is
678 * changed between 13 and 26 MHz during a transfer.
679 */
680 ret = stu300_init_hw(dev);
681 if (ret)
682 goto exit_disable;
683
684 /* Send a start condition */
685 cr = I2C_CR_PERIPHERAL_ENABLE;
686 /* Setting the START bit puts the block in master mode */
687 if (!(msg->flags & I2C_M_NOSTART))
688 cr |= I2C_CR_START_ENABLE;
689 if ((msg->flags & I2C_M_RD) && (msg->len > 1))
690 /* On read more than 1 byte, we need ack. */
691 cr |= I2C_CR_ACK_ENABLE;
692 /* Check that it gets through */
693 if (!(msg->flags & I2C_M_NOSTART)) {
694 if (attempts)
695 dev_dbg(&dev->pdev->dev, "send start event\n");
696 ret = stu300_start_and_await_event(dev, cr,
697 STU300_EVENT_5);
698 }
699
700 if (attempts)
701 dev_dbg(&dev->pdev->dev, "send address\n");
702
703 if (ret == 0)
704 /* Send address */
705 ret = stu300_send_address(dev, msg, attempts != 0);
706
707 if (ret != 0) {
708 attempts++;
709 dev_dbg(&dev->pdev->dev, "failed sending address, "
710 "retrying. Attempt: %d msg_index: %d/%d\n",
711 attempts, dev->msg_index, dev->msg_len);
712 }
713
714 } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
715
716 if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
717 dev_dbg(&dev->pdev->dev, "managed to get address "
718 "through after %d attempts\n", attempts);
719 } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
720 dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
721 "to resend address.\n",
722 NUM_ADDR_RESEND_ATTEMPTS);
723 goto exit_disable;
724 }
725
726 if (msg->flags & I2C_M_RD) {
727 /* READ: we read the actual bytes one at a time */
728 for (i = 0; i < msg->len; i++) {
729 if (i == msg->len-1) {
730 /*
731 * Disable ACK and set STOP condition before
732 * reading last byte
733 */
734 val = I2C_CR_PERIPHERAL_ENABLE;
735
736 if (stop)
737 val |= I2C_CR_STOP_ENABLE;
738
739 stu300_wr8(val,
740 dev->virtbase + I2C_CR);
741 }
742 /* Wait for this byte... */
743 ret = stu300_await_event(dev, STU300_EVENT_7);
744 if (ret != 0)
745 goto exit_disable;
746 /* This clears event 7 */
747 msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
748 }
749 } else {
750 /* WRITE: we send the actual bytes one at a time */
751 for (i = 0; i < msg->len; i++) {
752 /* Write the byte */
753 stu300_wr8(msg->buf[i],
754 dev->virtbase + I2C_DR);
755 /* Check status */
756 ret = stu300_await_event(dev, STU300_EVENT_8);
757 /* Next write to DR will clear event 8 */
758 if (ret != 0) {
759 dev_err(&dev->pdev->dev, "error awaiting "
760 "event 8 (%d)\n", ret);
761 goto exit_disable;
762 }
763 }
764 /* Check NAK */
765 if (!(msg->flags & I2C_M_IGNORE_NAK)) {
766 if (stu300_r8(dev->virtbase + I2C_SR2) &
767 I2C_SR2_AF_IND) {
768 dev_err(&dev->pdev->dev, "I2C payload "
769 "send returned NAK!\n");
770 ret = -EIO;
771 goto exit_disable;
772 }
773 }
774 if (stop) {
775 /* Send stop condition */
776 val = I2C_CR_PERIPHERAL_ENABLE;
777 val |= I2C_CR_STOP_ENABLE;
778 stu300_wr8(val, dev->virtbase + I2C_CR);
779 }
780 }
781
782 /* Check that the bus is free, or wait until some timeout occurs */
783 ret = stu300_wait_while_busy(dev);
784 if (ret != 0) {
785 dev_err(&dev->pdev->dev, "timout waiting for transfer "
786 "to commence.\n");
787 goto exit_disable;
788 }
789
790 /* Dummy read status registers */
791 val = stu300_r8(dev->virtbase + I2C_SR2);
792 val = stu300_r8(dev->virtbase + I2C_SR1);
793 ret = 0;
794
795 exit_disable:
796 /* Disable controller */
797 stu300_wr8(0x00, dev->virtbase + I2C_CR);
798 clk_disable(dev->clk);
799 return ret;
800}
801
802static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
803 int num)
804{
805 int ret = -1;
806 int i;
807 struct stu300_dev *dev = i2c_get_adapdata(adap);
808 dev->msg_len = num;
809 for (i = 0; i < num; i++) {
810 /*
811 * Another driver appears to send stop for each message,
812 * here we only do that for the last message. Possibly some
813 * peripherals require this behaviour, then their drivers
814 * have to send single messages in order to get "stop" for
815 * each message.
816 */
817 dev->msg_index = i;
818
819 ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
820 if (ret != 0) {
821 num = ret;
822 break;
823 }
824 }
825
826 return num;
827}
828
829static u32 stu300_func(struct i2c_adapter *adap)
830{
831 /* This is the simplest thing you can think of... */
832 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
833}
834
835static const struct i2c_algorithm stu300_algo = {
836 .master_xfer = stu300_xfer,
837 .functionality = stu300_func,
838};
839
840static int __init
841stu300_probe(struct platform_device *pdev)
842{
843 struct stu300_dev *dev;
844 struct i2c_adapter *adap;
845 struct resource *res;
846 int bus_nr;
847 int ret = 0;
848
849 dev = kzalloc(sizeof(struct stu300_dev), GFP_KERNEL);
850 if (!dev) {
851 dev_err(&pdev->dev, "could not allocate device struct\n");
852 ret = -ENOMEM;
853 goto err_no_devmem;
854 }
855
856 bus_nr = pdev->id;
857 dev->clk = clk_get(&pdev->dev, NULL);
858 if (IS_ERR(dev->clk)) {
859 ret = PTR_ERR(dev->clk);
860 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
861 goto err_no_clk;
862 }
863
864 dev->pdev = pdev;
865 platform_set_drvdata(pdev, dev);
866
867 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
868 if (!res) {
869 ret = -ENOENT;
870 goto err_no_resource;
871 }
872
873 dev->phybase = res->start;
874 dev->physize = resource_size(res);
875
876 if (request_mem_region(dev->phybase, dev->physize,
877 NAME " I/O Area") == NULL) {
878 ret = -EBUSY;
879 goto err_no_ioregion;
880 }
881
882 dev->virtbase = ioremap(dev->phybase, dev->physize);
883 dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
884 "base %p\n", bus_nr, dev->virtbase);
885 if (!dev->virtbase) {
886 ret = -ENOMEM;
887 goto err_no_ioremap;
888 }
889
890 dev->irq = platform_get_irq(pdev, 0);
891 if (request_irq(dev->irq, stu300_irh, IRQF_DISABLED,
892 NAME, dev)) {
893 ret = -EIO;
894 goto err_no_irq;
895 }
896
897 dev->speed = scl_frequency;
898
899 clk_enable(dev->clk);
900 ret = stu300_init_hw(dev);
901 clk_disable(dev->clk);
902
903 if (ret != 0) {
904 dev_err(&dev->pdev->dev, "error initializing hardware.\n");
905 goto err_init_hw;
906 }
907
908 /* IRQ event handling initialization */
909 spin_lock_init(&dev->cmd_issue_lock);
910 dev->cmd_event = STU300_EVENT_NONE;
911 dev->cmd_err = STU300_ERROR_NONE;
912
913 adap = &dev->adapter;
914 adap->owner = THIS_MODULE;
915 /* DDC class but actually often used for more generic I2C */
916 adap->class = I2C_CLASS_DDC;
917 strncpy(adap->name, "ST Microelectronics DDC I2C adapter",
918 sizeof(adap->name));
919 adap->nr = bus_nr;
920 adap->algo = &stu300_algo;
921 adap->dev.parent = &pdev->dev;
922 i2c_set_adapdata(adap, dev);
923
924 /* i2c device drivers may be active on return from add_adapter() */
925 ret = i2c_add_numbered_adapter(adap);
926 if (ret) {
927 dev_err(&dev->pdev->dev, "failure adding ST Micro DDC "
928 "I2C adapter\n");
929 goto err_add_adapter;
930 }
931 return 0;
932
933 err_add_adapter:
934 err_init_hw:
935 free_irq(dev->irq, dev);
936 err_no_irq:
937 iounmap(dev->virtbase);
938 err_no_ioremap:
939 release_mem_region(dev->phybase, dev->physize);
940 err_no_ioregion:
941 platform_set_drvdata(pdev, NULL);
942 err_no_resource:
943 clk_put(dev->clk);
944 err_no_clk:
945 kfree(dev);
946 err_no_devmem:
947 dev_err(&pdev->dev, "failed to add " NAME " adapter: %d\n",
948 pdev->id);
949 return ret;
950}
951
952#ifdef CONFIG_PM
953static int stu300_suspend(struct platform_device *pdev, pm_message_t state)
954{
955 struct stu300_dev *dev = platform_get_drvdata(pdev);
956
957 /* Turn off everything */
958 stu300_wr8(0x00, dev->virtbase + I2C_CR);
959 return 0;
960}
961
962static int stu300_resume(struct platform_device *pdev)
963{
964 int ret = 0;
965 struct stu300_dev *dev = platform_get_drvdata(pdev);
966
967 clk_enable(dev->clk);
968 ret = stu300_init_hw(dev);
969 clk_disable(dev->clk);
970
971 if (ret != 0)
972 dev_err(&pdev->dev, "error re-initializing hardware.\n");
973 return ret;
974}
975#else
976#define stu300_suspend NULL
977#define stu300_resume NULL
978#endif
979
980static int __exit
981stu300_remove(struct platform_device *pdev)
982{
983 struct stu300_dev *dev = platform_get_drvdata(pdev);
984
985 i2c_del_adapter(&dev->adapter);
986 /* Turn off everything */
987 stu300_wr8(0x00, dev->virtbase + I2C_CR);
988 free_irq(dev->irq, dev);
989 iounmap(dev->virtbase);
990 release_mem_region(dev->phybase, dev->physize);
991 clk_put(dev->clk);
992 platform_set_drvdata(pdev, NULL);
993 kfree(dev);
994 return 0;
995}
996
997static struct platform_driver stu300_i2c_driver = {
998 .driver = {
999 .name = NAME,
1000 .owner = THIS_MODULE,
1001 },
1002 .remove = __exit_p(stu300_remove),
1003 .suspend = stu300_suspend,
1004 .resume = stu300_resume,
1005
1006};
1007
1008static int __init stu300_init(void)
1009{
1010 return platform_driver_probe(&stu300_i2c_driver, stu300_probe);
1011}
1012
1013static void __exit stu300_exit(void)
1014{
1015 platform_driver_unregister(&stu300_i2c_driver);
1016}
1017
1018/*
1019 * The systems using this bus often have very basic devices such
1020 * as regulators on the I2C bus, so this needs to be loaded early.
1021 * Therefore it is registered in the subsys_initcall().
1022 */
1023subsys_initcall(stu300_init);
1024module_exit(stu300_exit);
1025
1026MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1027MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
1028MODULE_LICENSE("GPL");
1029MODULE_ALIAS("platform:" NAME);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 18:14:54 -0500