diff options
-rw-r--r-- | include/asm-mips/cpu-features.h | 45 | ||||
-rw-r--r-- | include/asm-mips/cpu.h | 17 |
2 files changed, 31 insertions, 31 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index f8be4a470754..78c9cc2735d5 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h | |||
@@ -116,6 +116,27 @@ | |||
116 | #endif | 116 | #endif |
117 | #endif | 117 | #endif |
118 | 118 | ||
119 | # ifndef cpu_has_mips32r1 | ||
120 | # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) | ||
121 | # endif | ||
122 | # ifndef cpu_has_mips32r2 | ||
123 | # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) | ||
124 | # endif | ||
125 | # ifndef cpu_has_mips64r1 | ||
126 | # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) | ||
127 | # endif | ||
128 | # ifndef cpu_has_mips64r2 | ||
129 | # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) | ||
130 | # endif | ||
131 | |||
132 | /* | ||
133 | * Shortcuts ... | ||
134 | */ | ||
135 | #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) | ||
136 | #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) | ||
137 | #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) | ||
138 | #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) | ||
139 | |||
119 | #ifndef cpu_has_dsp | 140 | #ifndef cpu_has_dsp |
120 | #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) | 141 | #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) |
121 | #endif | 142 | #endif |
@@ -144,18 +165,6 @@ | |||
144 | # ifndef cpu_has_64bit_addresses | 165 | # ifndef cpu_has_64bit_addresses |
145 | # define cpu_has_64bit_addresses 0 | 166 | # define cpu_has_64bit_addresses 0 |
146 | # endif | 167 | # endif |
147 | # ifndef cpu_has_mips32r1 | ||
148 | # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) | ||
149 | # endif | ||
150 | # ifndef cpu_has_mips32r2 | ||
151 | # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) | ||
152 | # endif | ||
153 | # ifndef cpu_has_mips64r1 | ||
154 | # define cpu_has_mips64r1 0 | ||
155 | # endif | ||
156 | # ifndef cpu_has_mips64r2 | ||
157 | # define cpu_has_mips64r2 0 | ||
158 | # endif | ||
159 | #endif | 168 | #endif |
160 | 169 | ||
161 | #ifdef CONFIG_64BIT | 170 | #ifdef CONFIG_64BIT |
@@ -174,18 +183,6 @@ | |||
174 | # ifndef cpu_has_64bit_addresses | 183 | # ifndef cpu_has_64bit_addresses |
175 | # define cpu_has_64bit_addresses 1 | 184 | # define cpu_has_64bit_addresses 1 |
176 | # endif | 185 | # endif |
177 | # ifndef cpu_has_mips32r1 | ||
178 | # define cpu_has_mips32r1 0 | ||
179 | # endif | ||
180 | # ifndef cpu_has_mips32r2 | ||
181 | # define cpu_has_mips32r2 0 | ||
182 | # endif | ||
183 | # ifndef cpu_has_mips64r1 | ||
184 | # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) | ||
185 | # endif | ||
186 | # ifndef cpu_has_mips64r2 | ||
187 | # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) | ||
188 | # endif | ||
189 | #endif | 186 | #endif |
190 | 187 | ||
191 | #ifdef CONFIG_CPU_MIPSR2 | 188 | #ifdef CONFIG_CPU_MIPSR2 |
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 48c37c46053a..934e063e79f1 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h | |||
@@ -202,17 +202,20 @@ | |||
202 | * ISA Level encodings | 202 | * ISA Level encodings |
203 | * | 203 | * |
204 | */ | 204 | */ |
205 | #define MIPS_CPU_ISA_64BIT 0x00008000 | ||
206 | |||
207 | #define MIPS_CPU_ISA_I 0x00000001 | 205 | #define MIPS_CPU_ISA_I 0x00000001 |
208 | #define MIPS_CPU_ISA_II 0x00000002 | 206 | #define MIPS_CPU_ISA_II 0x00000002 |
209 | #define MIPS_CPU_ISA_III (0x00000003 | MIPS_CPU_ISA_64BIT) | 207 | #define MIPS_CPU_ISA_III 0x00000003 |
210 | #define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) | 208 | #define MIPS_CPU_ISA_IV 0x00000004 |
211 | #define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) | 209 | #define MIPS_CPU_ISA_V 0x00000005 |
212 | #define MIPS_CPU_ISA_M32R1 0x00000020 | 210 | #define MIPS_CPU_ISA_M32R1 0x00000020 |
213 | #define MIPS_CPU_ISA_M32R2 0x00000040 | 211 | #define MIPS_CPU_ISA_M32R2 0x00000040 |
214 | #define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT) | 212 | #define MIPS_CPU_ISA_M64R1 0x00000080 |
215 | #define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT) | 213 | #define MIPS_CPU_ISA_M64R2 0x00000100 |
214 | |||
215 | #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ | ||
216 | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) | ||
217 | #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ | ||
218 | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) | ||
216 | 219 | ||
217 | /* | 220 | /* |
218 | * CPU Option encodings | 221 | * CPU Option encodings |