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-rw-r--r--arch/m68k/include/asm/coldfire.h42
-rw-r--r--arch/m68k/include/asm/m5206sim.h23
-rw-r--r--arch/m68k/include/asm/m520xsim.h50
-rw-r--r--arch/m68k/include/asm/m523xsim.h52
-rw-r--r--arch/m68k/include/asm/m5249sim.h30
-rw-r--r--arch/m68k/include/asm/m5272sim.h8
-rw-r--r--arch/m68k/include/asm/m527xsim.h68
-rw-r--r--arch/m68k/include/asm/m528xsim.h44
-rw-r--r--arch/m68k/include/asm/m5307sim.h25
-rw-r--r--arch/m68k/include/asm/m532xsim.h9
-rw-r--r--arch/m68k/include/asm/m5407sim.h25
-rw-r--r--arch/m68k/include/asm/m54xxsim.h14
-rw-r--r--arch/m68k/include/asm/mcfdma.h23
-rw-r--r--arch/m68k/include/asm/mcfpit.h16
-rw-r--r--arch/m68k/include/asm/mcftimer.h23
-rw-r--r--arch/m68knommu/Kconfig58
-rw-r--r--arch/m68knommu/kernel/irq.c6
-rw-r--r--arch/m68knommu/platform/5206/gpio.c6
-rw-r--r--arch/m68knommu/platform/5206e/gpio.c6
-rw-r--r--arch/m68knommu/platform/520x/config.c36
-rw-r--r--arch/m68knommu/platform/520x/gpio.c96
-rw-r--r--arch/m68knommu/platform/523x/config.c10
-rw-r--r--arch/m68knommu/platform/523x/gpio.c136
-rw-r--r--arch/m68knommu/platform/5249/gpio.c12
-rw-r--r--arch/m68knommu/platform/5249/intc2.c20
-rw-r--r--arch/m68knommu/platform/5272/gpio.c18
-rw-r--r--arch/m68knommu/platform/5272/intc.c33
-rw-r--r--arch/m68knommu/platform/527x/config.c14
-rw-r--r--arch/m68knommu/platform/527x/gpio.c312
-rw-r--r--arch/m68knommu/platform/528x/config.c14
-rw-r--r--arch/m68knommu/platform/528x/gpio.c210
-rw-r--r--arch/m68knommu/platform/5307/gpio.c6
-rw-r--r--arch/m68knommu/platform/532x/gpio.c166
-rw-r--r--arch/m68knommu/platform/5407/gpio.c6
-rw-r--r--arch/m68knommu/platform/54xx/Makefile1
-rw-r--r--arch/m68knommu/platform/54xx/firebee.c86
-rw-r--r--arch/m68knommu/platform/68328/ints.c12
-rw-r--r--arch/m68knommu/platform/68360/ints.c18
-rw-r--r--arch/m68knommu/platform/coldfire/dma.c8
-rw-r--r--arch/m68knommu/platform/coldfire/head.S10
-rw-r--r--arch/m68knommu/platform/coldfire/intc-2.c176
-rw-r--r--arch/m68knommu/platform/coldfire/intc-simr.c165
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c20
-rw-r--r--arch/m68knommu/platform/coldfire/pit.c2
-rw-r--r--arch/m68knommu/platform/coldfire/timers.c4
45 files changed, 1284 insertions, 835 deletions
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 213028cbe110..c94557b91448 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -14,39 +14,35 @@
14 14
15 15
16/* 16/*
17 * Define master clock frequency. This is essentially done at config 17 * Define master clock frequency. This is done at config time now.
18 * time now. No point enumerating dozens of possible clock options 18 * No point enumerating dozens of possible clock options here. And
19 * here. Also the peripheral clock (bus clock) divide ratio is set 19 * in any case new boards come along from time to time that have yet
20 * at config time too. 20 * another different clocking frequency.
21 */ 21 */
22#ifdef CONFIG_CLOCK_SET 22#ifdef CONFIG_CLOCK_SET
23#define MCF_CLK CONFIG_CLOCK_FREQ 23#define MCF_CLK CONFIG_CLOCK_FREQ
24#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
25#else 24#else
26#error "Don't know what your ColdFire CPU clock frequency is??" 25#error "Don't know what your ColdFire CPU clock frequency is??"
27#endif 26#endif
28 27
29/* 28/*
30 * Define the processor support peripherals base address. 29 * Define the processor internal peripherals base address.
31 * This is generally setup by the boards start up code. 30 *
31 * The majority of ColdFire parts use an MBAR register to set
32 * the base address. Some have an IPSBAR register instead, and it
33 * has slightly different rules on its size and alignment. Some
34 * parts have fixed addresses and the internal peripherals cannot
35 * be relocated in the CPU address space.
36 *
37 * The value of MBAR or IPSBAR is config time selectable, we no
38 * longer hard define it here. No MBAR or IPSBAR will be defined if
39 * this part has a fixed peripheral address map.
32 */ 40 */
33#define MCF_MBAR 0x10000000 41#ifdef CONFIG_MBAR
34#define MCF_MBAR2 0x80000000 42#define MCF_MBAR CONFIG_MBAR
35#if defined(CONFIG_M54xx)
36#define MCF_IPSBAR MCF_MBAR
37#elif defined(CONFIG_M520x)
38#define MCF_IPSBAR 0xFC000000
39#else
40#define MCF_IPSBAR 0x40000000
41#endif 43#endif
42 44#ifdef CONFIG_IPSBAR
43#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 45#define MCF_IPSBAR CONFIG_IPSBAR
44 defined(CONFIG_M520x)
45#undef MCF_MBAR
46#define MCF_MBAR MCF_IPSBAR
47#elif defined(CONFIG_M532x)
48#undef MCF_MBAR
49#define MCF_MBAR 0x00000000
50#endif 46#endif
51 47
52/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 561b03b5ddf8..9015eadd5c00 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -14,6 +14,7 @@
14 14
15#define CPU_NAME "COLDFIRE(m5206)" 15#define CPU_NAME "COLDFIRE(m5206)"
16#define CPU_INSTR_PER_JIFFY 3 16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK MCF_CLK
17 18
18#include <asm/m52xxacr.h> 19#include <asm/m52xxacr.h>
19 20
@@ -48,14 +49,14 @@
48#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ 49#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
49#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ 50#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
50 51
51#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ 52#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
52#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ 53#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
53#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ 54#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
54#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ 55#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
55#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ 56#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
56#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ 57#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
57#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 58#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
58#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ 59#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
59 60
60#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ 61#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
61#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ 62#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
@@ -89,9 +90,15 @@
89#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ 90#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
90#endif 91#endif
91 92
93#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
94#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
95
92#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ 96#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
93#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ 97#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
94 98
99#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
101
95#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
96#define MCFUART_BASE1 0x180 /* Base address of UART1 */ 103#define MCFUART_BASE1 0x180 /* Base address of UART1 */
97#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 104#define MCFUART_BASE2 0x140 /* Base address of UART2 */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 88ed8239fe4e..55d5a4c5fe0b 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -13,13 +13,14 @@
13 13
14#define CPU_NAME "COLDFIRE(m520x)" 14#define CPU_NAME "COLDFIRE(m520x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 520x SIM register set addresses. 21 * Define the 520x SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
23#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
24#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
25#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -35,9 +36,9 @@
35 * address to the SIMR and CIMR registers (not offsets into IPSBAR). 36 * address to the SIMR and CIMR registers (not offsets into IPSBAR).
36 * The 520x family only has a single INTC unit. 37 * The 520x family only has a single INTC unit.
37 */ 38 */
38#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) 39#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
39#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) 40#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
40#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) 41#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
41#define MCFINTC1_SIMR (0) 42#define MCFINTC1_SIMR (0)
42#define MCFINTC1_CIMR (0) 43#define MCFINTC1_CIMR (0)
43#define MCFINTC1_ICR0 (0) 44#define MCFINTC1_ICR0 (0)
@@ -52,19 +53,22 @@
52/* 53/*
53 * SDRAM configuration registers. 54 * SDRAM configuration registers.
54 */ 55 */
55#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ 56#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
56#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ 57#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
57#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ 58#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
58#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ 59#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
59#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 60#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
60#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 61#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
61 62
62/* 63/*
63 * EPORT and GPIO registers. 64 * EPORT and GPIO registers.
64 */ 65 */
66#define MCFEPORT_EPPAR 0xFC088000
65#define MCFEPORT_EPDDR 0xFC088002 67#define MCFEPORT_EPDDR 0xFC088002
68#define MCFEPORT_EPIER 0xFC088003
66#define MCFEPORT_EPDR 0xFC088004 69#define MCFEPORT_EPDR 0xFC088004
67#define MCFEPORT_EPPDR 0xFC088005 70#define MCFEPORT_EPPDR 0xFC088005
71#define MCFEPORT_EPFR 0xFC088006
68 72
69#define MCFGPIO_PODR_BUSCTL 0xFC0A4000 73#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
70#define MCFGPIO_PODR_BE 0xFC0A4001 74#define MCFGPIO_PODR_BE 0xFC0A4001
@@ -119,10 +123,10 @@
119#define MCFGPIO_IRQ_MAX 8 123#define MCFGPIO_IRQ_MAX 8
120#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 124#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
121 125
122#define MCF_GPIO_PAR_UART (0xA4036) 126#define MCF_GPIO_PAR_UART 0xFC0A4036
123#define MCF_GPIO_PAR_FECI2C (0xA4033) 127#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
124#define MCF_GPIO_PAR_QSPI (0xA4034) 128#define MCF_GPIO_PAR_QSPI 0xFC0A4034
125#define MCF_GPIO_PAR_FEC (0xA4038) 129#define MCF_GPIO_PAR_FEC 0xFC0A4038
126 130
127#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 131#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
128#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 132#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
@@ -134,11 +138,23 @@
134#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 138#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
135 139
136/* 140/*
141 * PIT timer module.
142 */
143#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
144#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
145
146/*
137 * UART module. 147 * UART module.
138 */ 148 */
139#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ 149#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
140#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ 150#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
141#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ 151#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
152
153/*
154 * FEC module.
155 */
156#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
157#define MCFFEC_SIZE 0x800 /* Register set size */
142 158
143/* 159/*
144 * Reset Controll Unit. 160 * Reset Controll Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ad7a00257a8..8996df62ede4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -13,14 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m523x)" 14#define CPU_NAME "COLDFIRE(m523x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 523x SIM register set addresses. 21 * Define the 523x SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ 24#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
25
24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -39,11 +41,11 @@
39/* 41/*
40 * SDRAM configuration registers. 42 * SDRAM configuration registers.
41 */ 43 */
42#define MCFSIM_DCR 0x44 /* SDRAM control */ 44#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
43#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 45#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
44#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 46#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
45#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 47#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
46#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
47 49
48/* 50/*
49 * Reset Controll Unit (relative to IPSBAR). 51 * Reset Controll Unit (relative to IPSBAR).
@@ -57,10 +59,19 @@
57/* 59/*
58 * UART module. 60 * UART module.
59 */ 61 */
60#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 62#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
61#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 63#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
62#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 64#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
65
66/*
67 * FEC ethernet module.
68 */
69#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
70#define MCFFEC_SIZE 0x800
63 71
72/*
73 * GPIO module.
74 */
64#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 75#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
65#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 76#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
66#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 77#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
@@ -118,12 +129,22 @@
118#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) 129#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
119 130
120/* 131/*
121 * EPort 132 * PIT timer base addresses.
122 */ 133 */
134#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
135#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
136#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
137#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
123 138
139/*
140 * EPort
141 */
142#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
124#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 143#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
144#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
125#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 145#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
126#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 146#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
147#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
127 148
128/* 149/*
129 * Generic GPIO support 150 * Generic GPIO support
@@ -143,5 +164,14 @@
143*/ 164*/
144#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 165#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
145#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 166#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
167
168/*
169 * DMA unit base addresses.
170 */
171#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
172#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
173#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
174#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
175
146/****************************************************************************/ 176/****************************************************************************/
147#endif /* m523xsim_h */ 177#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 4908b118f2fd..805714ca8d7d 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -13,10 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m5249)" 14#define CPU_NAME "COLDFIRE(m5249)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
21 * The 5249 has a second MBAR region, define its address.
22 */
23#define MCF_MBAR2 0x80000000
24
25/*
20 * Define the 5249 SIM register set addresses. 26 * Define the 5249 SIM register set addresses.
21 */ 27 */
22#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 28#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
@@ -55,11 +61,17 @@
55#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 61#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
56#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 62#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
57 63
58#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 64#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
59#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 65#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
60#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 66#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
61#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 67#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
62#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 68#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
69
70/*
71 * Timer module.
72 */
73#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
74#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
63 75
64/* 76/*
65 * UART module. 77 * UART module.
@@ -68,6 +80,14 @@
68#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 80#define MCFUART_BASE2 0x200 /* Base address of UART2 */
69 81
70/* 82/*
83 * DMA unit base addresses.
84 */
85#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
86#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
87#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
88#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
89
90/*
71 * Some symbol defines for the above... 91 * Some symbol defines for the above...
72 */ 92 */
73#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 93#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index b7cc50abc831..759c2b07a994 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -14,6 +14,7 @@
14 14
15#define CPU_NAME "COLDFIRE(m5272)" 15#define CPU_NAME "COLDFIRE(m5272)"
16#define CPU_INSTR_PER_JIFFY 3 16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK MCF_CLK
17 18
18#include <asm/m52xxacr.h> 19#include <asm/m52xxacr.h>
19 20
@@ -80,6 +81,13 @@
80#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 81#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
81#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 82#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
82 83
84#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
85
86#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
87#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
90
83/* 91/*
84 * Define system peripheral IRQ usage. 92 * Define system peripheral IRQ usage.
85 */ 93 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index e8042e8bc003..74855a66c050 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -13,14 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m527x)" 14#define CPU_NAME "COLDFIRE(m527x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 5270/5271 SIM register set addresses. 21 * Define the 5270/5271 SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ 24#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
25
24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -42,29 +44,45 @@
42 * SDRAM configuration registers. 44 * SDRAM configuration registers.
43 */ 45 */
44#ifdef CONFIG_M5271 46#ifdef CONFIG_M5271
45#define MCFSIM_DCR 0x40 /* SDRAM control */ 47#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
46#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 48#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
47#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 49#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
48#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 50#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
49#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 51#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
50#endif 52#endif
51#ifdef CONFIG_M5275 53#ifdef CONFIG_M5275
52#define MCFSIM_DMR 0x40 /* SDRAM mode */ 54#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
53#define MCFSIM_DCR 0x44 /* SDRAM control */ 55#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
54#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ 56#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
55#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ 57#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
56#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ 58#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
57#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ 59#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
58#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ 60#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
59#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ 61#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
60#endif 62#endif
61 63
62/* 64/*
65 * DMA unit base addresses.
66 */
67#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
68#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
69#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
70#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
71
72/*
63 * UART module. 73 * UART module.
64 */ 74 */
65#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 75#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
66#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 76#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
67#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 77#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
78
79/*
80 * FEC ethernet module.
81 */
82#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
83#define MCFFEC_SIZE0 0x800
84#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
85#define MCFFEC_SIZE1 0x800
68 86
69#ifdef CONFIG_M5271 87#ifdef CONFIG_M5271
70#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 88#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
@@ -231,14 +249,22 @@
231#endif 249#endif
232 250
233/* 251/*
234 * EPort 252 * PIT timer base addresses.
235 */ 253 */
254#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
255#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
256#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
257#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
236 258
259/*
260 * EPort
261 */
262#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
237#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 263#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
264#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
238#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 265#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
239#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 266#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
240 267#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
241
242 268
243/* 269/*
244 * GPIO pins setups to enable the UARTs. 270 * GPIO pins setups to enable the UARTs.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a6d2f4d9aaa0..d798bd5df56c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -13,14 +13,16 @@
13 13
14#define CPU_NAME "COLDFIRE(m528x)" 14#define CPU_NAME "COLDFIRE(m528x)"
15#define CPU_INSTR_PER_JIFFY 3 15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK MCF_CLK
16 17
17#include <asm/m52xxacr.h> 18#include <asm/m52xxacr.h>
18 19
19/* 20/*
20 * Define the 5280/5282 SIM register set addresses. 21 * Define the 5280/5282 SIM register set addresses.
21 */ 22 */
22#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 23#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ 24#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
25
24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -39,18 +41,32 @@
39/* 41/*
40 * SDRAM configuration registers. 42 * SDRAM configuration registers.
41 */ 43 */
42#define MCFSIM_DCR 0x44 /* SDRAM control */ 44#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
43#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 45#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
44#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 46#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
45#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 47#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
46#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
49
50/*
51 * DMA unit base addresses.
52 */
53#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
54#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
55#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
56#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
47 57
48/* 58/*
49 * UART module. 59 * UART module.
50 */ 60 */
51#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 61#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
52#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 62#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
53#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 63#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
64
65/*
66 * FEC ethernet module.
67 */
68#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
69#define MCFFEC_SIZE 0x800
54 70
55/* 71/*
56 * GPIO registers 72 * GPIO registers
@@ -163,6 +179,14 @@
163#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) 179#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
164 180
165/* 181/*
182 * PIT timer base addresses.
183 */
184#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
185#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
186#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
187#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
188
189/*
166 * Edge Port registers 190 * Edge Port registers
167 */ 191 */
168#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) 192#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 0bf57397e7a9..4c94c01f36c4 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -16,6 +16,7 @@
16 16
17#define CPU_NAME "COLDFIRE(m5307)" 17#define CPU_NAME "COLDFIRE(m5307)"
18#define CPU_INSTR_PER_JIFFY 3 18#define CPU_INSTR_PER_JIFFY 3
19#define MCF_BUSCLK (MCF_CLK / 2)
19 20
20#include <asm/m53xxacr.h> 21#include <asm/m53xxacr.h>
21 22
@@ -89,16 +90,30 @@
89#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 90#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
90#endif /* CONFIG_OLDMASK */ 91#endif /* CONFIG_OLDMASK */
91 92
92#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 93#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
93#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 94#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
94#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 95#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
95#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 96#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
96#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 97#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
98
99/*
100 * Timer module.
101 */
102#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
103#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
97 104
98#define MCFSIM_PADDR (MCF_MBAR + 0x244) 105#define MCFSIM_PADDR (MCF_MBAR + 0x244)
99#define MCFSIM_PADAT (MCF_MBAR + 0x248) 106#define MCFSIM_PADAT (MCF_MBAR + 0x248)
100 107
101/* 108/*
109 * DMA unit base addresses.
110 */
111#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
112#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
113#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
114#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
115
116/*
102 * UART module. 117 * UART module.
103 */ 118 */
104#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index e6470f8ca324..ba4cc784f574 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -11,6 +11,7 @@
11 11
12#define CPU_NAME "COLDFIRE(m532x)" 12#define CPU_NAME "COLDFIRE(m532x)"
13#define CPU_INSTR_PER_JIFFY 3 13#define CPU_INSTR_PER_JIFFY 3
14#define MCF_BUSCLK (MCF_CLK / 3)
14 15
15#include <asm/m53xxacr.h> 16#include <asm/m53xxacr.h>
16 17
@@ -85,6 +86,14 @@
85#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 86#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
86#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ 87#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
87 88
89/*
90 * Timer module.
91 */
92#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
93#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
94#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
95#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
96
88/********************************************************************* 97/*********************************************************************
89 * 98 *
90 * Reset Controller Module 99 * Reset Controller Module
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 75f5c28a551d..762c58c89050 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -16,6 +16,7 @@
16 16
17#define CPU_NAME "COLDFIRE(m5407)" 17#define CPU_NAME "COLDFIRE(m5407)"
18#define CPU_INSTR_PER_JIFFY 3 18#define CPU_INSTR_PER_JIFFY 3
19#define MCF_BUSCLK (MCF_CLK / 2)
19 20
20#include <asm/m54xxacr.h> 21#include <asm/m54xxacr.h>
21 22
@@ -72,11 +73,17 @@
72#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 73#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
73#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 74#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
74 75
75#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ 76#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
76#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ 77#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
77#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ 78#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
78#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 79#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
79#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 80#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
81
82/*
83 * Timer module.
84 */
85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
80 87
81#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 88#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
82#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 89#define MCFUART_BASE2 0x200 /* Base address of UART2 */
@@ -85,6 +92,14 @@
85#define MCFSIM_PADAT (MCF_MBAR + 0x248) 92#define MCFSIM_PADAT (MCF_MBAR + 0x248)
86 93
87/* 94/*
95 * DMA unit base addresses.
96 */
97#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
98#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
99#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
100#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
101
102/*
88 * Generic GPIO support 103 * Generic GPIO support
89 */ 104 */
90#define MCFGPIO_PIN_MAX 16 105#define MCFGPIO_PIN_MAX 16
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 462ae5328441..1ed8bfb02772 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -7,6 +7,7 @@
7 7
8#define CPU_NAME "COLDFIRE(m54xx)" 8#define CPU_NAME "COLDFIRE(m54xx)"
9#define CPU_INSTR_PER_JIFFY 2 9#define CPU_INSTR_PER_JIFFY 2
10#define MCF_BUSCLK (MCF_CLK / 2)
10 11
11#include <asm/m54xxacr.h> 12#include <asm/m54xxacr.h>
12 13
@@ -15,7 +16,8 @@
15/* 16/*
16 * Interrupt Controller Registers 17 * Interrupt Controller Registers
17 */ 18 */
18#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ 19#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
20
19#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 21#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
20#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 22#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
21#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 23#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -48,6 +50,16 @@
48#define MCFGPIO_IRQ_VECBASE -1 50#define MCFGPIO_IRQ_VECBASE -1
49 51
50/* 52/*
53 * EDGE Port support.
54 */
55#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
56#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
57#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
58#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
59#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
60#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
61
62/*
51 * Some PSC related definitions 63 * Some PSC related definitions
52 */ 64 */
53#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) 65#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h
index 705c52c79cd8..10bc7e391c14 100644
--- a/arch/m68k/include/asm/mcfdma.h
+++ b/arch/m68k/include/asm/mcfdma.h
@@ -11,29 +11,6 @@
11#define mcfdma_h 11#define mcfdma_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14
15/*
16 * Get address specific defines for this Coldfire member.
17 */
18#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
19#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
20#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
21#elif defined(CONFIG_M5272)
22#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */
23#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
24/* These are relative to the IPSBAR, not MBAR */
25#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */
26#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */
27#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */
28#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */
29#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
30#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
31#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
32#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
33#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
34#endif
35
36
37#if !defined(CONFIG_M5272) 14#if !defined(CONFIG_M5272)
38 15
39/* 16/*
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
index f570cf64fd29..9fd321ca0725 100644
--- a/arch/m68k/include/asm/mcfpit.h
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -11,22 +11,8 @@
11#define mcfpit_h 11#define mcfpit_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14
15/*
16 * Get address specific defines for the 5270/5271, 5280/5282, and 5208.
17 */
18#if defined(CONFIG_M520x)
19#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
20#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
21#else
22#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
23#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
24#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
25#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
26#endif
27
28/* 14/*
29 * Define the PIT timer register set addresses. 15 * Define the PIT timer register address offsets.
30 */ 16 */
31#define MCFPIT_PCSR 0x0 /* PIT control register */ 17#define MCFPIT_PCSR 0x0 /* PIT control register */
32#define MCFPIT_PMR 0x2 /* PIT modulus register */ 18#define MCFPIT_PMR 0x2 /* PIT modulus register */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 0f90f6d2227a..92b276fe8240 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -12,29 +12,6 @@
12#define mcftimer_h 12#define mcftimer_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15
16/*
17 * Get address specific defines for this ColdFire member.
18 */
19#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
20#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
21#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
22#elif defined(CONFIG_M5272)
23#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
24#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
25#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
26#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
27#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
28#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
29#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
30#elif defined(CONFIG_M532x)
31#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
32#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
33#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
34#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
35#endif
36
37
38/* 15/*
39 * Define the TIMER register set addresses. 16 * Define the TIMER register set addresses.
40 */ 17 */
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 8b9dacaa0f6e..b5424cf948e6 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -3,6 +3,7 @@ config M68K
3 default y 3 default y
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_GENERIC_HARDIRQS 5 select HAVE_GENERIC_HARDIRQS
6 select GENERIC_HARDIRQS_NO_DEPRECATED
6 7
7config MMU 8config MMU
8 bool 9 bool
@@ -78,6 +79,12 @@ config HAVE_CACHE_SPLIT
78config HAVE_CACHE_CB 79config HAVE_CACHE_CB
79 bool 80 bool
80 81
82config HAVE_MBAR
83 bool
84
85config HAVE_IPSBAR
86 bool
87
81source "init/Kconfig" 88source "init/Kconfig"
82 89
83source "kernel/Kconfig.freezer" 90source "kernel/Kconfig.freezer"
@@ -111,12 +118,14 @@ config M68360
111config M5206 118config M5206
112 bool "MCF5206" 119 bool "MCF5206"
113 select COLDFIRE_SW_A7 120 select COLDFIRE_SW_A7
121 select HAVE_MBAR
114 help 122 help
115 Motorola ColdFire 5206 processor support. 123 Motorola ColdFire 5206 processor support.
116 124
117config M5206e 125config M5206e
118 bool "MCF5206e" 126 bool "MCF5206e"
119 select COLDFIRE_SW_A7 127 select COLDFIRE_SW_A7
128 select HAVE_MBAR
120 help 129 help
121 Motorola ColdFire 5206e processor support. 130 Motorola ColdFire 5206e processor support.
122 131
@@ -131,30 +140,35 @@ config M523x
131 bool "MCF523x" 140 bool "MCF523x"
132 select GENERIC_CLOCKEVENTS 141 select GENERIC_CLOCKEVENTS
133 select HAVE_CACHE_SPLIT 142 select HAVE_CACHE_SPLIT
143 select HAVE_IPSBAR
134 help 144 help
135 Freescale Coldfire 5230/1/2/4/5 processor support 145 Freescale Coldfire 5230/1/2/4/5 processor support
136 146
137config M5249 147config M5249
138 bool "MCF5249" 148 bool "MCF5249"
139 select COLDFIRE_SW_A7 149 select COLDFIRE_SW_A7
150 select HAVE_MBAR
140 help 151 help
141 Motorola ColdFire 5249 processor support. 152 Motorola ColdFire 5249 processor support.
142 153
143config M5271 154config M5271
144 bool "MCF5271" 155 bool "MCF5271"
145 select HAVE_CACHE_SPLIT 156 select HAVE_CACHE_SPLIT
157 select HAVE_IPSBAR
146 help 158 help
147 Freescale (Motorola) ColdFire 5270/5271 processor support. 159 Freescale (Motorola) ColdFire 5270/5271 processor support.
148 160
149config M5272 161config M5272
150 bool "MCF5272" 162 bool "MCF5272"
151 select COLDFIRE_SW_A7 163 select COLDFIRE_SW_A7
164 select HAVE_MBAR
152 help 165 help
153 Motorola ColdFire 5272 processor support. 166 Motorola ColdFire 5272 processor support.
154 167
155config M5275 168config M5275
156 bool "MCF5275" 169 bool "MCF5275"
157 select HAVE_CACHE_SPLIT 170 select HAVE_CACHE_SPLIT
171 select HAVE_IPSBAR
158 help 172 help
159 Freescale (Motorola) ColdFire 5274/5275 processor support. 173 Freescale (Motorola) ColdFire 5274/5275 processor support.
160 174
@@ -162,6 +176,7 @@ config M528x
162 bool "MCF528x" 176 bool "MCF528x"
163 select GENERIC_CLOCKEVENTS 177 select GENERIC_CLOCKEVENTS
164 select HAVE_CACHE_SPLIT 178 select HAVE_CACHE_SPLIT
179 select HAVE_IPSBAR
165 help 180 help
166 Motorola ColdFire 5280/5282 processor support. 181 Motorola ColdFire 5280/5282 processor support.
167 182
@@ -169,6 +184,7 @@ config M5307
169 bool "MCF5307" 184 bool "MCF5307"
170 select COLDFIRE_SW_A7 185 select COLDFIRE_SW_A7
171 select HAVE_CACHE_CB 186 select HAVE_CACHE_CB
187 select HAVE_MBAR
172 help 188 help
173 Motorola ColdFire 5307 processor support. 189 Motorola ColdFire 5307 processor support.
174 190
@@ -182,18 +198,21 @@ config M5407
182 bool "MCF5407" 198 bool "MCF5407"
183 select COLDFIRE_SW_A7 199 select COLDFIRE_SW_A7
184 select HAVE_CACHE_CB 200 select HAVE_CACHE_CB
201 select HAVE_MBAR
185 help 202 help
186 Motorola ColdFire 5407 processor support. 203 Motorola ColdFire 5407 processor support.
187 204
188config M547x 205config M547x
189 bool "MCF547x" 206 bool "MCF547x"
190 select HAVE_CACHE_CB 207 select HAVE_CACHE_CB
208 select HAVE_MBAR
191 help 209 help
192 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. 210 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
193 211
194config M548x 212config M548x
195 bool "MCF548x" 213 bool "MCF548x"
196 select HAVE_CACHE_CB 214 select HAVE_CACHE_CB
215 select HAVE_MBAR
197 help 216 help
198 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. 217 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
199 218
@@ -241,17 +260,6 @@ config CLOCK_FREQ
241 if it is fitted (there are some exceptions). This value will be 260 if it is fitted (there are some exceptions). This value will be
242 specific to the exact CPU that you are using. 261 specific to the exact CPU that you are using.
243 262
244config CLOCK_DIV
245 int "Set the core/bus clock divide ratio"
246 default "1"
247 depends on CLOCK_SET
248 help
249 On many SoC style CPUs the master CPU clock is also used to drive
250 on-chip peripherals. The clock that is distributed to these
251 peripherals is sometimes a fixed ratio of the master clock
252 frequency. If so then set this to the divider ratio of the
253 master clock to the peripheral clock. If not sure then select 1.
254
255config OLDMASK 263config OLDMASK
256 bool "Old mask 5307 (1H55J) silicon" 264 bool "Old mask 5307 (1H55J) silicon"
257 depends on M5307 265 depends on M5307
@@ -500,6 +508,12 @@ config M5407C3
500 help 508 help
501 Support for the Motorola M5407C3 board. 509 Support for the Motorola M5407C3 board.
502 510
511config FIREBEE
512 bool "FireBee board support"
513 depends on M547x
514 help
515 Support for the FireBee ColdFire 5475 based board.
516
503config CLEOPATRA 517config CLEOPATRA
504 bool "Feith CLEOPATRA board support" 518 bool "Feith CLEOPATRA board support"
505 depends on (M5307 || M5407) 519 depends on (M5307 || M5407)
@@ -649,6 +663,28 @@ config VECTORBASE
649 platforms this address is programmed into the VBR register, thus 663 platforms this address is programmed into the VBR register, thus
650 actually setting the address to use. 664 actually setting the address to use.
651 665
666config MBAR
667 hex "Address of the MBAR (internal peripherals)"
668 default "0x10000000"
669 depends on HAVE_MBAR
670 help
671 Define the address of the internal system peripherals. This value
672 is set in the processors MBAR register. This is generally setup by
673 the boot loader, and will not be written by the kernel. By far most
674 ColdFire boards use the default 0x10000000 value, so if unsure then
675 use this.
676
677config IPSBAR
678 hex "Address of the IPSBAR (internal peripherals)"
679 default "0x40000000"
680 depends on HAVE_IPSBAR
681 help
682 Define the address of the internal system peripherals. This value
683 is set in the processors IPSBAR register. This is generally setup by
684 the boot loader, and will not be written by the kernel. By far most
685 ColdFire boards use the default 0x40000000 value, so if unsure then
686 use this.
687
652config KERNELBASE 688config KERNELBASE
653 hex "Address of the base of kernel code" 689 hex "Address of the base of kernel code"
654 default "0x400" 690 default "0x400"
diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c
index c9cac36d4422..c7dd48f37bee 100644
--- a/arch/m68knommu/kernel/irq.c
+++ b/arch/m68knommu/kernel/irq.c
@@ -38,11 +38,13 @@ int show_interrupts(struct seq_file *p, void *v)
38 seq_puts(p, " CPU0\n"); 38 seq_puts(p, " CPU0\n");
39 39
40 if (irq < NR_IRQS) { 40 if (irq < NR_IRQS) {
41 ap = irq_desc[irq].action; 41 struct irq_desc *desc = irq_to_desc(irq);
42
43 ap = desc->action;
42 if (ap) { 44 if (ap) {
43 seq_printf(p, "%3d: ", irq); 45 seq_printf(p, "%3d: ", irq);
44 seq_printf(p, "%10u ", kstat_irqs(irq)); 46 seq_printf(p, "%10u ", kstat_irqs(irq));
45 seq_printf(p, "%14s ", irq_desc[irq].chip->name); 47 seq_printf(p, "%14s ", get_irq_desc_chip(desc)->name);
46 48
47 seq_printf(p, "%s", ap->name); 49 seq_printf(p, "%s", ap->name);
48 for (ap = ap->next; ap; ap = ap->next) 50 for (ap = ap->next; ap; ap = ap->next)
diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68knommu/platform/5206/gpio.c
index 60f779ce1651..b9ab4a120f28 100644
--- a/arch/m68knommu/platform/5206/gpio.c
+++ b/arch/m68knommu/platform/5206/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 8, 33 .ngpio = 8,
34 }, 34 },
35 .pddr = MCFSIM_PADDR, 35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT, 36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT, 37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 }, 38 },
39}; 39};
40 40
diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68knommu/platform/5206e/gpio.c
index 60f779ce1651..b9ab4a120f28 100644
--- a/arch/m68knommu/platform/5206e/gpio.c
+++ b/arch/m68knommu/platform/5206e/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 8, 33 .ngpio = 8,
34 }, 34 },
35 .pddr = MCFSIM_PADDR, 35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT, 36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT, 37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 }, 38 },
39}; 39};
40 40
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 71d2ba474c63..621238f1a219 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -27,15 +27,15 @@
27 27
28static struct mcf_platform_uart m520x_uart_platform[] = { 28static struct mcf_platform_uart m520x_uart_platform[] = {
29 { 29 {
30 .mapbase = MCF_MBAR + MCFUART_BASE1, 30 .mapbase = MCFUART_BASE1,
31 .irq = MCFINT_VECBASE + MCFINT_UART0, 31 .irq = MCFINT_VECBASE + MCFINT_UART0,
32 }, 32 },
33 { 33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE2, 34 .mapbase = MCFUART_BASE2,
35 .irq = MCFINT_VECBASE + MCFINT_UART1, 35 .irq = MCFINT_VECBASE + MCFINT_UART1,
36 }, 36 },
37 { 37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE3, 38 .mapbase = MCFUART_BASE3,
39 .irq = MCFINT_VECBASE + MCFINT_UART2, 39 .irq = MCFINT_VECBASE + MCFINT_UART2,
40 }, 40 },
41 { }, 41 { },
@@ -49,8 +49,8 @@ static struct platform_device m520x_uart = {
49 49
50static struct resource m520x_fec_resources[] = { 50static struct resource m520x_fec_resources[] = {
51 { 51 {
52 .start = MCF_MBAR + 0x30000, 52 .start = MCFFEC_BASE,
53 .end = MCF_MBAR + 0x30000 + 0x7ff, 53 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
54 .flags = IORESOURCE_MEM, 54 .flags = IORESOURCE_MEM,
55 }, 55 },
56 { 56 {
@@ -208,11 +208,11 @@ static void __init m520x_qspi_init(void)
208{ 208{
209 u16 par; 209 u16 par;
210 /* setup Port QS for QSPI with gpio CS control */ 210 /* setup Port QS for QSPI with gpio CS control */
211 writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI); 211 writeb(0x3f, MCF_GPIO_PAR_QSPI);
212 /* make U1CTS and U2RTS gpio for cs_control */ 212 /* make U1CTS and U2RTS gpio for cs_control */
213 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 213 par = readw(MCF_GPIO_PAR_UART);
214 par &= 0x00ff; 214 par &= 0x00ff;
215 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); 215 writew(par, MCF_GPIO_PAR_UART);
216} 216}
217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ 217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
218 218
@@ -234,23 +234,23 @@ static void __init m520x_uart_init_line(int line, int irq)
234 234
235 switch (line) { 235 switch (line) {
236 case 0: 236 case 0:
237 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 237 par = readw(MCF_GPIO_PAR_UART);
238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | 238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
239 MCF_GPIO_PAR_UART_PAR_URXD0; 239 MCF_GPIO_PAR_UART_PAR_URXD0;
240 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); 240 writew(par, MCF_GPIO_PAR_UART);
241 break; 241 break;
242 case 1: 242 case 1:
243 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 243 par = readw(MCF_GPIO_PAR_UART);
244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | 244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
245 MCF_GPIO_PAR_UART_PAR_URXD1; 245 MCF_GPIO_PAR_UART_PAR_URXD1;
246 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); 246 writew(par, MCF_GPIO_PAR_UART);
247 break; 247 break;
248 case 2: 248 case 2:
249 par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 249 par2 = readb(MCF_GPIO_PAR_FECI2C);
250 par2 &= ~0x0F; 250 par2 &= ~0x0F;
251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | 251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; 252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
253 writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 253 writeb(par2, MCF_GPIO_PAR_FECI2C);
254 break; 254 break;
255 } 255 }
256} 256}
@@ -271,11 +271,11 @@ static void __init m520x_fec_init(void)
271 u8 v; 271 u8 v;
272 272
273 /* Set multi-function pins to ethernet mode */ 273 /* Set multi-function pins to ethernet mode */
274 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC); 274 v = readb(MCF_GPIO_PAR_FEC);
275 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC); 275 writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
276 276
277 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 277 v = readb(MCF_GPIO_PAR_FECI2C);
278 writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 278 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
279} 279}
280 280
281/***************************************************************************/ 281/***************************************************************************/
diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68knommu/platform/520x/gpio.c
index 15b5bb62a698..d757328563d1 100644
--- a/arch/m68knommu/platform/520x/gpio.c
+++ b/arch/m68knommu/platform/520x/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 8, 33 .ngpio = 8,
34 }, 34 },
35 .pddr = MCFEPORT_EPDDR, 35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR, 36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR, 37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 }, 38 },
39 { 39 {
40 .gpio_chip = { 40 .gpio_chip = {
@@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
48 .base = 8, 48 .base = 8,
49 .ngpio = 4, 49 .ngpio = 4,
50 }, 50 },
51 .pddr = MCFGPIO_PDDR_BUSCTL, 51 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
52 .podr = MCFGPIO_PODR_BUSCTL, 52 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
53 .ppdr = MCFGPIO_PPDSDR_BUSCTL, 53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
54 .setr = MCFGPIO_PPDSDR_BUSCTL, 54 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
55 .clrr = MCFGPIO_PCLRR_BUSCTL, 55 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
56 }, 56 },
57 { 57 {
58 .gpio_chip = { 58 .gpio_chip = {
@@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
66 .base = 16, 66 .base = 16,
67 .ngpio = 4, 67 .ngpio = 4,
68 }, 68 },
69 .pddr = MCFGPIO_PDDR_BE, 69 .pddr = (void __iomem *) MCFGPIO_PDDR_BE,
70 .podr = MCFGPIO_PODR_BE, 70 .podr = (void __iomem *) MCFGPIO_PODR_BE,
71 .ppdr = MCFGPIO_PPDSDR_BE, 71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
72 .setr = MCFGPIO_PPDSDR_BE, 72 .setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
73 .clrr = MCFGPIO_PCLRR_BE, 73 .clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
74 }, 74 },
75 { 75 {
76 .gpio_chip = { 76 .gpio_chip = {
@@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
84 .base = 25, 84 .base = 25,
85 .ngpio = 3, 85 .ngpio = 3,
86 }, 86 },
87 .pddr = MCFGPIO_PDDR_CS, 87 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
88 .podr = MCFGPIO_PODR_CS, 88 .podr = (void __iomem *) MCFGPIO_PODR_CS,
89 .ppdr = MCFGPIO_PPDSDR_CS, 89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
90 .setr = MCFGPIO_PPDSDR_CS, 90 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
91 .clrr = MCFGPIO_PCLRR_CS, 91 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
92 }, 92 },
93 { 93 {
94 .gpio_chip = { 94 .gpio_chip = {
@@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
102 .base = 32, 102 .base = 32,
103 .ngpio = 4, 103 .ngpio = 4,
104 }, 104 },
105 .pddr = MCFGPIO_PDDR_FECI2C, 105 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
106 .podr = MCFGPIO_PODR_FECI2C, 106 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
107 .ppdr = MCFGPIO_PPDSDR_FECI2C, 107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
108 .setr = MCFGPIO_PPDSDR_FECI2C, 108 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
109 .clrr = MCFGPIO_PCLRR_FECI2C, 109 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
110 }, 110 },
111 { 111 {
112 .gpio_chip = { 112 .gpio_chip = {
@@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
120 .base = 40, 120 .base = 40,
121 .ngpio = 4, 121 .ngpio = 4,
122 }, 122 },
123 .pddr = MCFGPIO_PDDR_QSPI, 123 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
124 .podr = MCFGPIO_PODR_QSPI, 124 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
125 .ppdr = MCFGPIO_PPDSDR_QSPI, 125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
126 .setr = MCFGPIO_PPDSDR_QSPI, 126 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
127 .clrr = MCFGPIO_PCLRR_QSPI, 127 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
128 }, 128 },
129 { 129 {
130 .gpio_chip = { 130 .gpio_chip = {
@@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
138 .base = 48, 138 .base = 48,
139 .ngpio = 4, 139 .ngpio = 4,
140 }, 140 },
141 .pddr = MCFGPIO_PDDR_TIMER, 141 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
142 .podr = MCFGPIO_PODR_TIMER, 142 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
143 .ppdr = MCFGPIO_PPDSDR_TIMER, 143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
144 .setr = MCFGPIO_PPDSDR_TIMER, 144 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
145 .clrr = MCFGPIO_PCLRR_TIMER, 145 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
146 }, 146 },
147 { 147 {
148 .gpio_chip = { 148 .gpio_chip = {
@@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
156 .base = 56, 156 .base = 56,
157 .ngpio = 8, 157 .ngpio = 8,
158 }, 158 },
159 .pddr = MCFGPIO_PDDR_UART, 159 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
160 .podr = MCFGPIO_PODR_UART, 160 .podr = (void __iomem *) MCFGPIO_PODR_UART,
161 .ppdr = MCFGPIO_PPDSDR_UART, 161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
162 .setr = MCFGPIO_PPDSDR_UART, 162 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
163 .clrr = MCFGPIO_PCLRR_UART, 163 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
164 }, 164 },
165 { 165 {
166 .gpio_chip = { 166 .gpio_chip = {
@@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
174 .base = 64, 174 .base = 64,
175 .ngpio = 8, 175 .ngpio = 8,
176 }, 176 },
177 .pddr = MCFGPIO_PDDR_FECH, 177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
178 .podr = MCFGPIO_PODR_FECH, 178 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
179 .ppdr = MCFGPIO_PPDSDR_FECH, 179 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
180 .setr = MCFGPIO_PPDSDR_FECH, 180 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
181 .clrr = MCFGPIO_PCLRR_FECH, 181 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
182 }, 182 },
183 { 183 {
184 .gpio_chip = { 184 .gpio_chip = {
@@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
192 .base = 72, 192 .base = 72,
193 .ngpio = 8, 193 .ngpio = 8,
194 }, 194 },
195 .pddr = MCFGPIO_PDDR_FECL, 195 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
196 .podr = MCFGPIO_PODR_FECL, 196 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
197 .ppdr = MCFGPIO_PPDSDR_FECL, 197 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
198 .setr = MCFGPIO_PPDSDR_FECL, 198 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
199 .clrr = MCFGPIO_PCLRR_FECL, 199 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
200 }, 200 },
201}; 201};
202 202
diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c
index 8980f6d7715a..418a76feb1e3 100644
--- a/arch/m68knommu/platform/523x/config.c
+++ b/arch/m68knommu/platform/523x/config.c
@@ -28,15 +28,15 @@
28 28
29static struct mcf_platform_uart m523x_uart_platform[] = { 29static struct mcf_platform_uart m523x_uart_platform[] = {
30 { 30 {
31 .mapbase = MCF_MBAR + MCFUART_BASE1, 31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0, 32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 }, 33 },
34 { 34 {
35 .mapbase = MCF_MBAR + MCFUART_BASE2, 35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1, 36 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
37 }, 37 },
38 { 38 {
39 .mapbase = MCF_MBAR + MCFUART_BASE3, 39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2, 40 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
41 }, 41 },
42 { }, 42 { },
@@ -50,8 +50,8 @@ static struct platform_device m523x_uart = {
50 50
51static struct resource m523x_fec_resources[] = { 51static struct resource m523x_fec_resources[] = {
52 { 52 {
53 .start = MCF_MBAR + 0x1000, 53 .start = MCFFEC_BASE,
54 .end = MCF_MBAR + 0x1000 + 0x7ff, 54 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 }, 56 },
57 { 57 {
diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c
index a8842dc27839..327ebf142c8e 100644
--- a/arch/m68knommu/platform/523x/gpio.c
+++ b/arch/m68knommu/platform/523x/gpio.c
@@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
33 .base = 1, 33 .base = 1,
34 .ngpio = 7, 34 .ngpio = 7,
35 }, 35 },
36 .pddr = MCFEPORT_EPDDR, 36 .pddr = (void __iomem *) MCFEPORT_EPDDR,
37 .podr = MCFEPORT_EPDR, 37 .podr = (void __iomem *) MCFEPORT_EPDR,
38 .ppdr = MCFEPORT_EPPDR, 38 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
39 }, 39 },
40 { 40 {
41 .gpio_chip = { 41 .gpio_chip = {
@@ -49,11 +49,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
49 .base = 13, 49 .base = 13,
50 .ngpio = 3, 50 .ngpio = 3,
51 }, 51 },
52 .pddr = MCFGPIO_PDDR_ADDR, 52 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
53 .podr = MCFGPIO_PODR_ADDR, 53 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
54 .ppdr = MCFGPIO_PPDSDR_ADDR, 54 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
55 .setr = MCFGPIO_PPDSDR_ADDR, 55 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .clrr = MCFGPIO_PCLRR_ADDR, 56 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
57 }, 57 },
58 { 58 {
59 .gpio_chip = { 59 .gpio_chip = {
@@ -67,11 +67,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
67 .base = 16, 67 .base = 16,
68 .ngpio = 8, 68 .ngpio = 8,
69 }, 69 },
70 .pddr = MCFGPIO_PDDR_DATAH, 70 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
71 .podr = MCFGPIO_PODR_DATAH, 71 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
72 .ppdr = MCFGPIO_PPDSDR_DATAH, 72 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
73 .setr = MCFGPIO_PPDSDR_DATAH, 73 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .clrr = MCFGPIO_PCLRR_DATAH, 74 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
75 }, 75 },
76 { 76 {
77 .gpio_chip = { 77 .gpio_chip = {
@@ -85,11 +85,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
85 .base = 24, 85 .base = 24,
86 .ngpio = 8, 86 .ngpio = 8,
87 }, 87 },
88 .pddr = MCFGPIO_PDDR_DATAL, 88 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
89 .podr = MCFGPIO_PODR_DATAL, 89 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
90 .ppdr = MCFGPIO_PPDSDR_DATAL, 90 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
91 .setr = MCFGPIO_PPDSDR_DATAL, 91 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .clrr = MCFGPIO_PCLRR_DATAL, 92 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
93 }, 93 },
94 { 94 {
95 .gpio_chip = { 95 .gpio_chip = {
@@ -103,11 +103,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
103 .base = 32, 103 .base = 32,
104 .ngpio = 8, 104 .ngpio = 8,
105 }, 105 },
106 .pddr = MCFGPIO_PDDR_BUSCTL, 106 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
107 .podr = MCFGPIO_PODR_BUSCTL, 107 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
108 .ppdr = MCFGPIO_PPDSDR_BUSCTL, 108 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
109 .setr = MCFGPIO_PPDSDR_BUSCTL, 109 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .clrr = MCFGPIO_PCLRR_BUSCTL, 110 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
111 }, 111 },
112 { 112 {
113 .gpio_chip = { 113 .gpio_chip = {
@@ -121,11 +121,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
121 .base = 40, 121 .base = 40,
122 .ngpio = 4, 122 .ngpio = 4,
123 }, 123 },
124 .pddr = MCFGPIO_PDDR_BS, 124 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
125 .podr = MCFGPIO_PODR_BS, 125 .podr = (void __iomem *) MCFGPIO_PODR_BS,
126 .ppdr = MCFGPIO_PPDSDR_BS, 126 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
127 .setr = MCFGPIO_PPDSDR_BS, 127 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .clrr = MCFGPIO_PCLRR_BS, 128 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
129 }, 129 },
130 { 130 {
131 .gpio_chip = { 131 .gpio_chip = {
@@ -139,11 +139,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
139 .base = 49, 139 .base = 49,
140 .ngpio = 7, 140 .ngpio = 7,
141 }, 141 },
142 .pddr = MCFGPIO_PDDR_CS, 142 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
143 .podr = MCFGPIO_PODR_CS, 143 .podr = (void __iomem *) MCFGPIO_PODR_CS,
144 .ppdr = MCFGPIO_PPDSDR_CS, 144 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
145 .setr = MCFGPIO_PPDSDR_CS, 145 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .clrr = MCFGPIO_PCLRR_CS, 146 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
147 }, 147 },
148 { 148 {
149 .gpio_chip = { 149 .gpio_chip = {
@@ -157,11 +157,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
157 .base = 56, 157 .base = 56,
158 .ngpio = 6, 158 .ngpio = 6,
159 }, 159 },
160 .pddr = MCFGPIO_PDDR_SDRAM, 160 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
161 .podr = MCFGPIO_PODR_SDRAM, 161 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
162 .ppdr = MCFGPIO_PPDSDR_SDRAM, 162 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
163 .setr = MCFGPIO_PPDSDR_SDRAM, 163 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .clrr = MCFGPIO_PCLRR_SDRAM, 164 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
165 }, 165 },
166 { 166 {
167 .gpio_chip = { 167 .gpio_chip = {
@@ -175,11 +175,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
175 .base = 64, 175 .base = 64,
176 .ngpio = 4, 176 .ngpio = 4,
177 }, 177 },
178 .pddr = MCFGPIO_PDDR_FECI2C, 178 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
179 .podr = MCFGPIO_PODR_FECI2C, 179 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
180 .ppdr = MCFGPIO_PPDSDR_FECI2C, 180 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
181 .setr = MCFGPIO_PPDSDR_FECI2C, 181 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .clrr = MCFGPIO_PCLRR_FECI2C, 182 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
183 }, 183 },
184 { 184 {
185 .gpio_chip = { 185 .gpio_chip = {
@@ -193,11 +193,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
193 .base = 72, 193 .base = 72,
194 .ngpio = 2, 194 .ngpio = 2,
195 }, 195 },
196 .pddr = MCFGPIO_PDDR_UARTH, 196 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
197 .podr = MCFGPIO_PODR_UARTH, 197 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
198 .ppdr = MCFGPIO_PPDSDR_UARTH, 198 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
199 .setr = MCFGPIO_PPDSDR_UARTH, 199 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .clrr = MCFGPIO_PCLRR_UARTH, 200 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
201 }, 201 },
202 { 202 {
203 .gpio_chip = { 203 .gpio_chip = {
@@ -211,11 +211,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
211 .base = 80, 211 .base = 80,
212 .ngpio = 8, 212 .ngpio = 8,
213 }, 213 },
214 .pddr = MCFGPIO_PDDR_UARTL, 214 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
215 .podr = MCFGPIO_PODR_UARTL, 215 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
216 .ppdr = MCFGPIO_PPDSDR_UARTL, 216 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
217 .setr = MCFGPIO_PPDSDR_UARTL, 217 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .clrr = MCFGPIO_PCLRR_UARTL, 218 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
219 }, 219 },
220 { 220 {
221 .gpio_chip = { 221 .gpio_chip = {
@@ -229,11 +229,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
229 .base = 88, 229 .base = 88,
230 .ngpio = 5, 230 .ngpio = 5,
231 }, 231 },
232 .pddr = MCFGPIO_PDDR_QSPI, 232 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
233 .podr = MCFGPIO_PODR_QSPI, 233 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
234 .ppdr = MCFGPIO_PPDSDR_QSPI, 234 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
235 .setr = MCFGPIO_PPDSDR_QSPI, 235 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .clrr = MCFGPIO_PCLRR_QSPI, 236 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
237 }, 237 },
238 { 238 {
239 .gpio_chip = { 239 .gpio_chip = {
@@ -247,11 +247,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
247 .base = 96, 247 .base = 96,
248 .ngpio = 8, 248 .ngpio = 8,
249 }, 249 },
250 .pddr = MCFGPIO_PDDR_TIMER, 250 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
251 .podr = MCFGPIO_PODR_TIMER, 251 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
252 .ppdr = MCFGPIO_PPDSDR_TIMER, 252 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
253 .setr = MCFGPIO_PPDSDR_TIMER, 253 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .clrr = MCFGPIO_PCLRR_TIMER, 254 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
255 }, 255 },
256 { 256 {
257 .gpio_chip = { 257 .gpio_chip = {
@@ -265,11 +265,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
265 .base = 104, 265 .base = 104,
266 .ngpio = 3, 266 .ngpio = 3,
267 }, 267 },
268 .pddr = MCFGPIO_PDDR_ETPU, 268 .pddr = (void __iomem *) MCFGPIO_PDDR_ETPU,
269 .podr = MCFGPIO_PODR_ETPU, 269 .podr = (void __iomem *) MCFGPIO_PODR_ETPU,
270 .ppdr = MCFGPIO_PPDSDR_ETPU, 270 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
271 .setr = MCFGPIO_PPDSDR_ETPU, 271 .setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
272 .clrr = MCFGPIO_PCLRR_ETPU, 272 .clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU,
273 }, 273 },
274}; 274};
275 275
diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c
index c611eab8b3b6..2b56c6ef65bf 100644
--- a/arch/m68knommu/platform/5249/gpio.c
+++ b/arch/m68knommu/platform/5249/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 32, 33 .ngpio = 32,
34 }, 34 },
35 .pddr = MCFSIM2_GPIOENABLE, 35 .pddr = (void __iomem *) MCFSIM2_GPIOENABLE,
36 .podr = MCFSIM2_GPIOWRITE, 36 .podr = (void __iomem *) MCFSIM2_GPIOWRITE,
37 .ppdr = MCFSIM2_GPIOREAD, 37 .ppdr = (void __iomem *) MCFSIM2_GPIOREAD,
38 }, 38 },
39 { 39 {
40 .gpio_chip = { 40 .gpio_chip = {
@@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
48 .base = 32, 48 .base = 32,
49 .ngpio = 32, 49 .ngpio = 32,
50 }, 50 },
51 .pddr = MCFSIM2_GPIO1ENABLE, 51 .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE,
52 .podr = MCFSIM2_GPIO1WRITE, 52 .podr = (void __iomem *) MCFSIM2_GPIO1WRITE,
53 .ppdr = MCFSIM2_GPIO1READ, 53 .ppdr = (void __iomem *) MCFSIM2_GPIO1READ,
54 }, 54 },
55}; 55};
56 56
diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c
index c5151f846591..8f4b63e17366 100644
--- a/arch/m68knommu/platform/5249/intc2.c
+++ b/arch/m68knommu/platform/5249/intc2.c
@@ -17,32 +17,32 @@
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19 19
20static void intc2_irq_gpio_mask(unsigned int irq) 20static void intc2_irq_gpio_mask(struct irq_data *d)
21{ 21{
22 u32 imr; 22 u32 imr;
23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0)); 24 imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
26} 26}
27 27
28static void intc2_irq_gpio_unmask(unsigned int irq) 28static void intc2_irq_gpio_unmask(struct irq_data *d)
29{ 29{
30 u32 imr; 30 u32 imr;
31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0)); 32 imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
34} 34}
35 35
36static void intc2_irq_gpio_ack(unsigned int irq) 36static void intc2_irq_gpio_ack(struct irq_data *d)
37{ 37{
38 writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); 38 writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
39} 39}
40 40
41static struct irq_chip intc2_irq_gpio_chip = { 41static struct irq_chip intc2_irq_gpio_chip = {
42 .name = "CF-INTC2", 42 .name = "CF-INTC2",
43 .mask = intc2_irq_gpio_mask, 43 .irq_mask = intc2_irq_gpio_mask,
44 .unmask = intc2_irq_gpio_unmask, 44 .irq_unmask = intc2_irq_gpio_unmask,
45 .ack = intc2_irq_gpio_ack, 45 .irq_ack = intc2_irq_gpio_ack,
46}; 46};
47 47
48static int __init mcf_intc2_init(void) 48static int __init mcf_intc2_init(void)
@@ -51,7 +51,7 @@ static int __init mcf_intc2_init(void)
51 51
52 /* GPIO interrupt sources */ 52 /* GPIO interrupt sources */
53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { 53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
54 irq_desc[irq].chip = &intc2_irq_gpio_chip; 54 set_irq_chip(irq, &intc2_irq_gpio_chip);
55 set_irq_handler(irq, handle_edge_irq); 55 set_irq_handler(irq, handle_edge_irq);
56 } 56 }
57 57
diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68knommu/platform/5272/gpio.c
index 459db89a89cc..57ac10a5d7f7 100644
--- a/arch/m68knommu/platform/5272/gpio.c
+++ b/arch/m68knommu/platform/5272/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 16, 33 .ngpio = 16,
34 }, 34 },
35 .pddr = MCFSIM_PADDR, 35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT, 36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT, 37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 }, 38 },
39 { 39 {
40 .gpio_chip = { 40 .gpio_chip = {
@@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
48 .base = 16, 48 .base = 16,
49 .ngpio = 16, 49 .ngpio = 16,
50 }, 50 },
51 .pddr = MCFSIM_PBDDR, 51 .pddr = (void __iomem *) MCFSIM_PBDDR,
52 .podr = MCFSIM_PBDAT, 52 .podr = (void __iomem *) MCFSIM_PBDAT,
53 .ppdr = MCFSIM_PBDAT, 53 .ppdr = (void __iomem *) MCFSIM_PBDAT,
54 }, 54 },
55 { 55 {
56 .gpio_chip = { 56 .gpio_chip = {
@@ -64,9 +64,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
64 .base = 32, 64 .base = 32,
65 .ngpio = 16, 65 .ngpio = 16,
66 }, 66 },
67 .pddr = MCFSIM_PCDDR, 67 .pddr = (void __iomem *) MCFSIM_PCDDR,
68 .podr = MCFSIM_PCDAT, 68 .podr = (void __iomem *) MCFSIM_PCDAT,
69 .ppdr = MCFSIM_PCDAT, 69 .ppdr = (void __iomem *) MCFSIM_PCDAT,
70 }, 70 },
71}; 71};
72 72
diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
index 3cf681c177aa..969ff0a467c6 100644
--- a/arch/m68knommu/platform/5272/intc.c
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -78,8 +78,10 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
78 * an interrupt on this irq (for the external irqs). So this mask function 78 * an interrupt on this irq (for the external irqs). So this mask function
79 * is also an ack_mask function. 79 * is also an ack_mask function.
80 */ 80 */
81static void intc_irq_mask(unsigned int irq) 81static void intc_irq_mask(struct irq_data *d)
82{ 82{
83 unsigned int irq = d->irq;
84
83 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { 85 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
84 u32 v; 86 u32 v;
85 irq -= MCFINT_VECBASE; 87 irq -= MCFINT_VECBASE;
@@ -88,8 +90,10 @@ static void intc_irq_mask(unsigned int irq)
88 } 90 }
89} 91}
90 92
91static void intc_irq_unmask(unsigned int irq) 93static void intc_irq_unmask(struct irq_data *d)
92{ 94{
95 unsigned int irq = d->irq;
96
93 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { 97 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
94 u32 v; 98 u32 v;
95 irq -= MCFINT_VECBASE; 99 irq -= MCFINT_VECBASE;
@@ -98,8 +102,10 @@ static void intc_irq_unmask(unsigned int irq)
98 } 102 }
99} 103}
100 104
101static void intc_irq_ack(unsigned int irq) 105static void intc_irq_ack(struct irq_data *d)
102{ 106{
107 unsigned int irq = d->irq;
108
103 /* Only external interrupts are acked */ 109 /* Only external interrupts are acked */
104 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { 110 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
105 irq -= MCFINT_VECBASE; 111 irq -= MCFINT_VECBASE;
@@ -113,8 +119,10 @@ static void intc_irq_ack(unsigned int irq)
113 } 119 }
114} 120}
115 121
116static int intc_irq_set_type(unsigned int irq, unsigned int type) 122static int intc_irq_set_type(struct irq_data *d, unsigned int type)
117{ 123{
124 unsigned int irq = d->irq;
125
118 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { 126 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
119 irq -= MCFINT_VECBASE; 127 irq -= MCFINT_VECBASE;
120 if (intc_irqmap[irq].ack) { 128 if (intc_irqmap[irq].ack) {
@@ -137,20 +145,17 @@ static int intc_irq_set_type(unsigned int irq, unsigned int type)
137 */ 145 */
138static void intc_external_irq(unsigned int irq, struct irq_desc *desc) 146static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
139{ 147{
140 kstat_incr_irqs_this_cpu(irq, desc); 148 get_irq_desc_chip(desc)->irq_ack(&desc->irq_data);
141 desc->status |= IRQ_INPROGRESS; 149 handle_simple_irq(irq, desc);
142 desc->chip->ack(irq);
143 handle_IRQ_event(irq, desc->action);
144 desc->status &= ~IRQ_INPROGRESS;
145} 150}
146 151
147static struct irq_chip intc_irq_chip = { 152static struct irq_chip intc_irq_chip = {
148 .name = "CF-INTC", 153 .name = "CF-INTC",
149 .mask = intc_irq_mask, 154 .irq_mask = intc_irq_mask,
150 .unmask = intc_irq_unmask, 155 .irq_unmask = intc_irq_unmask,
151 .mask_ack = intc_irq_mask, 156 .irq_mask_ack = intc_irq_mask,
152 .ack = intc_irq_ack, 157 .irq_ack = intc_irq_ack,
153 .set_type = intc_irq_set_type, 158 .irq_set_type = intc_irq_set_type,
154}; 159};
155 160
156void __init init_IRQ(void) 161void __init init_IRQ(void)
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index 3d9c35c98b98..fa359593b613 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -28,15 +28,15 @@
28 28
29static struct mcf_platform_uart m527x_uart_platform[] = { 29static struct mcf_platform_uart m527x_uart_platform[] = {
30 { 30 {
31 .mapbase = MCF_MBAR + MCFUART_BASE1, 31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0, 32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 }, 33 },
34 { 34 {
35 .mapbase = MCF_MBAR + MCFUART_BASE2, 35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART1, 36 .irq = MCFINT_VECBASE + MCFINT_UART1,
37 }, 37 },
38 { 38 {
39 .mapbase = MCF_MBAR + MCFUART_BASE3, 39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART2, 40 .irq = MCFINT_VECBASE + MCFINT_UART2,
41 }, 41 },
42 { }, 42 { },
@@ -50,8 +50,8 @@ static struct platform_device m527x_uart = {
50 50
51static struct resource m527x_fec0_resources[] = { 51static struct resource m527x_fec0_resources[] = {
52 { 52 {
53 .start = MCF_MBAR + 0x1000, 53 .start = MCFFEC_BASE0,
54 .end = MCF_MBAR + 0x1000 + 0x7ff, 54 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 }, 56 },
57 { 57 {
@@ -73,8 +73,8 @@ static struct resource m527x_fec0_resources[] = {
73 73
74static struct resource m527x_fec1_resources[] = { 74static struct resource m527x_fec1_resources[] = {
75 { 75 {
76 .start = MCF_MBAR + 0x1800, 76 .start = MCFFEC_BASE1,
77 .end = MCF_MBAR + 0x1800 + 0x7ff, 77 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
78 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
79 }, 79 },
80 { 80 {
diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68knommu/platform/527x/gpio.c
index 0b56e19db0f8..205da0aa0f2d 100644
--- a/arch/m68knommu/platform/527x/gpio.c
+++ b/arch/m68knommu/platform/527x/gpio.c
@@ -34,9 +34,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
34 .base = 1, 34 .base = 1,
35 .ngpio = 7, 35 .ngpio = 7,
36 }, 36 },
37 .pddr = MCFEPORT_EPDDR, 37 .pddr = (void __iomem *) MCFEPORT_EPDDR,
38 .podr = MCFEPORT_EPDR, 38 .podr = (void __iomem *) MCFEPORT_EPDR,
39 .ppdr = MCFEPORT_EPPDR, 39 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
40 }, 40 },
41 { 41 {
42 .gpio_chip = { 42 .gpio_chip = {
@@ -50,11 +50,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
50 .base = 13, 50 .base = 13,
51 .ngpio = 3, 51 .ngpio = 3,
52 }, 52 },
53 .pddr = MCFGPIO_PDDR_ADDR, 53 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
54 .podr = MCFGPIO_PODR_ADDR, 54 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
55 .ppdr = MCFGPIO_PPDSDR_ADDR, 55 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .setr = MCFGPIO_PPDSDR_ADDR, 56 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
57 .clrr = MCFGPIO_PCLRR_ADDR, 57 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
58 }, 58 },
59 { 59 {
60 .gpio_chip = { 60 .gpio_chip = {
@@ -68,11 +68,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
68 .base = 16, 68 .base = 16,
69 .ngpio = 8, 69 .ngpio = 8,
70 }, 70 },
71 .pddr = MCFGPIO_PDDR_DATAH, 71 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
72 .podr = MCFGPIO_PODR_DATAH, 72 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
73 .ppdr = MCFGPIO_PPDSDR_DATAH, 73 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .setr = MCFGPIO_PPDSDR_DATAH, 74 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
75 .clrr = MCFGPIO_PCLRR_DATAH, 75 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
76 }, 76 },
77 { 77 {
78 .gpio_chip = { 78 .gpio_chip = {
@@ -86,11 +86,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
86 .base = 24, 86 .base = 24,
87 .ngpio = 8, 87 .ngpio = 8,
88 }, 88 },
89 .pddr = MCFGPIO_PDDR_DATAL, 89 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
90 .podr = MCFGPIO_PODR_DATAL, 90 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
91 .ppdr = MCFGPIO_PPDSDR_DATAL, 91 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .setr = MCFGPIO_PPDSDR_DATAL, 92 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
93 .clrr = MCFGPIO_PCLRR_DATAL, 93 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
94 }, 94 },
95 { 95 {
96 .gpio_chip = { 96 .gpio_chip = {
@@ -104,11 +104,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
104 .base = 32, 104 .base = 32,
105 .ngpio = 8, 105 .ngpio = 8,
106 }, 106 },
107 .pddr = MCFGPIO_PDDR_BUSCTL, 107 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
108 .podr = MCFGPIO_PODR_BUSCTL, 108 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
109 .ppdr = MCFGPIO_PPDSDR_BUSCTL, 109 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .setr = MCFGPIO_PPDSDR_BUSCTL, 110 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
111 .clrr = MCFGPIO_PCLRR_BUSCTL, 111 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
112 }, 112 },
113 { 113 {
114 .gpio_chip = { 114 .gpio_chip = {
@@ -122,11 +122,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
122 .base = 40, 122 .base = 40,
123 .ngpio = 4, 123 .ngpio = 4,
124 }, 124 },
125 .pddr = MCFGPIO_PDDR_BS, 125 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
126 .podr = MCFGPIO_PODR_BS, 126 .podr = (void __iomem *) MCFGPIO_PODR_BS,
127 .ppdr = MCFGPIO_PPDSDR_BS, 127 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .setr = MCFGPIO_PPDSDR_BS, 128 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
129 .clrr = MCFGPIO_PCLRR_BS, 129 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
130 }, 130 },
131 { 131 {
132 .gpio_chip = { 132 .gpio_chip = {
@@ -140,11 +140,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
140 .base = 49, 140 .base = 49,
141 .ngpio = 7, 141 .ngpio = 7,
142 }, 142 },
143 .pddr = MCFGPIO_PDDR_CS, 143 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
144 .podr = MCFGPIO_PODR_CS, 144 .podr = (void __iomem *) MCFGPIO_PODR_CS,
145 .ppdr = MCFGPIO_PPDSDR_CS, 145 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .setr = MCFGPIO_PPDSDR_CS, 146 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
147 .clrr = MCFGPIO_PCLRR_CS, 147 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
148 }, 148 },
149 { 149 {
150 .gpio_chip = { 150 .gpio_chip = {
@@ -158,11 +158,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
158 .base = 56, 158 .base = 56,
159 .ngpio = 6, 159 .ngpio = 6,
160 }, 160 },
161 .pddr = MCFGPIO_PDDR_SDRAM, 161 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
162 .podr = MCFGPIO_PODR_SDRAM, 162 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
163 .ppdr = MCFGPIO_PPDSDR_SDRAM, 163 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .setr = MCFGPIO_PPDSDR_SDRAM, 164 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
165 .clrr = MCFGPIO_PCLRR_SDRAM, 165 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
166 }, 166 },
167 { 167 {
168 .gpio_chip = { 168 .gpio_chip = {
@@ -176,11 +176,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
176 .base = 64, 176 .base = 64,
177 .ngpio = 4, 177 .ngpio = 4,
178 }, 178 },
179 .pddr = MCFGPIO_PDDR_FECI2C, 179 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
180 .podr = MCFGPIO_PODR_FECI2C, 180 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
181 .ppdr = MCFGPIO_PPDSDR_FECI2C, 181 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .setr = MCFGPIO_PPDSDR_FECI2C, 182 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
183 .clrr = MCFGPIO_PCLRR_FECI2C, 183 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
184 }, 184 },
185 { 185 {
186 .gpio_chip = { 186 .gpio_chip = {
@@ -194,11 +194,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
194 .base = 72, 194 .base = 72,
195 .ngpio = 2, 195 .ngpio = 2,
196 }, 196 },
197 .pddr = MCFGPIO_PDDR_UARTH, 197 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
198 .podr = MCFGPIO_PODR_UARTH, 198 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
199 .ppdr = MCFGPIO_PPDSDR_UARTH, 199 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .setr = MCFGPIO_PPDSDR_UARTH, 200 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
201 .clrr = MCFGPIO_PCLRR_UARTH, 201 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
202 }, 202 },
203 { 203 {
204 .gpio_chip = { 204 .gpio_chip = {
@@ -212,11 +212,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
212 .base = 80, 212 .base = 80,
213 .ngpio = 8, 213 .ngpio = 8,
214 }, 214 },
215 .pddr = MCFGPIO_PDDR_UARTL, 215 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
216 .podr = MCFGPIO_PODR_UARTL, 216 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
217 .ppdr = MCFGPIO_PPDSDR_UARTL, 217 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .setr = MCFGPIO_PPDSDR_UARTL, 218 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
219 .clrr = MCFGPIO_PCLRR_UARTL, 219 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
220 }, 220 },
221 { 221 {
222 .gpio_chip = { 222 .gpio_chip = {
@@ -230,11 +230,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
230 .base = 88, 230 .base = 88,
231 .ngpio = 5, 231 .ngpio = 5,
232 }, 232 },
233 .pddr = MCFGPIO_PDDR_QSPI, 233 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
234 .podr = MCFGPIO_PODR_QSPI, 234 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
235 .ppdr = MCFGPIO_PPDSDR_QSPI, 235 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .setr = MCFGPIO_PPDSDR_QSPI, 236 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
237 .clrr = MCFGPIO_PCLRR_QSPI, 237 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
238 }, 238 },
239 { 239 {
240 .gpio_chip = { 240 .gpio_chip = {
@@ -248,11 +248,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
248 .base = 96, 248 .base = 96,
249 .ngpio = 8, 249 .ngpio = 8,
250 }, 250 },
251 .pddr = MCFGPIO_PDDR_TIMER, 251 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
252 .podr = MCFGPIO_PODR_TIMER, 252 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
253 .ppdr = MCFGPIO_PPDSDR_TIMER, 253 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .setr = MCFGPIO_PPDSDR_TIMER, 254 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
255 .clrr = MCFGPIO_PCLRR_TIMER, 255 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
256 }, 256 },
257#elif defined(CONFIG_M5275) 257#elif defined(CONFIG_M5275)
258 { 258 {
@@ -267,9 +267,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
267 .base = 1, 267 .base = 1,
268 .ngpio = 7, 268 .ngpio = 7,
269 }, 269 },
270 .pddr = MCFEPORT_EPDDR, 270 .pddr = (void __iomem *) MCFEPORT_EPDDR,
271 .podr = MCFEPORT_EPDR, 271 .podr = (void __iomem *) MCFEPORT_EPDR,
272 .ppdr = MCFEPORT_EPPDR, 272 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
273 }, 273 },
274 { 274 {
275 .gpio_chip = { 275 .gpio_chip = {
@@ -283,11 +283,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
283 .base = 8, 283 .base = 8,
284 .ngpio = 8, 284 .ngpio = 8,
285 }, 285 },
286 .pddr = MCFGPIO_PDDR_BUSCTL, 286 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
287 .podr = MCFGPIO_PODR_BUSCTL, 287 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
288 .ppdr = MCFGPIO_PPDSDR_BUSCTL, 288 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
289 .setr = MCFGPIO_PPDSDR_BUSCTL, 289 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
290 .clrr = MCFGPIO_PCLRR_BUSCTL, 290 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
291 }, 291 },
292 { 292 {
293 .gpio_chip = { 293 .gpio_chip = {
@@ -301,11 +301,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
301 .base = 21, 301 .base = 21,
302 .ngpio = 3, 302 .ngpio = 3,
303 }, 303 },
304 .pddr = MCFGPIO_PDDR_ADDR, 304 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
305 .podr = MCFGPIO_PODR_ADDR, 305 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
306 .ppdr = MCFGPIO_PPDSDR_ADDR, 306 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
307 .setr = MCFGPIO_PPDSDR_ADDR, 307 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
308 .clrr = MCFGPIO_PCLRR_ADDR, 308 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
309 }, 309 },
310 { 310 {
311 .gpio_chip = { 311 .gpio_chip = {
@@ -319,11 +319,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
319 .base = 25, 319 .base = 25,
320 .ngpio = 7, 320 .ngpio = 7,
321 }, 321 },
322 .pddr = MCFGPIO_PDDR_CS, 322 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
323 .podr = MCFGPIO_PODR_CS, 323 .podr = (void __iomem *) MCFGPIO_PODR_CS,
324 .ppdr = MCFGPIO_PPDSDR_CS, 324 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
325 .setr = MCFGPIO_PPDSDR_CS, 325 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
326 .clrr = MCFGPIO_PCLRR_CS, 326 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
327 }, 327 },
328 { 328 {
329 .gpio_chip = { 329 .gpio_chip = {
@@ -337,11 +337,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
337 .base = 32, 337 .base = 32,
338 .ngpio = 8, 338 .ngpio = 8,
339 }, 339 },
340 .pddr = MCFGPIO_PDDR_FEC0H, 340 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H,
341 .podr = MCFGPIO_PODR_FEC0H, 341 .podr = (void __iomem *) MCFGPIO_PODR_FEC0H,
342 .ppdr = MCFGPIO_PPDSDR_FEC0H, 342 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
343 .setr = MCFGPIO_PPDSDR_FEC0H, 343 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
344 .clrr = MCFGPIO_PCLRR_FEC0H, 344 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
345 }, 345 },
346 { 346 {
347 .gpio_chip = { 347 .gpio_chip = {
@@ -355,11 +355,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
355 .base = 40, 355 .base = 40,
356 .ngpio = 8, 356 .ngpio = 8,
357 }, 357 },
358 .pddr = MCFGPIO_PDDR_FEC0L, 358 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L,
359 .podr = MCFGPIO_PODR_FEC0L, 359 .podr = (void __iomem *) MCFGPIO_PODR_FEC0L,
360 .ppdr = MCFGPIO_PPDSDR_FEC0L, 360 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
361 .setr = MCFGPIO_PPDSDR_FEC0L, 361 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
362 .clrr = MCFGPIO_PCLRR_FEC0L, 362 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
363 }, 363 },
364 { 364 {
365 .gpio_chip = { 365 .gpio_chip = {
@@ -373,11 +373,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
373 .base = 48, 373 .base = 48,
374 .ngpio = 6, 374 .ngpio = 6,
375 }, 375 },
376 .pddr = MCFGPIO_PDDR_FECI2C, 376 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
377 .podr = MCFGPIO_PODR_FECI2C, 377 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
378 .ppdr = MCFGPIO_PPDSDR_FECI2C, 378 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
379 .setr = MCFGPIO_PPDSDR_FECI2C, 379 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
380 .clrr = MCFGPIO_PCLRR_FECI2C, 380 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
381 }, 381 },
382 { 382 {
383 .gpio_chip = { 383 .gpio_chip = {
@@ -391,11 +391,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
391 .base = 56, 391 .base = 56,
392 .ngpio = 7, 392 .ngpio = 7,
393 }, 393 },
394 .pddr = MCFGPIO_PDDR_QSPI, 394 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
395 .podr = MCFGPIO_PODR_QSPI, 395 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
396 .ppdr = MCFGPIO_PPDSDR_QSPI, 396 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
397 .setr = MCFGPIO_PPDSDR_QSPI, 397 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
398 .clrr = MCFGPIO_PCLRR_QSPI, 398 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
399 }, 399 },
400 { 400 {
401 .gpio_chip = { 401 .gpio_chip = {
@@ -409,11 +409,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
409 .base = 64, 409 .base = 64,
410 .ngpio = 8, 410 .ngpio = 8,
411 }, 411 },
412 .pddr = MCFGPIO_PDDR_SDRAM, 412 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
413 .podr = MCFGPIO_PODR_SDRAM, 413 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
414 .ppdr = MCFGPIO_PPDSDR_SDRAM, 414 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
415 .setr = MCFGPIO_PPDSDR_SDRAM, 415 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
416 .clrr = MCFGPIO_PCLRR_SDRAM, 416 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
417 }, 417 },
418 { 418 {
419 .gpio_chip = { 419 .gpio_chip = {
@@ -427,11 +427,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
427 .base = 72, 427 .base = 72,
428 .ngpio = 4, 428 .ngpio = 4,
429 }, 429 },
430 .pddr = MCFGPIO_PDDR_TIMERH, 430 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH,
431 .podr = MCFGPIO_PODR_TIMERH, 431 .podr = (void __iomem *) MCFGPIO_PODR_TIMERH,
432 .ppdr = MCFGPIO_PPDSDR_TIMERH, 432 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
433 .setr = MCFGPIO_PPDSDR_TIMERH, 433 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
434 .clrr = MCFGPIO_PCLRR_TIMERH, 434 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
435 }, 435 },
436 { 436 {
437 .gpio_chip = { 437 .gpio_chip = {
@@ -445,11 +445,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
445 .base = 80, 445 .base = 80,
446 .ngpio = 4, 446 .ngpio = 4,
447 }, 447 },
448 .pddr = MCFGPIO_PDDR_TIMERL, 448 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL,
449 .podr = MCFGPIO_PODR_TIMERL, 449 .podr = (void __iomem *) MCFGPIO_PODR_TIMERL,
450 .ppdr = MCFGPIO_PPDSDR_TIMERL, 450 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
451 .setr = MCFGPIO_PPDSDR_TIMERL, 451 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
452 .clrr = MCFGPIO_PCLRR_TIMERL, 452 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
453 }, 453 },
454 { 454 {
455 .gpio_chip = { 455 .gpio_chip = {
@@ -463,11 +463,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
463 .base = 88, 463 .base = 88,
464 .ngpio = 8, 464 .ngpio = 8,
465 }, 465 },
466 .pddr = MCFGPIO_PDDR_UARTL, 466 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
467 .podr = MCFGPIO_PODR_UARTL, 467 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
468 .ppdr = MCFGPIO_PPDSDR_UARTL, 468 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
469 .setr = MCFGPIO_PPDSDR_UARTL, 469 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
470 .clrr = MCFGPIO_PCLRR_UARTL, 470 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
471 }, 471 },
472 { 472 {
473 .gpio_chip = { 473 .gpio_chip = {
@@ -481,11 +481,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
481 .base = 96, 481 .base = 96,
482 .ngpio = 8, 482 .ngpio = 8,
483 }, 483 },
484 .pddr = MCFGPIO_PDDR_FEC1H, 484 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H,
485 .podr = MCFGPIO_PODR_FEC1H, 485 .podr = (void __iomem *) MCFGPIO_PODR_FEC1H,
486 .ppdr = MCFGPIO_PPDSDR_FEC1H, 486 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
487 .setr = MCFGPIO_PPDSDR_FEC1H, 487 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
488 .clrr = MCFGPIO_PCLRR_FEC1H, 488 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
489 }, 489 },
490 { 490 {
491 .gpio_chip = { 491 .gpio_chip = {
@@ -499,11 +499,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
499 .base = 104, 499 .base = 104,
500 .ngpio = 8, 500 .ngpio = 8,
501 }, 501 },
502 .pddr = MCFGPIO_PDDR_FEC1L, 502 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L,
503 .podr = MCFGPIO_PODR_FEC1L, 503 .podr = (void __iomem *) MCFGPIO_PODR_FEC1L,
504 .ppdr = MCFGPIO_PPDSDR_FEC1L, 504 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
505 .setr = MCFGPIO_PPDSDR_FEC1L, 505 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
506 .clrr = MCFGPIO_PCLRR_FEC1L, 506 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
507 }, 507 },
508 { 508 {
509 .gpio_chip = { 509 .gpio_chip = {
@@ -517,11 +517,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
517 .base = 114, 517 .base = 114,
518 .ngpio = 2, 518 .ngpio = 2,
519 }, 519 },
520 .pddr = MCFGPIO_PDDR_BS, 520 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
521 .podr = MCFGPIO_PODR_BS, 521 .podr = (void __iomem *) MCFGPIO_PODR_BS,
522 .ppdr = MCFGPIO_PPDSDR_BS, 522 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
523 .setr = MCFGPIO_PPDSDR_BS, 523 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
524 .clrr = MCFGPIO_PCLRR_BS, 524 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
525 }, 525 },
526 { 526 {
527 .gpio_chip = { 527 .gpio_chip = {
@@ -535,11 +535,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
535 .base = 121, 535 .base = 121,
536 .ngpio = 7, 536 .ngpio = 7,
537 }, 537 },
538 .pddr = MCFGPIO_PDDR_IRQ, 538 .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ,
539 .podr = MCFGPIO_PODR_IRQ, 539 .podr = (void __iomem *) MCFGPIO_PODR_IRQ,
540 .ppdr = MCFGPIO_PPDSDR_IRQ, 540 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
541 .setr = MCFGPIO_PPDSDR_IRQ, 541 .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
542 .clrr = MCFGPIO_PCLRR_IRQ, 542 .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ,
543 }, 543 },
544 { 544 {
545 .gpio_chip = { 545 .gpio_chip = {
@@ -553,11 +553,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
553 .base = 128, 553 .base = 128,
554 .ngpio = 1, 554 .ngpio = 1,
555 }, 555 },
556 .pddr = MCFGPIO_PDDR_USBH, 556 .pddr = (void __iomem *) MCFGPIO_PDDR_USBH,
557 .podr = MCFGPIO_PODR_USBH, 557 .podr = (void __iomem *) MCFGPIO_PODR_USBH,
558 .ppdr = MCFGPIO_PPDSDR_USBH, 558 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
559 .setr = MCFGPIO_PPDSDR_USBH, 559 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
560 .clrr = MCFGPIO_PCLRR_USBH, 560 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH,
561 }, 561 },
562 { 562 {
563 .gpio_chip = { 563 .gpio_chip = {
@@ -571,11 +571,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
571 .base = 136, 571 .base = 136,
572 .ngpio = 8, 572 .ngpio = 8,
573 }, 573 },
574 .pddr = MCFGPIO_PDDR_USBL, 574 .pddr = (void __iomem *) MCFGPIO_PDDR_USBL,
575 .podr = MCFGPIO_PODR_USBL, 575 .podr = (void __iomem *) MCFGPIO_PODR_USBL,
576 .ppdr = MCFGPIO_PPDSDR_USBL, 576 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
577 .setr = MCFGPIO_PPDSDR_USBL, 577 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
578 .clrr = MCFGPIO_PCLRR_USBL, 578 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL,
579 }, 579 },
580 { 580 {
581 .gpio_chip = { 581 .gpio_chip = {
@@ -589,11 +589,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
589 .base = 144, 589 .base = 144,
590 .ngpio = 4, 590 .ngpio = 4,
591 }, 591 },
592 .pddr = MCFGPIO_PDDR_UARTH, 592 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
593 .podr = MCFGPIO_PODR_UARTH, 593 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
594 .ppdr = MCFGPIO_PPDSDR_UARTH, 594 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
595 .setr = MCFGPIO_PPDSDR_UARTH, 595 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
596 .clrr = MCFGPIO_PCLRR_UARTH, 596 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
597 }, 597 },
598#endif 598#endif
599}; 599};
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index 76b743343bfa..ac39fc661219 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -29,15 +29,15 @@
29 29
30static struct mcf_platform_uart m528x_uart_platform[] = { 30static struct mcf_platform_uart m528x_uart_platform[] = {
31 { 31 {
32 .mapbase = MCF_MBAR + MCFUART_BASE1, 32 .mapbase = MCFUART_BASE1,
33 .irq = MCFINT_VECBASE + MCFINT_UART0, 33 .irq = MCFINT_VECBASE + MCFINT_UART0,
34 }, 34 },
35 { 35 {
36 .mapbase = MCF_MBAR + MCFUART_BASE2, 36 .mapbase = MCFUART_BASE2,
37 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1, 37 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
38 }, 38 },
39 { 39 {
40 .mapbase = MCF_MBAR + MCFUART_BASE3, 40 .mapbase = MCFUART_BASE3,
41 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2, 41 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
42 }, 42 },
43 { }, 43 { },
@@ -51,8 +51,8 @@ static struct platform_device m528x_uart = {
51 51
52static struct resource m528x_fec_resources[] = { 52static struct resource m528x_fec_resources[] = {
53 { 53 {
54 .start = MCF_MBAR + 0x1000, 54 .start = MCFFEC_BASE,
55 .end = MCF_MBAR + 0x1000 + 0x7ff, 55 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
56 .flags = IORESOURCE_MEM, 56 .flags = IORESOURCE_MEM,
57 }, 57 },
58 { 58 {
@@ -227,9 +227,9 @@ static void __init m528x_uart_init_line(int line, int irq)
227 227
228 /* make sure PUAPAR is set for UART0 and UART1 */ 228 /* make sure PUAPAR is set for UART0 and UART1 */
229 if (line < 2) { 229 if (line < 2) {
230 port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR); 230 port = readb(MCF5282_GPIO_PUAPAR);
231 port |= (0x03 << (line * 2)); 231 port |= (0x03 << (line * 2));
232 writeb(port, MCF_MBAR + MCF5282_GPIO_PUAPAR); 232 writeb(port, MCF5282_GPIO_PUAPAR);
233 } 233 }
234} 234}
235 235
diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68knommu/platform/528x/gpio.c
index eedaf0adbcd7..526db665d87e 100644
--- a/arch/m68knommu/platform/528x/gpio.c
+++ b/arch/m68knommu/platform/528x/gpio.c
@@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
33 .base = 1, 33 .base = 1,
34 .ngpio = 7, 34 .ngpio = 7,
35 }, 35 },
36 .pddr = MCFEPORT_EPDDR, 36 .pddr = (void __iomem *)MCFEPORT_EPDDR,
37 .podr = MCFEPORT_EPDR, 37 .podr = (void __iomem *)MCFEPORT_EPDR,
38 .ppdr = MCFEPORT_EPPDR, 38 .ppdr = (void __iomem *)MCFEPORT_EPPDR,
39 }, 39 },
40 { 40 {
41 .gpio_chip = { 41 .gpio_chip = {
@@ -49,9 +49,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
49 .base = 8, 49 .base = 8,
50 .ngpio = 4, 50 .ngpio = 4,
51 }, 51 },
52 .pddr = MCFGPTA_GPTDDR, 52 .pddr = (void __iomem *)MCFGPTA_GPTDDR,
53 .podr = MCFGPTA_GPTPORT, 53 .podr = (void __iomem *)MCFGPTA_GPTPORT,
54 .ppdr = MCFGPTB_GPTPORT, 54 .ppdr = (void __iomem *)MCFGPTB_GPTPORT,
55 }, 55 },
56 { 56 {
57 .gpio_chip = { 57 .gpio_chip = {
@@ -65,9 +65,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
65 .base = 16, 65 .base = 16,
66 .ngpio = 4, 66 .ngpio = 4,
67 }, 67 },
68 .pddr = MCFGPTB_GPTDDR, 68 .pddr = (void __iomem *)MCFGPTB_GPTDDR,
69 .podr = MCFGPTB_GPTPORT, 69 .podr = (void __iomem *)MCFGPTB_GPTPORT,
70 .ppdr = MCFGPTB_GPTPORT, 70 .ppdr = (void __iomem *)MCFGPTB_GPTPORT,
71 }, 71 },
72 { 72 {
73 .gpio_chip = { 73 .gpio_chip = {
@@ -81,9 +81,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
81 .base = 24, 81 .base = 24,
82 .ngpio = 4, 82 .ngpio = 4,
83 }, 83 },
84 .pddr = MCFQADC_DDRQA, 84 .pddr = (void __iomem *)MCFQADC_DDRQA,
85 .podr = MCFQADC_PORTQA, 85 .podr = (void __iomem *)MCFQADC_PORTQA,
86 .ppdr = MCFQADC_PORTQA, 86 .ppdr = (void __iomem *)MCFQADC_PORTQA,
87 }, 87 },
88 { 88 {
89 .gpio_chip = { 89 .gpio_chip = {
@@ -97,9 +97,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
97 .base = 32, 97 .base = 32,
98 .ngpio = 4, 98 .ngpio = 4,
99 }, 99 },
100 .pddr = MCFQADC_DDRQB, 100 .pddr = (void __iomem *)MCFQADC_DDRQB,
101 .podr = MCFQADC_PORTQB, 101 .podr = (void __iomem *)MCFQADC_PORTQB,
102 .ppdr = MCFQADC_PORTQB, 102 .ppdr = (void __iomem *)MCFQADC_PORTQB,
103 }, 103 },
104 { 104 {
105 .gpio_chip = { 105 .gpio_chip = {
@@ -113,11 +113,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
113 .base = 40, 113 .base = 40,
114 .ngpio = 8, 114 .ngpio = 8,
115 }, 115 },
116 .pddr = MCFGPIO_DDRA, 116 .pddr = (void __iomem *)MCFGPIO_DDRA,
117 .podr = MCFGPIO_PORTA, 117 .podr = (void __iomem *)MCFGPIO_PORTA,
118 .ppdr = MCFGPIO_PORTAP, 118 .ppdr = (void __iomem *)MCFGPIO_PORTAP,
119 .setr = MCFGPIO_SETA, 119 .setr = (void __iomem *)MCFGPIO_SETA,
120 .clrr = MCFGPIO_CLRA, 120 .clrr = (void __iomem *)MCFGPIO_CLRA,
121 }, 121 },
122 { 122 {
123 .gpio_chip = { 123 .gpio_chip = {
@@ -131,11 +131,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
131 .base = 48, 131 .base = 48,
132 .ngpio = 8, 132 .ngpio = 8,
133 }, 133 },
134 .pddr = MCFGPIO_DDRB, 134 .pddr = (void __iomem *)MCFGPIO_DDRB,
135 .podr = MCFGPIO_PORTB, 135 .podr = (void __iomem *)MCFGPIO_PORTB,
136 .ppdr = MCFGPIO_PORTBP, 136 .ppdr = (void __iomem *)MCFGPIO_PORTBP,
137 .setr = MCFGPIO_SETB, 137 .setr = (void __iomem *)MCFGPIO_SETB,
138 .clrr = MCFGPIO_CLRB, 138 .clrr = (void __iomem *)MCFGPIO_CLRB,
139 }, 139 },
140 { 140 {
141 .gpio_chip = { 141 .gpio_chip = {
@@ -149,11 +149,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
149 .base = 56, 149 .base = 56,
150 .ngpio = 8, 150 .ngpio = 8,
151 }, 151 },
152 .pddr = MCFGPIO_DDRC, 152 .pddr = (void __iomem *)MCFGPIO_DDRC,
153 .podr = MCFGPIO_PORTC, 153 .podr = (void __iomem *)MCFGPIO_PORTC,
154 .ppdr = MCFGPIO_PORTCP, 154 .ppdr = (void __iomem *)MCFGPIO_PORTCP,
155 .setr = MCFGPIO_SETC, 155 .setr = (void __iomem *)MCFGPIO_SETC,
156 .clrr = MCFGPIO_CLRC, 156 .clrr = (void __iomem *)MCFGPIO_CLRC,
157 }, 157 },
158 { 158 {
159 .gpio_chip = { 159 .gpio_chip = {
@@ -167,11 +167,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
167 .base = 64, 167 .base = 64,
168 .ngpio = 8, 168 .ngpio = 8,
169 }, 169 },
170 .pddr = MCFGPIO_DDRD, 170 .pddr = (void __iomem *)MCFGPIO_DDRD,
171 .podr = MCFGPIO_PORTD, 171 .podr = (void __iomem *)MCFGPIO_PORTD,
172 .ppdr = MCFGPIO_PORTDP, 172 .ppdr = (void __iomem *)MCFGPIO_PORTDP,
173 .setr = MCFGPIO_SETD, 173 .setr = (void __iomem *)MCFGPIO_SETD,
174 .clrr = MCFGPIO_CLRD, 174 .clrr = (void __iomem *)MCFGPIO_CLRD,
175 }, 175 },
176 { 176 {
177 .gpio_chip = { 177 .gpio_chip = {
@@ -185,11 +185,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
185 .base = 72, 185 .base = 72,
186 .ngpio = 8, 186 .ngpio = 8,
187 }, 187 },
188 .pddr = MCFGPIO_DDRE, 188 .pddr = (void __iomem *)MCFGPIO_DDRE,
189 .podr = MCFGPIO_PORTE, 189 .podr = (void __iomem *)MCFGPIO_PORTE,
190 .ppdr = MCFGPIO_PORTEP, 190 .ppdr = (void __iomem *)MCFGPIO_PORTEP,
191 .setr = MCFGPIO_SETE, 191 .setr = (void __iomem *)MCFGPIO_SETE,
192 .clrr = MCFGPIO_CLRE, 192 .clrr = (void __iomem *)MCFGPIO_CLRE,
193 }, 193 },
194 { 194 {
195 .gpio_chip = { 195 .gpio_chip = {
@@ -203,11 +203,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
203 .base = 80, 203 .base = 80,
204 .ngpio = 8, 204 .ngpio = 8,
205 }, 205 },
206 .pddr = MCFGPIO_DDRF, 206 .pddr = (void __iomem *)MCFGPIO_DDRF,
207 .podr = MCFGPIO_PORTF, 207 .podr = (void __iomem *)MCFGPIO_PORTF,
208 .ppdr = MCFGPIO_PORTFP, 208 .ppdr = (void __iomem *)MCFGPIO_PORTFP,
209 .setr = MCFGPIO_SETF, 209 .setr = (void __iomem *)MCFGPIO_SETF,
210 .clrr = MCFGPIO_CLRF, 210 .clrr = (void __iomem *)MCFGPIO_CLRF,
211 }, 211 },
212 { 212 {
213 .gpio_chip = { 213 .gpio_chip = {
@@ -221,11 +221,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
221 .base = 88, 221 .base = 88,
222 .ngpio = 8, 222 .ngpio = 8,
223 }, 223 },
224 .pddr = MCFGPIO_DDRG, 224 .pddr = (void __iomem *)MCFGPIO_DDRG,
225 .podr = MCFGPIO_PORTG, 225 .podr = (void __iomem *)MCFGPIO_PORTG,
226 .ppdr = MCFGPIO_PORTGP, 226 .ppdr = (void __iomem *)MCFGPIO_PORTGP,
227 .setr = MCFGPIO_SETG, 227 .setr = (void __iomem *)MCFGPIO_SETG,
228 .clrr = MCFGPIO_CLRG, 228 .clrr = (void __iomem *)MCFGPIO_CLRG,
229 }, 229 },
230 { 230 {
231 .gpio_chip = { 231 .gpio_chip = {
@@ -239,11 +239,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
239 .base = 96, 239 .base = 96,
240 .ngpio = 8, 240 .ngpio = 8,
241 }, 241 },
242 .pddr = MCFGPIO_DDRH, 242 .pddr = (void __iomem *)MCFGPIO_DDRH,
243 .podr = MCFGPIO_PORTH, 243 .podr = (void __iomem *)MCFGPIO_PORTH,
244 .ppdr = MCFGPIO_PORTHP, 244 .ppdr = (void __iomem *)MCFGPIO_PORTHP,
245 .setr = MCFGPIO_SETH, 245 .setr = (void __iomem *)MCFGPIO_SETH,
246 .clrr = MCFGPIO_CLRH, 246 .clrr = (void __iomem *)MCFGPIO_CLRH,
247 }, 247 },
248 { 248 {
249 .gpio_chip = { 249 .gpio_chip = {
@@ -257,11 +257,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
257 .base = 104, 257 .base = 104,
258 .ngpio = 8, 258 .ngpio = 8,
259 }, 259 },
260 .pddr = MCFGPIO_DDRJ, 260 .pddr = (void __iomem *)MCFGPIO_DDRJ,
261 .podr = MCFGPIO_PORTJ, 261 .podr = (void __iomem *)MCFGPIO_PORTJ,
262 .ppdr = MCFGPIO_PORTJP, 262 .ppdr = (void __iomem *)MCFGPIO_PORTJP,
263 .setr = MCFGPIO_SETJ, 263 .setr = (void __iomem *)MCFGPIO_SETJ,
264 .clrr = MCFGPIO_CLRJ, 264 .clrr = (void __iomem *)MCFGPIO_CLRJ,
265 }, 265 },
266 { 266 {
267 .gpio_chip = { 267 .gpio_chip = {
@@ -275,11 +275,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
275 .base = 112, 275 .base = 112,
276 .ngpio = 8, 276 .ngpio = 8,
277 }, 277 },
278 .pddr = MCFGPIO_DDRDD, 278 .pddr = (void __iomem *)MCFGPIO_DDRDD,
279 .podr = MCFGPIO_PORTDD, 279 .podr = (void __iomem *)MCFGPIO_PORTDD,
280 .ppdr = MCFGPIO_PORTDDP, 280 .ppdr = (void __iomem *)MCFGPIO_PORTDDP,
281 .setr = MCFGPIO_SETDD, 281 .setr = (void __iomem *)MCFGPIO_SETDD,
282 .clrr = MCFGPIO_CLRDD, 282 .clrr = (void __iomem *)MCFGPIO_CLRDD,
283 }, 283 },
284 { 284 {
285 .gpio_chip = { 285 .gpio_chip = {
@@ -293,11 +293,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
293 .base = 120, 293 .base = 120,
294 .ngpio = 8, 294 .ngpio = 8,
295 }, 295 },
296 .pddr = MCFGPIO_DDREH, 296 .pddr = (void __iomem *)MCFGPIO_DDREH,
297 .podr = MCFGPIO_PORTEH, 297 .podr = (void __iomem *)MCFGPIO_PORTEH,
298 .ppdr = MCFGPIO_PORTEHP, 298 .ppdr = (void __iomem *)MCFGPIO_PORTEHP,
299 .setr = MCFGPIO_SETEH, 299 .setr = (void __iomem *)MCFGPIO_SETEH,
300 .clrr = MCFGPIO_CLREH, 300 .clrr = (void __iomem *)MCFGPIO_CLREH,
301 }, 301 },
302 { 302 {
303 .gpio_chip = { 303 .gpio_chip = {
@@ -311,11 +311,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
311 .base = 128, 311 .base = 128,
312 .ngpio = 8, 312 .ngpio = 8,
313 }, 313 },
314 .pddr = MCFGPIO_DDREL, 314 .pddr = (void __iomem *)MCFGPIO_DDREL,
315 .podr = MCFGPIO_PORTEL, 315 .podr = (void __iomem *)MCFGPIO_PORTEL,
316 .ppdr = MCFGPIO_PORTELP, 316 .ppdr = (void __iomem *)MCFGPIO_PORTELP,
317 .setr = MCFGPIO_SETEL, 317 .setr = (void __iomem *)MCFGPIO_SETEL,
318 .clrr = MCFGPIO_CLREL, 318 .clrr = (void __iomem *)MCFGPIO_CLREL,
319 }, 319 },
320 { 320 {
321 .gpio_chip = { 321 .gpio_chip = {
@@ -329,11 +329,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
329 .base = 136, 329 .base = 136,
330 .ngpio = 6, 330 .ngpio = 6,
331 }, 331 },
332 .pddr = MCFGPIO_DDRAS, 332 .pddr = (void __iomem *)MCFGPIO_DDRAS,
333 .podr = MCFGPIO_PORTAS, 333 .podr = (void __iomem *)MCFGPIO_PORTAS,
334 .ppdr = MCFGPIO_PORTASP, 334 .ppdr = (void __iomem *)MCFGPIO_PORTASP,
335 .setr = MCFGPIO_SETAS, 335 .setr = (void __iomem *)MCFGPIO_SETAS,
336 .clrr = MCFGPIO_CLRAS, 336 .clrr = (void __iomem *)MCFGPIO_CLRAS,
337 }, 337 },
338 { 338 {
339 .gpio_chip = { 339 .gpio_chip = {
@@ -347,11 +347,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
347 .base = 144, 347 .base = 144,
348 .ngpio = 7, 348 .ngpio = 7,
349 }, 349 },
350 .pddr = MCFGPIO_DDRQS, 350 .pddr = (void __iomem *)MCFGPIO_DDRQS,
351 .podr = MCFGPIO_PORTQS, 351 .podr = (void __iomem *)MCFGPIO_PORTQS,
352 .ppdr = MCFGPIO_PORTQSP, 352 .ppdr = (void __iomem *)MCFGPIO_PORTQSP,
353 .setr = MCFGPIO_SETQS, 353 .setr = (void __iomem *)MCFGPIO_SETQS,
354 .clrr = MCFGPIO_CLRQS, 354 .clrr = (void __iomem *)MCFGPIO_CLRQS,
355 }, 355 },
356 { 356 {
357 .gpio_chip = { 357 .gpio_chip = {
@@ -365,11 +365,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
365 .base = 152, 365 .base = 152,
366 .ngpio = 6, 366 .ngpio = 6,
367 }, 367 },
368 .pddr = MCFGPIO_DDRSD, 368 .pddr = (void __iomem *)MCFGPIO_DDRSD,
369 .podr = MCFGPIO_PORTSD, 369 .podr = (void __iomem *)MCFGPIO_PORTSD,
370 .ppdr = MCFGPIO_PORTSDP, 370 .ppdr = (void __iomem *)MCFGPIO_PORTSDP,
371 .setr = MCFGPIO_SETSD, 371 .setr = (void __iomem *)MCFGPIO_SETSD,
372 .clrr = MCFGPIO_CLRSD, 372 .clrr = (void __iomem *)MCFGPIO_CLRSD,
373 }, 373 },
374 { 374 {
375 .gpio_chip = { 375 .gpio_chip = {
@@ -383,11 +383,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
383 .base = 160, 383 .base = 160,
384 .ngpio = 4, 384 .ngpio = 4,
385 }, 385 },
386 .pddr = MCFGPIO_DDRTC, 386 .pddr = (void __iomem *)MCFGPIO_DDRTC,
387 .podr = MCFGPIO_PORTTC, 387 .podr = (void __iomem *)MCFGPIO_PORTTC,
388 .ppdr = MCFGPIO_PORTTCP, 388 .ppdr = (void __iomem *)MCFGPIO_PORTTCP,
389 .setr = MCFGPIO_SETTC, 389 .setr = (void __iomem *)MCFGPIO_SETTC,
390 .clrr = MCFGPIO_CLRTC, 390 .clrr = (void __iomem *)MCFGPIO_CLRTC,
391 }, 391 },
392 { 392 {
393 .gpio_chip = { 393 .gpio_chip = {
@@ -401,11 +401,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
401 .base = 168, 401 .base = 168,
402 .ngpio = 4, 402 .ngpio = 4,
403 }, 403 },
404 .pddr = MCFGPIO_DDRTD, 404 .pddr = (void __iomem *)MCFGPIO_DDRTD,
405 .podr = MCFGPIO_PORTTD, 405 .podr = (void __iomem *)MCFGPIO_PORTTD,
406 .ppdr = MCFGPIO_PORTTDP, 406 .ppdr = (void __iomem *)MCFGPIO_PORTTDP,
407 .setr = MCFGPIO_SETTD, 407 .setr = (void __iomem *)MCFGPIO_SETTD,
408 .clrr = MCFGPIO_CLRTD, 408 .clrr = (void __iomem *)MCFGPIO_CLRTD,
409 }, 409 },
410 { 410 {
411 .gpio_chip = { 411 .gpio_chip = {
@@ -419,11 +419,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
419 .base = 176, 419 .base = 176,
420 .ngpio = 4, 420 .ngpio = 4,
421 }, 421 },
422 .pddr = MCFGPIO_DDRUA, 422 .pddr = (void __iomem *)MCFGPIO_DDRUA,
423 .podr = MCFGPIO_PORTUA, 423 .podr = (void __iomem *)MCFGPIO_PORTUA,
424 .ppdr = MCFGPIO_PORTUAP, 424 .ppdr = (void __iomem *)MCFGPIO_PORTUAP,
425 .setr = MCFGPIO_SETUA, 425 .setr = (void __iomem *)MCFGPIO_SETUA,
426 .clrr = MCFGPIO_CLRUA, 426 .clrr = (void __iomem *)MCFGPIO_CLRUA,
427 }, 427 },
428}; 428};
429 429
diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68knommu/platform/5307/gpio.c
index 8da5880e4066..5850612b4a38 100644
--- a/arch/m68knommu/platform/5307/gpio.c
+++ b/arch/m68knommu/platform/5307/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 16, 33 .ngpio = 16,
34 }, 34 },
35 .pddr = MCFSIM_PADDR, 35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT, 36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT, 37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 }, 38 },
39}; 39};
40 40
diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68knommu/platform/532x/gpio.c
index 184b77382c3d..212a85deac90 100644
--- a/arch/m68knommu/platform/532x/gpio.c
+++ b/arch/m68knommu/platform/532x/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 8, 33 .ngpio = 8,
34 }, 34 },
35 .pddr = MCFEPORT_EPDDR, 35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR, 36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR, 37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 }, 38 },
39 { 39 {
40 .gpio_chip = { 40 .gpio_chip = {
@@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
48 .base = 8, 48 .base = 8,
49 .ngpio = 8, 49 .ngpio = 8,
50 }, 50 },
51 .pddr = MCFGPIO_PDDR_FECH, 51 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
52 .podr = MCFGPIO_PODR_FECH, 52 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
53 .ppdr = MCFGPIO_PPDSDR_FECH, 53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
54 .setr = MCFGPIO_PPDSDR_FECH, 54 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
55 .clrr = MCFGPIO_PCLRR_FECH, 55 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
56 }, 56 },
57 { 57 {
58 .gpio_chip = { 58 .gpio_chip = {
@@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
66 .base = 16, 66 .base = 16,
67 .ngpio = 8, 67 .ngpio = 8,
68 }, 68 },
69 .pddr = MCFGPIO_PDDR_FECL, 69 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
70 .podr = MCFGPIO_PODR_FECL, 70 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
71 .ppdr = MCFGPIO_PPDSDR_FECL, 71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
72 .setr = MCFGPIO_PPDSDR_FECL, 72 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
73 .clrr = MCFGPIO_PCLRR_FECL, 73 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
74 }, 74 },
75 { 75 {
76 .gpio_chip = { 76 .gpio_chip = {
@@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
84 .base = 24, 84 .base = 24,
85 .ngpio = 5, 85 .ngpio = 5,
86 }, 86 },
87 .pddr = MCFGPIO_PDDR_SSI, 87 .pddr = (void __iomem *) MCFGPIO_PDDR_SSI,
88 .podr = MCFGPIO_PODR_SSI, 88 .podr = (void __iomem *) MCFGPIO_PODR_SSI,
89 .ppdr = MCFGPIO_PPDSDR_SSI, 89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
90 .setr = MCFGPIO_PPDSDR_SSI, 90 .setr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
91 .clrr = MCFGPIO_PCLRR_SSI, 91 .clrr = (void __iomem *) MCFGPIO_PCLRR_SSI,
92 }, 92 },
93 { 93 {
94 .gpio_chip = { 94 .gpio_chip = {
@@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
102 .base = 32, 102 .base = 32,
103 .ngpio = 4, 103 .ngpio = 4,
104 }, 104 },
105 .pddr = MCFGPIO_PDDR_BUSCTL, 105 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
106 .podr = MCFGPIO_PODR_BUSCTL, 106 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
107 .ppdr = MCFGPIO_PPDSDR_BUSCTL, 107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
108 .setr = MCFGPIO_PPDSDR_BUSCTL, 108 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = MCFGPIO_PCLRR_BUSCTL, 109 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
110 }, 110 },
111 { 111 {
112 .gpio_chip = { 112 .gpio_chip = {
@@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
120 .base = 40, 120 .base = 40,
121 .ngpio = 4, 121 .ngpio = 4,
122 }, 122 },
123 .pddr = MCFGPIO_PDDR_BE, 123 .pddr = (void __iomem *) MCFGPIO_PDDR_BE,
124 .podr = MCFGPIO_PODR_BE, 124 .podr = (void __iomem *) MCFGPIO_PODR_BE,
125 .ppdr = MCFGPIO_PPDSDR_BE, 125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
126 .setr = MCFGPIO_PPDSDR_BE, 126 .setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
127 .clrr = MCFGPIO_PCLRR_BE, 127 .clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
128 }, 128 },
129 { 129 {
130 .gpio_chip = { 130 .gpio_chip = {
@@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
138 .base = 49, 138 .base = 49,
139 .ngpio = 5, 139 .ngpio = 5,
140 }, 140 },
141 .pddr = MCFGPIO_PDDR_CS, 141 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
142 .podr = MCFGPIO_PODR_CS, 142 .podr = (void __iomem *) MCFGPIO_PODR_CS,
143 .ppdr = MCFGPIO_PPDSDR_CS, 143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
144 .setr = MCFGPIO_PPDSDR_CS, 144 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
145 .clrr = MCFGPIO_PCLRR_CS, 145 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
146 }, 146 },
147 { 147 {
148 .gpio_chip = { 148 .gpio_chip = {
@@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
156 .base = 58, 156 .base = 58,
157 .ngpio = 4, 157 .ngpio = 4,
158 }, 158 },
159 .pddr = MCFGPIO_PDDR_PWM, 159 .pddr = (void __iomem *) MCFGPIO_PDDR_PWM,
160 .podr = MCFGPIO_PODR_PWM, 160 .podr = (void __iomem *) MCFGPIO_PODR_PWM,
161 .ppdr = MCFGPIO_PPDSDR_PWM, 161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
162 .setr = MCFGPIO_PPDSDR_PWM, 162 .setr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
163 .clrr = MCFGPIO_PCLRR_PWM, 163 .clrr = (void __iomem *) MCFGPIO_PCLRR_PWM,
164 }, 164 },
165 { 165 {
166 .gpio_chip = { 166 .gpio_chip = {
@@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
174 .base = 64, 174 .base = 64,
175 .ngpio = 4, 175 .ngpio = 4,
176 }, 176 },
177 .pddr = MCFGPIO_PDDR_FECI2C, 177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
178 .podr = MCFGPIO_PODR_FECI2C, 178 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
179 .ppdr = MCFGPIO_PPDSDR_FECI2C, 179 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
180 .setr = MCFGPIO_PPDSDR_FECI2C, 180 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
181 .clrr = MCFGPIO_PCLRR_FECI2C, 181 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
182 }, 182 },
183 { 183 {
184 .gpio_chip = { 184 .gpio_chip = {
@@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
192 .base = 72, 192 .base = 72,
193 .ngpio = 8, 193 .ngpio = 8,
194 }, 194 },
195 .pddr = MCFGPIO_PDDR_UART, 195 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
196 .podr = MCFGPIO_PODR_UART, 196 .podr = (void __iomem *) MCFGPIO_PODR_UART,
197 .ppdr = MCFGPIO_PPDSDR_UART, 197 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
198 .setr = MCFGPIO_PPDSDR_UART, 198 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
199 .clrr = MCFGPIO_PCLRR_UART, 199 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
200 }, 200 },
201 { 201 {
202 .gpio_chip = { 202 .gpio_chip = {
@@ -210,11 +210,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
210 .base = 80, 210 .base = 80,
211 .ngpio = 6, 211 .ngpio = 6,
212 }, 212 },
213 .pddr = MCFGPIO_PDDR_QSPI, 213 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
214 .podr = MCFGPIO_PODR_QSPI, 214 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
215 .ppdr = MCFGPIO_PPDSDR_QSPI, 215 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
216 .setr = MCFGPIO_PPDSDR_QSPI, 216 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
217 .clrr = MCFGPIO_PCLRR_QSPI, 217 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
218 }, 218 },
219 { 219 {
220 .gpio_chip = { 220 .gpio_chip = {
@@ -228,11 +228,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
228 .base = 88, 228 .base = 88,
229 .ngpio = 4, 229 .ngpio = 4,
230 }, 230 },
231 .pddr = MCFGPIO_PDDR_TIMER, 231 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
232 .podr = MCFGPIO_PODR_TIMER, 232 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
233 .ppdr = MCFGPIO_PPDSDR_TIMER, 233 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
234 .setr = MCFGPIO_PPDSDR_TIMER, 234 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
235 .clrr = MCFGPIO_PCLRR_TIMER, 235 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
236 }, 236 },
237 { 237 {
238 .gpio_chip = { 238 .gpio_chip = {
@@ -246,11 +246,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
246 .base = 96, 246 .base = 96,
247 .ngpio = 2, 247 .ngpio = 2,
248 }, 248 },
249 .pddr = MCFGPIO_PDDR_LCDDATAH, 249 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
250 .podr = MCFGPIO_PODR_LCDDATAH, 250 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH,
251 .ppdr = MCFGPIO_PPDSDR_LCDDATAH, 251 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
252 .setr = MCFGPIO_PPDSDR_LCDDATAH, 252 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
253 .clrr = MCFGPIO_PCLRR_LCDDATAH, 253 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
254 }, 254 },
255 { 255 {
256 .gpio_chip = { 256 .gpio_chip = {
@@ -264,11 +264,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
264 .base = 104, 264 .base = 104,
265 .ngpio = 8, 265 .ngpio = 8,
266 }, 266 },
267 .pddr = MCFGPIO_PDDR_LCDDATAM, 267 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
268 .podr = MCFGPIO_PODR_LCDDATAM, 268 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM,
269 .ppdr = MCFGPIO_PPDSDR_LCDDATAM, 269 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
270 .setr = MCFGPIO_PPDSDR_LCDDATAM, 270 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
271 .clrr = MCFGPIO_PCLRR_LCDDATAM, 271 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
272 }, 272 },
273 { 273 {
274 .gpio_chip = { 274 .gpio_chip = {
@@ -282,11 +282,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
282 .base = 112, 282 .base = 112,
283 .ngpio = 8, 283 .ngpio = 8,
284 }, 284 },
285 .pddr = MCFGPIO_PDDR_LCDDATAL, 285 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
286 .podr = MCFGPIO_PODR_LCDDATAL, 286 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL,
287 .ppdr = MCFGPIO_PPDSDR_LCDDATAL, 287 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
288 .setr = MCFGPIO_PPDSDR_LCDDATAL, 288 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
289 .clrr = MCFGPIO_PCLRR_LCDDATAL, 289 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
290 }, 290 },
291 { 291 {
292 .gpio_chip = { 292 .gpio_chip = {
@@ -300,11 +300,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
300 .base = 120, 300 .base = 120,
301 .ngpio = 1, 301 .ngpio = 1,
302 }, 302 },
303 .pddr = MCFGPIO_PDDR_LCDCTLH, 303 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
304 .podr = MCFGPIO_PODR_LCDCTLH, 304 .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH,
305 .ppdr = MCFGPIO_PPDSDR_LCDCTLH, 305 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
306 .setr = MCFGPIO_PPDSDR_LCDCTLH, 306 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
307 .clrr = MCFGPIO_PCLRR_LCDCTLH, 307 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
308 }, 308 },
309 { 309 {
310 .gpio_chip = { 310 .gpio_chip = {
@@ -318,11 +318,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
318 .base = 128, 318 .base = 128,
319 .ngpio = 8, 319 .ngpio = 8,
320 }, 320 },
321 .pddr = MCFGPIO_PDDR_LCDCTLL, 321 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
322 .podr = MCFGPIO_PODR_LCDCTLL, 322 .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL,
323 .ppdr = MCFGPIO_PPDSDR_LCDCTLL, 323 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
324 .setr = MCFGPIO_PPDSDR_LCDCTLL, 324 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
325 .clrr = MCFGPIO_PCLRR_LCDCTLL, 325 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
326 }, 326 },
327}; 327};
328 328
diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68knommu/platform/5407/gpio.c
index 8da5880e4066..5850612b4a38 100644
--- a/arch/m68knommu/platform/5407/gpio.c
+++ b/arch/m68knommu/platform/5407/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
32 .set = mcf_gpio_set_value, 32 .set = mcf_gpio_set_value,
33 .ngpio = 16, 33 .ngpio = 16,
34 }, 34 },
35 .pddr = MCFSIM_PADDR, 35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT, 36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT, 37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 }, 38 },
39}; 39};
40 40
diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68knommu/platform/54xx/Makefile
index e6035e7a2d3f..6cfd090ec3cd 100644
--- a/arch/m68knommu/platform/54xx/Makefile
+++ b/arch/m68knommu/platform/54xx/Makefile
@@ -15,4 +15,5 @@
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o
18obj-$(CONFIG_FIREBEE) += firebee.o
18 19
diff --git a/arch/m68knommu/platform/54xx/firebee.c b/arch/m68knommu/platform/54xx/firebee.c
new file mode 100644
index 000000000000..46d50534f981
--- /dev/null
+++ b/arch/m68knommu/platform/54xx/firebee.c
@@ -0,0 +1,86 @@
1/***************************************************************************/
2
3/*
4 * firebee.c -- extra startup code support for the FireBee boards
5 *
6 * Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h>
17#include <linux/mtd/physmap.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21/***************************************************************************/
22
23/*
24 * 8MB of NOR flash fitted to the FireBee board.
25 */
26#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */
27#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */
28
29#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */
30#define PART_BOOT_SIZE 0x00040000 /* 256k in size */
31#define PART_IMAGE_START 0x00040000 /* Start after boot loader */
32#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */
33#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */
34#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */
35
36static struct mtd_partition firebee_flash_parts[] = {
37 {
38 .name = "dBUG",
39 .offset = PART_BOOT_START,
40 .size = PART_BOOT_SIZE,
41 },
42 {
43 .name = "FPGA",
44 .offset = PART_FPGA_START,
45 .size = PART_FPGA_SIZE,
46 },
47 {
48 .name = "image",
49 .offset = PART_IMAGE_START,
50 .size = PART_IMAGE_SIZE,
51 },
52};
53
54static struct physmap_flash_data firebee_flash_data = {
55 .width = 2,
56 .nr_parts = ARRAY_SIZE(firebee_flash_parts),
57 .parts = firebee_flash_parts,
58};
59
60static struct resource firebee_flash_resource = {
61 .start = FLASH_PHYS_ADDR,
62 .end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
63 .flags = IORESOURCE_MEM,
64};
65
66static struct platform_device firebee_flash = {
67 .name = "physmap-flash",
68 .id = 0,
69 .dev = {
70 .platform_data = &firebee_flash_data,
71 },
72 .num_resources = 1,
73 .resource = &firebee_flash_resource,
74};
75
76/***************************************************************************/
77
78static int __init init_firebee(void)
79{
80 platform_device_register(&firebee_flash);
81 return 0;
82}
83
84arch_initcall(init_firebee);
85
86/***************************************************************************/
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index 2a3af193ccd3..e5631831a200 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -135,20 +135,20 @@ void process_int(int vec, struct pt_regs *fp)
135 } 135 }
136} 136}
137 137
138static void intc_irq_unmask(unsigned int irq) 138static void intc_irq_unmask(struct irq_data *d)
139{ 139{
140 IMR &= ~(1<<irq); 140 IMR &= ~(1 << d->irq);
141} 141}
142 142
143static void intc_irq_mask(unsigned int irq) 143static void intc_irq_mask(struct irq_data *d)
144{ 144{
145 IMR |= (1<<irq); 145 IMR |= (1 << d->irq);
146} 146}
147 147
148static struct irq_chip intc_irq_chip = { 148static struct irq_chip intc_irq_chip = {
149 .name = "M68K-INTC", 149 .name = "M68K-INTC",
150 .mask = intc_irq_mask, 150 .irq_mask = intc_irq_mask,
151 .unmask = intc_irq_unmask, 151 .irq_unmask = intc_irq_unmask,
152}; 152};
153 153
154/* 154/*
diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c
index a29041c1a8a0..8de3feb568c6 100644
--- a/arch/m68knommu/platform/68360/ints.c
+++ b/arch/m68knommu/platform/68360/ints.c
@@ -37,26 +37,26 @@ extern void *_ramvec[];
37/* The number of spurious interrupts */ 37/* The number of spurious interrupts */
38volatile unsigned int num_spurious; 38volatile unsigned int num_spurious;
39 39
40static void intc_irq_unmask(unsigned int irq) 40static void intc_irq_unmask(struct irq_data *d)
41{ 41{
42 pquicc->intr_cimr |= (1 << irq); 42 pquicc->intr_cimr |= (1 << d->irq);
43} 43}
44 44
45static void intc_irq_mask(unsigned int irq) 45static void intc_irq_mask(struct irq_data *d)
46{ 46{
47 pquicc->intr_cimr &= ~(1 << irq); 47 pquicc->intr_cimr &= ~(1 << d->irq);
48} 48}
49 49
50static void intc_irq_ack(unsigned int irq) 50static void intc_irq_ack(struct irq_data *d)
51{ 51{
52 pquicc->intr_cisr = (1 << irq); 52 pquicc->intr_cisr = (1 << d->irq);
53} 53}
54 54
55static struct irq_chip intc_irq_chip = { 55static struct irq_chip intc_irq_chip = {
56 .name = "M68K-INTC", 56 .name = "M68K-INTC",
57 .mask = intc_irq_mask, 57 .irq_mask = intc_irq_mask,
58 .unmask = intc_irq_unmask, 58 .irq_unmask = intc_irq_unmask,
59 .ack = intc_irq_ack, 59 .irq_ack = intc_irq_ack,
60}; 60};
61 61
62/* 62/*
diff --git a/arch/m68knommu/platform/coldfire/dma.c b/arch/m68knommu/platform/coldfire/dma.c
index 2b30cf1b8f77..e88b95e2cc62 100644
--- a/arch/m68knommu/platform/coldfire/dma.c
+++ b/arch/m68knommu/platform/coldfire/dma.c
@@ -21,16 +21,16 @@
21 */ 21 */
22unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = { 22unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
23#ifdef MCFDMA_BASE0 23#ifdef MCFDMA_BASE0
24 MCF_MBAR + MCFDMA_BASE0, 24 MCFDMA_BASE0,
25#endif 25#endif
26#ifdef MCFDMA_BASE1 26#ifdef MCFDMA_BASE1
27 MCF_MBAR + MCFDMA_BASE1, 27 MCFDMA_BASE1,
28#endif 28#endif
29#ifdef MCFDMA_BASE2 29#ifdef MCFDMA_BASE2
30 MCF_MBAR + MCFDMA_BASE2, 30 MCFDMA_BASE2,
31#endif 31#endif
32#ifdef MCFDMA_BASE3 32#ifdef MCFDMA_BASE3
33 MCF_MBAR + MCFDMA_BASE3, 33 MCFDMA_BASE3,
34#endif 34#endif
35}; 35};
36 36
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index d5977909ae5f..129bff4956b5 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -41,17 +41,17 @@
41 * DRAM controller is quite different. 41 * DRAM controller is quite different.
42 */ 42 */
43.macro GET_MEM_SIZE 43.macro GET_MEM_SIZE
44 movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */ 44 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
45 btst #0,%d0 /* check if region enabled */ 45 btst #0,%d0 /* check if region enabled */
46 beq 1f 46 beq 1f
47 andl #0xfffc0000,%d0 47 andl #0xfffc0000,%d0
48 beq 1f 48 beq 1f
49 addl #0x00040000,%d0 /* convert mask to size */ 49 addl #0x00040000,%d0 /* convert mask to size */
501: 501:
51 movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ 51 movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
52 btst #0,%d1 /* check if region enabled */ 52 btst #0,%d1 /* check if region enabled */
53 beq 2f 53 beq 2f
54 andl #0xfffc0000, %d1 54 andl #0xfffc0000,%d1
55 beq 2f 55 beq 2f
56 addl #0x00040000,%d1 56 addl #0x00040000,%d1
57 addl %d1,%d0 /* total mem size in d0 */ 57 addl %d1,%d0 /* total mem size in d0 */
@@ -68,14 +68,14 @@
68#elif defined(CONFIG_M520x) 68#elif defined(CONFIG_M520x)
69.macro GET_MEM_SIZE 69.macro GET_MEM_SIZE
70 clrl %d0 70 clrl %d0
71 movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ 71 movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
72 andl #0x1f, %d2 /* Get only the chip select size */ 72 andl #0x1f, %d2 /* Get only the chip select size */
73 beq 3f /* Check if it is enabled */ 73 beq 3f /* Check if it is enabled */
74 addql #1, %d2 /* Form exponent */ 74 addql #1, %d2 /* Form exponent */
75 moveql #1, %d0 75 moveql #1, %d0
76 lsll %d2, %d0 /* 2 ^ exponent */ 76 lsll %d2, %d0 /* 2 ^ exponent */
773: 773:
78 movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ 78 movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
79 andl #0x1f, %d2 /* Get only the chip select size */ 79 andl #0x1f, %d2 /* Get only the chip select size */
80 beq 4f /* Check if it is enabled */ 80 beq 4f /* Check if it is enabled */
81 addql #1, %d2 /* Form exponent */ 81 addql #1, %d2 /* Form exponent */
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 85daa2b3001a..2cbfbf035db9 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -7,7 +7,10 @@
7 * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such 7 * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
8 * controllers, and the 547x and 548x families which have only one of them. 8 * controllers, and the 547x and 548x families which have only one of them.
9 * 9 *
10 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 10 * The external 7 fixed interrupts are part the the Edge Port unit of these
11 * ColdFire parts. They can be configured as level or edge triggered.
12 *
13 * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
11 * 14 *
12 * This file is subject to the terms and conditions of the GNU General Public 15 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive 16 * License. See the file COPYING in the main directory of this archive
@@ -31,11 +34,12 @@
31#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ 34#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
32 35
33/* 36/*
34 * Each vector needs a unique priority and level associated with it. 37 * The EDGE Port interrupts are the fixed 7 external interrupts.
35 * We don't really care so much what they are, we don't rely on the 38 * They need some special treatment, for example they need to be acked.
36 * traditional priority interrupt scheme of the m68k/ColdFire.
37 */ 39 */
38static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); 40#define EINT0 64 /* Is not actually used, but spot reserved for it */
41#define EINT1 65 /* EDGE Port interrupt 1 */
42#define EINT7 71 /* EDGE Port interrupt 7 */
39 43
40#ifdef MCFICM_INTC1 44#ifdef MCFICM_INTC1
41#define NR_VECS 128 45#define NR_VECS 128
@@ -43,66 +47,147 @@ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
43#define NR_VECS 64 47#define NR_VECS 64
44#endif 48#endif
45 49
46static void intc_irq_mask(unsigned int irq) 50static void intc_irq_mask(struct irq_data *d)
47{ 51{
48 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { 52 unsigned int irq = d->irq - MCFINT_VECBASE;
49 unsigned long imraddr; 53 unsigned long imraddr;
50 u32 val, imrbit; 54 u32 val, imrbit;
51 55
52 irq -= MCFINT_VECBASE;
53 imraddr = MCF_IPSBAR;
54#ifdef MCFICM_INTC1 56#ifdef MCFICM_INTC1
55 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 57 imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
56#else 58#else
57 imraddr += MCFICM_INTC0; 59 imraddr = MCFICM_INTC0;
58#endif 60#endif
59 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; 61 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
60 imrbit = 0x1 << (irq & 0x1f); 62 imrbit = 0x1 << (irq & 0x1f);
61 63
62 val = __raw_readl(imraddr); 64 val = __raw_readl(imraddr);
63 __raw_writel(val | imrbit, imraddr); 65 __raw_writel(val | imrbit, imraddr);
64 } 66}
67
68static void intc_irq_unmask(struct irq_data *d)
69{
70 unsigned int irq = d->irq - MCFINT_VECBASE;
71 unsigned long imraddr;
72 u32 val, imrbit;
73
74#ifdef MCFICM_INTC1
75 imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
76#else
77 imraddr = MCFICM_INTC0;
78#endif
79 imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
80 imrbit = 0x1 << (irq & 0x1f);
81
82 /* Don't set the "maskall" bit! */
83 if ((irq & 0x20) == 0)
84 imrbit |= 0x1;
85
86 val = __raw_readl(imraddr);
87 __raw_writel(val & ~imrbit, imraddr);
88}
89
90/*
91 * Only the external (or EDGE Port) interrupts need to be acknowledged
92 * here, as part of the IRQ handler. They only really need to be ack'ed
93 * if they are in edge triggered mode, but there is no harm in doing it
94 * for all types.
95 */
96static void intc_irq_ack(struct irq_data *d)
97{
98 unsigned int irq = d->irq;
99
100 __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
65} 101}
66 102
67static void intc_irq_unmask(unsigned int irq) 103/*
104 * Each vector needs a unique priority and level associated with it.
105 * We don't really care so much what they are, we don't rely on the
106 * traditional priority interrupt scheme of the m68k/ColdFire. This
107 * only needs to be set once for an interrupt, and we will never change
108 * these values once we have set them.
109 */
110static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
111
112static unsigned int intc_irq_startup(struct irq_data *d)
68{ 113{
69 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { 114 unsigned int irq = d->irq - MCFINT_VECBASE;
70 unsigned long intaddr, imraddr, icraddr; 115 unsigned long icraddr;
71 u32 val, imrbit;
72 116
73 irq -= MCFINT_VECBASE;
74 intaddr = MCF_IPSBAR;
75#ifdef MCFICM_INTC1 117#ifdef MCFICM_INTC1
76 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 118 icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
77#else 119#else
78 intaddr += MCFICM_INTC0; 120 icraddr = MCFICM_INTC0;
79#endif 121#endif
80 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); 122 icraddr += MCFINTC_ICR0 + (irq & 0x3f);
81 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); 123 if (__raw_readb(icraddr) == 0)
82 imrbit = 0x1 << (irq & 0x1f); 124 __raw_writeb(intc_intpri--, icraddr);
83 125
84 /* Don't set the "maskall" bit! */ 126 irq = d->irq;
85 if ((irq & 0x20) == 0) 127 if ((irq >= EINT1) && (irq <= EINT7)) {
86 imrbit |= 0x1; 128 u8 v;
87 129
88 if (__raw_readb(icraddr) == 0) 130 irq -= EINT0;
89 __raw_writeb(intc_intpri--, icraddr);
90 131
91 val = __raw_readl(imraddr); 132 /* Set EPORT line as input */
92 __raw_writel(val & ~imrbit, imraddr); 133 v = __raw_readb(MCFEPORT_EPDDR);
134 __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
135
136 /* Set EPORT line as interrupt source */
137 v = __raw_readb(MCFEPORT_EPIER);
138 __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
93 } 139 }
140
141 intc_irq_unmask(d);
142 return 0;
94} 143}
95 144
96static int intc_irq_set_type(unsigned int irq, unsigned int type) 145static int intc_irq_set_type(struct irq_data *d, unsigned int type)
97{ 146{
147 unsigned int irq = d->irq;
148 u16 pa, tb;
149
150 switch (type) {
151 case IRQ_TYPE_EDGE_RISING:
152 tb = 0x1;
153 break;
154 case IRQ_TYPE_EDGE_FALLING:
155 tb = 0x2;
156 break;
157 case IRQ_TYPE_EDGE_BOTH:
158 tb = 0x3;
159 break;
160 default:
161 /* Level triggered */
162 tb = 0;
163 break;
164 }
165
166 if (tb)
167 set_irq_handler(irq, handle_edge_irq);
168
169 irq -= EINT0;
170 pa = __raw_readw(MCFEPORT_EPPAR);
171 pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
172 __raw_writew(pa, MCFEPORT_EPPAR);
173
98 return 0; 174 return 0;
99} 175}
100 176
101static struct irq_chip intc_irq_chip = { 177static struct irq_chip intc_irq_chip = {
102 .name = "CF-INTC", 178 .name = "CF-INTC",
103 .mask = intc_irq_mask, 179 .irq_startup = intc_irq_startup,
104 .unmask = intc_irq_unmask, 180 .irq_mask = intc_irq_mask,
105 .set_type = intc_irq_set_type, 181 .irq_unmask = intc_irq_unmask,
182};
183
184static struct irq_chip intc_irq_chip_edge_port = {
185 .name = "CF-INTC-EP",
186 .irq_startup = intc_irq_startup,
187 .irq_mask = intc_irq_mask,
188 .irq_unmask = intc_irq_unmask,
189 .irq_ack = intc_irq_ack,
190 .irq_set_type = intc_irq_set_type,
106}; 191};
107 192
108void __init init_IRQ(void) 193void __init init_IRQ(void)
@@ -112,13 +197,16 @@ void __init init_IRQ(void)
112 init_vectors(); 197 init_vectors();
113 198
114 /* Mask all interrupt sources */ 199 /* Mask all interrupt sources */
115 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); 200 __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
116#ifdef MCFICM_INTC1 201#ifdef MCFICM_INTC1
117 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); 202 __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
118#endif 203#endif
119 204
120 for (irq = 0; (irq < NR_IRQS); irq++) { 205 for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
121 set_irq_chip(irq, &intc_irq_chip); 206 if ((irq >= EINT1) && (irq <=EINT7))
207 set_irq_chip(irq, &intc_irq_chip_edge_port);
208 else
209 set_irq_chip(irq, &intc_irq_chip);
122 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); 210 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
123 set_irq_handler(irq, handle_level_irq); 211 set_irq_handler(irq, handle_level_irq);
124 } 212 }
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index bb7048636140..e642b24ab729 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. 4 * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
5 * 5 *
6 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 6 * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive 9 * License. See the file COPYING in the main directory of this archive
@@ -20,47 +20,156 @@
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/traps.h> 21#include <asm/traps.h>
22 22
23static void intc_irq_mask(unsigned int irq) 23/*
24 * The EDGE Port interrupts are the fixed 7 external interrupts.
25 * They need some special treatment, for example they need to be acked.
26 */
27#ifdef CONFIG_M520x
28/*
29 * The 520x parts only support a limited range of these external
30 * interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67).
31 */
32#define EINT0 64 /* Is not actually used, but spot reserved for it */
33#define EINT1 65 /* EDGE Port interrupt 1 */
34#define EINT4 66 /* EDGE Port interrupt 4 */
35#define EINT7 67 /* EDGE Port interrupt 7 */
36
37static unsigned int irqebitmap[] = { 0, 1, 4, 7 };
38static unsigned int inline irq2ebit(unsigned int irq)
24{ 39{
25 if (irq >= MCFINT_VECBASE) { 40 return irqebitmap[irq - EINT0];
26 if (irq < MCFINT_VECBASE + 64) 41}
27 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR); 42
28 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR) 43#else
29 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR); 44
30 } 45/*
46 * Most of the ColdFire parts with the EDGE Port module just have
47 * a strait direct mapping of the 7 external interrupts. Although
48 * there is a bit reserved for 0, it is not used.
49 */
50#define EINT0 64 /* Is not actually used, but spot reserved for it */
51#define EINT1 65 /* EDGE Port interrupt 1 */
52#define EINT7 71 /* EDGE Port interrupt 7 */
53
54static unsigned int inline irq2ebit(unsigned int irq)
55{
56 return irq - EINT0;
57}
58
59#endif
60
61/*
62 * There maybe one or two interrupt control units, each has 64
63 * interrupts. If there is no second unit then MCFINTC1_* defines
64 * will be 0 (and code for them optimized away).
65 */
66
67static void intc_irq_mask(struct irq_data *d)
68{
69 unsigned int irq = d->irq - MCFINT_VECBASE;
70
71 if (MCFINTC1_SIMR && (irq > 64))
72 __raw_writeb(irq - 64, MCFINTC1_SIMR);
73 else
74 __raw_writeb(irq, MCFINTC0_SIMR);
31} 75}
32 76
33static void intc_irq_unmask(unsigned int irq) 77static void intc_irq_unmask(struct irq_data *d)
34{ 78{
35 if (irq >= MCFINT_VECBASE) { 79 unsigned int irq = d->irq - MCFINT_VECBASE;
36 if (irq < MCFINT_VECBASE + 64) 80
37 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR); 81 if (MCFINTC1_CIMR && (irq > 64))
38 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR) 82 __raw_writeb(irq - 64, MCFINTC1_CIMR);
39 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR); 83 else
84 __raw_writeb(irq, MCFINTC0_CIMR);
85}
86
87static void intc_irq_ack(struct irq_data *d)
88{
89 unsigned int ebit = irq2ebit(d->irq);
90
91 __raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
92}
93
94static unsigned int intc_irq_startup(struct irq_data *d)
95{
96 unsigned int irq = d->irq;
97
98 if ((irq >= EINT1) && (irq <= EINT7)) {
99 unsigned int ebit = irq2ebit(irq);
100 u8 v;
101
102 /* Set EPORT line as input */
103 v = __raw_readb(MCFEPORT_EPDDR);
104 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
105
106 /* Set EPORT line as interrupt source */
107 v = __raw_readb(MCFEPORT_EPIER);
108 __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
40 } 109 }
110
111 irq -= MCFINT_VECBASE;
112 if (MCFINTC1_ICR0 && (irq > 64))
113 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
114 else
115 __raw_writeb(5, MCFINTC0_ICR0 + irq);
116
117
118 intc_irq_unmask(d);
119 return 0;
41} 120}
42 121
43static int intc_irq_set_type(unsigned int irq, unsigned int type) 122static int intc_irq_set_type(struct irq_data *d, unsigned int type)
44{ 123{
45 if (irq >= MCFINT_VECBASE) { 124 unsigned int ebit, irq = d->irq;
46 if (irq < MCFINT_VECBASE + 64) 125 u16 pa, tb;
47 __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE); 126
48 else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0) 127 switch (type) {
49 __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64); 128 case IRQ_TYPE_EDGE_RISING:
129 tb = 0x1;
130 break;
131 case IRQ_TYPE_EDGE_FALLING:
132 tb = 0x2;
133 break;
134 case IRQ_TYPE_EDGE_BOTH:
135 tb = 0x3;
136 break;
137 default:
138 /* Level triggered */
139 tb = 0;
140 break;
50 } 141 }
142
143 if (tb)
144 set_irq_handler(irq, handle_edge_irq);
145
146 ebit = irq2ebit(irq) * 2;
147 pa = __raw_readw(MCFEPORT_EPPAR);
148 pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
149 __raw_writew(pa, MCFEPORT_EPPAR);
150
51 return 0; 151 return 0;
52} 152}
53 153
54static struct irq_chip intc_irq_chip = { 154static struct irq_chip intc_irq_chip = {
55 .name = "CF-INTC", 155 .name = "CF-INTC",
56 .mask = intc_irq_mask, 156 .irq_startup = intc_irq_startup,
57 .unmask = intc_irq_unmask, 157 .irq_mask = intc_irq_mask,
58 .set_type = intc_irq_set_type, 158 .irq_unmask = intc_irq_unmask,
159};
160
161static struct irq_chip intc_irq_chip_edge_port = {
162 .name = "CF-INTC-EP",
163 .irq_startup = intc_irq_startup,
164 .irq_mask = intc_irq_mask,
165 .irq_unmask = intc_irq_unmask,
166 .irq_ack = intc_irq_ack,
167 .irq_set_type = intc_irq_set_type,
59}; 168};
60 169
61void __init init_IRQ(void) 170void __init init_IRQ(void)
62{ 171{
63 int irq; 172 int irq, eirq;
64 173
65 init_vectors(); 174 init_vectors();
66 175
@@ -69,8 +178,12 @@ void __init init_IRQ(void)
69 if (MCFINTC1_SIMR) 178 if (MCFINTC1_SIMR)
70 __raw_writeb(0xff, MCFINTC1_SIMR); 179 __raw_writeb(0xff, MCFINTC1_SIMR);
71 180
72 for (irq = 0; (irq < NR_IRQS); irq++) { 181 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
73 set_irq_chip(irq, &intc_irq_chip); 182 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
183 if ((irq >= EINT1) && (irq <= EINT7))
184 set_irq_chip(irq, &intc_irq_chip_edge_port);
185 else
186 set_irq_chip(irq, &intc_irq_chip);
74 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); 187 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
75 set_irq_handler(irq, handle_level_irq); 188 set_irq_handler(irq, handle_level_irq);
76 } 189 }
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index 60d2fcbe182b..d648081a63f6 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -111,28 +111,28 @@ void mcf_autovector(int irq)
111#endif 111#endif
112} 112}
113 113
114static void intc_irq_mask(unsigned int irq) 114static void intc_irq_mask(struct irq_data *d)
115{ 115{
116 if (mcf_irq2imr[irq]) 116 if (mcf_irq2imr[d->irq])
117 mcf_setimr(mcf_irq2imr[irq]); 117 mcf_setimr(mcf_irq2imr[d->irq]);
118} 118}
119 119
120static void intc_irq_unmask(unsigned int irq) 120static void intc_irq_unmask(struct irq_data *d)
121{ 121{
122 if (mcf_irq2imr[irq]) 122 if (mcf_irq2imr[d->irq])
123 mcf_clrimr(mcf_irq2imr[irq]); 123 mcf_clrimr(mcf_irq2imr[d->irq]);
124} 124}
125 125
126static int intc_irq_set_type(unsigned int irq, unsigned int type) 126static int intc_irq_set_type(struct irq_data *d, unsigned int type)
127{ 127{
128 return 0; 128 return 0;
129} 129}
130 130
131static struct irq_chip intc_irq_chip = { 131static struct irq_chip intc_irq_chip = {
132 .name = "CF-INTC", 132 .name = "CF-INTC",
133 .mask = intc_irq_mask, 133 .irq_mask = intc_irq_mask,
134 .unmask = intc_irq_unmask, 134 .irq_unmask = intc_irq_unmask,
135 .set_type = intc_irq_set_type, 135 .irq_set_type = intc_irq_set_type,
136}; 136};
137 137
138void __init init_IRQ(void) 138void __init init_IRQ(void)
diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c
index aebea19abd78..c2b980926bec 100644
--- a/arch/m68knommu/platform/coldfire/pit.c
+++ b/arch/m68knommu/platform/coldfire/pit.c
@@ -31,7 +31,7 @@
31 * By default use timer1 as the system clock timer. 31 * By default use timer1 as the system clock timer.
32 */ 32 */
33#define FREQ ((MCF_CLK / 2) / 64) 33#define FREQ ((MCF_CLK / 2) / 64)
34#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) 34#define TA(a) (MCFPIT_BASE1 + (a))
35#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) 35#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
36 36
37static u32 pit_cnt; 37static u32 pit_cnt;
diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c
index 2304d736c701..60242f65fea9 100644
--- a/arch/m68knommu/platform/coldfire/timers.c
+++ b/arch/m68knommu/platform/coldfire/timers.c
@@ -28,7 +28,7 @@
28 * By default use timer1 as the system clock timer. 28 * By default use timer1 as the system clock timer.
29 */ 29 */
30#define FREQ (MCF_BUSCLK / 16) 30#define FREQ (MCF_BUSCLK / 16)
31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) 31#define TA(a) (MCFTIMER_BASE1 + (a))
32 32
33/* 33/*
34 * These provide the underlying interrupt vector support. 34 * These provide the underlying interrupt vector support.
@@ -126,7 +126,7 @@ void hw_timer_init(void)
126/* 126/*
127 * By default use timer2 as the profiler clock timer. 127 * By default use timer2 as the profiler clock timer.
128 */ 128 */
129#define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a)) 129#define PA(a) (MCFTIMER_BASE2 + (a))
130 130
131/* 131/*
132 * Choose a reasonably fast profile timer. Make it an odd value to 132 * Choose a reasonably fast profile timer. Make it an odd value to
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 21:02:19 -0500