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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h41
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c19
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c6
3 files changed, 16 insertions, 50 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 3a07e580d27a..135594c44167 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -485,13 +485,13 @@ enum nv04_fp_display_regs {
485}; 485};
486 486
487struct nv04_crtc_reg { 487struct nv04_crtc_reg {
488 unsigned char MiscOutReg; /* */ 488 unsigned char MiscOutReg;
489 uint8_t CRTC[0xa0]; 489 uint8_t CRTC[0xa0];
490 uint8_t CR58[0x10]; 490 uint8_t CR58[0x10];
491 uint8_t Sequencer[5]; 491 uint8_t Sequencer[5];
492 uint8_t Graphics[9]; 492 uint8_t Graphics[9];
493 uint8_t Attribute[21]; 493 uint8_t Attribute[21];
494 unsigned char DAC[768]; /* Internal Colorlookuptable */ 494 unsigned char DAC[768];
495 495
496 /* PCRTC regs */ 496 /* PCRTC regs */
497 uint32_t fb_start; 497 uint32_t fb_start;
@@ -539,43 +539,9 @@ struct nv04_output_reg {
539}; 539};
540 540
541struct nv04_mode_state { 541struct nv04_mode_state {
542 uint32_t bpp; 542 struct nv04_crtc_reg crtc_reg[2];
543 uint32_t width;
544 uint32_t height;
545 uint32_t interlace;
546 uint32_t repaint0;
547 uint32_t repaint1;
548 uint32_t screen;
549 uint32_t scale;
550 uint32_t dither;
551 uint32_t extra;
552 uint32_t fifo;
553 uint32_t pixel;
554 uint32_t horiz;
555 int arbitration0;
556 int arbitration1;
557 uint32_t pll;
558 uint32_t pllB;
559 uint32_t vpll;
560 uint32_t vpll2;
561 uint32_t vpllB;
562 uint32_t vpll2B;
563 uint32_t pllsel; 543 uint32_t pllsel;
564 uint32_t sel_clk; 544 uint32_t sel_clk;
565 uint32_t general;
566 uint32_t crtcOwner;
567 uint32_t head;
568 uint32_t head2;
569 uint32_t cursorConfig;
570 uint32_t cursor0;
571 uint32_t cursor1;
572 uint32_t cursor2;
573 uint32_t timingH;
574 uint32_t timingV;
575 uint32_t displayV;
576 uint32_t crtcSync;
577
578 struct nv04_crtc_reg crtc_reg[2];
579}; 545};
580 546
581enum nouveau_card_type { 547enum nouveau_card_type {
@@ -1239,7 +1205,6 @@ extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1239extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1205extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1240extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1206extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1241extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1207extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1242extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
1243 1208
1244/* nouveau_fence.c */ 1209/* nouveau_fence.c */
1245struct nouveau_fence; 1210struct nouveau_fence;
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index b9e1ffed8557..e2f2d59be3ea 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -209,8 +209,8 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
209 } 209 }
210 210
211 if (status & NV_PFIFO_INTR_DMA_PUSHER) { 211 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
212 u32 get = nv_rd32(dev, 0x003244); 212 u32 dma_get = nv_rd32(dev, 0x003244);
213 u32 put = nv_rd32(dev, 0x003240); 213 u32 dma_put = nv_rd32(dev, 0x003240);
214 u32 push = nv_rd32(dev, 0x003220); 214 u32 push = nv_rd32(dev, 0x003220);
215 u32 state = nv_rd32(dev, 0x003228); 215 u32 state = nv_rd32(dev, 0x003228);
216 216
@@ -224,13 +224,14 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
224 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x " 224 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
225 "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x " 225 "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
226 "State 0x%08x Push 0x%08x\n", 226 "State 0x%08x Push 0x%08x\n",
227 chid, ho_get, get, ho_put, put, 227 chid, ho_get, dma_get, ho_put,
228 ib_get, ib_put, state, push); 228 dma_put, ib_get, ib_put, state,
229 push);
229 230
230 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ 231 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
231 nv_wr32(dev, 0x003364, 0x00000000); 232 nv_wr32(dev, 0x003364, 0x00000000);
232 if (get != put || ho_get != ho_put) { 233 if (dma_get != dma_put || ho_get != ho_put) {
233 nv_wr32(dev, 0x003244, put); 234 nv_wr32(dev, 0x003244, dma_put);
234 nv_wr32(dev, 0x003328, ho_put); 235 nv_wr32(dev, 0x003328, ho_put);
235 } else 236 } else
236 if (ib_get != ib_put) { 237 if (ib_get != ib_put) {
@@ -239,10 +240,10 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
239 } else { 240 } else {
240 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x " 241 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
241 "Put 0x%08x State 0x%08x Push 0x%08x\n", 242 "Put 0x%08x State 0x%08x Push 0x%08x\n",
242 chid, get, put, state, push); 243 chid, dma_get, dma_put, state, push);
243 244
244 if (get != put) 245 if (dma_get != dma_put)
245 nv_wr32(dev, 0x003244, put); 246 nv_wr32(dev, 0x003244, dma_put);
246 } 247 }
247 248
248 nv_wr32(dev, 0x003228, 0x00000000); 249 nv_wr32(dev, 0x003228, 0x00000000);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index a163c7c612e7..1165c3e68200 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -33,9 +33,9 @@
33#include "drmP.h" 33#include "drmP.h"
34#include "drm.h" 34#include "drm.h"
35#include "drm_sarea.h" 35#include "drm_sarea.h"
36#include "nouveau_drv.h"
37 36
38#define MIN(a,b) a < b ? a : b 37#include "nouveau_drv.h"
38#include "nouveau_pm.h"
39 39
40/* 40/*
41 * NV10-NV40 tiling helpers 41 * NV10-NV40 tiling helpers
@@ -719,7 +719,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
719 tUNK_19 = 1; 719 tUNK_19 = 1;
720 tUNK_20 = 0; 720 tUNK_20 = 0;
721 tUNK_21 = 0; 721 tUNK_21 = 0;
722 switch (MIN(recordlen,21)) { 722 switch (min(recordlen, 21)) {
723 case 21: 723 case 21:
724 tUNK_21 = entry[21]; 724 tUNK_21 = entry[21];
725 case 20: 725 case 20: