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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c15
2 files changed, 18 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f79b13324faf..149d360d64a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -975,6 +975,8 @@
975#define LVDS_PORT_EN (1 << 31) 975#define LVDS_PORT_EN (1 << 31)
976/* Selects pipe B for LVDS data. Must be set on pre-965. */ 976/* Selects pipe B for LVDS data. Must be set on pre-965. */
977#define LVDS_PIPEB_SELECT (1 << 30) 977#define LVDS_PIPEB_SELECT (1 << 30)
978/* LVDS dithering flag on 965/g4x platform */
979#define LVDS_ENABLE_DITHER (1 << 25)
978/* Enable border for unscaled (or aspect-scaled) display */ 980/* Enable border for unscaled (or aspect-scaled) display */
979#define LVDS_BORDER_ENABLE (1 << 15) 981#define LVDS_BORDER_ENABLE (1 << 15)
980/* 982/*
@@ -1744,6 +1746,8 @@
1744 1746
1745/* Display & cursor control */ 1747/* Display & cursor control */
1746 1748
1749/* dithering flag on Ironlake */
1750#define PIPE_ENABLE_DITHER (1 << 4)
1747/* Pipe A */ 1751/* Pipe A */
1748#define PIPEADSL 0x70000 1752#define PIPEADSL 0x70000
1749#define PIPEACONF 0x70008 1753#define PIPEACONF 0x70008
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84705b7e01ec..0c9b79f2ab31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3195,7 +3195,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3195 * appropriately here, but we need to look more thoroughly into how 3195 * appropriately here, but we need to look more thoroughly into how
3196 * panels behave in the two modes. 3196 * panels behave in the two modes.
3197 */ 3197 */
3198 3198 /* set the dithering flag */
3199 if (IS_I965G(dev)) {
3200 if (dev_priv->lvds_dither) {
3201 if (IS_IRONLAKE(dev))
3202 pipeconf |= PIPE_ENABLE_DITHER;
3203 else
3204 lvds |= LVDS_ENABLE_DITHER;
3205 } else {
3206 if (IS_IRONLAKE(dev))
3207 pipeconf &= ~PIPE_ENABLE_DITHER;
3208 else
3209 lvds &= ~LVDS_ENABLE_DITHER;
3210 }
3211 }
3199 I915_WRITE(lvds_reg, lvds); 3212 I915_WRITE(lvds_reg, lvds);
3200 I915_READ(lvds_reg); 3213 I915_READ(lvds_reg);
3201 } 3214 }