diff options
-rw-r--r-- | drivers/ata/sata_promise.c | 124 |
1 files changed, 65 insertions, 59 deletions
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c index f5ea06bbde75..b5a2f4f25d19 100644 --- a/drivers/ata/sata_promise.c +++ b/drivers/ata/sata_promise.c | |||
@@ -53,7 +53,15 @@ enum { | |||
53 | PDC_MMIO_BAR = 3, | 53 | PDC_MMIO_BAR = 3, |
54 | PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ | 54 | PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ |
55 | 55 | ||
56 | /* register offsets */ | 56 | /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ |
57 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | ||
58 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | ||
59 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | ||
60 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ | ||
61 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ | ||
62 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | ||
63 | |||
64 | /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ | ||
57 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | 65 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ |
58 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | 66 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ |
59 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | 67 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ |
@@ -63,14 +71,11 @@ enum { | |||
63 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | 71 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ |
64 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ | 72 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
65 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | 73 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
66 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | ||
67 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | ||
68 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | 74 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
69 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | 75 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ |
70 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | 76 | |
71 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ | 77 | /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ |
72 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ | 78 | PDC_PHYMODE4 = 0x14, |
73 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | ||
74 | 79 | ||
75 | /* PDC_GLOBAL_CTL bit definitions */ | 80 | /* PDC_GLOBAL_CTL bit definitions */ |
76 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ | 81 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ |
@@ -332,12 +337,12 @@ static int pdc_sata_port_start(struct ata_port *ap) | |||
332 | 337 | ||
333 | /* fix up PHYMODE4 align timing */ | 338 | /* fix up PHYMODE4 align timing */ |
334 | if (ap->flags & PDC_FLAG_GEN_II) { | 339 | if (ap->flags & PDC_FLAG_GEN_II) { |
335 | void __iomem *mmio = ap->ioaddr.scr_addr; | 340 | void __iomem *sata_mmio = ap->ioaddr.scr_addr; |
336 | unsigned int tmp; | 341 | unsigned int tmp; |
337 | 342 | ||
338 | tmp = readl(mmio + 0x014); | 343 | tmp = readl(sata_mmio + PDC_PHYMODE4); |
339 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | 344 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ |
340 | writel(tmp, mmio + 0x014); | 345 | writel(tmp, sata_mmio + PDC_PHYMODE4); |
341 | } | 346 | } |
342 | 347 | ||
343 | return 0; | 348 | return 0; |
@@ -345,32 +350,32 @@ static int pdc_sata_port_start(struct ata_port *ap) | |||
345 | 350 | ||
346 | static void pdc_reset_port(struct ata_port *ap) | 351 | static void pdc_reset_port(struct ata_port *ap) |
347 | { | 352 | { |
348 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; | 353 | void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
349 | unsigned int i; | 354 | unsigned int i; |
350 | u32 tmp; | 355 | u32 tmp; |
351 | 356 | ||
352 | for (i = 11; i > 0; i--) { | 357 | for (i = 11; i > 0; i--) { |
353 | tmp = readl(mmio); | 358 | tmp = readl(ata_ctlstat_mmio); |
354 | if (tmp & PDC_RESET) | 359 | if (tmp & PDC_RESET) |
355 | break; | 360 | break; |
356 | 361 | ||
357 | udelay(100); | 362 | udelay(100); |
358 | 363 | ||
359 | tmp |= PDC_RESET; | 364 | tmp |= PDC_RESET; |
360 | writel(tmp, mmio); | 365 | writel(tmp, ata_ctlstat_mmio); |
361 | } | 366 | } |
362 | 367 | ||
363 | tmp &= ~PDC_RESET; | 368 | tmp &= ~PDC_RESET; |
364 | writel(tmp, mmio); | 369 | writel(tmp, ata_ctlstat_mmio); |
365 | readl(mmio); /* flush */ | 370 | readl(ata_ctlstat_mmio); /* flush */ |
366 | } | 371 | } |
367 | 372 | ||
368 | static int pdc_pata_cable_detect(struct ata_port *ap) | 373 | static int pdc_pata_cable_detect(struct ata_port *ap) |
369 | { | 374 | { |
370 | u8 tmp; | 375 | u8 tmp; |
371 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; | 376 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
372 | 377 | ||
373 | tmp = readb(mmio); | 378 | tmp = readb(ata_mmio + PDC_CTLSTAT + 3); |
374 | if (tmp & 0x01) | 379 | if (tmp & 0x01) |
375 | return ATA_CBL_PATA40; | 380 | return ATA_CBL_PATA40; |
376 | return ATA_CBL_PATA80; | 381 | return ATA_CBL_PATA80; |
@@ -624,14 +629,14 @@ static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap) | |||
624 | 629 | ||
625 | static void pdc_freeze(struct ata_port *ap) | 630 | static void pdc_freeze(struct ata_port *ap) |
626 | { | 631 | { |
627 | void __iomem *mmio = ap->ioaddr.cmd_addr; | 632 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
628 | u32 tmp; | 633 | u32 tmp; |
629 | 634 | ||
630 | tmp = readl(mmio + PDC_CTLSTAT); | 635 | tmp = readl(ata_mmio + PDC_CTLSTAT); |
631 | tmp |= PDC_IRQ_DISABLE; | 636 | tmp |= PDC_IRQ_DISABLE; |
632 | tmp &= ~PDC_DMA_ENABLE; | 637 | tmp &= ~PDC_DMA_ENABLE; |
633 | writel(tmp, mmio + PDC_CTLSTAT); | 638 | writel(tmp, ata_mmio + PDC_CTLSTAT); |
634 | readl(mmio + PDC_CTLSTAT); /* flush */ | 639 | readl(ata_mmio + PDC_CTLSTAT); /* flush */ |
635 | } | 640 | } |
636 | 641 | ||
637 | static void pdc_sata_freeze(struct ata_port *ap) | 642 | static void pdc_sata_freeze(struct ata_port *ap) |
@@ -659,17 +664,17 @@ static void pdc_sata_freeze(struct ata_port *ap) | |||
659 | 664 | ||
660 | static void pdc_thaw(struct ata_port *ap) | 665 | static void pdc_thaw(struct ata_port *ap) |
661 | { | 666 | { |
662 | void __iomem *mmio = ap->ioaddr.cmd_addr; | 667 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
663 | u32 tmp; | 668 | u32 tmp; |
664 | 669 | ||
665 | /* clear IRQ */ | 670 | /* clear IRQ */ |
666 | readl(mmio + PDC_COMMAND); | 671 | readl(ata_mmio + PDC_COMMAND); |
667 | 672 | ||
668 | /* turn IRQ back on */ | 673 | /* turn IRQ back on */ |
669 | tmp = readl(mmio + PDC_CTLSTAT); | 674 | tmp = readl(ata_mmio + PDC_CTLSTAT); |
670 | tmp &= ~PDC_IRQ_DISABLE; | 675 | tmp &= ~PDC_IRQ_DISABLE; |
671 | writel(tmp, mmio + PDC_CTLSTAT); | 676 | writel(tmp, ata_mmio + PDC_CTLSTAT); |
672 | readl(mmio + PDC_CTLSTAT); /* flush */ | 677 | readl(ata_mmio + PDC_CTLSTAT); /* flush */ |
673 | } | 678 | } |
674 | 679 | ||
675 | static void pdc_sata_thaw(struct ata_port *ap) | 680 | static void pdc_sata_thaw(struct ata_port *ap) |
@@ -747,7 +752,7 @@ static inline unsigned int pdc_host_intr(struct ata_port *ap, | |||
747 | struct ata_queued_cmd *qc) | 752 | struct ata_queued_cmd *qc) |
748 | { | 753 | { |
749 | unsigned int handled = 0; | 754 | unsigned int handled = 0; |
750 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; | 755 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
751 | u32 port_status, err_mask; | 756 | u32 port_status, err_mask; |
752 | 757 | ||
753 | err_mask = PDC_ERR_MASK; | 758 | err_mask = PDC_ERR_MASK; |
@@ -755,7 +760,7 @@ static inline unsigned int pdc_host_intr(struct ata_port *ap, | |||
755 | err_mask &= ~PDC1_ERR_MASK; | 760 | err_mask &= ~PDC1_ERR_MASK; |
756 | else | 761 | else |
757 | err_mask &= ~PDC2_ERR_MASK; | 762 | err_mask &= ~PDC2_ERR_MASK; |
758 | port_status = readl(port_mmio + PDC_GLOBAL_CTL); | 763 | port_status = readl(ata_mmio + PDC_GLOBAL_CTL); |
759 | if (unlikely(port_status & err_mask)) { | 764 | if (unlikely(port_status & err_mask)) { |
760 | pdc_error_intr(ap, qc, port_status, err_mask); | 765 | pdc_error_intr(ap, qc, port_status, err_mask); |
761 | return 1; | 766 | return 1; |
@@ -781,9 +786,9 @@ static inline unsigned int pdc_host_intr(struct ata_port *ap, | |||
781 | 786 | ||
782 | static void pdc_irq_clear(struct ata_port *ap) | 787 | static void pdc_irq_clear(struct ata_port *ap) |
783 | { | 788 | { |
784 | void __iomem *mmio = ap->ioaddr.cmd_addr; | 789 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; |
785 | 790 | ||
786 | readl(mmio + PDC_COMMAND); | 791 | readl(ata_mmio + PDC_COMMAND); |
787 | } | 792 | } |
788 | 793 | ||
789 | static irqreturn_t pdc_interrupt(int irq, void *dev_instance) | 794 | static irqreturn_t pdc_interrupt(int irq, void *dev_instance) |
@@ -793,7 +798,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance) | |||
793 | u32 mask = 0; | 798 | u32 mask = 0; |
794 | unsigned int i, tmp; | 799 | unsigned int i, tmp; |
795 | unsigned int handled = 0; | 800 | unsigned int handled = 0; |
796 | void __iomem *mmio_base; | 801 | void __iomem *host_mmio; |
797 | unsigned int hotplug_offset, ata_no; | 802 | unsigned int hotplug_offset, ata_no; |
798 | u32 hotplug_status; | 803 | u32 hotplug_status; |
799 | int is_sataii_tx4; | 804 | int is_sataii_tx4; |
@@ -805,7 +810,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance) | |||
805 | return IRQ_NONE; | 810 | return IRQ_NONE; |
806 | } | 811 | } |
807 | 812 | ||
808 | mmio_base = host->iomap[PDC_MMIO_BAR]; | 813 | host_mmio = host->iomap[PDC_MMIO_BAR]; |
809 | 814 | ||
810 | spin_lock(&host->lock); | 815 | spin_lock(&host->lock); |
811 | 816 | ||
@@ -814,13 +819,13 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance) | |||
814 | hotplug_offset = PDC2_SATA_PLUG_CSR; | 819 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
815 | else | 820 | else |
816 | hotplug_offset = PDC_SATA_PLUG_CSR; | 821 | hotplug_offset = PDC_SATA_PLUG_CSR; |
817 | hotplug_status = readl(mmio_base + hotplug_offset); | 822 | hotplug_status = readl(host_mmio + hotplug_offset); |
818 | if (hotplug_status & 0xff) | 823 | if (hotplug_status & 0xff) |
819 | writel(hotplug_status | 0xff, mmio_base + hotplug_offset); | 824 | writel(hotplug_status | 0xff, host_mmio + hotplug_offset); |
820 | hotplug_status &= 0xff; /* clear uninteresting bits */ | 825 | hotplug_status &= 0xff; /* clear uninteresting bits */ |
821 | 826 | ||
822 | /* reading should also clear interrupts */ | 827 | /* reading should also clear interrupts */ |
823 | mask = readl(mmio_base + PDC_INT_SEQMASK); | 828 | mask = readl(host_mmio + PDC_INT_SEQMASK); |
824 | 829 | ||
825 | if (mask == 0xffffffff && hotplug_status == 0) { | 830 | if (mask == 0xffffffff && hotplug_status == 0) { |
826 | VPRINTK("QUICK EXIT 2\n"); | 831 | VPRINTK("QUICK EXIT 2\n"); |
@@ -833,7 +838,7 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance) | |||
833 | goto done_irq; | 838 | goto done_irq; |
834 | } | 839 | } |
835 | 840 | ||
836 | writel(mask, mmio_base + PDC_INT_SEQMASK); | 841 | writel(mask, host_mmio + PDC_INT_SEQMASK); |
837 | 842 | ||
838 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); | 843 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); |
839 | 844 | ||
@@ -878,19 +883,20 @@ static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |||
878 | { | 883 | { |
879 | struct ata_port *ap = qc->ap; | 884 | struct ata_port *ap = qc->ap; |
880 | struct pdc_port_priv *pp = ap->private_data; | 885 | struct pdc_port_priv *pp = ap->private_data; |
881 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; | 886 | void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; |
887 | void __iomem *ata_mmio = ap->ioaddr.cmd_addr; | ||
882 | unsigned int port_no = ap->port_no; | 888 | unsigned int port_no = ap->port_no; |
883 | u8 seq = (u8) (port_no + 1); | 889 | u8 seq = (u8) (port_no + 1); |
884 | 890 | ||
885 | VPRINTK("ENTER, ap %p\n", ap); | 891 | VPRINTK("ENTER, ap %p\n", ap); |
886 | 892 | ||
887 | writel(0x00000001, mmio + (seq * 4)); | 893 | writel(0x00000001, host_mmio + (seq * 4)); |
888 | readl(mmio + (seq * 4)); /* flush */ | 894 | readl(host_mmio + (seq * 4)); /* flush */ |
889 | 895 | ||
890 | pp->pkt[2] = seq; | 896 | pp->pkt[2] = seq; |
891 | wmb(); /* flush PRD, pkt writes */ | 897 | wmb(); /* flush PRD, pkt writes */ |
892 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | 898 | writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); |
893 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | 899 | readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ |
894 | } | 900 | } |
895 | 901 | ||
896 | static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) | 902 | static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) |
@@ -986,7 +992,7 @@ static void pdc_ata_setup_port(struct ata_port *ap, | |||
986 | 992 | ||
987 | static void pdc_host_init(struct ata_host *host) | 993 | static void pdc_host_init(struct ata_host *host) |
988 | { | 994 | { |
989 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; | 995 | void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; |
990 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; | 996 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; |
991 | int hotplug_offset; | 997 | int hotplug_offset; |
992 | u32 tmp; | 998 | u32 tmp; |
@@ -1003,38 +1009,38 @@ static void pdc_host_init(struct ata_host *host) | |||
1003 | */ | 1009 | */ |
1004 | 1010 | ||
1005 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ | 1011 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1006 | tmp = readl(mmio + PDC_FLASH_CTL); | 1012 | tmp = readl(host_mmio + PDC_FLASH_CTL); |
1007 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ | 1013 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
1008 | if (!is_gen2) | 1014 | if (!is_gen2) |
1009 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | 1015 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ |
1010 | writel(tmp, mmio + PDC_FLASH_CTL); | 1016 | writel(tmp, host_mmio + PDC_FLASH_CTL); |
1011 | 1017 | ||
1012 | /* clear plug/unplug flags for all ports */ | 1018 | /* clear plug/unplug flags for all ports */ |
1013 | tmp = readl(mmio + hotplug_offset); | 1019 | tmp = readl(host_mmio + hotplug_offset); |
1014 | writel(tmp | 0xff, mmio + hotplug_offset); | 1020 | writel(tmp | 0xff, host_mmio + hotplug_offset); |
1015 | 1021 | ||
1016 | /* unmask plug/unplug ints */ | 1022 | /* unmask plug/unplug ints */ |
1017 | tmp = readl(mmio + hotplug_offset); | 1023 | tmp = readl(host_mmio + hotplug_offset); |
1018 | writel(tmp & ~0xff0000, mmio + hotplug_offset); | 1024 | writel(tmp & ~0xff0000, host_mmio + hotplug_offset); |
1019 | 1025 | ||
1020 | /* don't initialise TBG or SLEW on 2nd generation chips */ | 1026 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
1021 | if (is_gen2) | 1027 | if (is_gen2) |
1022 | return; | 1028 | return; |
1023 | 1029 | ||
1024 | /* reduce TBG clock to 133 Mhz. */ | 1030 | /* reduce TBG clock to 133 Mhz. */ |
1025 | tmp = readl(mmio + PDC_TBG_MODE); | 1031 | tmp = readl(host_mmio + PDC_TBG_MODE); |
1026 | tmp &= ~0x30000; /* clear bit 17, 16*/ | 1032 | tmp &= ~0x30000; /* clear bit 17, 16*/ |
1027 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | 1033 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ |
1028 | writel(tmp, mmio + PDC_TBG_MODE); | 1034 | writel(tmp, host_mmio + PDC_TBG_MODE); |
1029 | 1035 | ||
1030 | readl(mmio + PDC_TBG_MODE); /* flush */ | 1036 | readl(host_mmio + PDC_TBG_MODE); /* flush */ |
1031 | msleep(10); | 1037 | msleep(10); |
1032 | 1038 | ||
1033 | /* adjust slew rate control register. */ | 1039 | /* adjust slew rate control register. */ |
1034 | tmp = readl(mmio + PDC_SLEW_CTL); | 1040 | tmp = readl(host_mmio + PDC_SLEW_CTL); |
1035 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | 1041 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ |
1036 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | 1042 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ |
1037 | writel(tmp, mmio + PDC_SLEW_CTL); | 1043 | writel(tmp, host_mmio + PDC_SLEW_CTL); |
1038 | } | 1044 | } |
1039 | 1045 | ||
1040 | static int pdc_ata_init_one(struct pci_dev *pdev, | 1046 | static int pdc_ata_init_one(struct pci_dev *pdev, |
@@ -1044,7 +1050,7 @@ static int pdc_ata_init_one(struct pci_dev *pdev, | |||
1044 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; | 1050 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; |
1045 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; | 1051 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; |
1046 | struct ata_host *host; | 1052 | struct ata_host *host; |
1047 | void __iomem *base; | 1053 | void __iomem *host_mmio; |
1048 | int n_ports, i, rc; | 1054 | int n_ports, i, rc; |
1049 | int is_sataii_tx4; | 1055 | int is_sataii_tx4; |
1050 | 1056 | ||
@@ -1061,7 +1067,7 @@ static int pdc_ata_init_one(struct pci_dev *pdev, | |||
1061 | pcim_pin_device(pdev); | 1067 | pcim_pin_device(pdev); |
1062 | if (rc) | 1068 | if (rc) |
1063 | return rc; | 1069 | return rc; |
1064 | base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; | 1070 | host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; |
1065 | 1071 | ||
1066 | /* determine port configuration and setup host */ | 1072 | /* determine port configuration and setup host */ |
1067 | n_ports = 2; | 1073 | n_ports = 2; |
@@ -1071,7 +1077,7 @@ static int pdc_ata_init_one(struct pci_dev *pdev, | |||
1071 | ppi[i] = pi; | 1077 | ppi[i] = pi; |
1072 | 1078 | ||
1073 | if (pi->flags & PDC_FLAG_SATA_PATA) { | 1079 | if (pi->flags & PDC_FLAG_SATA_PATA) { |
1074 | u8 tmp = readb(base + PDC_FLASH_CTL+1); | 1080 | u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); |
1075 | if (!(tmp & 0x80)) | 1081 | if (!(tmp & 0x80)) |
1076 | ppi[n_ports++] = pi + 1; | 1082 | ppi[n_ports++] = pi + 1; |
1077 | } | 1083 | } |
@@ -1087,13 +1093,13 @@ static int pdc_ata_init_one(struct pci_dev *pdev, | |||
1087 | for (i = 0; i < host->n_ports; i++) { | 1093 | for (i = 0; i < host->n_ports; i++) { |
1088 | struct ata_port *ap = host->ports[i]; | 1094 | struct ata_port *ap = host->ports[i]; |
1089 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); | 1095 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); |
1090 | unsigned int port_offset = 0x200 + ata_no * 0x80; | 1096 | unsigned int ata_offset = 0x200 + ata_no * 0x80; |
1091 | unsigned int scr_offset = 0x400 + ata_no * 0x100; | 1097 | unsigned int scr_offset = 0x400 + ata_no * 0x100; |
1092 | 1098 | ||
1093 | pdc_ata_setup_port(ap, base + port_offset, base + scr_offset); | 1099 | pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); |
1094 | 1100 | ||
1095 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); | 1101 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); |
1096 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port"); | 1102 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); |
1097 | } | 1103 | } |
1098 | 1104 | ||
1099 | /* initialize adapter */ | 1105 | /* initialize adapter */ |