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-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c237
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c12
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h3
3 files changed, 127 insertions, 125 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 80a12acdf9f8..1c564c982270 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -110,32 +110,32 @@ static struct clk virt_38_4m_ck = {
110}; 110};
111 111
112static const struct clksel_rate osc_sys_12m_rates[] = { 112static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 } 114 { .div = 0 }
115}; 115};
116 116
117static const struct clksel_rate osc_sys_13m_rates[] = { 117static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 } 119 { .div = 0 }
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
127static const struct clksel_rate osc_sys_19_2m_rates[] = { 127static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_343X }, 128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 } 129 { .div = 0 }
130}; 130};
131 131
132static const struct clksel_rate osc_sys_26m_rates[] = { 132static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_343X }, 133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 } 134 { .div = 0 }
135}; 135};
136 136
137static const struct clksel_rate osc_sys_38_4m_rates[] = { 137static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_343X }, 138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 } 139 { .div = 0 }
140}; 140};
141 141
@@ -163,8 +163,8 @@ static struct clk osc_sys_ck = {
163}; 163};
164 164
165static const struct clksel_rate div2_rates[] = { 165static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 } 168 { .div = 0 }
169}; 169};
170 170
@@ -213,22 +213,22 @@ static struct clk sys_clkout1 = {
213/* CM CLOCKS */ 213/* CM CLOCKS */
214 214
215static const struct clksel_rate div16_dpll_rates[] = { 215static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_343X }, 220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_343X }, 222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_343X }, 224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_343X }, 225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_343X }, 226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_343X }, 227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_343X }, 228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_343X }, 229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_343X }, 230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_343X }, 231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 } 232 { .div = 0 }
233}; 233};
234 234
@@ -450,37 +450,37 @@ static struct clk dpll3_x2_ck = {
450}; 450};
451 451
452static const struct clksel_rate div31_dpll3_rates[] = { 452static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, 455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, 456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, 457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, 458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, 459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, 460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, 461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, 462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, 463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, 464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, 465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, 466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, 467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, 468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, 469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, 470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, 471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, 472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, 473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, 474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, 475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, 476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, 477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, 478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, 479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, 480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, 481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, 482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, 483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
484 { .div = 0 }, 484 { .div = 0 },
485}; 485};
486 486
@@ -708,12 +708,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
708}; 708};
709 709
710static const struct clksel_rate omap_96m_dpll_rates[] = { 710static const struct clksel_rate omap_96m_dpll_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 711 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
712 { .div = 0 } 712 { .div = 0 }
713}; 713};
714 714
715static const struct clksel_rate omap_96m_sys_rates[] = { 715static const struct clksel_rate omap_96m_sys_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 716 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
717 { .div = 0 } 717 { .div = 0 }
718}; 718};
719 719
@@ -799,12 +799,12 @@ static struct clk dpll4_m3x2_ck = {
799}; 799};
800 800
801static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 801static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
802 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 802 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
803 { .div = 0 } 803 { .div = 0 }
804}; 804};
805 805
806static const struct clksel_rate omap_54m_alt_rates[] = { 806static const struct clksel_rate omap_54m_alt_rates[] = {
807 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 807 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
808 { .div = 0 } 808 { .div = 0 }
809}; 809};
810 810
@@ -825,12 +825,12 @@ static struct clk omap_54m_fck = {
825}; 825};
826 826
827static const struct clksel_rate omap_48m_cm96m_rates[] = { 827static const struct clksel_rate omap_48m_cm96m_rates[] = {
828 { .div = 2, .val = 0, .flags = RATE_IN_343X }, 828 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
829 { .div = 0 } 829 { .div = 0 }
830}; 830};
831 831
832static const struct clksel_rate omap_48m_alt_rates[] = { 832static const struct clksel_rate omap_48m_alt_rates[] = {
833 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 833 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
834 { .div = 0 } 834 { .div = 0 }
835}; 835};
836 836
@@ -1049,22 +1049,22 @@ static struct clk dpll5_m2_ck = {
1049/* CM EXTERNAL CLOCK OUTPUTS */ 1049/* CM EXTERNAL CLOCK OUTPUTS */
1050 1050
1051static const struct clksel_rate clkout2_src_core_rates[] = { 1051static const struct clksel_rate clkout2_src_core_rates[] = {
1052 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 1052 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1053 { .div = 0 } 1053 { .div = 0 }
1054}; 1054};
1055 1055
1056static const struct clksel_rate clkout2_src_sys_rates[] = { 1056static const struct clksel_rate clkout2_src_sys_rates[] = {
1057 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 1057 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1058 { .div = 0 } 1058 { .div = 0 }
1059}; 1059};
1060 1060
1061static const struct clksel_rate clkout2_src_96m_rates[] = { 1061static const struct clksel_rate clkout2_src_96m_rates[] = {
1062 { .div = 1, .val = 2, .flags = RATE_IN_343X }, 1062 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1063 { .div = 0 } 1063 { .div = 0 }
1064}; 1064};
1065 1065
1066static const struct clksel_rate clkout2_src_54m_rates[] = { 1066static const struct clksel_rate clkout2_src_54m_rates[] = {
1067 { .div = 1, .val = 3, .flags = RATE_IN_343X }, 1067 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1068 { .div = 0 } 1068 { .div = 0 }
1069}; 1069};
1070 1070
@@ -1090,11 +1090,11 @@ static struct clk clkout2_src_ck = {
1090}; 1090};
1091 1091
1092static const struct clksel_rate sys_clkout2_rates[] = { 1092static const struct clksel_rate sys_clkout2_rates[] = {
1093 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 1093 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1094 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1094 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1095 { .div = 4, .val = 2, .flags = RATE_IN_343X }, 1095 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1096 { .div = 8, .val = 3, .flags = RATE_IN_343X }, 1096 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1097 { .div = 16, .val = 4, .flags = RATE_IN_343X }, 1097 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1098 { .div = 0 }, 1098 { .div = 0 },
1099}; 1099};
1100 1100
@@ -1125,9 +1125,9 @@ static struct clk corex2_fck = {
1125/* DPLL power domain clock controls */ 1125/* DPLL power domain clock controls */
1126 1126
1127static const struct clksel_rate div4_rates[] = { 1127static const struct clksel_rate div4_rates[] = {
1128 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 1128 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1129 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1129 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1130 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1130 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1131 { .div = 0 } 1131 { .div = 0 }
1132}; 1132};
1133 1133
@@ -1161,8 +1161,8 @@ static struct clk mpu_ck = {
1161 1161
1162/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1162/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1163static const struct clksel_rate arm_fck_rates[] = { 1163static const struct clksel_rate arm_fck_rates[] = {
1164 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 1164 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1165 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1165 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1166 { .div = 0 }, 1166 { .div = 0 },
1167}; 1167};
1168 1168
@@ -1333,9 +1333,9 @@ static struct clk gfx_cg2_ck = {
1333 1333
1334static const struct clksel_rate sgx_core_rates[] = { 1334static const struct clksel_rate sgx_core_rates[] = {
1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX }, 1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1336 { .div = 3, .val = 0, .flags = RATE_IN_343X }, 1336 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1337 { .div = 4, .val = 1, .flags = RATE_IN_343X }, 1337 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1338 { .div = 6, .val = 2, .flags = RATE_IN_343X }, 1338 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1339 { .div = 0 }, 1339 { .div = 0 },
1340}; 1340};
1341 1341
@@ -1351,7 +1351,7 @@ static const struct clksel_rate sgx_corex2_rates[] = {
1351}; 1351};
1352 1352
1353static const struct clksel_rate sgx_96m_rates[] = { 1353static const struct clksel_rate sgx_96m_rates[] = {
1354 { .div = 1, .val = 3, .flags = RATE_IN_343X }, 1354 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1355 { .div = 0 }, 1355 { .div = 0 },
1356}; 1356};
1357 1357
@@ -1576,12 +1576,12 @@ static struct clk i2c1_fck = {
1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. 1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1577 */ 1577 */
1578static const struct clksel_rate common_mcbsp_96m_rates[] = { 1578static const struct clksel_rate common_mcbsp_96m_rates[] = {
1579 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 1579 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1580 { .div = 0 } 1580 { .div = 0 }
1581}; 1581};
1582 1582
1583static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { 1583static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 1584 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1585 { .div = 0 } 1585 { .div = 0 }
1586}; 1586};
1587 1587
@@ -1714,12 +1714,12 @@ static struct clk hdq_fck = {
1714/* DPLL3-derived clock */ 1714/* DPLL3-derived clock */
1715 1715
1716static const struct clksel_rate ssi_ssr_corex2_rates[] = { 1716static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1717 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 1717 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1718 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1718 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1719 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 1719 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1720 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1720 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1721 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 1721 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1722 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 1722 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1723 { .div = 0 } 1723 { .div = 0 }
1724}; 1724};
1725 1725
@@ -2353,18 +2353,18 @@ static struct clk usbhost_ick = {
2353/* WKUP */ 2353/* WKUP */
2354 2354
2355static const struct clksel_rate usim_96m_rates[] = { 2355static const struct clksel_rate usim_96m_rates[] = {
2356 { .div = 2, .val = 3, .flags = RATE_IN_343X }, 2356 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2357 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2357 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2358 { .div = 8, .val = 5, .flags = RATE_IN_343X }, 2358 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2359 { .div = 10, .val = 6, .flags = RATE_IN_343X }, 2359 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2360 { .div = 0 }, 2360 { .div = 0 },
2361}; 2361};
2362 2362
2363static const struct clksel_rate usim_120m_rates[] = { 2363static const struct clksel_rate usim_120m_rates[] = {
2364 { .div = 4, .val = 7, .flags = RATE_IN_343X }, 2364 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2365 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 2365 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2366 { .div = 16, .val = 9, .flags = RATE_IN_343X }, 2366 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2367 { .div = 20, .val = 10, .flags = RATE_IN_343X }, 2367 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2368 { .div = 0 }, 2368 { .div = 0 },
2369}; 2369};
2370 2370
@@ -2951,22 +2951,22 @@ static struct clk mcbsp4_fck = {
2951/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ 2951/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2952 2952
2953static const struct clksel_rate emu_src_sys_rates[] = { 2953static const struct clksel_rate emu_src_sys_rates[] = {
2954 { .div = 1, .val = 0, .flags = RATE_IN_343X }, 2954 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2955 { .div = 0 }, 2955 { .div = 0 },
2956}; 2956};
2957 2957
2958static const struct clksel_rate emu_src_core_rates[] = { 2958static const struct clksel_rate emu_src_core_rates[] = {
2959 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 2959 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2960 { .div = 0 }, 2960 { .div = 0 },
2961}; 2961};
2962 2962
2963static const struct clksel_rate emu_src_per_rates[] = { 2963static const struct clksel_rate emu_src_per_rates[] = {
2964 { .div = 1, .val = 2, .flags = RATE_IN_343X }, 2964 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2965 { .div = 0 }, 2965 { .div = 0 },
2966}; 2966};
2967 2967
2968static const struct clksel_rate emu_src_mpu_rates[] = { 2968static const struct clksel_rate emu_src_mpu_rates[] = {
2969 { .div = 1, .val = 3, .flags = RATE_IN_343X }, 2969 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2970 { .div = 0 }, 2970 { .div = 0 },
2971}; 2971};
2972 2972
@@ -2995,10 +2995,10 @@ static struct clk emu_src_ck = {
2995}; 2995};
2996 2996
2997static const struct clksel_rate pclk_emu_rates[] = { 2997static const struct clksel_rate pclk_emu_rates[] = {
2998 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2998 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2999 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2999 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
3000 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 3000 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3001 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 3001 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
3002 { .div = 0 }, 3002 { .div = 0 },
3003}; 3003};
3004 3004
@@ -3019,9 +3019,9 @@ static struct clk pclk_fck = {
3019}; 3019};
3020 3020
3021static const struct clksel_rate pclkx2_emu_rates[] = { 3021static const struct clksel_rate pclkx2_emu_rates[] = {
3022 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 3022 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3023 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 3023 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3024 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 3024 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
3025 { .div = 0 }, 3025 { .div = 0 },
3026}; 3026};
3027 3027
@@ -3069,9 +3069,9 @@ static struct clk traceclk_src_fck = {
3069}; 3069};
3070 3070
3071static const struct clksel_rate traceclk_rates[] = { 3071static const struct clksel_rate traceclk_rates[] = {
3072 { .div = 1, .val = 1, .flags = RATE_IN_343X }, 3072 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3073 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 3073 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3074 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 3074 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3075 { .div = 0 }, 3075 { .div = 0 },
3076}; 3076};
3077 3077
@@ -3488,14 +3488,8 @@ int __init omap3xxx_clk_init(void)
3488 struct omap_clk *c; 3488 struct omap_clk *c;
3489 u32 cpu_clkflg = CK_3XXX; 3489 u32 cpu_clkflg = CK_3XXX;
3490 3490
3491 if (cpu_is_omap3517()) { 3491 if (cpu_is_omap34xx()) {
3492 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; 3492 cpu_mask = RATE_IN_3XXX;
3493 cpu_clkflg |= CK_3517;
3494 } else if (cpu_is_omap3505()) {
3495 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3496 cpu_clkflg |= CK_3505;
3497 } else if (cpu_is_omap34xx()) {
3498 cpu_mask = RATE_IN_343X;
3499 cpu_clkflg |= CK_343X; 3493 cpu_clkflg |= CK_343X;
3500 3494
3501 /* 3495 /*
@@ -3506,10 +3500,17 @@ int __init omap3xxx_clk_init(void)
3506 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 3500 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3507 cpu_clkflg |= CK_3430ES1; 3501 cpu_clkflg |= CK_3430ES1;
3508 } else { 3502 } else {
3509 cpu_mask |= RATE_IN_3430ES2; 3503 cpu_mask |= RATE_IN_3430ES2PLUS;
3510 cpu_clkflg |= CK_3430ES2; 3504 cpu_clkflg |= CK_3430ES2;
3511 } 3505 }
3506 } else if (cpu_is_omap3517()) {
3507 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3508 cpu_clkflg |= CK_3517;
3509 } else if (cpu_is_omap3505()) {
3510 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3511 cpu_clkflg |= CK_3505;
3512 } 3512 }
3513
3513 if (omap3_has_192mhz_clk()) 3514 if (omap3_has_192mhz_clk())
3514 omap_96m_alwon_fck = omap_96m_alwon_fck_3630; 3515 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3515 3516
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index 6f96dc4ef254..1cf8131205fa 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -20,20 +20,20 @@
20 20
21/* clksel_rate data common to 24xx/343x */ 21/* clksel_rate data common to 24xx/343x */
22const struct clksel_rate gpt_32k_rates[] = { 22const struct clksel_rate gpt_32k_rates[] = {
23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X }, 23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
24 { .div = 0 } 24 { .div = 0 }
25}; 25};
26 26
27const struct clksel_rate gpt_sys_rates[] = { 27const struct clksel_rate gpt_sys_rates[] = {
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, 28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
29 { .div = 0 } 29 { .div = 0 }
30}; 30};
31 31
32const struct clksel_rate gfx_l3_rates[] = { 32const struct clksel_rate gfx_l3_rates[] = {
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, 33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X }, 34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, 35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, 36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
37 { .div = 0 } 37 { .div = 0 }
38}; 38};
39 39
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 9c551d676c63..dfc472ca0cc4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -198,12 +198,13 @@ extern struct clk dummy_ck;
198/* Clksel_rate flags */ 198/* Clksel_rate flags */
199#define RATE_IN_242X (1 << 0) 199#define RATE_IN_242X (1 << 0)
200#define RATE_IN_243X (1 << 1) 200#define RATE_IN_243X (1 << 1)
201#define RATE_IN_343X (1 << 2) /* rates common to all 343X */ 201#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ 202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203#define RATE_IN_36XX (1 << 4) 203#define RATE_IN_36XX (1 << 4)
204#define RATE_IN_4430 (1 << 5) 204#define RATE_IN_4430 (1 << 5)
205 205
206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
207 207
208#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
208 209
209#endif 210#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 02:46:25 -0500