diff options
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b6f593a6d970..463f75330282 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -7325,6 +7325,19 @@ void ironlake_enable_rc6(struct drm_device *dev) | |||
7325 | OUT_RING(MI_FLUSH); | 7325 | OUT_RING(MI_FLUSH); |
7326 | ADVANCE_LP_RING(); | 7326 | ADVANCE_LP_RING(); |
7327 | 7327 | ||
7328 | /* | ||
7329 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | ||
7330 | * does an implicit flush, combined with MI_FLUSH above, it should be | ||
7331 | * safe to assume that renderctx is valid | ||
7332 | */ | ||
7333 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | ||
7334 | if (ret) { | ||
7335 | DRM_ERROR("failed to enable ironlake power power savings\n"); | ||
7336 | ironlake_teardown_rc6(dev); | ||
7337 | mutex_unlock(&dev->struct_mutex); | ||
7338 | return; | ||
7339 | } | ||
7340 | |||
7328 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); | 7341 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
7329 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | 7342 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
7330 | mutex_unlock(&dev->struct_mutex); | 7343 | mutex_unlock(&dev->struct_mutex); |