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-rw-r--r--drivers/mfd/asic3.c88
-rw-r--r--include/linux/mfd/asic3.h56
2 files changed, 72 insertions, 72 deletions
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index 1924eb01cc8c..9931581b08a1 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -55,8 +55,8 @@ static inline u32 asic3_read_register(struct asic3 *asic,
55 55
56/* IRQs */ 56/* IRQs */
57#define MAX_ASIC_ISR_LOOPS 20 57#define MAX_ASIC_ISR_LOOPS 20
58#define ASIC3_GPIO_Base_INCR \ 58#define ASIC3_GPIO_BASE_INCR \
59 (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base) 59 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
60 60
61static void asic3_irq_flip_edge(struct asic3 *asic, 61static void asic3_irq_flip_edge(struct asic3 *asic,
62 u32 base, int bit) 62 u32 base, int bit)
@@ -66,10 +66,10 @@ static void asic3_irq_flip_edge(struct asic3 *asic,
66 66
67 spin_lock_irqsave(&asic->lock, flags); 67 spin_lock_irqsave(&asic->lock, flags);
68 edge = asic3_read_register(asic, 68 edge = asic3_read_register(asic,
69 base + ASIC3_GPIO_EdgeTrigger); 69 base + ASIC3_GPIO_EDGE_TRIGGER);
70 edge ^= bit; 70 edge ^= bit;
71 asic3_write_register(asic, 71 asic3_write_register(asic,
72 base + ASIC3_GPIO_EdgeTrigger, edge); 72 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
73 spin_unlock_irqrestore(&asic->lock, flags); 73 spin_unlock_irqrestore(&asic->lock, flags);
74} 74}
75 75
@@ -89,7 +89,7 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
89 89
90 spin_lock_irqsave(&asic->lock, flags); 90 spin_lock_irqsave(&asic->lock, flags);
91 status = asic3_read_register(asic, 91 status = asic3_read_register(asic,
92 ASIC3_OFFSET(INTR, PIntStat)); 92 ASIC3_OFFSET(INTR, P_INT_STAT));
93 spin_unlock_irqrestore(&asic->lock, flags); 93 spin_unlock_irqrestore(&asic->lock, flags);
94 94
95 /* Check all ten register bits */ 95 /* Check all ten register bits */
@@ -101,17 +101,17 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
101 if (status & (1 << bank)) { 101 if (status & (1 << bank)) {
102 unsigned long base, istat; 102 unsigned long base, istat;
103 103
104 base = ASIC3_GPIO_A_Base 104 base = ASIC3_GPIO_A_BASE
105 + bank * ASIC3_GPIO_Base_INCR; 105 + bank * ASIC3_GPIO_BASE_INCR;
106 106
107 spin_lock_irqsave(&asic->lock, flags); 107 spin_lock_irqsave(&asic->lock, flags);
108 istat = asic3_read_register(asic, 108 istat = asic3_read_register(asic,
109 base + 109 base +
110 ASIC3_GPIO_IntStatus); 110 ASIC3_GPIO_INT_STATUS);
111 /* Clearing IntStatus */ 111 /* Clearing IntStatus */
112 asic3_write_register(asic, 112 asic3_write_register(asic,
113 base + 113 base +
114 ASIC3_GPIO_IntStatus, 0); 114 ASIC3_GPIO_INT_STATUS, 0);
115 spin_unlock_irqrestore(&asic->lock, flags); 115 spin_unlock_irqrestore(&asic->lock, flags);
116 116
117 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { 117 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
@@ -154,7 +154,7 @@ static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
154 154
155 n = (irq - asic->irq_base) >> 4; 155 n = (irq - asic->irq_base) >> 4;
156 156
157 return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)); 157 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
158} 158}
159 159
160static inline int asic3_irq_to_index(struct asic3 *asic, int irq) 160static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
@@ -172,9 +172,9 @@ static void asic3_mask_gpio_irq(unsigned int irq)
172 index = asic3_irq_to_index(asic, irq); 172 index = asic3_irq_to_index(asic, irq);
173 173
174 spin_lock_irqsave(&asic->lock, flags); 174 spin_lock_irqsave(&asic->lock, flags);
175 val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask); 175 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
176 val |= 1 << index; 176 val |= 1 << index;
177 asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val); 177 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
178 spin_unlock_irqrestore(&asic->lock, flags); 178 spin_unlock_irqrestore(&asic->lock, flags);
179} 179}
180 180
@@ -186,15 +186,15 @@ static void asic3_mask_irq(unsigned int irq)
186 186
187 spin_lock_irqsave(&asic->lock, flags); 187 spin_lock_irqsave(&asic->lock, flags);
188 regval = asic3_read_register(asic, 188 regval = asic3_read_register(asic,
189 ASIC3_INTR_Base + 189 ASIC3_INTR_BASE +
190 ASIC3_INTR_IntMask); 190 ASIC3_INTR_INT_MASK);
191 191
192 regval &= ~(ASIC3_INTMASK_MASK0 << 192 regval &= ~(ASIC3_INTMASK_MASK0 <<
193 (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); 193 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
194 194
195 asic3_write_register(asic, 195 asic3_write_register(asic,
196 ASIC3_INTR_Base + 196 ASIC3_INTR_BASE +
197 ASIC3_INTR_IntMask, 197 ASIC3_INTR_INT_MASK,
198 regval); 198 regval);
199 spin_unlock_irqrestore(&asic->lock, flags); 199 spin_unlock_irqrestore(&asic->lock, flags);
200} 200}
@@ -209,9 +209,9 @@ static void asic3_unmask_gpio_irq(unsigned int irq)
209 index = asic3_irq_to_index(asic, irq); 209 index = asic3_irq_to_index(asic, irq);
210 210
211 spin_lock_irqsave(&asic->lock, flags); 211 spin_lock_irqsave(&asic->lock, flags);
212 val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask); 212 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
213 val &= ~(1 << index); 213 val &= ~(1 << index);
214 asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val); 214 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
215 spin_unlock_irqrestore(&asic->lock, flags); 215 spin_unlock_irqrestore(&asic->lock, flags);
216} 216}
217 217
@@ -223,15 +223,15 @@ static void asic3_unmask_irq(unsigned int irq)
223 223
224 spin_lock_irqsave(&asic->lock, flags); 224 spin_lock_irqsave(&asic->lock, flags);
225 regval = asic3_read_register(asic, 225 regval = asic3_read_register(asic,
226 ASIC3_INTR_Base + 226 ASIC3_INTR_BASE +
227 ASIC3_INTR_IntMask); 227 ASIC3_INTR_INT_MASK);
228 228
229 regval |= (ASIC3_INTMASK_MASK0 << 229 regval |= (ASIC3_INTMASK_MASK0 <<
230 (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); 230 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
231 231
232 asic3_write_register(asic, 232 asic3_write_register(asic,
233 ASIC3_INTR_Base + 233 ASIC3_INTR_BASE +
234 ASIC3_INTR_IntMask, 234 ASIC3_INTR_INT_MASK,
235 regval); 235 regval);
236 spin_unlock_irqrestore(&asic->lock, flags); 236 spin_unlock_irqrestore(&asic->lock, flags);
237} 237}
@@ -249,11 +249,11 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
249 249
250 spin_lock_irqsave(&asic->lock, flags); 250 spin_lock_irqsave(&asic->lock, flags);
251 level = asic3_read_register(asic, 251 level = asic3_read_register(asic,
252 bank + ASIC3_GPIO_LevelTrigger); 252 bank + ASIC3_GPIO_LEVEL_TRIGGER);
253 edge = asic3_read_register(asic, 253 edge = asic3_read_register(asic,
254 bank + ASIC3_GPIO_EdgeTrigger); 254 bank + ASIC3_GPIO_EDGE_TRIGGER);
255 trigger = asic3_read_register(asic, 255 trigger = asic3_read_register(asic,
256 bank + ASIC3_GPIO_TriggerType); 256 bank + ASIC3_GPIO_TRIGGER_TYPE);
257 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit; 257 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
258 258
259 if (type == IRQT_RISING) { 259 if (type == IRQT_RISING) {
@@ -283,11 +283,11 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
283 */ 283 */
284 dev_notice(asic->dev, "irq type not changed\n"); 284 dev_notice(asic->dev, "irq type not changed\n");
285 } 285 }
286 asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger, 286 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
287 level); 287 level);
288 asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger, 288 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
289 edge); 289 edge);
290 asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType, 290 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
291 trigger); 291 trigger);
292 spin_unlock_irqrestore(&asic->lock, flags); 292 spin_unlock_irqrestore(&asic->lock, flags);
293 return 0; 293 return 0;
@@ -336,7 +336,7 @@ static int asic3_irq_probe(struct platform_device *pdev)
336 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 336 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
337 } 337 }
338 338
339 asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask), 339 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
340 ASIC3_INTMASK_GINTMASK); 340 ASIC3_INTMASK_GINTMASK);
341 341
342 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux); 342 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
@@ -374,7 +374,7 @@ static int asic3_gpio_direction(struct gpio_chip *chip,
374 asic = container_of(chip, struct asic3, gpio); 374 asic = container_of(chip, struct asic3, gpio);
375 gpio_base = ASIC3_GPIO_TO_BASE(offset); 375 gpio_base = ASIC3_GPIO_TO_BASE(offset);
376 376
377 if (gpio_base > ASIC3_GPIO_D_Base) { 377 if (gpio_base > ASIC3_GPIO_D_BASE) {
378 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", 378 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
379 gpio_base, offset); 379 gpio_base, offset);
380 return -EINVAL; 380 return -EINVAL;
@@ -382,7 +382,7 @@ static int asic3_gpio_direction(struct gpio_chip *chip,
382 382
383 spin_lock_irqsave(&asic->lock, flags); 383 spin_lock_irqsave(&asic->lock, flags);
384 384
385 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Direction); 385 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
386 386
387 /* Input is 0, Output is 1 */ 387 /* Input is 0, Output is 1 */
388 if (out) 388 if (out)
@@ -390,7 +390,7 @@ static int asic3_gpio_direction(struct gpio_chip *chip,
390 else 390 else
391 out_reg &= ~mask; 391 out_reg &= ~mask;
392 392
393 asic3_write_register(asic, gpio_base + ASIC3_GPIO_Direction, out_reg); 393 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
394 394
395 spin_unlock_irqrestore(&asic->lock, flags); 395 spin_unlock_irqrestore(&asic->lock, flags);
396 396
@@ -420,13 +420,13 @@ static int asic3_gpio_get(struct gpio_chip *chip,
420 asic = container_of(chip, struct asic3, gpio); 420 asic = container_of(chip, struct asic3, gpio);
421 gpio_base = ASIC3_GPIO_TO_BASE(offset); 421 gpio_base = ASIC3_GPIO_TO_BASE(offset);
422 422
423 if (gpio_base > ASIC3_GPIO_D_Base) { 423 if (gpio_base > ASIC3_GPIO_D_BASE) {
424 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", 424 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
425 gpio_base, offset); 425 gpio_base, offset);
426 return -EINVAL; 426 return -EINVAL;
427 } 427 }
428 428
429 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_Status) & mask; 429 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
430} 430}
431 431
432static void asic3_gpio_set(struct gpio_chip *chip, 432static void asic3_gpio_set(struct gpio_chip *chip,
@@ -440,7 +440,7 @@ static void asic3_gpio_set(struct gpio_chip *chip,
440 asic = container_of(chip, struct asic3, gpio); 440 asic = container_of(chip, struct asic3, gpio);
441 gpio_base = ASIC3_GPIO_TO_BASE(offset); 441 gpio_base = ASIC3_GPIO_TO_BASE(offset);
442 442
443 if (gpio_base > ASIC3_GPIO_D_Base) { 443 if (gpio_base > ASIC3_GPIO_D_BASE) {
444 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", 444 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
445 gpio_base, offset); 445 gpio_base, offset);
446 return; 446 return;
@@ -450,14 +450,14 @@ static void asic3_gpio_set(struct gpio_chip *chip,
450 450
451 spin_lock_irqsave(&asic->lock, flags); 451 spin_lock_irqsave(&asic->lock, flags);
452 452
453 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Out); 453 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
454 454
455 if (value) 455 if (value)
456 out_reg |= mask; 456 out_reg |= mask;
457 else 457 else
458 out_reg &= ~mask; 458 out_reg &= ~mask;
459 459
460 asic3_write_register(asic, gpio_base + ASIC3_GPIO_Out, out_reg); 460 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
461 461
462 spin_unlock_irqrestore(&asic->lock, flags); 462 spin_unlock_irqrestore(&asic->lock, flags);
463 463
@@ -478,10 +478,10 @@ static int asic3_gpio_probe(struct platform_device *pdev,
478 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS); 478 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS);
479 479
480 /* Enable all GPIOs */ 480 /* Enable all GPIOs */
481 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff); 481 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
482 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff); 482 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
483 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff); 483 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
484 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff); 484 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
485 485
486 for (i = 0; i < num; i++) { 486 for (i = 0; i < num; i++) {
487 u8 alt, pin, dir, init, bank_num, bit_num; 487 u8 alt, pin, dir, init, bank_num, bit_num;
@@ -503,14 +503,14 @@ static int asic3_gpio_probe(struct platform_device *pdev,
503 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) { 503 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
504 asic3_write_register(asic, 504 asic3_write_register(asic,
505 ASIC3_BANK_TO_BASE(i) + 505 ASIC3_BANK_TO_BASE(i) +
506 ASIC3_GPIO_Direction, 506 ASIC3_GPIO_DIRECTION,
507 dir_reg[i]); 507 dir_reg[i]);
508 asic3_write_register(asic, 508 asic3_write_register(asic,
509 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_Out, 509 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
510 out_reg[i]); 510 out_reg[i]);
511 asic3_write_register(asic, 511 asic3_write_register(asic,
512 ASIC3_BANK_TO_BASE(i) + 512 ASIC3_BANK_TO_BASE(i) +
513 ASIC3_GPIO_AltFunction, 513 ASIC3_GPIO_ALT_FUNCTION,
514 alt_reg[i]); 514 alt_reg[i]);
515 } 515 }
516 516
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index 7e47cfb0c440..6461a2ae69a2 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -45,39 +45,39 @@ struct asic3_platform_data {
45/* All offsets below are specified with this address bus shift */ 45/* All offsets below are specified with this address bus shift */
46#define ASIC3_DEFAULT_ADDR_SHIFT 2 46#define ASIC3_DEFAULT_ADDR_SHIFT 2
47 47
48#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg) 48#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
49#define ASIC3_GPIO_OFFSET(base, reg) \ 49#define ASIC3_GPIO_OFFSET(base, reg) \
50 (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg) 50 (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
51 51
52#define ASIC3_GPIO_A_Base 0x0000 52#define ASIC3_GPIO_A_BASE 0x0000
53#define ASIC3_GPIO_B_Base 0x0100 53#define ASIC3_GPIO_B_BASE 0x0100
54#define ASIC3_GPIO_C_Base 0x0200 54#define ASIC3_GPIO_C_BASE 0x0200
55#define ASIC3_GPIO_D_Base 0x0300 55#define ASIC3_GPIO_D_BASE 0x0300
56 56
57#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4) 57#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
58#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \ 58#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
59 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4))) 59 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
60#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio)) 60#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
61#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_Base + (((gpio) >> 4) * 0x0100)) 61#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
62#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_Base + ((bank) * 0x100)) 62#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
63 63
64#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */ 64#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
65#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */ 65#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
66#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */ 66#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
67#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */ 67#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
68#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */ 68#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
69#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */ 69#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
70#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */ 70#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
71#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */ 71#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
72#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */ 72#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
73#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */ 73#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
74#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */ 74#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
75#define ASIC3_GPIO_SleepConf 0x2c /* 75#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
76 * R/W bit 1: autosleep 76 * R/W bit 1: autosleep
77 * 0: disable gposlpout in normal mode, 77 * 0: disable gposlpout in normal mode,
78 * enable gposlpout in sleep mode. 78 * enable gposlpout in sleep mode.
79 */ 79 */
80#define ASIC3_GPIO_Status 0x30 /* R Pin status */ 80#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
81 81
82/* 82/*
83 * ASIC3 GPIO config 83 * ASIC3 GPIO config
@@ -137,7 +137,7 @@ struct asic3_platform_data {
137#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ 137#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
138#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ 138#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
139 139
140#define ASIC3_CLOCK_Base 0x0A00 140#define ASIC3_CLOCK_BASE 0x0A00
141#define ASIC3_CLOCK_CDEX 0x00 141#define ASIC3_CLOCK_CDEX 0x00
142#define ASIC3_CLOCK_SEL 0x04 142#define ASIC3_CLOCK_SEL 0x04
143 143
@@ -168,12 +168,12 @@ struct asic3_platform_data {
168#define CLOCK_SEL_CX (1 << 2) 168#define CLOCK_SEL_CX (1 << 2)
169 169
170 170
171#define ASIC3_INTR_Base 0x0B00 171#define ASIC3_INTR_BASE 0x0B00
172 172
173#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */ 173#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
174#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */ 174#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
175#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */ 175#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
176#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */ 176#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
177 177
178#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ 178#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
179#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ 179#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */