8 files changed, 35 insertions, 36 deletions

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3601466c5502..c31e818f8b08 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -544,11 +544,11 @@ static int i915_hws_info(struct seq_file *m, void *data)
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
         struct intel_ring_buffer *ring;
-        volatile u32 *hws;
+        const volatile u32 __iomem *hws;
         int i;
 
         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
-        hws = (volatile u32 *)ring->status_page.page_addr;
+        hws = (volatile u32 __iomem *)ring->status_page.page_addr;
         if (hws == NULL)
                 return 0;
 
@@ -615,7 +615,7 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data)
         if (!ring->obj) {
                 seq_printf(m, "No ringbuffer setup\n");
         } else {
-                u8 *virt = ring->virtual_start;
+                const u8 __iomem *virt = ring->virtual_start;
                 uint32_t off;
 
                 for (off = 0; off < ring->size; off += 4) {
@@ -1259,7 +1259,7 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
 }
 
 static struct drm_info_list i915_debugfs_list[] = {
-        {"i915_capabilities", i915_capabilities, 0, 0},
+        {"i915_capabilities", i915_capabilities, 0},
         {"i915_gem_objects", i915_gem_object_info, 0},
         {"i915_gem_gtt", i915_gem_gtt_info, 0},
         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 844f3c972b04..76f2df7b712d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -60,10 +60,11 @@ static int i915_init_phys_hws(struct drm_device *dev)
                 DRM_ERROR("Can not allocate hardware status page\n");
                 return -ENOMEM;
         }
-        ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
+        ring->status_page.page_addr =
+                (void __force __iomem *)dev_priv->status_page_dmah->vaddr;
         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 
-        memset(ring->status_page.page_addr, 0, PAGE_SIZE);
+        memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
 
         if (INTEL_INFO(dev)->gen >= 4)
                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
@@ -188,7 +189,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
                 }
         }
 
-        ring->virtual_start = ring->map.handle;
+        ring->virtual_start = (void __force __iomem *)ring->map.handle;
 
         dev_priv->cpp = init->cpp;
         dev_priv->back_offset = init->back_offset;
@@ -870,8 +871,9 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
                                 " G33 hw status page\n");
                 return -ENOMEM;
         }
-        ring->status_page.page_addr = dev_priv->hws_map.handle;
-        memset(ring->status_page.page_addr, 0, PAGE_SIZE);
+        ring->status_page.page_addr =
+                (void __force __iomem *)dev_priv->hws_map.handle;
+        memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 
         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 72fea2bcfc4f..2d31f5fd08f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -52,7 +52,7 @@ module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 unsigned int i915_panel_use_ssc = 1;
 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
 
-bool i915_try_reset = true;
+static bool i915_try_reset = true;
 module_param_named(reset, i915_try_reset, bool, 0600);
 
 static struct drm_driver driver;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b9a771110a4..eaec56ef12b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1392,25 +1392,4 @@ i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
        }
 }
 
-/**
- * Reads a dword out of the status page, which is written to from the command
- * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
- * MI_STORE_DATA_IMM.
- *
- * The following dwords have a reserved meaning:
- * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
- * 0x04: ring 0 head pointer
- * 0x05: ring 1 head pointer (915-class)
- * 0x06: ring 2 head pointer (915-class)
- * 0x10-0x1b: Context status DWords (GM45)
- * 0x1f: Last written status offset. (GM45)
- *
- * The area from dword 0x20 to 0x3ff is available for driver usage.
- */
-#define READ_HWSP(dev_priv, reg)  (((volatile u32 *)\
-                        (LP_RING(dev_priv)->status_page.page_addr))[reg])
-#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
-#define I915_GEM_HWS_INDEX              0x20
-#define I915_BREADCRUMB_INDEX           0x21
-
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index dcfdf4151b6d..94b80acfe6ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -690,8 +690,6 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
         /* reacquire the objects */
         eb_reset(eb);
         for (i = 0; i < count; i++) {
-                struct drm_i915_gem_object *obj;
-
                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
                                                         exec[i].handle));
                 if (obj == NULL) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fe8454a48eab..cb9d547aa42b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2327,7 +2327,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 
 }
 
-static const int const snb_b_fdi_train_param [] = {
+static const int snb_b_fdi_train_param [] = {
         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index fc6a0a9297c7..3eec52a0b8e6 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -503,7 +503,7 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
                 return drm_add_edid_modes(connector, intel_lvds->edid);
 
         mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
-        if (mode == 0)
+        if (mode == NULL)
                 return 0;
 
         drm_mode_probed_add(connector, mode);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index be9087e4c9be..d5911aa06597 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -43,7 +43,7 @@ struct  intel_ring_buffer {
                 RING_BLT = 0x4,
         } id;
         u32             mmio_base;
-        void            *virtual_start;
+        void            __iomem *virtual_start;
         struct          drm_device *dev;
         struct          drm_i915_gem_object *obj;
 
@@ -142,6 +142,26 @@ intel_read_status_page(struct intel_ring_buffer *ring,
         return ioread32(ring->status_page.page_addr + reg);
 }
 
+/**
+ * Reads a dword out of the status page, which is written to from the command
+ * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
+ * MI_STORE_DATA_IMM.
+ *
+ * The following dwords have a reserved meaning:
+ * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
+ * 0x04: ring 0 head pointer
+ * 0x05: ring 1 head pointer (915-class)
+ * 0x06: ring 2 head pointer (915-class)
+ * 0x10-0x1b: Context status DWords (GM45)
+ * 0x1f: Last written status offset. (GM45)
+ *
+ * The area from dword 0x20 to 0x3ff is available for driver usage.
+ */
+#define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
+#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
+#define I915_GEM_HWS_INDEX              0x20
+#define I915_BREADCRUMB_INDEX           0x21
+
 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);