8 files changed, 99 insertions, 89 deletions

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 96cd256e60e6..cbd911837b08 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -159,7 +159,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
 
         dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
 
-        DRM_DEBUG("Found panel mode in BIOS VBT tables:\n");
+        DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
         drm_mode_debug_printmodeline(panel_fixed_mode);
 
         return;
@@ -250,13 +250,13 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
                 u16 block_size = get_blocksize(general);
                 if (block_size >= sizeof(*general)) {
                         int bus_pin = general->crt_ddc_gmbus_pin;
-                        DRM_DEBUG("crt_ddc_bus_pin: %d\n", bus_pin);
+                        DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
                         if ((bus_pin >= 1) && (bus_pin <= 6)) {
                                 dev_priv->crt_ddc_bus =
                                         crt_bus_map_table[bus_pin-1];
                         }
                 } else {
-                        DRM_DEBUG("BDB_GD too small (%d). Invalid.\n",
+                        DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
                                   block_size);
                 }
         }
@@ -274,7 +274,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
 
         p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
         if (!p_defs) {
-                DRM_DEBUG("No general definition block is found\n");
+                DRM_DEBUG_KMS("No general definition block is found\n");
                 return;
         }
         /* judge whether the size of child device meets the requirements.
@@ -284,7 +284,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
          */
         if (p_defs->child_dev_size != sizeof(*p_child)) {
                 /* different child dev size . Ignore it */
-                DRM_DEBUG("different child size is found. Invalid.\n");
+                DRM_DEBUG_KMS("different child size is found. Invalid.\n");
                 return;
         }
         /* get the block size of general definitions */
@@ -310,11 +310,11 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
                 if (p_child->dvo_port != DEVICE_PORT_DVOB &&
                         p_child->dvo_port != DEVICE_PORT_DVOC) {
                         /* skip the incorrect SDVO port */
-                        DRM_DEBUG("Incorrect SDVO port. Skip it \n");
+                        DRM_DEBUG_KMS("Incorrect SDVO port. Skip it \n");
                         continue;
                 }
-                DRM_DEBUG("the SDVO device with slave addr %2x is found on "
-                                "%s port\n",
+                DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
+                                " %s port\n",
                                 p_child->slave_addr,
                                 (p_child->dvo_port == DEVICE_PORT_DVOB) ?
                                         "SDVOB" : "SDVOC");
@@ -325,21 +325,21 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
                         p_mapping->dvo_wiring = p_child->dvo_wiring;
                         p_mapping->initialized = 1;
                 } else {
-                        DRM_DEBUG("Maybe one SDVO port is shared by "
+                        DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
                                          "two SDVO device.\n");
                 }
                 if (p_child->slave2_addr) {
                         /* Maybe this is a SDVO device with multiple inputs */
                         /* And the mapping info is not added */
-                        DRM_DEBUG("there exists the slave2_addr. Maybe this "
-                                "is a SDVO device with multiple inputs.\n");
+                        DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
+                                " is a SDVO device with multiple inputs.\n");
                 }
                 count++;
         }
 
         if (!count) {
                 /* No SDVO device info is found */
-                DRM_DEBUG("No SDVO device info is found in VBT\n");
+                DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
         }
         return;
 }
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 212e22740fc1..9b48a4465c38 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -194,7 +194,7 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
                         ADPA_CRT_HOTPLUG_ENABLE |
                         ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
 
-        DRM_DEBUG("pch crt adpa 0x%x", adpa);
+        DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
         I915_WRITE(PCH_ADPA, adpa);
 
         while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 062c1d7cdace..8df81401c149 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -994,7 +994,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
                 fbc_ctl |= dev_priv->cfb_fence;
         I915_WRITE(FBC_CONTROL, fbc_ctl);
 
-        DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
+        DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
 }
 
@@ -1017,7 +1017,7 @@ void i8xx_disable_fbc(struct drm_device *dev)
 
         intel_wait_for_vblank(dev);
 
-        DRM_DEBUG("disabled FBC\n");
+        DRM_DEBUG_KMS("disabled FBC\n");
 }
 
 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
@@ -1062,7 +1062,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
         /* enable it... */
         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 
-        DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
+        DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 }
 
 void g4x_disable_fbc(struct drm_device *dev)
@@ -1076,7 +1076,7 @@ void g4x_disable_fbc(struct drm_device *dev)
         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
         intel_wait_for_vblank(dev);
 
-        DRM_DEBUG("disabled FBC\n");
+        DRM_DEBUG_KMS("disabled FBC\n");
 }
 
 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
@@ -1141,25 +1141,27 @@ static void intel_update_fbc(struct drm_crtc *crtc,
          *   - going to an unsupported config (interlace, pixel multiply, etc.)
          */
         if (intel_fb->obj->size > dev_priv->cfb_size) {
-                DRM_DEBUG("framebuffer too large, disabling compression\n");
+                DRM_DEBUG_KMS("framebuffer too large, disabling "
+                                "compression\n");
                 goto out_disable;
         }
         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
-                DRM_DEBUG("mode incompatible with compression, disabling\n");
+                DRM_DEBUG_KMS("mode incompatible with compression, "
+                                "disabling\n");
                 goto out_disable;
         }
         if ((mode->hdisplay > 2048) ||
             (mode->vdisplay > 1536)) {
-                DRM_DEBUG("mode too large for compression, disabling\n");
+                DRM_DEBUG_KMS("mode too large for compression, disabling\n");
                 goto out_disable;
         }
         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
-                DRM_DEBUG("plane not 0, disabling compression\n");
+                DRM_DEBUG_KMS("plane not 0, disabling compression\n");
                 goto out_disable;
         }
         if (obj_priv->tiling_mode != I915_TILING_X) {
-                DRM_DEBUG("framebuffer not tiled, disabling compression\n");
+                DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
                 goto out_disable;
         }
 
@@ -1181,7 +1183,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         return;
 
 out_disable:
-        DRM_DEBUG("unsupported config, disabling FBC\n");
+        DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
         /* Multiple disables should be harmless */
         if (dev_priv->display.fbc_enabled(crtc))
                 dev_priv->display.disable_fbc(dev);
@@ -1211,7 +1213,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 
         /* no fb bound */
         if (!crtc->fb) {
-                DRM_DEBUG("No FB bound\n");
+                DRM_DEBUG_KMS("No FB bound\n");
                 return 0;
         }
 
@@ -1311,7 +1313,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         Start = obj_priv->gtt_offset;
         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 
-        DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
         I915_WRITE(dspstride, crtc->fb->pitch);
         if (IS_I965G(dev)) {
                 I915_WRITE(dspbase, Offset);
@@ -1385,7 +1387,7 @@ static void igdng_disable_pll_edp (struct drm_crtc *crtc)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 dpa_ctl;
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_KMS("\n");
         dpa_ctl = I915_READ(DP_A);
         dpa_ctl &= ~DP_PLL_ENABLE;
         I915_WRITE(DP_A, dpa_ctl);
@@ -1410,7 +1412,7 @@ static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 dpa_ctl;
 
-        DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
+        DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
         dpa_ctl = I915_READ(DP_A);
         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 
@@ -1481,7 +1483,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
         case DRM_MODE_DPMS_ON:
         case DRM_MODE_DPMS_STANDBY:
         case DRM_MODE_DPMS_SUSPEND:
-                DRM_DEBUG("crtc %d dpms on\n", pipe);
+                DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
                 if (HAS_eDP) {
                         /* enable eDP PLL */
                         igdng_enable_pll_edp(crtc);
@@ -1568,12 +1570,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                         udelay(150);
 
                         temp = I915_READ(fdi_rx_iir_reg);
-                        DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 
                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
                                 for (j = 0; j < tries; j++) {
                                         temp = I915_READ(fdi_rx_iir_reg);
-                                        DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
+                                                                temp);
                                         if (temp & FDI_RX_BIT_LOCK)
                                                 break;
                                         udelay(200);
@@ -1582,11 +1585,11 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                                         I915_WRITE(fdi_rx_iir_reg,
                                                         temp | FDI_RX_BIT_LOCK);
                                 else
-                                        DRM_DEBUG("train 1 fail\n");
+                                        DRM_DEBUG_KMS("train 1 fail\n");
                         } else {
                                 I915_WRITE(fdi_rx_iir_reg,
                                                 temp | FDI_RX_BIT_LOCK);
-                                DRM_DEBUG("train 1 ok 2!\n");
+                                DRM_DEBUG_KMS("train 1 ok 2!\n");
                         }
                         temp = I915_READ(fdi_tx_reg);
                         temp &= ~FDI_LINK_TRAIN_NONE;
@@ -1601,12 +1604,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                         udelay(150);
 
                         temp = I915_READ(fdi_rx_iir_reg);
-                        DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 
                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
                                 for (j = 0; j < tries; j++) {
                                         temp = I915_READ(fdi_rx_iir_reg);
-                                        DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
+                                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
+                                                                temp);
                                         if (temp & FDI_RX_SYMBOL_LOCK)
                                                 break;
                                         udelay(200);
@@ -1614,15 +1618,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                                 if (j != tries) {
                                         I915_WRITE(fdi_rx_iir_reg,
                                                         temp | FDI_RX_SYMBOL_LOCK);
-                                        DRM_DEBUG("train 2 ok 1!\n");
+                                        DRM_DEBUG_KMS("train 2 ok 1!\n");
                                 } else
-                                        DRM_DEBUG("train 2 fail\n");
+                                        DRM_DEBUG_KMS("train 2 fail\n");
                         } else {
                                 I915_WRITE(fdi_rx_iir_reg,
                                                 temp | FDI_RX_SYMBOL_LOCK);
-                                DRM_DEBUG("train 2 ok 2!\n");
+                                DRM_DEBUG_KMS("train 2 ok 2!\n");
                         }
-                        DRM_DEBUG("train done\n");
+                        DRM_DEBUG_KMS("train done\n");
 
                         /* set transcoder timing */
                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1664,7 +1668,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 
         break;
         case DRM_MODE_DPMS_OFF:
-                DRM_DEBUG("crtc %d dpms off\n", pipe);
+                DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
 
                 i915_disable_vga(dev);
 
@@ -1690,12 +1694,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                                         udelay(500);
                                         continue;
                                 } else {
-                                        DRM_DEBUG("pipe %d off delay\n", pipe);
+                                        DRM_DEBUG_KMS("pipe %d off delay\n",
+                                                                pipe);
                                         break;
                                 }
                         }
                 } else
-                        DRM_DEBUG("crtc %d is disabled\n", pipe);
+                        DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 
                 if (HAS_eDP) {
                         igdng_disable_pll_edp(crtc);
@@ -1738,7 +1743,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                                         udelay(500);
                                         continue;
                                 } else {
-                                        DRM_DEBUG("transcoder %d off delay\n", pipe);
+                                        DRM_DEBUG_KMS("transcoder %d off "
+                                                        "delay\n", pipe);
                                         break;
                                 }
                         }
@@ -2245,11 +2251,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
                 1000;
         entries_required /= wm->cacheline_size;
 
-        DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
+        DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
 
         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
 
-        DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
+        DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 
         /* Don't promote wm_size to unsigned... */
         if (wm_size > (long)wm->max_wm)
@@ -2311,7 +2317,7 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
                         return latency;
         }
 
-        DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
+        DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 
         return NULL;
 }
@@ -2339,7 +2345,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
                 dev_priv->mem_freq);
         if (!latency) {
-                DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
+                DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
                 igd_disable_cxsr(dev);
                 return;
         }
@@ -2351,7 +2357,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
         reg &= 0x7fffff;
         reg |= wm << 23;
         I915_WRITE(DSPFW1, reg);
-        DRM_DEBUG("DSPFW1 register is %x\n", reg);
+        DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 
         /* cursor SR */
         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
@@ -2376,7 +2382,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
         reg &= ~(0x3f << 16);
         reg |= (wm & 0x3f) << 16;
         I915_WRITE(DSPFW3, reg);
-        DRM_DEBUG("DSPFW3 register is %x\n", reg);
+        DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 
         /* activate cxsr */
         reg = I915_READ(DSPFW3);
@@ -2416,8 +2422,8 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
                         (dsparb & 0x7f);
 
-        DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
-                  size);
+        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
+                        plane ? "B" : "A", size);
 
         return size;
 }
@@ -2435,8 +2441,8 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
                         (dsparb & 0x1ff);
         size >>= 1; /* Convert to cachelines */
 
-        DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
-                  size);
+        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
+                        plane ? "B" : "A", size);
 
         return size;
 }
@@ -2450,7 +2456,8 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
         size = dsparb & 0x7f;
         size >>= 2; /* Convert to cachelines */
 
-        DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
+        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
+                        plane ? "B" : "A",
                   size);
 
         return size;
@@ -2465,8 +2472,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
         size = dsparb & 0x7f;
         size >>= 1; /* Convert to cachelines */
 
-        DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
-                  size);
+        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
+                        plane ? "B" : "A", size);
 
         return size;
 }
@@ -2546,7 +2553,7 @@ static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
+        DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
 
         /* 965 has limitations... */
         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
@@ -2585,7 +2592,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
                                        pixel_size, latency_ns);
         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
                                        pixel_size, latency_ns);
-        DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
+        DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
         /*
          * Overlay gets an aggressive default since video jitter is bad.
@@ -2605,14 +2612,14 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
                               pixel_size * sr_hdisplay) / 1000;
                 sr_entries = roundup(sr_entries / cacheline_size, 1);
-                DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+                DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
                 srwm = total_size - sr_entries;
                 if (srwm < 0)
                         srwm = 1;
                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
         }
 
-        DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
+        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
                   planea_wm, planeb_wm, cwm, srwm);
 
         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
@@ -2639,7 +2646,7 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
                                        pixel_size, latency_ns);
         fwater_lo |= (3<<8) | planea_wm;
 
-        DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
+        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
 
         I915_WRITE(FW_BLC, fwater_lo);
 }
@@ -2693,11 +2700,11 @@ static void intel_update_watermarks(struct drm_device *dev)
                 if (crtc->enabled) {
                         enabled++;
                         if (intel_crtc->plane == 0) {
-                                DRM_DEBUG("plane A (pipe %d) clock: %d\n",
+                                DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
                                           intel_crtc->pipe, crtc->mode.clock);
                                 planea_clock = crtc->mode.clock;
                         } else {
-                                DRM_DEBUG("plane B (pipe %d) clock: %d\n",
+                                DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
                                           intel_crtc->pipe, crtc->mode.clock);
                                 planeb_clock = crtc->mode.clock;
                         }
@@ -2811,7 +2818,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
                 refclk = dev_priv->lvds_ssc_freq * 1000;
-                DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
+                DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
+                                        refclk / 1000);
         } else if (IS_I9XX(dev)) {
                 refclk = 96000;
                 if (IS_IGDNG(dev))
@@ -3069,7 +3077,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
                 I915_WRITE(PFIT_CONTROL, 0);
 
-        DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+        DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
         drm_mode_debug_printmodeline(mode);
 
         /* assign to IGDNG registers */
@@ -3147,14 +3155,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 I915_WRITE(fp_reg + 4, fp2);
                 intel_crtc->lowfreq_avail = true;
                 if (HAS_PIPE_CXSR(dev)) {
-                        DRM_DEBUG("enabling CxSR downclocking\n");
+                        DRM_DEBUG_KMS("enabling CxSR downclocking\n");
                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
                 }
         } else {
                 I915_WRITE(fp_reg + 4, fp);
                 intel_crtc->lowfreq_avail = false;
                 if (HAS_PIPE_CXSR(dev)) {
-                        DRM_DEBUG("disabling CxSR downclocking\n");
+                        DRM_DEBUG_KMS("disabling CxSR downclocking\n");
                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
                 }
         }
@@ -3266,11 +3274,11 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
         size_t addr;
         int ret;
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_KMS("\n");
 
         /* if we want to turn off the cursor ignore width and height */
         if (!handle) {
-                DRM_DEBUG("cursor off\n");
+                DRM_DEBUG_KMS("cursor off\n");
                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
                         temp |= CURSOR_MODE_DISABLE;
@@ -3604,7 +3612,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
                                 7 : 14;
                         break;
                 default:
-                        DRM_DEBUG("Unknown DPLL mode %08x in programmed "
+                        DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
                         return 0;
                 }
@@ -4042,7 +4050,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
         intel_crtc->pipe = pipe;
         intel_crtc->plane = pipe;
         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
-                DRM_DEBUG("swapping pipes & planes for FBC\n");
+                DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
         }
 
@@ -4471,7 +4479,7 @@ void intel_modeset_init(struct drm_device *dev)
                 num_pipe = 2;
         else
                 num_pipe = 1;
-        DRM_DEBUG("%d display pipe%s available.\n",
+        DRM_DEBUG_KMS("%d display pipe%s available.\n",
                   num_pipe, num_pipe > 1 ? "s" : "");
 
         if (IS_I85X(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d83447557f9b..fcab9dee93da 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -282,7 +282,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
         /* Timeouts occur when the device isn't connected, so they're
          * "normal" -- don't fill the kernel log with these */
         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
-                DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status);
+                DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
                 return -ETIMEDOUT;
         }
 
@@ -435,7 +435,8 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                                 dp_priv->link_bw = bws[clock];
                                 dp_priv->lane_count = lane_count;
                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
-                                DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
+                                DRM_DEBUG_KMS("Display port link bw %02x lane "
+                                                "count %d clock %d\n",
                                        dp_priv->link_bw, dp_priv->lane_count,
                                        adjusted_mode->clock);
                                 return true;
@@ -611,7 +612,7 @@ static void igdng_edp_backlight_on (struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 pp;
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_KMS("\n");
         pp = I915_READ(PCH_PP_CONTROL);
         pp |= EDP_BLC_ENABLE;
         I915_WRITE(PCH_PP_CONTROL, pp);
@@ -622,7 +623,7 @@ static void igdng_edp_backlight_off (struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 pp;
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_KMS("\n");
         pp = I915_READ(PCH_PP_CONTROL);
         pp &= ~EDP_BLC_ENABLE;
         I915_WRITE(PCH_PP_CONTROL, pp);
@@ -1010,7 +1011,7 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_KMS("\n");
 
         if (IS_eDP(intel_output)) {
                 DP &= ~DP_PLL_ENABLE;
diff --git a/drivers/gpu/drm/i915/intel_dp_i2c.c b/drivers/gpu/drm/i915/intel_dp_i2c.c
index a63b6f57d2d4..a57273ade677 100644
--- a/drivers/gpu/drm/i915/intel_dp_i2c.c
+++ b/drivers/gpu/drm/i915/intel_dp_i2c.c
@@ -85,7 +85,7 @@ i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
                                            msg, msg_bytes,
                                            reply, reply_bytes);
                 if (ret < 0) {
-                        DRM_DEBUG("aux_ch failed %d\n", ret);
+                        DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
                         return ret;
                 }
                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
@@ -95,10 +95,10 @@ i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
                         }
                         return reply_bytes - 1;
                 case AUX_I2C_REPLY_NACK:
-                        DRM_DEBUG("aux_ch nack\n");
+                        DRM_DEBUG_KMS("aux_ch nack\n");
                         return -EREMOTEIO;
                 case AUX_I2C_REPLY_DEFER:
-                        DRM_DEBUG("aux_ch defer\n");
+                        DRM_DEBUG_KMS("aux_ch defer\n");
                         udelay(100);
                         break;
                 default:
@@ -224,7 +224,7 @@ i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
         if (ret >= 0)
                 ret = num;
         i2c_algo_dp_aux_stop(adapter, reading);
-        DRM_DEBUG("dp_aux_xfer return %d\n", ret);
+        DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
         return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 2b0fe54cd92c..d4823cc87895 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -230,8 +230,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
         par->intel_fb = intel_fb;
 
         /* To allow resizeing without swapping buffers */
-        DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width,
-                  intel_fb->base.height, obj_priv->gtt_offset, fbo);
+        DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08x, bo %p\n",
+                        intel_fb->base.width, intel_fb->base.height,
+                        obj_priv->gtt_offset, fbo);
 
         mutex_unlock(&dev->struct_mutex);
         return 0;
@@ -249,7 +250,7 @@ int intelfb_probe(struct drm_device *dev)
 {
         int ret;
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_KMS("\n");
         ret = drm_fb_helper_single_fb_probe(dev, 32, intelfb_create);
         return ret;
 }
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 05598ae10c4b..b1e3af792cf9 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -950,7 +950,7 @@ void intel_lvds_init(struct drm_device *dev)
                 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
                         return;
                 if (dev_priv->edp_support) {
-                        DRM_DEBUG("disable LVDS for eDP support\n");
+                        DRM_DEBUG_KMS("disable LVDS for eDP support\n");
                         return;
                 }
                 gpio = PCH_GPIOC;
@@ -1082,7 +1082,7 @@ out:
         }
         dev_priv->lid_notifier.notifier_call = intel_lid_notify;
         if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
-                DRM_DEBUG("lid notifier registration failed\n");
+                DRM_DEBUG_KMS("lid notifier registration failed\n");
                 dev_priv->lid_notifier.notifier_call = NULL;
         }
         drm_sysfs_connector_add(connector);
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 9ca917931afb..a0e4bc47b0f7 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1416,16 +1416,16 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
          *  0 0 0 Component
          */
         if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
-                DRM_DEBUG("Detected Composite TV connection\n");
+                DRM_DEBUG_KMS("Detected Composite TV connection\n");
                 type = DRM_MODE_CONNECTOR_Composite;
         } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
-                DRM_DEBUG("Detected S-Video TV connection\n");
+                DRM_DEBUG_KMS("Detected S-Video TV connection\n");
                 type = DRM_MODE_CONNECTOR_SVIDEO;
         } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
-                DRM_DEBUG("Detected Component TV connection\n");
+                DRM_DEBUG_KMS("Detected Component TV connection\n");
                 type = DRM_MODE_CONNECTOR_Component;
         } else {
-                DRM_DEBUG("No TV connection detected\n");
+                DRM_DEBUG_KMS("No TV connection detected\n");
                 type = -1;
         }