diff options
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 27 |
1 files changed, 17 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9e80020ae2fe..cba51c2b512f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4060,18 +4060,17 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) | |||
4060 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | 4060 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4061 | return; | 4061 | return; |
4062 | 4062 | ||
4063 | if (IS_I945G(dev) || IS_I945GM(dev)) { | 4063 | if (!dev_priv->busy) { |
4064 | u32 fw_blc_self; | 4064 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
4065 | 4065 | u32 fw_blc_self; | |
4066 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | ||
4067 | fw_blc_self = I915_READ(FW_BLC_SELF); | ||
4068 | fw_blc_self &= ~FW_BLC_SELF_EN; | ||
4069 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | ||
4070 | } | ||
4071 | 4066 | ||
4072 | if (!dev_priv->busy) | 4067 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
4068 | fw_blc_self = I915_READ(FW_BLC_SELF); | ||
4069 | fw_blc_self &= ~FW_BLC_SELF_EN; | ||
4070 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | ||
4071 | } | ||
4073 | dev_priv->busy = true; | 4072 | dev_priv->busy = true; |
4074 | else | 4073 | } else |
4075 | mod_timer(&dev_priv->idle_timer, jiffies + | 4074 | mod_timer(&dev_priv->idle_timer, jiffies + |
4076 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | 4075 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
4077 | 4076 | ||
@@ -4083,6 +4082,14 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) | |||
4083 | intel_fb = to_intel_framebuffer(crtc->fb); | 4082 | intel_fb = to_intel_framebuffer(crtc->fb); |
4084 | if (intel_fb->obj == obj) { | 4083 | if (intel_fb->obj == obj) { |
4085 | if (!intel_crtc->busy) { | 4084 | if (!intel_crtc->busy) { |
4085 | if (IS_I945G(dev) || IS_I945GM(dev)) { | ||
4086 | u32 fw_blc_self; | ||
4087 | |||
4088 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | ||
4089 | fw_blc_self = I915_READ(FW_BLC_SELF); | ||
4090 | fw_blc_self &= ~FW_BLC_SELF_EN; | ||
4091 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | ||
4092 | } | ||
4086 | /* Non-busy -> busy, upclock */ | 4093 | /* Non-busy -> busy, upclock */ |
4087 | intel_increase_pllclock(crtc, true); | 4094 | intel_increase_pllclock(crtc, true); |
4088 | intel_crtc->busy = true; | 4095 | intel_crtc->busy = true; |