diff options
| -rw-r--r-- | drivers/infiniband/hw/amso1100/c2_cq.c | 4 | ||||
| -rw-r--r-- | drivers/infiniband/hw/cxgb3/cxio_wr.h | 2 | ||||
| -rw-r--r-- | drivers/infiniband/hw/cxgb3/iwch_provider.c | 32 | ||||
| -rw-r--r-- | drivers/infiniband/hw/ehca/ehca_irq.c | 9 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mlx4/qp.c | 4 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_cmd.c | 2 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_dev.h | 1 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_eq.c | 4 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_main.c | 17 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_mr.c | 16 | ||||
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_profile.c | 4 | ||||
| -rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.c | 14 | ||||
| -rw-r--r-- | drivers/net/mlx4/eq.c | 4 | ||||
| -rw-r--r-- | drivers/net/mlx4/main.c | 14 | ||||
| -rw-r--r-- | drivers/net/mlx4/mr.c | 6 | ||||
| -rw-r--r-- | drivers/net/mlx4/profile.c | 2 | ||||
| -rw-r--r-- | include/linux/mlx4/device.h | 1 | ||||
| -rw-r--r-- | include/linux/mlx4/qp.h | 1 |
18 files changed, 98 insertions, 39 deletions
diff --git a/drivers/infiniband/hw/amso1100/c2_cq.c b/drivers/infiniband/hw/amso1100/c2_cq.c index bb17cce3cb59..f5c45b194f53 100644 --- a/drivers/infiniband/hw/amso1100/c2_cq.c +++ b/drivers/infiniband/hw/amso1100/c2_cq.c | |||
| @@ -133,7 +133,7 @@ static inline int c2_poll_one(struct c2_dev *c2dev, | |||
| 133 | struct c2_qp *qp; | 133 | struct c2_qp *qp; |
| 134 | int is_recv = 0; | 134 | int is_recv = 0; |
| 135 | 135 | ||
| 136 | ce = (struct c2wr_ce *) c2_mq_consume(&cq->mq); | 136 | ce = c2_mq_consume(&cq->mq); |
| 137 | if (!ce) { | 137 | if (!ce) { |
| 138 | return -EAGAIN; | 138 | return -EAGAIN; |
| 139 | } | 139 | } |
| @@ -146,7 +146,7 @@ static inline int c2_poll_one(struct c2_dev *c2dev, | |||
| 146 | while ((qp = | 146 | while ((qp = |
| 147 | (struct c2_qp *) (unsigned long) ce->qp_user_context) == NULL) { | 147 | (struct c2_qp *) (unsigned long) ce->qp_user_context) == NULL) { |
| 148 | c2_mq_free(&cq->mq); | 148 | c2_mq_free(&cq->mq); |
| 149 | ce = (struct c2wr_ce *) c2_mq_consume(&cq->mq); | 149 | ce = c2_mq_consume(&cq->mq); |
| 150 | if (!ce) | 150 | if (!ce) |
| 151 | return -EAGAIN; | 151 | return -EAGAIN; |
| 152 | } | 152 | } |
diff --git a/drivers/infiniband/hw/cxgb3/cxio_wr.h b/drivers/infiniband/hw/cxgb3/cxio_wr.h index ff9be1a13106..32e3b1461d81 100644 --- a/drivers/infiniband/hw/cxgb3/cxio_wr.h +++ b/drivers/infiniband/hw/cxgb3/cxio_wr.h | |||
| @@ -176,7 +176,7 @@ struct t3_send_wr { | |||
| 176 | struct t3_sge sgl[T3_MAX_SGE]; /* 4+ */ | 176 | struct t3_sge sgl[T3_MAX_SGE]; /* 4+ */ |
| 177 | }; | 177 | }; |
| 178 | 178 | ||
| 179 | #define T3_MAX_FASTREG_DEPTH 24 | 179 | #define T3_MAX_FASTREG_DEPTH 10 |
| 180 | #define T3_MAX_FASTREG_FRAG 10 | 180 | #define T3_MAX_FASTREG_FRAG 10 |
| 181 | 181 | ||
| 182 | struct t3_fastreg_wr { | 182 | struct t3_fastreg_wr { |
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.c b/drivers/infiniband/hw/cxgb3/iwch_provider.c index 160ef482712d..e2a63214008a 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_provider.c +++ b/drivers/infiniband/hw/cxgb3/iwch_provider.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include <linux/spinlock.h> | 40 | #include <linux/spinlock.h> |
| 41 | #include <linux/ethtool.h> | 41 | #include <linux/ethtool.h> |
| 42 | #include <linux/rtnetlink.h> | 42 | #include <linux/rtnetlink.h> |
| 43 | #include <linux/inetdevice.h> | ||
| 43 | 44 | ||
| 44 | #include <asm/io.h> | 45 | #include <asm/io.h> |
| 45 | #include <asm/irq.h> | 46 | #include <asm/irq.h> |
| @@ -1152,12 +1153,39 @@ static int iwch_query_device(struct ib_device *ibdev, | |||
| 1152 | static int iwch_query_port(struct ib_device *ibdev, | 1153 | static int iwch_query_port(struct ib_device *ibdev, |
| 1153 | u8 port, struct ib_port_attr *props) | 1154 | u8 port, struct ib_port_attr *props) |
| 1154 | { | 1155 | { |
| 1156 | struct iwch_dev *dev; | ||
| 1157 | struct net_device *netdev; | ||
| 1158 | struct in_device *inetdev; | ||
| 1159 | |||
| 1155 | PDBG("%s ibdev %p\n", __func__, ibdev); | 1160 | PDBG("%s ibdev %p\n", __func__, ibdev); |
| 1156 | 1161 | ||
| 1162 | dev = to_iwch_dev(ibdev); | ||
| 1163 | netdev = dev->rdev.port_info.lldevs[port-1]; | ||
| 1164 | |||
| 1157 | memset(props, 0, sizeof(struct ib_port_attr)); | 1165 | memset(props, 0, sizeof(struct ib_port_attr)); |
| 1158 | props->max_mtu = IB_MTU_4096; | 1166 | props->max_mtu = IB_MTU_4096; |
| 1159 | props->active_mtu = IB_MTU_2048; | 1167 | if (netdev->mtu >= 4096) |
| 1160 | props->state = IB_PORT_ACTIVE; | 1168 | props->active_mtu = IB_MTU_4096; |
| 1169 | else if (netdev->mtu >= 2048) | ||
| 1170 | props->active_mtu = IB_MTU_2048; | ||
| 1171 | else if (netdev->mtu >= 1024) | ||
| 1172 | props->active_mtu = IB_MTU_1024; | ||
| 1173 | else if (netdev->mtu >= 512) | ||
| 1174 | props->active_mtu = IB_MTU_512; | ||
| 1175 | else | ||
| 1176 | props->active_mtu = IB_MTU_256; | ||
| 1177 | |||
| 1178 | if (!netif_carrier_ok(netdev)) | ||
| 1179 | props->state = IB_PORT_DOWN; | ||
| 1180 | else { | ||
| 1181 | inetdev = in_dev_get(netdev); | ||
| 1182 | if (inetdev->ifa_list) | ||
| 1183 | props->state = IB_PORT_ACTIVE; | ||
| 1184 | else | ||
| 1185 | props->state = IB_PORT_INIT; | ||
| 1186 | in_dev_put(inetdev); | ||
| 1187 | } | ||
| 1188 | |||
| 1161 | props->port_cap_flags = | 1189 | props->port_cap_flags = |
| 1162 | IB_PORT_CM_SUP | | 1190 | IB_PORT_CM_SUP | |
| 1163 | IB_PORT_SNMP_TUNNEL_SUP | | 1191 | IB_PORT_SNMP_TUNNEL_SUP | |
diff --git a/drivers/infiniband/hw/ehca/ehca_irq.c b/drivers/infiniband/hw/ehca/ehca_irq.c index 99bcbd7ffb0a..4b89b791be6a 100644 --- a/drivers/infiniband/hw/ehca/ehca_irq.c +++ b/drivers/infiniband/hw/ehca/ehca_irq.c | |||
| @@ -479,13 +479,13 @@ void ehca_tasklet_neq(unsigned long data) | |||
| 479 | struct ehca_eqe *eqe; | 479 | struct ehca_eqe *eqe; |
| 480 | u64 ret; | 480 | u64 ret; |
| 481 | 481 | ||
| 482 | eqe = (struct ehca_eqe *)ehca_poll_eq(shca, &shca->neq); | 482 | eqe = ehca_poll_eq(shca, &shca->neq); |
| 483 | 483 | ||
| 484 | while (eqe) { | 484 | while (eqe) { |
| 485 | if (!EHCA_BMASK_GET(NEQE_COMPLETION_EVENT, eqe->entry)) | 485 | if (!EHCA_BMASK_GET(NEQE_COMPLETION_EVENT, eqe->entry)) |
| 486 | parse_ec(shca, eqe->entry); | 486 | parse_ec(shca, eqe->entry); |
| 487 | 487 | ||
| 488 | eqe = (struct ehca_eqe *)ehca_poll_eq(shca, &shca->neq); | 488 | eqe = ehca_poll_eq(shca, &shca->neq); |
| 489 | } | 489 | } |
| 490 | 490 | ||
| 491 | ret = hipz_h_reset_event(shca->ipz_hca_handle, | 491 | ret = hipz_h_reset_event(shca->ipz_hca_handle, |
| @@ -572,8 +572,7 @@ void ehca_process_eq(struct ehca_shca *shca, int is_irq) | |||
| 572 | eqe_cnt = 0; | 572 | eqe_cnt = 0; |
| 573 | do { | 573 | do { |
| 574 | u32 token; | 574 | u32 token; |
| 575 | eqe_cache[eqe_cnt].eqe = | 575 | eqe_cache[eqe_cnt].eqe = ehca_poll_eq(shca, eq); |
| 576 | (struct ehca_eqe *)ehca_poll_eq(shca, eq); | ||
| 577 | if (!eqe_cache[eqe_cnt].eqe) | 576 | if (!eqe_cache[eqe_cnt].eqe) |
| 578 | break; | 577 | break; |
| 579 | eqe_value = eqe_cache[eqe_cnt].eqe->entry; | 578 | eqe_value = eqe_cache[eqe_cnt].eqe->entry; |
| @@ -637,7 +636,7 @@ void ehca_process_eq(struct ehca_shca *shca, int is_irq) | |||
| 637 | goto unlock_irq_spinlock; | 636 | goto unlock_irq_spinlock; |
| 638 | do { | 637 | do { |
| 639 | struct ehca_eqe *eqe; | 638 | struct ehca_eqe *eqe; |
| 640 | eqe = (struct ehca_eqe *)ehca_poll_eq(shca, &shca->eq); | 639 | eqe = ehca_poll_eq(shca, &shca->eq); |
| 641 | if (!eqe) | 640 | if (!eqe) |
| 642 | break; | 641 | break; |
| 643 | process_eqe(shca, eqe); | 642 | process_eqe(shca, eqe); |
diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 20724aee76f4..c4a02648c8af 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c | |||
| @@ -1585,12 +1585,16 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
| 1585 | break; | 1585 | break; |
| 1586 | 1586 | ||
| 1587 | case IB_WR_LOCAL_INV: | 1587 | case IB_WR_LOCAL_INV: |
| 1588 | ctrl->srcrb_flags |= | ||
| 1589 | cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); | ||
| 1588 | set_local_inv_seg(wqe, wr->ex.invalidate_rkey); | 1590 | set_local_inv_seg(wqe, wr->ex.invalidate_rkey); |
| 1589 | wqe += sizeof (struct mlx4_wqe_local_inval_seg); | 1591 | wqe += sizeof (struct mlx4_wqe_local_inval_seg); |
| 1590 | size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; | 1592 | size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; |
| 1591 | break; | 1593 | break; |
| 1592 | 1594 | ||
| 1593 | case IB_WR_FAST_REG_MR: | 1595 | case IB_WR_FAST_REG_MR: |
| 1596 | ctrl->srcrb_flags |= | ||
| 1597 | cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); | ||
| 1594 | set_fmr_seg(wqe, wr); | 1598 | set_fmr_seg(wqe, wr); |
| 1595 | wqe += sizeof (struct mlx4_wqe_fmr_seg); | 1599 | wqe += sizeof (struct mlx4_wqe_fmr_seg); |
| 1596 | size += sizeof (struct mlx4_wqe_fmr_seg) / 16; | 1600 | size += sizeof (struct mlx4_wqe_fmr_seg) / 16; |
diff --git a/drivers/infiniband/hw/mthca/mthca_cmd.c b/drivers/infiniband/hw/mthca/mthca_cmd.c index 6d55f9d748f6..8c2ed994d540 100644 --- a/drivers/infiniband/hw/mthca/mthca_cmd.c +++ b/drivers/infiniband/hw/mthca/mthca_cmd.c | |||
| @@ -1059,7 +1059,7 @@ int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, | |||
| 1059 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); | 1059 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); |
| 1060 | if (mthca_is_memfree(dev)) | 1060 | if (mthca_is_memfree(dev)) |
| 1061 | dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64), | 1061 | dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64), |
| 1062 | MTHCA_MTT_SEG_SIZE) / MTHCA_MTT_SEG_SIZE; | 1062 | dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size; |
| 1063 | else | 1063 | else |
| 1064 | dev_lim->reserved_mtts = 1 << (field >> 4); | 1064 | dev_lim->reserved_mtts = 1 << (field >> 4); |
| 1065 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); | 1065 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); |
diff --git a/drivers/infiniband/hw/mthca/mthca_dev.h b/drivers/infiniband/hw/mthca/mthca_dev.h index 252590116df5..9ef611f6dd36 100644 --- a/drivers/infiniband/hw/mthca/mthca_dev.h +++ b/drivers/infiniband/hw/mthca/mthca_dev.h | |||
| @@ -159,6 +159,7 @@ struct mthca_limits { | |||
| 159 | int reserved_eqs; | 159 | int reserved_eqs; |
| 160 | int num_mpts; | 160 | int num_mpts; |
| 161 | int num_mtt_segs; | 161 | int num_mtt_segs; |
| 162 | int mtt_seg_size; | ||
| 162 | int fmr_reserved_mtts; | 163 | int fmr_reserved_mtts; |
| 163 | int reserved_mtts; | 164 | int reserved_mtts; |
| 164 | int reserved_mrws; | 165 | int reserved_mrws; |
diff --git a/drivers/infiniband/hw/mthca/mthca_eq.c b/drivers/infiniband/hw/mthca/mthca_eq.c index 28f0e0c40d7d..90e4e450a120 100644 --- a/drivers/infiniband/hw/mthca/mthca_eq.c +++ b/drivers/infiniband/hw/mthca/mthca_eq.c | |||
| @@ -641,9 +641,11 @@ static void mthca_free_irqs(struct mthca_dev *dev) | |||
| 641 | if (dev->eq_table.have_irq) | 641 | if (dev->eq_table.have_irq) |
| 642 | free_irq(dev->pdev->irq, dev); | 642 | free_irq(dev->pdev->irq, dev); |
| 643 | for (i = 0; i < MTHCA_NUM_EQ; ++i) | 643 | for (i = 0; i < MTHCA_NUM_EQ; ++i) |
| 644 | if (dev->eq_table.eq[i].have_irq) | 644 | if (dev->eq_table.eq[i].have_irq) { |
| 645 | free_irq(dev->eq_table.eq[i].msi_x_vector, | 645 | free_irq(dev->eq_table.eq[i].msi_x_vector, |
| 646 | dev->eq_table.eq + i); | 646 | dev->eq_table.eq + i); |
| 647 | dev->eq_table.eq[i].have_irq = 0; | ||
| 648 | } | ||
| 647 | } | 649 | } |
| 648 | 650 | ||
| 649 | static int mthca_map_reg(struct mthca_dev *dev, | 651 | static int mthca_map_reg(struct mthca_dev *dev, |
diff --git a/drivers/infiniband/hw/mthca/mthca_main.c b/drivers/infiniband/hw/mthca/mthca_main.c index 1d83cf7caf38..13da9f1d24c0 100644 --- a/drivers/infiniband/hw/mthca/mthca_main.c +++ b/drivers/infiniband/hw/mthca/mthca_main.c | |||
| @@ -125,6 +125,10 @@ module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444); | |||
| 125 | MODULE_PARM_DESC(fmr_reserved_mtts, | 125 | MODULE_PARM_DESC(fmr_reserved_mtts, |
| 126 | "number of memory translation table segments reserved for FMR"); | 126 | "number of memory translation table segments reserved for FMR"); |
| 127 | 127 | ||
| 128 | static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8); | ||
| 129 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); | ||
| 130 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)"); | ||
| 131 | |||
| 128 | static char mthca_version[] __devinitdata = | 132 | static char mthca_version[] __devinitdata = |
| 129 | DRV_NAME ": Mellanox InfiniBand HCA driver v" | 133 | DRV_NAME ": Mellanox InfiniBand HCA driver v" |
| 130 | DRV_VERSION " (" DRV_RELDATE ")\n"; | 134 | DRV_VERSION " (" DRV_RELDATE ")\n"; |
| @@ -162,6 +166,7 @@ static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim) | |||
| 162 | int err; | 166 | int err; |
| 163 | u8 status; | 167 | u8 status; |
| 164 | 168 | ||
| 169 | mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8; | ||
| 165 | err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status); | 170 | err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status); |
| 166 | if (err) { | 171 | if (err) { |
| 167 | mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n"); | 172 | mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n"); |
| @@ -460,11 +465,11 @@ static int mthca_init_icm(struct mthca_dev *mdev, | |||
| 460 | } | 465 | } |
| 461 | 466 | ||
| 462 | /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */ | 467 | /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */ |
| 463 | mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE, | 468 | mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size, |
| 464 | dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE; | 469 | dma_get_cache_alignment()) / mdev->limits.mtt_seg_size; |
| 465 | 470 | ||
| 466 | mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base, | 471 | mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base, |
| 467 | MTHCA_MTT_SEG_SIZE, | 472 | mdev->limits.mtt_seg_size, |
| 468 | mdev->limits.num_mtt_segs, | 473 | mdev->limits.num_mtt_segs, |
| 469 | mdev->limits.reserved_mtts, | 474 | mdev->limits.reserved_mtts, |
| 470 | 1, 0); | 475 | 1, 0); |
| @@ -1315,6 +1320,12 @@ static void __init mthca_validate_profile(void) | |||
| 1315 | printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n", | 1320 | printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n", |
| 1316 | hca_profile.fmr_reserved_mtts); | 1321 | hca_profile.fmr_reserved_mtts); |
| 1317 | } | 1322 | } |
| 1323 | |||
| 1324 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) { | ||
| 1325 | printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n", | ||
| 1326 | log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8)); | ||
| 1327 | log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8); | ||
| 1328 | } | ||
| 1318 | } | 1329 | } |
| 1319 | 1330 | ||
| 1320 | static int __init mthca_init(void) | 1331 | static int __init mthca_init(void) |
diff --git a/drivers/infiniband/hw/mthca/mthca_mr.c b/drivers/infiniband/hw/mthca/mthca_mr.c index 882e6b735915..d606edf10858 100644 --- a/drivers/infiniband/hw/mthca/mthca_mr.c +++ b/drivers/infiniband/hw/mthca/mthca_mr.c | |||
| @@ -220,7 +220,7 @@ static struct mthca_mtt *__mthca_alloc_mtt(struct mthca_dev *dev, int size, | |||
| 220 | 220 | ||
| 221 | mtt->buddy = buddy; | 221 | mtt->buddy = buddy; |
| 222 | mtt->order = 0; | 222 | mtt->order = 0; |
| 223 | for (i = MTHCA_MTT_SEG_SIZE / 8; i < size; i <<= 1) | 223 | for (i = dev->limits.mtt_seg_size / 8; i < size; i <<= 1) |
| 224 | ++mtt->order; | 224 | ++mtt->order; |
| 225 | 225 | ||
| 226 | mtt->first_seg = mthca_alloc_mtt_range(dev, mtt->order, buddy); | 226 | mtt->first_seg = mthca_alloc_mtt_range(dev, mtt->order, buddy); |
| @@ -267,7 +267,7 @@ static int __mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt, | |||
| 267 | 267 | ||
| 268 | while (list_len > 0) { | 268 | while (list_len > 0) { |
| 269 | mtt_entry[0] = cpu_to_be64(dev->mr_table.mtt_base + | 269 | mtt_entry[0] = cpu_to_be64(dev->mr_table.mtt_base + |
| 270 | mtt->first_seg * MTHCA_MTT_SEG_SIZE + | 270 | mtt->first_seg * dev->limits.mtt_seg_size + |
| 271 | start_index * 8); | 271 | start_index * 8); |
| 272 | mtt_entry[1] = 0; | 272 | mtt_entry[1] = 0; |
| 273 | for (i = 0; i < list_len && i < MTHCA_MAILBOX_SIZE / 8 - 2; ++i) | 273 | for (i = 0; i < list_len && i < MTHCA_MAILBOX_SIZE / 8 - 2; ++i) |
| @@ -326,7 +326,7 @@ static void mthca_tavor_write_mtt_seg(struct mthca_dev *dev, | |||
| 326 | u64 __iomem *mtts; | 326 | u64 __iomem *mtts; |
| 327 | int i; | 327 | int i; |
| 328 | 328 | ||
| 329 | mtts = dev->mr_table.tavor_fmr.mtt_base + mtt->first_seg * MTHCA_MTT_SEG_SIZE + | 329 | mtts = dev->mr_table.tavor_fmr.mtt_base + mtt->first_seg * dev->limits.mtt_seg_size + |
| 330 | start_index * sizeof (u64); | 330 | start_index * sizeof (u64); |
| 331 | for (i = 0; i < list_len; ++i) | 331 | for (i = 0; i < list_len; ++i) |
| 332 | mthca_write64_raw(cpu_to_be64(buffer_list[i] | MTHCA_MTT_FLAG_PRESENT), | 332 | mthca_write64_raw(cpu_to_be64(buffer_list[i] | MTHCA_MTT_FLAG_PRESENT), |
| @@ -345,10 +345,10 @@ static void mthca_arbel_write_mtt_seg(struct mthca_dev *dev, | |||
| 345 | /* For Arbel, all MTTs must fit in the same page. */ | 345 | /* For Arbel, all MTTs must fit in the same page. */ |
| 346 | BUG_ON(s / PAGE_SIZE != (s + list_len * sizeof(u64) - 1) / PAGE_SIZE); | 346 | BUG_ON(s / PAGE_SIZE != (s + list_len * sizeof(u64) - 1) / PAGE_SIZE); |
| 347 | /* Require full segments */ | 347 | /* Require full segments */ |
| 348 | BUG_ON(s % MTHCA_MTT_SEG_SIZE); | 348 | BUG_ON(s % dev->limits.mtt_seg_size); |
| 349 | 349 | ||
| 350 | mtts = mthca_table_find(dev->mr_table.mtt_table, mtt->first_seg + | 350 | mtts = mthca_table_find(dev->mr_table.mtt_table, mtt->first_seg + |
| 351 | s / MTHCA_MTT_SEG_SIZE, &dma_handle); | 351 | s / dev->limits.mtt_seg_size, &dma_handle); |
| 352 | 352 | ||
| 353 | BUG_ON(!mtts); | 353 | BUG_ON(!mtts); |
| 354 | 354 | ||
| @@ -479,7 +479,7 @@ int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift, | |||
| 479 | if (mr->mtt) | 479 | if (mr->mtt) |
| 480 | mpt_entry->mtt_seg = | 480 | mpt_entry->mtt_seg = |
| 481 | cpu_to_be64(dev->mr_table.mtt_base + | 481 | cpu_to_be64(dev->mr_table.mtt_base + |
| 482 | mr->mtt->first_seg * MTHCA_MTT_SEG_SIZE); | 482 | mr->mtt->first_seg * dev->limits.mtt_seg_size); |
| 483 | 483 | ||
| 484 | if (0) { | 484 | if (0) { |
| 485 | mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey); | 485 | mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey); |
| @@ -626,7 +626,7 @@ int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd, | |||
| 626 | goto err_out_table; | 626 | goto err_out_table; |
| 627 | } | 627 | } |
| 628 | 628 | ||
| 629 | mtt_seg = mr->mtt->first_seg * MTHCA_MTT_SEG_SIZE; | 629 | mtt_seg = mr->mtt->first_seg * dev->limits.mtt_seg_size; |
| 630 | 630 | ||
| 631 | if (mthca_is_memfree(dev)) { | 631 | if (mthca_is_memfree(dev)) { |
| 632 | mr->mem.arbel.mtts = mthca_table_find(dev->mr_table.mtt_table, | 632 | mr->mem.arbel.mtts = mthca_table_find(dev->mr_table.mtt_table, |
| @@ -908,7 +908,7 @@ int mthca_init_mr_table(struct mthca_dev *dev) | |||
| 908 | dev->mr_table.mtt_base); | 908 | dev->mr_table.mtt_base); |
| 909 | 909 | ||
| 910 | dev->mr_table.tavor_fmr.mtt_base = | 910 | dev->mr_table.tavor_fmr.mtt_base = |
| 911 | ioremap(addr, mtts * MTHCA_MTT_SEG_SIZE); | 911 | ioremap(addr, mtts * dev->limits.mtt_seg_size); |
| 912 | if (!dev->mr_table.tavor_fmr.mtt_base) { | 912 | if (!dev->mr_table.tavor_fmr.mtt_base) { |
| 913 | mthca_warn(dev, "MTT ioremap for FMR failed.\n"); | 913 | mthca_warn(dev, "MTT ioremap for FMR failed.\n"); |
| 914 | err = -ENOMEM; | 914 | err = -ENOMEM; |
diff --git a/drivers/infiniband/hw/mthca/mthca_profile.c b/drivers/infiniband/hw/mthca/mthca_profile.c index d168c2540611..8edb28a9a0e7 100644 --- a/drivers/infiniband/hw/mthca/mthca_profile.c +++ b/drivers/infiniband/hw/mthca/mthca_profile.c | |||
| @@ -94,7 +94,7 @@ s64 mthca_make_profile(struct mthca_dev *dev, | |||
| 94 | profile[MTHCA_RES_RDB].size = MTHCA_RDB_ENTRY_SIZE; | 94 | profile[MTHCA_RES_RDB].size = MTHCA_RDB_ENTRY_SIZE; |
| 95 | profile[MTHCA_RES_MCG].size = MTHCA_MGM_ENTRY_SIZE; | 95 | profile[MTHCA_RES_MCG].size = MTHCA_MGM_ENTRY_SIZE; |
| 96 | profile[MTHCA_RES_MPT].size = dev_lim->mpt_entry_sz; | 96 | profile[MTHCA_RES_MPT].size = dev_lim->mpt_entry_sz; |
| 97 | profile[MTHCA_RES_MTT].size = MTHCA_MTT_SEG_SIZE; | 97 | profile[MTHCA_RES_MTT].size = dev->limits.mtt_seg_size; |
| 98 | profile[MTHCA_RES_UAR].size = dev_lim->uar_scratch_entry_sz; | 98 | profile[MTHCA_RES_UAR].size = dev_lim->uar_scratch_entry_sz; |
| 99 | profile[MTHCA_RES_UDAV].size = MTHCA_AV_SIZE; | 99 | profile[MTHCA_RES_UDAV].size = MTHCA_AV_SIZE; |
| 100 | profile[MTHCA_RES_UARC].size = request->uarc_size; | 100 | profile[MTHCA_RES_UARC].size = request->uarc_size; |
| @@ -232,7 +232,7 @@ s64 mthca_make_profile(struct mthca_dev *dev, | |||
| 232 | dev->limits.num_mtt_segs = profile[i].num; | 232 | dev->limits.num_mtt_segs = profile[i].num; |
| 233 | dev->mr_table.mtt_base = profile[i].start; | 233 | dev->mr_table.mtt_base = profile[i].start; |
| 234 | init_hca->mtt_base = profile[i].start; | 234 | init_hca->mtt_base = profile[i].start; |
| 235 | init_hca->mtt_seg_sz = ffs(MTHCA_MTT_SEG_SIZE) - 7; | 235 | init_hca->mtt_seg_sz = ffs(dev->limits.mtt_seg_size) - 7; |
| 236 | break; | 236 | break; |
| 237 | case MTHCA_RES_UAR: | 237 | case MTHCA_RES_UAR: |
| 238 | dev->limits.num_uars = profile[i].num; | 238 | dev->limits.num_uars = profile[i].num; |
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c index b832a7b814a2..4a84d02ece06 100644 --- a/drivers/infiniband/hw/nes/nes_hw.c +++ b/drivers/infiniband/hw/nes/nes_hw.c | |||
| @@ -667,7 +667,7 @@ static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_ | |||
| 667 | i = 0; | 667 | i = 0; |
| 668 | while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000) | 668 | while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000) |
| 669 | mdelay(1); | 669 | mdelay(1); |
| 670 | if (i >= 10000) { | 670 | if (i > 10000) { |
| 671 | nes_debug(NES_DBG_INIT, "Did not see full soft reset done.\n"); | 671 | nes_debug(NES_DBG_INIT, "Did not see full soft reset done.\n"); |
| 672 | return 0; | 672 | return 0; |
| 673 | } | 673 | } |
| @@ -675,7 +675,7 @@ static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_ | |||
| 675 | i = 0; | 675 | i = 0; |
| 676 | while ((nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS) != 0x80) && i++ < 10000) | 676 | while ((nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS) != 0x80) && i++ < 10000) |
| 677 | mdelay(1); | 677 | mdelay(1); |
| 678 | if (i >= 10000) { | 678 | if (i > 10000) { |
| 679 | printk(KERN_ERR PFX "Internal CPU not ready, status = %02X\n", | 679 | printk(KERN_ERR PFX "Internal CPU not ready, status = %02X\n", |
| 680 | nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS)); | 680 | nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS)); |
| 681 | return 0; | 681 | return 0; |
| @@ -701,7 +701,7 @@ static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_ | |||
| 701 | i = 0; | 701 | i = 0; |
| 702 | while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000) | 702 | while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000) |
| 703 | mdelay(1); | 703 | mdelay(1); |
| 704 | if (i >= 10000) { | 704 | if (i > 10000) { |
| 705 | nes_debug(NES_DBG_INIT, "Did not see port soft reset done.\n"); | 705 | nes_debug(NES_DBG_INIT, "Did not see port soft reset done.\n"); |
| 706 | return 0; | 706 | return 0; |
| 707 | } | 707 | } |
| @@ -711,7 +711,7 @@ static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_ | |||
| 711 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0) | 711 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0) |
| 712 | & 0x0000000f)) != 0x0000000f) && i++ < 5000) | 712 | & 0x0000000f)) != 0x0000000f) && i++ < 5000) |
| 713 | mdelay(1); | 713 | mdelay(1); |
| 714 | if (i >= 5000) { | 714 | if (i > 5000) { |
| 715 | nes_debug(NES_DBG_INIT, "Serdes 0 not ready, status=%x\n", u32temp); | 715 | nes_debug(NES_DBG_INIT, "Serdes 0 not ready, status=%x\n", u32temp); |
| 716 | return 0; | 716 | return 0; |
| 717 | } | 717 | } |
| @@ -722,7 +722,7 @@ static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_ | |||
| 722 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1) | 722 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1) |
| 723 | & 0x0000000f)) != 0x0000000f) && i++ < 5000) | 723 | & 0x0000000f)) != 0x0000000f) && i++ < 5000) |
| 724 | mdelay(1); | 724 | mdelay(1); |
| 725 | if (i >= 5000) { | 725 | if (i > 5000) { |
| 726 | nes_debug(NES_DBG_INIT, "Serdes 1 not ready, status=%x\n", u32temp); | 726 | nes_debug(NES_DBG_INIT, "Serdes 1 not ready, status=%x\n", u32temp); |
| 727 | return 0; | 727 | return 0; |
| 728 | } | 728 | } |
| @@ -792,7 +792,7 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
| 792 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0) | 792 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0) |
| 793 | & 0x0000000f)) != 0x0000000f) && i++ < 5000) | 793 | & 0x0000000f)) != 0x0000000f) && i++ < 5000) |
| 794 | mdelay(1); | 794 | mdelay(1); |
| 795 | if (i >= 5000) { | 795 | if (i > 5000) { |
| 796 | nes_debug(NES_DBG_PHY, "Init: serdes 0 not ready, status=%x\n", u32temp); | 796 | nes_debug(NES_DBG_PHY, "Init: serdes 0 not ready, status=%x\n", u32temp); |
| 797 | return 1; | 797 | return 1; |
| 798 | } | 798 | } |
| @@ -815,7 +815,7 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
| 815 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1) | 815 | while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1) |
| 816 | & 0x0000000f)) != 0x0000000f) && (i++ < 5000)) | 816 | & 0x0000000f)) != 0x0000000f) && (i++ < 5000)) |
| 817 | mdelay(1); | 817 | mdelay(1); |
| 818 | if (i >= 5000) { | 818 | if (i > 5000) { |
| 819 | printk("%s: Init: serdes 1 not ready, status=%x\n", __func__, u32temp); | 819 | printk("%s: Init: serdes 1 not ready, status=%x\n", __func__, u32temp); |
| 820 | /* return 1; */ | 820 | /* return 1; */ |
| 821 | } | 821 | } |
diff --git a/drivers/net/mlx4/eq.c b/drivers/net/mlx4/eq.c index 8830dcb92ec8..ce064e324200 100644 --- a/drivers/net/mlx4/eq.c +++ b/drivers/net/mlx4/eq.c | |||
| @@ -497,8 +497,10 @@ static void mlx4_free_irqs(struct mlx4_dev *dev) | |||
| 497 | if (eq_table->have_irq) | 497 | if (eq_table->have_irq) |
| 498 | free_irq(dev->pdev->irq, dev); | 498 | free_irq(dev->pdev->irq, dev); |
| 499 | for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) | 499 | for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) |
| 500 | if (eq_table->eq[i].have_irq) | 500 | if (eq_table->eq[i].have_irq) { |
| 501 | free_irq(eq_table->eq[i].irq, eq_table->eq + i); | 501 | free_irq(eq_table->eq[i].irq, eq_table->eq + i); |
| 502 | eq_table->eq[i].have_irq = 0; | ||
| 503 | } | ||
| 502 | 504 | ||
| 503 | kfree(eq_table->irq_names); | 505 | kfree(eq_table->irq_names); |
| 504 | } | 506 | } |
diff --git a/drivers/net/mlx4/main.c b/drivers/net/mlx4/main.c index 30bea9689694..018348c01193 100644 --- a/drivers/net/mlx4/main.c +++ b/drivers/net/mlx4/main.c | |||
| @@ -100,6 +100,10 @@ module_param_named(use_prio, use_prio, bool, 0444); | |||
| 100 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " | 100 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " |
| 101 | "(0/1, default 0)"); | 101 | "(0/1, default 0)"); |
| 102 | 102 | ||
| 103 | static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); | ||
| 104 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); | ||
| 105 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)"); | ||
| 106 | |||
| 103 | int mlx4_check_port_params(struct mlx4_dev *dev, | 107 | int mlx4_check_port_params(struct mlx4_dev *dev, |
| 104 | enum mlx4_port_type *port_type) | 108 | enum mlx4_port_type *port_type) |
| 105 | { | 109 | { |
| @@ -203,12 +207,13 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
| 203 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | 207 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; |
| 204 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | 208 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; |
| 205 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | 209 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; |
| 210 | dev->caps.mtts_per_seg = 1 << log_mtts_per_seg; | ||
| 206 | dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts, | 211 | dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts, |
| 207 | MLX4_MTT_ENTRY_PER_SEG); | 212 | dev->caps.mtts_per_seg); |
| 208 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; | 213 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
| 209 | dev->caps.reserved_uars = dev_cap->reserved_uars; | 214 | dev->caps.reserved_uars = dev_cap->reserved_uars; |
| 210 | dev->caps.reserved_pds = dev_cap->reserved_pds; | 215 | dev->caps.reserved_pds = dev_cap->reserved_pds; |
| 211 | dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz; | 216 | dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz; |
| 212 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; | 217 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
| 213 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); | 218 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
| 214 | dev->caps.flags = dev_cap->flags; | 219 | dev->caps.flags = dev_cap->flags; |
| @@ -1304,6 +1309,11 @@ static int __init mlx4_verify_params(void) | |||
| 1304 | return -1; | 1309 | return -1; |
| 1305 | } | 1310 | } |
| 1306 | 1311 | ||
| 1312 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) { | ||
| 1313 | printk(KERN_WARNING "mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); | ||
| 1314 | return -1; | ||
| 1315 | } | ||
| 1316 | |||
| 1307 | return 0; | 1317 | return 0; |
| 1308 | } | 1318 | } |
| 1309 | 1319 | ||
diff --git a/drivers/net/mlx4/mr.c b/drivers/net/mlx4/mr.c index 0caf74cae8bc..3b8973d19933 100644 --- a/drivers/net/mlx4/mr.c +++ b/drivers/net/mlx4/mr.c | |||
| @@ -209,7 +209,7 @@ int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |||
| 209 | } else | 209 | } else |
| 210 | mtt->page_shift = page_shift; | 210 | mtt->page_shift = page_shift; |
| 211 | 211 | ||
| 212 | for (mtt->order = 0, i = MLX4_MTT_ENTRY_PER_SEG; i < npages; i <<= 1) | 212 | for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1) |
| 213 | ++mtt->order; | 213 | ++mtt->order; |
| 214 | 214 | ||
| 215 | mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order); | 215 | mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order); |
| @@ -350,7 +350,7 @@ int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr) | |||
| 350 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | | 350 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | |
| 351 | MLX4_MPT_PD_FLAG_RAE); | 351 | MLX4_MPT_PD_FLAG_RAE); |
| 352 | mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) * | 352 | mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) * |
| 353 | MLX4_MTT_ENTRY_PER_SEG); | 353 | dev->caps.mtts_per_seg); |
| 354 | } else { | 354 | } else { |
| 355 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); | 355 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); |
| 356 | } | 356 | } |
| @@ -391,7 +391,7 @@ static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |||
| 391 | (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64))) | 391 | (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64))) |
| 392 | return -EINVAL; | 392 | return -EINVAL; |
| 393 | 393 | ||
| 394 | if (start_index & (MLX4_MTT_ENTRY_PER_SEG - 1)) | 394 | if (start_index & (dev->caps.mtts_per_seg - 1)) |
| 395 | return -EINVAL; | 395 | return -EINVAL; |
| 396 | 396 | ||
| 397 | mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg + | 397 | mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg + |
diff --git a/drivers/net/mlx4/profile.c b/drivers/net/mlx4/profile.c index cebdf3243ca1..bd22df95adf9 100644 --- a/drivers/net/mlx4/profile.c +++ b/drivers/net/mlx4/profile.c | |||
| @@ -98,7 +98,7 @@ u64 mlx4_make_profile(struct mlx4_dev *dev, | |||
| 98 | profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz; | 98 | profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz; |
| 99 | profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz; | 99 | profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz; |
| 100 | profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz; | 100 | profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz; |
| 101 | profile[MLX4_RES_MTT].size = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz; | 101 | profile[MLX4_RES_MTT].size = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz; |
| 102 | profile[MLX4_RES_MCG].size = MLX4_MGM_ENTRY_SIZE; | 102 | profile[MLX4_RES_MCG].size = MLX4_MGM_ENTRY_SIZE; |
| 103 | 103 | ||
| 104 | profile[MLX4_RES_QP].num = request->num_qp; | 104 | profile[MLX4_RES_QP].num = request->num_qp; |
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 3aff8a6a389e..ce7cc6c7bcbb 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -210,6 +210,7 @@ struct mlx4_caps { | |||
| 210 | int num_comp_vectors; | 210 | int num_comp_vectors; |
| 211 | int num_mpts; | 211 | int num_mpts; |
| 212 | int num_mtt_segs; | 212 | int num_mtt_segs; |
| 213 | int mtts_per_seg; | ||
| 213 | int fmr_reserved_mtts; | 214 | int fmr_reserved_mtts; |
| 214 | int reserved_mtts; | 215 | int reserved_mtts; |
| 215 | int reserved_mrws; | 216 | int reserved_mrws; |
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index bf8f11982dae..9f29d86e5dc9 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h | |||
| @@ -165,6 +165,7 @@ enum { | |||
| 165 | MLX4_WQE_CTRL_IP_CSUM = 1 << 4, | 165 | MLX4_WQE_CTRL_IP_CSUM = 1 << 4, |
| 166 | MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, | 166 | MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, |
| 167 | MLX4_WQE_CTRL_INS_VLAN = 1 << 6, | 167 | MLX4_WQE_CTRL_INS_VLAN = 1 << 6, |
| 168 | MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, | ||
| 168 | }; | 169 | }; |
| 169 | 170 | ||
| 170 | struct mlx4_wqe_ctrl_seg { | 171 | struct mlx4_wqe_ctrl_seg { |
