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-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h5
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h19
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h5
-rw-r--r--arch/arm/mach-omap2/prm44xx.h15
4 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 63ef9e3a857c..e2d7a56b2ad6 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -40,6 +40,11 @@
40#define OMAP4430_CM1_RESTORE_INST 0x0e00 40#define OMAP4430_CM1_RESTORE_INST 0x0e00
41#define OMAP4430_CM1_INSTR_INST 0x0f00 41#define OMAP4430_CM1_INSTR_INST 0x0f00
42 42
43/* CM1 clockdomain register offsets (from instance start) */
44#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
45#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
46#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
47
43/* CM1 */ 48/* CM1 */
44 49
45/* CM1.OCP_SOCKET_CM1 register offsets */ 50/* CM1.OCP_SOCKET_CM1 register offsets */
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index 0fd021069792..aa4745044065 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -46,6 +46,25 @@
46#define OMAP4430_CM2_RESTORE_INST 0x1e00 46#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_INST 0x1f00 47#define OMAP4430_CM2_INSTR_INST 0x1f00
48 48
49/* CM2 clockdomain register offsets (from instance start) */
50#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000
51#define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000
52#define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100
53#define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200
54#define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300
55#define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400
56#define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500
57#define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600
58#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700
59#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000
60#define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000
61#define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000
62#define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000
63#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000
64#define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000
65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
67
49 68
50/* CM2 */ 69/* CM2 */
51 70
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index e5190e99fd94..729a644ce852 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -37,6 +37,11 @@
37#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 37#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 39
40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000
42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000
43
44
40/* 45/*
41 * PRCM_MPU 46 * PRCM_MPU
42 * 47 *
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 95542aec6c90..67a0d3feb3f6 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -56,6 +56,21 @@
56#define OMAP4430_PRM_DEVICE_INST 0x1b00 56#define OMAP4430_PRM_DEVICE_INST 0x1b00
57#define OMAP4430_PRM_INSTR_INST 0x1f00 57#define OMAP4430_PRM_INSTR_INST 0x1f00
58 58
59/* PRM clockdomain register offsets (from instance start) */
60#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
61#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
62#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
63#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
64#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
65#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
66#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
67#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
68#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
69#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
70#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
71#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
72#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
73#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
59 74
60/* OMAP4 specific register offsets */ 75/* OMAP4 specific register offsets */
61#define OMAP4_RM_RSTCTRL 0x0000 76#define OMAP4_RM_RSTCTRL 0x0000