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-rw-r--r--arch/arm/mach-omap1/clock.c6
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c4
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c62
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/id.c41
-rw-r--r--arch/arm/mach-omap2/irq.c18
-rw-r--r--arch/arm/mach-omap2/mux.c27
-rw-r--r--arch/arm/mach-omap2/mux.h24
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c3
-rw-r--r--arch/arm/mach-omap2/pm-debug.c12
-rw-r--r--arch/arm/mach-omap2/pm.h8
-rw-r--r--arch/arm/mach-omap2/pm34xx.c47
-rw-r--r--arch/arm/mach-omap2/prcm.c11
-rw-r--r--arch/arm/mach-omap2/prm.h2
-rw-r--r--arch/arm/mach-omap2/prm44xx.h32
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S13
-rw-r--r--arch/arm/mach-s3c6410/mach-hmt.c2
-rw-r--r--arch/arm/plat-omap/common.c26
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c13
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h1
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h1
-rw-r--r--drivers/i2c/busses/i2c-imx.c26
-rw-r--r--drivers/mtd/maps/Kconfig17
-rw-r--r--drivers/mtd/maps/pismo.c320
-rw-r--r--drivers/mtd/mtdoops.c2
-rw-r--r--drivers/mtd/tests/mtd_readtest.c6
-rw-r--r--drivers/mtd/tests/mtd_speedtest.c7
-rw-r--r--drivers/mtd/tests/mtd_stresstest.c6
-rw-r--r--include/linux/kmsg_dump.h1
-rw-r--r--include/linux/mtd/pismo.h17
-rw-r--r--kernel/kexec.c4
-rw-r--r--kernel/panic.c3
-rw-r--r--kernel/printk.c1
-rw-r--r--kernel/time/clockevents.c3
37 files changed, 625 insertions, 150 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 2ba9ab953731..04f1d29cba2c 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
214 struct mpu_rate * ptr; 214 struct mpu_rate * ptr;
215 unsigned long dpll1_rate, ref_rate; 215 unsigned long dpll1_rate, ref_rate;
216 216
217 dpll1_rate = clk_get_rate(ck_dpll1_p); 217 dpll1_rate = ck_dpll1_p->rate;
218 ref_rate = clk_get_rate(ck_ref_p); 218 ref_rate = ck_ref_p->rate;
219 219
220 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 220 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
221 if (ptr->xtal != ref_rate) 221 if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
306 long highest_rate; 306 long highest_rate;
307 unsigned long ref_rate; 307 unsigned long ref_rate;
308 308
309 ref_rate = clk_get_rate(ck_ref_p); 309 ref_rate = ck_ref_p->rate;
310 310
311 highest_rate = -EINVAL; 311 highest_rate = -EINVAL;
312 312
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index c6031d74d6f6..74930e3158e3 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
671 .name = "dpll4_m3x2_ck", 671 .name = "dpll4_m3x2_ck",
672 .ops = &clkops_omap2_dflt_wait, 672 .ops = &clkops_omap2_dflt_wait,
673 .parent = &dpll4_m3_ck, 673 .parent = &dpll4_m3_ck,
674 .init = &omap2_init_clksel_parent,
675 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 674 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
676 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 675 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
677 .flags = INVERT_ENABLE, 676 .flags = INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
811 .name = "dpll4_m6x2_ck", 810 .name = "dpll4_m6x2_ck",
812 .ops = &clkops_omap2_dflt_wait, 811 .ops = &clkops_omap2_dflt_wait,
813 .parent = &dpll4_m6_ck, 812 .parent = &dpll4_m6_ck,
814 .init = &omap2_init_clksel_parent,
815 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 813 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
816 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 814 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
817 .flags = INVERT_ENABLE, 815 .flags = INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
1047 .name = "iva2_ck", 1045 .name = "iva2_ck",
1048 .ops = &clkops_omap2_dflt_wait, 1046 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &dpll2_m2_ck, 1047 .parent = &dpll2_m2_ck,
1050 .init = &omap2_init_clksel_parent,
1051 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1052 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1049 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1053 .clkdm_name = "iva2_clkdm", 1050 .clkdm_name = "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
1121 .name = "gfx_l3_ck", 1118 .name = "gfx_l3_ck",
1122 .ops = &clkops_omap2_dflt_wait, 1119 .ops = &clkops_omap2_dflt_wait,
1123 .parent = &l3_ick, 1120 .parent = &l3_ick,
1124 .init = &omap2_init_clksel_parent,
1125 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1121 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1126 .enable_bit = OMAP_EN_GFX_SHIFT, 1122 .enable_bit = OMAP_EN_GFX_SHIFT,
1127 .recalc = &followparent_recalc, 1123 .recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2210e227d78a..9d882bcb56e3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -346,37 +346,37 @@ static struct clk aess_fclk = {
346}; 346};
347 347
348static const struct clksel_rate div31_1to31_rates[] = { 348static const struct clksel_rate div31_1to31_rates[] = {
349 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 349 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
350 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 350 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
351 { .div = 3, .val = 2, .flags = RATE_IN_4430 }, 351 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
352 { .div = 4, .val = 3, .flags = RATE_IN_4430 }, 352 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
353 { .div = 5, .val = 4, .flags = RATE_IN_4430 }, 353 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
354 { .div = 6, .val = 5, .flags = RATE_IN_4430 }, 354 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
355 { .div = 7, .val = 6, .flags = RATE_IN_4430 }, 355 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
356 { .div = 8, .val = 7, .flags = RATE_IN_4430 }, 356 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
357 { .div = 9, .val = 8, .flags = RATE_IN_4430 }, 357 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
358 { .div = 10, .val = 9, .flags = RATE_IN_4430 }, 358 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
359 { .div = 11, .val = 10, .flags = RATE_IN_4430 }, 359 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
360 { .div = 12, .val = 11, .flags = RATE_IN_4430 }, 360 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
361 { .div = 13, .val = 12, .flags = RATE_IN_4430 }, 361 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
362 { .div = 14, .val = 13, .flags = RATE_IN_4430 }, 362 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
363 { .div = 15, .val = 14, .flags = RATE_IN_4430 }, 363 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
364 { .div = 16, .val = 15, .flags = RATE_IN_4430 }, 364 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
365 { .div = 17, .val = 16, .flags = RATE_IN_4430 }, 365 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
366 { .div = 18, .val = 17, .flags = RATE_IN_4430 }, 366 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
367 { .div = 19, .val = 18, .flags = RATE_IN_4430 }, 367 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
368 { .div = 20, .val = 19, .flags = RATE_IN_4430 }, 368 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
369 { .div = 21, .val = 20, .flags = RATE_IN_4430 }, 369 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
370 { .div = 22, .val = 21, .flags = RATE_IN_4430 }, 370 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
371 { .div = 23, .val = 22, .flags = RATE_IN_4430 }, 371 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
372 { .div = 24, .val = 23, .flags = RATE_IN_4430 }, 372 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
373 { .div = 25, .val = 24, .flags = RATE_IN_4430 }, 373 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
374 { .div = 26, .val = 25, .flags = RATE_IN_4430 }, 374 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
375 { .div = 27, .val = 26, .flags = RATE_IN_4430 }, 375 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
376 { .div = 28, .val = 27, .flags = RATE_IN_4430 }, 376 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
377 { .div = 29, .val = 28, .flags = RATE_IN_4430 }, 377 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
378 { .div = 30, .val = 29, .flags = RATE_IN_4430 }, 378 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
379 { .div = 31, .val = 30, .flags = RATE_IN_4430 }, 379 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
380 { .div = 0 }, 380 { .div = 0 },
381}; 381};
382 382
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a26d6a08ae3f..12f0cbfc2894 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -137,7 +137,7 @@ return_sleep_time:
137 local_irq_enable(); 137 local_irq_enable();
138 local_fiq_enable(); 138 local_fiq_enable();
139 139
140 return (u32)timespec_to_ns(&ts_idle)/1000; 140 return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
141} 141}
142 142
143/** 143/**
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index bd8cb5974726..3f1334f62e7a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -534,6 +534,8 @@ void __init gpmc_init(void)
534 BUG(); 534 BUG();
535 } 535 }
536 536
537 clk_enable(gpmc_l3_clk);
538
537 l = gpmc_read_reg(GPMC_REVISION); 539 l = gpmc_read_reg(GPMC_REVISION);
538 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 540 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
539 /* Set smart idle mode and automatic L3 clock gating */ 541 /* Set smart idle mode and automatic L3 clock gating */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a091b53657b9..3d65c50bd017 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -188,6 +188,8 @@ void __init omap3_check_revision(void)
188 u16 hawkeye; 188 u16 hawkeye;
189 u8 rev; 189 u8 rev;
190 190
191 omap_chip.oc = CHIP_IS_OMAP3430;
192
191 /* 193 /*
192 * We cannot access revision registers on ES1.0. 194 * We cannot access revision registers on ES1.0.
193 * If the processor type is Cortex-A8 and the revision is 0x0 195 * If the processor type is Cortex-A8 and the revision is 0x0
@@ -196,6 +198,7 @@ void __init omap3_check_revision(void)
196 cpuid = read_cpuid(CPUID_ID); 198 cpuid = read_cpuid(CPUID_ID);
197 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 199 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
198 omap_revision = OMAP3430_REV_ES1_0; 200 omap_revision = OMAP3430_REV_ES1_0;
201 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
199 return; 202 return;
200 } 203 }
201 204
@@ -216,18 +219,28 @@ void __init omap3_check_revision(void)
216 case 0: /* Take care of early samples */ 219 case 0: /* Take care of early samples */
217 case 1: 220 case 1:
218 omap_revision = OMAP3430_REV_ES2_0; 221 omap_revision = OMAP3430_REV_ES2_0;
222 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
219 break; 223 break;
220 case 2: 224 case 2:
221 omap_revision = OMAP3430_REV_ES2_1; 225 omap_revision = OMAP3430_REV_ES2_1;
226 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
222 break; 227 break;
223 case 3: 228 case 3:
224 omap_revision = OMAP3430_REV_ES3_0; 229 omap_revision = OMAP3430_REV_ES3_0;
230 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
225 break; 231 break;
226 case 4: 232 case 4:
233 omap_revision = OMAP3430_REV_ES3_1;
234 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
235 break;
236 case 7:
227 /* FALLTHROUGH */ 237 /* FALLTHROUGH */
228 default: 238 default:
229 /* Use the latest known revision as default */ 239 /* Use the latest known revision as default */
230 omap_revision = OMAP3430_REV_ES3_1; 240 omap_revision = OMAP3430_REV_ES3_1_2;
241
242 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
243 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
231 } 244 }
232 break; 245 break;
233 case 0xb868: 246 case 0xb868:
@@ -235,14 +248,18 @@ void __init omap3_check_revision(void)
235 * 248 *
236 * Set the device to be OMAP3505 here. Actual device 249 * Set the device to be OMAP3505 here. Actual device
237 * is identified later based on the features. 250 * is identified later based on the features.
251 *
252 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
238 */ 253 */
239 omap_revision = OMAP3505_REV(rev); 254 omap_revision = OMAP3505_REV(rev);
255 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
240 break; 256 break;
241 case 0xb891: 257 case 0xb891:
242 /* FALLTHROUGH */ 258 /* FALLTHROUGH */
243 default: 259 default:
244 /* Unknown default to latest silicon rev as default*/ 260 /* Unknown default to latest silicon rev as default*/
245 omap_revision = OMAP3630_REV_ES1_0; 261 omap_revision = OMAP3630_REV_ES1_0;
262 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
246 } 263 }
247} 264}
248 265
@@ -360,6 +377,7 @@ void __init omap2_check_revision(void)
360 omap3_check_revision(); 377 omap3_check_revision();
361 omap3_check_features(); 378 omap3_check_features();
362 omap3_cpuinfo(); 379 omap3_cpuinfo();
380 return;
363 } else if (cpu_is_omap44xx()) { 381 } else if (cpu_is_omap44xx()) {
364 omap4_check_revision(); 382 omap4_check_revision();
365 return; 383 return;
@@ -374,27 +392,14 @@ void __init omap2_check_revision(void)
374 if (cpu_is_omap243x()) { 392 if (cpu_is_omap243x()) {
375 /* Currently only supports 2430ES2.1 and 2430-all */ 393 /* Currently only supports 2430ES2.1 and 2430-all */
376 omap_chip.oc |= CHIP_IS_OMAP2430; 394 omap_chip.oc |= CHIP_IS_OMAP2430;
395 return;
377 } else if (cpu_is_omap242x()) { 396 } else if (cpu_is_omap242x()) {
378 /* Currently only supports 2420ES2.1.1 and 2420-all */ 397 /* Currently only supports 2420ES2.1.1 and 2420-all */
379 omap_chip.oc |= CHIP_IS_OMAP2420; 398 omap_chip.oc |= CHIP_IS_OMAP2420;
380 } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 399 return;
381 omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
382 } else if (cpu_is_omap343x()) {
383 omap_chip.oc = CHIP_IS_OMAP3430;
384 if (omap_rev() == OMAP3430_REV_ES1_0)
385 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
386 else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
387 omap_rev() <= OMAP3430_REV_ES2_1)
388 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
389 else if (omap_rev() == OMAP3430_REV_ES3_0)
390 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
391 else if (omap_rev() == OMAP3430_REV_ES3_1)
392 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
393 else if (omap_rev() == OMAP3630_REV_ES1_0)
394 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
395 } else {
396 pr_err("Uninitialized omap_chip, please fix!\n");
397 } 400 }
401
402 pr_err("Uninitialized omap_chip, please fix!\n");
398} 403}
399 404
400/* 405/*
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e9bc782fa414..27054025da2b 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -274,4 +274,22 @@ void omap_intc_restore_context(void)
274 } 274 }
275 /* MIRs are saved and restore with other PRCM registers */ 275 /* MIRs are saved and restore with other PRCM registers */
276} 276}
277
278void omap3_intc_suspend(void)
279{
280 /* A pending interrupt would prevent OMAP from entering suspend */
281 omap_ack_irq(0);
282}
283
284void omap3_intc_prepare_idle(void)
285{
286 /* Disable autoidle as it can stall interrupt controller */
287 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
288}
289
290void omap3_intc_resume_idle(void)
291{
292 /* Re-enable autoidle */
293 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
294}
277#endif /* CONFIG_ARCH_OMAP3 */ 295#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 459ef23ab8a8..3f59bd12cbbf 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -51,7 +51,7 @@ struct omap_mux_entry {
51static unsigned long mux_phys; 51static unsigned long mux_phys;
52static void __iomem *mux_base; 52static void __iomem *mux_base;
53 53
54static inline u16 omap_mux_read(u16 reg) 54u16 omap_mux_read(u16 reg)
55{ 55{
56 if (cpu_is_omap24xx()) 56 if (cpu_is_omap24xx())
57 return __raw_readb(mux_base + reg); 57 return __raw_readb(mux_base + reg);
@@ -59,7 +59,7 @@ static inline u16 omap_mux_read(u16 reg)
59 return __raw_readw(mux_base + reg); 59 return __raw_readw(mux_base + reg);
60} 60}
61 61
62static inline void omap_mux_write(u16 val, u16 reg) 62void omap_mux_write(u16 val, u16 reg)
63{ 63{
64 if (cpu_is_omap24xx()) 64 if (cpu_is_omap24xx())
65 __raw_writeb(val, mux_base + reg); 65 __raw_writeb(val, mux_base + reg);
@@ -67,6 +67,14 @@ static inline void omap_mux_write(u16 val, u16 reg)
67 __raw_writew(val, mux_base + reg); 67 __raw_writew(val, mux_base + reg);
68} 68}
69 69
70void omap_mux_write_array(struct omap_board_mux *board_mux)
71{
72 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
73 omap_mux_write(board_mux->value, board_mux->reg_offset);
74 board_mux++;
75 }
76}
77
70#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) 78#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
71 79
72static struct omap_mux_cfg arch_mux_cfg; 80static struct omap_mux_cfg arch_mux_cfg;
@@ -833,14 +841,6 @@ static void __init omap_mux_set_cmdline_signals(void)
833 kfree(options); 841 kfree(options);
834} 842}
835 843
836static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
837{
838 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
839 omap_mux_write(board_mux->value, board_mux->reg_offset);
840 board_mux++;
841 }
842}
843
844static int __init omap_mux_copy_names(struct omap_mux *src, 844static int __init omap_mux_copy_names(struct omap_mux *src,
845 struct omap_mux *dst) 845 struct omap_mux *dst)
846{ 846{
@@ -998,12 +998,15 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
998 omap_mux_package_fixup(package_subset, superset); 998 omap_mux_package_fixup(package_subset, superset);
999 if (package_balls) 999 if (package_balls)
1000 omap_mux_package_init_balls(package_balls, superset); 1000 omap_mux_package_init_balls(package_balls, superset);
1001 omap_mux_set_cmdline_signals();
1002 omap_mux_set_board_signals(board_mux);
1003#endif 1001#endif
1004 1002
1005 omap_mux_init_list(superset); 1003 omap_mux_init_list(superset);
1006 1004
1005#ifdef CONFIG_OMAP_MUX
1006 omap_mux_set_cmdline_signals();
1007 omap_mux_write_array(board_mux);
1008#endif
1009
1007 return 0; 1010 return 0;
1008} 1011}
1009 1012
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index d8b4d5ad2278..f8c2e7a8f063 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -147,6 +147,30 @@ u16 omap_mux_get_gpio(int gpio);
147void omap_mux_set_gpio(u16 val, int gpio); 147void omap_mux_set_gpio(u16 val, int gpio);
148 148
149/** 149/**
150 * omap_mux_read() - read mux register
151 * @mux_offset: Offset of the mux register
152 *
153 */
154u16 omap_mux_read(u16 mux_offset);
155
156/**
157 * omap_mux_write() - write mux register
158 * @val: New mux register value
159 * @mux_offset: Offset of the mux register
160 *
161 * This should be only needed for dynamic remuxing of non-gpio signals.
162 */
163void omap_mux_write(u16 val, u16 mux_offset);
164
165/**
166 * omap_mux_write_array() - write an array of mux registers
167 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
168 *
169 * This should be only needed for dynamic remuxing of non-gpio signals.
170 */
171void omap_mux_write_array(struct omap_board_mux *board_mux);
172
173/**
150 * omap3_mux_init() - initialize mux system with board specific set 174 * omap3_mux_init() - initialize mux system with board specific set
151 * @board_mux: Board specific mux table 175 * @board_mux: Board specific mux table
152 * @flags: OMAP package type used for the board 176 * @flags: OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d8c8545875b1..478ae585ca39 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
94 94
95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); 95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
96 96
97 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; 97 if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
98 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
98 99
99 return 0; 100 return 0;
100} 101}
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 860b755d2220..a0866268aa41 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -54,8 +54,6 @@ int omap2_pm_debug;
54 regs[reg_count++].val = \ 54 regs[reg_count++].val = \
55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) 55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
56 56
57static int __init pm_dbg_init(void);
58
59void omap2_pm_dump(int mode, int resume, unsigned int us) 57void omap2_pm_dump(int mode, int resume, unsigned int us)
60{ 58{
61 struct reg { 59 struct reg {
@@ -167,6 +165,8 @@ struct dentry *pm_dbg_dir;
167 165
168static int pm_dbg_init_done; 166static int pm_dbg_init_done;
169 167
168static int __init pm_dbg_init(void);
169
170enum { 170enum {
171 DEBUG_FILE_COUNTERS = 0, 171 DEBUG_FILE_COUNTERS = 0,
172 DEBUG_FILE_TIMERS, 172 DEBUG_FILE_TIMERS,
@@ -488,9 +488,11 @@ int pm_dbg_regset_init(int reg_set)
488 488
489static int pwrdm_suspend_get(void *data, u64 *val) 489static int pwrdm_suspend_get(void *data, u64 *val)
490{ 490{
491 *val = omap3_pm_get_suspend_state((struct powerdomain *)data); 491 int ret;
492 ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
493 *val = ret;
492 494
493 if (*val >= 0) 495 if (ret >= 0)
494 return 0; 496 return 0;
495 return *val; 497 return *val;
496} 498}
@@ -604,6 +606,4 @@ static int __init pm_dbg_init(void)
604} 606}
605arch_initcall(pm_dbg_init); 607arch_initcall(pm_dbg_init);
606 608
607#else
608void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
609#endif 609#endif
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0bf345db7147..7a9c2d004511 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -32,12 +32,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
32#ifdef CONFIG_PM_DEBUG 32#ifdef CONFIG_PM_DEBUG
33extern void omap2_pm_dump(int mode, int resume, unsigned int us); 33extern void omap2_pm_dump(int mode, int resume, unsigned int us);
34extern int omap2_pm_debug; 34extern int omap2_pm_debug;
35#else
36#define omap2_pm_dump(mode, resume, us) do {} while (0);
37#define omap2_pm_debug 0
38#endif
39
40#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
35extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); 41extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
36extern int pm_dbg_regset_save(int reg_set); 42extern int pm_dbg_regset_save(int reg_set);
37extern int pm_dbg_regset_init(int reg_set); 43extern int pm_dbg_regset_init(int reg_set);
38#else 44#else
39#define omap2_pm_dump(mode, resume, us) do {} while (0);
40#define omap2_pm_debug 0
41#define pm_dbg_update_time(pwrdm, prev) do {} while (0); 45#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
42#define pm_dbg_regset_save(reg_set) do {} while (0); 46#define pm_dbg_regset_save(reg_set) do {} while (0);
43#define pm_dbg_regset_init(reg_set) do {} while (0); 47#define pm_dbg_regset_init(reg_set) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c6cc809afb79..910a7acf542d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -26,6 +26,7 @@
26#include <linux/err.h> 26#include <linux/err.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/delay.h>
29 30
30#include <plat/sram.h> 31#include <plat/sram.h>
31#include <plat/clockdomain.h> 32#include <plat/clockdomain.h>
@@ -126,7 +127,15 @@ static void omap3_core_save_context(void)
126 /* wait for the save to complete */ 127 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 128 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE)) 129 & PADCONF_SAVE_DONE))
129 ; 130 udelay(1);
131
132 /*
133 * Force write last pad into memory, as this can fail in some
134 * cases according to erratas 1.157, 1.185
135 */
136 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
137 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
138
130 /* Save the Interrupt controller context */ 139 /* Save the Interrupt controller context */
131 omap_intc_save_context(); 140 omap_intc_save_context();
132 /* Save the GPMC context */ 141 /* Save the GPMC context */
@@ -392,6 +401,7 @@ void omap_sram_idle(void)
392 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 401 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
393 omap3_enable_io_chain(); 402 omap3_enable_io_chain();
394 } 403 }
404 omap3_intc_prepare_idle();
395 405
396 /* 406 /*
397 * On EMU/HS devices ROM code restores a SRDC value 407 * On EMU/HS devices ROM code restores a SRDC value
@@ -438,6 +448,7 @@ void omap_sram_idle(void)
438 OMAP3430_GR_MOD, 448 OMAP3430_GR_MOD,
439 OMAP3_PRM_VOLTCTRL_OFFSET); 449 OMAP3_PRM_VOLTCTRL_OFFSET);
440 } 450 }
451 omap3_intc_resume_idle();
441 452
442 /* PER */ 453 /* PER */
443 if (per_next_state < PWRDM_POWER_ON) { 454 if (per_next_state < PWRDM_POWER_ON) {
@@ -578,6 +589,8 @@ static int omap3_pm_suspend(void)
578 } 589 }
579 590
580 omap_uart_prepare_suspend(); 591 omap_uart_prepare_suspend();
592 omap3_intc_suspend();
593
581 omap_sram_idle(); 594 omap_sram_idle();
582 595
583restore: 596restore:
@@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void)
835 CM_AUTOIDLE); 848 CM_AUTOIDLE);
836 } 849 }
837 850
851 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
852
838 /* 853 /*
839 * Set all plls to autoidle. This is needed until autoidle is 854 * Set all plls to autoidle. This is needed until autoidle is
840 * enabled by clockfw 855 * enabled by clockfw
@@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void)
875 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 890 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
876 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 891 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
877 892
893 /* Enable PM_WKEN to support DSS LPR */
894 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
895 OMAP3430_DSS_MOD, PM_WKEN);
896
878 /* Enable wakeups in PER */ 897 /* Enable wakeups in PER */
879 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 898 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
880 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 899 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
881 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 900 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
901 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
902 OMAP3430_EN_MCBSP4,
882 OMAP3430_PER_MOD, PM_WKEN); 903 OMAP3430_PER_MOD, PM_WKEN);
883 /* and allow them to wake up MPU */ 904 /* and allow them to wake up MPU */
884 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 905 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
885 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 906 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
886 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 907 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
908 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
909 OMAP3430_EN_MCBSP4,
887 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 910 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
888 911
889 /* Don't attach IVA interrupts */ 912 /* Don't attach IVA interrupts */
@@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void)
904 /* Clear any pending PRCM interrupts */ 927 /* Clear any pending PRCM interrupts */
905 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 928 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
906 929
907 /* Don't attach IVA interrupts */
908 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
909 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
910 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
911 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
912
913 /* Clear any pending 'reset' flags */
914 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
915 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
916 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
917 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
918 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
919 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
920 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
921
922 /* Clear any pending PRCM interrupts */
923 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
924
925 omap3_iva_idle(); 930 omap3_iva_idle();
926 omap3_d2d_idle(); 931 omap3_d2d_idle();
927} 932}
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 3ea8177ffb25..cf466ea1dffc 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -44,7 +44,6 @@ struct omap3_prcm_regs {
44 u32 iva2_cm_clksel2; 44 u32 iva2_cm_clksel2;
45 u32 cm_sysconfig; 45 u32 cm_sysconfig;
46 u32 sgx_cm_clksel; 46 u32 sgx_cm_clksel;
47 u32 wkup_cm_clksel;
48 u32 dss_cm_clksel; 47 u32 dss_cm_clksel;
49 u32 cam_cm_clksel; 48 u32 cam_cm_clksel;
50 u32 per_cm_clksel; 49 u32 per_cm_clksel;
@@ -53,7 +52,6 @@ struct omap3_prcm_regs {
53 u32 pll_cm_autoidle2; 52 u32 pll_cm_autoidle2;
54 u32 pll_cm_clksel4; 53 u32 pll_cm_clksel4;
55 u32 pll_cm_clksel5; 54 u32 pll_cm_clksel5;
56 u32 pll_cm_clken;
57 u32 pll_cm_clken2; 55 u32 pll_cm_clken2;
58 u32 cm_polctrl; 56 u32 cm_polctrl;
59 u32 iva2_cm_fclken; 57 u32 iva2_cm_fclken;
@@ -77,7 +75,6 @@ struct omap3_prcm_regs {
77 u32 usbhost_cm_iclken; 75 u32 usbhost_cm_iclken;
78 u32 iva2_cm_autiidle2; 76 u32 iva2_cm_autiidle2;
79 u32 mpu_cm_autoidle2; 77 u32 mpu_cm_autoidle2;
80 u32 pll_cm_autoidle;
81 u32 iva2_cm_clkstctrl; 78 u32 iva2_cm_clkstctrl;
82 u32 mpu_cm_clkstctrl; 79 u32 mpu_cm_clkstctrl;
83 u32 core_cm_clkstctrl; 80 u32 core_cm_clkstctrl;
@@ -274,7 +271,6 @@ void omap3_prcm_save_context(void)
274 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 271 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
275 prcm_context.sgx_cm_clksel = 272 prcm_context.sgx_cm_clksel =
276 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 273 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
277 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
278 prcm_context.dss_cm_clksel = 274 prcm_context.dss_cm_clksel =
279 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); 275 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
280 prcm_context.cam_cm_clksel = 276 prcm_context.cam_cm_clksel =
@@ -291,8 +287,6 @@ void omap3_prcm_save_context(void)
291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); 287 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
292 prcm_context.pll_cm_clksel5 = 288 prcm_context.pll_cm_clksel5 =
293 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 289 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
294 prcm_context.pll_cm_clken =
295 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
296 prcm_context.pll_cm_clken2 = 290 prcm_context.pll_cm_clken2 =
297 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
298 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); 292 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
@@ -338,8 +332,6 @@ void omap3_prcm_save_context(void)
338 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 332 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
339 prcm_context.mpu_cm_autoidle2 = 333 prcm_context.mpu_cm_autoidle2 =
340 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); 334 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
341 prcm_context.pll_cm_autoidle =
342 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
343 prcm_context.iva2_cm_clkstctrl = 335 prcm_context.iva2_cm_clkstctrl =
344 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); 336 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
345 prcm_context.mpu_cm_clkstctrl = 337 prcm_context.mpu_cm_clkstctrl =
@@ -431,7 +423,6 @@ void omap3_prcm_restore_context(void)
431 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 423 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
432 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 424 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
433 CM_CLKSEL); 425 CM_CLKSEL);
434 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
435 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 426 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
436 CM_CLKSEL); 427 CM_CLKSEL);
437 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, 428 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
@@ -448,7 +439,6 @@ void omap3_prcm_restore_context(void)
448 OMAP3430ES2_CM_CLKSEL4); 439 OMAP3430ES2_CM_CLKSEL4);
449 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, 440 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
450 OMAP3430ES2_CM_CLKSEL5); 441 OMAP3430ES2_CM_CLKSEL5);
451 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
452 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, 442 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
453 OMAP3430ES2_CM_CLKEN2); 443 OMAP3430ES2_CM_CLKEN2);
454 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); 444 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
@@ -487,7 +477,6 @@ void omap3_prcm_restore_context(void)
487 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, 477 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
488 CM_AUTOIDLE2); 478 CM_AUTOIDLE2);
489 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); 479 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
490 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
491 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, 480 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
492 CM_CLKSTCTRL); 481 CM_CLKSTCTRL);
493 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); 482 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ea050ce188a7..40f006285163 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,6 +24,8 @@
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25#define OMAP44XX_PRM_REGADDR(module, reg) \ 25#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
27#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
27 29
28#include "prm44xx.h" 30#include "prm44xx.h"
29 31
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 89be97f0589d..adb2558bb121 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -386,26 +386,26 @@
386 386
387 387
388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ 388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
389#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) 389#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
390 390
391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ 391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) 392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
393 393
394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ 394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) 395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) 396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) 397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) 398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) 399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) 400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) 401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
402 402
403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ 403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) 404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) 405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) 406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) 407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) 408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) 409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) 410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
411#endif 411#endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 15268f8b61de..c3626ea48143 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -245,7 +245,8 @@ restore:
245 mov r1, #0 @ set task id for ROM code in r1 245 mov r1, #0 @ set task id for ROM code in r1
246 mov r2, #4 @ set some flags in r2, r6 246 mov r2, #4 @ set some flags in r2, r6
247 mov r6, #0xff 247 mov r6, #0xff
248 adr r3, write_aux_control_params @ r3 points to parameters 248 ldr r4, scratchpad_base
249 ldr r3, [r4, #0xBC] @ r3 points to parameters
249 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 250 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
250 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 251 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
251 .word 0xE1600071 @ call SMI monitor (smi #1) 252 .word 0xE1600071 @ call SMI monitor (smi #1)
@@ -253,14 +254,14 @@ restore:
253 b logic_l1_restore 254 b logic_l1_restore
254l2_inv_api_params: 255l2_inv_api_params:
255 .word 0x1, 0x00 256 .word 0x1, 0x00
256write_aux_control_params:
257 .word 0x1, 0x72
258l2_inv_gp: 257l2_inv_gp:
259 /* Execute smi to invalidate L2 cache */ 258 /* Execute smi to invalidate L2 cache */
260 mov r12, #0x1 @ set up to invalide L2 259 mov r12, #0x1 @ set up to invalide L2
261smi: .word 0xE1600070 @ Call SMI monitor (smieq) 260smi: .word 0xE1600070 @ Call SMI monitor (smieq)
262 /* Write to Aux control register to set some bits */ 261 /* Write to Aux control register to set some bits */
263 mov r0, #0x72 262 ldr r4, scratchpad_base
263 ldr r3, [r4,#0xBC]
264 ldr r0, [r3,#4]
264 mov r12, #0x3 265 mov r12, #0x3
265 .word 0xE1600070 @ Call SMI monitor (smieq) 266 .word 0xE1600070 @ Call SMI monitor (smieq)
266logic_l1_restore: 267logic_l1_restore:
@@ -271,6 +272,7 @@ logic_l1_restore:
271 272
272 ldr r4, scratchpad_base 273 ldr r4, scratchpad_base
273 ldr r3, [r4,#0xBC] 274 ldr r3, [r4,#0xBC]
275 adds r3, r3, #8
274 ldmia r3!, {r4-r6} 276 ldmia r3!, {r4-r6}
275 mov sp, r4 277 mov sp, r4
276 msr spsr_cxsf, r5 278 msr spsr_cxsf, r5
@@ -387,6 +389,9 @@ usettbr0:
387save_context_wfi: 389save_context_wfi:
388 /*b save_context_wfi*/ @ enable to debug save code 390 /*b save_context_wfi*/ @ enable to debug save code
389 mov r8, r0 /* Store SDRAM address in r8 */ 391 mov r8, r0 /* Store SDRAM address in r8 */
392 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
393 mov r4, #0x1 @ Number of parameters for restore call
394 stmia r8!, {r4-r5}
390 /* Check what that target sleep state is:stored in r1*/ 395 /* Check what that target sleep state is:stored in r1*/
391 /* 1 - Only L1 and logic lost */ 396 /* 1 - Only L1 and logic lost */
392 /* 2 - Only L2 lost */ 397 /* 2 - Only L2 lost */
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
index cdd4b5378552..7619456f2ae8 100644
--- a/arch/arm/mach-s3c6410/mach-hmt.c
+++ b/arch/arm/mach-s3c6410/mach-hmt.c
@@ -82,7 +82,7 @@ static int hmt_bl_init(struct device *dev)
82 return ret; 82 return ret;
83} 83}
84 84
85static int hmt_bl_notify(int brightness) 85static int hmt_bl_notify(struct device *dev, int brightness)
86{ 86{
87 /* 87 /*
88 * translate from CIELUV/CIELAB L*->brightness, E.G. from 88 * translate from CIELUV/CIELAB L*->brightness, E.G. from
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bf1eaf3a27d4..dddc0273bc8b 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -172,6 +172,32 @@ unsigned long long sched_clock(void)
172 clocksource_32k.mult, clocksource_32k.shift); 172 clocksource_32k.mult, clocksource_32k.shift);
173} 173}
174 174
175/**
176 * read_persistent_clock - Return time from a persistent clock.
177 *
178 * Reads the time from a source which isn't disabled during PM, the
179 * 32k sync timer. Convert the cycles elapsed since last read into
180 * nsecs and adds to a monotonically increasing timespec.
181 */
182static struct timespec persistent_ts;
183static cycles_t cycles, last_cycles;
184void read_persistent_clock(struct timespec *ts)
185{
186 unsigned long long nsecs;
187 cycles_t delta;
188 struct timespec *tsp = &persistent_ts;
189
190 last_cycles = cycles;
191 cycles = clocksource_32k.read(&clocksource_32k);
192 delta = cycles - last_cycles;
193
194 nsecs = clocksource_cyc2ns(delta,
195 clocksource_32k.mult, clocksource_32k.shift);
196
197 timespec_add_ns(tsp, nsecs);
198 *ts = *tsp;
199}
200
175static int __init omap_init_clocksource_32k(void) 201static int __init omap_init_clocksource_32k(void)
176{ 202{
177 static char err[] __initdata = KERN_ERR 203 static char err[] __initdata = KERN_ERR
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 09d82b3c66ce..728c64204184 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1183,7 +1183,7 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
1183 } 1183 }
1184 1184
1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1186 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1186 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1188 "before unlinking\n"); 1188 "before unlinking\n");
1189 dump_stack(); 1189 dump_stack();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 64f407ee0f4e..08ccf8922520 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -551,6 +551,19 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
551 if (l & OMAP_TIMER_CTRL_ST) { 551 if (l & OMAP_TIMER_CTRL_ST) {
552 l &= ~0x1; 552 l &= ~0x1;
553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
554#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
555 defined(CONFIG_ARCH_OMAP4)
556 /* Readback to make sure write has completed */
557 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
558 /*
559 * Wait for functional clock period x 3.5 to make sure that
560 * timer is stopped
561 */
562 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
563 /* Ack possibly pending interrupt */
564 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
565 OMAP_TIMER_INT_OVERFLOW);
566#endif
554 } 567 }
555} 568}
556EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 569EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 9a028bdebb06..a162f585b1e3 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -434,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517)
434#define OMAP3430_REV_ES2_1 0x34302034 434#define OMAP3430_REV_ES2_1 0x34302034
435#define OMAP3430_REV_ES3_0 0x34303034 435#define OMAP3430_REV_ES3_0 0x34303034
436#define OMAP3430_REV_ES3_1 0x34304034 436#define OMAP3430_REV_ES3_1 0x34304034
437#define OMAP3430_REV_ES3_1_2 0x34305034
437 438
438#define OMAP3630_REV_ES1_0 0x36300034 439#define OMAP3630_REV_ES1_0 0x36300034
439 440
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 97d6c50c3dcb..c0ab7c80f72e 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -499,6 +499,9 @@ extern void omap_init_irq(void);
499extern int omap_irq_pending(void); 499extern int omap_irq_pending(void);
500void omap_intc_save_context(void); 500void omap_intc_save_context(void);
501void omap_intc_restore_context(void); 501void omap_intc_restore_context(void);
502void omap3_intc_suspend(void);
503void omap3_intc_prepare_idle(void);
504void omap3_intc_resume_idle(void);
502#endif 505#endif
503 506
504#include <mach/hardware.h> 507#include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 007935a921ea..33933256a226 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -227,6 +227,7 @@ struct omap_hwmod_ocp_if {
227#define SYSC_HAS_SIDLEMODE (1 << 5) 227#define SYSC_HAS_SIDLEMODE (1 << 5)
228#define SYSC_HAS_MIDLEMODE (1 << 6) 228#define SYSC_HAS_MIDLEMODE (1 << 6)
229#define SYSS_MISSING (1 << 7) 229#define SYSS_MISSING (1 << 7)
230#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
230 231
231/* omap_hwmod_sysconfig.clockact flags */ 232/* omap_hwmod_sysconfig.clockact flags */
232#define CLOCKACT_TEST_BOTH 0x0 233#define CLOCKACT_TEST_BOTH 0x0
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index e3654d683e15..75bf820e7ccb 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -226,7 +226,6 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
226 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 226 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
227 temp &= ~(I2CR_MSTA | I2CR_MTX); 227 temp &= ~(I2CR_MSTA | I2CR_MTX);
228 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 228 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
229 i2c_imx->stopped = 1;
230 } 229 }
231 if (cpu_is_mx1()) { 230 if (cpu_is_mx1()) {
232 /* 231 /*
@@ -236,8 +235,10 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
236 udelay(i2c_imx->disable_delay); 235 udelay(i2c_imx->disable_delay);
237 } 236 }
238 237
239 if (!i2c_imx->stopped) 238 if (!i2c_imx->stopped) {
240 i2c_imx_bus_busy(i2c_imx, 0); 239 i2c_imx_bus_busy(i2c_imx, 0);
240 i2c_imx->stopped = 1;
241 }
241 242
242 /* Disable I2C controller */ 243 /* Disable I2C controller */
243 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 244 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
@@ -496,22 +497,23 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
496 } 497 }
497 498
498 res_size = resource_size(res); 499 res_size = resource_size(res);
500
501 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
502 ret = -EBUSY;
503 goto fail0;
504 }
505
499 base = ioremap(res->start, res_size); 506 base = ioremap(res->start, res_size);
500 if (!base) { 507 if (!base) {
501 dev_err(&pdev->dev, "ioremap failed\n"); 508 dev_err(&pdev->dev, "ioremap failed\n");
502 ret = -EIO; 509 ret = -EIO;
503 goto fail0; 510 goto fail1;
504 } 511 }
505 512
506 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL); 513 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
507 if (!i2c_imx) { 514 if (!i2c_imx) {
508 dev_err(&pdev->dev, "can't allocate interface\n"); 515 dev_err(&pdev->dev, "can't allocate interface\n");
509 ret = -ENOMEM; 516 ret = -ENOMEM;
510 goto fail1;
511 }
512
513 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
514 ret = -EBUSY;
515 goto fail2; 517 goto fail2;
516 } 518 }
517 519
@@ -582,11 +584,11 @@ fail5:
582fail4: 584fail4:
583 clk_put(i2c_imx->clk); 585 clk_put(i2c_imx->clk);
584fail3: 586fail3:
585 release_mem_region(i2c_imx->res->start, resource_size(res));
586fail2:
587 kfree(i2c_imx); 587 kfree(i2c_imx);
588fail1: 588fail2:
589 iounmap(base); 589 iounmap(base);
590fail1:
591 release_mem_region(res->start, resource_size(res));
590fail0: 592fail0:
591 if (pdata && pdata->exit) 593 if (pdata && pdata->exit)
592 pdata->exit(&pdev->dev); 594 pdata->exit(&pdev->dev);
@@ -618,8 +620,8 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
618 620
619 clk_put(i2c_imx->clk); 621 clk_put(i2c_imx->clk);
620 622
621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
622 iounmap(i2c_imx->base); 623 iounmap(i2c_imx->base);
624 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
623 kfree(i2c_imx); 625 kfree(i2c_imx);
624 return 0; 626 return 0;
625} 627}
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 4c364d44ad59..2de0cc823d60 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -549,4 +549,21 @@ config MTD_VMU
549 To build this as a module select M here, the module will be called 549 To build this as a module select M here, the module will be called
550 vmu-flash. 550 vmu-flash.
551 551
552config MTD_PISMO
553 tristate "MTD discovery driver for PISMO modules"
554 depends on I2C
555 depends on ARCH_VERSATILE
556 help
557 This driver allows for discovery of PISMO modules - see
558 <http://www.pismoworld.org/>. These are small modules containing
559 up to five memory devices (eg, SRAM, flash, DOC) described by an
560 I2C EEPROM.
561
562 This driver does not create any MTD maps itself; instead it
563 creates MTD physmap and MTD SRAM platform devices. If you
564 enable this option, you should consider enabling MTD_PHYSMAP
565 and/or MTD_PLATRAM according to the devices on your module.
566
567 When built as a module, it will be called pismo.ko
568
552endmenu 569endmenu
diff --git a/drivers/mtd/maps/pismo.c b/drivers/mtd/maps/pismo.c
new file mode 100644
index 000000000000..c48cad271f5d
--- /dev/null
+++ b/drivers/mtd/maps/pismo.c
@@ -0,0 +1,320 @@
1/*
2 * PISMO memory driver - http://www.pismoworld.org/
3 *
4 * For ARM Realview and Versatile platforms
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/i2c.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15#include <linux/mutex.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mtd/plat-ram.h>
18#include <linux/mtd/pismo.h>
19
20#define PISMO_NUM_CS 5
21
22struct pismo_cs_block {
23 u8 type;
24 u8 width;
25 __le16 access;
26 __le32 size;
27 u32 reserved[2];
28 char device[32];
29} __packed;
30
31struct pismo_eeprom {
32 struct pismo_cs_block cs[PISMO_NUM_CS];
33 char board[15];
34 u8 sum;
35} __packed;
36
37struct pismo_mem {
38 phys_addr_t base;
39 u32 size;
40 u16 access;
41 u8 width;
42 u8 type;
43};
44
45struct pismo_data {
46 struct i2c_client *client;
47 void (*vpp)(void *, int);
48 void *vpp_data;
49 struct platform_device *dev[PISMO_NUM_CS];
50};
51
52/* FIXME: set_vpp could do with a better calling convention */
53static struct pismo_data *vpp_pismo;
54static DEFINE_MUTEX(pismo_mutex);
55
56static int pismo_setvpp_probe_fix(struct pismo_data *pismo)
57{
58 mutex_lock(&pismo_mutex);
59 if (vpp_pismo) {
60 mutex_unlock(&pismo_mutex);
61 kfree(pismo);
62 return -EBUSY;
63 }
64 vpp_pismo = pismo;
65 mutex_unlock(&pismo_mutex);
66 return 0;
67}
68
69static void pismo_setvpp_remove_fix(struct pismo_data *pismo)
70{
71 mutex_lock(&pismo_mutex);
72 if (vpp_pismo == pismo)
73 vpp_pismo = NULL;
74 mutex_unlock(&pismo_mutex);
75}
76
77static void pismo_set_vpp(struct map_info *map, int on)
78{
79 struct pismo_data *pismo = vpp_pismo;
80
81 pismo->vpp(pismo->vpp_data, on);
82}
83/* end of hack */
84
85
86static unsigned int __devinit pismo_width_to_bytes(unsigned int width)
87{
88 width &= 15;
89 if (width > 2)
90 return 0;
91 return 1 << width;
92}
93
94static int __devinit pismo_eeprom_read(struct i2c_client *client, void *buf,
95 u8 addr, size_t size)
96{
97 int ret;
98 struct i2c_msg msg[] = {
99 {
100 .addr = client->addr,
101 .len = sizeof(addr),
102 .buf = &addr,
103 }, {
104 .addr = client->addr,
105 .flags = I2C_M_RD,
106 .len = size,
107 .buf = buf,
108 },
109 };
110
111 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
112
113 return ret == ARRAY_SIZE(msg) ? size : -EIO;
114}
115
116static int __devinit pismo_add_device(struct pismo_data *pismo, int i,
117 struct pismo_mem *region, const char *name, void *pdata, size_t psize)
118{
119 struct platform_device *dev;
120 struct resource res = { };
121 phys_addr_t base = region.base;
122 int ret;
123
124 if (base == ~0)
125 return -ENXIO;
126
127 res.start = base;
128 res.end = base + region->size - 1;
129 res.flags = IORESOURCE_MEM;
130
131 dev = platform_device_alloc(name, i);
132 if (!dev)
133 return -ENOMEM;
134 dev->dev.parent = &pismo->client->dev;
135
136 do {
137 ret = platform_device_add_resources(dev, &res, 1);
138 if (ret)
139 break;
140
141 ret = platform_device_add_data(dev, pdata, psize);
142 if (ret)
143 break;
144
145 ret = platform_device_add(dev);
146 if (ret)
147 break;
148
149 pismo->dev[i] = dev;
150 return 0;
151 } while (0);
152
153 platform_device_put(dev);
154 return ret;
155}
156
157static int __devinit pismo_add_nor(struct pismo_data *pismo, int i,
158 struct pismo_mem *region)
159{
160 struct physmap_flash_data data = {
161 .width = region->width,
162 };
163
164 if (pismo->vpp)
165 data.set_vpp = pismo_set_vpp;
166
167 return pismo_add_device(pismo, i, region, "physmap-flash",
168 &data, sizeof(data));
169}
170
171static int __devinit pismo_add_sram(struct pismo_data *pismo, int i,
172 struct pismo_mem *region)
173{
174 struct platdata_mtd_ram data = {
175 .bankwidth = region->width,
176 };
177
178 return pismo_add_device(pismo, i, region, "mtd-ram",
179 &data, sizeof(data));
180}
181
182static void __devinit pismo_add_one(struct pismo_data *pismo, int i,
183 const struct pismo_cs_block *cs, phys_addr_t base)
184{
185 struct device *dev = &pismo->client->dev;
186 struct pismo_mem region;
187
188 region.base = base;
189 region.type = cs->type;
190 region.width = pismo_width_to_bytes(cs->width);
191 region.access = le16_to_cpu(cs->access);
192 region.size = le32_to_cpu(cs->size);
193
194 if (region.width == 0) {
195 dev_err(dev, "cs%u: bad width: %02x, ignoring\n", i, cs->width);
196 return;
197 }
198
199 /*
200 * FIXME: may need to the platforms memory controller here, but at
201 * the moment we assume that it has already been correctly setup.
202 * The memory controller can also tell us the base address as well.
203 */
204
205 dev_info(dev, "cs%u: %.32s: type %02x access %u00ps size %uK\n",
206 i, cs->device, region.type, region.access, region.size / 1024);
207
208 switch (region.type) {
209 case 0:
210 break;
211 case 1:
212 /* static DOC */
213 break;
214 case 2:
215 /* static NOR */
216 pismo_add_nor(pismo, i, &region);
217 break;
218 case 3:
219 /* static RAM */
220 pismo_add_sram(pismo, i, &region);
221 break;
222 }
223}
224
225static int __devexit pismo_remove(struct i2c_client *client)
226{
227 struct pismo_data *pismo = i2c_get_clientdata(client);
228 int i;
229
230 for (i = 0; i < ARRAY_SIZE(pismo->dev); i++)
231 platform_device_unregister(pismo->dev[i]);
232
233 /* FIXME: set_vpp needs saner arguments */
234 pismo_setvpp_remove_fix(pismo);
235
236 kfree(pismo);
237
238 return 0;
239}
240
241static int __devinit pismo_probe(struct i2c_client *client,
242 const struct i2c_device_id *id)
243{
244 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
245 struct pismo_pdata *pdata = client->dev.platform_data;
246 struct pismo_eeprom eeprom;
247 struct pismo_data *pismo;
248 int ret, i;
249
250 if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
251 dev_err(&client->dev, "functionality mismatch\n");
252 return -EIO;
253 }
254
255 pismo = kzalloc(sizeof(*pismo), GFP_KERNEL);
256 if (!pismo)
257 return -ENOMEM;
258
259 /* FIXME: set_vpp needs saner arguments */
260 ret = pismo_setvpp_probe_fix(pismo);
261 if (ret)
262 return ret;
263
264 pismo->client = client;
265 if (pdata) {
266 pismo->vpp = pdata->set_vpp;
267 pismo->vpp_data = pdata->vpp_data;
268 }
269 i2c_set_clientdata(client, pismo);
270
271 ret = pismo_eeprom_read(client, &eeprom, 0, sizeof(eeprom));
272 if (ret < 0) {
273 dev_err(&client->dev, "error reading EEPROM: %d\n", ret);
274 return ret;
275 }
276
277 dev_info(&client->dev, "%.15s board found\n", eeprom.board);
278
279 for (i = 0; i < ARRAY_SIZE(eeprom.cs); i++)
280 if (eeprom.cs[i].type != 0xff)
281 pismo_add_one(pismo, i, &eeprom.cs[i],
282 pdata->cs_addrs[i]);
283
284 return 0;
285}
286
287static const struct i2c_device_id pismo_id[] = {
288 { "pismo" },
289 { },
290};
291MODULE_DEVICE_TABLE(i2c, pismo_id);
292
293static struct i2c_driver pismo_driver = {
294 .driver = {
295 .name = "pismo",
296 .owner = THIS_MODULE,
297 },
298 .probe = pismo_probe,
299 .remove = __devexit_p(pismo_remove),
300 .id_table = pismo_id,
301};
302
303static int __init pismo_init(void)
304{
305 BUILD_BUG_ON(sizeof(struct pismo_cs_block) != 48);
306 BUILD_BUG_ON(sizeof(struct pismo_eeprom) != 256);
307
308 return i2c_add_driver(&pismo_driver);
309}
310module_init(pismo_init);
311
312static void __exit pismo_exit(void)
313{
314 i2c_del_driver(&pismo_driver);
315}
316module_exit(pismo_exit);
317
318MODULE_AUTHOR("Russell King <linux@arm.linux.org.uk>");
319MODULE_DESCRIPTION("PISMO memory driver");
320MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c
index a714ec482761..92e12df0917f 100644
--- a/drivers/mtd/mtdoops.c
+++ b/drivers/mtd/mtdoops.c
@@ -322,7 +322,7 @@ static void mtdoops_do_dump(struct kmsg_dumper *dumper,
322 memcpy(dst + l1_cpy, s2 + s2_start, l2_cpy); 322 memcpy(dst + l1_cpy, s2 + s2_start, l2_cpy);
323 323
324 /* Panics must be written immediately */ 324 /* Panics must be written immediately */
325 if (reason == KMSG_DUMP_PANIC) { 325 if (reason != KMSG_DUMP_OOPS) {
326 if (!cxt->mtd->panic_write) 326 if (!cxt->mtd->panic_write)
327 printk(KERN_ERR "mtdoops: Cannot write from panic without panic_write\n"); 327 printk(KERN_ERR "mtdoops: Cannot write from panic without panic_write\n");
328 else 328 else
diff --git a/drivers/mtd/tests/mtd_readtest.c b/drivers/mtd/tests/mtd_readtest.c
index 79fc4530987b..25c5dd03a837 100644
--- a/drivers/mtd/tests/mtd_readtest.c
+++ b/drivers/mtd/tests/mtd_readtest.c
@@ -147,6 +147,10 @@ static int scan_for_bad_eraseblocks(void)
147 } 147 }
148 memset(bbt, 0 , ebcnt); 148 memset(bbt, 0 , ebcnt);
149 149
150 /* NOR flash does not implement block_isbad */
151 if (mtd->block_isbad == NULL)
152 return 0;
153
150 printk(PRINT_PREF "scanning for bad eraseblocks\n"); 154 printk(PRINT_PREF "scanning for bad eraseblocks\n");
151 for (i = 0; i < ebcnt; ++i) { 155 for (i = 0; i < ebcnt; ++i) {
152 bbt[i] = is_block_bad(i) ? 1 : 0; 156 bbt[i] = is_block_bad(i) ? 1 : 0;
@@ -184,7 +188,7 @@ static int __init mtd_readtest_init(void)
184 tmp = mtd->size; 188 tmp = mtd->size;
185 do_div(tmp, mtd->erasesize); 189 do_div(tmp, mtd->erasesize);
186 ebcnt = tmp; 190 ebcnt = tmp;
187 pgcnt = mtd->erasesize / mtd->writesize; 191 pgcnt = mtd->erasesize / pgsize;
188 192
189 printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, " 193 printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, "
190 "page size %u, count of eraseblocks %u, pages per " 194 "page size %u, count of eraseblocks %u, pages per "
diff --git a/drivers/mtd/tests/mtd_speedtest.c b/drivers/mtd/tests/mtd_speedtest.c
index 141363a7e805..7fbb51d4eabe 100644
--- a/drivers/mtd/tests/mtd_speedtest.c
+++ b/drivers/mtd/tests/mtd_speedtest.c
@@ -301,6 +301,10 @@ static int scan_for_bad_eraseblocks(void)
301 } 301 }
302 memset(bbt, 0 , ebcnt); 302 memset(bbt, 0 , ebcnt);
303 303
304 /* NOR flash does not implement block_isbad */
305 if (mtd->block_isbad == NULL)
306 goto out;
307
304 printk(PRINT_PREF "scanning for bad eraseblocks\n"); 308 printk(PRINT_PREF "scanning for bad eraseblocks\n");
305 for (i = 0; i < ebcnt; ++i) { 309 for (i = 0; i < ebcnt; ++i) {
306 bbt[i] = is_block_bad(i) ? 1 : 0; 310 bbt[i] = is_block_bad(i) ? 1 : 0;
@@ -309,6 +313,7 @@ static int scan_for_bad_eraseblocks(void)
309 cond_resched(); 313 cond_resched();
310 } 314 }
311 printk(PRINT_PREF "scanned %d eraseblocks, %d are bad\n", i, bad); 315 printk(PRINT_PREF "scanned %d eraseblocks, %d are bad\n", i, bad);
316out:
312 goodebcnt = ebcnt - bad; 317 goodebcnt = ebcnt - bad;
313 return 0; 318 return 0;
314} 319}
@@ -340,7 +345,7 @@ static int __init mtd_speedtest_init(void)
340 tmp = mtd->size; 345 tmp = mtd->size;
341 do_div(tmp, mtd->erasesize); 346 do_div(tmp, mtd->erasesize);
342 ebcnt = tmp; 347 ebcnt = tmp;
343 pgcnt = mtd->erasesize / mtd->writesize; 348 pgcnt = mtd->erasesize / pgsize;
344 349
345 printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, " 350 printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, "
346 "page size %u, count of eraseblocks %u, pages per " 351 "page size %u, count of eraseblocks %u, pages per "
diff --git a/drivers/mtd/tests/mtd_stresstest.c b/drivers/mtd/tests/mtd_stresstest.c
index 63920476b57a..a99d3cd737d8 100644
--- a/drivers/mtd/tests/mtd_stresstest.c
+++ b/drivers/mtd/tests/mtd_stresstest.c
@@ -227,6 +227,10 @@ static int scan_for_bad_eraseblocks(void)
227 } 227 }
228 memset(bbt, 0 , ebcnt); 228 memset(bbt, 0 , ebcnt);
229 229
230 /* NOR flash does not implement block_isbad */
231 if (mtd->block_isbad == NULL)
232 return 0;
233
230 printk(PRINT_PREF "scanning for bad eraseblocks\n"); 234 printk(PRINT_PREF "scanning for bad eraseblocks\n");
231 for (i = 0; i < ebcnt; ++i) { 235 for (i = 0; i < ebcnt; ++i) {
232 bbt[i] = is_block_bad(i) ? 1 : 0; 236 bbt[i] = is_block_bad(i) ? 1 : 0;
@@ -265,7 +269,7 @@ static int __init mtd_stresstest_init(void)
265 tmp = mtd->size; 269 tmp = mtd->size;
266 do_div(tmp, mtd->erasesize); 270 do_div(tmp, mtd->erasesize);
267 ebcnt = tmp; 271 ebcnt = tmp;
268 pgcnt = mtd->erasesize / mtd->writesize; 272 pgcnt = mtd->erasesize / pgsize;
269 273
270 printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, " 274 printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, "
271 "page size %u, count of eraseblocks %u, pages per " 275 "page size %u, count of eraseblocks %u, pages per "
diff --git a/include/linux/kmsg_dump.h b/include/linux/kmsg_dump.h
index e32aa268efac..24b44145a886 100644
--- a/include/linux/kmsg_dump.h
+++ b/include/linux/kmsg_dump.h
@@ -17,6 +17,7 @@
17enum kmsg_dump_reason { 17enum kmsg_dump_reason {
18 KMSG_DUMP_OOPS, 18 KMSG_DUMP_OOPS,
19 KMSG_DUMP_PANIC, 19 KMSG_DUMP_PANIC,
20 KMSG_DUMP_KEXEC,
20}; 21};
21 22
22/** 23/**
diff --git a/include/linux/mtd/pismo.h b/include/linux/mtd/pismo.h
new file mode 100644
index 000000000000..8dfb7e1421c5
--- /dev/null
+++ b/include/linux/mtd/pismo.h
@@ -0,0 +1,17 @@
1/*
2 * PISMO memory driver - http://www.pismoworld.org/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License.
7 */
8#ifndef __LINUX_MTD_PISMO_H
9#define __LINUX_MTD_PISMO_H
10
11struct pismo_pdata {
12 void (*set_vpp)(void *, int);
13 void *vpp_data;
14 phys_addr_t cs_addrs[5];
15};
16
17#endif
diff --git a/kernel/kexec.c b/kernel/kexec.c
index a9a93d9ee7a7..ef077fb73155 100644
--- a/kernel/kexec.c
+++ b/kernel/kexec.c
@@ -32,6 +32,7 @@
32#include <linux/console.h> 32#include <linux/console.h>
33#include <linux/vmalloc.h> 33#include <linux/vmalloc.h>
34#include <linux/swap.h> 34#include <linux/swap.h>
35#include <linux/kmsg_dump.h>
35 36
36#include <asm/page.h> 37#include <asm/page.h>
37#include <asm/uaccess.h> 38#include <asm/uaccess.h>
@@ -1074,6 +1075,9 @@ void crash_kexec(struct pt_regs *regs)
1074 if (mutex_trylock(&kexec_mutex)) { 1075 if (mutex_trylock(&kexec_mutex)) {
1075 if (kexec_crash_image) { 1076 if (kexec_crash_image) {
1076 struct pt_regs fixed_regs; 1077 struct pt_regs fixed_regs;
1078
1079 kmsg_dump(KMSG_DUMP_KEXEC);
1080
1077 crash_setup_regs(&fixed_regs, regs); 1081 crash_setup_regs(&fixed_regs, regs);
1078 crash_save_vmcoreinfo(); 1082 crash_save_vmcoreinfo();
1079 machine_crash_shutdown(&fixed_regs); 1083 machine_crash_shutdown(&fixed_regs);
diff --git a/kernel/panic.c b/kernel/panic.c
index 5827f7b97254..c787333282b8 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -75,7 +75,6 @@ NORET_TYPE void panic(const char * fmt, ...)
75 dump_stack(); 75 dump_stack();
76#endif 76#endif
77 77
78 kmsg_dump(KMSG_DUMP_PANIC);
79 /* 78 /*
80 * If we have crashed and we have a crash kernel loaded let it handle 79 * If we have crashed and we have a crash kernel loaded let it handle
81 * everything else. 80 * everything else.
@@ -83,6 +82,8 @@ NORET_TYPE void panic(const char * fmt, ...)
83 */ 82 */
84 crash_kexec(NULL); 83 crash_kexec(NULL);
85 84
85 kmsg_dump(KMSG_DUMP_PANIC);
86
86 /* 87 /*
87 * Note smp_send_stop is the usual smp shutdown function, which 88 * Note smp_send_stop is the usual smp shutdown function, which
88 * unfortunately means it may not be hardened to work in a panic 89 * unfortunately means it may not be hardened to work in a panic
diff --git a/kernel/printk.c b/kernel/printk.c
index 17463ca2e229..1751c456b71f 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -1467,6 +1467,7 @@ EXPORT_SYMBOL_GPL(kmsg_dump_unregister);
1467static const char const *kmsg_reasons[] = { 1467static const char const *kmsg_reasons[] = {
1468 [KMSG_DUMP_OOPS] = "oops", 1468 [KMSG_DUMP_OOPS] = "oops",
1469 [KMSG_DUMP_PANIC] = "panic", 1469 [KMSG_DUMP_PANIC] = "panic",
1470 [KMSG_DUMP_KEXEC] = "kexec",
1470}; 1471};
1471 1472
1472static const char *kmsg_to_str(enum kmsg_dump_reason reason) 1473static const char *kmsg_to_str(enum kmsg_dump_reason reason)
diff --git a/kernel/time/clockevents.c b/kernel/time/clockevents.c
index 6f740d9f0948..d7395fdfb9f3 100644
--- a/kernel/time/clockevents.c
+++ b/kernel/time/clockevents.c
@@ -259,7 +259,8 @@ void clockevents_notify(unsigned long reason, void *arg)
259 cpu = *((int *)arg); 259 cpu = *((int *)arg);
260 list_for_each_entry_safe(dev, tmp, &clockevent_devices, list) { 260 list_for_each_entry_safe(dev, tmp, &clockevent_devices, list) {
261 if (cpumask_test_cpu(cpu, dev->cpumask) && 261 if (cpumask_test_cpu(cpu, dev->cpumask) &&
262 cpumask_weight(dev->cpumask) == 1) { 262 cpumask_weight(dev->cpumask) == 1 &&
263 !tick_is_broadcast_device(dev)) {
263 BUG_ON(dev->mode != CLOCK_EVT_MODE_UNUSED); 264 BUG_ON(dev->mode != CLOCK_EVT_MODE_UNUSED);
264 list_del(&dev->list); 265 list_del(&dev->list);
265 } 266 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 22:25:40 -0500