277 files changed, 17166 insertions, 10144 deletions

diff --git a/Documentation/DocBook/kernel-api.tmpl b/Documentation/DocBook/kernel-api.tmpl
index 8c5698a8c2e1..46bcff2849bd 100644
--- a/Documentation/DocBook/kernel-api.tmpl
+++ b/Documentation/DocBook/kernel-api.tmpl
@@ -643,6 +643,60 @@ X!Idrivers/video/console/fonts.c
 !Edrivers/spi/spi.c
   </chapter>
 
+  <chapter id="i2c">
+     <title>I<superscript>2</superscript>C and SMBus Subsystem</title>
+
+     <para>
+        I<superscript>2</superscript>C (or without fancy typography, "I2C")
+        is an acronym for the "Inter-IC" bus, a simple bus protocol which is
+        widely used where low data rate communications suffice.
+        Since it's also a licensed trademark, some vendors use another
+        name (such as "Two-Wire Interface", TWI) for the same bus.
+        I2C only needs two signals (SCL for clock, SDA for data), conserving
+        board real estate and minimizing signal quality issues.
+        Most I2C devices use seven bit addresses, and bus speeds of up
+        to 400 kHz; there's a high speed extension (3.4 MHz) that's not yet
+        found wide use.
+        I2C is a multi-master bus; open drain signaling is used to
+        arbitrate between masters, as well as to handshake and to
+        synchronize clocks from slower clients.
+     </para>
+
+     <para>
+        The Linux I2C programming interfaces support only the master
+        side of bus interactions, not the slave side.
+        The programming interface is structured around two kinds of driver,
+        and two kinds of device.
+        An I2C "Adapter Driver" abstracts the controller hardware; it binds
+        to a physical device (perhaps a PCI device or platform_device) and
+        exposes a <structname>struct i2c_adapter</structname> representing
+        each I2C bus segment it manages.
+        On each I2C bus segment will be I2C devices represented by a
+        <structname>struct i2c_client</structname>.  Those devices will
+        be bound to a <structname>struct i2c_driver</structname>,
+        which should follow the standard Linux driver model.
+        (At this writing, a legacy model is more widely used.)
+        There are functions to perform various I2C protocol operations; at
+        this writing all such functions are usable only from task context.
+     </para>
+
+     <para>
+        The System Management Bus (SMBus) is a sibling protocol.  Most SMBus
+        systems are also I2C conformant.  The electrical constraints are
+        tighter for SMBus, and it standardizes particular protocol messages
+        and idioms.  Controllers that support I2C can also support most
+        SMBus operations, but SMBus controllers don't support all the protocol
+        options that an I2C controller will.
+        There are functions to perform various SMBus protocol operations,
+        either using I2C primitives or by issuing SMBus commands to
+        i2c_adapter devices which don't support those I2C operations.
+     </para>
+
+!Iinclude/linux/i2c.h
+!Fdrivers/i2c/i2c-boardinfo.c i2c_register_board_info
+!Edrivers/i2c/i2c-core.c
+  </chapter>
+
   <chapter id="splice">
       <title>splice API</title>
   <para>)
@@ -654,4 +708,5 @@ X!Idrivers/video/console/fonts.c
 !Ffs/splice.c
   </chapter>
 
+
 </book>
diff --git a/Documentation/blackfin/kgdb.txt b/Documentation/blackfin/kgdb.txt
new file mode 100644
index 000000000000..84f6a484ae9a
--- /dev/null
+++ b/Documentation/blackfin/kgdb.txt
@@ -0,0 +1,155 @@
+                        A Simple Guide to Configure KGDB
+
+                        Sonic Zhang <sonic.zhang@analog.com>
+                                Aug. 24th 2006
+
+
+This KGDB patch enables the kernel developer to do source level debugging on
+the kernel for the Blackfin architecture.  The debugging works over either the
+ethernet interface or one of the uarts.  Both software breakpoints and
+hardware breakpoints are supported in this version.
+http://docs.blackfin.uclinux.org/doku.php?id=kgdb
+
+
+2 known issues:
+1. This bug:
+       http://blackfin.uclinux.org/tracker/index.php?func=detail&aid=544&group_id=18&atid=145
+   The GDB client for Blackfin uClinux causes incorrect values of local
+   variables to be displayed when the user breaks the running of kernel in GDB.
+2. Because of a hardware bug in Blackfin 533 v1.0.3:
+       05000067 - Watchpoints (Hardware Breakpoints) are not supported
+   Hardware breakpoints cannot be set properly.
+
+
+Debug over Ethernet:
+ 
+1. Compile and install the cross platform version of gdb for blackfin, which
+   can be found at $(BINROOT)/bfin-elf-gdb.
+
+2. Apply this patch to the 2.6.x kernel.  Select the menuconfig option under
+   "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
+   With this selected, option "Full Symbolic/Source Debugging support" and 
+   "Compile the kernel with frame pointers" are also selected.
+
+3. Select option "KGDB: connect over (Ethernet)".  Add "kgdboe=@target-IP/,@host-IP/" to
+   the option "Compiled-in Kernel Boot Parameter" under "Kernel hacking".
+
+4. Connect minicom to the serial port and boot the kernel image.
+
+5. Configure the IP "/> ifconfig eth0 target-IP"
+
+6. Start GDB client "bfin-elf-gdb vmlinux".
+
+7. Connect to the target "(gdb) target remote udp:target-IP:6443".
+
+8. Set software breakpoint "(gdb) break sys_open".
+
+9. Continue "(gdb) c".
+
+10. Run ls in the target console "/> ls".
+
+11. Breakpoint hits. "Breakpoint 1: sys_open(..."
+
+12. Display local variables and function paramters.
+    (*) This operation gives wrong results, see known issue 1.
+
+13. Single stepping "(gdb) si".
+
+14. Remove breakpoint 1. "(gdb) del 1"
+
+15. Set hardware breakpoint "(gdb) hbreak sys_open".
+
+16. Continue "(gdb) c".
+
+17. Run ls in the target console "/> ls".
+
+18. Hardware breakpoint hits. "Breakpoint 1: sys_open(...".
+    (*) This hardware breakpoint will not be hit, see known issue 2.
+
+19. Continue "(gdb) c".
+
+20. Interrupt the target in GDB "Ctrl+C".
+
+21. Detach from the target "(gdb) detach".
+
+22. Exit GDB "(gdb) quit".
+
+
+Debug over the UART:
+
+1. Compile and install the cross platform version of gdb for blackfin, which
+   can be found at $(BINROOT)/bfin-elf-gdb.
+
+2. Apply this patch to the 2.6.x kernel.  Select the menuconfig option under
+   "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
+   With this selected, option "Full Symbolic/Source Debugging support" and 
+   "Compile the kernel with frame pointers" are also selected.
+
+3. Select option "KGDB: connect over (UART)".  Set "KGDB: UART port number" to be
+   a different one from the console.  Don't forget to change the mode of
+   blackfin serial driver to PIO.  Otherwise kgdb works incorrectly on UART.
+ 
+4. If you want connect to kgdb when the kernel boots, enable
+   "KGDB: Wait for gdb connection early" 
+
+5. Compile kernel.
+
+6. Connect minicom to the serial port of the console and boot the kernel image.
+
+7. Start GDB client "bfin-elf-gdb vmlinux".
+
+8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
+
+9. Connect to the target on the second serial port "(gdb) target remote /dev/ttyS1".
+
+10. Set software breakpoint "(gdb) break sys_open".
+
+11. Continue "(gdb) c". 
+
+12. Run ls in the target console "/> ls". 
+
+13. A breakpoint is hit. "Breakpoint 1: sys_open(..."
+
+14. All other operations are the same as that in KGDB over Ethernet. 
+
+
+Debug over the same UART as console:
+
+1. Compile and install the cross platform version of gdb for blackfin, which
+   can be found at $(BINROOT)/bfin-elf-gdb.
+
+2. Apply this patch to the 2.6.x kernel.  Select the menuconfig option under
+   "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
+   With this selected, option "Full Symbolic/Source Debugging support" and 
+   "Compile the kernel with frame pointers" are also selected.
+
+3. Select option "KGDB: connect over UART".  Set "KGDB: UART port number" to console.
+   Don't forget to change the mode of blackfin serial driver to PIO.
+   Otherwise kgdb works incorrectly on UART.
+ 
+4. If you want connect to kgdb when the kernel boots, enable
+   "KGDB: Wait for gdb connection early" 
+
+5. Connect minicom to the serial port and boot the kernel image. 
+
+6. (Optional) Ask target to wait for gdb connection by entering Ctrl+A. In minicom, you should enter Ctrl+A+A.
+
+7. Start GDB client "bfin-elf-gdb vmlinux".
+
+8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
+
+9. Connect to the target "(gdb) target remote /dev/ttyS0".
+
+10. Set software breakpoint "(gdb) break sys_open".
+
+11. Continue "(gdb) c". Then enter Ctrl+C twice to stop GDB connection.
+
+12. Run ls in the target console "/> ls". Dummy string can be seen on the console.
+
+13. Then connect the gdb to target again. "(gdb) target remote /dev/ttyS0".
+    Now you will find a breakpoint is hit. "Breakpoint 1: sys_open(..."
+
+14. All other operations are the same as that in KGDB over Ethernet.  The only
+    difference is that after continue command in GDB, please stop GDB
+    connection by 2 "Ctrl+C"s and connect again after breakpoints are hit or
+    Ctrl+A is entered.
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 062fc2e79c86..0599a0c7c026 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -311,6 +311,13 @@ Who:  Tejun Heo <htejun@gmail.com>
 
 ---------------------------
 
+What:   Legacy RTC drivers (under drivers/i2c/chips)
+When:   November 2007
+Why:    Obsolete. We have a RTC subsystem with better drivers.
+Who:    Jean Delvare <khali@linux-fr.org>
+
+---------------------------
+
 What:   iptables SAME target
 When:   1.1. 2008
 Files:  net/ipv4/netfilter/ipt_SAME.c, include/linux/netfilter_ipv4/ipt_SAME.h
diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
index c34f0db78a30..fe6406f2f9a6 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -5,8 +5,8 @@ Supported adapters:
     '810' and '810E' chipsets)
   * Intel 82801BA (ICH2 - part of the '815E' chipset)
   * Intel 82801CA/CAM (ICH3)
-  * Intel 82801DB (ICH4) (HW PEC supported, 32 byte buffer not supported)
-  * Intel 82801EB/ER (ICH5) (HW PEC supported, 32 byte buffer not supported)
+  * Intel 82801DB (ICH4) (HW PEC supported)
+  * Intel 82801EB/ER (ICH5) (HW PEC supported)
   * Intel 6300ESB
   * Intel 82801FB/FR/FW/FRW (ICH6)
   * Intel 82801G (ICH7)
diff --git a/Documentation/i2c/busses/i2c-piix4 b/Documentation/i2c/busses/i2c-piix4
index 7cbe43fa2701..fa0c786a8bf5 100644
--- a/Documentation/i2c/busses/i2c-piix4
+++ b/Documentation/i2c/busses/i2c-piix4
@@ -6,7 +6,7 @@ Supported adapters:
     Datasheet: Publicly available at the Intel website
   * ServerWorks OSB4, CSB5, CSB6 and HT-1000 southbridges
     Datasheet: Only available via NDA from ServerWorks
-  * ATI IXP200, IXP300, IXP400 and SB600 southbridges
+  * ATI IXP200, IXP300, IXP400, SB600 and SB700 southbridges
     Datasheet: Not publicly available
   * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
     Datasheet: Publicly available at the SMSC website http://www.smsc.com
diff --git a/Documentation/i2c/busses/i2c-taos-evm b/Documentation/i2c/busses/i2c-taos-evm
new file mode 100644
index 000000000000..9146e33be6dd
--- /dev/null
+++ b/Documentation/i2c/busses/i2c-taos-evm
@@ -0,0 +1,46 @@
+Kernel driver i2c-taos-evm
+
+Author: Jean Delvare <khali@linux-fr.org>
+
+This is a driver for the evaluation modules for TAOS I2C/SMBus chips.
+The modules include an SMBus master with limited capabilities, which can
+be controlled over the serial port. Virtually all evaluation modules
+are supported, but a few lines of code need to be added for each new
+module to instantiate the right I2C chip on the bus. Obviously, a driver
+for the chip in question is also needed.
+
+Currently supported devices are:
+
+* TAOS TSL2550 EVM
+
+For addtional information on TAOS products, please see
+  http://www.taosinc.com/
+
+
+Using this driver
+-----------------
+
+In order to use this driver, you'll need the serport driver, and the
+inputattach tool, which is part of the input-utils package. The following
+commands will tell the kernel that you have a TAOS EVM on the first
+serial port:
+
+# modprobe serport
+# inputattach --taos-evm /dev/ttyS0
+
+
+Technical details
+-----------------
+
+Only 4 SMBus transaction types are supported by the TAOS evaluation
+modules:
+* Receive Byte
+* Send Byte
+* Read Byte
+* Write Byte
+
+The communication protocol is text-based and pretty simple. It is
+described in a PDF document on the CD which comes with the evaluation
+module. The communication is rather slow, because the serial port has
+to operate at 1200 bps. However, I don't think this is a big concern in
+practice, as these modules are meant for evaluation and testing only.
diff --git a/Documentation/i2c/chips/max6875 b/Documentation/i2c/chips/max6875
index 96fec562a8e9..a0cd8af2f408 100644
--- a/Documentation/i2c/chips/max6875
+++ b/Documentation/i2c/chips/max6875
@@ -99,7 +99,7 @@ And then read the data
 
   or
 
-  count = i2c_smbus_read_i2c_block_data(fd, 0x84, buffer);
+  count = i2c_smbus_read_i2c_block_data(fd, 0x84, 16, buffer);
 
 The block read should read 16 bytes.
 0x84 is the block read command.
diff --git a/Documentation/i2c/chips/x1205 b/Documentation/i2c/chips/x1205
deleted file mode 100644
index 09407c991fe5..000000000000
--- a/Documentation/i2c/chips/x1205
+++ /dev/null
@@ -1,38 +0,0 @@
-Kernel driver x1205
-===================
-
-Supported chips:
-  * Xicor X1205 RTC
-    Prefix: 'x1205'
-    Addresses scanned: none
-    Datasheet: http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
-
-Authors:
-        Karen Spearel <kas11@tampabay.rr.com>,
-        Alessandro Zummo <a.zummo@towertech.it>
-
-Description
------------
-
-This module aims to provide complete access to the Xicor X1205 RTC.
-Recently Xicor has merged with Intersil, but the chip is
-still sold under the Xicor brand.
-
-This chip is located at address 0x6f and uses a 2-byte register addressing.
-Two bytes need to be written to read a single register, while most
-other chips just require one and take the second one as the data
-to be written. To prevent corrupting unknown chips, the user must
-explicitely set the probe parameter.
-
-example:
-
-modprobe x1205 probe=0,0x6f
-
-The module supports one more option, hctosys, which is used to set the
-software clock from the x1205. On systems where the x1205 is the
-only hardware rtc, this parameter could be used to achieve a correct
-date/time earlier in the system boot sequence.
-
-example:
-
-modprobe x1205 probe=0,0x6f hctosys=1
diff --git a/Documentation/i2c/summary b/Documentation/i2c/summary
index aea60bf7e8f0..003c7319b8c7 100644
--- a/Documentation/i2c/summary
+++ b/Documentation/i2c/summary
@@ -67,7 +67,6 @@ i2c-proc: The /proc/sys/dev/sensors interface for device (client) drivers
 Algorithm drivers
 -----------------
 
-i2c-algo-8xx:    An algorithm for CPM's I2C device in Motorola 8xx processors (NOT BUILT BY DEFAULT)
 i2c-algo-bit:    A bit-banging algorithm
 i2c-algo-pcf:    A PCF 8584 style algorithm
 i2c-algo-ibm_ocp: An algorithm for the I2C device in IBM 4xx processors (NOT BUILT BY DEFAULT)
@@ -81,6 +80,5 @@ i2c-pcf-epp:     PCF8584 on a EPP parallel port (uses i2c-algo-pcf) (NOT mkpatch
 i2c-philips-par: Philips style parallel port adapter (uses i2c-algo-bit)
 i2c-adap-ibm_ocp: IBM 4xx processor I2C device (uses i2c-algo-ibm_ocp) (NOT BUILT BY DEFAULT)
 i2c-pport:       Primitive parallel port adapter (uses i2c-algo-bit)
-i2c-rpx:         RPX board Motorola 8xx I2C device (uses i2c-algo-8xx) (NOT BUILT BY DEFAULT)
 i2c-velleman:    Velleman K8000 parallel port adapter (uses i2c-algo-bit)
 
diff --git a/Documentation/i2c/writing-clients b/Documentation/i2c/writing-clients
index 3d8d36b0ad12..2c170032bf37 100644
--- a/Documentation/i2c/writing-clients
+++ b/Documentation/i2c/writing-clients
@@ -571,7 +571,7 @@ SMBus communication
                                         u8 command, u8 length,
                                         u8 *values);
   extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client,
-                                           u8 command, u8 *values);
+                                           u8 command, u8 length, u8 *values);
 
 These ones were removed in Linux 2.6.10 because they had no users, but could
 be added back later if needed:
diff --git a/Documentation/i386/zero-page.txt b/Documentation/i386/zero-page.txt
index c04a421f4a7c..75b3680c41eb 100644
--- a/Documentation/i386/zero-page.txt
+++ b/Documentation/i386/zero-page.txt
@@ -37,6 +37,7 @@ Offset	Type		Description
 0x1d0   unsigned long   EFI memory descriptor map pointer
 0x1d4   unsigned long   EFI memory descriptor map size
 0x1e0   unsigned long   ALT_MEM_K, alternative mem check, in Kb
+0x1e4   unsigned long   Scratch field for the kernel setup code
 0x1e8   char            number of entries in E820MAP (below)
 0x1e9   unsigned char   number of entries in EDDBUF (below)
 0x1ea   unsigned char   number of entries in EDD_MBR_SIG_BUFFER (below)
diff --git a/MAINTAINERS b/MAINTAINERS
index fcfe598b8d74..cba5f4df0e21 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1750,8 +1750,8 @@ T:	http://www.harbaum.org/till/i2c_tiny_usb
 S:      Maintained
 
 i386 BOOT CODE
-P:      Riley H. Williams
-M:      Riley@Williams.Name
+P:      H. Peter Anvin
+M:      hpa@zytor.com
 L:      Linux-Kernel@vger.kernel.org
 S:      Maintained
 
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d98bafcaca59..017defaa525b 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -71,6 +71,7 @@ config GENERIC_CALIBRATE_DELAY
 
 config IRQCHIP_DEMUX_GPIO
         bool
+        depends on (BF53x || BF561 || BF54x)
         default y
 
 source "init/Kconfig"
@@ -114,6 +115,26 @@ config BF537
         help
           BF537 Processor Support.
 
+config BF542
+        bool "BF542"
+        help
+          BF542 Processor Support.
+
+config BF544
+        bool "BF544"
+        help
+          BF544 Processor Support.
+
+config BF548
+        bool "BF548"
+        help
+          BF548 Processor Support.
+
+config BF549
+        bool "BF549"
+        help
+          BF549 Processor Support.
+
 config BF561
         bool "BF561"
         help
@@ -125,6 +146,11 @@ choice
         prompt "Silicon Rev"
         default BF_REV_0_2 if BF537
         default BF_REV_0_3 if BF533
+        default BF_REV_0_0 if BF549
+
+config BF_REV_0_0
+        bool "0.0"
+        depends on (BF549)
 
 config BF_REV_0_2
         bool "0.2"
@@ -150,6 +176,16 @@ config BF_REV_NONE
 
 endchoice
 
+config BF53x
+        bool
+        depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
+        default y
+
+config BF54x
+        bool
+        depends on (BF542 || BF544 || BF548 || BF549)
+        default y
+
 config BFIN_DUAL_CORE
         bool
         depends on (BF561)
@@ -198,6 +234,12 @@ config BFIN537_BLUETECHNIX_CM
         help
           CM-BF537 support for EVAL- and DEV-Board.
 
+config BFIN548_EZKIT
+        bool "BF548-EZKIT"
+        depends on (BF548 || BF549)
+          help
+          BFIN548-EZKIT board Support.
+
 config BFIN561_BLUETECHNIX_CM
         bool "Bluetechnix CM-BF561"
         depends on (BF561)
@@ -265,6 +307,7 @@ config BFIN_SHARED_FLASH_ENET
 source "arch/blackfin/mach-bf533/Kconfig"
 source "arch/blackfin/mach-bf561/Kconfig"
 source "arch/blackfin/mach-bf537/Kconfig"
+source "arch/blackfin/mach-bf548/Kconfig"
 
 menu "Board customizations"
 
@@ -497,7 +540,8 @@ config IP_CHECKSUM_L1
 
 config CACHELINE_ALIGNED_L1
         bool "Locate cacheline_aligned data to L1 Data Memory"
-        default y
+        default y if !BF54x
+        default n if BF54x
         depends on !BF531
         help
           If enabled cacheline_anligned data is linked
@@ -541,9 +585,17 @@ endchoice
 
 source "mm/Kconfig"
 
+config LARGE_ALLOCS
+        bool "Allow allocating large blocks (> 1MB) of memory"
+        help
+          Allow the slab memory allocator to keep chains for very large
+          memory sizes - upto 32MB. You may need this if your system has
+          a lot of RAM, and you need to able to allocate very large
+          contiguous chunks. If unsure, say N.
+
 config BFIN_DMA_5XX
         bool "Enable DMA Support"
-        depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561)
+        depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
         default y
         help
           DMA driver for BF5xx.
@@ -686,6 +738,7 @@ config C_AMCKEN
 
 config C_CDPRIO
         bool "DMA has priority over core for ext. accesses"
+        depends on !BF54x
         default n
 
 config C_B0PEN
@@ -839,7 +892,7 @@ endchoice
 
 endmenu
 
-if (BF537 || BF533)
+if (BF537 || BF533 || BF54x)
 
 menu "CPU Frequency scaling"
 
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 6971a4418dfe..1b75672dfc8f 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -24,6 +24,8 @@ machine-$(CONFIG_BF533) := bf533
 machine-$(CONFIG_BF534) := bf537
 machine-$(CONFIG_BF536) := bf537
 machine-$(CONFIG_BF537) := bf537
+machine-$(CONFIG_BF548) := bf548
+machine-$(CONFIG_BF549) := bf548
 machine-$(CONFIG_BF561) := bf561
 MACHINE := $(machine-y)
 export MACHINE
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 49e8098d4c21..8cd33560e817 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -13,7 +13,8 @@ extra-y += vmlinux.bin vmlinux.gz
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C gzip -a $(CONFIG_BOOT_LOAD) -e $(CONFIG_BOOT_LOAD) -n 'Linux-$(KERNELRELEASE)' \
+                   -C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
+                   -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
                    -d $< $@
 
 $(obj)/vmlinux.bin: vmlinux FORCE
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
new file mode 100644
index 000000000000..ac8390fafa9c
--- /dev/null
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -0,0 +1,1100 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.21.5
+#
+# CONFIG_MMU is not set
+# CONFIG_FPU is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_BLACKFIN=y
+CONFIG_ZONE_DMA=y
+CONFIG_BFIN=y
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_IRQCHIP_DEMUX_GPIO=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
+# CONFIG_NP2 is not set
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+
+#
+# Blackfin Processor Options
+#
+
+#
+# Processor and Board Settings
+#
+# CONFIG_BF531 is not set
+# CONFIG_BF532 is not set
+# CONFIG_BF533 is not set
+# CONFIG_BF534 is not set
+# CONFIG_BF536 is not set
+# CONFIG_BF537 is not set
+# CONFIG_BF542 is not set
+# CONFIG_BF544 is not set
+# CONFIG_BF548 is not set
+CONFIG_BF549=y
+# CONFIG_BF561 is not set
+CONFIG_BF_REV_0_0=y
+# CONFIG_BF_REV_0_2 is not set
+# CONFIG_BF_REV_0_3 is not set
+# CONFIG_BF_REV_0_4 is not set
+# CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_ANY is not set
+# CONFIG_BF_REV_NONE is not set
+CONFIG_BF54x=y
+CONFIG_BFIN_SINGLE_CORE=y
+# CONFIG_BFIN533_EZKIT is not set
+# CONFIG_BFIN533_STAMP is not set
+# CONFIG_BFIN537_STAMP is not set
+# CONFIG_BFIN533_BLUETECHNIX_CM is not set
+# CONFIG_BFIN537_BLUETECHNIX_CM is not set
+CONFIG_BFIN548_EZKIT=y
+# CONFIG_BFIN561_BLUETECHNIX_CM is not set
+# CONFIG_BFIN561_EZKIT is not set
+# CONFIG_BFIN561_TEPLA is not set
+# CONFIG_PNAV10 is not set
+# CONFIG_GENERIC_BOARD is not set
+CONFIG_IRQ_PLL_WAKEUP=7
+CONFIG_IRQ_TIMER0=11
+CONFIG_IRQ_TIMER1=11
+CONFIG_IRQ_TIMER2=11
+CONFIG_IRQ_TIMER3=11
+CONFIG_IRQ_TIMER4=11
+CONFIG_IRQ_TIMER5=11
+CONFIG_IRQ_TIMER6=11
+CONFIG_IRQ_TIMER7=11
+CONFIG_IRQ_TIMER8=11
+CONFIG_IRQ_TIMER9=11
+CONFIG_IRQ_TIMER10=11
+CONFIG_IRQ_RTC=8
+CONFIG_IRQ_SPORT0_RX=9
+CONFIG_IRQ_SPORT0_TX=9
+CONFIG_IRQ_SPORT1_RX=9
+CONFIG_IRQ_SPORT1_TX=9
+CONFIG_IRQ_UART0_RX=10
+CONFIG_IRQ_UART0_TX=10
+CONFIG_IRQ_UART1_RX=10
+CONFIG_IRQ_UART1_TX=10
+
+#
+# BF548 Specific Configuration
+#
+
+#
+# Interrupt Priority Assignment
+#
+
+#
+# Priority
+#
+CONFIG_IRQ_DMAC0_ERR=7
+CONFIG_IRQ_EPPI0_ERR=7
+CONFIG_IRQ_SPORT0_ERR=7
+CONFIG_IRQ_SPORT1_ERR=7
+CONFIG_IRQ_SPI0_ERR=7
+CONFIG_IRQ_UART0_ERR=7
+CONFIG_IRQ_EPPI0=8
+CONFIG_IRQ_SPI0=10
+CONFIG_IRQ_PINT0=12
+CONFIG_IRQ_PINT1=12
+CONFIG_IRQ_MDMAS0=13
+CONFIG_IRQ_MDMAS1=13
+CONFIG_IRQ_WATCHDOG=13
+CONFIG_IRQ_DMAC1_ERR=7
+CONFIG_IRQ_SPORT2_ERR=7
+CONFIG_IRQ_SPORT3_ERR=7
+CONFIG_IRQ_MXVR_DATA=7
+CONFIG_IRQ_SPI1_ERR=7
+CONFIG_IRQ_SPI2_ERR=7
+CONFIG_IRQ_UART1_ERR=7
+CONFIG_IRQ_UART2_ERR=7
+CONFIG_IRQ_CAN0_ERR=7
+CONFIG_IRQ_SPORT2_RX=9
+CONFIG_IRQ_SPORT2_TX=9
+CONFIG_IRQ_SPORT3_RX=9
+CONFIG_IRQ_SPORT3_TX=9
+CONFIG_IRQ_EPPI1=9
+CONFIG_IRQ_EPPI2=9
+CONFIG_IRQ_SPI1=10
+CONFIG_IRQ_SPI2=10
+CONFIG_IRQ_ATAPI_RX=10
+CONFIG_IRQ_ATAPI_TX=10
+CONFIG_IRQ_TWI0=11
+CONFIG_IRQ_TWI1=11
+CONFIG_IRQ_CAN0_RX=11
+CONFIG_IRQ_CAN0_TX=11
+CONFIG_IRQ_MDMAS2=13
+CONFIG_IRQ_MDMAS3=13
+CONFIG_IRQ_MXVR_ERR=11
+CONFIG_IRQ_MXVR_MSG=11
+CONFIG_IRQ_MXVR_PKT=11
+CONFIG_IRQ_EPPI1_ERR=7
+CONFIG_IRQ_EPPI2_ERR=7
+CONFIG_IRQ_UART3_ERR=7
+CONFIG_IRQ_HOST_ERR=7
+CONFIG_IRQ_PIXC_ERR=7
+CONFIG_IRQ_NFC_ERR=7
+CONFIG_IRQ_ATAPI_ERR=7
+CONFIG_IRQ_CAN1_ERR=7
+CONFIG_IRQ_HS_DMA_ERR=7
+CONFIG_IRQ_PIXC_IN0=8
+CONFIG_IRQ_PIXC_IN1=8
+CONFIG_IRQ_PIXC_OUT=8
+CONFIG_IRQ_SDH=8
+CONFIG_IRQ_CNT=8
+CONFIG_IRQ_KEY=8
+CONFIG_IRQ_CAN1_RX=11
+CONFIG_IRQ_CAN1_TX=11
+CONFIG_IRQ_SDH_MASK0=11
+CONFIG_IRQ_SDH_MASK1=11
+CONFIG_IRQ_USB_INT0=11
+CONFIG_IRQ_USB_INT1=11
+CONFIG_IRQ_USB_INT2=11
+CONFIG_IRQ_USB_DMA=11
+CONFIG_IRQ_OTPSEC=11
+CONFIG_IRQ_PINT2=11
+CONFIG_IRQ_PINT3=11
+
+#
+# Board customizations
+#
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Board Setup
+#
+CONFIG_CLKIN_HZ=25000000
+CONFIG_MEM_SIZE=64
+CONFIG_MEM_ADD_WIDTH=10
+CONFIG_BOOT_LOAD=0x1000
+
+#
+# Blackfin Kernel Optimizations
+#
+
+#
+# Timer Tick
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+
+#
+# Memory Optimizations
+#
+CONFIG_I_ENTRY_L1=y
+CONFIG_EXCPT_IRQ_SYSC_L1=y
+CONFIG_DO_IRQ_L1=y
+CONFIG_CORE_TIMER_IRQ_L1=y
+CONFIG_IDLE_L1=y
+CONFIG_SCHEDULE_L1=y
+CONFIG_ARITHMETIC_OPS_L1=y
+CONFIG_ACCESS_OK_L1=y
+CONFIG_MEMSET_L1=y
+CONFIG_MEMCPY_L1=y
+CONFIG_SYS_BFIN_SPINLOCK_L1=y
+# CONFIG_IP_CHECKSUM_L1 is not set
+CONFIG_CACHELINE_ALIGNED_L1=y
+# CONFIG_SYSCALL_TAB_L1 is not set
+# CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_RAMKERNEL=y
+# CONFIG_ROMKERNEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_LARGE_ALLOCS=y
+CONFIG_BFIN_DMA_5XX=y
+# CONFIG_DMA_UNCACHED_2M is not set
+CONFIG_DMA_UNCACHED_1M=y
+# CONFIG_DMA_UNCACHED_NONE is not set
+
+#
+# Cache Support
+#
+CONFIG_BLKFIN_CACHE=y
+CONFIG_BLKFIN_DCACHE=y
+# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BLKFIN_WB is not set
+CONFIG_BLKFIN_WT=y
+CONFIG_L1_MAX_PIECE=16
+
+#
+# Clock Settings
+#
+# CONFIG_BFIN_KERNEL_CLOCK is not set
+
+#
+# Asynchonous Memory Configuration
+#
+
+#
+# EBIU_AMBCTL Global Control
+#
+CONFIG_C_AMCKEN=y
+CONFIG_C_CDPRIO=y
+# CONFIG_C_AMBEN is not set
+# CONFIG_C_AMBEN_B0 is not set
+# CONFIG_C_AMBEN_B0_B1 is not set
+# CONFIG_C_AMBEN_B0_B1_B2 is not set
+CONFIG_C_AMBEN_ALL=y
+
+#
+# EBIU_AMBCTL Control
+#
+CONFIG_BANK_0=0x7BB0
+CONFIG_BANK_1=0x7BB0
+CONFIG_BANK_2=0x7BB0
+CONFIG_BANK_3=0x99B3
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF_FDPIC=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_BF5xx is not set
+CONFIG_MTD_UCLINUX=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Misc devices
+#
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_NETLINK is not set
+
+#
+# Serial ATA (prod) and Parallel ATA (experimental) drivers
+#
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_SMC91X is not set
+# CONFIG_SMSC911X is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_BF53X_PFBUTTONS is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_AD9960 is not set
+# CONFIG_SPI_ADC_BF533 is not set
+# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BF5xx_PPIFCD is not set
+# CONFIG_BF5xx_TIMERS is not set
+# CONFIG_BF5xx_PPI is not set
+# CONFIG_BFIN_SPORT is not set
+# CONFIG_BFIN_TIMER_LATENCY is not set
+# CONFIG_BF5xx_FBDMA is not set
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+# CONFIG_SERIAL_BFIN_DMA is not set
+CONFIG_SERIAL_BFIN_PIO=y
+# CONFIG_SERIAL_BFIN_UART0 is not set
+CONFIG_SERIAL_BFIN_UART1=y
+# CONFIG_BFIN_UART1_CTSRTS is not set
+# CONFIG_SERIAL_BFIN_UART2 is not set
+# CONFIG_SERIAL_BFIN_UART3 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_BFIN_SPORT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# CAN, the car bus and industrial fieldbus
+#
+# CONFIG_CAN4LINUX is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+
+#
+# RTC drivers
+#
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_V3020 is not set
+CONFIG_RTC_DRV_BFIN=y
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# Auxiliary Display support
+#
+
+#
+# Virtualization
+#
+
+#
+# PBX support
+#
+# CONFIG_PBX is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_YAFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_DEBUG_HWERR=y
+# CONFIG_DEBUG_ICACHE_CHECK is not set
+# CONFIG_DEBUG_KERNEL_START is not set
+# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
+CONFIG_DEBUG_HUNT_FOR_ZERO=y
+# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_CPLB_INFO=y
+CONFIG_ACCESS_CHECK=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITY_NETWORK is not set
+CONFIG_SECURITY_CAPABILITIES=y
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index f3b7d2f9d49c..f429ebc3a961 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -6,9 +6,12 @@ extra-y := init_task.o vmlinux.lds
 
 obj-y := \
         entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
-        sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \
-        flat.o
+        sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
+        fixed_code.o cplbinit.o cacheinit.o
 
+obj-$(CONFIG_BF53x)                  += bfin_gpio.o
+obj-$(CONFIG_BF561)                  += bfin_gpio.o
 obj-$(CONFIG_MODULES)                += module.o
 obj-$(CONFIG_BFIN_DMA_5XX)           += bfin_dma_5xx.o
 obj-$(CONFIG_DUAL_CORE_TEST_MODULE)  += dualcore_test.o
+obj-$(CONFIG_KGDB)                   += kgdb.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index e455f4504509..b56b2741cdea 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -32,11 +32,10 @@
 #include <linux/kernel_stat.h>
 #include <linux/ptrace.h>
 #include <linux/hardirq.h>
-#include <asm/irq.h>
-#include <asm/thread_info.h>
+#include <linux/irq.h>
+#include <linux/thread_info.h>
 
-#define DEFINE(sym, val) \
-        asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+#define DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
 
 int main(void)
 {
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 069a896a8f26..7cf02f02a1db 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -34,6 +34,7 @@
 #include <linux/kernel.h>
 #include <linux/param.h>
 
+#include <asm/blackfin.h>
 #include <asm/dma.h>
 #include <asm/cacheflush.h>
 
@@ -45,67 +46,6 @@
 ***************************************************************************/
 
 static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
-#if defined (CONFIG_BF561)
-static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
-        (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
-        (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
-        (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
-        (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
-        (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
-};
-#else
-static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
-        (struct dma_register *) DMA0_NEXT_DESC_PTR,
-        (struct dma_register *) DMA1_NEXT_DESC_PTR,
-        (struct dma_register *) DMA2_NEXT_DESC_PTR,
-        (struct dma_register *) DMA3_NEXT_DESC_PTR,
-        (struct dma_register *) DMA4_NEXT_DESC_PTR,
-        (struct dma_register *) DMA5_NEXT_DESC_PTR,
-        (struct dma_register *) DMA6_NEXT_DESC_PTR,
-        (struct dma_register *) DMA7_NEXT_DESC_PTR,
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
-        (struct dma_register *) DMA8_NEXT_DESC_PTR,
-        (struct dma_register *) DMA9_NEXT_DESC_PTR,
-        (struct dma_register *) DMA10_NEXT_DESC_PTR,
-        (struct dma_register *) DMA11_NEXT_DESC_PTR,
-#endif
-        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-#endif
 
 /*------------------------------------------------------------------------------
  *       Set the Buffer Clear bit in the Configuration register of specific DMA
@@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void)
 
 arch_initcall(blackfin_dma_init);
 
-/*
- *      Form the channel find the irq number for that channel.
- */
-#if !defined(CONFIG_BF561)
-
-static int bf533_channel2irq(unsigned int channel)
-{
-        int ret_irq = -1;
-
-        switch (channel) {
-        case CH_PPI:
-                ret_irq = IRQ_PPI;
-                break;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
-        case CH_EMAC_RX:
-                ret_irq = IRQ_MAC_RX;
-                break;
-
-        case CH_EMAC_TX:
-                ret_irq = IRQ_MAC_TX;
-                break;
-
-        case CH_UART1_RX:
-                ret_irq = IRQ_UART1_RX;
-                break;
-
-        case CH_UART1_TX:
-                ret_irq = IRQ_UART1_TX;
-                break;
-#endif
-
-        case CH_SPORT0_RX:
-                ret_irq = IRQ_SPORT0_RX;
-                break;
-
-        case CH_SPORT0_TX:
-                ret_irq = IRQ_SPORT0_TX;
-                break;
-
-        case CH_SPORT1_RX:
-                ret_irq = IRQ_SPORT1_RX;
-                break;
-
-        case CH_SPORT1_TX:
-                ret_irq = IRQ_SPORT1_TX;
-                break;
-
-        case CH_SPI:
-                ret_irq = IRQ_SPI;
-                break;
-
-        case CH_UART_RX:
-                ret_irq = IRQ_UART_RX;
-                break;
-
-        case CH_UART_TX:
-                ret_irq = IRQ_UART_TX;
-                break;
-
-        case CH_MEM_STREAM0_SRC:
-        case CH_MEM_STREAM0_DEST:
-                ret_irq = IRQ_MEM_DMA0;
-                break;
-
-        case CH_MEM_STREAM1_SRC:
-        case CH_MEM_STREAM1_DEST:
-                ret_irq = IRQ_MEM_DMA1;
-                break;
-        }
-        return ret_irq;
-}
-
-# define channel2irq(channel) bf533_channel2irq(channel)
-
-#else
-
-static int bf561_channel2irq(unsigned int channel)
-{
-        int ret_irq = -1;
-
-        switch (channel) {
-        case CH_PPI0:
-                ret_irq = IRQ_PPI0;
-                break;
-        case CH_PPI1:
-                ret_irq = IRQ_PPI1;
-                break;
-        case CH_SPORT0_RX:
-                ret_irq = IRQ_SPORT0_RX;
-                break;
-        case CH_SPORT0_TX:
-                ret_irq = IRQ_SPORT0_TX;
-                break;
-        case CH_SPORT1_RX:
-                ret_irq = IRQ_SPORT1_RX;
-                break;
-        case CH_SPORT1_TX:
-                ret_irq = IRQ_SPORT1_TX;
-                break;
-        case CH_SPI:
-                ret_irq = IRQ_SPI;
-                break;
-        case CH_UART_RX:
-                ret_irq = IRQ_UART_RX;
-                break;
-        case CH_UART_TX:
-                ret_irq = IRQ_UART_TX;
-                break;
-
-        case CH_MEM_STREAM0_SRC:
-        case CH_MEM_STREAM0_DEST:
-                ret_irq = IRQ_MEM_DMA0;
-                break;
-        case CH_MEM_STREAM1_SRC:
-        case CH_MEM_STREAM1_DEST:
-                ret_irq = IRQ_MEM_DMA1;
-                break;
-        case CH_MEM_STREAM2_SRC:
-        case CH_MEM_STREAM2_DEST:
-                ret_irq = IRQ_MEM_DMA2;
-                break;
-        case CH_MEM_STREAM3_SRC:
-        case CH_MEM_STREAM3_DEST:
-                ret_irq = IRQ_MEM_DMA3;
-                break;
-
-        case CH_IMEM_STREAM0_SRC:
-        case CH_IMEM_STREAM0_DEST:
-                ret_irq = IRQ_IMEM_DMA0;
-                break;
-        case CH_IMEM_STREAM1_SRC:
-        case CH_IMEM_STREAM1_DEST:
-                ret_irq = IRQ_IMEM_DMA1;
-                break;
-        }
-        return ret_irq;
-}
-
-# define channel2irq(channel) bf561_channel2irq(channel)
-
-#endif
-
 /*------------------------------------------------------------------------------
  *      Request the specific DMA channel from the system.
  *-----------------------------------------------------------------------------*/
@@ -535,7 +332,7 @@ set_bfin_dma_config(char direction, char flow_mode,
 }
 EXPORT_SYMBOL(set_bfin_dma_config);
 
-void set_dma_sg(unsigned int channel, struct dmasg * sg, int nr_sg)
+void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
 {
         BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
                && channel < MAX_BLACKFIN_DMA_CHANNEL));
@@ -604,7 +401,7 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size)
 
         if (size <= 0)
                 return NULL;
-        
+
         local_irq_save(flags);
 
         if ((unsigned long)src < memory_end)
@@ -748,7 +545,6 @@ void *dma_memcpy(void *dest, const void *src, size_t size)
         addr = __dma_memcpy(dest+bulk, src+bulk, rest);
         return addr;
 }
-
 EXPORT_SYMBOL(dma_memcpy);
 
 void *safe_dma_memcpy(void *dest, const void *src, size_t size)
@@ -761,14 +557,13 @@ EXPORT_SYMBOL(safe_dma_memcpy);
 
 void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
 {
-
         unsigned long flags;
-        
+
         local_irq_save(flags);
-        
-        blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
 
-        bfin_write_MDMA_D0_START_ADDR(addr);
+        blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
+
+        bfin_write_MDMA_D0_START_ADDR(addr);
         bfin_write_MDMA_D0_X_COUNT(len);
         bfin_write_MDMA_D0_X_MODIFY(0);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -796,9 +591,9 @@ EXPORT_SYMBOL(dma_outsb);
 void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
 {
         unsigned long flags;
-                
+
         local_irq_save(flags);
-        bfin_write_MDMA_D0_START_ADDR(buf);
+        bfin_write_MDMA_D0_START_ADDR(buf);
         bfin_write_MDMA_D0_X_COUNT(len);
         bfin_write_MDMA_D0_X_MODIFY(1);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -827,12 +622,12 @@ EXPORT_SYMBOL(dma_insb);
 void dma_outsw(void __iomem *addr, const void  *buf, unsigned short len)
 {
         unsigned long flags;
-        
+
         local_irq_save(flags);
-                
-        blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
 
-        bfin_write_MDMA_D0_START_ADDR(addr);
+        blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
+
+        bfin_write_MDMA_D0_START_ADDR(addr);
         bfin_write_MDMA_D0_X_COUNT(len);
         bfin_write_MDMA_D0_X_MODIFY(0);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -859,10 +654,10 @@ EXPORT_SYMBOL(dma_outsw);
 void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
 {
         unsigned long flags;
-                
+
         local_irq_save(flags);
-        
-        bfin_write_MDMA_D0_START_ADDR(buf);
+
+        bfin_write_MDMA_D0_START_ADDR(buf);
         bfin_write_MDMA_D0_X_COUNT(len);
         bfin_write_MDMA_D0_X_MODIFY(2);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -891,12 +686,12 @@ EXPORT_SYMBOL(dma_insw);
 void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
 {
         unsigned long flags;
-        
+
         local_irq_save(flags);
-        
-        blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
 
-        bfin_write_MDMA_D0_START_ADDR(addr);
+        blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
+
+        bfin_write_MDMA_D0_START_ADDR(addr);
         bfin_write_MDMA_D0_X_COUNT(len);
         bfin_write_MDMA_D0_X_MODIFY(0);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -923,10 +718,10 @@ EXPORT_SYMBOL(dma_outsl);
 void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
 {
         unsigned long flags;
-        
+
         local_irq_save(flags);
-        
-        bfin_write_MDMA_D0_START_ADDR(buf);
+
+        bfin_write_MDMA_D0_START_ADDR(buf);
         bfin_write_MDMA_D0_X_COUNT(len);
         bfin_write_MDMA_D0_X_MODIFY(4);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index bb1f4fb2467c..bafcfa52142b 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -162,7 +162,7 @@ static void port_setup(unsigned short gpio, unsigned short usage)
 
 static void default_gpio(unsigned short gpio)
 {
-        unsigned short bank,bitmask;
+        unsigned short bank, bitmask;
 
         bank = gpio_bank(gpio);
         bitmask = gpio_bit(gpio);
@@ -183,7 +183,7 @@ static int __init bfin_gpio_init(void)
 
         printk(KERN_INFO "Blackfin GPIO Controller\n");
 
-        for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE)
+        for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE)
                 reserved_map[gpio_bank(i)] = 0;
 
 #if defined(BF537_FAMILY) && (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
@@ -478,7 +478,7 @@ u32 gpio_pm_setup(void)
         u32 sic_iwr = 0;
         u16 bank, mask, i, gpio;
 
-        for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) {
+        for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                 mask = wakeup_map[gpio_bank(i)];
                 bank = gpio_bank(i);
 
@@ -522,12 +522,11 @@ u32 gpio_pm_setup(void)
                 return IWR_ENABLE_ALL;
 }
 
-
 void gpio_pm_restore(void)
 {
         u16 bank, mask, i;
 
-        for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) {
+        for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                 mask = wakeup_map[gpio_bank(i)];
                 bank = gpio_bank(i);
 
@@ -591,7 +590,6 @@ int gpio_request(unsigned short gpio, const char *label)
 }
 EXPORT_SYMBOL(gpio_request);
 
-
 void gpio_free(unsigned short gpio)
 {
         unsigned long flags;
@@ -616,7 +614,6 @@ void gpio_free(unsigned short gpio)
 }
 EXPORT_SYMBOL(gpio_free);
 
-
 void gpio_direction_input(unsigned short gpio)
 {
         unsigned long flags;
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index f64ecb638fab..70455949cfd2 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -28,10 +28,11 @@
  */
 
 #include <linux/module.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
+#include <linux/uaccess.h>
+
 #include <asm/checksum.h>
 #include <asm/cacheflush.h>
-#include <asm/uaccess.h>
 
 /* platform dependent support */
 
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c
new file mode 100644
index 000000000000..4d41a40e8133
--- /dev/null
+++ b/arch/blackfin/kernel/cacheinit.c
@@ -0,0 +1,66 @@
+/*
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/cpu.h>
+
+#include <asm/cacheflush.h>
+#include <asm/blackfin.h>
+#include <asm/cplbinit.h>
+
+#if defined(CONFIG_BLKFIN_CACHE)
+void bfin_icache_init(void)
+{
+        unsigned long *table = icplb_table;
+        unsigned long ctrl;
+        int i;
+
+        for (i = 0; i < MAX_CPLBS; i++) {
+                unsigned long addr = *table++;
+                unsigned long data = *table++;
+                if (addr == (unsigned long)-1)
+                        break;
+                bfin_write32(ICPLB_ADDR0 + i * 4, addr);
+                bfin_write32(ICPLB_DATA0 + i * 4, data);
+        }
+        ctrl = bfin_read_IMEM_CONTROL();
+        ctrl |= IMC | ENICPLB;
+        bfin_write_IMEM_CONTROL(ctrl);
+}
+#endif
+
+#if defined(CONFIG_BLKFIN_DCACHE)
+void bfin_dcache_init(void)
+{
+        unsigned long *table = dcplb_table;
+        unsigned long ctrl;
+        int i;
+
+        for (i = 0; i < MAX_CPLBS; i++) {
+                unsigned long addr = *table++;
+                unsigned long data = *table++;
+                if (addr == (unsigned long)-1)
+                        break;
+                bfin_write32(DCPLB_ADDR0 + i * 4, addr);
+                bfin_write32(DCPLB_DATA0 + i * 4, data);
+        }
+        ctrl = bfin_read_DMEM_CONTROL();
+        ctrl |= DMEM_CNTR;
+        bfin_write_DMEM_CONTROL(ctrl);
+}
+#endif
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
new file mode 100644
index 000000000000..bbdb403fcb55
--- /dev/null
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -0,0 +1,433 @@
+/*
+ * Blackfin CPLB initialization
+ *
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/cplbinit.h>
+
+u_long icplb_table[MAX_CPLBS+1];
+u_long dcplb_table[MAX_CPLBS+1];
+
+#ifdef CONFIG_CPLB_SWITCH_TAB_L1
+u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
+u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
+
+#ifdef CONFIG_CPLB_INFO
+u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
+u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
+#endif /* CONFIG_CPLB_INFO */
+
+#else
+
+u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
+u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
+
+#ifdef CONFIG_CPLB_INFO
+u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
+u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
+#endif /* CONFIG_CPLB_INFO */
+
+#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
+
+struct s_cplb {
+        struct cplb_tab init_i;
+        struct cplb_tab init_d;
+        struct cplb_tab switch_i;
+        struct cplb_tab switch_d;
+};
+
+#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
+static struct cplb_desc cplb_data[] = {
+        {
+                .start = 0,
+                .end = SIZE_1K,
+                .psize = SIZE_1K,
+                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
+                .i_conf = SDRAM_OOPS,
+                .d_conf = SDRAM_OOPS,
+#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
+                .valid = 1,
+#else
+                .valid = 0,
+#endif
+                .name = "ZERO Pointer Saveguard",
+        },
+        {
+                .start = L1_CODE_START,
+                .end = L1_CODE_START + L1_CODE_LENGTH,
+                .psize = SIZE_4M,
+                .attr = INITIAL_T | SWITCH_T | I_CPLB,
+                .i_conf = L1_IMEMORY,
+                .d_conf = 0,
+                .valid = 1,
+                .name = "L1 I-Memory",
+        },
+        {
+                .start = L1_DATA_A_START,
+                .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
+                .psize = SIZE_4M,
+                .attr = INITIAL_T | SWITCH_T | D_CPLB,
+                .i_conf = 0,
+                .d_conf = L1_DMEMORY,
+#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
+                .valid = 1,
+#else
+                .valid = 0,
+#endif
+                .name = "L1 D-Memory",
+        },
+        {
+                .start = 0,
+                .end = 0,  /* dynamic */
+                .psize = 0,
+                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
+                .i_conf =  SDRAM_IGENERIC,
+                .d_conf =  SDRAM_DGENERIC,
+                .valid = 1,
+                .name = "SDRAM Kernel",
+        },
+        {
+                .start = 0, /* dynamic */
+                .end = 0, /* dynamic */
+                .psize = 0,
+                .attr = INITIAL_T | SWITCH_T | D_CPLB,
+                .i_conf =  SDRAM_IGENERIC,
+                .d_conf =  SDRAM_DNON_CHBL,
+                .valid = 1,
+                .name = "SDRAM RAM MTD",
+        },
+        {
+                .start = 0, /* dynamic */
+                .end = 0,   /* dynamic */
+                .psize = SIZE_1M,
+                .attr = INITIAL_T | SWITCH_T | D_CPLB,
+                .d_conf = SDRAM_DNON_CHBL,
+                .valid = 1,
+                .name = "SDRAM Uncached DMA ZONE",
+        },
+        {
+                .start = 0, /* dynamic */
+                .end = 0, /* dynamic */
+                .psize = 0,
+                .attr = SWITCH_T | D_CPLB,
+                .i_conf = 0, /* dynamic */
+                .d_conf = 0, /* dynamic */
+                .valid = 1,
+                .name = "SDRAM Reserved Memory",
+        },
+        {
+                .start = ASYNC_BANK0_BASE,
+                .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
+                .psize = 0,
+                .attr = SWITCH_T | D_CPLB,
+                .d_conf = SDRAM_EBIU,
+                .valid = 1,
+                .name = "ASYNC Memory",
+        },
+        {
+#if defined(CONFIG_BF561)
+                .start = L2_SRAM,
+                .end = L2_SRAM_END,
+                .psize = SIZE_1M,
+                .attr = SWITCH_T | D_CPLB,
+                .i_conf = L2_MEMORY,
+                .d_conf = L2_MEMORY,
+                .valid = 1,
+#else
+                .valid = 0,
+#endif
+                .name = "L2 Memory",
+        }
+};
+
+static u16 __init lock_kernel_check(u32 start, u32 end)
+{
+        if ((start <= (u32) _stext && end >= (u32) _end)
+            || (start >= (u32) _stext && end <= (u32) _end))
+                return IN_KERNEL;
+        return 0;
+}
+
+static unsigned short __init
+fill_cplbtab(struct cplb_tab *table,
+             unsigned long start, unsigned long end,
+             unsigned long block_size, unsigned long cplb_data)
+{
+        int i;
+
+        switch (block_size) {
+        case SIZE_4M:
+                i = 3;
+                break;
+        case SIZE_1M:
+                i = 2;
+                break;
+        case SIZE_4K:
+                i = 1;
+                break;
+        case SIZE_1K:
+        default:
+                i = 0;
+                break;
+        }
+
+        cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
+
+        while ((start < end) && (table->pos < table->size)) {
+
+                table->tab[table->pos++] = start;
+
+                if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
+                        table->tab[table->pos++] =
+                            cplb_data | CPLB_LOCK | CPLB_DIRTY;
+                else
+                        table->tab[table->pos++] = cplb_data;
+
+                start += block_size;
+        }
+        return 0;
+}
+
+static unsigned short __init
+close_cplbtab(struct cplb_tab *table)
+{
+
+        while (table->pos < table->size) {
+
+                table->tab[table->pos++] = 0;
+                table->tab[table->pos++] = 0; /* !CPLB_VALID */
+        }
+        return 0;
+}
+
+/* helper function */
+static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
+{
+        if (cplb_data[i].psize) {
+                fill_cplbtab(t,
+                                cplb_data[i].start,
+                                cplb_data[i].end,
+                                cplb_data[i].psize,
+                                cplb_data[i].i_conf);
+        } else {
+#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
+                if (i == SDRAM_KERN) {
+                        fill_cplbtab(t,
+                                        cplb_data[i].start,
+                                        cplb_data[i].end,
+                                        SIZE_4M,
+                                        cplb_data[i].i_conf);
+                } else
+#endif
+                {
+                        fill_cplbtab(t,
+                                        cplb_data[i].start,
+                                        a_start,
+                                        SIZE_1M,
+                                        cplb_data[i].i_conf);
+                        fill_cplbtab(t,
+                                        a_start,
+                                        a_end,
+                                        SIZE_4M,
+                                        cplb_data[i].i_conf);
+                        fill_cplbtab(t, a_end,
+                                        cplb_data[i].end,
+                                        SIZE_1M,
+                                        cplb_data[i].i_conf);
+                }
+        }
+}
+
+static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
+{
+        if (cplb_data[i].psize) {
+                fill_cplbtab(t,
+                                cplb_data[i].start,
+                                cplb_data[i].end,
+                                cplb_data[i].psize,
+                                cplb_data[i].d_conf);
+        } else {
+                fill_cplbtab(t,
+                                cplb_data[i].start,
+                                a_start, SIZE_1M,
+                                cplb_data[i].d_conf);
+                fill_cplbtab(t, a_start,
+                                a_end, SIZE_4M,
+                                cplb_data[i].d_conf);
+                fill_cplbtab(t, a_end,
+                                cplb_data[i].end,
+                                SIZE_1M,
+                                cplb_data[i].d_conf);
+        }
+}
+
+void __init generate_cpl_tables(void)
+{
+
+        u16 i, j, process;
+        u32 a_start, a_end, as, ae, as_1m;
+
+        struct cplb_tab *t_i = NULL;
+        struct cplb_tab *t_d = NULL;
+        struct s_cplb cplb;
+
+        cplb.init_i.size = MAX_CPLBS;
+        cplb.init_d.size = MAX_CPLBS;
+        cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
+        cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
+
+        cplb.init_i.pos = 0;
+        cplb.init_d.pos = 0;
+        cplb.switch_i.pos = 0;
+        cplb.switch_d.pos = 0;
+
+        cplb.init_i.tab = icplb_table;
+        cplb.init_d.tab = dcplb_table;
+        cplb.switch_i.tab = ipdt_table;
+        cplb.switch_d.tab = dpdt_table;
+
+        cplb_data[SDRAM_KERN].end = memory_end;
+
+#ifdef CONFIG_MTD_UCLINUX
+        cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
+        cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
+        cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
+# if defined(CONFIG_ROMFS_FS)
+        cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
+
+        /*
+         * The ROMFS_FS size is often not multiple of 1MB.
+         * This can cause multiple CPLB sets covering the same memory area.
+         * This will then cause multiple CPLB hit exceptions.
+         * Workaround: We ensure a contiguous memory area by extending the kernel
+         * memory section over the mtd section.
+         * For ROMFS_FS memory must be covered with ICPLBs anyways.
+         * So there is no difference between kernel and mtd memory setup.
+         */
+
+        cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
+        cplb_data[SDRAM_RAM_MTD].valid = 0;
+
+# endif
+#else
+        cplb_data[SDRAM_RAM_MTD].valid = 0;
+#endif
+
+        cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
+        cplb_data[SDRAM_DMAZ].end = _ramend;
+
+        cplb_data[RES_MEM].start = _ramend;
+        cplb_data[RES_MEM].end = physical_mem_end;
+
+        if (reserved_mem_dcache_on)
+                cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
+        else
+                cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
+
+        if (reserved_mem_icache_on)
+                cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
+        else
+                cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
+
+        for (i = ZERO_P; i <= L2_MEM; i++) {
+                if (!cplb_data[i].valid)
+                        continue;
+
+                as_1m = cplb_data[i].start % SIZE_1M;
+
+                /* We need to make sure all sections are properly 1M aligned
+                 * However between Kernel Memory and the Kernel mtd section, depending on the
+                 * rootfs size, there can be overlapping memory areas.
+                 */
+
+                if (as_1m && i != L1I_MEM && i != L1D_MEM) {
+#ifdef CONFIG_MTD_UCLINUX
+                        if (i == SDRAM_RAM_MTD) {
+                                if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
+                                        cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
+                                else
+                                        cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
+                        } else
+#endif
+                                printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
+                                       cplb_data[i].name, cplb_data[i].start);
+                }
+
+                as = cplb_data[i].start % SIZE_4M;
+                ae = cplb_data[i].end % SIZE_4M;
+
+                if (as)
+                        a_start = cplb_data[i].start + (SIZE_4M - (as));
+                else
+                        a_start = cplb_data[i].start;
+
+                a_end = cplb_data[i].end - ae;
+
+                for (j = INITIAL_T; j <= SWITCH_T; j++) {
+
+                        switch (j) {
+                        case INITIAL_T:
+                                if (cplb_data[i].attr & INITIAL_T) {
+                                        t_i = &cplb.init_i;
+                                        t_d = &cplb.init_d;
+                                        process = 1;
+                                } else
+                                        process = 0;
+                                break;
+                        case SWITCH_T:
+                                if (cplb_data[i].attr & SWITCH_T) {
+                                        t_i = &cplb.switch_i;
+                                        t_d = &cplb.switch_d;
+                                        process = 1;
+                                } else
+                                        process = 0;
+                                break;
+                        default:
+                                        process = 0;
+                                break;
+                        }
+
+                        if (!process)
+                                continue;
+                        if (cplb_data[i].attr & I_CPLB)
+                                __fill_code_cplbtab(t_i, i, a_start, a_end);
+
+                        if (cplb_data[i].attr & D_CPLB)
+                                __fill_data_cplbtab(t_d, i, a_start, a_end);
+                }
+        }
+
+/* close tables */
+
+        close_cplbtab(&cplb.init_i);
+        close_cplbtab(&cplb.init_d);
+
+        cplb.init_i.tab[cplb.init_i.pos] = -1;
+        cplb.init_d.tab[cplb.init_d.pos] = -1;
+        cplb.switch_i.tab[cplb.switch_i.pos] = -1;
+        cplb.switch_d.tab[cplb.switch_d.pos] = -1;
+
+}
+
+#endif
+
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index 539eb24e062f..ea48d5b13f11 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -34,8 +34,8 @@
 #include <linux/spinlock.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/io.h>
 #include <asm/cacheflush.h>
-#include <asm/io.h>
 #include <asm/bfin-global.h>
 
 static spinlock_t dma_page_lock;
@@ -159,10 +159,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 
         BUG_ON(direction == DMA_NONE);
 
-        for (i = 0; i < nents; i++)
-                invalidate_dcache_range(sg_dma_address(&sg[i]),
-                                        sg_dma_address(&sg[i]) +
-                                        sg_dma_len(&sg[i]));
+        for (i = 0; i < nents; i++, sg++) {
+                sg->dma_address = page_address(sg->page) + sg->offset;
+
+                invalidate_dcache_range(sg_dma_address(sg),
+                                        sg_dma_address(sg) +
+                                        sg_dma_len(sg));
+        }
 
         return nents;
 }
diff --git a/arch/blackfin/kernel/dualcore_test.c b/arch/blackfin/kernel/dualcore_test.c
index 8b89c99f9dfa..0fcba74840b7 100644
--- a/arch/blackfin/kernel/dualcore_test.c
+++ b/arch/blackfin/kernel/dualcore_test.c
@@ -30,19 +30,19 @@
 #include <linux/init.h>
 #include <linux/module.h>
 
-static int *testarg = (int*)0xfeb00000;
+static int *testarg = (int *)0xfeb00000;
 
 static int test_init(void)
 {
         *testarg = 1;
-        printk("Dual core test module inserted: set testarg = [%d]\n @ [%p]\n",
+        printk(KERN_INFO "Dual core test module inserted: set testarg = [%d]\n @ [%p]\n",
                *testarg, testarg);
         return 0;
 }
 
 static void test_exit(void)
 {
-        printk("Dual core test module removed: testarg = [%d]\n", *testarg);
+        printk(KERN_INFO "Dual core test module removed: testarg = [%d]\n", *testarg);
 }
 
 module_init(test_init);
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
new file mode 100644
index 000000000000..d8b1ebc70996
--- /dev/null
+++ b/arch/blackfin/kernel/fixed_code.S
@@ -0,0 +1,132 @@
+/*
+ * This file contains sequences of code that will be copied to a
+ * fixed location, defined in <asm/atomic_seq.h>.  The interrupt
+ * handlers ensure that these sequences appear to be atomic when
+ * executed from userspace.
+ * These are aligned to 16 bytes, so that we have some space to replace
+ * these sequences with something else (e.g. kernel traps if we ever do
+ * BF561 SMP).
+ */
+#include <linux/linkage.h>
+#include <linux/unistd.h>
+#include <asm/entry.h>
+
+.text
+ENTRY(_fixed_code_start)
+
+.align 16
+ENTRY(_sigreturn_stub)
+        P0 = __NR_rt_sigreturn;
+        EXCPT 0;
+        /* Speculative execution paranoia.  */
+0:      JUMP.S 0b;
+ENDPROC (_sigreturn_stub)
+
+.align 16
+        /*
+         * Atomic swap, 8 bit.
+         * Inputs:      P0: memory address to use
+         *              R1: value to store
+         * Output:      R0: old contents of the memory address, zero extended.
+         */
+ENTRY(_atomic_xchg32)
+        R0 = [P0];
+        [P0] = R1;
+        rts;
+ENDPROC (_atomic_xchg32)
+
+.align 16
+        /*
+         * Compare and swap, 32 bit.
+         * Inputs:      P0: memory address to use
+         *              R1: compare value
+         *              R2: new value to store
+         * The new value is stored if the contents of the memory
+         * address is equal to the compare value.
+         * Output:      R0: old contents of the memory address.
+         */
+ENTRY(_atomic_cas32)
+        R0 = [P0];
+        CC = R0 == R1;
+        IF !CC JUMP 1f;
+        [P0] = R2;
+1:
+        rts;
+ENDPROC (_atomic_cas32)
+
+.align 16
+        /*
+         * Atomic add, 32 bit.
+         * Inputs:      P0: memory address to use
+         *              R0: value to add
+         * Outputs:     R0: new contents of the memory address.
+         *              R1: previous contents of the memory address.
+         */
+ENTRY(_atomic_add32)
+        R1 = [P0];
+        R0 = R1 + R0;
+        [P0] = R0;
+        rts;
+ENDPROC (_atomic_add32)
+
+.align 16
+        /*
+         * Atomic sub, 32 bit.
+         * Inputs:      P0: memory address to use
+         *              R0: value to subtract
+         * Outputs:     R0: new contents of the memory address.
+         *              R1: previous contents of the memory address.
+         */
+ENTRY(_atomic_sub32)
+        R1 = [P0];
+        R0 = R1 - R0;
+        [P0] = R0;
+        rts;
+ENDPROC (_atomic_sub32)
+
+.align 16
+        /*
+         * Atomic ior, 32 bit.
+         * Inputs:      P0: memory address to use
+         *              R0: value to ior
+         * Outputs:     R0: new contents of the memory address.
+         *              R1: previous contents of the memory address.
+         */
+ENTRY(_atomic_ior32)
+        R1 = [P0];
+        R0 = R1 | R0;
+        [P0] = R0;
+        rts;
+ENDPROC (_atomic_ior32)
+
+.align 16
+        /*
+         * Atomic ior, 32 bit.
+         * Inputs:      P0: memory address to use
+         *              R0: value to ior
+         * Outputs:     R0: new contents of the memory address.
+         *              R1: previous contents of the memory address.
+         */
+ENTRY(_atomic_and32)
+        R1 = [P0];
+        R0 = R1 & R0;
+        [P0] = R0;
+        rts;
+ENDPROC (_atomic_ior32)
+
+.align 16
+        /*
+         * Atomic ior, 32 bit.
+         * Inputs:      P0: memory address to use
+         *              R0: value to ior
+         * Outputs:     R0: new contents of the memory address.
+         *              R1: previous contents of the memory address.
+         */
+ENTRY(_atomic_xor32)
+        R1 = [P0];
+        R0 = R1 ^ R0;
+        [P0] = R0;
+        rts;
+ENDPROC (_atomic_ior32)
+
+ENTRY(_fixed_code_end)
diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c
index a92587b628b5..d188b2430536 100644
--- a/arch/blackfin/kernel/flat.c
+++ b/arch/blackfin/kernel/flat.c
@@ -36,24 +36,22 @@ unsigned long bfin_get_addr_from_rp(unsigned long *ptr,
         unsigned long val;
 
         switch (type) {
-                case FLAT_BFIN_RELOC_TYPE_16_BIT:
-                case FLAT_BFIN_RELOC_TYPE_16H_BIT:
-                        usptr = (unsigned short *)ptr;
-                        pr_debug("*usptr = %x", get_unaligned(usptr));
-                        val = get_unaligned(usptr);
-                        val += *persistent;
-                        break;
+        case FLAT_BFIN_RELOC_TYPE_16_BIT:
+        case FLAT_BFIN_RELOC_TYPE_16H_BIT:
+                usptr = (unsigned short *)ptr;
+                pr_debug("*usptr = %x", get_unaligned(usptr));
+                val = get_unaligned(usptr);
+                val += *persistent;
+                break;
 
-                case FLAT_BFIN_RELOC_TYPE_32_BIT:
-                        pr_debug("*ptr = %lx", get_unaligned(ptr));
-                        val = get_unaligned(ptr);
-                        break;
+        case FLAT_BFIN_RELOC_TYPE_32_BIT:
+                pr_debug("*ptr = %lx", get_unaligned(ptr));
+                val = get_unaligned(ptr);
+                break;
 
-                default:
-                        pr_debug("BINFMT_FLAT: Unknown relocation type %x\n",
-                                type);
-
-                        return 0;
+        default:
+                pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
+                return 0;
         }
 
         /*
@@ -81,21 +79,20 @@ void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
         int type = (relval >> 26) & 7;
 
         switch (type) {
-                case FLAT_BFIN_RELOC_TYPE_16_BIT:
-                        put_unaligned(addr, usptr);
-                        pr_debug("new value %x at %p", get_unaligned(usptr),
-                                usptr);
-                        break;
+        case FLAT_BFIN_RELOC_TYPE_16_BIT:
+                put_unaligned(addr, usptr);
+                pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
+                break;
 
-                case FLAT_BFIN_RELOC_TYPE_16H_BIT:
-                        put_unaligned(addr >> 16, usptr);
-                        pr_debug("new value %x", get_unaligned(usptr));
-                        break;
+        case FLAT_BFIN_RELOC_TYPE_16H_BIT:
+                put_unaligned(addr >> 16, usptr);
+                pr_debug("new value %x", get_unaligned(usptr));
+                break;
 
-                case FLAT_BFIN_RELOC_TYPE_32_BIT:
-                        put_unaligned(addr, ptr);
-                        pr_debug("new ptr =%lx", get_unaligned(ptr));
-                        break;
+        case FLAT_BFIN_RELOC_TYPE_32_BIT:
+                put_unaligned(addr, ptr);
+                pr_debug("new ptr =%lx", get_unaligned(ptr));
+                break;
         }
 }
 EXPORT_SYMBOL(bfin_put_addr_at_rp);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 80996a1a94ca..1fc001c7abda 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -82,7 +82,7 @@ int show_interrupts(struct seq_file *p, void *v)
                         seq_printf(p, ", %s", action->name);
 
                 seq_putc(p, '\n');
-              unlock:
+ unlock:
                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
                 seq_printf(p, "Err: %10lu\n", irq_err_count);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
new file mode 100644
index 000000000000..a9c15515bfd7
--- /dev/null
+++ b/arch/blackfin/kernel/kgdb.c
@@ -0,0 +1,421 @@
+/*
+ * File:         arch/blackfin/kernel/kgdb.c
+ * Based on:
+ * Author:       Sonic Zhang
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:          $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
+ *
+ * Modified:
+ *               Copyright 2005-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/ptrace.h>               /* for linux pt_regs struct */
+#include <linux/kgdb.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/debugger.h>
+#include <linux/errno.h>
+#include <linux/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/blackfin.h>
+
+/* Put the error code here just in case the user cares.  */
+int gdb_bf533errcode;
+/* Likewise, the vector number here (since GDB only gets the signal
+   number through the usual means, and that's not very specific).  */
+int gdb_bf533vector = -1;
+
+#if KGDB_MAX_NO_CPUS != 8
+#error change the definition of slavecpulocks
+#endif
+
+void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        gdb_regs[BFIN_R0] = regs->r0;
+        gdb_regs[BFIN_R1] = regs->r1;
+        gdb_regs[BFIN_R2] = regs->r2;
+        gdb_regs[BFIN_R3] = regs->r3;
+        gdb_regs[BFIN_R4] = regs->r4;
+        gdb_regs[BFIN_R5] = regs->r5;
+        gdb_regs[BFIN_R6] = regs->r6;
+        gdb_regs[BFIN_R7] = regs->r7;
+        gdb_regs[BFIN_P0] = regs->p0;
+        gdb_regs[BFIN_P1] = regs->p1;
+        gdb_regs[BFIN_P2] = regs->p2;
+        gdb_regs[BFIN_P3] = regs->p3;
+        gdb_regs[BFIN_P4] = regs->p4;
+        gdb_regs[BFIN_P5] = regs->p5;
+        gdb_regs[BFIN_SP] = regs->reserved;
+        gdb_regs[BFIN_FP] = regs->fp;
+        gdb_regs[BFIN_I0] = regs->i0;
+        gdb_regs[BFIN_I1] = regs->i1;
+        gdb_regs[BFIN_I2] = regs->i2;
+        gdb_regs[BFIN_I3] = regs->i3;
+        gdb_regs[BFIN_M0] = regs->m0;
+        gdb_regs[BFIN_M1] = regs->m1;
+        gdb_regs[BFIN_M2] = regs->m2;
+        gdb_regs[BFIN_M3] = regs->m3;
+        gdb_regs[BFIN_B0] = regs->b0;
+        gdb_regs[BFIN_B1] = regs->b1;
+        gdb_regs[BFIN_B2] = regs->b2;
+        gdb_regs[BFIN_B3] = regs->b3;
+        gdb_regs[BFIN_L0] = regs->l0;
+        gdb_regs[BFIN_L1] = regs->l1;
+        gdb_regs[BFIN_L2] = regs->l2;
+        gdb_regs[BFIN_L3] = regs->l3;
+        gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
+        gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
+        gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
+        gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
+        gdb_regs[BFIN_ASTAT] = regs->astat;
+        gdb_regs[BFIN_RETS] = regs->rets;
+        gdb_regs[BFIN_LC0] = regs->lc0;
+        gdb_regs[BFIN_LT0] = regs->lt0;
+        gdb_regs[BFIN_LB0] = regs->lb0;
+        gdb_regs[BFIN_LC1] = regs->lc1;
+        gdb_regs[BFIN_LT1] = regs->lt1;
+        gdb_regs[BFIN_LB1] = regs->lb1;
+        gdb_regs[BFIN_CYCLES] = 0;
+        gdb_regs[BFIN_CYCLES2] = 0;
+        gdb_regs[BFIN_USP] = regs->usp;
+        gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
+        gdb_regs[BFIN_SYSCFG] = regs->syscfg;
+        gdb_regs[BFIN_RETI] = regs->pc;
+        gdb_regs[BFIN_RETX] = regs->retx;
+        gdb_regs[BFIN_RETN] = regs->retn;
+        gdb_regs[BFIN_RETE] = regs->rete;
+        gdb_regs[BFIN_PC] = regs->pc;
+        gdb_regs[BFIN_CC] = 0;
+        gdb_regs[BFIN_EXTRA1] = 0;
+        gdb_regs[BFIN_EXTRA2] = 0;
+        gdb_regs[BFIN_EXTRA3] = 0;
+        gdb_regs[BFIN_IPEND] = regs->ipend;
+}
+
+/*
+ * Extracts ebp, esp and eip values understandable by gdb from the values
+ * saved by switch_to.
+ * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
+ * prior to entering switch_to is 8 greater then the value that is saved.
+ * If switch_to changes, change following code appropriately.
+ */
+void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
+{
+        gdb_regs[BFIN_SP] = p->thread.ksp;
+        gdb_regs[BFIN_PC] = p->thread.pc;
+        gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
+}
+
+void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        regs->r0 = gdb_regs[BFIN_R0];
+        regs->r1 = gdb_regs[BFIN_R1];
+        regs->r2 = gdb_regs[BFIN_R2];
+        regs->r3 = gdb_regs[BFIN_R3];
+        regs->r4 = gdb_regs[BFIN_R4];
+        regs->r5 = gdb_regs[BFIN_R5];
+        regs->r6 = gdb_regs[BFIN_R6];
+        regs->r7 = gdb_regs[BFIN_R7];
+        regs->p0 = gdb_regs[BFIN_P0];
+        regs->p1 = gdb_regs[BFIN_P1];
+        regs->p2 = gdb_regs[BFIN_P2];
+        regs->p3 = gdb_regs[BFIN_P3];
+        regs->p4 = gdb_regs[BFIN_P4];
+        regs->p5 = gdb_regs[BFIN_P5];
+        regs->fp = gdb_regs[BFIN_FP];
+        regs->i0 = gdb_regs[BFIN_I0];
+        regs->i1 = gdb_regs[BFIN_I1];
+        regs->i2 = gdb_regs[BFIN_I2];
+        regs->i3 = gdb_regs[BFIN_I3];
+        regs->m0 = gdb_regs[BFIN_M0];
+        regs->m1 = gdb_regs[BFIN_M1];
+        regs->m2 = gdb_regs[BFIN_M2];
+        regs->m3 = gdb_regs[BFIN_M3];
+        regs->b0 = gdb_regs[BFIN_B0];
+        regs->b1 = gdb_regs[BFIN_B1];
+        regs->b2 = gdb_regs[BFIN_B2];
+        regs->b3 = gdb_regs[BFIN_B3];
+        regs->l0 = gdb_regs[BFIN_L0];
+        regs->l1 = gdb_regs[BFIN_L1];
+        regs->l2 = gdb_regs[BFIN_L2];
+        regs->l3 = gdb_regs[BFIN_L3];
+        regs->a0x = gdb_regs[BFIN_A0_DOT_X];
+        regs->a0w = gdb_regs[BFIN_A0_DOT_W];
+        regs->a1x = gdb_regs[BFIN_A1_DOT_X];
+        regs->a1w = gdb_regs[BFIN_A1_DOT_W];
+        regs->rets = gdb_regs[BFIN_RETS];
+        regs->lc0 = gdb_regs[BFIN_LC0];
+        regs->lt0 = gdb_regs[BFIN_LT0];
+        regs->lb0 = gdb_regs[BFIN_LB0];
+        regs->lc1 = gdb_regs[BFIN_LC1];
+        regs->lt1 = gdb_regs[BFIN_LT1];
+        regs->lb1 = gdb_regs[BFIN_LB1];
+        regs->usp = gdb_regs[BFIN_USP];
+        regs->syscfg = gdb_regs[BFIN_SYSCFG];
+        regs->retx = gdb_regs[BFIN_PC];
+        regs->retn = gdb_regs[BFIN_RETN];
+        regs->rete = gdb_regs[BFIN_RETE];
+        regs->pc = gdb_regs[BFIN_PC];
+
+#if 0                           /* can't change these */
+        regs->astat = gdb_regs[BFIN_ASTAT];
+        regs->seqstat = gdb_regs[BFIN_SEQSTAT];
+        regs->ipend = gdb_regs[BFIN_IPEND];
+#endif
+}
+
+struct hw_breakpoint {
+        unsigned int occupied:1;
+        unsigned int skip:1;
+        unsigned int enabled:1;
+        unsigned int type:1;
+        unsigned int dataacc:2;
+        unsigned short count;
+        unsigned int addr;
+} breakinfo[HW_BREAKPOINT_NUM];
+
+int kgdb_arch_init(void)
+{
+        kgdb_remove_all_hw_break();
+        return 0;
+}
+
+int kgdb_set_hw_break(unsigned long addr)
+{
+        int breakno;
+        for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
+                if (!breakinfo[breakno].occupied) {
+                        breakinfo[breakno].occupied = 1;
+                        breakinfo[breakno].enabled = 1;
+                        breakinfo[breakno].type = 1;
+                        breakinfo[breakno].addr = addr;
+                        return 0;
+                }
+
+        return -ENOSPC;
+}
+
+int kgdb_remove_hw_break(unsigned long addr)
+{
+        int breakno;
+        for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
+                if (breakinfo[breakno].addr == addr)
+                        memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint));
+
+        return 0;
+}
+
+void kgdb_remove_all_hw_break(void)
+{
+        memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8);
+}
+
+/*
+void kgdb_show_info(void)
+{
+        printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n",
+                bfin_read_WPIA0(), bfin_read_WPIACNT0(),
+                bfin_read_WPIACTL(), bfin_read_WPSTAT());
+}
+*/
+
+void kgdb_correct_hw_break(void)
+{
+        int breakno;
+        int correctit;
+        uint32_t wpdactl = bfin_read_WPDACTL();
+
+        correctit = 0;
+        for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) {
+                if (breakinfo[breakno].type == 1) {
+                        switch (breakno) {
+                        case 0:
+                                if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) {
+                                        correctit = 1;
+                                        wpdactl &= ~(WPIREN01|EMUSW0);
+                                        wpdactl |= WPIAEN0|WPICNTEN0;
+                                        bfin_write_WPIA0(breakinfo[breakno].addr);
+                                        bfin_write_WPIACNT0(breakinfo[breakno].skip);
+                                } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) {
+                                        correctit = 1;
+                                        wpdactl &= ~WPIAEN0;
+                                }
+                                break;
+
+                        case 1:
+                                if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) {
+                                        correctit = 1;
+                                        wpdactl &= ~(WPIREN01|EMUSW1);
+                                        wpdactl |= WPIAEN1|WPICNTEN1;
+                                        bfin_write_WPIA1(breakinfo[breakno].addr);
+                                        bfin_write_WPIACNT1(breakinfo[breakno].skip);
+                                } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) {
+                                        correctit = 1;
+                                        wpdactl &= ~WPIAEN1;
+                                }
+                                break;
+
+                        case 2:
+                                if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) {
+                                        correctit = 1;
+                                        wpdactl &= ~(WPIREN23|EMUSW2);
+                                        wpdactl |= WPIAEN2|WPICNTEN2;
+                                        bfin_write_WPIA2(breakinfo[breakno].addr);
+                                        bfin_write_WPIACNT2(breakinfo[breakno].skip);
+                                } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) {
+                                        correctit = 1;
+                                        wpdactl &= ~WPIAEN2;
+                                }
+                                break;
+
+                        case 3:
+                                if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) {
+                                        correctit = 1;
+                                        wpdactl &= ~(WPIREN23|EMUSW3);
+                                        wpdactl |= WPIAEN3|WPICNTEN3;
+                                        bfin_write_WPIA3(breakinfo[breakno].addr);
+                                        bfin_write_WPIACNT3(breakinfo[breakno].skip);
+                                } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) {
+                                        correctit = 1;
+                                        wpdactl &= ~WPIAEN3;
+                                }
+                                break;
+                        case 4:
+                                if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) {
+                                        correctit = 1;
+                                        wpdactl &= ~(WPIREN45|EMUSW4);
+                                        wpdactl |= WPIAEN4|WPICNTEN4;
+                                        bfin_write_WPIA4(breakinfo[breakno].addr);
+                                        bfin_write_WPIACNT4(breakinfo[breakno].skip);
+                                } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) {
+                                        correctit = 1;
+                                        wpdactl &= ~WPIAEN4;
+                                }
+                                break;
+                        case 5:
+                                if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) {
+                                        correctit = 1;
+                                        wpdactl &= ~(WPIREN45|EMUSW5);
+                                        wpdactl |= WPIAEN5|WPICNTEN5;
+                                        bfin_write_WPIA5(breakinfo[breakno].addr);
+                                        bfin_write_WPIACNT5(breakinfo[breakno].skip);
+                                } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) {
+                                        correctit = 1;
+                                        wpdactl &= ~WPIAEN5;
+                                }
+                                break;
+                        }
+                }
+        }
+        if (correctit) {
+                wpdactl &= ~WPAND;
+                wpdactl |= WPPWR;
+                /*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/
+                bfin_write_WPDACTL(wpdactl);
+                CSYNC();
+                /*kgdb_show_info();*/
+        }
+}
+
+void kgdb_disable_hw_debug(struct pt_regs *regs)
+{
+        /* Disable hardware debugging while we are in kgdb */
+        bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1);
+        CSYNC();
+}
+
+void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code)
+{
+        /* Master processor is completely in the debugger */
+        gdb_bf533vector = eVector;
+        gdb_bf533errcode = err_code;
+}
+
+int kgdb_arch_handle_exception(int exceptionVector, int signo,
+                               int err_code, char *remcom_in_buffer,
+                               char *remcom_out_buffer,
+                               struct pt_regs *linux_regs)
+{
+        long addr;
+        long breakno;
+        char *ptr;
+        int newPC;
+        int wp_status;
+
+        switch (remcom_in_buffer[0]) {
+        case 'c':
+        case 's':
+                if (kgdb_contthread && kgdb_contthread != current) {
+                        strcpy(remcom_out_buffer, "E00");
+                        break;
+                }
+
+                kgdb_contthread = NULL;
+
+                /* try to read optional parameter, pc unchanged if no parm */
+                ptr = &remcom_in_buffer[1];
+                if (kgdb_hex2long(&ptr, &addr)) {
+                        linux_regs->retx = addr;
+                }
+                newPC = linux_regs->retx;
+
+                /* clear the trace bit */
+                linux_regs->syscfg &= 0xfffffffe;
+
+                /* set the trace bit if we're stepping */
+                if (remcom_in_buffer[0] == 's') {
+                        linux_regs->syscfg |= 0x1;
+                        debugger_step = 1;
+                }
+
+                wp_status = bfin_read_WPSTAT();
+                CSYNC();
+
+                if (exceptionVector == VEC_WATCH) {
+                        for (breakno = 0; breakno < 6; ++breakno) {
+                                if (wp_status & (1 << breakno)) {
+                                        breakinfo->skip = 1;
+                                        break;
+                                }
+                        }
+                }
+                kgdb_correct_hw_break();
+
+                bfin_write_WPSTAT(0);
+
+                return 0;
+        }                       /* switch */
+        return -1;              /* this means that we do not want to exit from the handler */
+}
+
+struct kgdb_arch arch_kgdb_ops = {
+        .gdb_bpt_instr = {0xa1},
+        .flags = KGDB_HW_BREAKPOINT,
+};
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
index 372f756f1ad9..8b9fe29d03f4 100644
--- a/arch/blackfin/kernel/module.c
+++ b/arch/blackfin/kernel/module.c
@@ -165,8 +165,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
 
         for (s = sechdrs; s < sechdrs_end; ++s) {
                 if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) ||
-                        ((strcmp(".text", secstrings + s->sh_name)==0) &&
-                         (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) {
+                    ((strcmp(".text", secstrings + s->sh_name) == 0) &&
+                     (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) {
                         mod->arch.text_l1 = s;
                         dest = l1_inst_sram_alloc(s->sh_size);
                         if (dest == NULL) {
@@ -179,9 +179,9 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
                         s->sh_flags &= ~SHF_ALLOC;
                         s->sh_addr = (unsigned long)dest;
                 }
-                if ((strcmp(".l1.data", secstrings + s->sh_name) == 0)||
-                        ((strcmp(".data", secstrings + s->sh_name)==0) &&
-                         (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
+                if ((strcmp(".l1.data", secstrings + s->sh_name) == 0) ||
+                    ((strcmp(".data", secstrings + s->sh_name) == 0) &&
+                     (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
                         mod->arch.data_a_l1 = s;
                         dest = l1_data_sram_alloc(s->sh_size);
                         if (dest == NULL) {
@@ -195,8 +195,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
                         s->sh_addr = (unsigned long)dest;
                 }
                 if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 ||
-                        ((strcmp(".bss", secstrings + s->sh_name)==0) &&
-                         (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
+                    ((strcmp(".bss", secstrings + s->sh_name) == 0) &&
+                     (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
                         mod->arch.bss_a_l1 = s;
                         dest = l1_data_sram_alloc(s->sh_size);
                         if (dest == NULL) {
@@ -326,7 +326,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
                         pr_debug("before %x after %x\n", *location16,
                                        (value & 0xffff));
                         tmp = (value & 0xffff);
-                        if((unsigned long)location16 >= L1_CODE_START) {
+                        if ((unsigned long)location16 >= L1_CODE_START) {
                                 dma_memcpy(location16, &tmp, 2);
                         } else
                                 *location16 = tmp;
@@ -335,7 +335,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
                         pr_debug("before %x after %x\n", *location16,
                                        ((value >> 16) & 0xffff));
                         tmp = ((value >> 16) & 0xffff);
-                        if((unsigned long)location16 >= L1_CODE_START) {
+                        if ((unsigned long)location16 >= L1_CODE_START) {
                                 dma_memcpy(location16, &tmp, 2);
                         } else
                                 *location16 = tmp;
@@ -404,8 +404,8 @@ module_finalize(const Elf_Ehdr * hdr,
                         continue;
 
                 if ((sechdrs[i].sh_type == SHT_RELA) &&
-                    ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0)||
-                        ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) &&
+                    ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) ||
+                    ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) &&
                          (hdr->e_flags & FLG_CODE_IN_L1)))) {
                         apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
                                            symindex, i, mod);
@@ -417,13 +417,13 @@ module_finalize(const Elf_Ehdr * hdr,
 void module_arch_cleanup(struct module *mod)
 {
         if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr))
-                l1_inst_sram_free((void*)mod->arch.text_l1->sh_addr);
+                l1_inst_sram_free((void *)mod->arch.text_l1->sh_addr);
         if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr))
-                l1_data_sram_free((void*)mod->arch.data_a_l1->sh_addr);
+                l1_data_sram_free((void *)mod->arch.data_a_l1->sh_addr);
         if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr))
-                l1_data_sram_free((void*)mod->arch.bss_a_l1->sh_addr);
+                l1_data_sram_free((void *)mod->arch.bss_a_l1->sh_addr);
         if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr))
-                l1_data_B_sram_free((void*)mod->arch.data_b_l1->sh_addr);
+                l1_data_B_sram_free((void *)mod->arch.data_b_l1->sh_addr);
         if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr))
-                l1_data_B_sram_free((void*)mod->arch.bss_b_l1->sh_addr);
+                l1_data_B_sram_free((void *)mod->arch.bss_b_l1->sh_addr);
 }
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 3eff7439d8d3..5a51dd6ab280 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -32,9 +32,10 @@
 #include <linux/unistd.h>
 #include <linux/user.h>
 #include <linux/a.out.h>
+#include <linux/uaccess.h>
 
 #include <asm/blackfin.h>
-#include <asm/uaccess.h>
+#include <asm/fixed_code.h>
 
 #define LED_ON  0
 #define LED_OFF 1
@@ -173,8 +174,8 @@ void show_regs(struct pt_regs *regs)
         printk(KERN_NOTICE "R4: %08lx  R5: %08lx  R6: %08lx  R7: %08lx\n",
                regs->r4, regs->r5, regs->r6, regs->r7);
 
-        if (!(regs->ipend))
-                printk("USP: %08lx\n", rdusp());
+        if (!regs->ipend)
+                printk(KERN_NOTICE "USP: %08lx\n", rdusp());
 }
 
 /* Fill in the fpu structure for a core dump.  */
@@ -322,7 +323,7 @@ asmlinkage int sys_execve(char *name, char **argv, char **envp)
                 goto out;
         error = do_execve(filename, argv, envp, regs);
         putname(filename);
-      out:
+ out:
         unlock_kernel();
         return error;
 }
@@ -350,13 +351,77 @@ unsigned long get_wchan(struct task_struct *p)
         return 0;
 }
 
+void finish_atomic_sections (struct pt_regs *regs)
+{
+        if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END)
+                return;
+
+        switch (regs->pc) {
+        case ATOMIC_XCHG32 + 2:
+                put_user(regs->r1, (int *)regs->p0);
+                regs->pc += 2;
+                break;
+
+        case ATOMIC_CAS32 + 2:
+        case ATOMIC_CAS32 + 4:
+                if (regs->r0 == regs->r1)
+                        put_user(regs->r2, (int *)regs->p0);
+                regs->pc = ATOMIC_CAS32 + 8;
+                break;
+        case ATOMIC_CAS32 + 6:
+                put_user(regs->r2, (int *)regs->p0);
+                regs->pc += 2;
+                break;
+
+        case ATOMIC_ADD32 + 2:
+                regs->r0 = regs->r1 + regs->r0;
+                /* fall through */
+        case ATOMIC_ADD32 + 4:
+                put_user(regs->r0, (int *)regs->p0);
+                regs->pc = ATOMIC_ADD32 + 6;
+                break;
+
+        case ATOMIC_SUB32 + 2:
+                regs->r0 = regs->r1 - regs->r0;
+                /* fall through */
+        case ATOMIC_SUB32 + 4:
+                put_user(regs->r0, (int *)regs->p0);
+                regs->pc = ATOMIC_SUB32 + 6;
+                break;
+
+        case ATOMIC_IOR32 + 2:
+                regs->r0 = regs->r1 | regs->r0;
+                /* fall through */
+        case ATOMIC_IOR32 + 4:
+                put_user(regs->r0, (int *)regs->p0);
+                regs->pc = ATOMIC_IOR32 + 6;
+                break;
+
+        case ATOMIC_AND32 + 2:
+                regs->r0 = regs->r1 & regs->r0;
+                /* fall through */
+        case ATOMIC_AND32 + 4:
+                put_user(regs->r0, (int *)regs->p0);
+                regs->pc = ATOMIC_AND32 + 6;
+                break;
+
+        case ATOMIC_XOR32 + 2:
+                regs->r0 = regs->r1 ^ regs->r0;
+                /* fall through */
+        case ATOMIC_XOR32 + 4:
+                put_user(regs->r0, (int *)regs->p0);
+                regs->pc = ATOMIC_XOR32 + 6;
+                break;
+        }
+}
+
 #if defined(CONFIG_ACCESS_CHECK)
 int _access_ok(unsigned long addr, unsigned long size)
 {
 
         if (addr > (addr + size))
                 return 0;
-        if (segment_eq(get_fs(),KERNEL_DS))
+        if (segment_eq(get_fs(), KERNEL_DS))
                 return 1;
 #ifdef CONFIG_MTD_UCLINUX
         if (addr >= memory_start && (addr + size) <= memory_end)
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index e718bb4a1ef0..ed800c7456dd 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -36,8 +36,8 @@
 #include <linux/ptrace.h>
 #include <linux/user.h>
 #include <linux/signal.h>
+#include <linux/uaccess.h>
 
-#include <asm/uaccess.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -122,7 +122,7 @@ static inline long get_reg(struct task_struct *task, int regno)
 static inline int
 put_reg(struct task_struct *task, int regno, unsigned long data)
 {
-        char * reg_ptr;
+        char *reg_ptr;
 
         struct pt_regs *regs =
             (struct pt_regs *)((unsigned long)task_stack_page(task) +
@@ -146,7 +146,7 @@ put_reg(struct task_struct *task, int regno, unsigned long data)
                 break;
         default:
                 if (regno <= 216)
-                        *(long *)(reg_ptr + regno) = data;
+                        *(long *)(reg_ptr + regno) = data;
         }
         return 0;
 }
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 83060f98d15d..f59dcee7bae3 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -42,6 +42,7 @@
 #include <asm/cacheflush.h>
 #include <asm/blackfin.h>
 #include <asm/cplbinit.h>
+#include <asm/fixed_code.h>
 
 u16 _bfin_swrst;
 
@@ -63,10 +64,6 @@ EXPORT_SYMBOL(mtd_size);
 
 char __initdata command_line[COMMAND_LINE_SIZE];
 
-#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
-static void generate_cpl_tables(void);
-#endif
-
 void __init bf53x_cache_init(void)
 {
 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
@@ -197,6 +194,17 @@ void __init setup_arch(char **cmdline_p)
         /* this give a chance to get printk() working before crash. */
 #endif
 
+        printk(KERN_INFO "Hardware Trace ");
+        if (bfin_read_TBUFCTL() & 0x1 )
+                printk("Active ");
+        else
+                printk("Off ");
+        if (bfin_read_TBUFCTL() & 0x2)
+                printk("and Enabled\n");
+        else
+        printk("and Disabled\n");
+
+
 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
         /* we need to initialize the Flashrom device here since we might
          * do things with flash early on in the boot
@@ -354,15 +362,15 @@ void __init setup_arch(char **cmdline_p)
                , _stext, _etext,
                __start_rodata, __end_rodata,
                _sdata, _edata,
-               (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
+               (void *)&init_thread_union, (void *)((int)(&init_thread_union) + 0x2000),
                __init_begin, __init_end,
                __bss_start, __bss_stop,
-               (void*)_ramstart, (void*)memory_end
+               (void *)_ramstart, (void *)memory_end
 #ifdef CONFIG_MTD_UCLINUX
-               , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
+               , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
 #endif
 #if DMA_UNCACHED_REGION > 0
-               , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
+               , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
 #endif
                );
 
@@ -388,11 +396,11 @@ void __init setup_arch(char **cmdline_p)
         /* check the size of the l1 area */
         l1_length = _etext_l1 - _stext_l1;
         if (l1_length > L1_CODE_LENGTH)
-                panic("L1 memory overflow\n");
+                panic("L1 code memory overflow\n");
 
         l1_length = _ebss_l1 - _sdata_l1;
         if (l1_length > L1_DATA_A_LENGTH)
-                panic("L1 memory overflow\n");
+                panic("L1 data memory overflow\n");
 
 #ifdef BF561_FAMILY
         _bfin_swrst = bfin_read_SICA_SWRST();
@@ -400,10 +408,28 @@ void __init setup_arch(char **cmdline_p)
         _bfin_swrst = bfin_read_SWRST();
 #endif
 
-        bf53x_cache_init();
+        /* Copy atomic sequences to their fixed location, and sanity check that
+           these locations are the ones that we advertise to userspace.  */
+        memcpy((void *)FIXED_CODE_START, &fixed_code_start,
+               FIXED_CODE_END - FIXED_CODE_START);
+        BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
+               != SIGRETURN_STUB - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
+               != ATOMIC_XCHG32 - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
+               != ATOMIC_CAS32 - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
+               != ATOMIC_ADD32 - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
+               != ATOMIC_SUB32 - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
+               != ATOMIC_IOR32 - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
+               != ATOMIC_AND32 - FIXED_CODE_START);
+        BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
+               != ATOMIC_XOR32 - FIXED_CODE_START);
 
-        printk(KERN_INFO "Hardware Trace Enabled\n");
-        bfin_write_TBUFCTL(0x03);
+        bf53x_cache_init();
 }
 
 static int __init topology_init(void)
@@ -421,286 +447,6 @@ static int __init topology_init(void)
 
 subsys_initcall(topology_init);
 
-#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
-static u16 __init lock_kernel_check(u32 start, u32 end)
-{
-        if ((start <= (u32) _stext && end >= (u32) _end)
-            || (start >= (u32) _stext && end <= (u32) _end))
-                return IN_KERNEL;
-        return 0;
-}
-
-static unsigned short __init
-fill_cplbtab(struct cplb_tab *table,
-             unsigned long start, unsigned long end,
-             unsigned long block_size, unsigned long cplb_data)
-{
-        int i;
-
-        switch (block_size) {
-        case SIZE_4M:
-                i = 3;
-                break;
-        case SIZE_1M:
-                i = 2;
-                break;
-        case SIZE_4K:
-                i = 1;
-                break;
-        case SIZE_1K:
-        default:
-                i = 0;
-                break;
-        }
-
-        cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
-
-        while ((start < end) && (table->pos < table->size)) {
-
-                table->tab[table->pos++] = start;
-
-                if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
-                        table->tab[table->pos++] =
-                            cplb_data | CPLB_LOCK | CPLB_DIRTY;
-                else
-                        table->tab[table->pos++] = cplb_data;
-
-                start += block_size;
-        }
-        return 0;
-}
-
-static unsigned short __init
-close_cplbtab(struct cplb_tab *table)
-{
-
-        while (table->pos < table->size) {
-
-                table->tab[table->pos++] = 0;
-                table->tab[table->pos++] = 0; /* !CPLB_VALID */
-        }
-        return 0;
-}
-
-/* helper function */
-static void __fill_code_cplbtab(struct cplb_tab *t, int i,
-                                u32 a_start, u32 a_end)
-{
-        if (cplb_data[i].psize) {
-                fill_cplbtab(t,
-                                cplb_data[i].start,
-                                cplb_data[i].end,
-                                cplb_data[i].psize,
-                                cplb_data[i].i_conf);
-        } else {
-#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
-                if (i == SDRAM_KERN) {
-                        fill_cplbtab(t,
-                                        cplb_data[i].start,
-                                        cplb_data[i].end,
-                                        SIZE_4M,
-                                        cplb_data[i].i_conf);
-                } else {
-#endif
-                        fill_cplbtab(t,
-                                        cplb_data[i].start,
-                                        a_start,
-                                        SIZE_1M,
-                                        cplb_data[i].i_conf);
-                        fill_cplbtab(t,
-                                        a_start,
-                                        a_end,
-                                        SIZE_4M,
-                                        cplb_data[i].i_conf);
-                        fill_cplbtab(t, a_end,
-                                        cplb_data[i].end,
-                                        SIZE_1M,
-                                        cplb_data[i].i_conf);
-                }
-        }
-}
-
-static void __fill_data_cplbtab(struct cplb_tab *t, int i,
-                                u32 a_start, u32 a_end)
-{
-        if (cplb_data[i].psize) {
-                fill_cplbtab(t,
-                                cplb_data[i].start,
-                                cplb_data[i].end,
-                                cplb_data[i].psize,
-                                cplb_data[i].d_conf);
-        } else {
-                fill_cplbtab(t,
-                                cplb_data[i].start,
-                                a_start, SIZE_1M,
-                                cplb_data[i].d_conf);
-                fill_cplbtab(t, a_start,
-                                a_end, SIZE_4M,
-                                cplb_data[i].d_conf);
-                fill_cplbtab(t, a_end,
-                                cplb_data[i].end,
-                                SIZE_1M,
-                                cplb_data[i].d_conf);
-        }
-}
-static void __init generate_cpl_tables(void)
-{
-
-        u16 i, j, process;
-        u32 a_start, a_end, as, ae, as_1m;
-
-        struct cplb_tab *t_i = NULL;
-        struct cplb_tab *t_d = NULL;
-        struct s_cplb cplb;
-
-        cplb.init_i.size = MAX_CPLBS;
-        cplb.init_d.size = MAX_CPLBS;
-        cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
-        cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
-
-        cplb.init_i.pos = 0;
-        cplb.init_d.pos = 0;
-        cplb.switch_i.pos = 0;
-        cplb.switch_d.pos = 0;
-
-        cplb.init_i.tab = icplb_table;
-        cplb.init_d.tab = dcplb_table;
-        cplb.switch_i.tab = ipdt_table;
-        cplb.switch_d.tab = dpdt_table;
-
-        cplb_data[SDRAM_KERN].end = memory_end;
-
-#ifdef CONFIG_MTD_UCLINUX
-        cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
-        cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
-        cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
-# if defined(CONFIG_ROMFS_FS)
-        cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
-
-        /*
-         * The ROMFS_FS size is often not multiple of 1MB.
-         * This can cause multiple CPLB sets covering the same memory area.
-         * This will then cause multiple CPLB hit exceptions.
-         * Workaround: We ensure a contiguous memory area by extending the kernel
-         * memory section over the mtd section.
-         * For ROMFS_FS memory must be covered with ICPLBs anyways.
-         * So there is no difference between kernel and mtd memory setup.
-         */
-
-        cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
-        cplb_data[SDRAM_RAM_MTD].valid = 0;
-
-# endif
-#else
-        cplb_data[SDRAM_RAM_MTD].valid = 0;
-#endif
-
-        cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
-        cplb_data[SDRAM_DMAZ].end = _ramend;
-
-        cplb_data[RES_MEM].start = _ramend;
-        cplb_data[RES_MEM].end = physical_mem_end;
-
-        if (reserved_mem_dcache_on)
-                cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
-        else
-                cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
-
-        if (reserved_mem_icache_on)
-                cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
-        else
-                cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
-
-        for (i = ZERO_P; i <= L2_MEM; i++) {
-                if (!cplb_data[i].valid)
-                        continue;
-
-                as_1m = cplb_data[i].start % SIZE_1M;
-
-                /*
-                 * We need to make sure all sections are properly 1M aligned
-                 * However between Kernel Memory and the Kernel mtd section,
-                 * depending on the rootfs size, there can be overlapping
-                 * memory areas.
-                 */
-
-                if (as_1m && i != L1I_MEM && i != L1D_MEM) {
-#ifdef CONFIG_MTD_UCLINUX
-                        if (i == SDRAM_RAM_MTD) {
-                                if ((cplb_data[SDRAM_KERN].end + 1) >
-                                                cplb_data[SDRAM_RAM_MTD].start)
-                                        cplb_data[SDRAM_RAM_MTD].start =
-                                                (cplb_data[i].start &
-                                                 (-2*SIZE_1M)) + SIZE_1M;
-                                else
-                                        cplb_data[SDRAM_RAM_MTD].start =
-                                                (cplb_data[i].start &
-                                                 (-2*SIZE_1M));
-                        } else
-#endif
-                                printk(KERN_WARNING
-                                        "Unaligned Start of %s at 0x%X\n",
-                                        cplb_data[i].name, cplb_data[i].start);
-                }
-
-                as = cplb_data[i].start % SIZE_4M;
-                ae = cplb_data[i].end % SIZE_4M;
-
-                if (as)
-                        a_start = cplb_data[i].start + (SIZE_4M - (as));
-                else
-                        a_start = cplb_data[i].start;
-
-                a_end = cplb_data[i].end - ae;
-
-                for (j = INITIAL_T; j <= SWITCH_T; j++) {
-
-                        switch (j) {
-                        case INITIAL_T:
-                                if (cplb_data[i].attr & INITIAL_T) {
-                                        t_i = &cplb.init_i;
-                                        t_d = &cplb.init_d;
-                                        process = 1;
-                                } else
-                                        process = 0;
-                                break;
-                        case SWITCH_T:
-                                if (cplb_data[i].attr & SWITCH_T) {
-                                        t_i = &cplb.switch_i;
-                                        t_d = &cplb.switch_d;
-                                        process = 1;
-                                } else
-                                        process = 0;
-                                break;
-                        default:
-                                        process = 0;
-                                break;
-                        }
-
-                        if (!process)
-                                continue;
-                        if (cplb_data[i].attr & I_CPLB)
-                                __fill_code_cplbtab(t_i, i, a_start, a_end);
-
-                        if (cplb_data[i].attr & D_CPLB)
-                                __fill_data_cplbtab(t_d, i, a_start, a_end);
-                }
-        }
-
-/* close tables */
-
-        close_cplbtab(&cplb.init_i);
-        close_cplbtab(&cplb.init_d);
-
-        cplb.init_i.tab[cplb.init_i.pos] = -1;
-        cplb.init_d.tab[cplb.init_d.pos] = -1;
-        cplb.switch_i.tab[cplb.switch_i.pos] = -1;
-        cplb.switch_d.tab[cplb.switch_d.pos] = -1;
-
-}
-
-#endif
-
 static u_long get_vco(void)
 {
         u_long msel;
@@ -730,7 +476,6 @@ u_long get_cclk(void)
                 return get_vco() / ssel;
         return get_vco() >> csel;
 }
-
 EXPORT_SYMBOL(get_cclk);
 
 /* Get the System clock */
@@ -749,7 +494,6 @@ u_long get_sclk(void)
 
         return get_vco() / ssel;
 }
-
 EXPORT_SYMBOL(get_sclk);
 
 /*
@@ -804,23 +548,23 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 seq_printf(m, "D-CACHE:\tOFF\n");
 
 
-        switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
-                case ACACHE_BSRAM:
-                        seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
-                        dcache_size = 16;
-                        dsup_banks = 1;
-                        break;
-                case ACACHE_BCACHE:
-                        seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
-                        dcache_size = 32;
-                        dsup_banks = 2;
-                        break;
-                case ASRAM_BSRAM:
-                        seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
-                        dcache_size = 0;
-                        dsup_banks = 0;
-                        break;
-                default:
+        switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
+        case ACACHE_BSRAM:
+                seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
+                dcache_size = 16;
+                dsup_banks = 1;
+                break;
+        case ACACHE_BCACHE:
+                seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
+                dcache_size = 32;
+                dsup_banks = 2;
+                break;
+        case ASRAM_BSRAM:
+                seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
+                dcache_size = 0;
+                dsup_banks = 0;
+                break;
+        default:
                 break;
         }
 
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
index 316e65c3439d..5564c9588aa8 100644
--- a/arch/blackfin/kernel/signal.c
+++ b/arch/blackfin/kernel/signal.c
@@ -34,8 +34,8 @@
 #include <linux/personality.h>
 #include <linux/binfmts.h>
 #include <linux/freezer.h>
+#include <linux/uaccess.h>
 
-#include <asm/uaccess.h>
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
 
@@ -124,7 +124,7 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused)
 
         return r0;
 
-      badframe:
+ badframe:
         force_sig(SIGSEGV, current);
         return 0;
 }
@@ -239,7 +239,7 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t * info,
 
         return 0;
 
-      give_sigsegv:
+ give_sigsegv:
         if (sig == SIGSEGV)
                 ka->sa.sa_handler = SIG_DFL;
         force_sig(SIGSEGV, current);
@@ -263,7 +263,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
                 }
                 /* fallthrough */
         case -ERESTARTNOINTR:
-              do_restart:
+ do_restart:
                 regs->p0 = regs->orig_p0;
                 regs->r0 = regs->orig_r0;
                 regs->pc -= 2;
@@ -341,7 +341,7 @@ asmlinkage void do_signal(struct pt_regs *regs)
                 return;
         }
 
-no_signal:
+ no_signal:
         /* Did we come from a system call? */
         if (regs->orig_p0 >= 0)
                 /* Restart the system call - no handlers present */
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index f436e6743f5a..f5e1ae3d1705 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -37,12 +37,12 @@
 #include <linux/syscalls.h>
 #include <linux/mman.h>
 #include <linux/file.h>
+#include <linux/uaccess.h>
+#include <linux/ipc.h>
+#include <linux/unistd.h>
 
 #include <asm/cacheflush.h>
-#include <asm/uaccess.h>
-#include <asm/ipc.h>
 #include <asm/dma.h>
-#include <asm/unistd.h>
 
 /*
  * sys_pipe() is the normal C calling standard for creating
@@ -83,7 +83,7 @@ do_mmap2(unsigned long addr, unsigned long len,
 
         if (file)
                 fput(file);
-      out:
+ out:
         return error;
 }
 
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index f578176b6d92..beef057bd1dc 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -87,7 +87,7 @@ void __init init_leds(void)
 static inline void do_leds(void)
 {
         static unsigned int count = 50;
-        static int flag = 0;
+        static int flag;
         unsigned short tmp = 0;
 
         if (--count == 0) {
@@ -200,7 +200,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text));
 irqreturn_t timer_interrupt(int irq, void *dummy)
 {
         /* last time the cmos clock got updated */
-        static long last_rtc_update = 0;
+        static long last_rtc_update;
 
         write_seqlock(&xtime_lock);
 
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 56058b0b6d4a..3909f5b35536 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -27,15 +27,15 @@
  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/kallsyms.h>
 #include <asm/traps.h>
 #include <asm/cacheflush.h>
 #include <asm/blackfin.h>
-#include <asm/uaccess.h>
 #include <asm/irq_handler.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
+#include <asm/trace.h>
 
 #ifdef CONFIG_KGDB
 # include <linux/debugger.h>
@@ -76,7 +76,7 @@ static int printk_address(unsigned long address)
                 if (!modname)
                         modname = delim = "";
                 return printk("<0x%p> { %s%s%s%s + 0x%lx }",
-                              (void*)address, delim, modname, delim, symname,
+                              (void *)address, delim, modname, delim, symname,
                               (unsigned long)offset);
 
         }
@@ -119,7 +119,7 @@ static int printk_address(unsigned long address)
 
                                 write_unlock_irq(&tasklist_lock);
                                 return printk("<0x%p> [ %s + 0x%lx ]",
-                                              (void*)address, name, offset);
+                                              (void *)address, name, offset);
                         }
 
                         vml = vml->next;
@@ -128,19 +128,9 @@ static int printk_address(unsigned long address)
         write_unlock_irq(&tasklist_lock);
 
         /* we were unable to find this address anywhere */
-        return printk("[<0x%p>]", (void*)address);
+        return printk("[<0x%p>]", (void *)address);
 }
 
-#define trace_buffer_save(x) \
-        do { \
-                (x) = bfin_read_TBUFCTL(); \
-                bfin_write_TBUFCTL((x) & ~TBUFEN); \
-        } while (0)
-#define trace_buffer_restore(x) \
-        do { \
-                bfin_write_TBUFCTL((x));        \
-        } while (0)
-
 asmlinkage void trap_c(struct pt_regs *fp)
 {
         int j, sig = 0;
@@ -203,15 +193,14 @@ asmlinkage void trap_c(struct pt_regs *fp)
 #else
         /* 0x02 - User Defined, Caught by default */
 #endif
-        /* 0x03  - Atomic test and set */
+        /* 0x03 - User Defined, userspace stack overflow */
         case VEC_EXCPT03:
                 info.si_code = SEGV_STACKFLOW;
                 sig = SIGSEGV;
                 printk(KERN_EMERG EXC_0x03);
                 CHK_DEBUGGER_TRAP();
                 break;
-        /* 0x04 - spinlock - handled by _ex_spinlock,
-                getting here is an error */
+        /* 0x04 - User Defined, Caught by default */
         /* 0x05 - User Defined, Caught by default */
         /* 0x06 - User Defined, Caught by default */
         /* 0x07 - User Defined, Caught by default */
@@ -547,29 +536,28 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
                 printk(KERN_EMERG "TEXT = 0x%p-0x%p  DATA = 0x%p-0x%p\n"
                        KERN_EMERG "BSS = 0x%p-0x%p   USER-STACK = 0x%p\n"
                        KERN_EMERG "\n",
-                       (void*)current->mm->start_code,
-                       (void*)current->mm->end_code,
-                       (void*)current->mm->start_data,
-                       (void*)current->mm->end_data,
-                       (void*)current->mm->end_data,
-                       (void*)current->mm->brk,
-                       (void*)current->mm->start_stack);
+                       (void *)current->mm->start_code,
+                       (void *)current->mm->end_code,
+                       (void *)current->mm->start_data,
+                       (void *)current->mm->end_data,
+                       (void *)current->mm->end_data,
+                       (void *)current->mm->brk,
+                       (void *)current->mm->start_stack);
         }
 
         printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr);
-        if (retaddr != 0 && retaddr <= (void*)physical_mem_end
+        if (retaddr != 0 && retaddr <= (void *)physical_mem_end
 #if L1_CODE_LENGTH != 0
             /* FIXME: Copy the code out of L1 Instruction SRAM through dma
                memcpy.  */
-            && !(retaddr >= (void*)L1_CODE_START
-                 && retaddr < (void*)(L1_CODE_START + L1_CODE_LENGTH))
+            && !(retaddr >= (void *)L1_CODE_START
+                 && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
 #endif
         ) {
                 int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
                 unsigned short x = 0;
-                for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ;
-                        i += 2) {
-                        if ( !(i & 0xF) )
+                for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) {
+                        if (!(i & 0xF))
                                 printk(KERN_EMERG "\n" KERN_EMERG
                                         "0x%08x: ", i);
 
@@ -588,7 +576,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
                                         " The rest of this error"
                                         " is meanless\n");
 #endif
-                        if ( i == (unsigned int)retaddr )
+                        if (i == (unsigned int)retaddr)
                                 printk("[%04x]", x);
                         else
                                 printk(" %04x ", x);
@@ -681,8 +669,8 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
                 break;
         }
 
-        printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void*)bfin_read_DCPLB_FAULT_ADDR());
-        printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void*)bfin_read_ICPLB_FAULT_ADDR());
+        printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR());
+        printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR());
         dump_bfin_regs(fp, (void *)fp->retx);
         dump_stack();
         panic("Unrecoverable event\n");
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 1ef1e36b3957..d06f860f4790 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -31,6 +31,7 @@
 
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/mem_map.h>
+#include <asm/page.h>
 
 OUTPUT_FORMAT("elf32-bfin")
 ENTRY(__start)
@@ -63,8 +64,8 @@ SECTIONS
 
         .data :
         {
+                . = ALIGN(PAGE_SIZE);
                 __sdata = .;
-                . = ALIGN(0x2000);
                 *(.data.init_task)
                 DATA_DATA
                 CONSTRUCTORS
@@ -72,14 +73,14 @@ SECTIONS
                 . = ALIGN(32);
                 *(.data.cacheline_aligned)
 
-                . = ALIGN(0x2000);
+                . = ALIGN(PAGE_SIZE);
                 __edata = .;
         }
 
+        . = ALIGN(PAGE_SIZE);
         ___init_begin = .;
         .init :
         {
-                . = ALIGN(4096);
                 __sinittext = .;
                 *(.init.text)
                 __einittext = .;
@@ -152,9 +153,10 @@ SECTIONS
                 __ebss_b_l1 = .;
         }
 
-        ___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
+        . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
+        ___init_end = ALIGN(PAGE_SIZE);
 
-        .bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) :
+        .bss ___init_end :
         {
                 . = ALIGN(4);
                 ___bss_start = .;
diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c
index 2ad47c4254ba..4eeefd86907f 100644
--- a/arch/blackfin/lib/strcmp.c
+++ b/arch/blackfin/lib/strcmp.c
@@ -6,6 +6,5 @@
 
 int strcmp(const char *dest, const char *src)
 {
-                return __inline_strcmp(dest, src);
+        return __inline_strcmp(dest, src);
 }
-
diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c
index 4dc835a8a19b..534589db7256 100644
--- a/arch/blackfin/lib/strcpy.c
+++ b/arch/blackfin/lib/strcpy.c
@@ -6,6 +6,5 @@
 
 char *strcpy(char *dest, const char *src)
 {
-                return __inline_strcpy(dest, src);
+        return __inline_strcpy(dest, src);
 }
-
diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c
index 947bcfe3f3bb..d791f120bff7 100644
--- a/arch/blackfin/lib/strncmp.c
+++ b/arch/blackfin/lib/strncmp.c
@@ -6,6 +6,5 @@
 
 int strncmp(const char *cs, const char *ct, size_t count)
 {
-                return __inline_strncmp(cs, ct, count);
+        return __inline_strncmp(cs, ct, count);
 }
-
diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c
index 77a9b2e95097..1fecb5c71ffb 100644
--- a/arch/blackfin/lib/strncpy.c
+++ b/arch/blackfin/lib/strncpy.c
@@ -6,6 +6,5 @@
 
 char *strncpy(char *dest, const char *src, size_t n)
 {
-                return __inline_strncpy(dest, src, n);
+        return __inline_strncpy(dest, src, n);
 }
-
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
index 76d2c2b8579a..8cce1736360d 100644
--- a/arch/blackfin/mach-bf533/Makefile
+++ b/arch/blackfin/mach-bf533/Makefile
@@ -4,6 +4,6 @@
 
 extra-y := head.o
 
-obj-y := ints-priority.o
+obj-y := ints-priority.o dma.o
 
-obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o
+obj-$(CONFIG_CPU_FREQ)   += cpu.o
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index edd31ce4f8d2..4545f363e641 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -34,7 +34,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/bfin5xx_spi.h>
 
 /*
@@ -51,11 +51,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -98,7 +98,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .platform_data = &bfin_spi_flash_data,
                 .controller_data = &spi_flash_chip_info,
                 .mode = SPI_MODE_3,
-        },{
+        }, {
                 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                 .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 1,               /* Framework bus number */
@@ -145,7 +145,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20200300,
                 .end = 0x20200300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF0,
                 .end = IRQ_PF0,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -194,11 +194,11 @@ static struct resource isp1362_hcd_resources[] = {
                 .start = 0x20308000,
                 .end = 0x20308000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20308004,
                 .end = 0x20308004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF4,
                 .end = IRQ_PF4,
                 .flags = IORESOURCE_IRQ,
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 0b522d95160d..0000b8f1239c 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -35,7 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/bfin5xx_spi.h>
 
 /*
@@ -61,7 +61,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20310300,
                 .end = 0x20310300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF9,
                 .end = IRQ_PF9,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -85,11 +85,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
index c0f43ccfbfb5..9bc1f0d0ab50 100644
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ b/arch/blackfin/mach-bf533/boards/generic_board.c
@@ -30,7 +30,7 @@
 
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -53,11 +53,11 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20300300,
                 .end = 0x20300300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PROG_INTB,
                 .end = IRQ_PROG_INTB,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },{
+        }, {
                 /*
                  *  denotes the flag pin and is used directly if
                  *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 9a472fe15833..a9143c4cbdcd 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -37,7 +37,7 @@
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb_isp1362.h>
 #endif
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/bfin5xx_spi.h>
 
 /*
@@ -62,7 +62,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20300300,
                 .end = 0x20300300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -83,7 +83,7 @@ static struct resource net2272_bfin_resources[] = {
                 .start = 0x20300000,
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF10,
                 .end = IRQ_PF10,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -108,11 +108,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -229,19 +229,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 
 #if defined(CONFIG_PBX)
         {
-                .modalias       = "fxs-spi",
-                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num        = 1,
-                .chip_select    = 3,
-                .controller_data= &spi_si3xxx_chip_info,
+                .modalias = "fxs-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 1,
+                .chip_select = 3,
+                .controller_data = &spi_si3xxx_chip_info,
                 .mode = SPI_MODE_3,
         },
         {
-                .modalias       = "fxo-spi",
-                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num        = 1,
-                .chip_select    = 2,
-                .controller_data= &spi_si3xxx_chip_info,
+                .modalias = "fxo-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 1,
+                .chip_select = 2,
+                .controller_data = &spi_si3xxx_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
diff --git a/arch/blackfin/mach-bf533/cpu.c b/arch/blackfin/mach-bf533/cpu.c
index 99547c4c290e..6fd9cfd0a31b 100644
--- a/arch/blackfin/mach-bf533/cpu.c
+++ b/arch/blackfin/mach-bf533/cpu.c
@@ -79,8 +79,7 @@ static int bf533_target(struct cpufreq_policy *policy,
         int i;
 
         struct cpufreq_freqs freqs;
-        if (cpufreq_frequency_table_target
-            (policy, bf533_freq_table, target_freq, relation, &index))
+        if (cpufreq_frequency_table_target(policy, bf533_freq_table, target_freq, relation, &index))
                 return -EINVAL;
         cclk_mhz = bf533_freq_table[index].frequency;
         vco_mhz = bf533_freq_table[index].index;
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
new file mode 100644
index 000000000000..6c909cf4f7bf
--- /dev/null
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -0,0 +1,95 @@
+/*
+ * File:         arch/blackfin/mach-bf533/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+        (struct dma_register *) DMA0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA7_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+
+        switch (channel) {
+        case CH_PPI:
+                ret_irq = IRQ_PPI;
+                break;
+
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+                break;
+
+        case CH_SPI:
+                ret_irq = IRQ_SPI;
+                break;
+
+        case CH_UART_RX:
+                ret_irq = IRQ_UART_RX;
+                break;
+
+        case CH_UART_TX:
+                ret_irq = IRQ_UART_TX;
+                break;
+
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MEM_DMA0;
+                break;
+
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MEM_DMA1;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7e2aa8d0f44f..7dd0e9c3a936 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -30,6 +30,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/blackfin.h>
+#include <asm/trace.h>
 #if CONFIG_BFIN_KERNEL_CLOCK
 #include <asm/mach/mem_init.h>
 #endif
@@ -96,6 +97,10 @@ ENTRY(__start)
         M2 = r0;
         M3 = r0;
 
+        trace_buffer_start(p0,r0);
+        P0 = R1;
+        R0 = R1;
+
 #if CONFIG_DEBUG_KERNEL_START
 
 /*
diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c
index a3e1789167be..7d79e0f9503d 100644
--- a/arch/blackfin/mach-bf533/ints-priority.c
+++ b/arch/blackfin/mach-bf533/ints-priority.c
@@ -28,8 +28,8 @@
  */
 
 #include <linux/module.h>
+#include <linux/irq.h>
 #include <asm/blackfin.h>
-#include <asm/irq.h>
 
 void program_IAR(void)
 {
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
index f32d44215bb7..7e7c9c8ac5b2 100644
--- a/arch/blackfin/mach-bf537/Makefile
+++ b/arch/blackfin/mach-bf537/Makefile
@@ -4,6 +4,6 @@
 
 extra-y := head.o
 
-obj-y := ints-priority.o
+obj-y := ints-priority.o dma.o
 
 obj-$(CONFIG_CPU_FREQ)   += cpu.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 6a60618a78ec..a8f947b72754 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -35,7 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/bfin5xx_spi.h>
 
 /*
@@ -53,11 +53,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -202,7 +202,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20200300,
                 .end = 0x20200300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF14,
                 .end = IRQ_PF14,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -223,11 +223,11 @@ static struct resource isp1362_hcd_resources[] = {
                 .start = 0x20308000,
                 .end = 0x20308000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20308004,
                 .end = 0x20308004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PG15,
                 .end = IRQ_PG15,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -262,7 +262,7 @@ static struct resource net2272_bfin_resources[] = {
                 .start = 0x20200000,
                 .end = 0x20200000 + 0x100,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -283,7 +283,7 @@ static struct resource bfin_uart_resources[] = {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/eth_mac.c b/arch/blackfin/mach-bf537/boards/eth_mac.c
index e129a08d63de..a725cc8a9290 100644
--- a/arch/blackfin/mach-bf537/boards/eth_mac.c
+++ b/arch/blackfin/mach-bf537/boards/eth_mac.c
@@ -20,8 +20,7 @@
 #include <linux/module.h>
 #include <asm/blackfin.h>
 
-#if     defined(CONFIG_GENERIC_BOARD) \
-        || defined(CONFIG_BFIN537_STAMP)
+#if     defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
 
 /*
  * Currently the MAC address is saved in Flash by U-Boot
@@ -43,7 +42,7 @@ void get_bf537_ether_addr(char *addr)
  */
 void get_bf537_ether_addr(char *addr)
 {
-        printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n",__FILE__);
+        printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__);
 }
 
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index fd57e7439e0f..648d984e98d6 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -35,9 +35,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
-#include <asm/irq.h>
-#include <asm/bfin5xx_spi.h>
+#include <linux/irq.h>
 #include <linux/usb_sl811.h>
+#include <asm/bfin5xx_spi.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -54,19 +54,19 @@ static struct resource bfin_pcmcia_cf_resources[] = {
                 .start = 0x20310000, /* IO PORT */
                 .end = 0x20312000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20311000, /* Attribute Memory */
                 .end = 0x20311FFF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PROG_INTA,
                 .end = IRQ_PROG_INTA,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },{
+        }, {
                 .start = IRQ_PF4,
                 .end = IRQ_PF4,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },{
+        }, {
                 .start = 6, /* Card Detect PF6 */
                 .end = 6,
                 .flags = IORESOURCE_IRQ,
@@ -95,11 +95,11 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20300300,
                 .end = 0x20300300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PROG_INTB,
                 .end = IRQ_PROG_INTB,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },{
+        }, {
                 /*
                  *  denotes the flag pin and is used directly if
                  *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
@@ -123,15 +123,15 @@ static struct resource sl811_hcd_resources[] = {
                 .start = 0x20340000,
                 .end = 0x20340000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20340004,
                 .end = 0x20340004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PROG_INTA,
                 .end = IRQ_PROG_INTA,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },{
+        }, {
                 .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
                 .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -179,15 +179,15 @@ static struct resource isp1362_hcd_resources[] = {
                 .start = 0x20360000,
                 .end = 0x20360000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20360004,
                 .end = 0x20360004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PROG_INTA,
                 .end = IRQ_PROG_INTA,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },{
+        }, {
                 .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
                 .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
                 .flags = IORESOURCE_IRQ,
@@ -228,7 +228,7 @@ static struct resource net2272_bfin_resources[] = {
                 .start = 0x20300000,
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -253,11 +253,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -375,7 +375,7 @@ static struct resource bfin_uart_resources[] = {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 8aaf76dfce80..8806f1230f2d 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -37,7 +37,7 @@
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb_isp1362.h>
 #endif
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/bfin5xx_spi.h>
 #include <linux/usb_sl811.h>
 
@@ -58,15 +58,15 @@ static struct resource bfin_pcmcia_cf_resources[] = {
                 .start = 0x20310000, /* IO PORT */
                 .end = 0x20312000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20311000, /* Attribute Memory */
                 .end = 0x20311FFF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF4,
                 .end = IRQ_PF4,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },{
+        }, {
                 .start = 6, /* Card Detect PF6 */
                 .end = 6,
                 .flags = IORESOURCE_IRQ,
@@ -95,7 +95,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20300300,
                 .end = 0x20300300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
 
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
@@ -116,11 +116,11 @@ static struct resource sl811_hcd_resources[] = {
                 .start = 0x20340000,
                 .end = 0x20340000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20340004,
                 .end = 0x20340004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = CONFIG_USB_SL811_BFIN_IRQ,
                 .end = CONFIG_USB_SL811_BFIN_IRQ,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -167,11 +167,11 @@ static struct resource isp1362_hcd_resources[] = {
                 .start = 0x20360000,
                 .end = 0x20360000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20360004,
                 .end = 0x20360004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
                 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -212,7 +212,7 @@ static struct resource net2272_bfin_resources[] = {
                 .start = 0x20300000,
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -238,11 +238,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -294,16 +294,6 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_PBX)
-static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
-        .ctl_reg        = 0x4, /* send zero */
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-        .cs_change_per_word = 1,
-};
-#endif
-
-
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
         .cs_change_per_word = 1,
@@ -392,24 +382,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .mode = SPI_MODE_3,
         },
 #endif
-#if defined(CONFIG_PBX)
-        {
-                .modalias       = "fxs-spi",
-                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num        = 1,
-                .chip_select    = 3,
-                .controller_data= &spi_si3xxx_chip_info,
-                .mode = SPI_MODE_3,
-        },
-        {
-                .modalias       = "fxo-spi",
-                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num        = 1,
-                .chip_select    = 2,
-                .controller_data= &spi_si3xxx_chip_info,
-                .mode = SPI_MODE_3,
-        },
-#endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 {
         .modalias               = "ad7877",
@@ -451,7 +423,7 @@ static struct resource bfin_uart_resources[] = {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3a29b4d15f25..9c43d7756510 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -37,12 +37,10 @@
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb_isp1362.h>
 #endif
-#include <asm/irq.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
-#include <asm/bfin5xx_spi.h>
 #include <linux/usb_sl811.h>
-
+#include <asm/bfin5xx_spi.h>
 #include <linux/spi/ad7877.h>
 
 /*
@@ -85,7 +83,7 @@ static struct platform_device *bfin_isp1761_devices[] = {
 
 int __init bfin_isp1761_init(void)
 {
-        unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices);
+        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
 
         printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
         set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
@@ -107,15 +105,15 @@ static struct resource bfin_pcmcia_cf_resources[] = {
                 .start = 0x20310000, /* IO PORT */
                 .end = 0x20312000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20311000, /* Attribute Memory */
                 .end = 0x20311FFF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF4,
                 .end = IRQ_PF4,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },{
+        }, {
                 .start = 6, /* Card Detect PF6 */
                 .end = 6,
                 .flags = IORESOURCE_IRQ,
@@ -144,7 +142,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x20300300,
                 .end = 0x20300300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
 
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
@@ -159,17 +157,39 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+static struct resource dm9000_resources[] = {
+        [0] = {
+                .start  = 0x203FB800,
+                .end    = 0x203FB800 + 8,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PF9,
+                .end    = IRQ_PF9,
+                .flags  = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
+        },
+};
+
+static struct platform_device dm9000_device = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm9000_resources),
+        .resource       = dm9000_resources,
+};
+#endif
+
 #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
 static struct resource sl811_hcd_resources[] = {
         {
                 .start = 0x20340000,
                 .end = 0x20340000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20340004,
                 .end = 0x20340004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = CONFIG_USB_SL811_BFIN_IRQ,
                 .end = CONFIG_USB_SL811_BFIN_IRQ,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -216,11 +236,11 @@ static struct resource isp1362_hcd_resources[] = {
                 .start = 0x20360000,
                 .end = 0x20360000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x20360004,
                 .end = 0x20360004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
                 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -261,7 +281,7 @@ static struct resource net2272_bfin_resources[] = {
                 .start = 0x20300000,
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -287,11 +307,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -361,7 +381,6 @@ static struct bfin5xx_spi_chip ad5304_chip_info = {
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-//      .cs_change_per_word = 1,
         .enable_dma = 0,
         .bits_per_word = 16,
 };
@@ -449,19 +468,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 #if defined(CONFIG_PBX)
         {
-                .modalias       = "fxs-spi",
-                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num        = 1,
-                .chip_select    = 3,
-                .controller_data= &spi_si3xxx_chip_info,
+                .modalias = "fxs-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 1,
+                .chip_select = 3,
+                .controller_data = &spi_si3xxx_chip_info,
                 .mode = SPI_MODE_3,
         },
         {
-                .modalias       = "fxo-spi",
-                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num        = 1,
-                .chip_select    = 2,
-                .controller_data= &spi_si3xxx_chip_info,
+                .modalias = "fxo-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 1,
+                .chip_select = 2,
+                .controller_data = &spi_si3xxx_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -516,7 +535,7 @@ static struct resource bfin_uart_resources[] = {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
@@ -571,6 +590,10 @@ static struct platform_device *stamp_devices[] __initdata = {
         &smc91x_device,
 #endif
 
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+        &dm9000_device,
+#endif
+
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
         &bfin_mac_device,
 #endif
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
new file mode 100644
index 000000000000..706cb97b0265
--- /dev/null
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -0,0 +1,115 @@
+/*
+ * File:         arch/blackfin/mach-bf537/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+        (struct dma_register *) DMA0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA11_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+
+        switch (channel) {
+        case CH_PPI:
+                ret_irq = IRQ_PPI;
+                break;
+
+        case CH_EMAC_RX:
+                ret_irq = IRQ_MAC_RX;
+                break;
+
+        case CH_EMAC_TX:
+                ret_irq = IRQ_MAC_TX;
+                break;
+
+        case CH_UART1_RX:
+                ret_irq = IRQ_UART1_RX;
+                break;
+
+        case CH_UART1_TX:
+                ret_irq = IRQ_UART1_TX;
+                break;
+
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+                break;
+
+        case CH_SPI:
+                ret_irq = IRQ_SPI;
+                break;
+
+        case CH_UART_RX:
+                ret_irq = IRQ_UART_RX;
+                break;
+
+        case CH_UART_TX:
+                ret_irq = IRQ_UART_TX;
+                break;
+
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MEM_DMA0;
+                break;
+
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MEM_DMA1;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 7d902bbd860f..429c8a1019da 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -30,6 +30,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/blackfin.h>
+#include <asm/trace.h>
+
 #if CONFIG_BFIN_KERNEL_CLOCK
 #include <asm/mach/mem_init.h>
 #endif
@@ -93,6 +95,10 @@ ENTRY(__start)
         M2 = r0;
         M3 = r0;
 
+        trace_buffer_start(p0,r0);
+        P0 = R1;
+        R0 = R1;
+
         /* Turn off the icache */
         p0.l = (IMEM_CONTROL & 0xFFFF);
         p0.h = (IMEM_CONTROL >> 16);
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index 2dbf3df465d1..a8b915f202ec 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -28,8 +28,8 @@
  */
 
 #include <linux/module.h>
+#include <linux/irq.h>
 #include <asm/blackfin.h>
-#include <asm/irq.h>
 
 void program_IAR(void)
 {
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
new file mode 100644
index 000000000000..e78b03d56c7c
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -0,0 +1,316 @@
+if (BF54x)
+
+menu "BF548 Specific Configuration"
+
+comment "Interrupt Priority Assignment"
+menu "Priority"
+
+config IRQ_PLL_WAKEUP
+        int "IRQ_PLL_WAKEUP"
+        default 7
+config IRQ_DMAC0_ERR
+        int "IRQ_DMAC0_ERR"
+        default 7
+config IRQ_EPPI0_ERR
+        int "IRQ_EPPI0_ERR"
+        default 7
+config IRQ_SPORT0_ERR
+        int "IRQ_SPORT0_ERR"
+        default 7
+config IRQ_SPORT1_ERR
+        int "IRQ_SPORT1_ERR"
+        default 7
+config IRQ_SPI0_ERR
+        int "IRQ_SPI0_ERR"
+        default 7
+config IRQ_UART0_ERR
+        int "IRQ_UART0_ERR"
+        default 7
+config IRQ_RTC
+        int "IRQ_RTC"
+        default 8
+config IRQ_EPPI0
+        int "IRQ_EPPI0"
+        default 8
+config IRQ_SPORT0_RX
+        int "IRQ_SPORT0_RX"
+        default 9
+config IRQ_SPORT0_TX
+        int "IRQ_SPORT0_TX"
+        default 9
+config IRQ_SPORT1_RX
+        int "IRQ_SPORT1_RX"
+        default 9
+config IRQ_SPORT1_TX
+        int "IRQ_SPORT1_TX"
+        default 9
+config IRQ_SPI0
+        int "IRQ_SPI0"
+        default 10
+config IRQ_UART0_RX
+        int "IRQ_UART0_RX"
+        default 10
+config IRQ_UART0_TX
+        int "IRQ_UART0_TX"
+        default 10
+config IRQ_TIMER8
+        int "IRQ_TIMER8"
+        default 11
+config IRQ_TIMER9
+        int "IRQ_TIMER9"
+        default 11
+config IRQ_TIMER10
+        int "IRQ_TIMER10"
+        default 11
+config IRQ_PINT0
+        int "IRQ_PINT0"
+        default 12
+config IRQ_PINT1
+        int "IRQ_PINT0"
+        default 12
+config IRQ_MDMAS0
+        int "IRQ_MDMAS0"
+        default 13
+config IRQ_MDMAS1
+        int "IRQ_DMDMAS1"
+        default 13
+config IRQ_WATCHDOG
+        int "IRQ_WATCHDOG"
+        default 13
+config IRQ_DMAC1_ERR
+        int "IRQ_DMAC1_ERR"
+        default 7
+config IRQ_SPORT2_ERR
+        int "IRQ_SPORT2_ERR"
+        default 7
+config IRQ_SPORT3_ERR
+        int "IRQ_SPORT3_ERR"
+        default 7
+config IRQ_MXVR_DATA
+        int "IRQ MXVR Data"
+        default 7
+config IRQ_SPI1_ERR
+        int "IRQ_SPI1_ERR"
+        default 7
+config IRQ_SPI2_ERR
+        int "IRQ_SPI2_ERR"
+        default 7
+config IRQ_UART1_ERR
+        int "IRQ_UART1_ERR"
+        default 7
+config IRQ_UART2_ERR
+        int "IRQ_UART2_ERR"
+        default 7
+config IRQ_CAN0_ERR
+        int "IRQ_CAN0_ERR"
+        default 7
+config IRQ_SPORT2_RX
+        int "IRQ_SPORT2_RX"
+        default 9
+config IRQ_SPORT2_TX
+        int "IRQ_SPORT2_TX"
+        default 9
+config IRQ_SPORT3_RX
+        int "IRQ_SPORT3_RX"
+        default 9
+config IRQ_SPORT3_TX
+        int "IRQ_SPORT3_TX"
+        default 9
+config IRQ_EPPI1
+        int "IRQ_EPPI1"
+        default 9
+config IRQ_EPPI2
+        int "IRQ_EPPI2"
+        default 9
+config IRQ_SPI1
+        int "IRQ_SPI1"
+        default 10
+config IRQ_SPI2
+        int "IRQ_SPI2"
+        default 10
+config IRQ_UART1_RX
+        int "IRQ_UART1_RX"
+        default 10
+config IRQ_UART1_TX
+        int "IRQ_UART1_TX"
+        default 10
+config IRQ_ATAPI_RX
+        int "IRQ_ATAPI_RX"
+        default 10
+config IRQ_ATAPI_TX
+        int "IRQ_ATAPI_TX"
+        default 10
+config IRQ_TWI0
+        int "IRQ_TWI0"
+        default 11
+config IRQ_TWI1
+        int "IRQ_TWI1"
+        default 11
+config IRQ_CAN0_RX
+        int "IRQ_CAN_RX"
+        default 11
+config IRQ_CAN0_TX
+        int "IRQ_CAN_TX"
+        default 11
+config IRQ_MDMAS2
+        int "IRQ_MDMAS2"
+        default 13
+config IRQ_MDMAS3
+        int "IRQ_DMMAS3"
+        default 13
+config IRQ_MXVR_ERR
+        int "IRQ_MXVR_ERR"
+        default 11
+config IRQ_MXVR_MSG
+        int "IRQ_MXVR_MSG"
+        default 11
+config IRQ_MXVR_PKT
+        int "IRQ_MXVR_PKT"
+        default 11
+config IRQ_EPPI1_ERR
+        int "IRQ_EPPI1_ERR"
+        default 7
+config IRQ_EPPI2_ERR
+        int "IRQ_EPPI2_ERR"
+        default 7
+config IRQ_UART3_ERR
+        int "IRQ_UART3_ERR"
+        default 7
+config IRQ_HOST_ERR
+        int "IRQ_HOST_ERR"
+        default 7
+config IRQ_PIXC_ERR
+        int "IRQ_PIXC_ERR"
+        default 7
+config IRQ_NFC_ERR
+        int "IRQ_NFC_ERR"
+        default 7
+config IRQ_ATAPI_ERR
+        int "IRQ_ATAPI_ERR"
+        default 7
+config IRQ_CAN1_ERR
+        int "IRQ_CAN1_ERR"
+        default 7
+config IRQ_HS_DMA_ERR
+        int "IRQ Handshake DMA Status"
+        default 7
+config IRQ_PIXC_IN0
+        int "IRQ PIXC IN0"
+        default 8
+config IRQ_PIXC_IN1
+        int "IRQ PIXC IN1"
+        default 8
+config IRQ_PIXC_OUT
+        int "IRQ PIXC OUT"
+        default 8
+config IRQ_SDH
+        int "IRQ SDH"
+        default 8
+config IRQ_CNT
+        int "IRQ CNT"
+        default 8
+config IRQ_KEY
+        int "IRQ KEY"
+        default 8
+config IRQ_CAN1_RX
+        int "IRQ CAN1 RX"
+        default 11
+config IRQ_CAN1_TX
+        int "IRQ_CAN1_TX"
+        default 11
+config IRQ_SDH_MASK0
+        int "IRQ_SDH_MASK0"
+        default 11
+config IRQ_SDH_MASK1
+        int "IRQ_SDH_MASK1"
+        default 11
+config IRQ_USB_INT0
+        int "IRQ USB INT0"
+        default 11
+config IRQ_USB_INT1
+        int "IRQ USB INT1"
+        default 11
+config IRQ_USB_INT2
+        int "IRQ USB INT2"
+        default 11
+config IRQ_USB_DMA
+        int "IRQ USB DMA"
+        default 11
+config IRQ_OTPSEC
+        int "IRQ OPTSEC"
+        default 11
+config IRQ_TIMER0
+        int "IRQ_TIMER0"
+        default 11
+config IRQ_TIMER1
+        int "IRQ_TIMER1"
+        default 11
+config IRQ_TIMER2
+        int "IRQ_TIMER2"
+        default 11
+config IRQ_TIMER3
+        int "IRQ_TIMER3"
+        default 11
+config IRQ_TIMER4
+        int "IRQ_TIMER4"
+        default 11
+config IRQ_TIMER5
+        int "IRQ_TIMER5"
+        default 11
+config IRQ_TIMER6
+        int "IRQ_TIMER6"
+        default 11
+config IRQ_TIMER7
+        int "IRQ_TIMER7"
+        default 11
+config IRQ_PINT2
+        int "IRQ_PIN2"
+        default 11
+config IRQ_PINT3
+        int "IRQ_PIN3"
+        default 11
+
+        help
+          Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
+          This applies to all the above.  It is not recommended to assign the
+          highest priority number 7 to UART or any other device.
+
+endmenu
+
+comment "Pin Interrupt to Port Assignment"
+menu "Assignment"
+
+config PINTx_REASSIGN
+        bool "Reprogram PINT Assignment"
+        default n
+        help
+          The interrupt assignment registers controls the pin-to-interrupt
+          assignment in a byte-wide manner. Each option allows you to select
+          a set of pins (High/Low Byte) of an specific Port being mapped
+          to one of the four PIN Interrupts IRQ_PINTx.
+
+          You shouldn't change any of these unless you know exactly what you're doing.
+          Please consult the Blackfin BF54x Processor Hardware Reference Manual.
+
+config PINT0_ASSIGN
+        hex "PINT0_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT1_ASSIGN
+        hex "PINT1_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x01010000
+config PINT2_ASSIGN
+        hex "PINT2_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT3_ASSIGN
+        hex "PINT3_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x02020303
+
+endmenu
+
+endmenu
+
+endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
new file mode 100644
index 000000000000..060ad78ebf1d
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -0,0 +1,9 @@
+#
+# arch/blackfin/mach-bf537/Makefile
+#
+
+extra-y := head.o
+
+obj-y := ints-priority.o dma.o gpio.o
+
+obj-$(CONFIG_CPU_FREQ)   += cpu.o
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
new file mode 100644
index 000000000000..486e07c99a51
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/Makefile
@@ -0,0 +1,5 @@
+#
+# arch/blackfin/mach-bf548/boards/Makefile
+#
+
+obj-$(CONFIG_BFIN548_EZKIT)             += ezkit.o led.o
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
new file mode 100644
index 000000000000..96ad95fab1a8
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -0,0 +1,114 @@
+/*
+ * File:         arch/blackfin/mach-bf548/boards/ezkit.c
+ * Based on:     arch/blackfin/mach-bf537/boards/ezkit.c
+ * Author:       Aidan Williams <aidan@nicta.com.au>
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2005 National ICT Australia (NICTA)
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/irq.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/bfin5xx_spi.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+char *bfin_board_name = "ADSP-BF548-EZKIT";
+
+/*
+ *  Driver needs to know address, irq and flag pin.
+ */
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+        .name = "rtc-bfin",
+        .id   = -1,
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+static struct resource bfin_uart_resources[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+                .start = 0xFFC02000,
+                .end = 0xFFC020FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART2
+        {
+                .start = 0xFFC02100,
+                .end = 0xFFC021FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART3
+        {
+                .start = 0xFFC03100,
+                .end = 0xFFC031FF,
+        },
+#endif
+};
+
+static struct platform_device bfin_uart_device = {
+        .name = "bfin-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart_resources),
+        .resource = bfin_uart_resources,
+};
+#endif
+
+static struct platform_device *ezkit_devices[] __initdata = {
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+        &bfin_uart_device,
+#endif
+};
+
+static int __init stamp_init(void)
+{
+        printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
+        platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
+        return 0;
+}
+
+arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf548/boards/led.S b/arch/blackfin/mach-bf548/boards/led.S
new file mode 100644
index 000000000000..f47daf3770d0
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/led.S
@@ -0,0 +1,172 @@
+/****************************************************
+ * LED1 ---- PG6        LED2 ---- PG7               *
+ * LED3 ---- PG8        LED4 ---- PG9               *
+ * LED5 ---- PG10       LED6 ---- PG11              *
+ ****************************************************/
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+
+/* All functions in this file save the registers they uses.
+   So there is no need to save any registers before calling them.  */
+
+        .text;
+
+/* Initialize LEDs.  */
+
+ENTRY(_led_init)
+        LINK 0;
+        [--SP] = P0;
+        [--SP] = R0;
+        [--SP] = R1;
+        [--SP] = R2;
+        R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
+        R2 = ~R1;
+
+        P0.H = hi(PORTG_FER);
+        P0.L = lo(PORTG_FER);
+        R0 = W[P0](Z);
+        SSYNC;
+        R0 = R0 & R2;
+        W[P0] = R0.L;
+        SSYNC;
+
+        P0.H = hi(PORTG_DIR_SET);
+        P0.L = lo(PORTG_DIR_SET);
+        W[P0] = R1.L;
+        SSYNC;
+
+        P0.H = hi(PORTG_INEN);
+        P0.L = lo(PORTG_INEN);
+        R0 = W[P0](Z);
+        SSYNC;
+        R0 = R0 & R2;
+        W[P0] = R0.L;
+        SSYNC;
+
+        R2 = [SP++];
+        R1 = [SP++];
+        R0 = [SP++];
+        P0 = [SP++];
+        RTS;
+        .size   _led_init, .-_led_init
+
+/* Set one LED on. Leave other LEDs unchanged.
+   It expects the LED number passed through R0.  */
+
+ENTRY(_led_on)
+        LINK 0;
+        [--SP] = P0;
+        [--SP] = R1;
+        CALL _led_init;
+        R1 = 1;
+        R0 += 5;
+        R1 <<= R0;
+        P0.H = hi(PORTG_SET);
+        P0.L = lo(PORTG_SET);
+        W[P0] = R1.L;
+        SSYNC;
+        R1 = [SP++];
+        P0 = [SP++];
+        UNLINK;
+        RTS;
+        .size   _led_on, .-_led_on
+
+/* Set one LED off. Leave other LEDs unchanged.  */
+
+ENTRY(_led_off)
+        LINK 0;
+        [--SP] = P0;
+        [--SP] = R1;
+        CALL _led_init;
+        R1 = 1;
+        R0 += 5;
+        R1 <<= R0;
+        P0.H = hi(PORTG_CLEAR);
+        P0.L = lo(PORTG_CLEAR);
+        W[P0] = R1.L;
+        SSYNC;
+        R1 = [SP++];
+        P0 = [SP++];
+        UNLINK;
+        RTS;
+        .size   _led_off, .-_led_off
+
+/* Toggle one LED. Leave other LEDs unchanged.  */
+
+ENTRY(_led_toggle)
+        LINK 0;
+        [--SP] = P0;
+        [--SP] = R1;
+        CALL _led_init;
+        R1 = 1;
+        R0 += 5;
+        R1 <<= R0;
+        P0.H = hi(PORTG);
+        P0.L = lo(PORTG);
+        R0 = W[P0](Z);
+        SSYNC;
+        R0 = R0 ^ R1;
+        W[P0] = R0.L;
+        SSYNC;
+        R1 = [SP++];
+        P0 = [SP++];
+        UNLINK;
+        RTS;
+        .size   _led_toggle, .-_led_toggle
+
+/* Display the number using LEDs in binary format.  */
+
+ENTRY(_led_disp_num)
+        LINK 0;
+        [--SP] = P0;
+        [--SP] = R1;
+        [--SP] = R2;
+        CALL _led_init;
+        R1 = 0x3f(X);
+        R0 = R0 & R1;
+        R2 = 6(X);
+        R0 <<= R2;
+        R1 <<= R2;
+        P0.H = hi(PORTG);
+        P0.L = lo(PORTG);
+        R2 = W[P0](Z);
+        SSYNC;
+        R1 = ~R1;
+        R2 = R2 & R1;
+        R2 = R2 | R0;
+        W[P0] = R2.L;
+        SSYNC;
+        R2 = [SP++];
+        R1 = [SP++];
+        P0 = [SP++];
+        UNLINK;
+        RTS;
+        .size   _led_disp_num, .-_led_disp_num
+
+/* Toggle the number using LEDs in binary format.  */
+
+ENTRY(_led_toggle_num)
+        LINK 0;
+        [--SP] = P0;
+        [--SP] = R1;
+        [--SP] = R2;
+        CALL _led_init;
+        R1 = 0x3f(X);
+        R0 = R0 & R1;
+        R1 = 6(X);
+        R0 <<= R1;
+        P0.H = hi(PORTG);
+        P0.L = lo(PORTG);
+        R1 = W[P0](Z);
+        SSYNC;
+        R1 = R1 ^ R0;
+        W[P0] = R1.L;
+        SSYNC;
+        R2 = [SP++];
+        R1 = [SP++];
+        P0 = [SP++];
+        UNLINK;
+        RTS;
+        .size   _led_toggle_num, .-_led_toggle_num
+
diff --git a/arch/blackfin/mach-bf548/cpu.c b/arch/blackfin/mach-bf548/cpu.c
new file mode 100644
index 000000000000..4298a3ccfbfc
--- /dev/null
+++ b/arch/blackfin/mach-bf548/cpu.c
@@ -0,0 +1,159 @@
+/*
+ * File:         arch/blackfin/mach-bf548/cpu.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  clock scaling for the bf54x
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <asm/dpmc.h>
+#include <linux/fs.h>
+#include <asm/bfin-global.h>
+
+/* CONFIG_CLKIN_HZ=25000000 */
+#define VCO5 (CONFIG_CLKIN_HZ*45)
+#define VCO4 (CONFIG_CLKIN_HZ*36)
+#define VCO3 (CONFIG_CLKIN_HZ*27)
+#define VCO2 (CONFIG_CLKIN_HZ*18)
+#define VCO1 (CONFIG_CLKIN_HZ*9)
+#define VCO(x) VCO##x
+
+#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
+/* frequency */
+static struct cpufreq_frequency_table bf548_freq_table[] = {
+        MFREQ(1),
+        MFREQ(3),
+        {VCO4, VCO4 / 2}, {VCO4, VCO4},
+        MFREQ(5),
+        {0, CPUFREQ_TABLE_END},
+};
+
+/*
+ * dpmc_fops->ioctl()
+ * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+ */
+static int bf548_getfreq(unsigned int cpu)
+{
+        unsigned long cclk_mhz;
+
+        /* The driver only support single cpu */
+        if (cpu == 0)
+                dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
+        else
+                cclk_mhz = -1;
+
+        return cclk_mhz;
+}
+
+static int bf548_target(struct cpufreq_policy *policy,
+                            unsigned int target_freq, unsigned int relation)
+{
+        unsigned long cclk_mhz;
+        unsigned long vco_mhz;
+        unsigned long flags;
+        unsigned int index;
+        struct cpufreq_freqs freqs;
+
+        if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
+                return -EINVAL;
+
+        cclk_mhz = bf548_freq_table[index].frequency;
+        vco_mhz = bf548_freq_table[index].index;
+
+        dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
+        freqs.old = bf548_getfreq(0);
+        freqs.new = cclk_mhz;
+        freqs.cpu = 0;
+
+        pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
+                 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+        local_irq_save(flags);
+        dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
+        local_irq_restore(flags);
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        vco_mhz = get_vco();
+        cclk_mhz = get_cclk();
+        return 0;
+}
+
+/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
+ * this platform, anyway.
+ */
+static int bf548_verify_speed(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
+}
+
+static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+        /*Now ,only support one cpu */
+        policy->cur = bf548_getfreq(0);
+        cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
+        return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
+}
+
+static struct freq_attr *bf548_freq_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+
+static struct cpufreq_driver bf548_driver = {
+        .verify = bf548_verify_speed,
+        .target = bf548_target,
+        .get = bf548_getfreq,
+        .init = __bf548_cpu_init,
+        .name = "bf548",
+        .owner = THIS_MODULE,
+        .attr = bf548_freq_attr,
+};
+
+static int __init bf548_cpu_init(void)
+{
+        return cpufreq_register_driver(&bf548_driver);
+}
+
+static void __exit bf548_cpu_exit(void)
+{
+        cpufreq_unregister_driver(&bf548_driver);
+}
+
+MODULE_AUTHOR("Mickael Kang");
+MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
+MODULE_LICENSE("GPL");
+
+module_init(bf548_cpu_init);
+module_exit(bf548_cpu_exit);
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
new file mode 100644
index 000000000000..a8184113be48
--- /dev/null
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -0,0 +1,156 @@
+/*
+ * File:         arch/blackfin/mach-bf561/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+        (struct dma_register *) DMA0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA11_NEXT_DESC_PTR,
+        (struct dma_register *) DMA12_NEXT_DESC_PTR,
+        (struct dma_register *) DMA13_NEXT_DESC_PTR,
+        (struct dma_register *) DMA14_NEXT_DESC_PTR,
+        (struct dma_register *) DMA15_NEXT_DESC_PTR,
+        (struct dma_register *) DMA16_NEXT_DESC_PTR,
+        (struct dma_register *) DMA17_NEXT_DESC_PTR,
+        (struct dma_register *) DMA18_NEXT_DESC_PTR,
+        (struct dma_register *) DMA19_NEXT_DESC_PTR,
+        (struct dma_register *) DMA20_NEXT_DESC_PTR,
+        (struct dma_register *) DMA21_NEXT_DESC_PTR,
+        (struct dma_register *) DMA22_NEXT_DESC_PTR,
+        (struct dma_register *) DMA23_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+
+        switch (channel) {
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+        case CH_SPI0:
+                ret_irq = IRQ_SPI0;
+                break;
+        case CH_SPI1:
+                ret_irq = IRQ_SPI1;
+                break;
+        case CH_UART0_RX:
+                ret_irq = IRQ_UART_RX;
+                break;
+        case CH_UART0_TX:
+                ret_irq = IRQ_UART_TX;
+                break;
+        case CH_UART1_RX:
+                ret_irq = IRQ_UART_RX;
+                break;
+        case CH_UART1_TX:
+                ret_irq = IRQ_UART_TX;
+                break;
+        case CH_EPPI0:
+                ret_irq = IRQ_EPPI0;
+                break;
+        case CH_EPPI1:
+                ret_irq = IRQ_EPPI1;
+                break;
+        case CH_EPPI2:
+                ret_irq = IRQ_EPPI2;
+                break;
+        case CH_PIXC_IMAGE:
+                ret_irq = IRQ_PIXC_IN0;
+                break;
+        case CH_PIXC_OVERLAY:
+                ret_irq = IRQ_PIXC_IN1;
+                break;
+        case CH_PIXC_OUTPUT:
+                ret_irq = IRQ_PIXC_OUT;
+                break;
+        case CH_SPORT2_RX:
+                ret_irq = IRQ_SPORT2_RX;
+                break;
+        case CH_SPORT2_TX:
+                ret_irq = IRQ_SPORT2_TX;
+                break;
+        case CH_SPORT3_RX:
+                ret_irq = IRQ_SPORT3_RX;
+                break;
+        case CH_SPORT3_TX:
+                ret_irq = IRQ_SPORT3_TX;
+                break;
+        case CH_SDH:
+                ret_irq = IRQ_SDH;
+                break;
+        case CH_SPI2:
+                ret_irq = IRQ_SPI2;
+                break;
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MDMAS0;
+                break;
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MDMAS1;
+                break;
+        case CH_MEM_STREAM2_SRC:
+        case CH_MEM_STREAM2_DEST:
+                ret_irq = IRQ_MDMAS2;
+                break;
+        case CH_MEM_STREAM3_SRC:
+        case CH_MEM_STREAM3_DEST:
+                ret_irq = IRQ_MDMAS3;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c
new file mode 100644
index 000000000000..0da5f0003b8c
--- /dev/null
+++ b/arch/blackfin/mach-bf548/gpio.c
@@ -0,0 +1,323 @@
+/*
+ * File:         arch/blackfin/mach-bf548/gpio.c
+ * Based on:
+ * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
+ *
+ * Created:
+ * Description:  GPIO Abstraction Layer
+ *
+ * Modified:
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <linux/irq.h>
+
+static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+        (struct gpio_port_t *)PORTA_FER,
+        (struct gpio_port_t *)PORTB_FER,
+        (struct gpio_port_t *)PORTC_FER,
+        (struct gpio_port_t *)PORTD_FER,
+        (struct gpio_port_t *)PORTE_FER,
+        (struct gpio_port_t *)PORTF_FER,
+        (struct gpio_port_t *)PORTG_FER,
+        (struct gpio_port_t *)PORTH_FER,
+        (struct gpio_port_t *)PORTI_FER,
+        (struct gpio_port_t *)PORTJ_FER,
+};
+
+static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
+
+inline int check_gpio(unsigned short gpio)
+{
+        if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
+            || gpio == GPIO_PH14 || gpio == GPIO_PH15
+            || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
+            || gpio > MAX_BLACKFIN_GPIOS)
+                return -EINVAL;
+        return 0;
+}
+
+inline void portmux_setup(unsigned short portno, unsigned short function)
+{
+        u32 pmux;
+
+        pmux = gpio_array[gpio_bank(portno)]->port_mux;
+
+        pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
+        pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
+
+        gpio_array[gpio_bank(portno)]->port_mux = pmux;
+
+}
+
+inline u16 get_portmux(unsigned short portno)
+{
+        u32 pmux;
+
+        pmux = gpio_array[gpio_bank(portno)]->port_mux;
+
+        return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
+
+}
+
+static void port_setup(unsigned short gpio, unsigned short usage)
+{
+        if (usage == GPIO_USAGE) {
+                if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
+                        printk(KERN_WARNING
+                               "bfin-gpio: Possible Conflict with Peripheral "
+                               "usage and GPIO %d detected!\n", gpio);
+                gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
+        } else
+                gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
+        SSYNC();
+}
+
+static int __init bfin_gpio_init(void)
+{
+        printk(KERN_INFO "Blackfin GPIO Controller\n");
+
+        return 0;
+}
+
+arch_initcall(bfin_gpio_init);
+
+int peripheral_request(unsigned short per, const char *label)
+{
+        unsigned long flags;
+        unsigned short ident = P_IDENT(per);
+
+        if (!(per & P_DEFINED))
+                return -ENODEV;
+
+        if (check_gpio(ident) < 0)
+                return -EINVAL;
+
+        local_irq_save(flags);
+
+        if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
+                printk(KERN_ERR
+                       "%s: Peripheral %d is already reserved as GPIO!\n",
+                       __FUNCTION__, per);
+                dump_stack();
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+
+        if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
+
+                u16 funct = get_portmux(ident);
+
+                if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
+                        printk(KERN_ERR
+                               "%s: Peripheral %d is already reserved!\n",
+                               __FUNCTION__, per);
+                        dump_stack();
+                        local_irq_restore(flags);
+                        return -EBUSY;
+                }
+        }
+
+        reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
+
+        portmux_setup(ident, P_FUNCT2MUX(per));
+        port_setup(ident, PERIPHERAL_USAGE);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(peripheral_request);
+
+int peripheral_request_list(unsigned short per[], const char *label)
+{
+
+        u16 cnt;
+        int ret;
+
+        for (cnt = 0; per[cnt] != 0; cnt++) {
+                ret = peripheral_request(per[cnt], label);
+                if (ret < 0)
+                        return ret;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(peripheral_request_list);
+
+void peripheral_free(unsigned short per)
+{
+        unsigned long flags;
+        unsigned short ident = P_IDENT(per);
+
+        if (!(per & P_DEFINED))
+                return;
+
+        if (check_gpio(ident) < 0)
+                return;
+
+        local_irq_save(flags);
+
+        if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
+                printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
+                dump_stack();
+                local_irq_restore(flags);
+                return;
+        }
+
+        if (!(per & P_MAYSHARE)) {
+                port_setup(ident, GPIO_USAGE);
+        }
+
+        reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(peripheral_free);
+
+void peripheral_free_list(unsigned short per[])
+{
+        u16 cnt;
+
+        for (cnt = 0; per[cnt] != 0; cnt++) {
+                peripheral_free(per[cnt]);
+        }
+
+}
+EXPORT_SYMBOL(peripheral_free_list);
+
+/***********************************************************
+*
+* FUNCTIONS: Blackfin GPIO Driver
+*
+* INPUTS/OUTPUTS:
+* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
+*
+*
+* DESCRIPTION: Blackfin GPIO Driver API
+*
+* CAUTION:
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+int gpio_request(unsigned short gpio, const char *label)
+{
+        unsigned long flags;
+
+        if (check_gpio(gpio) < 0)
+                return -EINVAL;
+
+        local_irq_save(flags);
+
+        if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
+                dump_stack();
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+
+        if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                printk(KERN_ERR
+                       "bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
+                dump_stack();
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+
+        reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
+
+        local_irq_restore(flags);
+
+        port_setup(gpio, GPIO_USAGE);
+
+        return 0;
+}
+EXPORT_SYMBOL(gpio_request);
+
+void gpio_free(unsigned short gpio)
+{
+        unsigned long flags;
+
+        if (check_gpio(gpio) < 0)
+                return;
+
+        local_irq_save(flags);
+
+        if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
+                printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
+                dump_stack();
+                local_irq_restore(flags);
+                return;
+        }
+
+        reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_free);
+
+void gpio_direction_input(unsigned short gpio)
+{
+        unsigned long flags;
+
+        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+
+        local_irq_save(flags);
+        gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
+        gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_direction_input);
+
+void gpio_direction_output(unsigned short gpio)
+{
+        unsigned long flags;
+
+        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+
+        local_irq_save(flags);
+        gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
+        gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_direction_output);
+
+void gpio_set_value(unsigned short gpio, unsigned short arg)
+{
+        if (arg)
+                gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
+        else
+                gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
+
+}
+EXPORT_SYMBOL(gpio_set_value);
+
+unsigned short gpio_get_value(unsigned short gpio)
+{
+        return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
+}
+EXPORT_SYMBOL(gpio_get_value);
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
new file mode 100644
index 000000000000..06751ae8b857
--- /dev/null
+++ b/arch/blackfin/mach-bf548/head.S
@@ -0,0 +1,512 @@
+/*
+ * File:         arch/blackfin/mach-bf548/head.S
+ * Based on:     arch/blackfin/mach-bf537/head.S
+ * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
+ *
+ * Created:      1998
+ * Description:  Startup code for Blackfin BF548
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/trace.h>
+#if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach/mem_init.h>
+#endif
+
+.global __rambase
+.global __ramstart
+.global __ramend
+.extern ___bss_stop
+.extern ___bss_start
+.extern _bf53x_relocate_l1_mem
+
+#define INITIAL_STACK   0xFFB01000
+
+.text
+
+ENTRY(__start)
+ENTRY(__stext)
+        /* R0: argument of command line string, passed from uboot, save it */
+        R7 = R0;
+        /* Set the SYSCFG register */
+        R0 = 0x36;
+        SYSCFG = R0;   /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
+        R0 = 0;
+
+        /* Clear Out All the data and pointer  Registers*/
+        R1 = R0;
+        R2 = R0;
+        R3 = R0;
+        R4 = R0;
+        R5 = R0;
+        R6 = R0;
+
+        P0 = R0;
+        P1 = R0;
+        P2 = R0;
+        P3 = R0;
+        P4 = R0;
+        P5 = R0;
+
+        LC0 = r0;
+        LC1 = r0;
+        L0 = r0;
+        L1 = r0;
+        L2 = r0;
+        L3 = r0;
+
+        /* Clear Out All the DAG Registers*/
+        B0 = r0;
+        B1 = r0;
+        B2 = r0;
+        B3 = r0;
+
+        I0 = r0;
+        I1 = r0;
+        I2 = r0;
+        I3 = r0;
+
+        M0 = r0;
+        M1 = r0;
+        M2 = r0;
+        M3 = r0;
+
+        trace_buffer_start(p0,r0);
+        P0 = R1;
+        R0 = R1;
+
+        /* Turn off the icache */
+        p0.l = (IMEM_CONTROL & 0xFFFF);
+        p0.h = (IMEM_CONTROL >> 16);
+        R1 = [p0];
+        R0 = ~ENICPLB;
+        R0 = R0 & R1;
+        [p0] = R0;
+        SSYNC;
+
+        /* Turn off the dcache */
+        p0.l = (DMEM_CONTROL & 0xFFFF);
+        p0.h = (DMEM_CONTROL >> 16);
+        R1 = [p0];
+        R0 = ~ENDCPLB;
+        R0 = R0 & R1;
+        [p0] = R0;
+        SSYNC;
+
+        /* Initialize stack pointer */
+        SP.L = LO(INITIAL_STACK);
+        SP.H = HI(INITIAL_STACK);
+        FP = SP;
+        USP = SP;
+
+        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
+        call _bf53x_relocate_l1_mem;
+#if CONFIG_BFIN_KERNEL_CLOCK
+        call _start_dma_code;
+#endif
+        /* Code for initializing Async memory banks */
+
+        p2.h = hi(EBIU_AMBCTL1);
+        p2.l = lo(EBIU_AMBCTL1);
+        r0.h = hi(AMBCTL1VAL);
+        r0.l = lo(AMBCTL1VAL);
+        [p2] = r0;
+        ssync;
+
+        p2.h = hi(EBIU_AMBCTL0);
+        p2.l = lo(EBIU_AMBCTL0);
+        r0.h = hi(AMBCTL0VAL);
+        r0.l = lo(AMBCTL0VAL);
+        [p2] = r0;
+        ssync;
+
+        p2.h = hi(EBIU_AMGCTL);
+        p2.l = lo(EBIU_AMGCTL);
+        r0 = AMGCTLVAL;
+        w[p2] = r0;
+        ssync;
+
+        /* This section keeps the processor in supervisor mode
+         * during kernel boot.  Switches to user mode at end of boot.
+         * See page 3-9 of Hardware Reference manual for documentation.
+         */
+
+        /* EVT15 = _real_start */
+
+        p0.l = lo(EVT15);
+        p0.h = hi(EVT15);
+        p1.l = _real_start;
+        p1.h = _real_start;
+        [p0] = p1;
+        csync;
+
+        p0.l = lo(IMASK);
+        p0.h = hi(IMASK);
+        p1.l = IMASK_IVG15;
+        p1.h = 0x0;
+        [p0] = p1;
+        csync;
+
+        raise 15;
+        p0.l = .LWAIT_HERE;
+        p0.h = .LWAIT_HERE;
+        reti = p0;
+#if defined (ANOMALY_05000281)
+        nop;
+        nop;
+        nop;
+#endif
+        rti;
+
+.LWAIT_HERE:
+        jump .LWAIT_HERE;
+
+ENTRY(_real_start)
+        [ -- sp ] = reti;
+        p0.l = lo(WDOG_CTL);
+        p0.h = hi(WDOG_CTL);
+        r0 = 0xAD6(z);
+        w[p0] = r0;     /* watchdog off for now */
+        ssync;
+
+        /* Code update for BSS size == 0
+         * Zero out the bss region.
+         */
+
+        p1.l = ___bss_start;
+        p1.h = ___bss_start;
+        p2.l = ___bss_stop;
+        p2.h = ___bss_stop;
+        r0 = 0;
+        p2 -= p1;
+        lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
+.L_clear_bss:
+        B[p1++] = r0;
+
+        /* In case there is a NULL pointer reference
+         * Zero out region before stext
+         */
+
+        p1.l = 0x0;
+        p1.h = 0x0;
+        r0.l = __stext;
+        r0.h = __stext;
+        r0 = r0 >> 1;
+        p2 = r0;
+        r0 = 0;
+        lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
+.L_clear_zero:
+        W[p1++] = r0;
+
+        /* pass the uboot arguments to the global value command line */
+        R0 = R7;
+        call _cmdline_init;
+
+        p1.l = __rambase;
+        p1.h = __rambase;
+        r0.l = __sdata;
+        r0.h = __sdata;
+        [p1] = r0;
+
+        p1.l = __ramstart;
+        p1.h = __ramstart;
+        p3.l = ___bss_stop;
+        p3.h = ___bss_stop;
+
+        r1 = p3;
+        [p1] = r1;
+
+
+        /*
+         *  load the current thread pointer and stack
+         */
+        r1.l = _init_thread_union;
+        r1.h = _init_thread_union;
+
+        r2.l = 0x2000;
+        r2.h = 0x0000;
+        r1 = r1 + r2;
+        sp = r1;
+        usp = sp;
+        fp = sp;
+        call _start_kernel;
+.L_exit:
+        jump.s  .L_exit;
+
+.section .l1.text
+#if CONFIG_BFIN_KERNEL_CLOCK
+ENTRY(_start_dma_code)
+
+        /* Enable PHY CLK buffer output */
+        p0.h = hi(VR_CTL);
+        p0.l = lo(VR_CTL);
+        r0.l = w[p0];
+        bitset(r0, 14);
+        w[p0] = r0.l;
+        ssync;
+
+        p0.h = hi(SIC_IWR);
+        p0.l = lo(SIC_IWR);
+        r0.l = 0x1;
+        r0.h = 0x0;
+        [p0] = r0;
+        SSYNC;
+
+        /*
+         *  Set PLL_CTL
+         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+         *   - [7]     = output delay (add 200ps of delay to mem signals)
+         *   - [6]     = input delay (add 200ps of input delay to mem signals)
+         *   - [5]     = PDWN      : 1=All Clocks off
+         *   - [3]     = STOPCK    : 1=Core Clock off
+         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+         *   all other bits set to zero
+         */
+
+        p0.h = hi(PLL_LOCKCNT);
+        p0.l = lo(PLL_LOCKCNT);
+        r0 = 0x300(Z);
+        w[p0] = r0.l;
+        ssync;
+
+        P2.H = hi(EBIU_SDGCTL);
+        P2.L = lo(EBIU_SDGCTL);
+        R0 = [P2];
+        BITSET (R0, 24);
+        [P2] = R0;
+        SSYNC;
+
+        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
+        r0 = r0 << 9;                    /* Shift it over,                  */
+        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
+        r0 = r1 | r0;
+        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
+        r1 = r1 << 8;                    /* Shift it over                   */
+        r0 = r1 | r0;                    /* add them all together           */
+
+        p0.h = hi(PLL_CTL);
+        p0.l = lo(PLL_CTL);              /* Load the address                */
+        cli r2;                          /* Disable interrupts              */
+        ssync;
+        w[p0] = r0.l;                    /* Set the value                   */
+        idle;                            /* Wait for the PLL to stablize    */
+        sti r2;                          /* Enable interrupts               */
+
+.Lcheck_again:
+        p0.h = hi(PLL_STAT);
+        p0.l = lo(PLL_STAT);
+        R0 = W[P0](Z);
+        CC = BITTST(R0,5);
+        if ! CC jump .Lcheck_again;
+
+        /* Configure SCLK & CCLK Dividers */
+        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+        p0.h = hi(PLL_DIV);
+        p0.l = lo(PLL_DIV);
+        w[p0] = r0.l;
+        ssync;
+
+        p0.l = lo(EBIU_SDRRC);
+        p0.h = hi(EBIU_SDRRC);
+        r0 = mem_SDRRC;
+        w[p0] = r0.l;
+        ssync;
+
+        p0.l = (EBIU_SDBCTL & 0xFFFF);
+        p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+        r0 = mem_SDBCTL;
+        w[p0] = r0.l;
+        ssync;
+
+        P2.H = hi(EBIU_SDGCTL);
+        P2.L = lo(EBIU_SDGCTL);
+        R0 = [P2];
+        BITCLR (R0, 24);
+        p0.h = hi(EBIU_SDSTAT);
+        p0.l = lo(EBIU_SDSTAT);
+        r2.l = w[p0];
+        cc = bittst(r2,3);
+        if !cc jump .Lskip;
+        NOP;
+        BITSET (R0, 23);
+.Lskip:
+        [P2] = R0;
+        SSYNC;
+
+        R0.L = lo(mem_SDGCTL);
+        R0.H = hi(mem_SDGCTL);
+        R1 = [p2];
+        R1 = R1 | R0;
+        [P2] = R1;
+        SSYNC;
+
+        p0.h = hi(SIC_IWR);
+        p0.l = lo(SIC_IWR);
+        r0.l = lo(IWR_ENABLE_ALL);
+        r0.h = hi(IWR_ENABLE_ALL);
+        [p0] = r0;
+        SSYNC;
+
+        RTS;
+#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+
+ENTRY(_bfin_reset)
+        /* No more interrupts to be handled*/
+        CLI R6;
+        SSYNC;
+
+#if defined(CONFIG_MTD_M25P80)
+/*
+ * The following code fix the SPI flash reboot issue,
+ * /CS signal of the chip which is using PF10 return to GPIO mode
+ */
+        p0.h = hi(PORTF_FER);
+        p0.l = lo(PORTF_FER);
+        r0.l = 0x0000;
+        w[p0] = r0.l;
+        SSYNC;
+
+/* /CS return to high */
+        p0.h = hi(PORTFIO);
+        p0.l = lo(PORTFIO);
+        r0.l = 0xFFFF;
+        w[p0] = r0.l;
+        SSYNC;
+
+/* Delay some time, This is necessary */
+        r1.h = 0;
+        r1.l = 0x400;
+        p1   = r1;
+        lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
+_delay_lab1:
+        r0.h = 0;
+        r0.l = 0x8000;
+        p0   = r0;
+        lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
+_delay_lab0:
+        nop;
+_delay_lab0_end:
+        nop;
+_delay_lab1_end:
+        nop;
+#endif
+
+        /* Clear the bits 13-15 in SWRST if they werent cleared */
+        p0.h = hi(SWRST);
+        p0.l = lo(SWRST);
+        csync;
+        r0.l = w[p0];
+
+        /* Clear the IMASK register */
+        p0.h = hi(IMASK);
+        p0.l = lo(IMASK);
+        r0 = 0x0;
+        [p0] = r0;
+
+        /* Clear the ILAT register */
+        p0.h = hi(ILAT);
+        p0.l = lo(ILAT);
+        r0 = [p0];
+        [p0] = r0;
+        SSYNC;
+
+        /* Disable the WDOG TIMER */
+        p0.h = hi(WDOG_CTL);
+        p0.l = lo(WDOG_CTL);
+        r0.l = 0xAD6;
+        w[p0] = r0.l;
+        SSYNC;
+
+        /* Clear the sticky bit incase it is already set */
+        p0.h = hi(WDOG_CTL);
+        p0.l = lo(WDOG_CTL);
+        r0.l = 0x8AD6;
+        w[p0] = r0.l;
+        SSYNC;
+
+        /* Program the count value */
+        R0.l = 0x100;
+        R0.h = 0x0;
+        P0.h = hi(WDOG_CNT);
+        P0.l = lo(WDOG_CNT);
+        [P0] = R0;
+        SSYNC;
+
+        /* Program WDOG_STAT if necessary */
+        P0.h = hi(WDOG_CTL);
+        P0.l = lo(WDOG_CTL);
+        R0 = W[P0](Z);
+        CC = BITTST(R0,1);
+        if !CC JUMP .LWRITESTAT;
+        CC = BITTST(R0,2);
+        if !CC JUMP .LWRITESTAT;
+        JUMP .LSKIP_WRITE;
+
+.LWRITESTAT:
+        /* When watch dog timer is enabled,
+         * a write to STAT will load the contents of CNT to STAT
+         */
+        R0 = 0x0000(z);
+        P0.h = hi(WDOG_STAT);
+        P0.l = lo(WDOG_STAT)
+        [P0] = R0;
+        SSYNC;
+
+.LSKIP_WRITE:
+        /* Enable the reset event */
+        P0.h = hi(WDOG_CTL);
+        P0.l = lo(WDOG_CTL);
+        R0 = W[P0](Z);
+        BITCLR(R0,1);
+        BITCLR(R0,2);
+        W[P0] = R0.L;
+        SSYNC;
+        NOP;
+
+        /* Enable the wdog counter */
+        R0 = W[P0](Z);
+        BITCLR(R0,4);
+        W[P0] = R0.L;
+        SSYNC;
+
+        IDLE;
+
+        RTS;
+
+.data
+
+/*
+ * Set up the usable of RAM stuff. Size of RAM is determined then
+ * an initial stack set up at the end.
+ */
+
+.align 4
+__rambase:
+.long   0
+__ramstart:
+.long   0
+__ramend:
+.long   0
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
new file mode 100644
index 000000000000..cb0ebac53c79
--- /dev/null
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -0,0 +1,137 @@
+/*
+ * File:         arch/blackfin/mach-bf537/ints-priority.c
+ * Based on:     arch/blackfin/mach-bf533/ints-priority.c
+ * Author:       Michael Hennerich
+ *
+ * Created:
+ * Description:  Set up the interupt priorities
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/blackfin.h>
+
+void program_IAR(void)
+{
+        /* Program the IAR0 Register with the configured priority */
+        bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
+                            ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
+                            ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
+                            ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
+                            ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
+                            ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
+                            ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
+                            ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
+
+        bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
+                            ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
+                            ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
+                            ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
+                            ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
+                            ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
+                            ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
+                            ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
+
+        bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
+                            ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
+                            ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
+                            ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
+                            ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
+                            ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
+                            ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
+
+        bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
+                            ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
+                            ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
+                            ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
+                            ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
+                            ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
+                            ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
+                            ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
+
+        bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
+                            ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
+                            ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
+                            ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
+                            ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
+                            ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
+                            ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
+                            ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
+
+        bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
+                            ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
+                            ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
+                            ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
+                            ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
+                            ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
+                            ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
+                            ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
+
+        bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
+                            ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
+                            ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
+                            ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
+                            ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
+                            ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
+                            ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
+                            ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
+
+        bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
+                            ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
+                            ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
+                            ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
+                            ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
+                            ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
+                            ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
+
+        bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
+                            ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
+                            ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
+                            ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
+                            ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
+                            ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
+                            ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
+                            ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
+
+        bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
+                            ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
+                            ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
+                            ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
+                            ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
+                            ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
+                            ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
+
+        bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+                             ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
+
+        bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+                             ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
+                             ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
+                             ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
+                             ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
+                             ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
+                             ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
+                             ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
+
+        SSYNC();
+}
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
index 57f475a55161..f39235a55783 100644
--- a/arch/blackfin/mach-bf561/Makefile
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -4,6 +4,6 @@
 
 extra-y := head.o
 
-obj-y := ints-priority.o
+obj-y := ints-priority.o dma.o
 
 obj-$(CONFIG_BF561_COREB) += coreb.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 3dc5c042048c..5b2b544529a1 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -34,7 +34,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/bfin5xx_spi.h>
 
 /*
@@ -52,11 +52,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .size = 0x00020000,
                 .offset = 0,
                 .mask_flags = MTD_CAP_ROM
-        },{
+        }, {
                 .name = "kernel",
                 .size = 0xe0000,
                 .offset = 0x20000
-        },{
+        }, {
                 .name = "file system",
                 .size = 0x700000,
                 .offset = 0x00100000,
@@ -186,7 +186,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x28000300,
                 .end = 0x28000300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF0,
                 .end = IRQ_PF0,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -206,11 +206,11 @@ static struct resource isp1362_hcd_resources[] = {
                 .start = 0x24008000,
                 .end = 0x24008000,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = 0x24008004,
                 .end = 0x24008004,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PF47,
                 .end = IRQ_PF47,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -241,25 +241,25 @@ static struct platform_device isp1362_hcd_device = {
 
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
-        {
-                .start = 0xFFC00400,
-                .end = 0xFFC004FF,
-                .flags = IORESOURCE_MEM,
-        },
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
 };
 
 static struct platform_device bfin_uart_device = {
-        .name = "bfin-uart",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(bfin_uart_resources),
-        .resource = bfin_uart_resources,
+        .name = "bfin-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart_resources),
+        .resource = bfin_uart_resources,
 };
 #endif
 
 static struct platform_device *cm_bf561_devices[] __initdata = {
 
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
-        &bfin_uart_device,
+        &bfin_uart_device,
 #endif
 
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9720b5c307ab..724191da20a2 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -30,10 +30,9 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
-#include <asm/irq.h>
-#include <asm/bfin5xx_spi.h>
-#include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/bfin5xx_spi.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -45,13 +44,13 @@ char *bfin_board_name = "ADDS-BF561-EZKIT";
 
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
 static struct resource bfin_isp1761_resources[] = {
-        [0] = {
+        {
                 .name   = "isp1761-regs",
                 .start  = ISP1761_BASE + 0x00000000,
                 .end    = ISP1761_BASE + 0x000fffff,
                 .flags  = IORESOURCE_MEM,
         },
-        [1] = {
+        {
                 .start  = ISP1761_IRQ,
                 .end    = ISP1761_IRQ,
                 .flags  = IORESOURCE_IRQ,
@@ -71,7 +70,7 @@ static struct platform_device *bfin_isp1761_devices[] = {
 
 int __init bfin_isp1761_init(void)
 {
-        unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices);
+        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
 
         printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
         set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
@@ -98,7 +97,7 @@ static struct resource smc91x_resources[] = {
                 .start = 0x2C010300,
                 .end = 0x2C010300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
 
                 .start = IRQ_PF9,
                 .end = IRQ_PF9,
@@ -116,18 +115,18 @@ static struct platform_device smc91x_device = {
 
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
-        {
-                .start = 0xFFC00400,
-                .end = 0xFFC004FF,
-                .flags = IORESOURCE_MEM,
-        },
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
 };
 
 static struct platform_device bfin_uart_device = {
-        .name = "bfin-uart",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(bfin_uart_resources),
-        .resource = bfin_uart_resources,
+        .name = "bfin-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart_resources),
+        .resource = bfin_uart_resources,
 };
 #endif
 
@@ -176,7 +175,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &spi_bfin_master_device,
 #endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
-        &bfin_uart_device,
+        &bfin_uart_device,
 #endif
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
index 585ecdd2f6a5..4dfea5da674c 100644
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ b/arch/blackfin/mach-bf561/boards/generic_board.c
@@ -30,7 +30,7 @@
 
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 
 char *bfin_board_name = "UNKNOWN BOARD";
 
@@ -43,11 +43,11 @@ static struct resource smc91x_resources[] = {
                 .start = 0x2C010300,
                 .end = 0x2C010300 + 16,
                 .flags = IORESOURCE_MEM,
-        },{
+        }, {
                 .start = IRQ_PROG_INTB,
                 .end = IRQ_PROG_INTB,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },{
+        }, {
                 /*
                  *  denotes the flag pin and is used directly if
                  *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index db308c7ccabb..c442eb23db5e 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -14,7 +14,7 @@
 
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 
 char *bfin_board_name = "Tepla-BF561";
 
@@ -26,11 +26,11 @@ static struct resource smc91x_resources[] = {
                 .start  = 0x2C000300,
                 .end    = 0x2C000320,
                 .flags  = IORESOURCE_MEM,
-        },{
+        }, {
                 .start  = IRQ_PROG_INTB,
                 .end    = IRQ_PROG_INTB,
                 .flags  = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
-        },{
+        }, {
                 /*
                  *  denotes the flag pin and is used directly if
                  *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index b28582fe083c..5d1d21b4c2a7 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -32,8 +32,8 @@
 #include <linux/device.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/uaccess.h>
 #include <asm/dma.h>
-#include <asm/uaccess.h>
 
 #define MODULE_VER              "v0.1"
 
@@ -202,7 +202,7 @@ static int coreb_open(struct inode *inode, struct file *file)
         spin_unlock_irq(&coreb_lock);
         return 0;
 
-      out_busy:
+ out_busy:
         spin_unlock_irq(&coreb_lock);
         return -EBUSY;
 }
@@ -365,19 +365,19 @@ int __init bf561_coreb_init(void)
         printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
         return 0;
 
-      release_dma_src:
+ release_dma_src:
         free_dma(CH_MEM_STREAM2_SRC);
-      release_dma_dest:
+ release_dma_dest:
         free_dma(CH_MEM_STREAM2_DEST);
-      release_data_a_sram:
+ release_data_a_sram:
         release_mem_region(0xff400000, 0x8000);
-      release_data_b_sram:
+ release_data_b_sram:
         release_mem_region(0xff500000, 0x8000);
-      release_instruction_b_sram:
+ release_instruction_b_sram:
         release_mem_region(0xff610000, 0x4000);
-      release_instruction_a_sram:
+ release_instruction_a_sram:
         release_mem_region(0xff600000, 0x4000);
-      exit:
+ exit:
         return -ENOMEM;
 }
 
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
new file mode 100644
index 000000000000..89c65bb0bed3
--- /dev/null
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -0,0 +1,131 @@
+/*
+ * File:         arch/blackfin/mach-bf561/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+        (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
+        (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+
+        switch (channel) {
+        case CH_PPI0:
+                ret_irq = IRQ_PPI0;
+                break;
+        case CH_PPI1:
+                ret_irq = IRQ_PPI1;
+                break;
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+                break;
+        case CH_SPI:
+                ret_irq = IRQ_SPI;
+                break;
+        case CH_UART_RX:
+                ret_irq = IRQ_UART_RX;
+                break;
+        case CH_UART_TX:
+                ret_irq = IRQ_UART_TX;
+                break;
+
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MEM_DMA0;
+                break;
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MEM_DMA1;
+                break;
+        case CH_MEM_STREAM2_SRC:
+        case CH_MEM_STREAM2_DEST:
+                ret_irq = IRQ_MEM_DMA2;
+                break;
+        case CH_MEM_STREAM3_SRC:
+        case CH_MEM_STREAM3_DEST:
+                ret_irq = IRQ_MEM_DMA3;
+                break;
+
+        case CH_IMEM_STREAM0_SRC:
+        case CH_IMEM_STREAM0_DEST:
+                ret_irq = IRQ_IMEM_DMA0;
+                break;
+        case CH_IMEM_STREAM1_SRC:
+        case CH_IMEM_STREAM1_DEST:
+                ret_irq = IRQ_IMEM_DMA1;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 31cbc75c85cf..2f08bcb2dded 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -30,6 +30,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/blackfin.h>
+#include <asm/trace.h>
+
 #if CONFIG_BFIN_KERNEL_CLOCK
 #include <asm/mach/mem_init.h>
 #endif
@@ -93,6 +95,10 @@ ENTRY(__start)
         M2 = r0;
         M3 = r0;
 
+        trace_buffer_start(p0,r0);
+        P0 = R1;
+        R0 = R1;
+
         /* Turn off the icache */
         p0.l = (IMEM_CONTROL & 0xFFFF);
         p0.h = (IMEM_CONTROL >> 16);
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
index 86e3b0ee93f4..09b541b0f7c2 100644
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -28,8 +28,8 @@
  */
 
 #include <linux/module.h>
+#include <linux/irq.h>
 #include <asm/blackfin.h>
-#include <asm/irq.h>
 
 void program_IAR(void)
 {
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index d3a49073d196..0279ede70392 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,9 +4,9 @@
 
 obj-y := \
         cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
-        interrupt.o lock.o dpmc.o irqpanic.o
+        interrupt.o lock.o irqpanic.o
 
 obj-$(CONFIG_CPLB_INFO)          += cplbinfo.o
 obj-$(CONFIG_BFIN_SINGLE_CORE)   += ints-priority-sc.o
 obj-$(CONFIG_BFIN_DUAL_CORE)     += ints-priority-dc.o
-obj-$(CONFIG_PM)                 += pm.o
+obj-$(CONFIG_PM)                 += pm.o dpmc.o
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 7924a90d9658..9d475623b724 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,104 +38,37 @@
 
 .text
 
+#ifdef ANOMALY_05000125
 #if defined(CONFIG_BLKFIN_CACHE)
-ENTRY(_bfin_icache_init)
+ENTRY(_bfin_write_IMEM_CONTROL)
 
-        /* Initialize Instruction CPLBS */
-
-        I0.L = (ICPLB_ADDR0 & 0xFFFF);
-        I0.H = (ICPLB_ADDR0 >> 16);
-
-        I1.L = (ICPLB_DATA0 & 0xFFFF);
-        I1.H = (ICPLB_DATA0 >> 16);
-
-        I2.L = _icplb_table;
-        I2.H = _icplb_table;
-
-        r1 = -1;        /* end point comparison */
-        r3 = 15;        /* max counter */
-
-/* read entries from table */
-
-.Lread_iaddr:
-        R0 = [I2++];
-        CC = R0 == R1;
-        IF CC JUMP .Lidone;
-        [I0++] = R0;
-
-.Lread_idata:
-        R2 = [I2++];
-        [I1++] = R2;
-        R3 = R3 + R1;
-        CC = R3 == R1;
-        IF !CC JUMP .Lread_iaddr;
-
-.Lidone:
         /* Enable Instruction Cache */
         P0.l = (IMEM_CONTROL & 0xFFFF);
         P0.h = (IMEM_CONTROL >> 16);
-        R1 = [P0];
-        R0 = (IMC | ENICPLB);
-        R0 = R0 | R1;
 
         /* Anomaly 05000125 */
-        CLI R2;
+        CLI R1;
         SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
         .align 8;
         [P0] = R0;
         SSYNC;
-        STI R2;
+        STI R1;
         RTS;
 
-ENDPROC(_bfin_icache_init)
+ENDPROC(_bfin_write_IMEM_CONTROL)
 #endif
 
 #if defined(CONFIG_BLKFIN_DCACHE)
-ENTRY(_bfin_dcache_init)
-
-        /* Initialize Data CPLBS */
-
-        I0.L = (DCPLB_ADDR0 & 0xFFFF);
-        I0.H = (DCPLB_ADDR0 >> 16);
-
-        I1.L = (DCPLB_DATA0 & 0xFFFF);
-        I1.H = (DCPLB_DATA0 >> 16);
-
-        I2.L = _dcplb_table;
-        I2.H = _dcplb_table;
-
-        R1 = -1;        /* end point comparison */
-        R3 = 15;        /* max counter */
-
-        /* read entries from table */
-.Lread_daddr:
-        R0 = [I2++];
-        cc = R0 == R1;
-        IF CC JUMP .Lddone;
-        [I0++] = R0;
-
-.Lread_ddata:
-        R2 = [I2++];
-        [I1++] = R2;
-        R3 = R3 + R1;
-        CC = R3 == R1;
-        IF !CC JUMP .Lread_daddr;
-.Lddone:
-        P0.L = (DMEM_CONTROL & 0xFFFF);
-        P0.H = (DMEM_CONTROL >> 16);
-        R1 = [P0];
-
-        R0 = DMEM_CNTR;
-
-        R0 = R0 | R1;
-        /* Anomaly 05000125 */
-        CLI R2;
+ENTRY(_bfin_write_DMEM_CONTROL)
+        CLI R1;
         SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
         .align 8;
         [P0] = R0;
         SSYNC;
-        STI R2;
+        STI R1;
         RTS;
 
-ENDPROC(_bfin_dcache_init)
+ENDPROC(_bfin_write_DMEM_CONTROL)
+#endif
+
 #endif
diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/mach-common/cplbinfo.c
index caa9623e6bd6..785ca9816971 100644
--- a/arch/blackfin/mach-common/cplbinfo.c
+++ b/arch/blackfin/mach-common/cplbinfo.c
@@ -31,11 +31,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/proc_fs.h>
+#include <linux/uaccess.h>
 
 #include <asm/current.h>
-#include <asm/uaccess.h>
 #include <asm/system.h>
-
 #include <asm/cplb.h>
 #include <asm/blackfin.h>
 
@@ -92,8 +91,7 @@ static char *cplb_print_entry(char *buf, int type)
         } else
                 buf += sprintf(buf, "Data CPLB entry:\n");
 
-        buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\
-\tiCount\toCount\n");
+        buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\n\tiCount\toCount\n");
 
         while (*p_addr != 0xffffffff) {
                 entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data);
@@ -144,8 +142,7 @@ static int cplbinfo_proc_output(char *buf)
 
         p = buf;
 
-        p += sprintf(p,
-                     "------------------ CPLB Information ------------------\n\n");
+        p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
 
         if (bfin_read_IMEM_CONTROL() & ENICPLB)
                 p = cplb_print_entry(p, CPLB_I);
@@ -191,9 +188,9 @@ static int __init cplbinfo_init(void)
 {
         struct proc_dir_entry *entry;
 
-        if ((entry = create_proc_entry("cplbinfo", 0, NULL)) == NULL) {
+        entry = create_proc_entry("cplbinfo", 0, NULL);
+        if (!entry)
                 return -ENOMEM;
-        }
 
         entry->read_proc = cplbinfo_read_proc;
         entry->write_proc = cplbinfo_write_proc;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 40045b1386ad..d61bba98fb54 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -49,34 +49,15 @@
 
 
 #include <linux/linkage.h>
+#include <linux/unistd.h>
 #include <asm/blackfin.h>
-#include <asm/unistd.h>
 #include <asm/errno.h>
 #include <asm/thread_info.h>  /* TIF_NEED_RESCHED */
 #include <asm/asm-offsets.h>
+#include <asm/trace.h>
 
 #include <asm/mach-common/context.S>
 
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-        /*
-         * TODO: this should be proper save/restore, but for now
-         * we'll just cheat and use 0x1/0x13
-         */
-# define DEBUG_START_HWTRACE \
-        P5.l = LO(TBUFCTL); \
-        P5.h = HI(TBUFCTL); \
-        R7 = 0x13; \
-        [P5] = R7;
-# define DEBUG_STOP_HWTRACE \
-        P5.l = LO(TBUFCTL); \
-        P5.h = HI(TBUFCTL); \
-        R7 = 0x01; \
-        [P5] = R7;
-#else
-# define DEBUG_START_HWTRACE
-# define DEBUG_STOP_HWTRACE
-#endif
-
 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
 .section .l1.text
 #else
@@ -110,25 +91,14 @@ ENTRY(_ex_icplb)
         ASTAT = [sp++];
         SAVE_ALL_SYS
         call __cplb_hdr;
-        DEBUG_START_HWTRACE
+        DEBUG_START_HWTRACE(p5, r7)
         RESTORE_ALL_SYS
         SP = RETN;
         rtx;
 ENDPROC(_ex_icplb)
 
-ENTRY(_ex_spinlock)
-        /* Transform this into a syscall - twiddle the syscall vector.  */
-        p5.l = lo(EVT15);
-        p5.h = hi(EVT15);
-        r7.l = _spinlock_bh;
-        r7.h = _spinlock_bh;
-        [p5] = r7;
-        csync;
-        /* Fall through.  */
-ENDPROC(_ex_spinlock)
-
 ENTRY(_ex_syscall)
-        DEBUG_START_HWTRACE
+        DEBUG_START_HWTRACE(p5, r7)
         (R7:6,P5:4) = [sp++];
         ASTAT = [sp++];
         raise 15;               /* invoked by TRAP #0, for sys call */
@@ -136,26 +106,6 @@ ENTRY(_ex_syscall)
         rtx
 ENDPROC(_ex_syscall)
 
-ENTRY(_spinlock_bh)
-        SAVE_ALL_SYS
-        /* To end up here, vector 15 was changed - so we have to change it
-         * back.
-         */
-        p0.l = lo(EVT15);
-        p0.h = hi(EVT15);
-        p1.l = _evt_system_call;
-        p1.h = _evt_system_call;
-        [p0] = p1;
-        csync;
-        r0 = [sp + PT_R0];
-        sp += -12;
-        call _sys_bfin_spinlock;
-        sp += 12;
-        [SP + PT_R0] = R0;
-        RESTORE_ALL_SYS
-        rti;
-ENDPROC(_spinlock_bh)
-
 ENTRY(_ex_soft_bp)
         r7 = retx;
         r7 += -2;
@@ -186,7 +136,7 @@ ENTRY(_ex_single_step)
         if !cc jump _ex_trap_c;
 
 _return_from_exception:
-        DEBUG_START_HWTRACE
+        DEBUG_START_HWTRACE(p5, r7)
 #ifdef ANOMALY_05000257
         R7=LC0;
         LC0=R7;
@@ -208,7 +158,7 @@ ENTRY(_handle_bad_cplb)
          * need to make a CPLB exception look like a normal exception
          */
 
-        DEBUG_START_HWTRACE
+        DEBUG_START_HWTRACE(p5, r7)
         RESTORE_ALL_SYS
         [--sp] = ASTAT;
         [--sp] = (R7:6, P5:4);
@@ -251,7 +201,7 @@ ENTRY(_ex_trap_c)
         R6 = SEQSTAT;
         [P5] = R6;
 
-        DEBUG_START_HWTRACE
+        DEBUG_START_HWTRACE(p5, r7)
         (R7:6,P5:4) = [sp++];
         ASTAT = [sp++];
         SP = RETN;
@@ -335,7 +285,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
         /* Try to deal with syscalls quickly.  */
         [--sp] = ASTAT;
         [--sp] = (R7:6, P5:4);
-        DEBUG_STOP_HWTRACE
+        DEBUG_STOP_HWTRACE(p5, r7)
         r7 = SEQSTAT;           /* reason code is in bit 5:0 */
         r6.l = lo(SEQSTAT_EXCAUSE);
         r6.h = hi(SEQSTAT_EXCAUSE);
@@ -741,6 +691,10 @@ _schedule_and_signal_from_int:
         r0 = [p0];
         sti r0;
 
+        r0 = sp;
+        sp += -12;
+        call _finish_atomic_sections;
+        sp += 12;
         jump.s .Lresume_userspace;
 
 _schedule_and_signal:
@@ -790,14 +744,14 @@ ENDPROC(_init_exception_buff)
 ALIGN
 _extable:
         /* entry for each EXCAUSE[5:0]
-         * This table bmust be in sync with the table in ./kernel/traps.c
+         * This table must be in sync with the table in ./kernel/traps.c
          * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
          */
         .long _ex_syscall;      /* 0x00 - User Defined - Linux Syscall */
         .long _ex_soft_bp       /* 0x01 - User Defined - Software breakpoint */
         .long _ex_trap_c        /* 0x02 - User Defined */
-        .long _ex_trap_c        /* 0x03 - User Defined  - Atomic test and set service */
-        .long _ex_spinlock      /* 0x04 - User Defined */
+        .long _ex_trap_c        /* 0x03 - User Defined - userspace stack overflow */
+        .long _ex_trap_c        /* 0x04 - User Defined */
         .long _ex_trap_c        /* 0x05 - User Defined */
         .long _ex_trap_c        /* 0x06 - User Defined */
         .long _ex_trap_c        /* 0x07 - User Defined */
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 8be548e061bf..203e20709163 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -34,6 +34,7 @@
 #include <linux/linkage.h>
 #include <asm/entry.h>
 #include <asm/asm-offsets.h>
+#include <asm/trace.h>
 
 #include <asm/mach-common/context.S>
 
@@ -170,10 +171,9 @@ ENTRY(_evt_ivhw)
         r7.l = W[p5];
 1:
 #endif
-        p0.l = lo(TBUFCTL);
-        p0.h = hi(TBUFCTL);
-        r0 = 1;
-        [p0] = r0;
+
+        trace_buffer_stop(p0, r0);
+
         r0 = IRQ_HWERR;
         r1 = sp;
 
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 80943bbd37c2..6b9fd03ce835 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -183,7 +183,7 @@ static void bf561_gpio_ack_irq(unsigned int irq)
 {
         u16 gpionr = irq - IRQ_PF0;
 
-        if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
+        if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
                 set_gpio_data(gpionr, 0);
                 SSYNC();
         }
@@ -193,7 +193,7 @@ static void bf561_gpio_mask_ack_irq(unsigned int irq)
 {
         u16 gpionr = irq - IRQ_PF0;
 
-        if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
+        if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
                 set_gpio_data(gpionr, 0);
                 SSYNC();
         }
@@ -222,7 +222,7 @@ static unsigned int bf561_gpio_irq_startup(unsigned int irq)
         if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
 
                 ret = gpio_request(gpionr, NULL);
-                if(ret)
+                if (ret)
                         return ret;
 
         }
@@ -262,7 +262,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
                 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
 
                         ret = gpio_request(gpionr, NULL);
-                        if(ret)
+                        if (ret)
                                 return ret;
 
                 }
@@ -371,6 +371,9 @@ int __init init_arch_irq(void)
         bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
         SSYNC();
 
+        bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
+        bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
+
         local_irq_disable();
 
         init_exception_buff();
@@ -393,7 +396,7 @@ int __init init_arch_irq(void)
         bfin_write_EVT15(evt_system_call);
         CSYNC();
 
-        for (irq = 0; irq < SYS_IRQS; irq++) {
+        for (irq = 0; irq <= SYS_IRQS; irq++) {
                 if (irq <= IRQ_CORETMR)
                         set_irq_chip(irq, &bf561_core_irqchip);
                 else
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 2cfc7d5aec5c..28a878c3577a 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -13,7 +13,7 @@
  *               2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  *               2003 Metrowerks/Motorola
  *               2003 Bas Vermeulen <bas@buyways.nl>
- *               Copyright 2004-2006 Analog Devices Inc.
+ *               Copyright 2004-2007 Analog Devices Inc.
  *
  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  *
@@ -65,9 +65,9 @@ atomic_t num_spurious;
 
 struct ivgx {
         /* irq number for request_irq, available in mach-bf533/irq.h */
-        int irqno;
+        unsigned int irqno;
         /* corresponding bit in the SIC_ISR register */
-        int isrflag;
+        unsigned int isrflag;
 } ivg_table[NR_PERI_INTS];
 
 struct ivg_slice {
@@ -88,17 +88,16 @@ static void __init search_IAR(void)
         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
                 int irqn;
 
-                ivg7_13[ivg].istop = ivg7_13[ivg].ifirst =
-                    &ivg_table[irq_pos];
+                ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
 
                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
                         int iar_shift = (irqn & 7) * 4;
                         if (ivg ==
                             (0xf &
-                             bfin_read32((unsigned long *) SIC_IAR0 +
+                             bfin_read32((unsigned long *)SIC_IAR0 +
                                          (irqn >> 3)) >> iar_shift)) {
                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
-                                ivg_table[irq_pos].isrflag = 1 << irqn;
+                                ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
                                 ivg7_13[ivg].istop++;
                                 irq_pos++;
                         }
@@ -141,15 +140,31 @@ static void bfin_core_unmask_irq(unsigned int irq)
 
 static void bfin_internal_mask_irq(unsigned int irq)
 {
+#ifndef CONFIG_BF54x
         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
                              ~(1 << (irq - (IRQ_CORETMR + 1))));
+#else
+        unsigned mask_bank, mask_bit;
+        mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
+        mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
+        bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
+                             ~(1 << mask_bit));
+#endif
         SSYNC();
 }
 
 static void bfin_internal_unmask_irq(unsigned int irq)
 {
+#ifndef CONFIG_BF54x
         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
                              (1 << (irq - (IRQ_CORETMR + 1))));
+#else
+        unsigned mask_bank, mask_bit;
+        mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
+        mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
+        bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
+                             (1 << mask_bit));
+#endif
         SSYNC();
 }
 
@@ -206,7 +221,7 @@ static struct irq_chip bfin_generic_error_irqchip = {
 };
 
 static void bfin_demux_error_irq(unsigned int int_err_irq,
-                                  struct irq_desc *intb_desc)
+                                 struct irq_desc *intb_desc)
 {
         int irq = 0;
 
@@ -270,8 +285,8 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
                         }
 
                         pr_debug("IRQ %d:"
-                                " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
-                                irq);
+                                 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
+                                 irq);
                 }
         } else
                 printk(KERN_ERR
@@ -279,11 +294,10 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
                        __FUNCTION__, __FILE__, __LINE__);
 
-
 }
 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
 
 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -361,8 +375,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
         }
 
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
-                    IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
-        {
+                    IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
                 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
                         ret = gpio_request(gpionr, NULL);
                         if (ret)
@@ -407,7 +420,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
         return 0;
 }
 
-
 static struct irq_chip bfin_gpio_irqchip = {
         .ack = bfin_gpio_ack_irq,
         .mask = bfin_gpio_mask_irq,
@@ -419,20 +431,20 @@ static struct irq_chip bfin_gpio_irqchip = {
 };
 
 static void bfin_demux_gpio_irq(unsigned int intb_irq,
-                                 struct irq_desc *intb_desc)
+                                struct irq_desc *intb_desc)
 {
         u16 i;
+        struct irq_desc *desc;
 
-        for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=16) {
+        for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
                 int irq = IRQ_PF0 + i;
                 int flag_d = get_gpiop_data(i);
                 int mask =
-                        flag_d & (gpio_enabled[gpio_bank(i)] &
-                              get_gpiop_maska(i));
+                    flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
 
                 while (mask) {
                         if (mask & 1) {
-                                struct irq_desc *desc = irq_desc + irq;
+                                desc = irq_desc + irq;
                                 desc->handle_irq(irq, desc);
                         }
                         irq++;
@@ -441,6 +453,264 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
         }
 }
 
+#else                           /* CONFIG_IRQCHIP_DEMUX_GPIO */
+
+#define NR_PINT_SYS_IRQS        4
+#define NR_PINT_BITS            32
+#define NR_PINTS                160
+#define IRQ_NOT_AVAIL           0xFF
+
+#define PINT_2_BANK(x)          ((x) >> 5)
+#define PINT_2_BIT(x)           ((x) & 0x1F)
+#define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
+
+static unsigned char irq2pint_lut[NR_PINTS];
+static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
+
+struct pin_int_t {
+        unsigned int mask_set;
+        unsigned int mask_clear;
+        unsigned int request;
+        unsigned int assign;
+        unsigned int edge_set;
+        unsigned int edge_clear;
+        unsigned int invert_set;
+        unsigned int invert_clear;
+        unsigned int pinstate;
+        unsigned int latch;
+};
+
+static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
+        (struct pin_int_t *)PINT0_MASK_SET,
+        (struct pin_int_t *)PINT1_MASK_SET,
+        (struct pin_int_t *)PINT2_MASK_SET,
+        (struct pin_int_t *)PINT3_MASK_SET,
+};
+
+unsigned short get_irq_base(u8 bank, u8 bmap)
+{
+
+        u16 irq_base;
+
+        if (bank < 2) {         /*PA-PB */
+                irq_base = IRQ_PA0 + bmap * 16;
+        } else {                /*PC-PJ */
+                irq_base = IRQ_PC0 + bmap * 16;
+        }
+
+        return irq_base;
+
+}
+
+        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
+void init_pint_lut(void)
+{
+        u16 bank, bit, irq_base, bit_pos;
+        u32 pint_assign;
+        u8 bmap;
+
+        memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
+
+                pint_assign = pint[bank]->assign;
+
+                for (bit = 0; bit < NR_PINT_BITS; bit++) {
+
+                        bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
+
+                        irq_base = get_irq_base(bank, bmap);
+
+                        irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
+                        bit_pos = bit + bank * NR_PINT_BITS;
+
+                        pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
+                        irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
+
+                }
+
+        }
+
+}
+
+static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
+
+static void bfin_gpio_ack_irq(unsigned int irq)
+{
+        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+
+        pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
+        SSYNC();
+}
+
+static void bfin_gpio_mask_ack_irq(unsigned int irq)
+{
+        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 pintbit = PINT_BIT(pint_val);
+        u8 bank = PINT_2_BANK(pint_val);
+
+        pint[bank]->request = pintbit;
+        pint[bank]->mask_clear = pintbit;
+        SSYNC();
+}
+
+static void bfin_gpio_mask_irq(unsigned int irq)
+{
+        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+
+        pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
+        SSYNC();
+}
+
+static void bfin_gpio_unmask_irq(unsigned int irq)
+{
+        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 pintbit = PINT_BIT(pint_val);
+        u8 bank = PINT_2_BANK(pint_val);
+
+        pint[bank]->request = pintbit;
+        pint[bank]->mask_set = pintbit;
+        SSYNC();
+}
+
+static unsigned int bfin_gpio_irq_startup(unsigned int irq)
+{
+        unsigned int ret;
+        u16 gpionr = irq - IRQ_PA0;
+        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+
+        if (pint_val == IRQ_NOT_AVAIL)
+                return -ENODEV;
+
+        if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
+                ret = gpio_request(gpionr, NULL);
+                if (ret)
+                        return ret;
+        }
+
+        gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
+        bfin_gpio_unmask_irq(irq);
+
+        return ret;
+}
+
+static void bfin_gpio_irq_shutdown(unsigned int irq)
+{
+        bfin_gpio_mask_irq(irq);
+        gpio_free(irq - IRQ_PA0);
+        gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
+}
+
+static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+
+        unsigned int ret;
+        u16 gpionr = irq - IRQ_PA0;
+        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 pintbit = PINT_BIT(pint_val);
+        u8 bank = PINT_2_BANK(pint_val);
+
+        if (pint_val == IRQ_NOT_AVAIL)
+                return -ENODEV;
+
+        if (type == IRQ_TYPE_PROBE) {
+                /* only probe unenabled GPIO interrupt lines */
+                if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
+                        return 0;
+                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        }
+
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
+                    IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
+                if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
+                        ret = gpio_request(gpionr, NULL);
+                        if (ret)
+                                return ret;
+                }
+
+                gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
+        } else {
+                gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
+                return 0;
+        }
+
+        gpio_direction_input(gpionr);
+
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+                pint[bank]->edge_set = pintbit;
+        } else {
+                pint[bank]->edge_clear = pintbit;
+        }
+
+        if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
+                pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
+        else
+                pint[bank]->invert_set = pintbit;       /* high or rising edge denoted by zero */
+
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                pint[bank]->invert_set = pintbit;
+        else
+                pint[bank]->invert_set = pintbit;
+
+        SSYNC();
+
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                set_irq_handler(irq, handle_edge_irq);
+        else
+                set_irq_handler(irq, handle_level_irq);
+
+        return 0;
+}
+
+static struct irq_chip bfin_gpio_irqchip = {
+        .ack = bfin_gpio_ack_irq,
+        .mask = bfin_gpio_mask_irq,
+        .mask_ack = bfin_gpio_mask_ack_irq,
+        .unmask = bfin_gpio_unmask_irq,
+        .set_type = bfin_gpio_irq_type,
+        .startup = bfin_gpio_irq_startup,
+        .shutdown = bfin_gpio_irq_shutdown
+};
+
+static void bfin_demux_gpio_irq(unsigned int intb_irq,
+                                struct irq_desc *intb_desc)
+{
+        u8 bank, pint_val;
+        u32 request, irq;
+        struct irq_desc *desc;
+
+        switch (intb_irq) {
+        case IRQ_PINT0:
+                bank = 0;
+                break;
+        case IRQ_PINT2:
+                bank = 2;
+                break;
+        case IRQ_PINT3:
+                bank = 3;
+                break;
+        case IRQ_PINT1:
+                bank = 1;
+                break;
+        default:
+                return;
+        }
+
+        pint_val = bank * NR_PINT_BITS;
+
+        request = pint[bank]->request;
+
+        while (request) {
+                if (request & 1) {
+                        irq = pint2irq_lut[pint_val] + SYS_IRQS;
+                        desc = irq_desc + irq;
+                        desc->handle_irq(irq, desc);
+                }
+                pint_val++;
+                request >>= 1;
+        }
+
+}
 #endif                          /* CONFIG_IRQCHIP_DEMUX_GPIO */
 
 /*
@@ -452,7 +722,18 @@ int __init init_arch_irq(void)
         int irq;
         unsigned long ilat = 0;
         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
+#ifdef CONFIG_BF54x
+        bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
+        bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
+        bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
+        bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
+        bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+        bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+#else
         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
+        bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+#endif
+
         SSYNC();
 
         local_irq_disable();
@@ -475,7 +756,18 @@ int __init init_arch_irq(void)
         bfin_write_EVT15(evt_system_call);
         CSYNC();
 
-        for (irq = 0; irq < SYS_IRQS; irq++) {
+#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
+#ifdef CONFIG_PINTx_REASSIGN
+        pint[0]->assign = CONFIG_PINT0_ASSIGN;
+        pint[1]->assign = CONFIG_PINT1_ASSIGN;
+        pint[2]->assign = CONFIG_PINT2_ASSIGN;
+        pint[3]->assign = CONFIG_PINT3_ASSIGN;
+#endif
+        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
+        init_pint_lut();
+#endif
+
+        for (irq = 0; irq <= SYS_IRQS; irq++) {
                 if (irq <= IRQ_CORETMR)
                         set_irq_chip(irq, &bfin_core_irqchip);
                 else
@@ -484,20 +776,42 @@ int __init init_arch_irq(void)
                 if (irq != IRQ_GENERIC_ERROR) {
 #endif
 
+                        switch (irq) {
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
-                        if ((irq != IRQ_PROG_INTA) /*PORT F & G MASK_A Interrupt*/
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
-                                && (irq != IRQ_MAC_RX) /*PORT H MASK_A Interrupt*/
-# endif
-                            ) {
+#ifndef CONFIG_BF54x
+                        case IRQ_PROG_INTA:
+                                set_irq_chained_handler(irq,
+                                                        bfin_demux_gpio_irq);
+                                break;
+#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
+                        case IRQ_MAC_RX:
+                                set_irq_chained_handler(irq,
+                                                        bfin_demux_gpio_irq);
+                                break;
 #endif
-                                set_irq_handler(irq, handle_simple_irq);
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
-                        } else {
+#else
+                        case IRQ_PINT0:
                                 set_irq_chained_handler(irq,
                                                         bfin_demux_gpio_irq);
-                        }
+                                break;
+                        case IRQ_PINT1:
+                                set_irq_chained_handler(irq,
+                                                        bfin_demux_gpio_irq);
+                                break;
+                        case IRQ_PINT2:
+                                set_irq_chained_handler(irq,
+                                                        bfin_demux_gpio_irq);
+                                break;
+                        case IRQ_PINT3:
+                                set_irq_chained_handler(irq,
+                                                        bfin_demux_gpio_irq);
+                                break;
+#endif                          /*CONFIG_BF54x */
 #endif
+                        default:
+                                set_irq_handler(irq, handle_simple_irq);
+                                break;
+                        }
 
 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
                 } else {
@@ -513,7 +827,11 @@ int __init init_arch_irq(void)
 #endif
 
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+#ifndef CONFIG_BF54x
         for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
+#else
+        for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
+#endif
                 set_irq_chip(irq, &bfin_gpio_irqchip);
                 /* if configured as edge, then will be changed to do_edge_IRQ */
                 set_irq_handler(irq, handle_level_irq);
@@ -526,8 +844,7 @@ int __init init_arch_irq(void)
         bfin_write_ILAT(ilat);
         CSYNC();
 
-        printk(KERN_INFO
-               "Configuring Blackfin Priority Driven Interrupts\n");
+        printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
         /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
          * local_irq_enable()
          */
@@ -538,14 +855,13 @@ int __init init_arch_irq(void)
         /* Enable interrupts IVG7-15 */
         irq_flags = irq_flags | IMASK_IVG15 |
             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
-            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 |
-            IMASK_IVGHW;
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
         return 0;
 }
 
 #ifdef CONFIG_DO_IRQ_L1
-void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text));
+void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text));
 #endif
 
 void do_irq(int vec, struct pt_regs *fp)
@@ -555,9 +871,25 @@ void do_irq(int vec, struct pt_regs *fp)
         } else {
                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
-                unsigned long sic_status;
+#ifdef CONFIG_BF54x
+                unsigned long sic_status[3];
 
                 SSYNC();
+                sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
+                sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
+                sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
+
+                for (;; ivg++) {
+                        if (ivg >= ivg_stop) {
+                                atomic_inc(&num_spurious);
+                                return;
+                        }
+                        if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
+                                break;
+                }
+#else
+                unsigned long sic_status;
+                SSYNC();
                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
 
                 for (;; ivg++) {
@@ -567,6 +899,7 @@ void do_irq(int vec, struct pt_regs *fp)
                         } else if (sic_status & ivg->isrflag)
                                 break;
                 }
+#endif
                 vec = ivg->irqno;
         }
         asm_do_IRQ(vec, fp);
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 150ef5d088dc..1772d8d2c1a7 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -35,10 +35,10 @@
 #include <linux/pm.h>
 #include <linux/sched.h>
 #include <linux/proc_fs.h>
+#include <linux/io.h>
+#include <linux/irq.h>
 
-#include <asm/io.h>
 #include <asm/dpmc.h>
-#include <asm/irq.h>
 #include <asm/gpio.h>
 
 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/blackfin_sram.c
index 68107924639e..16c6169ed01b 100644
--- a/arch/blackfin/mm/blackfin_sram.c
+++ b/arch/blackfin/mm/blackfin_sram.c
@@ -87,7 +87,7 @@ void __init l1sram_init(void)
                L1_SCRATCH_LENGTH >> 10);
 
         memset(&l1_ssram, 0x00, sizeof(l1_ssram));
-        l1_ssram[0].paddr = (void*)L1_SCRATCH_START;
+        l1_ssram[0].paddr = (void *)L1_SCRATCH_START;
         l1_ssram[0].size = L1_SCRATCH_LENGTH;
         l1_ssram[0].flag = SRAM_SLT_FREE;
 
@@ -126,7 +126,7 @@ void __init l1_inst_sram_init(void)
 {
 #if L1_CODE_LENGTH != 0
         memset(&l1_inst_sram, 0x00, sizeof(l1_inst_sram));
-        l1_inst_sram[0].paddr = (void*)L1_CODE_START + (_etext_l1 - _stext_l1);
+        l1_inst_sram[0].paddr = (void *)L1_CODE_START + (_etext_l1 - _stext_l1);
         l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
         l1_inst_sram[0].flag = SRAM_SLT_FREE;
 
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 570356dbe028..68459cc052a1 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -29,8 +29,8 @@
 
 #include <linux/swap.h>
 #include <linux/bootmem.h>
+#include <linux/uaccess.h>
 #include <asm/bfin-global.h>
-#include <asm/uaccess.h>
 #include <asm/l1layout.h>
 #include "blackfin_sram.h"
 
@@ -168,42 +168,31 @@ void __init mem_init(void)
         }
 }
 
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
+static __init void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 {
-        int pages = 0;
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
+        unsigned long addr;
+        /* next to check that the page we free is not a partial page */
+        for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(addr));
+                init_page_count(virt_to_page(addr));
+                free_page(addr);
                 totalram_pages++;
-                pages++;
         }
-        printk(KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages);
+        printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+void __init free_initrd_mem(unsigned long start, unsigned long end)
+{
+        free_init_pages("initrd memory", start, end);
 }
 #endif
 
 void __init free_initmem(void)
 {
 #ifdef CONFIG_RAMKERNEL
-        unsigned long addr;
-        /*
-         *      the following code should be cool even if these sections
-         *      are not page aligned.
-         */
-        addr = PAGE_ALIGN((unsigned long)(__init_begin));
-        /* next to check that the page we free is not a partial page */
-        for (; addr + PAGE_SIZE < (unsigned long)(__init_end);
-             addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_NOTICE
-               "Freeing unused kernel memory: %ldk freed (0x%x - 0x%x)\n",
-               (addr - PAGE_ALIGN((long)__init_begin)) >> 10,
-               (int)(PAGE_ALIGN((unsigned long)(__init_begin))),
-               (int)(addr - PAGE_SIZE));
+        free_init_pages("unused kernel memory",
+                        (unsigned long)(&__init_begin),
+                        (unsigned long)(&__init_end));
 #endif
 }
diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c
index 009a1700c854..cb8b8d5af34f 100644
--- a/arch/blackfin/oprofile/common.c
+++ b/arch/blackfin/oprofile/common.c
@@ -33,12 +33,12 @@
 #include <linux/smp.h>
 #include <linux/errno.h>
 #include <linux/mutex.h>
+#include <linux/ptrace.h>
+#include <linux/irq.h>
+#include <linux/io.h>
 
-#include <asm/ptrace.h>
 #include <asm/system.h>
 #include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/io.h>
 
 #include "op_blackfin.h"
 
diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c
index b7a20a006b49..872dffe33623 100644
--- a/arch/blackfin/oprofile/op_model_bf533.c
+++ b/arch/blackfin/oprofile/op_model_bf533.c
@@ -32,12 +32,12 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
-#include <asm/ptrace.h>
+#include <linux/ptrace.h>
+#include <linux/irq.h>
+#include <linux/io.h>
 #include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/io.h>
 
 #include "op_blackfin.h"
 
diff --git a/arch/blackfin/oprofile/timer_int.c b/arch/blackfin/oprofile/timer_int.c
index 8fba16c846c9..6c6f8606af4c 100644
--- a/arch/blackfin/oprofile/timer_int.c
+++ b/arch/blackfin/oprofile/timer_int.c
@@ -31,8 +31,7 @@
 #include <linux/smp.h>
 #include <linux/irq.h>
 #include <linux/oprofile.h>
-
-#include <asm/ptrace.h>
+#include <linux/ptrace.h>
 
 static void enable_sys_timer0()
 {
diff --git a/arch/i386/Kconfig.cpu b/arch/i386/Kconfig.cpu
index 5c95ceb7f122..9cbe76c3aa35 100644
--- a/arch/i386/Kconfig.cpu
+++ b/arch/i386/Kconfig.cpu
@@ -344,8 +344,8 @@ config X86_CMOV
         depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7)
         default y
 
-config X86_MINIMUM_CPU_MODEL
+config X86_MINIMUM_CPU_FAMILY
         int
-        default "4" if X86_XADD || X86_CMPXCHG || X86_BSWAP
-        default "0"
+        default "4" if X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK
+        default "3"
 
diff --git a/arch/i386/boot/Makefile b/arch/i386/boot/Makefile
index bfbc32098a4a..08678a0a3d19 100644
--- a/arch/i386/boot/Makefile
+++ b/arch/i386/boot/Makefile
@@ -25,27 +25,56 @@ SVGA_MODE := -DSVGA_MODE=NORMAL_VGA
 
 #RAMDISK := -DRAMDISK=512
 
-targets         := vmlinux.bin bootsect bootsect.o \
-                   setup setup.o zImage bzImage
+targets         := vmlinux.bin setup.bin setup.elf zImage bzImage
 subdir-         := compressed
 
+setup-y         += a20.o apm.o cmdline.o copy.o cpu.o cpucheck.o edd.o
+setup-y         += header.o main.o mca.o memory.o pm.o pmjump.o
+setup-y         += printf.o string.o tty.o video.o version.o voyager.o
+
+# The link order of the video-*.o modules can matter.  In particular,
+# video-vga.o *must* be listed first, followed by video-vesa.o.
+# Hardware-specific drivers should follow in the order they should be
+# probed, and video-bios.o should typically be last.
+setup-y         += video-vga.o
+setup-y         += video-vesa.o
+setup-y         += video-bios.o
+
 hostprogs-y     := tools/build
 
 HOSTCFLAGS_build.o := $(LINUXINCLUDE)
 
 # ---------------------------------------------------------------------------
 
+# How to compile the 16-bit code.  Note we always compile for -march=i386,
+# that way we can complain to the user if the CPU is insufficient.
+cflags-i386   := 
+cflags-x86_64 := -m32
+CFLAGS          := $(LINUXINCLUDE) -g -Os -D_SETUP -D__KERNEL__ \
+                   $(cflags-$(ARCH)) \
+                   -Wall -Wstrict-prototypes \
+                   -march=i386 -mregparm=3 \
+                   -include $(srctree)/$(src)/code16gcc.h \
+                   -fno-strict-aliasing -fomit-frame-pointer \
+                   $(call cc-option, -ffreestanding) \
+                   $(call cc-option, -fno-toplevel-reorder,\
+                        $(call cc-option, -fno-unit-at-a-time)) \
+                   $(call cc-option, -fno-stack-protector) \
+                   $(call cc-option, -mpreferred-stack-boundary=2)
+AFLAGS          := $(CFLAGS) -D__ASSEMBLY__
+
 $(obj)/zImage:  IMAGE_OFFSET := 0x1000
 $(obj)/zImage:  EXTRA_AFLAGS := $(SVGA_MODE) $(RAMDISK)
 $(obj)/bzImage: IMAGE_OFFSET := 0x100000
+$(obj)/bzImage: EXTRA_CFLAGS := -D__BIG_KERNEL__
 $(obj)/bzImage: EXTRA_AFLAGS := $(SVGA_MODE) $(RAMDISK) -D__BIG_KERNEL__
 $(obj)/bzImage: BUILDFLAGS   := -b
 
 quiet_cmd_image = BUILD   $@
-cmd_image = $(obj)/tools/build $(BUILDFLAGS) $(obj)/bootsect $(obj)/setup \
+cmd_image = $(obj)/tools/build $(BUILDFLAGS) $(obj)/setup.bin \
             $(obj)/vmlinux.bin $(ROOT_DEV) > $@
 
-$(obj)/zImage $(obj)/bzImage: $(obj)/bootsect $(obj)/setup \
+$(obj)/zImage $(obj)/bzImage: $(obj)/setup.bin \
                               $(obj)/vmlinux.bin $(obj)/tools/build FORCE
         $(call if_changed,image)
         @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
@@ -53,12 +82,17 @@ $(obj)/zImage $(obj)/bzImage: $(obj)/bootsect $(obj)/setup \
 $(obj)/vmlinux.bin: $(obj)/compressed/vmlinux FORCE
         $(call if_changed,objcopy)
 
-LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
-LDFLAGS_setup    := -Ttext 0x0 -s --oformat binary -e begtext
+SETUP_OBJS = $(addprefix $(obj)/,$(setup-y))
 
-$(obj)/setup $(obj)/bootsect: %: %.o FORCE
+LDFLAGS_setup.elf       := -T
+$(obj)/setup.elf: $(src)/setup.ld $(SETUP_OBJS) FORCE
         $(call if_changed,ld)
 
+OBJCOPYFLAGS_setup.bin  := -O binary
+
+$(obj)/setup.bin: $(obj)/setup.elf FORCE
+        $(call if_changed,objcopy)
+
 $(obj)/compressed/vmlinux: FORCE
         $(Q)$(MAKE) $(build)=$(obj)/compressed IMAGE_OFFSET=$(IMAGE_OFFSET) $@
 
diff --git a/arch/i386/boot/a20.c b/arch/i386/boot/a20.c
new file mode 100644
index 000000000000..31348d054fca
--- /dev/null
+++ b/arch/i386/boot/a20.c
@@ -0,0 +1,161 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/a20.c
+ *
+ * Enable A20 gate (return -1 on failure)
+ */
+
+#include "boot.h"
+
+#define MAX_8042_LOOPS  100000
+
+static int empty_8042(void)
+{
+        u8 status;
+        int loops = MAX_8042_LOOPS;
+
+        while (loops--) {
+                io_delay();
+
+                status = inb(0x64);
+                if (status & 1) {
+                        /* Read and discard input data */
+                        io_delay();
+                        (void)inb(0x60);
+                } else if (!(status & 2)) {
+                        /* Buffers empty, finished! */
+                        return 0;
+                }
+        }
+
+        return -1;
+}
+
+/* Returns nonzero if the A20 line is enabled.  The memory address
+   used as a test is the int $0x80 vector, which should be safe. */
+
+#define A20_TEST_ADDR   (4*0x80)
+#define A20_TEST_SHORT  32
+#define A20_TEST_LONG   2097152 /* 2^21 */
+
+static int a20_test(int loops)
+{
+        int ok = 0;
+        int saved, ctr;
+
+        set_fs(0x0000);
+        set_gs(0xffff);
+
+        saved = ctr = rdfs32(A20_TEST_ADDR);
+
+        while (loops--) {
+                wrfs32(++ctr, A20_TEST_ADDR);
+                io_delay();     /* Serialize and make delay constant */
+                ok = rdgs32(A20_TEST_ADDR+0x10) ^ ctr;
+                if (ok)
+                        break;
+        }
+
+        wrfs32(saved, A20_TEST_ADDR);
+        return ok;
+}
+
+/* Quick test to see if A20 is already enabled */
+static int a20_test_short(void)
+{
+        return a20_test(A20_TEST_SHORT);
+}
+
+/* Longer test that actually waits for A20 to come on line; this
+   is useful when dealing with the KBC or other slow external circuitry. */
+static int a20_test_long(void)
+{
+        return a20_test(A20_TEST_LONG);
+}
+
+static void enable_a20_bios(void)
+{
+        asm volatile("pushfl; int $0x15; popfl"
+                     : : "a" ((u16)0x2401));
+}
+
+static void enable_a20_kbc(void)
+{
+        empty_8042();
+
+        outb(0xd1, 0x64);       /* Command write */
+        empty_8042();
+
+        outb(0xdf, 0x60);       /* A20 on */
+        empty_8042();
+}
+
+static void enable_a20_fast(void)
+{
+        u8 port_a;
+
+        port_a = inb(0x92);     /* Configuration port A */
+        port_a |=  0x02;        /* Enable A20 */
+        port_a &= ~0x01;        /* Do not reset machine */
+        outb(port_a, 0x92);
+}
+
+/*
+ * Actual routine to enable A20; return 0 on ok, -1 on failure
+ */
+
+#define A20_ENABLE_LOOPS 255    /* Number of times to try */
+
+int enable_a20(void)
+{
+        int loops = A20_ENABLE_LOOPS;
+
+#if defined(CONFIG_X86_ELAN)
+        /* Elan croaks if we try to touch the KBC */
+        enable_a20_fast();
+        while (!a20_test_long())
+                ;
+        return 0;
+#elif defined(CONFIG_X86_VOYAGER)
+        /* On Voyager, a20_test() is unsafe? */
+        enable_a20_kbc();
+        return 0;
+#else
+        while (loops--) {
+                /* First, check to see if A20 is already enabled
+                   (legacy free, etc.) */
+                if (a20_test_short())
+                        return 0;
+
+                /* Next, try the BIOS (INT 0x15, AX=0x2401) */
+                enable_a20_bios();
+                if (a20_test_short())
+                        return 0;
+
+                /* Try enabling A20 through the keyboard controller */
+                empty_8042();
+                if (a20_test_short())
+                        return 0; /* BIOS worked, but with delayed reaction */
+
+                enable_a20_kbc();
+                if (a20_test_long())
+                        return 0;
+
+                /* Finally, try enabling the "fast A20 gate" */
+                enable_a20_fast();
+                if (a20_test_long())
+                        return 0;
+        }
+
+        return -1;
+#endif
+}
diff --git a/arch/i386/boot/apm.c b/arch/i386/boot/apm.c
new file mode 100644
index 000000000000..a34087c370c0
--- /dev/null
+++ b/arch/i386/boot/apm.c
@@ -0,0 +1,97 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   Original APM BIOS checking by Stephen Rothwell, May 1994
+ *   (sfr@canb.auug.org.au)
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/apm.c
+ *
+ * Get APM BIOS information
+ */
+
+#include "boot.h"
+
+#if defined(CONFIG_APM) || defined(CONFIG_APM_MODULE)
+
+int query_apm_bios(void)
+{
+        u16 ax, bx, cx, dx, di;
+        u32 ebx, esi;
+        u8 err;
+
+        /* APM BIOS installation check */
+        ax = 0x5300;
+        bx = cx = 0;
+        asm volatile("pushl %%ebp ; int $0x15 ; popl %%ebp ; setc %0"
+                     : "=d" (err), "+a" (ax), "+b" (bx), "+c" (cx)
+                     : : "esi", "edi");
+
+        if (err)
+                return -1;              /* No APM BIOS */
+
+        if (bx != 0x504d)       /* "PM" signature */
+                return -1;
+
+        if (cx & 0x02)          /* 32 bits supported? */
+                return -1;
+
+        /* Disconnect first, just in case */
+        ax = 0x5304;
+        asm volatile("pushl %%ebp ; int $0x15 ; popl %%ebp"
+                     : "+a" (ax)
+                     : : "ebx", "ecx", "edx", "esi", "edi");
+
+        /* Paranoia */
+        ebx = esi = 0;
+        cx = dx = di = 0;
+
+        /* 32-bit connect */
+        asm volatile("pushl %%ebp ; int $0x15 ; popl %%ebp ; setc %6"
+                     : "=a" (ax), "+b" (ebx), "+c" (cx), "+d" (dx),
+                       "+S" (esi), "+D" (di), "=m" (err)
+                     : "a" (0x5303));
+
+        boot_params.apm_bios_info.cseg = ax;
+        boot_params.apm_bios_info.offset = ebx;
+        boot_params.apm_bios_info.cseg_16 = cx;
+        boot_params.apm_bios_info.dseg = dx;
+        boot_params.apm_bios_info.cseg_len = (u16)esi;
+        boot_params.apm_bios_info.cseg_16_len = esi >> 16;
+        boot_params.apm_bios_info.dseg_len = di;
+
+        if (err)
+                return -1;
+
+        /* Redo the installation check as the 32-bit connect;
+           some BIOSes return different flags this way... */
+
+        ax = 0x5300;
+        bx = cx = 0;
+        asm volatile("pushl %%ebp ; int $0x15 ; popl %%ebp ; setc %0"
+                     : "=d" (err), "+a" (ax), "+b" (bx), "+c" (cx)
+                     : : "esi", "edi");
+
+        if (err || bx != 0x504d) {
+                /* Failure with 32-bit connect, try to disconect and ignore */
+                ax = 0x5304;
+                bx = 0;
+                asm volatile("pushl %%ebp ; int $0x15 ; popl %%ebp"
+                             : "+a" (ax), "+b" (bx)
+                             : : "ecx", "edx", "esi", "edi");
+                return -1;
+        }
+
+        boot_params.apm_bios_info.version = ax;
+        boot_params.apm_bios_info.flags = cx;
+        return 0;
+}
+
+#endif
diff --git a/arch/i386/boot/bitops.h b/arch/i386/boot/bitops.h
new file mode 100644
index 000000000000..8dcc8dc7db88
--- /dev/null
+++ b/arch/i386/boot/bitops.h
@@ -0,0 +1,45 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/bitops.h
+ *
+ * Very simple bitops for the boot code.
+ */
+
+#ifndef BOOT_BITOPS_H
+#define BOOT_BITOPS_H
+#define _LINUX_BITOPS_H         /* Inhibit inclusion of <linux/bitops.h> */
+
+static inline int constant_test_bit(int nr, const void *addr)
+{
+        const u32 *p = (const u32 *)addr;
+        return ((1UL << (nr & 31)) & (p[nr >> 5])) != 0;
+}
+static inline int variable_test_bit(int nr, const void *addr)
+{
+        u8 v;
+        const u32 *p = (const u32 *)addr;
+
+        asm("btl %2,%1; setc %0" : "=qm" (v) : "m" (*p), "Ir" (nr));
+        return v;
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ constant_test_bit((nr),(addr)) : \
+ variable_test_bit((nr),(addr)))
+
+static inline void set_bit(int nr, void *addr)
+{
+        asm("btsl %1,%0" : "+m" (*(u32 *)addr) : "Ir" (nr));
+}
+
+#endif /* BOOT_BITOPS_H */
diff --git a/arch/i386/boot/boot.h b/arch/i386/boot/boot.h
new file mode 100644
index 000000000000..0329c4fe4f88
--- /dev/null
+++ b/arch/i386/boot/boot.h
@@ -0,0 +1,296 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/boot.h
+ *
+ * Header file for the real-mode kernel code
+ */
+
+#ifndef BOOT_BOOT_H
+#define BOOT_BOOT_H
+
+#ifndef __ASSEMBLY__
+
+#include <stdarg.h>
+#include <linux/types.h>
+#include <linux/edd.h>
+#include <asm/boot.h>
+#include <asm/bootparam.h>
+
+/* Useful macros */
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+extern struct setup_header hdr;
+extern struct boot_params boot_params;
+
+/* Basic port I/O */
+static inline void outb(u8 v, u16 port)
+{
+        asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
+}
+static inline u8 inb(u16 port)
+{
+        u8 v;
+        asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
+        return v;
+}
+
+static inline void outw(u16 v, u16 port)
+{
+        asm volatile("outw %0,%1" : : "a" (v), "dN" (port));
+}
+static inline u16 inw(u16 port)
+{
+        u16 v;
+        asm volatile("inw %1,%0" : "=a" (v) : "dN" (port));
+        return v;
+}
+
+static inline void outl(u32 v, u16 port)
+{
+        asm volatile("outl %0,%1" : : "a" (v), "dn" (port));
+}
+static inline u32 inl(u32 port)
+{
+        u32 v;
+        asm volatile("inl %1,%0" : "=a" (v) : "dN" (port));
+        return v;
+}
+
+static inline void io_delay(void)
+{
+        const u16 DELAY_PORT = 0x80;
+        asm volatile("outb %%al,%0" : : "dN" (DELAY_PORT));
+}
+
+/* These functions are used to reference data in other segments. */
+
+static inline u16 ds(void)
+{
+        u16 seg;
+        asm("movw %%ds,%0" : "=rm" (seg));
+        return seg;
+}
+
+static inline void set_fs(u16 seg)
+{
+        asm volatile("movw %0,%%fs" : : "rm" (seg));
+}
+static inline u16 fs(void)
+{
+        u16 seg;
+        asm("movw %%fs,%0" : "=rm" (seg));
+        return seg;
+}
+
+static inline void set_gs(u16 seg)
+{
+        asm volatile("movw %0,%%gs" : : "rm" (seg));
+}
+static inline u16 gs(void)
+{
+        u16 seg;
+        asm("movw %%gs,%0" : "=rm" (seg));
+        return seg;
+}
+
+typedef unsigned int addr_t;
+
+static inline u8 rdfs8(addr_t addr)
+{
+        u8 v;
+        asm("movb %%fs:%1,%0" : "=r" (v) : "m" (*(u8 *)addr));
+        return v;
+}
+static inline u16 rdfs16(addr_t addr)
+{
+        u16 v;
+        asm("movw %%fs:%1,%0" : "=r" (v) : "m" (*(u16 *)addr));
+        return v;
+}
+static inline u32 rdfs32(addr_t addr)
+{
+        u32 v;
+        asm("movl %%fs:%1,%0" : "=r" (v) : "m" (*(u32 *)addr));
+        return v;
+}
+
+static inline void wrfs8(u8 v, addr_t addr)
+{
+        asm volatile("movb %1,%%fs:%0" : "+m" (*(u8 *)addr) : "r" (v));
+}
+static inline void wrfs16(u16 v, addr_t addr)
+{
+        asm volatile("movw %1,%%fs:%0" : "+m" (*(u16 *)addr) : "r" (v));
+}
+static inline void wrfs32(u32 v, addr_t addr)
+{
+        asm volatile("movl %1,%%fs:%0" : "+m" (*(u32 *)addr) : "r" (v));
+}
+
+static inline u8 rdgs8(addr_t addr)
+{
+        u8 v;
+        asm("movb %%gs:%1,%0" : "=r" (v) : "m" (*(u8 *)addr));
+        return v;
+}
+static inline u16 rdgs16(addr_t addr)
+{
+        u16 v;
+        asm("movw %%gs:%1,%0" : "=r" (v) : "m" (*(u16 *)addr));
+        return v;
+}
+static inline u32 rdgs32(addr_t addr)
+{
+        u32 v;
+        asm("movl %%gs:%1,%0" : "=r" (v) : "m" (*(u32 *)addr));
+        return v;
+}
+
+static inline void wrgs8(u8 v, addr_t addr)
+{
+        asm volatile("movb %1,%%gs:%0" : "+m" (*(u8 *)addr) : "r" (v));
+}
+static inline void wrgs16(u16 v, addr_t addr)
+{
+        asm volatile("movw %1,%%gs:%0" : "+m" (*(u16 *)addr) : "r" (v));
+}
+static inline void wrgs32(u32 v, addr_t addr)
+{
+        asm volatile("movl %1,%%gs:%0" : "+m" (*(u32 *)addr) : "r" (v));
+}
+
+/* Note: these only return true/false, not a signed return value! */
+static inline int memcmp(const void *s1, const void *s2, size_t len)
+{
+        u8 diff;
+        asm("repe; cmpsb; setnz %0"
+            : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
+        return diff;
+}
+
+static inline int memcmp_fs(const void *s1, addr_t s2, size_t len)
+{
+        u8 diff;
+        asm("fs; repe; cmpsb; setnz %0"
+            : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
+        return diff;
+}
+static inline int memcmp_gs(const void *s1, addr_t s2, size_t len)
+{
+        u8 diff;
+        asm("gs; repe; cmpsb; setnz %0"
+            : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
+        return diff;
+}
+
+static inline int isdigit(int ch)
+{
+        return (ch >= '0') && (ch <= '9');
+}
+
+/* Heap -- available for dynamic lists. */
+#define STACK_SIZE      512     /* Minimum number of bytes for stack */
+
+extern char _end[];
+extern char *HEAP;
+extern char *heap_end;
+#define RESET_HEAP() ((void *)( HEAP = _end ))
+static inline char *__get_heap(size_t s, size_t a, size_t n)
+{
+        char *tmp;
+
+        HEAP = (char *)(((size_t)HEAP+(a-1)) & ~(a-1));
+        tmp = HEAP;
+        HEAP += s*n;
+        return tmp;
+}
+#define GET_HEAP(type, n) \
+        ((type *)__get_heap(sizeof(type),__alignof__(type),(n)))
+
+static inline int heap_free(void)
+{
+        return heap_end-HEAP;
+}
+
+/* copy.S */
+
+void copy_to_fs(addr_t dst, void *src, size_t len);
+void *copy_from_fs(void *dst, addr_t src, size_t len);
+void copy_to_gs(addr_t dst, void *src, size_t len);
+void *copy_from_gs(void *dst, addr_t src, size_t len);
+void *memcpy(void *dst, void *src, size_t len);
+void *memset(void *dst, int c, size_t len);
+
+#define memcpy(d,s,l) __builtin_memcpy(d,s,l)
+#define memset(d,c,l) __builtin_memset(d,c,l)
+
+/* a20.c */
+int enable_a20(void);
+
+/* apm.c */
+int query_apm_bios(void);
+
+/* cmdline.c */
+int cmdline_find_option(const char *option, char *buffer, int bufsize);
+
+/* cpu.c, cpucheck.c */
+int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr);
+int validate_cpu(void);
+
+/* edd.c */
+void query_edd(void);
+
+/* header.S */
+void __attribute__((noreturn)) die(void);
+
+/* mca.c */
+int query_mca(void);
+
+/* memory.c */
+int detect_memory(void);
+
+/* pm.c */
+void __attribute__((noreturn)) go_to_protected_mode(void);
+
+/* pmjump.S */
+void __attribute__((noreturn))
+        protected_mode_jump(u32 entrypoint, u32 bootparams);
+
+/* printf.c */
+int sprintf(char *buf, const char *fmt, ...);
+int vsprintf(char *buf, const char *fmt, va_list args);
+int printf(const char *fmt, ...);
+
+/* string.c */
+int strcmp(const char *str1, const char *str2);
+size_t strnlen(const char *s, size_t maxlen);
+unsigned int atou(const char *s);
+
+/* tty.c */
+void puts(const char *);
+void putchar(int);
+int getchar(void);
+void kbd_flush(void);
+int getchar_timeout(void);
+
+/* video.c */
+void set_video(void);
+
+/* video-vesa.c */
+void vesa_store_edid(void);
+
+/* voyager.c */
+int query_voyager(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* BOOT_BOOT_H */
diff --git a/arch/i386/boot/bootsect.S b/arch/i386/boot/bootsect.S
deleted file mode 100644
index 011b7a4993d4..000000000000
--- a/arch/i386/boot/bootsect.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *      bootsect.S              Copyright (C) 1991, 1992 Linus Torvalds
- *
- *      modified by Drew Eckhardt
- *      modified by Bruce Evans (bde)
- *      modified by Chris Noe (May 1999) (as86 -> gas)
- *      gutted by H. Peter Anvin (Jan 2003)
- *
- * BIG FAT NOTE: We're in real mode using 64k segments.  Therefore segment
- * addresses must be multiplied by 16 to obtain their respective linear
- * addresses. To avoid confusion, linear addresses are written using leading
- * hex while segment addresses are written as segment:offset.
- *
- */
-
-#include <asm/boot.h>
-
-SETUPSECTS      = 4                     /* default nr of setup-sectors */
-BOOTSEG         = 0x07C0                /* original address of boot-sector */
-INITSEG         = DEF_INITSEG           /* we move boot here - out of the way */
-SETUPSEG        = DEF_SETUPSEG          /* setup starts here */
-SYSSEG          = DEF_SYSSEG            /* system loaded at 0x10000 (65536) */
-SYSSIZE         = DEF_SYSSIZE           /* system size: # of 16-byte clicks */
-                                        /* to be loaded */
-ROOT_DEV        = 0                     /* ROOT_DEV is now written by "build" */
-SWAP_DEV        = 0                     /* SWAP_DEV is now written by "build" */
-
-#ifndef SVGA_MODE
-#define SVGA_MODE ASK_VGA
-#endif
-
-#ifndef RAMDISK
-#define RAMDISK 0
-#endif
-
-#ifndef ROOT_RDONLY
-#define ROOT_RDONLY 1
-#endif
-
-.code16
-.text
-
-.global _start
-_start:
-
-        # Normalize the start address
-        jmpl    $BOOTSEG, $start2
-
-start2:
-        movw    %cs, %ax
-        movw    %ax, %ds
-        movw    %ax, %es
-        movw    %ax, %ss
-        movw    $0x7c00, %sp
-        sti
-        cld
-
-        movw    $bugger_off_msg, %si
-
-msg_loop:
-        lodsb
-        andb    %al, %al
-        jz      die
-        movb    $0xe, %ah
-        movw    $7, %bx
-        int     $0x10
-        jmp     msg_loop
-
-die:
-        # Allow the user to press a key, then reboot
-        xorw    %ax, %ax
-        int     $0x16
-        int     $0x19
-
-        # int 0x19 should never return.  In case it does anyway,
-        # invoke the BIOS reset code...
-        ljmp    $0xf000,$0xfff0
-
-
-bugger_off_msg:
-        .ascii  "Direct booting from floppy is no longer supported.\r\n"
-        .ascii  "Please use a boot loader program instead.\r\n"
-        .ascii  "\n"
-        .ascii  "Remove disk and press any key to reboot . . .\r\n"
-        .byte   0
-
-
-        # Kernel attributes; used by setup
-
-        .org 497
-setup_sects:    .byte SETUPSECTS
-root_flags:     .word ROOT_RDONLY
-syssize:        .word SYSSIZE
-swap_dev:       .word SWAP_DEV
-ram_size:       .word RAMDISK
-vid_mode:       .word SVGA_MODE
-root_dev:       .word ROOT_DEV
-boot_flag:      .word 0xAA55
diff --git a/arch/i386/boot/cmdline.c b/arch/i386/boot/cmdline.c
new file mode 100644
index 000000000000..34bb778c4357
--- /dev/null
+++ b/arch/i386/boot/cmdline.c
@@ -0,0 +1,97 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/cmdline.c
+ *
+ * Simple command-line parser for early boot.
+ */
+
+#include "boot.h"
+
+static inline int myisspace(u8 c)
+{
+        return c <= ' ';        /* Close enough approximation */
+}
+
+/*
+ * Find a non-boolean option, that is, "option=argument".  In accordance
+ * with standard Linux practice, if this option is repeated, this returns
+ * the last instance on the command line.
+ *
+ * Returns the length of the argument (regardless of if it was
+ * truncated to fit in the buffer), or -1 on not found.
+ */
+int cmdline_find_option(const char *option, char *buffer, int bufsize)
+{
+        u32 cmdline_ptr = boot_params.hdr.cmd_line_ptr;
+        addr_t cptr;
+        char c;
+        int len = -1;
+        const char *opptr = NULL;
+        char *bufptr = buffer;
+        enum {
+                st_wordstart,   /* Start of word/after whitespace */
+                st_wordcmp,     /* Comparing this word */
+                st_wordskip,    /* Miscompare, skip */
+                st_bufcpy       /* Copying this to buffer */
+        } state = st_wordstart;
+
+        if (!cmdline_ptr || cmdline_ptr >= 0x100000)
+                return -1;      /* No command line, or inaccessible */
+
+        cptr = cmdline_ptr & 0xf;
+        set_fs(cmdline_ptr >> 4);
+
+        while (cptr < 0x10000 && (c = rdfs8(cptr++))) {
+                switch (state) {
+                case st_wordstart:
+                        if (myisspace(c))
+                                break;
+
+                        /* else */
+                        state = st_wordcmp;
+                        opptr = option;
+                        /* fall through */
+
+                case st_wordcmp:
+                        if (c == '=' && !*opptr) {
+                                len = 0;
+                                bufptr = buffer;
+                                state = st_bufcpy;
+                        } else if (myisspace(c)) {
+                                state = st_wordstart;
+                        } else if (c != *opptr++) {
+                                state = st_wordskip;
+                        }
+                        break;
+
+                case st_wordskip:
+                        if (myisspace(c))
+                                state = st_wordstart;
+                        break;
+
+                case st_bufcpy:
+                        if (myisspace(c)) {
+                                state = st_wordstart;
+                        } else {
+                                if (len < bufsize-1)
+                                        *bufptr++ = c;
+                                len++;
+                        }
+                        break;
+                }
+        }
+
+        if (bufsize)
+                *bufptr = '\0';
+
+        return len;
+}
diff --git a/arch/i386/boot/code16gcc.h b/arch/i386/boot/code16gcc.h
new file mode 100644
index 000000000000..3bd848093b9d
--- /dev/null
+++ b/arch/i386/boot/code16gcc.h
@@ -0,0 +1,15 @@
+/*
+ * code16gcc.h
+ *
+ * This file is -include'd when compiling 16-bit C code.
+ * Note: this asm() needs to be emitted before gcc omits any code.
+ * Depending on gcc version, this requires -fno-unit-at-a-time or
+ * -fno-toplevel-reorder.
+ *
+ * Hopefully gcc will eventually have a real -m16 option so we can
+ * drop this hack long term.
+ */
+
+#ifndef __ASSEMBLY__
+asm(".code16gcc");
+#endif
diff --git a/arch/i386/boot/compressed/Makefile b/arch/i386/boot/compressed/Makefile
index a661217f33ec..189fa1dbefcc 100644
--- a/arch/i386/boot/compressed/Makefile
+++ b/arch/i386/boot/compressed/Makefile
@@ -9,9 +9,14 @@ targets		:= vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o \
 EXTRA_AFLAGS    := -traditional
 
 LDFLAGS_vmlinux := -T
-CFLAGS_misc.o += -fPIC
 hostprogs-y     := relocs
 
+CFLAGS  := -m32 -D__KERNEL__ $(LINUX_INCLUDE) -O2 \
+           -fno-strict-aliasing -fPIC \
+           $(call cc-option,-ffreestanding) \
+           $(call cc-option,-fno-stack-protector)
+LDFLAGS := -m elf_i386
+
 $(obj)/vmlinux: $(src)/vmlinux.lds $(obj)/head.o $(obj)/misc.o $(obj)/piggy.o FORCE
         $(call if_changed,ld)
         @:
diff --git a/arch/i386/boot/compressed/head.S b/arch/i386/boot/compressed/head.S
index 3517a32aaf41..f35ea2237522 100644
--- a/arch/i386/boot/compressed/head.S
+++ b/arch/i386/boot/compressed/head.S
@@ -45,10 +45,10 @@ startup_32:
  * at and where we were actually loaded at.  This can only be done
  * with a short local call on x86.  Nothing  else will tell us what
  * address we are running at.  The reserved chunk of the real-mode
- * data at 0x34-0x3f are used as the stack for this calculation.
- * Only 4 bytes are needed.
+ * data at 0x1e4 (defined as a scratch field) are used as the stack
+ * for this calculation. Only 4 bytes are needed.
  */
-        leal 0x40(%esi), %esp
+        leal (0x1e4+4)(%esi), %esp
         call 1f
 1:      popl %ebp
         subl $1b, %ebp
diff --git a/arch/i386/boot/copy.S b/arch/i386/boot/copy.S
new file mode 100644
index 000000000000..ef127e56a3cf
--- /dev/null
+++ b/arch/i386/boot/copy.S
@@ -0,0 +1,101 @@
+/* ----------------------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/copy.S
+ *
+ * Memory copy routines
+ */
+
+        .code16gcc
+        .text
+
+        .globl  memcpy
+        .type   memcpy, @function
+memcpy:
+        pushw   %si
+        pushw   %di
+        movw    %ax, %di
+        movw    %dx, %si
+        pushw   %cx
+        shrw    $2, %cx
+        rep; movsl
+        popw    %cx
+        andw    $3, %cx
+        rep; movsb
+        popw    %di
+        popw    %si
+        ret
+        .size   memcpy, .-memcpy
+
+        .globl  memset
+        .type   memset, @function
+memset:
+        pushw   %di
+        movw    %ax, %di
+        movzbl  %dl, %eax
+        imull   $0x01010101,%eax
+        pushw   %cx
+        shrw    $2, %cx
+        rep; stosl
+        popw    %cx
+        andw    $3, %cx
+        rep; stosb
+        popw    %di
+        ret
+        .size   memset, .-memset
+
+        .globl  copy_from_fs
+        .type   copy_from_fs, @function
+copy_from_fs:
+        pushw   %ds
+        pushw   %fs
+        popw    %ds
+        call    memcpy
+        popw    %ds
+        ret
+        .size   copy_from_fs, .-copy_from_fs
+
+        .globl  copy_to_fs
+        .type   copy_to_fs, @function
+copy_to_fs:
+        pushw   %es
+        pushw   %fs
+        popw    %es
+        call    memcpy
+        popw    %es
+        ret
+        .size   copy_to_fs, .-copy_to_fs
+
+#if 0 /* Not currently used, but can be enabled as needed */
+
+        .globl  copy_from_gs
+        .type   copy_from_gs, @function
+copy_from_gs:
+        pushw   %ds
+        pushw   %gs
+        popw    %ds
+        call    memcpy
+        popw    %ds
+        ret
+        .size   copy_from_gs, .-copy_from_gs
+        .globl  copy_to_gs
+
+        .type   copy_to_gs, @function
+copy_to_gs:
+        pushw   %es
+        pushw   %gs
+        popw    %es
+        call    memcpy
+        popw    %es
+        ret
+        .size   copy_to_gs, .-copy_to_gs
+
+#endif
diff --git a/arch/i386/boot/cpu.c b/arch/i386/boot/cpu.c
new file mode 100644
index 000000000000..2a5c32da5852
--- /dev/null
+++ b/arch/i386/boot/cpu.c
@@ -0,0 +1,69 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/cpu.c
+ *
+ * Check for obligatory CPU features and abort if the features are not
+ * present.
+ */
+
+#include "boot.h"
+#include "bitops.h"
+#include <asm/cpufeature.h>
+
+static char *cpu_name(int level)
+{
+        static char buf[6];
+
+        if (level == 64) {
+                return "x86-64";
+        } else {
+                sprintf(buf, "i%d86", level);
+                return buf;
+        }
+}
+
+int validate_cpu(void)
+{
+        u32 *err_flags;
+        int cpu_level, req_level;
+
+        check_cpu(&cpu_level, &req_level, &err_flags);
+
+        if (cpu_level < req_level) {
+                printf("This kernel requires an %s CPU, ",
+                       cpu_name(req_level));
+                printf("but only detected an %s CPU.\n",
+                       cpu_name(cpu_level));
+                return -1;
+        }
+
+        if (err_flags) {
+                int i, j;
+                puts("This kernel requires the following features "
+                     "not present on the CPU:\n");
+
+                for (i = 0; i < NCAPINTS; i++) {
+                        u32 e = err_flags[i];
+
+                        for (j = 0; j < 32; j++) {
+                                if (e & 1)
+                                        printf("%d:%d ", i, j);
+
+                                e >>= 1;
+                        }
+                }
+                putchar('\n');
+                return -1;
+        } else {
+                return 0;
+        }
+}
diff --git a/arch/i386/boot/cpucheck.c b/arch/i386/boot/cpucheck.c
new file mode 100644
index 000000000000..8b0f4473b083
--- /dev/null
+++ b/arch/i386/boot/cpucheck.c
@@ -0,0 +1,267 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/cpucheck.c
+ *
+ * Check for obligatory CPU features and abort if the features are not
+ * present.  This code should be compilable as 16-, 32- or 64-bit
+ * code, so be very careful with types and inline assembly.
+ *
+ * This code should not contain any messages; that requires an
+ * additional wrapper.
+ *
+ * As written, this code is not safe for inclusion into the kernel
+ * proper (after FPU initialization, in particular).
+ */
+
+#ifdef _SETUP
+# include "boot.h"
+# include "bitops.h"
+#endif
+#include <linux/types.h>
+#include <asm/cpufeature.h>
+#include <asm/processor-flags.h>
+#include <asm/required-features.h>
+#include <asm/msr-index.h>
+
+struct cpu_features {
+        int level;              /* Family, or 64 for x86-64 */
+        int model;
+        u32 flags[NCAPINTS];
+};
+
+static struct cpu_features cpu;
+static u32 cpu_vendor[3];
+static u32 err_flags[NCAPINTS];
+
+#ifdef CONFIG_X86_64
+static const int req_level = 64;
+#elif defined(CONFIG_X86_MINIMUM_CPU_FAMILY)
+static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
+#else
+static const int req_level = 3;
+#endif
+
+static const u32 req_flags[NCAPINTS] =
+{
+        REQUIRED_MASK0,
+        REQUIRED_MASK1,
+        REQUIRED_MASK2,
+        REQUIRED_MASK3,
+        REQUIRED_MASK4,
+        REQUIRED_MASK5,
+        REQUIRED_MASK6,
+        REQUIRED_MASK7,
+};
+
+#define A32(a,b,c,d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
+
+static int is_amd(void)
+{
+        return cpu_vendor[0] == A32('A','u','t','h') &&
+               cpu_vendor[1] == A32('e','n','t','i') &&
+               cpu_vendor[2] == A32('c','A','M','D');
+}
+
+static int is_centaur(void)
+{
+        return cpu_vendor[0] == A32('C','e','n','t') &&
+               cpu_vendor[1] == A32('a','u','r','H') &&
+               cpu_vendor[2] == A32('a','u','l','s');
+}
+
+static int is_transmeta(void)
+{
+        return cpu_vendor[0] == A32('G','e','n','u') &&
+               cpu_vendor[1] == A32('i','n','e','T') &&
+               cpu_vendor[2] == A32('M','x','8','6');
+}
+
+static int has_fpu(void)
+{
+        u16 fcw = -1, fsw = -1;
+        u32 cr0;
+
+        asm("movl %%cr0,%0" : "=r" (cr0));
+        if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
+                cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
+                asm volatile("movl %0,%%cr0" : : "r" (cr0));
+        }
+
+        asm("fninit ; fnstsw %0 ; fnstcw %1" : "+m" (fsw), "+m" (fcw));
+
+        return fsw == 0 && (fcw & 0x103f) == 0x003f;
+}
+
+static int has_eflag(u32 mask)
+{
+        u32 f0, f1;
+
+        asm("pushfl ; "
+            "pushfl ; "
+            "popl %0 ; "
+            "movl %0,%1 ; "
+            "xorl %2,%1 ; "
+            "pushl %1 ; "
+            "popfl ; "
+            "pushfl ; "
+            "popl %1 ; "
+            "popfl"
+            : "=r" (f0), "=r" (f1)
+            : "g" (mask));
+
+        return !!((f0^f1) & mask);
+}
+
+static void get_flags(void)
+{
+        u32 max_intel_level, max_amd_level;
+        u32 tfms;
+
+        if (has_fpu())
+                set_bit(X86_FEATURE_FPU, cpu.flags);
+
+        if (has_eflag(X86_EFLAGS_ID)) {
+                asm("cpuid"
+                    : "=a" (max_intel_level),
+                      "=b" (cpu_vendor[0]),
+                      "=d" (cpu_vendor[1]),
+                      "=c" (cpu_vendor[2])
+                    : "a" (0));
+
+                if (max_intel_level >= 0x00000001 &&
+                    max_intel_level <= 0x0000ffff) {
+                        asm("cpuid"
+                            : "=a" (tfms),
+                              "=c" (cpu.flags[4]),
+                              "=d" (cpu.flags[0])
+                            : "a" (0x00000001)
+                            : "ebx");
+                        cpu.level = (tfms >> 8) & 15;
+                        cpu.model = (tfms >> 4) & 15;
+                        if (cpu.level >= 6)
+                                cpu.model += ((tfms >> 16) & 0xf) << 4;
+                }
+
+                asm("cpuid"
+                    : "=a" (max_amd_level)
+                    : "a" (0x80000000)
+                    : "ebx", "ecx", "edx");
+
+                if (max_amd_level >= 0x80000001 &&
+                    max_amd_level <= 0x8000ffff) {
+                        u32 eax = 0x80000001;
+                        asm("cpuid"
+                            : "+a" (eax),
+                              "=c" (cpu.flags[6]),
+                              "=d" (cpu.flags[1])
+                            : : "ebx");
+                }
+        }
+}
+
+/* Returns a bitmask of which words we have error bits in */
+static int check_flags(void)
+{
+        u32 err;
+        int i;
+
+        err = 0;
+        for (i = 0; i < NCAPINTS; i++) {
+                err_flags[i] = req_flags[i] & ~cpu.flags[i];
+                if (err_flags[i])
+                        err |= 1 << i;
+        }
+
+        return err;
+}
+
+/*
+ * Returns -1 on error.
+ *
+ * *cpu_level is set to the current CPU level; *req_level to the required
+ * level.  x86-64 is considered level 64 for this purpose.
+ *
+ * *err_flags_ptr is set to the flags error array if there are flags missing.
+ */
+int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
+{
+        int err;
+
+        memset(&cpu.flags, 0, sizeof cpu.flags);
+        cpu.level = 3;
+
+        if (has_eflag(X86_EFLAGS_AC))
+                cpu.level = 4;
+
+        get_flags();
+        err = check_flags();
+
+        if (test_bit(X86_FEATURE_LM, cpu.flags))
+                cpu.level = 64;
+
+        if (err == 0x01 &&
+            !(err_flags[0] &
+              ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
+            is_amd()) {
+                /* If this is an AMD and we're only missing SSE+SSE2, try to
+                   turn them on */
+
+                u32 ecx = MSR_K7_HWCR;
+                u32 eax, edx;
+
+                asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
+                eax &= ~(1 << 15);
+                asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
+
+                get_flags();    /* Make sure it really did something */
+                err = check_flags();
+        } else if (err == 0x01 &&
+                   !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
+                   is_centaur() && cpu.model >= 6) {
+                /* If this is a VIA C3, we might have to enable CX8
+                   explicitly */
+
+                u32 ecx = MSR_VIA_FCR;
+                u32 eax, edx;
+
+                asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
+                eax |= (1<<1)|(1<<7);
+                asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
+
+                set_bit(X86_FEATURE_CX8, cpu.flags);
+                err = check_flags();
+        } else if (err == 0x01 && is_transmeta()) {
+                /* Transmeta might have masked feature bits in word 0 */
+
+                u32 ecx = 0x80860004;
+                u32 eax, edx;
+                u32 level = 1;
+
+                asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
+                asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
+                asm("cpuid"
+                    : "+a" (level), "=d" (cpu.flags[0])
+                    : : "ecx", "ebx");
+                asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
+
+                err = check_flags();
+        }
+
+        if (err_flags_ptr)
+                *err_flags_ptr = err ? err_flags : NULL;
+        if (cpu_level_ptr)
+                *cpu_level_ptr = cpu.level;
+        if (req_level_ptr)
+                *req_level_ptr = req_level;
+
+        return (cpu.level < req_level || err) ? -1 : 0;
+}
diff --git a/arch/i386/boot/edd.S b/arch/i386/boot/edd.S
deleted file mode 100644
index 34321368011a..000000000000
--- a/arch/i386/boot/edd.S
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * BIOS Enhanced Disk Drive support
- * Copyright (C) 2002, 2003, 2004 Dell, Inc.
- * by Matt Domsch <Matt_Domsch@dell.com> October 2002
- * conformant to T13 Committee www.t13.org
- *   projects 1572D, 1484D, 1386D, 1226DT
- * disk signature read by Matt Domsch <Matt_Domsch@dell.com>
- *      and Andrew Wilks <Andrew_Wilks@dell.com> September 2003, June 2004
- * legacy CHS retrieval by Patrick J. LoPresti <patl@users.sourceforge.net>
- *      March 2004
- * Command line option parsing, Matt Domsch, November 2004
- */
-
-#include <linux/edd.h>
-#include <asm/setup.h>
-
-#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
-
-# It is assumed that %ds == INITSEG here
-
-        movb    $0, (EDD_MBR_SIG_NR_BUF)
-        movb    $0, (EDDNR)
-
-# Check the command line for options:
-# edd=of  disables EDD completely  (edd=off)
-# edd=sk  skips the MBR test    (edd=skipmbr)
-# edd=on  re-enables EDD (edd=on)
-
-        pushl   %esi
-        movw    $edd_mbr_sig_start, %di # Default to edd=on
-
-        movl    %cs:(cmd_line_ptr), %esi
-        andl    %esi, %esi
-        jz      old_cl                  # Old boot protocol?
-
-# Convert to a real-mode pointer in fs:si
-        movl    %esi, %eax
-        shrl    $4, %eax
-        movw    %ax, %fs
-        andw    $0xf, %si
-        jmp     have_cl_pointer
-
-# Old-style boot protocol?
-old_cl:
-        push    %ds                     # aka INITSEG
-        pop     %fs
-
-        cmpw    $0xa33f, (0x20)
-        jne     done_cl                 # No command line at all?
-        movw    (0x22), %si             # Pointer relative to INITSEG
-
-# fs:si has the pointer to the command line now
-have_cl_pointer:
-
-# Loop through kernel command line one byte at a time.  Just in
-# case the loader is buggy and failed to null-terminate the command line
-# terminate if we get close enough to the end of the segment that we
-# cannot fit "edd=XX"...
-cl_atspace:
-        cmpw    $-5, %si                # Watch for segment wraparound
-        jae     done_cl
-        movl    %fs:(%si), %eax
-        andb    %al, %al                # End of line?
-        jz      done_cl
-        cmpl    $EDD_CL_EQUALS, %eax
-        jz      found_edd_equals
-        cmpb    $0x20, %al              # <= space consider whitespace
-        ja      cl_skipword
-        incw    %si
-        jmp     cl_atspace
-
-cl_skipword:
-        cmpw    $-5, %si                # Watch for segment wraparound
-        jae     done_cl
-        movb    %fs:(%si), %al          # End of string?
-        andb    %al, %al
-        jz      done_cl
-        cmpb    $0x20, %al
-        jbe     cl_atspace
-        incw    %si
-        jmp     cl_skipword
-
-found_edd_equals:
-# only looking at first two characters after equals
-# late overrides early on the command line, so keep going after finding something
-        movw    %fs:4(%si), %ax
-        cmpw    $EDD_CL_OFF, %ax        # edd=of
-        je      do_edd_off
-        cmpw    $EDD_CL_SKIP, %ax       # edd=sk
-        je      do_edd_skipmbr
-        cmpw    $EDD_CL_ON, %ax         # edd=on
-        je      do_edd_on
-        jmp     cl_skipword
-do_edd_skipmbr:
-        movw    $edd_start, %di
-        jmp     cl_skipword
-do_edd_off:
-        movw    $edd_done, %di
-        jmp     cl_skipword
-do_edd_on:
-        movw    $edd_mbr_sig_start, %di
-        jmp     cl_skipword
-
-done_cl:
-        popl    %esi
-        jmpw    *%di
-
-# Read the first sector of each BIOS disk device and store the 4-byte signature
-edd_mbr_sig_start:
-        movb    $0x80, %dl                      # from device 80
-        movw    $EDD_MBR_SIG_BUF, %bx           # store buffer ptr in bx
-edd_mbr_sig_read:
-        movl    $0xFFFFFFFF, %eax
-        movl    %eax, (%bx)                     # assume failure
-        pushw   %bx
-        movb    $READ_SECTORS, %ah
-        movb    $1, %al                         # read 1 sector
-        movb    $0, %dh                         # at head 0
-        movw    $1, %cx                         # cylinder 0, sector 0
-        pushw   %es
-        pushw   %ds
-        popw    %es
-        movw    $EDDBUF, %bx                    # disk's data goes into EDDBUF
-        pushw   %dx             # work around buggy BIOSes
-        stc                     # work around buggy BIOSes
-        int     $0x13
-        sti                     # work around buggy BIOSes
-        popw    %dx
-        popw    %es
-        popw    %bx
-        jc      edd_mbr_sig_done                # on failure, we're done.
-        cmpb    $0, %ah         # some BIOSes do not set CF
-        jne     edd_mbr_sig_done                # on failure, we're done.
-        movl    (EDDBUF+EDD_MBR_SIG_OFFSET), %eax # read sig out of the MBR
-        movl    %eax, (%bx)                     # store success
-        incb    (EDD_MBR_SIG_NR_BUF)            # note that we stored something
-        incb    %dl                             # increment to next device
-        addw    $4, %bx                         # increment sig buffer ptr
-        cmpb    $EDD_MBR_SIG_MAX, (EDD_MBR_SIG_NR_BUF)  # Out of space?
-        jb      edd_mbr_sig_read                # keep looping
-edd_mbr_sig_done:
-
-# Do the BIOS Enhanced Disk Drive calls
-# This consists of two calls:
-#    int 13h ah=41h "Check Extensions Present"
-#    int 13h ah=48h "Get Device Parameters"
-#    int 13h ah=08h "Legacy Get Device Parameters"
-#
-# A buffer of size EDDMAXNR*(EDDEXTSIZE+EDDPARMSIZE) is reserved for our use
-# in the boot_params at EDDBUF.  The first four bytes of which are
-# used to store the device number, interface support map and version
-# results from fn41.  The next four bytes are used to store the legacy
-# cylinders, heads, and sectors from fn08. The following 74 bytes are used to
-# store the results from fn48.  Starting from device 80h, fn41, then fn48
-# are called and their results stored in EDDBUF+n*(EDDEXTSIZE+EDDPARMIZE).
-# Then the pointer is incremented to store the data for the next call.
-# This repeats until either a device doesn't exist, or until EDDMAXNR
-# devices have been stored.
-# The one tricky part is that ds:si always points EDDEXTSIZE bytes into
-# the structure, and the fn41 and fn08 results are stored at offsets
-# from there.  This removes the need to increment the pointer for
-# every store, and leaves it ready for the fn48 call.
-# A second one-byte buffer, EDDNR, in the boot_params stores
-# the number of BIOS devices which exist, up to EDDMAXNR.
-# In setup.c, copy_edd() stores both boot_params buffers away
-# for later use, as they would get overwritten otherwise.
-# This code is sensitive to the size of the structs in edd.h
-edd_start:
-                                                # %ds points to the bootsector
-                                                # result buffer for fn48
-        movw    $EDDBUF+EDDEXTSIZE, %si         # in ds:si, fn41 results
-                                                # kept just before that
-        movb    $0x80, %dl                      # BIOS device 0x80
-
-edd_check_ext:
-        movb    $CHECKEXTENSIONSPRESENT, %ah    # Function 41
-        movw    $EDDMAGIC1, %bx                 # magic
-        int     $0x13                           # make the call
-        jc      edd_done                        # no more BIOS devices
-
-        cmpw    $EDDMAGIC2, %bx                 # is magic right?
-        jne     edd_next                        # nope, next...
-
-        movb    %dl, %ds:-8(%si)                # store device number
-        movb    %ah, %ds:-7(%si)                # store version
-        movw    %cx, %ds:-6(%si)                # store extensions
-        incb    (EDDNR)                         # note that we stored something
-
-edd_get_device_params:
-        movw    $EDDPARMSIZE, %ds:(%si)         # put size
-        movw    $0x0, %ds:2(%si)                # work around buggy BIOSes
-        movb    $GETDEVICEPARAMETERS, %ah       # Function 48
-        int     $0x13                           # make the call
-                                                # Don't check for fail return
-                                                # it doesn't matter.
-edd_get_legacy_chs:
-        xorw    %ax, %ax
-        movw    %ax, %ds:-4(%si)
-        movw    %ax, %ds:-2(%si)
-        # Ralf Brown's Interrupt List says to set ES:DI to
-        # 0000h:0000h "to guard against BIOS bugs"
-        pushw   %es
-        movw    %ax, %es
-        movw    %ax, %di
-        pushw   %dx                             # legacy call clobbers %dl
-        movb    $LEGACYGETDEVICEPARAMETERS, %ah # Function 08
-        int     $0x13                           # make the call
-        jc      edd_legacy_done                 # failed
-        movb    %cl, %al                        # Low 6 bits are max
-        andb    $0x3F, %al                      #   sector number
-        movb    %al, %ds:-1(%si)                # Record max sect
-        movb    %dh, %ds:-2(%si)                # Record max head number
-        movb    %ch, %al                        # Low 8 bits of max cyl
-        shr     $6, %cl
-        movb    %cl, %ah                        # High 2 bits of max cyl
-        movw    %ax, %ds:-4(%si)
-
-edd_legacy_done:
-        popw    %dx
-        popw    %es
-        movw    %si, %ax                        # increment si
-        addw    $EDDPARMSIZE+EDDEXTSIZE, %ax
-        movw    %ax, %si
-
-edd_next:
-        incb    %dl                             # increment to next device
-        cmpb    $EDDMAXNR, (EDDNR)              # Out of space?
-        jb      edd_check_ext                   # keep looping
-
-edd_done:
-#endif
diff --git a/arch/i386/boot/edd.c b/arch/i386/boot/edd.c
new file mode 100644
index 000000000000..25a282494f4c
--- /dev/null
+++ b/arch/i386/boot/edd.c
@@ -0,0 +1,196 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/edd.c
+ *
+ * Get EDD BIOS disk information
+ */
+
+#include "boot.h"
+#include <linux/edd.h>
+
+#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
+
+struct edd_dapa {
+        u8      pkt_size;
+        u8      rsvd;
+        u16     sector_cnt;
+        u16     buf_off, buf_seg;
+        u64     lba;
+        u64     buf_lin_addr;
+};
+
+/*
+ * Read the MBR (first sector) from a specific device.
+ */
+static int read_mbr(u8 devno, void *buf)
+{
+        struct edd_dapa dapa;
+        u16 ax, bx, cx, dx, si;
+
+        memset(&dapa, 0, sizeof dapa);
+        dapa.pkt_size = sizeof(dapa);
+        dapa.sector_cnt = 1;
+        dapa.buf_off = (size_t)buf;
+        dapa.buf_seg = ds();
+        /* dapa.lba = 0; */
+
+        ax = 0x4200;            /* Extended Read */
+        si = (size_t)&dapa;
+        dx = devno;
+        asm("pushfl; stc; int $0x13; setc %%al; popfl"
+            : "+a" (ax), "+S" (si), "+d" (dx)
+            : "m" (dapa)
+            : "ebx", "ecx", "edi", "memory");
+
+        if (!(u8)ax)
+                return 0;       /* OK */
+
+        ax = 0x0201;            /* Legacy Read, one sector */
+        cx = 0x0001;            /* Sector 0-0-1 */
+        dx = devno;
+        bx = (size_t)buf;
+        asm("pushfl; stc; int $0x13; setc %%al; popfl"
+            : "+a" (ax), "+c" (cx), "+d" (dx), "+b" (bx)
+            : : "esi", "edi", "memory");
+
+        return -(u8)ax;         /* 0 or -1 */
+}
+
+static u32 read_mbr_sig(u8 devno, struct edd_info *ei)
+{
+        int sector_size;
+        char *mbrbuf_ptr, *mbrbuf_end;
+        u32 mbrsig;
+        u32 buf_base, mbr_base;
+        extern char _end[];
+        static char mbr_buf[1024];
+
+        sector_size = ei->params.bytes_per_sector;
+        if (!sector_size)
+                sector_size = 512; /* Best available guess */
+
+        buf_base = (ds() << 4) + (u32)&_end;
+        mbr_base = (buf_base+sector_size-1) & ~(sector_size-1);
+        mbrbuf_ptr = mbr_buf + (mbr_base-buf_base);
+        mbrbuf_end = mbrbuf_ptr + sector_size;
+
+        if (!(boot_params.hdr.loadflags & CAN_USE_HEAP))
+                return 0;
+        if (mbrbuf_end > (char *)(size_t)boot_params.hdr.heap_end_ptr)
+                return 0;
+
+        if (read_mbr(devno, mbrbuf_ptr))
+                return 0;
+
+        mbrsig = *(u32 *)&mbrbuf_ptr[EDD_MBR_SIG_OFFSET];
+        return mbrsig;
+}
+
+static int get_edd_info(u8 devno, struct edd_info *ei)
+{
+        u16 ax, bx, cx, dx, di;
+
+        memset(ei, 0, sizeof *ei);
+
+        /* Check Extensions Present */
+
+        ax = 0x4100;
+        bx = EDDMAGIC1;
+        dx = devno;
+        asm("pushfl; stc; int $0x13; setc %%al; popfl"
+            : "+a" (ax), "+b" (bx), "=c" (cx), "+d" (dx)
+            : : "esi", "edi");
+
+        if ((u8)ax)
+                return -1;      /* No extended information */
+
+        if (bx != EDDMAGIC2)
+                return -1;
+
+        ei->device  = devno;
+        ei->version = ax >> 8;  /* EDD version number */
+        ei->interface_support = cx; /* EDD functionality subsets */
+
+        /* Extended Get Device Parameters */
+
+        ei->params.length = sizeof(ei->params);
+        ax = 0x4800;
+        dx = devno;
+        asm("pushfl; int $0x13; popfl"
+            : "+a" (ax), "+d" (dx)
+            : "S" (&ei->params)
+            : "ebx", "ecx", "edi");
+
+        /* Get legacy CHS parameters */
+
+        /* Ralf Brown recommends setting ES:DI to 0:0 */
+        ax = 0x0800;
+        dx = devno;
+        di = 0;
+        asm("pushw %%es; "
+            "movw %%di,%%es; "
+            "pushfl; stc; int $0x13; setc %%al; popfl; "
+            "popw %%es"
+            : "+a" (ax), "=b" (bx), "=c" (cx), "+d" (dx), "+D" (di)
+            : : "esi");
+
+        if ((u8)ax == 0) {
+                ei->legacy_max_cylinder = (cx >> 8) + ((cx & 0xc0) << 2);
+                ei->legacy_max_head = dx >> 8;
+                ei->legacy_sectors_per_track = cx & 0x3f;
+        }
+
+        return 0;
+}
+
+void query_edd(void)
+{
+        char eddarg[8];
+        int do_mbr = 1;
+        int do_edd = 1;
+        int devno;
+        struct edd_info ei, *edp;
+
+        if (cmdline_find_option("edd", eddarg, sizeof eddarg) > 0) {
+                if (!strcmp(eddarg, "skipmbr") || !strcmp(eddarg, "skip"))
+                        do_mbr = 0;
+                else if (!strcmp(eddarg, "off"))
+                        do_edd = 0;
+        }
+
+        edp = (struct edd_info *)boot_params.eddbuf;
+
+        if (!do_edd)
+                return;
+
+        for (devno = 0x80; devno < 0x80+EDD_MBR_SIG_MAX; devno++) {
+                /*
+                 * Scan the BIOS-supported hard disks and query EDD
+                 * information...
+                 */
+                get_edd_info(devno, &ei);
+
+                if (boot_params.eddbuf_entries < EDDMAXNR) {
+                        memcpy(edp, &ei, sizeof ei);
+                        edp++;
+                        boot_params.eddbuf_entries++;
+                }
+
+                if (do_mbr) {
+                        u32 mbr_sig;
+                        mbr_sig = read_mbr_sig(devno, &ei);
+                        boot_params.edd_mbr_sig_buffer[devno-0x80] = mbr_sig;
+                }
+        }
+}
+
+#endif
diff --git a/arch/i386/boot/header.S b/arch/i386/boot/header.S
new file mode 100644
index 000000000000..6b9923fb6eae
--- /dev/null
+++ b/arch/i386/boot/header.S
@@ -0,0 +1,283 @@
+/*
+ *      header.S
+ *
+ *      Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ *      Based on bootsect.S and setup.S
+ *      modified by more people than can be counted
+ *
+ *      Rewritten as a common file by H. Peter Anvin (Apr 2007)
+ *
+ * BIG FAT NOTE: We're in real mode using 64k segments.  Therefore segment
+ * addresses must be multiplied by 16 to obtain their respective linear
+ * addresses. To avoid confusion, linear addresses are written using leading
+ * hex while segment addresses are written as segment:offset.
+ *
+ */
+
+#include <asm/segment.h>
+#include <linux/utsrelease.h>
+#include <asm/boot.h>
+#include <asm/e820.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include "boot.h"
+
+SETUPSECTS      = 4                     /* default nr of setup-sectors */
+BOOTSEG         = 0x07C0                /* original address of boot-sector */
+SYSSEG          = DEF_SYSSEG            /* system loaded at 0x10000 (65536) */
+SYSSIZE         = DEF_SYSSIZE           /* system size: # of 16-byte clicks */
+                                        /* to be loaded */
+ROOT_DEV        = 0                     /* ROOT_DEV is now written by "build" */
+SWAP_DEV        = 0                     /* SWAP_DEV is now written by "build" */
+
+#ifndef SVGA_MODE
+#define SVGA_MODE ASK_VGA
+#endif
+
+#ifndef RAMDISK
+#define RAMDISK 0
+#endif
+
+#ifndef ROOT_RDONLY
+#define ROOT_RDONLY 1
+#endif
+
+        .code16
+        .section ".bstext", "ax"
+
+        .global bootsect_start
+bootsect_start:
+
+        # Normalize the start address
+        ljmp    $BOOTSEG, $start2
+
+start2:
+        movw    %cs, %ax
+        movw    %ax, %ds
+        movw    %ax, %es
+        movw    %ax, %ss
+        xorw    %sp, %sp
+        sti
+        cld
+
+        movw    $bugger_off_msg, %si
+
+msg_loop:
+        lodsb
+        andb    %al, %al
+        jz      bs_die
+        movb    $0xe, %ah
+        movw    $7, %bx
+        int     $0x10
+        jmp     msg_loop
+
+bs_die:
+        # Allow the user to press a key, then reboot
+        xorw    %ax, %ax
+        int     $0x16
+        int     $0x19
+
+        # int 0x19 should never return.  In case it does anyway,
+        # invoke the BIOS reset code...
+        ljmp    $0xf000,$0xfff0
+
+        .section ".bsdata", "a"
+bugger_off_msg:
+        .ascii  "Direct booting from floppy is no longer supported.\r\n"
+        .ascii  "Please use a boot loader program instead.\r\n"
+        .ascii  "\n"
+        .ascii  "Remove disk and press any key to reboot . . .\r\n"
+        .byte   0
+
+
+        # Kernel attributes; used by setup.  This is part 1 of the
+        # header, from the old boot sector.
+
+        .section ".header", "a"
+        .globl  hdr
+hdr:
+setup_sects:    .byte SETUPSECTS
+root_flags:     .word ROOT_RDONLY
+syssize:        .long SYSSIZE
+ram_size:       .word RAMDISK
+vid_mode:       .word SVGA_MODE
+root_dev:       .word ROOT_DEV
+boot_flag:      .word 0xAA55
+
+        # offset 512, entry point
+
+        .globl  _start
+_start:
+                # Explicitly enter this as bytes, or the assembler
+                # tries to generate a 3-byte jump here, which causes
+                # everything else to push off to the wrong offset.
+                .byte   0xeb            # short (2-byte) jump
+                .byte   start_of_setup-1f
+1:
+
+        # Part 2 of the header, from the old setup.S
+
+                .ascii  "HdrS"          # header signature
+                .word   0x0206          # header version number (>= 0x0105)
+                                        # or else old loadlin-1.5 will fail)
+                .globl realmode_swtch
+realmode_swtch: .word   0, 0            # default_switch, SETUPSEG
+start_sys_seg:  .word   SYSSEG
+                .word   kernel_version-512 # pointing to kernel version string
+                                        # above section of header is compatible
+                                        # with loadlin-1.5 (header v1.5). Don't
+                                        # change it.
+
+type_of_loader: .byte   0               # = 0, old one (LILO, Loadlin,
+                                        #      Bootlin, SYSLX, bootsect...)
+                                        # See Documentation/i386/boot.txt for
+                                        # assigned ids
+
+# flags, unused bits must be zero (RFU) bit within loadflags
+loadflags:
+LOADED_HIGH     = 1                     # If set, the kernel is loaded high
+CAN_USE_HEAP    = 0x80                  # If set, the loader also has set
+                                        # heap_end_ptr to tell how much
+                                        # space behind setup.S can be used for
+                                        # heap purposes.
+                                        # Only the loader knows what is free
+#ifndef __BIG_KERNEL__
+                .byte   0
+#else
+                .byte   LOADED_HIGH
+#endif
+
+setup_move_size: .word  0x8000          # size to move, when setup is not
+                                        # loaded at 0x90000. We will move setup
+                                        # to 0x90000 then just before jumping
+                                        # into the kernel. However, only the
+                                        # loader knows how much data behind
+                                        # us also needs to be loaded.
+
+code32_start:                           # here loaders can put a different
+                                        # start address for 32-bit code.
+#ifndef __BIG_KERNEL__
+                .long   0x1000          #   0x1000 = default for zImage
+#else
+                .long   0x100000        # 0x100000 = default for big kernel
+#endif
+
+ramdisk_image:  .long   0               # address of loaded ramdisk image
+                                        # Here the loader puts the 32-bit
+                                        # address where it loaded the image.
+                                        # This only will be read by the kernel.
+
+ramdisk_size:   .long   0               # its size in bytes
+
+bootsect_kludge:
+                .long   0               # obsolete
+
+heap_end_ptr:   .word   _end+1024       # (Header version 0x0201 or later)
+                                        # space from here (exclusive) down to
+                                        # end of setup code can be used by setup
+                                        # for local heap purposes.
+
+pad1:           .word   0
+cmd_line_ptr:   .long   0               # (Header version 0x0202 or later)
+                                        # If nonzero, a 32-bit pointer
+                                        # to the kernel command line.
+                                        # The command line should be
+                                        # located between the start of
+                                        # setup and the end of low
+                                        # memory (0xa0000), or it may
+                                        # get overwritten before it
+                                        # gets read.  If this field is
+                                        # used, there is no longer
+                                        # anything magical about the
+                                        # 0x90000 segment; the setup
+                                        # can be located anywhere in
+                                        # low memory 0x10000 or higher.
+
+ramdisk_max:    .long (-__PAGE_OFFSET-(512 << 20)-1) & 0x7fffffff
+                                        # (Header version 0x0203 or later)
+                                        # The highest safe address for
+                                        # the contents of an initrd
+
+kernel_alignment:  .long CONFIG_PHYSICAL_ALIGN  #physical addr alignment
+                                                #required for protected mode
+                                                #kernel
+#ifdef CONFIG_RELOCATABLE
+relocatable_kernel:    .byte 1
+#else
+relocatable_kernel:    .byte 0
+#endif
+pad2:                   .byte 0
+pad3:                   .word 0
+
+cmdline_size:   .long   COMMAND_LINE_SIZE-1     #length of the command line,
+                                                #added with boot protocol
+                                                #version 2.06
+
+# End of setup header #####################################################
+
+        .section ".inittext", "ax"
+start_of_setup:
+#ifdef SAFE_RESET_DISK_CONTROLLER
+# Reset the disk controller.
+        movw    $0x0000, %ax            # Reset disk controller
+        movb    $0x80, %dl              # All disks
+        int     $0x13
+#endif
+
+# We will have entired with %cs = %ds+0x20, normalize %cs so
+# it is on par with the other segments.
+        pushw   %ds
+        pushw   $setup2
+        lretw
+
+setup2:
+# Force %es = %ds
+        movw    %ds, %ax
+        movw    %ax, %es
+        cld
+
+# Stack paranoia: align the stack and make sure it is good
+# for both 16- and 32-bit references.  In particular, if we
+# were meant to have been using the full 16-bit segment, the
+# caller might have set %sp to zero, which breaks %esp-based
+# references.
+        andw    $~3, %sp        # dword align (might as well...)
+        jnz     1f
+        movw    $0xfffc, %sp    # Make sure we're not zero
+1:      movzwl  %sp, %esp       # Clear upper half of %esp
+        sti
+
+# Check signature at end of setup
+        cmpl    $0x5a5aaa55, setup_sig
+        jne     setup_bad
+
+# Zero the bss
+        movw    $__bss_start, %di
+        movw    $_end+3, %cx
+        xorl    %eax, %eax
+        subw    %di, %cx
+        shrw    $2, %cx
+        rep; stosl
+
+# Jump to C code (should not return)
+        calll   main
+
+# Setup corrupt somehow...
+setup_bad:
+        movl    $setup_corrupt, %eax
+        calll   puts
+        # Fall through...
+
+        .globl  die
+        .type   die, @function
+die:
+        hlt
+        jmp     die
+
+        .size   die, .-due
+
+        .section ".initdata", "a"
+setup_corrupt:
+        .byte   7
+        .string "No setup signature found..."
diff --git a/arch/i386/boot/main.c b/arch/i386/boot/main.c
new file mode 100644
index 000000000000..7f01f96c4fb8
--- /dev/null
+++ b/arch/i386/boot/main.c
@@ -0,0 +1,161 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/main.c
+ *
+ * Main module for the real-mode kernel code
+ */
+
+#include "boot.h"
+
+struct boot_params boot_params __attribute__((aligned(16)));
+
+char *HEAP = _end;
+char *heap_end = _end;          /* Default end of heap = no heap */
+
+/*
+ * Copy the header into the boot parameter block.  Since this
+ * screws up the old-style command line protocol, adjust by
+ * filling in the new-style command line pointer instead.
+ */
+#define OLD_CL_MAGIC    0xA33F
+#define OLD_CL_ADDRESS  0x20
+
+static void copy_boot_params(void)
+{
+        struct old_cmdline {
+                u16 cl_magic;
+                u16 cl_offset;
+        };
+        const struct old_cmdline * const oldcmd =
+                (const struct old_cmdline *)OLD_CL_ADDRESS;
+
+        BUILD_BUG_ON(sizeof boot_params != 4096);
+        memcpy(&boot_params.hdr, &hdr, sizeof hdr);
+
+        if (!boot_params.hdr.cmd_line_ptr &&
+            oldcmd->cl_magic == OLD_CL_MAGIC) {
+                /* Old-style command line protocol. */
+                u16 cmdline_seg;
+
+                /* Figure out if the command line falls in the region
+                   of memory that an old kernel would have copied up
+                   to 0x90000... */
+                if (oldcmd->cl_offset < boot_params.hdr.setup_move_size)
+                        cmdline_seg = ds();
+                else
+                        cmdline_seg = 0x9000;
+
+                boot_params.hdr.cmd_line_ptr =
+                        (cmdline_seg << 4) + oldcmd->cl_offset;
+        }
+}
+
+/*
+ * Set the keyboard repeat rate to maximum.  Unclear why this
+ * is done here; this might be possible to kill off as stale code.
+ */
+static void keyboard_set_repeat(void)
+{
+        u16 ax = 0x0305;
+        u16 bx = 0;
+        asm volatile("int $0x16"
+                     : "+a" (ax), "+b" (bx)
+                     : : "ecx", "edx", "esi", "edi");
+}
+
+/*
+ * Get Intel SpeedStep IST information.
+ */
+static void query_speedstep_ist(void)
+{
+        asm("int $0x15"
+            : "=a" (boot_params.speedstep_info[0]),
+              "=b" (boot_params.speedstep_info[1]),
+              "=c" (boot_params.speedstep_info[2]),
+              "=d" (boot_params.speedstep_info[3])
+            : "a" (0x0000e980),  /* IST Support */
+              "d" (0x47534943)); /* Request value */
+}
+
+/*
+ * Tell the BIOS what CPU mode we intend to run in.
+ */
+static void set_bios_mode(void)
+{
+#ifdef CONFIG_X86_64
+        u32 eax, ebx;
+
+        eax = 0xec00;
+        ebx = 2;
+        asm volatile("int $0x15"
+                     : "+a" (eax), "+b" (ebx)
+                     : : "ecx", "edx", "esi", "edi");
+#endif
+}
+
+void main(void)
+{
+        /* First, copy the boot header into the "zeropage" */
+        copy_boot_params();
+
+        /* End of heap check */
+        if (boot_params.hdr.loadflags & CAN_USE_HEAP) {
+                heap_end = (char *)(boot_params.hdr.heap_end_ptr
+                                    +0x200-STACK_SIZE);
+        } else {
+                /* Boot protocol 2.00 only, no heap available */
+                puts("WARNING: Ancient bootloader, some functionality "
+                     "may be limited!\n");
+        }
+
+        /* Make sure we have all the proper CPU support */
+        if (validate_cpu()) {
+                puts("Unable to boot - please use a kernel appropriate "
+                     "for your CPU.\n");
+                die();
+        }
+
+        /* Tell the BIOS what CPU mode we intend to run in. */
+        set_bios_mode();
+
+        /* Detect memory layout */
+        detect_memory();
+
+        /* Set keyboard repeat rate (why?) */
+        keyboard_set_repeat();
+
+        /* Set the video mode */
+        set_video();
+
+        /* Query MCA information */
+        query_mca();
+
+        /* Voyager */
+#ifdef CONFIG_X86_VOYAGER
+        query_voyager();
+#endif
+
+        /* Query SpeedStep IST information */
+        query_speedstep_ist();
+
+        /* Query APM information */
+#if defined(CONFIG_APM) || defined(CONFIG_APM_MODULE)
+        query_apm_bios();
+#endif
+
+        /* Query EDD information */
+#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
+        query_edd();
+#endif
+        /* Do the last things and invoke protected mode */
+        go_to_protected_mode();
+}
diff --git a/arch/i386/boot/mca.c b/arch/i386/boot/mca.c
new file mode 100644
index 000000000000..9b68bd1aef19
--- /dev/null
+++ b/arch/i386/boot/mca.c
@@ -0,0 +1,43 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/mca.c
+ *
+ * Get the MCA system description table
+ */
+
+#include "boot.h"
+
+int query_mca(void)
+{
+        u8 err;
+        u16 es, bx, len;
+
+        asm("pushw %%es ; "
+            "int $0x15 ; "
+            "setc %0 ; "
+            "movw %%es, %1 ; "
+            "popw %%es"
+            : "=acdSDm" (err), "=acdSDm" (es), "=b" (bx)
+            : "a" (0xc000));
+
+        if (err)
+                return -1;      /* No MCA present */
+
+        set_fs(es);
+        len = rdfs16(bx);
+
+        if (len > sizeof(boot_params.sys_desc_table))
+                len = sizeof(boot_params.sys_desc_table);
+
+        copy_from_fs(&boot_params.sys_desc_table, bx, len);
+        return 0;
+}
diff --git a/arch/i386/boot/memory.c b/arch/i386/boot/memory.c
new file mode 100644
index 000000000000..1a2e62db8bed
--- /dev/null
+++ b/arch/i386/boot/memory.c
@@ -0,0 +1,99 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/memory.c
+ *
+ * Memory detection code
+ */
+
+#include "boot.h"
+
+#define SMAP    0x534d4150      /* ASCII "SMAP" */
+
+static int detect_memory_e820(void)
+{
+        u32 next = 0;
+        u32 size, id;
+        u8 err;
+        struct e820entry *desc = boot_params.e820_map;
+
+        do {
+                size = sizeof(struct e820entry);
+                id = SMAP;
+                asm("int $0x15; setc %0"
+                    : "=am" (err), "+b" (next), "+d" (id), "+c" (size),
+                      "=m" (*desc)
+                    : "D" (desc), "a" (0xe820));
+
+                if (err || id != SMAP)
+                        break;
+
+                boot_params.e820_entries++;
+                desc++;
+        } while (next && boot_params.e820_entries < E820MAX);
+
+        return boot_params.e820_entries;
+}
+
+static int detect_memory_e801(void)
+{
+        u16 ax, bx, cx, dx;
+        u8 err;
+
+        bx = cx = dx = 0;
+        ax = 0xe801;
+        asm("stc; int $0x15; setc %0"
+            : "=m" (err), "+a" (ax), "+b" (bx), "+c" (cx), "+d" (dx));
+
+        if (err)
+                return -1;
+
+        /* Do we really need to do this? */
+        if (cx || dx) {
+                ax = cx;
+                bx = dx;
+        }
+
+        if (ax > 15*1024)
+                return -1;      /* Bogus! */
+
+        /* This ignores memory above 16MB if we have a memory hole
+           there.  If someone actually finds a machine with a memory
+           hole at 16MB and no support for 0E820h they should probably
+           generate a fake e820 map. */
+        boot_params.alt_mem_k = (ax == 15*1024) ? (dx << 6)+ax : ax;
+
+        return 0;
+}
+
+static int detect_memory_88(void)
+{
+        u16 ax;
+        u8 err;
+
+        ax = 0x8800;
+        asm("stc; int $0x15; setc %0" : "=bcdm" (err), "+a" (ax));
+
+        boot_params.screen_info.ext_mem_k = ax;
+
+        return -err;
+}
+
+int detect_memory(void)
+{
+        if (detect_memory_e820() > 0)
+                return 0;
+
+        if (!detect_memory_e801())
+                return 0;
+
+        return detect_memory_88();
+}
diff --git a/arch/i386/boot/pm.c b/arch/i386/boot/pm.c
new file mode 100644
index 000000000000..3fa53e15ed77
--- /dev/null
+++ b/arch/i386/boot/pm.c
@@ -0,0 +1,170 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/pm.c
+ *
+ * Prepare the machine for transition to protected mode.
+ */
+
+#include "boot.h"
+#include <asm/segment.h>
+
+/*
+ * Invoke the realmode switch hook if present; otherwise
+ * disable all interrupts.
+ */
+static void realmode_switch_hook(void)
+{
+        if (boot_params.hdr.realmode_swtch) {
+                asm volatile("lcallw *%0"
+                             : : "m" (boot_params.hdr.realmode_swtch)
+                             : "eax", "ebx", "ecx", "edx");
+        } else {
+                asm volatile("cli");
+                outb(0x80, 0x70); /* Disable NMI */
+                io_delay();
+        }
+}
+
+/*
+ * A zImage kernel is loaded at 0x10000 but wants to run at 0x1000.
+ * A bzImage kernel is loaded and runs at 0x100000.
+ */
+static void move_kernel_around(void)
+{
+        /* Note: rely on the compile-time option here rather than
+           the LOADED_HIGH flag.  The Qemu kernel loader unconditionally
+           sets the loadflags to zero. */
+#ifndef __BIG_KERNEL__
+        u16 dst_seg, src_seg;
+        u32 syssize;
+
+        dst_seg =  0x1000 >> 4;
+        src_seg = 0x10000 >> 4;
+        syssize = boot_params.hdr.syssize; /* Size in 16-byte paragraphs */
+
+        while (syssize) {
+                int paras  = (syssize >= 0x1000) ? 0x1000 : syssize;
+                int dwords = paras << 2;
+
+                asm volatile("pushw %%es ; "
+                             "pushw %%ds ; "
+                             "movw %1,%%es ; "
+                             "movw %2,%%ds ; "
+                             "xorw %%di,%%di ; "
+                             "xorw %%si,%%si ; "
+                             "rep;movsl ; "
+                             "popw %%ds ; "
+                             "popw %%es"
+                             : "+c" (dwords)
+                             : "rm" (dst_seg), "rm" (src_seg)
+                             : "esi", "edi");
+
+                syssize -= paras;
+                dst_seg += paras;
+                src_seg += paras;
+        }
+#endif
+}
+
+/*
+ * Disable all interrupts at the legacy PIC.
+ */
+static void mask_all_interrupts(void)
+{
+        outb(0xff, 0xa1);       /* Mask all interrupts on the seconday PIC */
+        io_delay();
+        outb(0xfb, 0x21);       /* Mask all but cascade on the primary PIC */
+        io_delay();
+}
+
+/*
+ * Reset IGNNE# if asserted in the FPU.
+ */
+static void reset_coprocessor(void)
+{
+        outb(0, 0xf0);
+        io_delay();
+        outb(0, 0xf1);
+        io_delay();
+}
+
+/*
+ * Set up the GDT
+ */
+#define GDT_ENTRY(flags,base,limit)             \
+        (((u64)(base & 0xff000000) << 32) |     \
+         ((u64)flags << 40) |                   \
+         ((u64)(limit & 0x00ff0000) << 32) |    \
+         ((u64)(base & 0x00ffff00) << 16) |     \
+         ((u64)(limit & 0x0000ffff)))
+
+struct gdt_ptr {
+        u16 len;
+        u32 ptr;
+} __attribute__((packed));
+
+static void setup_gdt(void)
+{
+        /* There are machines which are known to not boot with the GDT
+           being 8-byte unaligned.  Intel recommends 16 byte alignment. */
+        static const u64 boot_gdt[] __attribute__((aligned(16))) = {
+                /* CS: code, read/execute, 4 GB, base 0 */
+                [GDT_ENTRY_BOOT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
+                /* DS: data, read/write, 4 GB, base 0 */
+                [GDT_ENTRY_BOOT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
+        };
+        struct gdt_ptr gdt;
+
+        gdt.len = sizeof(boot_gdt)-1;
+        gdt.ptr = (u32)&boot_gdt + (ds() << 4);
+
+        asm volatile("lgdtl %0" : : "m" (gdt));
+}
+
+/*
+ * Set up the IDT
+ */
+static void setup_idt(void)
+{
+        static const struct gdt_ptr null_idt = {0, 0};
+        asm volatile("lidtl %0" : : "m" (null_idt));
+}
+
+/*
+ * Actual invocation sequence
+ */
+void go_to_protected_mode(void)
+{
+        /* Hook before leaving real mode, also disables interrupts */
+        realmode_switch_hook();
+
+        /* Move the kernel/setup to their final resting places */
+        move_kernel_around();
+
+        /* Enable the A20 gate */
+        if (enable_a20()) {
+                puts("A20 gate not responding, unable to boot...\n");
+                die();
+        }
+
+        /* Reset coprocessor (IGNNE#) */
+        reset_coprocessor();
+
+        /* Mask all interrupts in the PIC */
+        mask_all_interrupts();
+
+        /* Actual transition to protected mode... */
+        setup_idt();
+        setup_gdt();
+        protected_mode_jump(boot_params.hdr.code32_start,
+                            (u32)&boot_params + (ds() << 4));
+}
diff --git a/arch/i386/boot/pmjump.S b/arch/i386/boot/pmjump.S
new file mode 100644
index 000000000000..2e559233725a
--- /dev/null
+++ b/arch/i386/boot/pmjump.S
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/pmjump.S
+ *
+ * The actual transition into protected mode
+ */
+
+#include <asm/boot.h>
+#include <asm/segment.h>
+
+        .text
+
+        .globl  protected_mode_jump
+        .type   protected_mode_jump, @function
+
+        .code16
+
+/*
+ * void protected_mode_jump(u32 entrypoint, u32 bootparams);
+ */
+protected_mode_jump:
+        xorl    %ebx, %ebx              # Flag to indicate this is a boot
+        movl    %edx, %esi              # Pointer to boot_params table
+        movl    %eax, 2f                # Patch ljmpl instruction
+        jmp     1f                      # Short jump to flush instruction q.
+
+1:
+        movw    $__BOOT_DS, %cx
+
+        movl    %cr0, %edx
+        orb     $1, %dl                 # Protected mode (PE) bit
+        movl    %edx, %cr0
+
+        movw    %cx, %ds
+        movw    %cx, %es
+        movw    %cx, %fs
+        movw    %cx, %gs
+        movw    %cx, %ss
+
+        # Jump to the 32-bit entrypoint
+        .byte   0x66, 0xea              # ljmpl opcode
+2:      .long   0                       # offset
+        .word   __BOOT_CS               # segment
+
+        .size   protected_mode_jump, .-protected_mode_jump
diff --git a/arch/i386/boot/printf.c b/arch/i386/boot/printf.c
new file mode 100644
index 000000000000..1a09f9309d3c
--- /dev/null
+++ b/arch/i386/boot/printf.c
@@ -0,0 +1,307 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/printf.c
+ *
+ * Oh, it's a waste of space, but oh-so-yummy for debugging.  This
+ * version of printf() does not include 64-bit support.  "Live with
+ * it."
+ *
+ */
+
+#include "boot.h"
+
+static int skip_atoi(const char **s)
+{
+        int i = 0;
+
+        while (isdigit(**s))
+                i = i * 10 + *((*s)++) - '0';
+        return i;
+}
+
+#define ZEROPAD 1               /* pad with zero */
+#define SIGN    2               /* unsigned/signed long */
+#define PLUS    4               /* show plus */
+#define SPACE   8               /* space if plus */
+#define LEFT    16              /* left justified */
+#define SPECIAL 32              /* 0x */
+#define LARGE   64              /* use 'ABCDEF' instead of 'abcdef' */
+
+#define do_div(n,base) ({ \
+int __res; \
+__res = ((unsigned long) n) % (unsigned) base; \
+n = ((unsigned long) n) / (unsigned) base; \
+__res; })
+
+static char *number(char *str, long num, int base, int size, int precision,
+                    int type)
+{
+        char c, sign, tmp[66];
+        const char *digits = "0123456789abcdefghijklmnopqrstuvwxyz";
+        int i;
+
+        if (type & LARGE)
+                digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+        if (type & LEFT)
+                type &= ~ZEROPAD;
+        if (base < 2 || base > 36)
+                return 0;
+        c = (type & ZEROPAD) ? '0' : ' ';
+        sign = 0;
+        if (type & SIGN) {
+                if (num < 0) {
+                        sign = '-';
+                        num = -num;
+                        size--;
+                } else if (type & PLUS) {
+                        sign = '+';
+                        size--;
+                } else if (type & SPACE) {
+                        sign = ' ';
+                        size--;
+                }
+        }
+        if (type & SPECIAL) {
+                if (base == 16)
+                        size -= 2;
+                else if (base == 8)
+                        size--;
+        }
+        i = 0;
+        if (num == 0)
+                tmp[i++] = '0';
+        else
+                while (num != 0)
+                        tmp[i++] = digits[do_div(num, base)];
+        if (i > precision)
+                precision = i;
+        size -= precision;
+        if (!(type & (ZEROPAD + LEFT)))
+                while (size-- > 0)
+                        *str++ = ' ';
+        if (sign)
+                *str++ = sign;
+        if (type & SPECIAL) {
+                if (base == 8)
+                        *str++ = '0';
+                else if (base == 16) {
+                        *str++ = '0';
+                        *str++ = digits[33];
+                }
+        }
+        if (!(type & LEFT))
+                while (size-- > 0)
+                        *str++ = c;
+        while (i < precision--)
+                *str++ = '0';
+        while (i-- > 0)
+                *str++ = tmp[i];
+        while (size-- > 0)
+                *str++ = ' ';
+        return str;
+}
+
+int vsprintf(char *buf, const char *fmt, va_list args)
+{
+        int len;
+        unsigned long num;
+        int i, base;
+        char *str;
+        const char *s;
+
+        int flags;              /* flags to number() */
+
+        int field_width;        /* width of output field */
+        int precision;          /* min. # of digits for integers; max
+                                   number of chars for from string */
+        int qualifier;          /* 'h', 'l', or 'L' for integer fields */
+
+        for (str = buf; *fmt; ++fmt) {
+                if (*fmt != '%') {
+                        *str++ = *fmt;
+                        continue;
+                }
+
+                /* process flags */
+                flags = 0;
+              repeat:
+                ++fmt;          /* this also skips first '%' */
+                switch (*fmt) {
+                case '-':
+                        flags |= LEFT;
+                        goto repeat;
+                case '+':
+                        flags |= PLUS;
+                        goto repeat;
+                case ' ':
+                        flags |= SPACE;
+                        goto repeat;
+                case '#':
+                        flags |= SPECIAL;
+                        goto repeat;
+                case '0':
+                        flags |= ZEROPAD;
+                        goto repeat;
+                }
+
+                /* get field width */
+                field_width = -1;
+                if (isdigit(*fmt))
+                        field_width = skip_atoi(&fmt);
+                else if (*fmt == '*') {
+                        ++fmt;
+                        /* it's the next argument */
+                        field_width = va_arg(args, int);
+                        if (field_width < 0) {
+                                field_width = -field_width;
+                                flags |= LEFT;
+                        }
+                }
+
+                /* get the precision */
+                precision = -1;
+                if (*fmt == '.') {
+                        ++fmt;
+                        if (isdigit(*fmt))
+                                precision = skip_atoi(&fmt);
+                        else if (*fmt == '*') {
+                                ++fmt;
+                                /* it's the next argument */
+                                precision = va_arg(args, int);
+                        }
+                        if (precision < 0)
+                                precision = 0;
+                }
+
+                /* get the conversion qualifier */
+                qualifier = -1;
+                if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
+                        qualifier = *fmt;
+                        ++fmt;
+                }
+
+                /* default base */
+                base = 10;
+
+                switch (*fmt) {
+                case 'c':
+                        if (!(flags & LEFT))
+                                while (--field_width > 0)
+                                        *str++ = ' ';
+                        *str++ = (unsigned char)va_arg(args, int);
+                        while (--field_width > 0)
+                                *str++ = ' ';
+                        continue;
+
+                case 's':
+                        s = va_arg(args, char *);
+                        len = strnlen(s, precision);
+
+                        if (!(flags & LEFT))
+                                while (len < field_width--)
+                                        *str++ = ' ';
+                        for (i = 0; i < len; ++i)
+                                *str++ = *s++;
+                        while (len < field_width--)
+                                *str++ = ' ';
+                        continue;
+
+                case 'p':
+                        if (field_width == -1) {
+                                field_width = 2 * sizeof(void *);
+                                flags |= ZEROPAD;
+                        }
+                        str = number(str,
+                                     (unsigned long)va_arg(args, void *), 16,
+                                     field_width, precision, flags);
+                        continue;
+
+                case 'n':
+                        if (qualifier == 'l') {
+                                long *ip = va_arg(args, long *);
+                                *ip = (str - buf);
+                        } else {
+                                int *ip = va_arg(args, int *);
+                                *ip = (str - buf);
+                        }
+                        continue;
+
+                case '%':
+                        *str++ = '%';
+                        continue;
+
+                        /* integer number formats - set up the flags and "break" */
+                case 'o':
+                        base = 8;
+                        break;
+
+                case 'X':
+                        flags |= LARGE;
+                case 'x':
+                        base = 16;
+                        break;
+
+                case 'd':
+                case 'i':
+                        flags |= SIGN;
+                case 'u':
+                        break;
+
+                default:
+                        *str++ = '%';
+                        if (*fmt)
+                                *str++ = *fmt;
+                        else
+                                --fmt;
+                        continue;
+                }
+                if (qualifier == 'l')
+                        num = va_arg(args, unsigned long);
+                else if (qualifier == 'h') {
+                        num = (unsigned short)va_arg(args, int);
+                        if (flags & SIGN)
+                                num = (short)num;
+                } else if (flags & SIGN)
+                        num = va_arg(args, int);
+                else
+                        num = va_arg(args, unsigned int);
+                str = number(str, num, base, field_width, precision, flags);
+        }
+        *str = '\0';
+        return str - buf;
+}
+
+int sprintf(char *buf, const char *fmt, ...)
+{
+        va_list args;
+        int i;
+
+        va_start(args, fmt);
+        i = vsprintf(buf, fmt, args);
+        va_end(args);
+        return i;
+}
+
+int printf(const char *fmt, ...)
+{
+        char printf_buf[1024];
+        va_list args;
+        int printed;
+
+        va_start(args, fmt);
+        printed = vsprintf(printf_buf, fmt, args);
+        va_end(args);
+
+        puts(printf_buf);
+
+        return printed;
+}
diff --git a/arch/i386/boot/setup.S b/arch/i386/boot/setup.S
deleted file mode 100644
index 6dbcc95b2120..000000000000
--- a/arch/i386/boot/setup.S
+++ /dev/null
@@ -1,1075 +0,0 @@
-/*
- *      setup.S         Copyright (C) 1991, 1992 Linus Torvalds
- *
- * setup.s is responsible for getting the system data from the BIOS,
- * and putting them into the appropriate places in system memory.
- * both setup.s and system has been loaded by the bootblock.
- *
- * This code asks the bios for memory/disk/other parameters, and
- * puts them in a "safe" place: 0x90000-0x901FF, ie where the
- * boot-block used to be. It is then up to the protected mode
- * system to read them from there before the area is overwritten
- * for buffer-blocks.
- *
- * Move PS/2 aux init code to psaux.c
- * (troyer@saifr00.cfsat.Honeywell.COM) 03Oct92
- *
- * some changes and additional features by Christoph Niemann,
- * March 1993/June 1994 (Christoph.Niemann@linux.org)
- *
- * add APM BIOS checking by Stephen Rothwell, May 1994
- * (sfr@canb.auug.org.au)
- *
- * High load stuff, initrd support and position independency
- * by Hans Lermen & Werner Almesberger, February 1996
- * <lermen@elserv.ffm.fgan.de>, <almesber@lrc.epfl.ch>
- *
- * Video handling moved to video.S by Martin Mares, March 1996
- * <mj@k332.feld.cvut.cz>
- *
- * Extended memory detection scheme retwiddled by orc@pell.chi.il.us (david
- * parsons) to avoid loadlin confusion, July 1997
- *
- * Transcribed from Intel (as86) -> AT&T (gas) by Chris Noe, May 1999.
- * <stiker@northlink.com>
- *
- * Fix to work around buggy BIOSes which don't use carry bit correctly
- * and/or report extended memory in CX/DX for e801h memory size detection 
- * call.  As a result the kernel got wrong figures.  The int15/e801h docs
- * from Ralf Brown interrupt list seem to indicate AX/BX should be used
- * anyway.  So to avoid breaking many machines (presumably there was a reason
- * to orginally use CX/DX instead of AX/BX), we do a kludge to see
- * if CX/DX have been changed in the e801 call and if so use AX/BX .
- * Michael Miller, April 2001 <michaelm@mjmm.org>
- *
- * New A20 code ported from SYSLINUX by H. Peter Anvin. AMD Elan bugfixes
- * by Robert Schwebel, December 2001 <robert@schwebel.de>
- */
-
-#include <asm/segment.h>
-#include <linux/utsrelease.h>
-#include <linux/compile.h>
-#include <asm/boot.h>
-#include <asm/e820.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-        
-/* Signature words to ensure LILO loaded us right */
-#define SIG1    0xAA55
-#define SIG2    0x5A5A
-
-INITSEG  = DEF_INITSEG          # 0x9000, we move boot here, out of the way
-SYSSEG   = DEF_SYSSEG           # 0x1000, system loaded at 0x10000 (65536).
-SETUPSEG = DEF_SETUPSEG         # 0x9020, this is the current segment
-                                # ... and the former contents of CS
-
-DELTA_INITSEG = SETUPSEG - INITSEG      # 0x0020
-
-.code16
-.globl begtext, begdata, begbss, endtext, enddata, endbss
-
-.text
-begtext:
-.data
-begdata:
-.bss
-begbss:
-.text
-
-start:
-        jmp     trampoline
-
-# This is the setup header, and it must start at %cs:2 (old 0x9020:2)
-
-                .ascii  "HdrS"          # header signature
-                .word   0x0206          # header version number (>= 0x0105)
-                                        # or else old loadlin-1.5 will fail)
-realmode_swtch: .word   0, 0            # default_switch, SETUPSEG
-start_sys_seg:  .word   SYSSEG
-                .word   kernel_version  # pointing to kernel version string
-                                        # above section of header is compatible
-                                        # with loadlin-1.5 (header v1.5). Don't
-                                        # change it.
-
-type_of_loader: .byte   0               # = 0, old one (LILO, Loadlin,
-                                        #      Bootlin, SYSLX, bootsect...)
-                                        # See Documentation/i386/boot.txt for
-                                        # assigned ids
-        
-# flags, unused bits must be zero (RFU) bit within loadflags
-loadflags:
-LOADED_HIGH     = 1                     # If set, the kernel is loaded high
-CAN_USE_HEAP    = 0x80                  # If set, the loader also has set
-                                        # heap_end_ptr to tell how much
-                                        # space behind setup.S can be used for
-                                        # heap purposes.
-                                        # Only the loader knows what is free
-#ifndef __BIG_KERNEL__
-                .byte   0
-#else
-                .byte   LOADED_HIGH
-#endif
-
-setup_move_size: .word  0x8000          # size to move, when setup is not
-                                        # loaded at 0x90000. We will move setup 
-                                        # to 0x90000 then just before jumping
-                                        # into the kernel. However, only the
-                                        # loader knows how much data behind
-                                        # us also needs to be loaded.
-
-code32_start:                           # here loaders can put a different
-                                        # start address for 32-bit code.
-#ifndef __BIG_KERNEL__
-                .long   0x1000          #   0x1000 = default for zImage
-#else
-                .long   0x100000        # 0x100000 = default for big kernel
-#endif
-
-ramdisk_image:  .long   0               # address of loaded ramdisk image
-                                        # Here the loader puts the 32-bit
-                                        # address where it loaded the image.
-                                        # This only will be read by the kernel.
-
-ramdisk_size:   .long   0               # its size in bytes
-
-bootsect_kludge:
-                .long   0               # obsolete
-
-heap_end_ptr:   .word   modelist+1024   # (Header version 0x0201 or later)
-                                        # space from here (exclusive) down to
-                                        # end of setup code can be used by setup
-                                        # for local heap purposes.
-
-pad1:           .word   0
-cmd_line_ptr:   .long 0                 # (Header version 0x0202 or later)
-                                        # If nonzero, a 32-bit pointer
-                                        # to the kernel command line.
-                                        # The command line should be
-                                        # located between the start of
-                                        # setup and the end of low
-                                        # memory (0xa0000), or it may
-                                        # get overwritten before it
-                                        # gets read.  If this field is
-                                        # used, there is no longer
-                                        # anything magical about the
-                                        # 0x90000 segment; the setup
-                                        # can be located anywhere in
-                                        # low memory 0x10000 or higher.
-
-ramdisk_max:    .long (-__PAGE_OFFSET-(512 << 20)-1) & 0x7fffffff
-                                        # (Header version 0x0203 or later)
-                                        # The highest safe address for
-                                        # the contents of an initrd
-
-kernel_alignment:  .long CONFIG_PHYSICAL_ALIGN  #physical addr alignment
-                                                #required for protected mode
-                                                #kernel
-#ifdef CONFIG_RELOCATABLE
-relocatable_kernel:    .byte 1
-#else
-relocatable_kernel:    .byte 0
-#endif
-pad2:                   .byte 0
-pad3:                   .word 0
-
-cmdline_size:   .long   COMMAND_LINE_SIZE-1     #length of the command line,
-                                                #added with boot protocol
-                                                #version 2.06
-
-trampoline:     call    start_of_setup
-                .align 16
-                                        # The offset at this point is 0x240
-                .space  (0xeff-0x240+1) # E820 & EDD space (ending at 0xeff)
-# End of setup header #####################################################
-
-start_of_setup:
-# Bootlin depends on this being done early
-        movw    $0x01500, %ax
-        movb    $0x81, %dl
-        int     $0x13
-
-#ifdef SAFE_RESET_DISK_CONTROLLER
-# Reset the disk controller.
-        movw    $0x0000, %ax
-        movb    $0x80, %dl
-        int     $0x13
-#endif
-
-# Set %ds = %cs, we know that SETUPSEG = %cs at this point
-        movw    %cs, %ax                # aka SETUPSEG
-        movw    %ax, %ds
-# Check signature at end of setup
-        cmpw    $SIG1, setup_sig1
-        jne     bad_sig
-
-        cmpw    $SIG2, setup_sig2
-        jne     bad_sig
-
-        jmp     good_sig1
-
-# Routine to print asciiz string at ds:si
-prtstr:
-        lodsb
-        andb    %al, %al
-        jz      fin
-
-        call    prtchr
-        jmp     prtstr
-
-fin:    ret
-
-# Space printing
-prtsp2: call    prtspc          # Print double space
-prtspc: movb    $0x20, %al      # Print single space (note: fall-thru)
-
-# Part of above routine, this one just prints ascii al
-prtchr: pushw   %ax
-        pushw   %cx
-        movw    $7,%bx
-        movw    $0x01, %cx
-        movb    $0x0e, %ah
-        int     $0x10
-        popw    %cx
-        popw    %ax
-        ret
-
-beep:   movb    $0x07, %al
-        jmp     prtchr
-        
-no_sig_mess: .string    "No setup signature found ..."
-
-good_sig1:
-        jmp     good_sig
-
-# We now have to find the rest of the setup code/data
-bad_sig:
-        movw    %cs, %ax                        # SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # INITSEG
-        movw    %ax, %ds
-        xorb    %bh, %bh
-        movb    (497), %bl                      # get setup sect from bootsect
-        subw    $4, %bx                         # LILO loads 4 sectors of setup
-        shlw    $8, %bx                         # convert to words (1sect=2^8 words)
-        movw    %bx, %cx
-        shrw    $3, %bx                         # convert to segment
-        addw    $SYSSEG, %bx
-        movw    %bx, %cs:start_sys_seg
-# Move rest of setup code/data to here
-        movw    $2048, %di                      # four sectors loaded by LILO
-        subw    %si, %si
-        pushw   %cs
-        popw    %es
-        movw    $SYSSEG, %ax
-        movw    %ax, %ds
-        rep
-        movsw
-        movw    %cs, %ax                        # aka SETUPSEG
-        movw    %ax, %ds
-        cmpw    $SIG1, setup_sig1
-        jne     no_sig
-
-        cmpw    $SIG2, setup_sig2
-        jne     no_sig
-
-        jmp     good_sig
-
-no_sig:
-        lea     no_sig_mess, %si
-        call    prtstr
-
-no_sig_loop:
-        hlt
-        jmp     no_sig_loop
-
-good_sig:
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %ds
-# Check if an old loader tries to load a big-kernel
-        testb   $LOADED_HIGH, %cs:loadflags     # Do we have a big kernel?
-        jz      loader_ok                       # No, no danger for old loaders.
-
-        cmpb    $0, %cs:type_of_loader          # Do we have a loader that
-                                                # can deal with us?
-        jnz     loader_ok                       # Yes, continue.
-
-        pushw   %cs                             # No, we have an old loader,
-        popw    %ds                             # die. 
-        lea     loader_panic_mess, %si
-        call    prtstr
-
-        jmp     no_sig_loop
-
-loader_panic_mess: .string "Wrong loader, giving up..."
-
-# check minimum cpuid
-# we do this here because it is the last place we can actually
-# show a user visible error message. Later the video modus
-# might be already messed up.
-loader_ok:
-        call verify_cpu
-        testl  %eax,%eax
-        jz      cpu_ok
-        movw    %cs,%ax         # aka SETUPSEG
-        movw    %ax,%ds
-        lea     cpu_panic_mess,%si
-        call    prtstr
-1:      jmp     1b
-
-cpu_panic_mess:
-        .asciz  "PANIC: CPU too old for this kernel."
-
-#include "../kernel/verify_cpu.S"
-
-cpu_ok:
-# Get memory size (extended mem, kB)
-
-        xorl    %eax, %eax
-        movl    %eax, (0x1e0)
-#ifndef STANDARD_MEMORY_BIOS_CALL
-        movb    %al, (E820NR)
-# Try three different memory detection schemes.  First, try
-# e820h, which lets us assemble a memory map, then try e801h,
-# which returns a 32-bit memory size, and finally 88h, which
-# returns 0-64m
-
-# method E820H:
-# the memory map from hell.  e820h returns memory classified into
-# a whole bunch of different types, and allows memory holes and
-# everything.  We scan through this memory map and build a list
-# of the first 32 memory areas, which we return at [E820MAP].
-# This is documented at http://www.acpi.info/, in the ACPI 2.0 specification.
-
-#define SMAP  0x534d4150
-
-meme820:
-        xorl    %ebx, %ebx                      # continuation counter
-        movw    $E820MAP, %di                   # point into the whitelist
-                                                # so we can have the bios
-                                                # directly write into it.
-
-jmpe820:
-        movl    $0x0000e820, %eax               # e820, upper word zeroed
-        movl    $SMAP, %edx                     # ascii 'SMAP'
-        movl    $20, %ecx                       # size of the e820rec
-        pushw   %ds                             # data record.
-        popw    %es
-        int     $0x15                           # make the call
-        jc      bail820                         # fall to e801 if it fails
-
-        cmpl    $SMAP, %eax                     # check the return is `SMAP'
-        jne     bail820                         # fall to e801 if it fails
-
-#       cmpl    $1, 16(%di)                     # is this usable memory?
-#       jne     again820
-
-        # If this is usable memory, we save it by simply advancing %di by
-        # sizeof(e820rec).
-        #
-good820:
-        movb    (E820NR), %al                   # up to 128 entries
-        cmpb    $E820MAX, %al
-        jae     bail820
-
-        incb    (E820NR)
-        movw    %di, %ax
-        addw    $20, %ax
-        movw    %ax, %di
-again820:
-        cmpl    $0, %ebx                        # check to see if
-        jne     jmpe820                         # %ebx is set to EOF
-bail820:
-
-
-# method E801H:
-# memory size is in 1k chunksizes, to avoid confusing loadlin.
-# we store the 0xe801 memory size in a completely different place,
-# because it will most likely be longer than 16 bits.
-# (use 1e0 because that's what Larry Augustine uses in his
-# alternative new memory detection scheme, and it's sensible
-# to write everything into the same place.)
-
-meme801:
-        stc                                     # fix to work around buggy
-        xorw    %cx,%cx                         # BIOSes which don't clear/set
-        xorw    %dx,%dx                         # carry on pass/error of
-                                                # e801h memory size call
-                                                # or merely pass cx,dx though
-                                                # without changing them.
-        movw    $0xe801, %ax
-        int     $0x15
-        jc      mem88
-
-        cmpw    $0x0, %cx                       # Kludge to handle BIOSes
-        jne     e801usecxdx                     # which report their extended
-        cmpw    $0x0, %dx                       # memory in AX/BX rather than
-        jne     e801usecxdx                     # CX/DX.  The spec I have read
-        movw    %ax, %cx                        # seems to indicate AX/BX 
-        movw    %bx, %dx                        # are more reasonable anyway...
-
-e801usecxdx:
-        andl    $0xffff, %edx                   # clear sign extend
-        shll    $6, %edx                        # and go from 64k to 1k chunks
-        movl    %edx, (0x1e0)                   # store extended memory size
-        andl    $0xffff, %ecx                   # clear sign extend
-        addl    %ecx, (0x1e0)                   # and add lower memory into
-                                                # total size.
-
-# Ye Olde Traditional Methode.  Returns the memory size (up to 16mb or
-# 64mb, depending on the bios) in ax.
-mem88:
-
-#endif
-        movb    $0x88, %ah
-        int     $0x15
-        movw    %ax, (2)
-
-# Set the keyboard repeat rate to the max
-        movw    $0x0305, %ax
-        xorw    %bx, %bx
-        int     $0x16
-
-# Check for video adapter and its parameters and allow the
-# user to browse video modes.
-        call    video                           # NOTE: we need %ds pointing
-                                                # to bootsector
-
-# Get hd0 data...
-        xorw    %ax, %ax
-        movw    %ax, %ds
-        ldsw    (4 * 0x41), %si
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        pushw   %ax
-        movw    %ax, %es
-        movw    $0x0080, %di
-        movw    $0x10, %cx
-        pushw   %cx
-        cld
-        rep
-        movsb
-# Get hd1 data...
-        xorw    %ax, %ax
-        movw    %ax, %ds
-        ldsw    (4 * 0x46), %si
-        popw    %cx
-        popw    %es
-        movw    $0x0090, %di
-        rep
-        movsb
-# Check that there IS a hd1 :-)
-        movw    $0x01500, %ax
-        movb    $0x81, %dl
-        int     $0x13
-        jc      no_disk1
-        
-        cmpb    $3, %ah
-        je      is_disk1
-
-no_disk1:
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %es
-        movw    $0x0090, %di
-        movw    $0x10, %cx
-        xorw    %ax, %ax
-        cld
-        rep
-        stosb
-is_disk1:
-# check for Micro Channel (MCA) bus
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %ds
-        xorw    %ax, %ax
-        movw    %ax, (0xa0)                     # set table length to 0
-        movb    $0xc0, %ah
-        stc
-        int     $0x15                           # moves feature table to es:bx
-        jc      no_mca
-
-        pushw   %ds
-        movw    %es, %ax
-        movw    %ax, %ds
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %es
-        movw    %bx, %si
-        movw    $0xa0, %di
-        movw    (%si), %cx
-        addw    $2, %cx                         # table length is a short
-        cmpw    $0x10, %cx
-        jc      sysdesc_ok
-
-        movw    $0x10, %cx                      # we keep only first 16 bytes
-sysdesc_ok:
-        rep
-        movsb
-        popw    %ds
-no_mca:
-#ifdef CONFIG_X86_VOYAGER
-        movb    $0xff, 0x40     # flag on config found
-        movb    $0xc0, %al
-        mov     $0xff, %ah
-        int     $0x15           # put voyager config info at es:di
-        jc      no_voyager
-        movw    $0x40, %si      # place voyager info in apm table
-        cld
-        movw    $7, %cx
-voyager_rep:
-        movb    %es:(%di), %al
-        movb    %al,(%si)
-        incw    %di
-        incw    %si
-        decw    %cx
-        jnz     voyager_rep
-no_voyager:     
-#endif
-# Check for PS/2 pointing device
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %ds
-        movb    $0, (0x1ff)                     # default is no pointing device
-        int     $0x11                           # int 0x11: equipment list
-        testb   $0x04, %al                      # check if mouse installed
-        jz      no_psmouse
-
-        movb    $0xAA, (0x1ff)                  # device present
-no_psmouse:
-
-#if defined(CONFIG_X86_SPEEDSTEP_SMI) || defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE)
-        movl    $0x0000E980, %eax               # IST Support 
-        movl    $0x47534943, %edx               # Request value
-        int     $0x15
-
-        movl    %eax, (96)
-        movl    %ebx, (100)
-        movl    %ecx, (104)
-        movl    %edx, (108)
-#endif
-
-#if defined(CONFIG_APM) || defined(CONFIG_APM_MODULE)
-# Then check for an APM BIOS...
-                                                # %ds points to the bootsector
-        movw    $0, 0x40                        # version = 0 means no APM BIOS
-        movw    $0x05300, %ax                   # APM BIOS installation check
-        xorw    %bx, %bx
-        int     $0x15
-        jc      done_apm_bios                   # Nope, no APM BIOS
-        
-        cmpw    $0x0504d, %bx                   # Check for "PM" signature
-        jne     done_apm_bios                   # No signature, no APM BIOS
-
-        andw    $0x02, %cx                      # Is 32 bit supported?
-        je      done_apm_bios                   # No 32-bit, no (good) APM BIOS
-
-        movw    $0x05304, %ax                   # Disconnect first just in case
-        xorw    %bx, %bx
-        int     $0x15                           # ignore return code
-        movw    $0x05303, %ax                   # 32 bit connect
-        xorl    %ebx, %ebx
-        xorw    %cx, %cx                        # paranoia :-)
-        xorw    %dx, %dx                        #   ...
-        xorl    %esi, %esi                      #   ...
-        xorw    %di, %di                        #   ...
-        int     $0x15
-        jc      no_32_apm_bios                  # Ack, error. 
-
-        movw    %ax,  (66)                      # BIOS code segment
-        movl    %ebx, (68)                      # BIOS entry point offset
-        movw    %cx,  (72)                      # BIOS 16 bit code segment
-        movw    %dx,  (74)                      # BIOS data segment
-        movl    %esi, (78)                      # BIOS code segment lengths
-        movw    %di,  (82)                      # BIOS data segment length
-# Redo the installation check as the 32 bit connect
-# modifies the flags returned on some BIOSs
-        movw    $0x05300, %ax                   # APM BIOS installation check
-        xorw    %bx, %bx
-        xorw    %cx, %cx                        # paranoia
-        int     $0x15
-        jc      apm_disconnect                  # error -> shouldn't happen
-
-        cmpw    $0x0504d, %bx                   # check for "PM" signature
-        jne     apm_disconnect                  # no sig -> shouldn't happen
-
-        movw    %ax, (64)                       # record the APM BIOS version
-        movw    %cx, (76)                       # and flags
-        jmp     done_apm_bios
-
-apm_disconnect:                                 # Tidy up
-        movw    $0x05304, %ax                   # Disconnect
-        xorw    %bx, %bx
-        int     $0x15                           # ignore return code
-
-        jmp     done_apm_bios
-
-no_32_apm_bios:
-        andw    $0xfffd, (76)                   # remove 32 bit support bit
-done_apm_bios:
-#endif
-
-#include "edd.S"
-
-# Now we want to move to protected mode ...
-        cmpw    $0, %cs:realmode_swtch
-        jz      rmodeswtch_normal
-
-        lcall   *%cs:realmode_swtch
-
-        jmp     rmodeswtch_end
-
-rmodeswtch_normal:
-        pushw   %cs
-        call    default_switch
-
-rmodeswtch_end:
-# Now we move the system to its rightful place ... but we check if we have a
-# big-kernel. In that case we *must* not move it ...
-        testb   $LOADED_HIGH, %cs:loadflags
-        jz      do_move0                        # .. then we have a normal low
-                                                # loaded zImage
-                                                # .. or else we have a high
-                                                # loaded bzImage
-        jmp     end_move                        # ... and we skip moving
-
-do_move0:
-        movw    $0x100, %ax                     # start of destination segment
-        movw    %cs, %bp                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %bp             # aka INITSEG
-        movw    %cs:start_sys_seg, %bx          # start of source segment
-        cld
-do_move:
-        movw    %ax, %es                        # destination segment
-        incb    %ah                             # instead of add ax,#0x100
-        movw    %bx, %ds                        # source segment
-        addw    $0x100, %bx
-        subw    %di, %di
-        subw    %si, %si
-        movw    $0x800, %cx
-        rep
-        movsw
-        cmpw    %bp, %bx                        # assume start_sys_seg > 0x200,
-                                                # so we will perhaps read one
-                                                # page more than needed, but
-                                                # never overwrite INITSEG
-                                                # because destination is a
-                                                # minimum one page below source
-        jb      do_move
-
-end_move:
-# then we load the segment descriptors
-        movw    %cs, %ax                        # aka SETUPSEG
-        movw    %ax, %ds
-                
-# Check whether we need to be downward compatible with version <=201
-        cmpl    $0, cmd_line_ptr
-        jne     end_move_self           # loader uses version >=202 features
-        cmpb    $0x20, type_of_loader
-        je      end_move_self           # bootsect loader, we know of it
-
-# Boot loader doesnt support boot protocol version 2.02.
-# If we have our code not at 0x90000, we need to move it there now.
-# We also then need to move the params behind it (commandline)
-# Because we would overwrite the code on the current IP, we move
-# it in two steps, jumping high after the first one.
-        movw    %cs, %ax
-        cmpw    $SETUPSEG, %ax
-        je      end_move_self
-
-        cli                                     # make sure we really have
-                                                # interrupts disabled !
-                                                # because after this the stack
-                                                # should not be used
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ss, %dx
-        cmpw    %ax, %dx
-        jb      move_self_1
-
-        addw    $INITSEG, %dx
-        subw    %ax, %dx                        # this will go into %ss after
-                                                # the move
-move_self_1:
-        movw    %ax, %ds
-        movw    $INITSEG, %ax                   # real INITSEG
-        movw    %ax, %es
-        movw    %cs:setup_move_size, %cx
-        std                                     # we have to move up, so we use
-                                                # direction down because the
-                                                # areas may overlap
-        movw    %cx, %di
-        decw    %di
-        movw    %di, %si
-        subw    $move_self_here+0x200, %cx
-        rep
-        movsb
-        ljmp    $SETUPSEG, $move_self_here
-
-move_self_here:
-        movw    $move_self_here+0x200, %cx
-        rep
-        movsb
-        movw    $SETUPSEG, %ax
-        movw    %ax, %ds
-        movw    %dx, %ss
-end_move_self:                                  # now we are at the right place
-
-#
-# Enable A20.  This is at the very best an annoying procedure.
-# A20 code ported from SYSLINUX 1.52-1.63 by H. Peter Anvin.
-# AMD Elan bug fix by Robert Schwebel.
-#
-
-#if defined(CONFIG_X86_ELAN)
-        movb $0x02, %al                 # alternate A20 gate
-        outb %al, $0x92                 # this works on SC410/SC520
-a20_elan_wait:
-        call a20_test
-        jz a20_elan_wait
-        jmp a20_done
-#endif
-
-
-A20_TEST_LOOPS          =  32           # Iterations per wait
-A20_ENABLE_LOOPS        = 255           # Total loops to try            
-
-
-#ifndef CONFIG_X86_VOYAGER
-a20_try_loop:
-
-        # First, see if we are on a system with no A20 gate.
-a20_none:
-        call    a20_test
-        jnz     a20_done
-
-        # Next, try the BIOS (INT 0x15, AX=0x2401)
-a20_bios:
-        movw    $0x2401, %ax
-        pushfl                                  # Be paranoid about flags
-        int     $0x15
-        popfl
-
-        call    a20_test
-        jnz     a20_done
-
-        # Try enabling A20 through the keyboard controller
-#endif /* CONFIG_X86_VOYAGER */
-a20_kbc:
-        call    empty_8042
-
-#ifndef CONFIG_X86_VOYAGER
-        call    a20_test                        # Just in case the BIOS worked
-        jnz     a20_done                        # but had a delayed reaction.
-#endif
-
-        movb    $0xD1, %al                      # command write
-        outb    %al, $0x64
-        call    empty_8042
-
-        movb    $0xDF, %al                      # A20 on
-        outb    %al, $0x60
-        call    empty_8042
-
-#ifndef CONFIG_X86_VOYAGER
-        # Wait until a20 really *is* enabled; it can take a fair amount of
-        # time on certain systems; Toshiba Tecras are known to have this
-        # problem.
-a20_kbc_wait:
-        xorw    %cx, %cx
-a20_kbc_wait_loop:
-        call    a20_test
-        jnz     a20_done
-        loop    a20_kbc_wait_loop
-
-        # Final attempt: use "configuration port A"
-a20_fast:
-        inb     $0x92, %al                      # Configuration Port A
-        orb     $0x02, %al                      # "fast A20" version
-        andb    $0xFE, %al                      # don't accidentally reset
-        outb    %al, $0x92
-
-        # Wait for configuration port A to take effect
-a20_fast_wait:
-        xorw    %cx, %cx
-a20_fast_wait_loop:
-        call    a20_test
-        jnz     a20_done
-        loop    a20_fast_wait_loop
-
-        # A20 is still not responding.  Try frobbing it again.
-        # 
-        decb    (a20_tries)
-        jnz     a20_try_loop
-        
-        movw    $a20_err_msg, %si
-        call    prtstr
-
-a20_die:
-        hlt
-        jmp     a20_die
-
-a20_tries:
-        .byte   A20_ENABLE_LOOPS
-
-a20_err_msg:
-        .ascii  "linux: fatal error: A20 gate not responding!"
-        .byte   13, 10, 0
-
-        # If we get here, all is good
-a20_done:
-
-#endif /* CONFIG_X86_VOYAGER */
-# set up gdt and idt and 32bit start address
-        lidt    idt_48                          # load idt with 0,0
-        xorl    %eax, %eax                      # Compute gdt_base
-        movw    %ds, %ax                        # (Convert %ds:gdt to a linear ptr)
-        shll    $4, %eax
-        addl    %eax, code32
-        addl    $gdt, %eax
-        movl    %eax, (gdt_48+2)
-        lgdt    gdt_48                          # load gdt with whatever is
-                                                # appropriate
-
-# make sure any possible coprocessor is properly reset..
-        xorw    %ax, %ax
-        outb    %al, $0xf0
-        call    delay
-
-        outb    %al, $0xf1
-        call    delay
-
-# well, that went ok, I hope. Now we mask all interrupts - the rest
-# is done in init_IRQ().
-        movb    $0xFF, %al                      # mask all interrupts for now
-        outb    %al, $0xA1
-        call    delay
-        
-        movb    $0xFB, %al                      # mask all irq's but irq2 which
-        outb    %al, $0x21                      # is cascaded
-
-# Well, that certainly wasn't fun :-(. Hopefully it works, and we don't
-# need no steenking BIOS anyway (except for the initial loading :-).
-# The BIOS-routine wants lots of unnecessary data, and it's less
-# "interesting" anyway. This is how REAL programmers do it.
-#
-# Well, now's the time to actually move into protected mode. To make
-# things as simple as possible, we do no register set-up or anything,
-# we let the gnu-compiled 32-bit programs do that. We just jump to
-# absolute address 0x1000 (or the loader supplied one),
-# in 32-bit protected mode.
-#
-# Note that the short jump isn't strictly needed, although there are
-# reasons why it might be a good idea. It won't hurt in any case.
-        movw    $1, %ax                         # protected mode (PE) bit
-        lmsw    %ax                             # This is it!
-        jmp     flush_instr
-
-flush_instr:
-        xorw    %bx, %bx                        # Flag to indicate a boot
-        xorl    %esi, %esi                      # Pointer to real-mode code
-        movw    %cs, %si
-        subw    $DELTA_INITSEG, %si
-        shll    $4, %esi                        # Convert to 32-bit pointer
-
-# jump to startup_32 in arch/i386/boot/compressed/head.S
-#       
-# NOTE: For high loaded big kernels we need a
-#       jmpi    0x100000,__BOOT_CS
-#
-#       but we yet haven't reloaded the CS register, so the default size 
-#       of the target offset still is 16 bit.
-#       However, using an operand prefix (0x66), the CPU will properly
-#       take our 48 bit far pointer. (INTeL 80386 Programmer's Reference
-#       Manual, Mixing 16-bit and 32-bit code, page 16-6)
-
-        .byte 0x66, 0xea                        # prefix + jmpi-opcode
-code32: .long   startup_32                      # will be set to %cs+startup_32
-        .word   __BOOT_CS
-.code32
-startup_32:
-        movl $(__BOOT_DS), %eax
-        movl %eax, %ds
-        movl %eax, %es
-        movl %eax, %fs
-        movl %eax, %gs
-        movl %eax, %ss
-
-        xorl %eax, %eax
-1:      incl %eax                               # check that A20 really IS enabled
-        movl %eax, 0x00000000                   # loop forever if it isn't
-        cmpl %eax, 0x00100000
-        je 1b
-
-        # Jump to the 32bit entry point
-        jmpl *(code32_start - start + (DELTA_INITSEG << 4))(%esi)
-.code16
-
-# Here's a bunch of information about your current kernel..
-kernel_version: .ascii  UTS_RELEASE
-                .ascii  " ("
-                .ascii  LINUX_COMPILE_BY
-                .ascii  "@"
-                .ascii  LINUX_COMPILE_HOST
-                .ascii  ") "
-                .ascii  UTS_VERSION
-                .byte   0
-
-# This is the default real mode switch routine.
-# to be called just before protected mode transition
-default_switch:
-        cli                                     # no interrupts allowed !
-        movb    $0x80, %al                      # disable NMI for bootup
-                                                # sequence
-        outb    %al, $0x70
-        lret
-
-
-#ifndef CONFIG_X86_VOYAGER
-# This routine tests whether or not A20 is enabled.  If so, it
-# exits with zf = 0.
-#
-# The memory address used, 0x200, is the int $0x80 vector, which
-# should be safe.
-
-A20_TEST_ADDR = 4*0x80
-
-a20_test:
-        pushw   %cx
-        pushw   %ax
-        xorw    %cx, %cx
-        movw    %cx, %fs                        # Low memory
-        decw    %cx
-        movw    %cx, %gs                        # High memory area
-        movw    $A20_TEST_LOOPS, %cx
-        movw    %fs:(A20_TEST_ADDR), %ax
-        pushw   %ax
-a20_test_wait:
-        incw    %ax
-        movw    %ax, %fs:(A20_TEST_ADDR)
-        call    delay                           # Serialize and make delay constant
-        cmpw    %gs:(A20_TEST_ADDR+0x10), %ax
-        loope   a20_test_wait
-
-        popw    %fs:(A20_TEST_ADDR)
-        popw    %ax
-        popw    %cx
-        ret     
-
-#endif /* CONFIG_X86_VOYAGER */
-
-# This routine checks that the keyboard command queue is empty
-# (after emptying the output buffers)
-#
-# Some machines have delusions that the keyboard buffer is always full
-# with no keyboard attached...
-#
-# If there is no keyboard controller, we will usually get 0xff
-# to all the reads.  With each IO taking a microsecond and
-# a timeout of 100,000 iterations, this can take about half a
-# second ("delay" == outb to port 0x80). That should be ok,
-# and should also be plenty of time for a real keyboard controller
-# to empty.
-#
-
-empty_8042:
-        pushl   %ecx
-        movl    $100000, %ecx
-
-empty_8042_loop:
-        decl    %ecx
-        jz      empty_8042_end_loop
-
-        call    delay
-
-        inb     $0x64, %al                      # 8042 status port
-        testb   $1, %al                         # output buffer?
-        jz      no_output
-
-        call    delay
-        inb     $0x60, %al                      # read it
-        jmp     empty_8042_loop
-
-no_output:
-        testb   $2, %al                         # is input buffer full?
-        jnz     empty_8042_loop                 # yes - loop
-empty_8042_end_loop:
-        popl    %ecx
-        ret
-
-# Read the cmos clock. Return the seconds in al
-gettime:
-        pushw   %cx
-        movb    $0x02, %ah
-        int     $0x1a
-        movb    %dh, %al                        # %dh contains the seconds
-        andb    $0x0f, %al
-        movb    %dh, %ah
-        movb    $0x04, %cl
-        shrb    %cl, %ah
-        aad
-        popw    %cx
-        ret
-
-# Delay is needed after doing I/O
-delay:
-        outb    %al,$0x80
-        ret
-
-# Descriptor tables
-#
-# NOTE: The intel manual says gdt should be sixteen bytes aligned for
-# efficiency reasons.  However, there are machines which are known not
-# to boot with misaligned GDTs, so alter this at your peril!  If you alter
-# GDT_ENTRY_BOOT_CS (in asm/segment.h) remember to leave at least two
-# empty GDT entries (one for NULL and one reserved).
-#
-# NOTE: On some CPUs, the GDT must be 8 byte aligned.  This is
-# true for the Voyager Quad CPU card which will not boot without
-# This directive.  16 byte aligment is recommended by intel.
-#
-        .align 16
-gdt:
-        .fill GDT_ENTRY_BOOT_CS,8,0
-
-        .word   0xFFFF                          # 4Gb - (0x100000*0x1000 = 4Gb)
-        .word   0                               # base address = 0
-        .word   0x9A00                          # code read/exec
-        .word   0x00CF                          # granularity = 4096, 386
-                                                #  (+5th nibble of limit)
-
-        .word   0xFFFF                          # 4Gb - (0x100000*0x1000 = 4Gb)
-        .word   0                               # base address = 0
-        .word   0x9200                          # data read/write
-        .word   0x00CF                          # granularity = 4096, 386
-                                                #  (+5th nibble of limit)
-gdt_end:
-        .align  4
-        
-        .word   0                               # alignment byte
-idt_48:
-        .word   0                               # idt limit = 0
-        .word   0, 0                            # idt base = 0L
-
-        .word   0                               # alignment byte
-gdt_48:
-        .word   gdt_end - gdt - 1               # gdt limit
-        .word   0, 0                            # gdt base (filled in later)
-
-# Include video setup & detection code
-
-#include "video.S"
-
-# Setup signature -- must be last
-setup_sig1:     .word   SIG1
-setup_sig2:     .word   SIG2
-
-# After this point, there is some free space which is used by the video mode
-# handling code to store the temporary mode table (not used by the kernel).
-
-modelist:
-
-.text
-endtext:
-.data
-enddata:
-.bss
-endbss:
diff --git a/arch/i386/boot/setup.ld b/arch/i386/boot/setup.ld
new file mode 100644
index 000000000000..df9234b3a5e0
--- /dev/null
+++ b/arch/i386/boot/setup.ld
@@ -0,0 +1,54 @@
+/*
+ * setup.ld
+ *
+ * Linker script for the i386 setup code
+ */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+        . = 0;
+        .bstext         : { *(.bstext) }
+        .bsdata         : { *(.bsdata) }
+
+        . = 497;
+        .header         : { *(.header) }
+        .inittext       : { *(.inittext) }
+        .initdata       : { *(.initdata) }
+        .text           : { *(.text*) }
+
+        . = ALIGN(16);
+        .rodata         : { *(.rodata*) }
+
+        .videocards     : {
+                video_cards = .;
+                *(.videocards)
+                video_cards_end = .;
+        }
+
+        . = ALIGN(16);
+        .data           : { *(.data*) }
+
+        .signature      : {
+                setup_sig = .;
+                LONG(0x5a5aaa55)
+        }
+
+
+        . = ALIGN(16);
+        .bss            :
+        {
+                __bss_start = .;
+                *(.bss)
+                __bss_end = .;
+        }
+        . = ALIGN(16);
+        _end = .;
+
+        /DISCARD/ : { *(.note*) }
+
+        . = ASSERT(_end <= 0x8000, "Setup too big!");
+        . = ASSERT(hdr == 0x1f1, "The setup header has the wrong offset!");
+}
diff --git a/arch/i386/boot/string.c b/arch/i386/boot/string.c
new file mode 100644
index 000000000000..481a22097781
--- /dev/null
+++ b/arch/i386/boot/string.c
@@ -0,0 +1,52 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/string.c
+ *
+ * Very basic string functions
+ */
+
+#include "boot.h"
+
+int strcmp(const char *str1, const char *str2)
+{
+        const unsigned char *s1 = (const unsigned char *)str1;
+        const unsigned char *s2 = (const unsigned char *)str2;
+        int delta = 0;
+
+        while (*s1 || *s2) {
+                delta = *s2 - *s1;
+                if (delta)
+                        return delta;
+                s1++;
+                s2++;
+        }
+        return 0;
+}
+
+size_t strnlen(const char *s, size_t maxlen)
+{
+        const char *es = s;
+        while (*es && maxlen) {
+                es++;
+                maxlen--;
+        }
+
+        return (es - s);
+}
+
+unsigned int atou(const char *s)
+{
+        unsigned int i = 0;
+        while (isdigit(*s))
+                i = i * 10 + (*s++ - '0');
+        return i;
+}
diff --git a/arch/i386/boot/tools/build.c b/arch/i386/boot/tools/build.c
index 05798419a6a9..886f47d8a488 100644
--- a/arch/i386/boot/tools/build.c
+++ b/arch/i386/boot/tools/build.c
@@ -1,13 +1,12 @@
 /*
  *  Copyright (C) 1991, 1992  Linus Torvalds
  *  Copyright (C) 1997 Martin Mares
+ *  Copyright (C) 2007 H. Peter Anvin
  */
 
 /*
  * This file builds a disk-image from three different files:
  *
- * - bootsect: compatibility mbr which prints an error message if
- *             someone tries to boot the kernel directly.
  * - setup: 8086 machine code, sets up system parm
  * - system: 80386 code for actual system
  *
@@ -21,6 +20,7 @@
  * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
  * Cross compiling fixes by Gertjan van Wingerde, July 1996
  * Rewritten by Martin Mares, April 1997
+ * Substantially overhauled by H. Peter Anvin, April 2007
  */
 
 #include <stdio.h>
@@ -32,23 +32,25 @@
 #include <sys/sysmacros.h>
 #include <unistd.h>
 #include <fcntl.h>
+#include <sys/mman.h>
 #include <asm/boot.h>
 
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long u32;
+typedef unsigned char  u8;
+typedef unsigned short u16;
+typedef unsigned long  u32;
 
 #define DEFAULT_MAJOR_ROOT 0
 #define DEFAULT_MINOR_ROOT 0
 
-/* Minimal number of setup sectors (see also bootsect.S) */
-#define SETUP_SECTS 4
+/* Minimal number of setup sectors */
+#define SETUP_SECT_MIN 5
+#define SETUP_SECT_MAX 64
 
-byte buf[1024];
-int fd;
+/* This must be large enough to hold the entire setup */
+u8 buf[SETUP_SECT_MAX*512];
 int is_big_kernel;
 
-void die(const char * str, ...)
+static void die(const char * str, ...)
 {
         va_list args;
         va_start(args, str);
@@ -57,15 +59,9 @@ void die(const char * str, ...)
         exit(1);
 }
 
-void file_open(const char *name)
+static void usage(void)
 {
-        if ((fd = open(name, O_RDONLY, 0)) < 0)
-                die("Unable to open `%s': %m", name);
-}
-
-void usage(void)
-{
-        die("Usage: build [-b] bootsect setup system [rootdev] [> image]");
+        die("Usage: build [-b] setup system [rootdev] [> image]");
 }
 
 int main(int argc, char ** argv)
@@ -73,27 +69,30 @@ int main(int argc, char ** argv)
         unsigned int i, sz, setup_sectors;
         int c;
         u32 sys_size;
-        byte major_root, minor_root;
+        u8 major_root, minor_root;
         struct stat sb;
+        FILE *file;
+        int fd;
+        void *kernel;
 
         if (argc > 2 && !strcmp(argv[1], "-b"))
           {
             is_big_kernel = 1;
             argc--, argv++;
           }
-        if ((argc < 4) || (argc > 5))
+        if ((argc < 3) || (argc > 4))
                 usage();
-        if (argc > 4) {
-                if (!strcmp(argv[4], "CURRENT")) {
+        if (argc > 3) {
+                if (!strcmp(argv[3], "CURRENT")) {
                         if (stat("/", &sb)) {
                                 perror("/");
                                 die("Couldn't stat /");
                         }
                         major_root = major(sb.st_dev);
                         minor_root = minor(sb.st_dev);
-                } else if (strcmp(argv[4], "FLOPPY")) {
-                        if (stat(argv[4], &sb)) {
-                                perror(argv[4]);
+                } else if (strcmp(argv[3], "FLOPPY")) {
+                        if (stat(argv[3], &sb)) {
+                                perror(argv[3]);
                                 die("Couldn't stat root device.");
                         }
                         major_root = major(sb.st_rdev);
@@ -108,79 +107,62 @@ int main(int argc, char ** argv)
         }
         fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
 
-        file_open(argv[1]);
-        i = read(fd, buf, sizeof(buf));
-        fprintf(stderr,"Boot sector %d bytes.\n",i);
-        if (i != 512)
-                die("Boot block must be exactly 512 bytes");
+        /* Copy the setup code */
+        file = fopen(argv[1], "r");
+        if (!file)
+                die("Unable to open `%s': %m", argv[1]);
+        c = fread(buf, 1, sizeof(buf), file);
+        if (ferror(file))
+                die("read-error on `setup'");
+        if (c < 1024)
+                die("The setup must be at least 1024 bytes");
         if (buf[510] != 0x55 || buf[511] != 0xaa)
                 die("Boot block hasn't got boot flag (0xAA55)");
+        fclose(file);
+
+        /* Pad unused space with zeros */
+        setup_sectors = (c + 511) / 512;
+        if (setup_sectors < SETUP_SECT_MIN)
+                setup_sectors = SETUP_SECT_MIN;
+        i = setup_sectors*512;
+        memset(buf+c, 0, i-c);
+
+        /* Set the default root device */
         buf[508] = minor_root;
         buf[509] = major_root;
-        if (write(1, buf, 512) != 512)
-                die("Write call failed");
-        close (fd);
-
-        file_open(argv[2]);                                 /* Copy the setup code */
-        for (i=0 ; (c=read(fd, buf, sizeof(buf)))>0 ; i+=c )
-                if (write(1, buf, c) != c)
-                        die("Write call failed");
-        if (c != 0)
-                die("read-error on `setup'");
-        close (fd);
-
-        setup_sectors = (i + 511) / 512;        /* Pad unused space with zeros */
-        /* for compatibility with ancient versions of LILO. */
-        if (setup_sectors < SETUP_SECTS)
-                setup_sectors = SETUP_SECTS;
-        fprintf(stderr, "Setup is %d bytes.\n", i);
-        memset(buf, 0, sizeof(buf));
-        while (i < setup_sectors * 512) {
-                c = setup_sectors * 512 - i;
-                if (c > sizeof(buf))
-                        c = sizeof(buf);
-                if (write(1, buf, c) != c)
-                        die("Write call failed");
-                i += c;
-        }
 
-        file_open(argv[3]);
-        if (fstat (fd, &sb))
-                die("Unable to stat `%s': %m", argv[3]);
+        fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i);
+
+        /* Open and stat the kernel file */
+        fd = open(argv[2], O_RDONLY);
+        if (fd < 0)
+                die("Unable to open `%s': %m", argv[2]);
+        if (fstat(fd, &sb))
+                die("Unable to stat `%s': %m", argv[2]);
         sz = sb.st_size;
-        fprintf (stderr, "System is %d kB\n", sz/1024);
+        fprintf (stderr, "System is %d kB\n", (sz+1023)/1024);
+        kernel = mmap(NULL, sz, PROT_READ, MAP_SHARED, fd, 0);
+        if (kernel == MAP_FAILED)
+                die("Unable to mmap '%s': %m", argv[2]);
         sys_size = (sz + 15) / 16;
         if (!is_big_kernel && sys_size > DEF_SYSSIZE)
                 die("System is too big. Try using bzImage or modules.");
-        while (sz > 0) {
-                int l, n;
-
-                l = (sz > sizeof(buf)) ? sizeof(buf) : sz;
-                if ((n=read(fd, buf, l)) != l) {
-                        if (n < 0)
-                                die("Error reading %s: %m", argv[3]);
-                        else
-                                die("%s: Unexpected EOF", argv[3]);
-                }
-                if (write(1, buf, l) != l)
-                        die("Write failed");
-                sz -= l;
-        }
+
+        /* Patch the setup code with the appropriate size parameters */
+        buf[0x1f1] = setup_sectors-1;
+        buf[0x1f4] = sys_size;
+        buf[0x1f5] = sys_size >> 8;
+        buf[0x1f6] = sys_size >> 16;
+        buf[0x1f7] = sys_size >> 24;
+
+        if (fwrite(buf, 1, i, stdout) != i)
+                die("Writing setup failed");
+
+        /* Copy the kernel code */
+        if (fwrite(kernel, 1, sz, stdout) != sz)
+                die("Writing kernel failed");
         close(fd);
 
-        if (lseek(1, 497, SEEK_SET) != 497)                 /* Write sizes to the bootsector */
-                die("Output: seek failed");
-        buf[0] = setup_sectors;
-        if (write(1, buf, 1) != 1)
-                die("Write of setup sector count failed");
-        if (lseek(1, 500, SEEK_SET) != 500)
-                die("Output: seek failed");
-        buf[0] = (sys_size & 0xff);
-        buf[1] = ((sys_size >> 8) & 0xff);
-        buf[2] = ((sys_size >> 16) & 0xff);
-        buf[3] = ((sys_size >> 24) & 0xff);
-        if (write(1, buf, 4) != 4)
-                die("Write of image length failed");
-
-        return 0;                                           /* Everything is OK */
+        /* Everything is OK */
+        return 0;
 }
diff --git a/arch/i386/boot/tty.c b/arch/i386/boot/tty.c
new file mode 100644
index 000000000000..a8db78736b02
--- /dev/null
+++ b/arch/i386/boot/tty.c
@@ -0,0 +1,112 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/tty.c
+ *
+ * Very simple screen I/O
+ * XXX: Probably should add very simple serial I/O?
+ */
+
+#include "boot.h"
+
+/*
+ * These functions are in .inittext so they can be used to signal
+ * error during initialization.
+ */
+
+void __attribute__((section(".inittext"))) putchar(int ch)
+{
+        unsigned char c = ch;
+
+        if (c == '\n')
+                putchar('\r');  /* \n -> \r\n */
+
+        /* int $0x10 is known to have bugs involving touching registers
+           it shouldn't.  Be extra conservative... */
+        asm volatile("pushal; int $0x10; popal"
+                     : : "b" (0x0007), "c" (0x0001), "a" (0x0e00|ch));
+}
+
+void __attribute__((section(".inittext"))) puts(const char *str)
+{
+        int n = 0;
+        while (*str) {
+                putchar(*str++);
+                n++;
+        }
+}
+
+/*
+ * Read the CMOS clock through the BIOS, and return the
+ * seconds in BCD.
+ */
+
+static u8 gettime(void)
+{
+        u16 ax = 0x0200;
+        u16 cx, dx;
+
+        asm("int $0x1a"
+            : "+a" (ax), "=c" (cx), "=d" (dx)
+            : : "ebx", "esi", "edi");
+
+        return dx >> 8;
+}
+
+/*
+ * Read from the keyboard
+ */
+int getchar(void)
+{
+        u16 ax = 0;
+        asm("int $0x16" : "+a" (ax));
+
+        return ax & 0xff;
+}
+
+static int kbd_pending(void)
+{
+        u8 pending;
+        asm("int $0x16; setnz %0"
+            : "=rm" (pending)
+            : "a" (0x0100));
+        return pending;
+}
+
+void kbd_flush(void)
+{
+        for (;;) {
+                if (!kbd_pending())
+                        break;
+                getchar();
+        }
+}
+
+int getchar_timeout(void)
+{
+        int cnt = 30;
+        int t0, t1;
+
+        t0 = gettime();
+
+        while (cnt) {
+                if (kbd_pending())
+                        return getchar();
+
+                t1 = gettime();
+                if (t0 != t1) {
+                        cnt--;
+                        t0 = t1;
+                }
+        }
+
+        return 0;               /* Timeout! */
+}
diff --git a/arch/i386/boot/version.c b/arch/i386/boot/version.c
new file mode 100644
index 000000000000..c61462f7d9a7
--- /dev/null
+++ b/arch/i386/boot/version.c
@@ -0,0 +1,23 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/version.c
+ *
+ * Kernel version string
+ */
+
+#include "boot.h"
+#include <linux/utsrelease.h>
+#include <linux/compile.h>
+
+const char kernel_version[] =
+        UTS_RELEASE " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") "
+        UTS_VERSION;
diff --git a/arch/i386/boot/vesa.h b/arch/i386/boot/vesa.h
new file mode 100644
index 000000000000..ff5b73cd406f
--- /dev/null
+++ b/arch/i386/boot/vesa.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------- *
+ *
+ *   Copyright 1999-2007 H. Peter Anvin - All Rights Reserved
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
+ *   Boston MA 02111-1307, USA; either version 2 of the License, or
+ *   (at your option) any later version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+#ifndef BOOT_VESA_H
+#define BOOT_VESA_H
+
+typedef struct {
+        u16 off, seg;
+} far_ptr;
+
+/* VESA General Information table */
+struct vesa_general_info {
+        u32 signature;          /* 0 Magic number = "VESA" */
+        u16 version;            /* 4 */
+        far_ptr vendor_string;  /* 6 */
+        u32 capabilities;       /* 10 */
+        far_ptr video_mode_ptr; /* 14 */
+        u16 total_memory;       /* 18 */
+
+        u16 oem_software_rev;   /* 20 */
+        far_ptr oem_vendor_name_ptr;    /* 22 */
+        far_ptr oem_product_name_ptr;   /* 26 */
+        far_ptr oem_product_rev_ptr;    /* 30 */
+
+        u8 reserved[222];       /* 34 */
+        u8 oem_data[256];       /* 256 */
+} __attribute__ ((packed));
+
+#define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
+#define VBE2_MAGIC ('V' + ('B' << 8) + ('E' << 16) + ('2' << 24))
+
+struct vesa_mode_info {
+        u16 mode_attr;          /* 0 */
+        u8 win_attr[2];         /* 2 */
+        u16 win_grain;          /* 4 */
+        u16 win_size;           /* 6 */
+        u16 win_seg[2];         /* 8 */
+        far_ptr win_scheme;     /* 12 */
+        u16 logical_scan;       /* 16 */
+
+        u16 h_res;              /* 18 */
+        u16 v_res;              /* 20 */
+        u8 char_width;          /* 22 */
+        u8 char_height;         /* 23 */
+        u8 memory_planes;       /* 24 */
+        u8 bpp;                 /* 25 */
+        u8 banks;               /* 26 */
+        u8 memory_layout;       /* 27 */
+        u8 bank_size;           /* 28 */
+        u8 image_planes;        /* 29 */
+        u8 page_function;       /* 30 */
+
+        u8 rmask;               /* 31 */
+        u8 rpos;                /* 32 */
+        u8 gmask;               /* 33 */
+        u8 gpos;                /* 34 */
+        u8 bmask;               /* 35 */
+        u8 bpos;                /* 36 */
+        u8 resv_mask;           /* 37 */
+        u8 resv_pos;            /* 38 */
+        u8 dcm_info;            /* 39 */
+
+        u32 lfb_ptr;            /* 40 Linear frame buffer address */
+        u32 offscreen_ptr;      /* 44 Offscreen memory address */
+        u16 offscreen_size;     /* 48 */
+
+        u8 reserved[206];       /* 50 */
+} __attribute__ ((packed));
+
+#endif                          /* LIB_SYS_VESA_H */
diff --git a/arch/i386/boot/video-bios.c b/arch/i386/boot/video-bios.c
new file mode 100644
index 000000000000..afea46c500cc
--- /dev/null
+++ b/arch/i386/boot/video-bios.c
@@ -0,0 +1,125 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/video-bios.c
+ *
+ * Standard video BIOS modes
+ *
+ * We have two options for this; silent and scanned.
+ */
+
+#include "boot.h"
+#include "video.h"
+
+__videocard video_bios;
+
+/* Set a conventional BIOS mode */
+static int set_bios_mode(u8 mode);
+
+static int bios_set_mode(struct mode_info *mi)
+{
+        return set_bios_mode(mi->mode - VIDEO_FIRST_BIOS);
+}
+
+static int set_bios_mode(u8 mode)
+{
+        u16 ax;
+        u8 new_mode;
+
+        ax = mode;              /* AH=0x00 Set Video Mode */
+        asm volatile(INT10
+                     : "+a" (ax)
+                     : : "ebx", "ecx", "edx", "esi", "edi");
+
+        ax = 0x0f00;            /* Get Current Video Mode */
+        asm volatile(INT10
+                     : "+a" (ax)
+                     : : "ebx", "ecx", "edx", "esi", "edi");
+
+        do_restore = 1;         /* Assume video contents was lost */
+        new_mode = ax & 0x7f;   /* Not all BIOSes are clean with the top bit */
+
+        if (new_mode == mode)
+                return 0;       /* Mode change OK */
+
+        if (new_mode != boot_params.screen_info.orig_video_mode) {
+                /* Mode setting failed, but we didn't end up where we
+                   started.  That's bad.  Try to revert to the original
+                   video mode. */
+                ax = boot_params.screen_info.orig_video_mode;
+                asm volatile(INT10
+                             : "+a" (ax)
+                             : : "ebx", "ecx", "edx", "esi", "edi");
+        }
+        return -1;
+}
+
+static int bios_probe(void)
+{
+        u8 mode;
+        u8 saved_mode = boot_params.screen_info.orig_video_mode;
+        u16 crtc;
+        struct mode_info *mi;
+        int nmodes = 0;
+
+        if (adapter != ADAPTER_EGA && adapter != ADAPTER_VGA)
+                return 0;
+
+        set_fs(0);
+        crtc = vga_crtc();
+
+        video_bios.modes = GET_HEAP(struct mode_info, 0);
+
+        for (mode = 0x14; mode <= 0x7f; mode++) {
+                if (heap_free() < sizeof(struct mode_info))
+                        break;
+
+                if (mode_defined(VIDEO_FIRST_BIOS+mode))
+                        continue;
+
+                if (set_bios_mode(mode))
+                        continue;
+
+                /* Try to verify that it's a text mode. */
+
+                /* Attribute Controller: make graphics controller disabled */
+                if (in_idx(0x3c0, 0x10) & 0x01)
+                        continue;
+
+                /* Graphics Controller: verify Alpha addressing enabled */
+                if (in_idx(0x3ce, 0x06) & 0x01)
+                        continue;
+
+                /* CRTC cursor location low should be zero(?) */
+                if (in_idx(crtc, 0x0f))
+                        continue;
+
+                mi = GET_HEAP(struct mode_info, 1);
+                mi->mode = VIDEO_FIRST_BIOS+mode;
+                mi->x = rdfs16(0x44a);
+                mi->y = rdfs8(0x484)+1;
+                nmodes++;
+        }
+
+        set_bios_mode(saved_mode);
+
+        return nmodes;
+}
+
+__videocard video_bios =
+{
+        .card_name      = "BIOS (scanned)",
+        .probe          = bios_probe,
+        .set_mode       = bios_set_mode,
+        .unsafe         = 1,
+        .xmode_first    = VIDEO_FIRST_BIOS,
+        .xmode_n        = 0x80,
+};
diff --git a/arch/i386/boot/video-vesa.c b/arch/i386/boot/video-vesa.c
new file mode 100644
index 000000000000..e6aa9eb8d93a
--- /dev/null
+++ b/arch/i386/boot/video-vesa.c
@@ -0,0 +1,284 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/video-vesa.c
+ *
+ * VESA text modes
+ */
+
+#include "boot.h"
+#include "video.h"
+#include "vesa.h"
+
+/* VESA information */
+static struct vesa_general_info vginfo;
+static struct vesa_mode_info vminfo;
+
+__videocard video_vesa;
+
+static void vesa_store_mode_params_graphics(void);
+
+static int vesa_probe(void)
+{
+#if defined(CONFIG_VIDEO_VESA) || defined(CONFIG_FIRMWARE_EDID)
+        u16 ax;
+        u16 mode;
+        addr_t mode_ptr;
+        struct mode_info *mi;
+        int nmodes = 0;
+
+        video_vesa.modes = GET_HEAP(struct mode_info, 0);
+
+        vginfo.signature = VBE2_MAGIC;
+
+        /* Optimistically assume a VESA BIOS is register-clean... */
+        ax = 0x4f00;
+        asm("int $0x10" : "+a" (ax), "=m" (vginfo) : "D" (&vginfo));
+
+        if (ax != 0x004f ||
+            vginfo.signature != VESA_MAGIC ||
+            vginfo.version < 0x0102)
+                return 0;       /* Not present */
+#endif /* CONFIG_VIDEO_VESA || CONFIG_FIRMWARE_EDID */
+#ifdef CONFIG_VIDEO_VESA
+        set_fs(vginfo.video_mode_ptr.seg);
+        mode_ptr = vginfo.video_mode_ptr.off;
+
+        while ((mode = rdfs16(mode_ptr)) != 0xffff) {
+                mode_ptr += 2;
+
+                if (heap_free() < sizeof(struct mode_info))
+                        break;  /* Heap full, can't save mode info */
+
+                if (mode & ~0x1ff)
+                        continue;
+
+                memset(&vminfo, 0, sizeof vminfo); /* Just in case... */
+
+                ax = 0x4f01;
+                asm("int $0x10"
+                    : "+a" (ax), "=m" (vminfo)
+                    : "c" (mode), "D" (&vminfo));
+
+                if (ax != 0x004f)
+                        continue;
+
+                if ((vminfo.mode_attr & 0x15) == 0x05) {
+                        /* Text Mode, TTY BIOS supported,
+                           supported by hardware */
+                        mi = GET_HEAP(struct mode_info, 1);
+                        mi->mode = mode + VIDEO_FIRST_VESA;
+                        mi->x    = vminfo.h_res;
+                        mi->y    = vminfo.v_res;
+                        nmodes++;
+                } else if ((vminfo.mode_attr & 0x99) == 0x99) {
+#ifdef CONFIG_FB
+                        /* Graphics mode, color, linear frame buffer
+                           supported -- register the mode but hide from
+                           the menu.  Only do this if framebuffer is
+                           configured, however, otherwise the user will
+                           be left without a screen. */
+                        mi = GET_HEAP(struct mode_info, 1);
+                        mi->mode = mode + VIDEO_FIRST_VESA;
+                        mi->x = mi->y = 0;
+                        nmodes++;
+#endif
+                }
+        }
+
+        return nmodes;
+#else
+        return 0;
+#endif /* CONFIG_VIDEO_VESA */
+}
+
+static int vesa_set_mode(struct mode_info *mode)
+{
+        u16 ax;
+        int is_graphic;
+        u16 vesa_mode = mode->mode - VIDEO_FIRST_VESA;
+
+        memset(&vminfo, 0, sizeof vminfo); /* Just in case... */
+
+        ax = 0x4f01;
+        asm("int $0x10"
+            : "+a" (ax), "=m" (vminfo)
+            : "c" (vesa_mode), "D" (&vminfo));
+
+        if (ax != 0x004f)
+                return -1;
+
+        if ((vminfo.mode_attr & 0x15) == 0x05) {
+                /* It's a supported text mode */
+                is_graphic = 0;
+        } else if ((vminfo.mode_attr & 0x99) == 0x99) {
+                /* It's a graphics mode with linear frame buffer */
+                is_graphic = 1;
+                vesa_mode |= 0x4000; /* Request linear frame buffer */
+        } else {
+                return -1;      /* Invalid mode */
+        }
+
+
+        ax = 0x4f02;
+        asm volatile("int $0x10"
+                     : "+a" (ax)
+                     : "b" (vesa_mode), "D" (0));
+
+        if (ax != 0x004f)
+                return -1;
+
+        graphic_mode = is_graphic;
+        if (!is_graphic) {
+                /* Text mode */
+                force_x = mode->x;
+                force_y = mode->y;
+                do_restore = 1;
+        } else {
+                /* Graphics mode */
+                vesa_store_mode_params_graphics();
+        }
+
+        return 0;
+}
+
+
+/* Switch DAC to 8-bit mode */
+static void vesa_dac_set_8bits(void)
+{
+        u8 dac_size = 6;
+
+        /* If possible, switch the DAC to 8-bit mode */
+        if (vginfo.capabilities & 1) {
+                u16 ax, bx;
+
+                ax = 0x4f08;
+                bx = 0x0800;
+                asm volatile(INT10
+                             : "+a" (ax), "+b" (bx)
+                             : : "ecx", "edx", "esi", "edi");
+
+                if (ax == 0x004f)
+                        dac_size = bx >> 8;
+        }
+
+        /* Set the color sizes to the DAC size, and offsets to 0 */
+        boot_params.screen_info.red_size = dac_size;
+        boot_params.screen_info.green_size = dac_size;
+        boot_params.screen_info.blue_size = dac_size;
+        boot_params.screen_info.rsvd_size = dac_size;
+
+        boot_params.screen_info.red_pos = 0;
+        boot_params.screen_info.green_pos = 0;
+        boot_params.screen_info.blue_pos = 0;
+        boot_params.screen_info.rsvd_pos = 0;
+}
+
+/* Save the VESA protected mode info */
+static void vesa_store_pm_info(void)
+{
+        u16 ax, bx, di, es;
+
+        ax = 0x4f0a;
+        bx = di = 0;
+        asm("pushw %%es; "INT10"; movw %%es,%0; popw %%es"
+            : "=d" (es), "+a" (ax), "+b" (bx), "+D" (di)
+            : : "ecx", "esi");
+
+        if (ax != 0x004f)
+                return;
+
+        boot_params.screen_info.vesapm_seg = es;
+        boot_params.screen_info.vesapm_off = di;
+}
+
+/*
+ * Save video mode parameters for graphics mode
+ */
+static void vesa_store_mode_params_graphics(void)
+{
+        /* Tell the kernel we're in VESA graphics mode */
+        boot_params.screen_info.orig_video_isVGA = 0x23;
+
+        /* Mode parameters */
+        boot_params.screen_info.vesa_attributes = vminfo.mode_attr;
+        boot_params.screen_info.lfb_linelength = vminfo.logical_scan;
+        boot_params.screen_info.lfb_width = vminfo.h_res;
+        boot_params.screen_info.lfb_height = vminfo.v_res;
+        boot_params.screen_info.lfb_depth = vminfo.bpp;
+        boot_params.screen_info.pages = vminfo.image_planes;
+        boot_params.screen_info.lfb_base = vminfo.lfb_ptr;
+        memcpy(&boot_params.screen_info.red_size,
+               &vminfo.rmask, 8);
+
+        /* General parameters */
+        boot_params.screen_info.lfb_size = vginfo.total_memory;
+
+        if (vminfo.bpp <= 8)
+                vesa_dac_set_8bits();
+
+        vesa_store_pm_info();
+}
+
+/*
+ * Save EDID information for the kernel; this is invoked, separately,
+ * after mode-setting.
+ */
+void vesa_store_edid(void)
+{
+#ifdef CONFIG_FIRMWARE_EDID
+        u16 ax, bx, cx, dx, di;
+
+        /* Apparently used as a nonsense token... */
+        memset(&boot_params.edid_info, 0x13, sizeof boot_params.edid_info);
+
+        if (vginfo.version < 0x0200)
+                return;         /* EDID requires VBE 2.0+ */
+
+        ax = 0x4f15;            /* VBE DDC */
+        bx = 0x0000;            /* Report DDC capabilities */
+        cx = 0;                 /* Controller 0 */
+        di = 0;                 /* ES:DI must be 0 by spec */
+
+        /* Note: The VBE DDC spec is different from the main VESA spec;
+           we genuinely have to assume all registers are destroyed here. */
+
+        asm("pushw %%es; movw %2,%%es; "INT10"; popw %%es"
+            : "+a" (ax), "+b" (bx)
+            :  "c" (cx), "D" (di)
+            : "esi");
+
+        if (ax != 0x004f)
+                return;         /* No EDID */
+
+        /* BH = time in seconds to transfer EDD information */
+        /* BL = DDC level supported */
+
+        ax = 0x4f15;            /* VBE DDC */
+        bx = 0x0001;            /* Read EDID */
+        cx = 0;                 /* Controller 0 */
+        dx = 0;                 /* EDID block number */
+        di =(size_t) &boot_params.edid_info; /* (ES:)Pointer to block */
+        asm(INT10
+            : "+a" (ax), "+b" (bx), "+d" (dx)
+            : "c" (cx), "D" (di)
+            : "esi");
+#endif /* CONFIG_FIRMWARE_EDID */
+}
+
+__videocard video_vesa =
+{
+        .card_name      = "VESA",
+        .probe          = vesa_probe,
+        .set_mode       = vesa_set_mode,
+        .xmode_first    = VIDEO_FIRST_VESA,
+        .xmode_n        = 0x200,
+};
diff --git a/arch/i386/boot/video-vga.c b/arch/i386/boot/video-vga.c
new file mode 100644
index 000000000000..700d09a9c9b3
--- /dev/null
+++ b/arch/i386/boot/video-vga.c
@@ -0,0 +1,260 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/video-vga.c
+ *
+ * Common all-VGA modes
+ */
+
+#include "boot.h"
+#include "video.h"
+
+static struct mode_info vga_modes[] = {
+        { VIDEO_80x25,  80, 25 },
+        { VIDEO_8POINT, 80, 50 },
+        { VIDEO_80x43,  80, 43 },
+        { VIDEO_80x28,  80, 28 },
+        { VIDEO_80x30,  80, 30 },
+        { VIDEO_80x34,  80, 34 },
+        { VIDEO_80x60,  80, 60 },
+};
+
+static struct mode_info ega_modes[] = {
+        { VIDEO_80x25,  80, 25 },
+        { VIDEO_8POINT, 80, 43 },
+};
+
+static struct mode_info cga_modes[] = {
+        { VIDEO_80x25,  80, 25 },
+};
+
+__videocard video_vga;
+
+/* Set basic 80x25 mode */
+static u8 vga_set_basic_mode(void)
+{
+        u16 ax;
+        u8 rows;
+        u8 mode;
+
+#ifdef CONFIG_VIDEO_400_HACK
+        if (adapter >= ADAPTER_VGA) {
+                asm(INT10
+                    : : "a" (0x1202), "b" (0x0030)
+                    : "ecx", "edx", "esi", "edi");
+        }
+#endif
+
+        ax = 0x0f00;
+        asm(INT10
+            : "+a" (ax)
+            : : "ebx", "ecx", "edx", "esi", "edi");
+
+        mode = (u8)ax;
+
+        set_fs(0);
+        rows = rdfs8(0x484);    /* rows minus one */
+
+#ifndef CONFIG_VIDEO_400_HACK
+        if ((ax == 0x5003 || ax == 0x5007) &&
+            (rows == 0 || rows == 24))
+                return mode;
+#endif
+
+        if (mode != 3 && mode != 7)
+                mode = 3;
+
+        /* Set the mode */
+        asm volatile(INT10
+                     : : "a" (mode)
+                     : "ebx", "ecx", "edx", "esi", "edi");
+        do_restore = 1;
+        return mode;
+}
+
+static void vga_set_8font(void)
+{
+        /* Set 8x8 font - 80x43 on EGA, 80x50 on VGA */
+
+        /* Set 8x8 font */
+        asm volatile(INT10 : : "a" (0x1112), "b" (0));
+
+        /* Use alternate print screen */
+        asm volatile(INT10 : : "a" (0x1200), "b" (0x20));
+
+        /* Turn off cursor emulation */
+        asm volatile(INT10 : : "a" (0x1201), "b" (0x34));
+
+        /* Cursor is scan lines 6-7 */
+        asm volatile(INT10 : : "a" (0x0100), "c" (0x0607));
+}
+
+static void vga_set_14font(void)
+{
+        /* Set 9x14 font - 80x28 on VGA */
+
+        /* Set 9x14 font */
+        asm volatile(INT10 : : "a" (0x1111), "b" (0));
+
+        /* Turn off cursor emulation */
+        asm volatile(INT10 : : "a" (0x1201), "b" (0x34));
+
+        /* Cursor is scan lines 11-12 */
+        asm volatile(INT10 : : "a" (0x0100), "c" (0x0b0c));
+}
+
+static void vga_set_80x43(void)
+{
+        /* Set 80x43 mode on VGA (not EGA) */
+
+        /* Set 350 scans */
+        asm volatile(INT10 : : "a" (0x1201), "b" (0x30));
+
+        /* Reset video mode */
+        asm volatile(INT10 : : "a" (0x0003));
+
+        vga_set_8font();
+}
+
+/* I/O address of the VGA CRTC */
+u16 vga_crtc(void)
+{
+        return (inb(0x3cc) & 1) ? 0x3d4 : 0x3b4;
+}
+
+static void vga_set_480_scanlines(int end)
+{
+        u16 crtc;
+        u8  csel;
+
+        crtc = vga_crtc();
+
+        out_idx(0x0c, crtc, 0x11); /* Vertical sync end, unlock CR0-7 */
+        out_idx(0x0b, crtc, 0x06); /* Vertical total */
+        out_idx(0x3e, crtc, 0x07); /* Vertical overflow */
+        out_idx(0xea, crtc, 0x10); /* Vertical sync start */
+        out_idx(end, crtc, 0x12); /* Vertical display end */
+        out_idx(0xe7, crtc, 0x15); /* Vertical blank start */
+        out_idx(0x04, crtc, 0x16); /* Vertical blank end */
+        csel = inb(0x3cc);
+        csel &= 0x0d;
+        csel |= 0xe2;
+        outb(csel, 0x3cc);
+}
+
+static void vga_set_80x30(void)
+{
+        vga_set_480_scanlines(0xdf);
+}
+
+static void vga_set_80x34(void)
+{
+        vga_set_14font();
+        vga_set_480_scanlines(0xdb);
+}
+
+static void vga_set_80x60(void)
+{
+        vga_set_8font();
+        vga_set_480_scanlines(0xdf);
+}
+
+static int vga_set_mode(struct mode_info *mode)
+{
+        /* Set the basic mode */
+        vga_set_basic_mode();
+
+        /* Override a possibly broken BIOS */
+        force_x = mode->x;
+        force_y = mode->y;
+
+        switch (mode->mode) {
+        case VIDEO_80x25:
+                break;
+        case VIDEO_8POINT:
+                vga_set_8font();
+                break;
+        case VIDEO_80x43:
+                vga_set_80x43();
+                break;
+        case VIDEO_80x28:
+                vga_set_14font();
+                break;
+        case VIDEO_80x30:
+                vga_set_80x30();
+                break;
+        case VIDEO_80x34:
+                vga_set_80x34();
+                break;
+        case VIDEO_80x60:
+                vga_set_80x60();
+                break;
+        }
+
+        return 0;
+}
+
+/*
+ * Note: this probe includes basic information required by all
+ * systems.  It should be executed first, by making sure
+ * video-vga.c is listed first in the Makefile.
+ */
+static int vga_probe(void)
+{
+        static const char *card_name[] = {
+                "CGA/MDA/HGC", "EGA", "VGA"
+        };
+        static struct mode_info *mode_lists[] = {
+                cga_modes,
+                ega_modes,
+                vga_modes,
+        };
+        static int mode_count[] = {
+                sizeof(cga_modes)/sizeof(struct mode_info),
+                sizeof(ega_modes)/sizeof(struct mode_info),
+                sizeof(vga_modes)/sizeof(struct mode_info),
+        };
+        u8 vga_flag;
+
+        asm(INT10
+            : "=b" (boot_params.screen_info.orig_video_ega_bx)
+            : "a" (0x1200), "b" (0x10) /* Check EGA/VGA */
+            : "ecx", "edx", "esi", "edi");
+
+        /* If we have MDA/CGA/HGC then BL will be unchanged at 0x10 */
+        if ((u8)boot_params.screen_info.orig_video_ega_bx != 0x10) {
+                /* EGA/VGA */
+                asm(INT10
+                    : "=a" (vga_flag)
+                    : "a" (0x1a00)
+                    : "ebx", "ecx", "edx", "esi", "edi");
+
+                if (vga_flag == 0x1a) {
+                        adapter = ADAPTER_VGA;
+                        boot_params.screen_info.orig_video_isVGA = 1;
+                } else {
+                        adapter = ADAPTER_EGA;
+                }
+        } else {
+                adapter = ADAPTER_CGA;
+        }
+
+        video_vga.modes = mode_lists[adapter];
+        video_vga.card_name = card_name[adapter];
+        return mode_count[adapter];
+}
+
+__videocard video_vga =
+{
+        .card_name      = "VGA",
+        .probe          = vga_probe,
+        .set_mode       = vga_set_mode,
+};
diff --git a/arch/i386/boot/video.S b/arch/i386/boot/video.S
deleted file mode 100644
index 8143c9516cb4..000000000000
--- a/arch/i386/boot/video.S
+++ /dev/null
@@ -1,2043 +0,0 @@
-/*      video.S
- *
- *      Display adapter & video mode setup, version 2.13 (14-May-99)
- *
- *      Copyright (C) 1995 -- 1998 Martin Mares <mj@ucw.cz>
- *      Based on the original setup.S code (C) Linus Torvalds and Mats Anderson
- *
- *      Rewritten to use GNU 'as' by Chris Noe <stiker@northlink.com> May 1999
- *
- *      For further information, look at Documentation/svga.txt.
- *
- */
-
-/* Enable autodetection of SVGA adapters and modes. */
-#undef CONFIG_VIDEO_SVGA
-
-/* Enable autodetection of VESA modes */
-#define CONFIG_VIDEO_VESA
-
-/* Enable compacting of mode table */
-#define CONFIG_VIDEO_COMPACT
-
-/* Retain screen contents when switching modes */
-#define CONFIG_VIDEO_RETAIN
-
-/* Enable local mode list */
-#undef CONFIG_VIDEO_LOCAL
-
-/* Force 400 scan lines for standard modes (hack to fix bad BIOS behaviour */
-#undef CONFIG_VIDEO_400_HACK
-
-/* Hack that lets you force specific BIOS mode ID and specific dimensions */
-#undef CONFIG_VIDEO_GFX_HACK
-#define VIDEO_GFX_BIOS_AX 0x4f02        /* 800x600 on ThinkPad */
-#define VIDEO_GFX_BIOS_BX 0x0102
-#define VIDEO_GFX_DUMMY_RESOLUTION 0x6425       /* 100x37 */
-
-/* This code uses an extended set of video mode numbers. These include:
- * Aliases for standard modes
- *      NORMAL_VGA (-1)
- *      EXTENDED_VGA (-2)
- *      ASK_VGA (-3)
- * Video modes numbered by menu position -- NOT RECOMMENDED because of lack
- * of compatibility when extending the table. These are between 0x00 and 0xff.
- */
-#define VIDEO_FIRST_MENU 0x0000
-
-/* Standard BIOS video modes (BIOS number + 0x0100) */
-#define VIDEO_FIRST_BIOS 0x0100
-
-/* VESA BIOS video modes (VESA number + 0x0200) */
-#define VIDEO_FIRST_VESA 0x0200
-
-/* Video7 special modes (BIOS number + 0x0900) */
-#define VIDEO_FIRST_V7 0x0900
-
-/* Special video modes */
-#define VIDEO_FIRST_SPECIAL 0x0f00
-#define VIDEO_80x25 0x0f00
-#define VIDEO_8POINT 0x0f01
-#define VIDEO_80x43 0x0f02
-#define VIDEO_80x28 0x0f03
-#define VIDEO_CURRENT_MODE 0x0f04
-#define VIDEO_80x30 0x0f05
-#define VIDEO_80x34 0x0f06
-#define VIDEO_80x60 0x0f07
-#define VIDEO_GFX_HACK 0x0f08
-#define VIDEO_LAST_SPECIAL 0x0f09
-
-/* Video modes given by resolution */
-#define VIDEO_FIRST_RESOLUTION 0x1000
-
-/* The "recalculate timings" flag */
-#define VIDEO_RECALC 0x8000
-
-/* Positions of various video parameters passed to the kernel */
-/* (see also include/linux/tty.h) */
-#define PARAM_CURSOR_POS        0x00
-#define PARAM_VIDEO_PAGE        0x04
-#define PARAM_VIDEO_MODE        0x06
-#define PARAM_VIDEO_COLS        0x07
-#define PARAM_VIDEO_EGA_BX      0x0a
-#define PARAM_VIDEO_LINES       0x0e
-#define PARAM_HAVE_VGA          0x0f
-#define PARAM_FONT_POINTS       0x10
-
-#define PARAM_LFB_WIDTH         0x12
-#define PARAM_LFB_HEIGHT        0x14
-#define PARAM_LFB_DEPTH         0x16
-#define PARAM_LFB_BASE          0x18
-#define PARAM_LFB_SIZE          0x1c
-#define PARAM_LFB_LINELENGTH    0x24
-#define PARAM_LFB_COLORS        0x26
-#define PARAM_VESAPM_SEG        0x2e
-#define PARAM_VESAPM_OFF        0x30
-#define PARAM_LFB_PAGES         0x32
-#define PARAM_VESA_ATTRIB       0x34
-#define PARAM_CAPABILITIES      0x36
-
-/* Define DO_STORE according to CONFIG_VIDEO_RETAIN */
-#ifdef CONFIG_VIDEO_RETAIN
-#define DO_STORE call store_screen
-#else
-#define DO_STORE
-#endif /* CONFIG_VIDEO_RETAIN */
-
-# This is the main entry point called by setup.S
-# %ds *must* be pointing to the bootsector
-video:  pushw   %ds             # We use different segments
-        pushw   %ds             # FS contains original DS
-        popw    %fs
-        pushw   %cs             # DS is equal to CS
-        popw    %ds
-        pushw   %cs             # ES is equal to CS
-        popw    %es
-        xorw    %ax, %ax
-        movw    %ax, %gs        # GS is zero
-        cld
-        call    basic_detect    # Basic adapter type testing (EGA/VGA/MDA/CGA)
-#ifdef CONFIG_VIDEO_SELECT
-        movw    %fs:(0x01fa), %ax               # User selected video mode
-        cmpw    $ASK_VGA, %ax                   # Bring up the menu
-        jz      vid2
-
-        call    mode_set                        # Set the mode
-        jc      vid1
-
-        leaw    badmdt, %si                     # Invalid mode ID
-        call    prtstr
-vid2:   call    mode_menu
-vid1:
-#ifdef CONFIG_VIDEO_RETAIN
-        call    restore_screen                  # Restore screen contents
-#endif /* CONFIG_VIDEO_RETAIN */
-        call    store_edid
-#endif /* CONFIG_VIDEO_SELECT */
-        call    mode_params                     # Store mode parameters
-        popw    %ds                             # Restore original DS
-        ret
-
-# Detect if we have CGA, MDA, EGA or VGA and pass it to the kernel.
-basic_detect:
-        movb    $0, %fs:(PARAM_HAVE_VGA)
-        movb    $0x12, %ah      # Check EGA/VGA
-        movb    $0x10, %bl
-        int     $0x10
-        movw    %bx, %fs:(PARAM_VIDEO_EGA_BX)   # Identifies EGA to the kernel
-        cmpb    $0x10, %bl                      # No, it's a CGA/MDA/HGA card.
-        je      basret
-
-        incb    adapter
-        movw    $0x1a00, %ax                    # Check EGA or VGA?
-        int     $0x10
-        cmpb    $0x1a, %al                      # 1a means VGA...
-        jne     basret                          # anything else is EGA.
-        
-        incb    %fs:(PARAM_HAVE_VGA)            # We've detected a VGA
-        incb    adapter
-basret: ret
-
-# Store the video mode parameters for later usage by the kernel.
-# This is done by asking the BIOS except for the rows/columns
-# parameters in the default 80x25 mode -- these are set directly,
-# because some very obscure BIOSes supply insane values.
-mode_params:
-#ifdef CONFIG_VIDEO_SELECT
-        cmpb    $0, graphic_mode
-        jnz     mopar_gr
-#endif
-        movb    $0x03, %ah                      # Read cursor position
-        xorb    %bh, %bh
-        int     $0x10
-        movw    %dx, %fs:(PARAM_CURSOR_POS)
-        movb    $0x0f, %ah                      # Read page/mode/width
-        int     $0x10
-        movw    %bx, %fs:(PARAM_VIDEO_PAGE)
-        movw    %ax, %fs:(PARAM_VIDEO_MODE)     # Video mode and screen width
-        cmpb    $0x7, %al                       # MDA/HGA => segment differs
-        jnz     mopar0
-
-        movw    $0xb000, video_segment
-mopar0: movw    %gs:(0x485), %ax                # Font size
-        movw    %ax, %fs:(PARAM_FONT_POINTS)    # (valid only on EGA/VGA)
-        movw    force_size, %ax                 # Forced size?
-        orw     %ax, %ax
-        jz      mopar1
-
-        movb    %ah, %fs:(PARAM_VIDEO_COLS)
-        movb    %al, %fs:(PARAM_VIDEO_LINES)
-        ret
-
-mopar1: movb    $25, %al
-        cmpb    $0, adapter                     # If we are on CGA/MDA/HGA, the
-        jz      mopar2                          # screen must have 25 lines.
-
-        movb    %gs:(0x484), %al                # On EGA/VGA, use the EGA+ BIOS
-        incb    %al                             # location of max lines.
-mopar2: movb    %al, %fs:(PARAM_VIDEO_LINES)
-        ret
-
-#ifdef CONFIG_VIDEO_SELECT
-# Fetching of VESA frame buffer parameters
-mopar_gr:
-        leaw    modelist+1024, %di
-        movb    $0x23, %fs:(PARAM_HAVE_VGA)
-        movw    16(%di), %ax
-        movw    %ax, %fs:(PARAM_LFB_LINELENGTH)
-        movw    18(%di), %ax
-        movw    %ax, %fs:(PARAM_LFB_WIDTH)
-        movw    20(%di), %ax
-        movw    %ax, %fs:(PARAM_LFB_HEIGHT)
-        movb    25(%di), %al
-        movb    $0, %ah
-        movw    %ax, %fs:(PARAM_LFB_DEPTH)
-        movb    29(%di), %al    
-        movb    $0, %ah
-        movw    %ax, %fs:(PARAM_LFB_PAGES)
-        movl    40(%di), %eax
-        movl    %eax, %fs:(PARAM_LFB_BASE)
-        movl    31(%di), %eax
-        movl    %eax, %fs:(PARAM_LFB_COLORS)
-        movl    35(%di), %eax
-        movl    %eax, %fs:(PARAM_LFB_COLORS+4)
-        movw    0(%di), %ax
-        movw    %ax, %fs:(PARAM_VESA_ATTRIB)
-
-# get video mem size
-        leaw    modelist+1024, %di
-        movw    $0x4f00, %ax
-        int     $0x10
-        xorl    %eax, %eax
-        movw    18(%di), %ax
-        movl    %eax, %fs:(PARAM_LFB_SIZE)
-
-# store mode capabilities
-        movl 10(%di), %eax
-        movl %eax, %fs:(PARAM_CAPABILITIES)
-
-# switching the DAC to 8-bit is for <= 8 bpp only
-        movw    %fs:(PARAM_LFB_DEPTH), %ax
-        cmpw    $8, %ax
-        jg      dac_done
-
-# get DAC switching capability
-        xorl    %eax, %eax
-        movb    10(%di), %al
-        testb   $1, %al
-        jz      dac_set
-
-# attempt to switch DAC to 8-bit
-        movw    $0x4f08, %ax
-        movw    $0x0800, %bx
-        int     $0x10
-        cmpw    $0x004f, %ax
-        jne     dac_set
-        movb    %bh, dac_size           # store actual DAC size
-
-dac_set:
-# set color size to DAC size
-        movb    dac_size, %al
-        movb    %al, %fs:(PARAM_LFB_COLORS+0)
-        movb    %al, %fs:(PARAM_LFB_COLORS+2)
-        movb    %al, %fs:(PARAM_LFB_COLORS+4)
-        movb    %al, %fs:(PARAM_LFB_COLORS+6)
-
-# set color offsets to 0
-        movb    $0, %fs:(PARAM_LFB_COLORS+1)
-        movb    $0, %fs:(PARAM_LFB_COLORS+3)
-        movb    $0, %fs:(PARAM_LFB_COLORS+5)
-        movb    $0, %fs:(PARAM_LFB_COLORS+7)
-
-dac_done:
-# get protected mode interface informations
-        movw    $0x4f0a, %ax
-        xorw    %bx, %bx
-        xorw    %di, %di
-        int     $0x10
-        cmp     $0x004f, %ax
-        jnz     no_pm
-
-        movw    %es, %fs:(PARAM_VESAPM_SEG)
-        movw    %di, %fs:(PARAM_VESAPM_OFF)
-no_pm:  ret
-
-# The video mode menu
-mode_menu:
-        leaw    keymsg, %si                     # "Return/Space/Timeout" message
-        call    prtstr
-        call    flush
-nokey:  call    getkt
-
-        cmpb    $0x0d, %al                      # ENTER ?
-        je      listm                           # yes - manual mode selection
-
-        cmpb    $0x20, %al                      # SPACE ?
-        je      defmd1                          # no - repeat
-
-        call    beep
-        jmp     nokey
-
-defmd1: ret                                     # No mode chosen? Default 80x25
-
-listm:  call    mode_table                      # List mode table
-listm0: leaw    name_bann, %si                  # Print adapter name
-        call    prtstr
-        movw    card_name, %si
-        orw     %si, %si
-        jnz     an2
-
-        movb    adapter, %al
-        leaw    old_name, %si
-        orb     %al, %al
-        jz      an1
-
-        leaw    ega_name, %si
-        decb    %al
-        jz      an1
-
-        leaw    vga_name, %si
-        jmp     an1
-
-an2:    call    prtstr
-        leaw    svga_name, %si
-an1:    call    prtstr
-        leaw    listhdr, %si                    # Table header
-        call    prtstr
-        movb    $0x30, %dl                      # DL holds mode number
-        leaw    modelist, %si
-lm1:    cmpw    $ASK_VGA, (%si)                 # End?
-        jz      lm2
-
-        movb    %dl, %al                        # Menu selection number
-        call    prtchr
-        call    prtsp2
-        lodsw
-        call    prthw                           # Mode ID
-        call    prtsp2
-        movb    0x1(%si), %al
-        call    prtdec                          # Rows
-        movb    $0x78, %al                      # the letter 'x'
-        call    prtchr
-        lodsw
-        call    prtdec                          # Columns
-        movb    $0x0d, %al                      # New line
-        call    prtchr
-        movb    $0x0a, %al
-        call    prtchr
-        incb    %dl                             # Next character
-        cmpb    $0x3a, %dl
-        jnz     lm1
-
-        movb    $0x61, %dl
-        jmp     lm1
-
-lm2:    leaw    prompt, %si                     # Mode prompt
-        call    prtstr
-        leaw    edit_buf, %di                   # Editor buffer
-lm3:    call    getkey
-        cmpb    $0x0d, %al                      # Enter?
-        jz      lment
-
-        cmpb    $0x08, %al                      # Backspace?
-        jz      lmbs
-
-        cmpb    $0x20, %al                      # Printable?
-        jc      lm3
-
-        cmpw    $edit_buf+4, %di                # Enough space?
-        jz      lm3
-
-        stosb
-        call    prtchr
-        jmp     lm3
-
-lmbs:   cmpw    $edit_buf, %di                  # Backspace
-        jz      lm3
-
-        decw    %di
-        movb    $0x08, %al
-        call    prtchr
-        call    prtspc
-        movb    $0x08, %al
-        call    prtchr
-        jmp     lm3
-        
-lment:  movb    $0, (%di)
-        leaw    crlft, %si
-        call    prtstr
-        leaw    edit_buf, %si
-        cmpb    $0, (%si)                       # Empty string = default mode
-        jz      lmdef
-
-        cmpb    $0, 1(%si)                      # One character = menu selection
-        jz      mnusel
-
-        cmpw    $0x6373, (%si)                  # "scan" => mode scanning
-        jnz     lmhx
-
-        cmpw    $0x6e61, 2(%si)
-        jz      lmscan
-
-lmhx:   xorw    %bx, %bx                        # Else => mode ID in hex
-lmhex:  lodsb
-        orb     %al, %al
-        jz      lmuse1
-
-        subb    $0x30, %al
-        jc      lmbad
-
-        cmpb    $10, %al
-        jc      lmhx1
-
-        subb    $7, %al
-        andb    $0xdf, %al
-        cmpb    $10, %al
-        jc      lmbad
-
-        cmpb    $16, %al
-        jnc     lmbad
-
-lmhx1:  shlw    $4, %bx
-        orb     %al, %bl
-        jmp     lmhex
-
-lmuse1: movw    %bx, %ax
-        jmp     lmuse
-
-mnusel: lodsb                                   # Menu selection
-        xorb    %ah, %ah
-        subb    $0x30, %al
-        jc      lmbad
-
-        cmpb    $10, %al
-        jc      lmuse
-        
-        cmpb    $0x61-0x30, %al
-        jc      lmbad
-        
-        subb    $0x61-0x30-10, %al
-        cmpb    $36, %al
-        jnc     lmbad
-
-lmuse:  call    mode_set
-        jc      lmdef
-
-lmbad:  leaw    unknt, %si
-        call    prtstr
-        jmp     lm2
-lmscan: cmpb    $0, adapter                     # Scanning only on EGA/VGA
-        jz      lmbad
-
-        movw    $0, mt_end                      # Scanning of modes is
-        movb    $1, scanning                    # done as new autodetection.
-        call    mode_table
-        jmp     listm0
-lmdef:  ret
-
-# Additional parts of mode_set... (relative jumps, you know)
-setv7:                                          # Video7 extended modes
-        DO_STORE
-        subb    $VIDEO_FIRST_V7>>8, %bh
-        movw    $0x6f05, %ax
-        int     $0x10
-        stc
-        ret
-
-_setrec:        jmp     setrec                  # Ugly...
-_set_80x25:     jmp     set_80x25
-
-# Aliases for backward compatibility.
-setalias:
-        movw    $VIDEO_80x25, %ax
-        incw    %bx
-        jz      mode_set
-
-        movb    $VIDEO_8POINT-VIDEO_FIRST_SPECIAL, %al
-        incw    %bx
-        jnz     setbad                          # Fall-through!
-
-# Setting of user mode (AX=mode ID) => CF=success
-mode_set:
-        movw    %ax, %fs:(0x01fa)               # Store mode for use in acpi_wakeup.S
-        movw    %ax, %bx
-        cmpb    $0xff, %ah
-        jz      setalias
-
-        testb   $VIDEO_RECALC>>8, %ah
-        jnz     _setrec
-
-        cmpb    $VIDEO_FIRST_RESOLUTION>>8, %ah
-        jnc     setres
-        
-        cmpb    $VIDEO_FIRST_SPECIAL>>8, %ah
-        jz      setspc
-        
-        cmpb    $VIDEO_FIRST_V7>>8, %ah
-        jz      setv7
-        
-        cmpb    $VIDEO_FIRST_VESA>>8, %ah
-        jnc     check_vesa
-        
-        orb     %ah, %ah
-        jz      setmenu
-        
-        decb    %ah
-        jz      setbios
-
-setbad: clc
-        movb    $0, do_restore                  # The screen needn't be restored
-        ret
-
-setvesa:
-        DO_STORE
-        subb    $VIDEO_FIRST_VESA>>8, %bh
-        movw    $0x4f02, %ax                    # VESA BIOS mode set call
-        int     $0x10
-        cmpw    $0x004f, %ax                    # AL=4f if implemented
-        jnz     setbad                          # AH=0 if OK
-
-        stc
-        ret
-
-setbios:
-        DO_STORE
-        int     $0x10                           # Standard BIOS mode set call
-        pushw   %bx
-        movb    $0x0f, %ah                      # Check if really set
-        int     $0x10
-        popw    %bx
-        cmpb    %bl, %al
-        jnz     setbad
-        
-        stc
-        ret
-
-setspc: xorb    %bh, %bh                        # Set special mode
-        cmpb    $VIDEO_LAST_SPECIAL-VIDEO_FIRST_SPECIAL, %bl
-        jnc     setbad
-        
-        addw    %bx, %bx
-        jmp     *spec_inits(%bx)
-
-setmenu:
-        orb     %al, %al                        # 80x25 is an exception
-        jz      _set_80x25
-        
-        pushw   %bx                             # Set mode chosen from menu
-        call    mode_table                      # Build the mode table
-        popw    %ax
-        shlw    $2, %ax
-        addw    %ax, %si
-        cmpw    %di, %si
-        jnc     setbad
-        
-        movw    (%si), %ax                      # Fetch mode ID
-_m_s:   jmp     mode_set
-
-setres: pushw   %bx                             # Set mode chosen by resolution
-        call    mode_table
-        popw    %bx
-        xchgb   %bl, %bh
-setr1:  lodsw
-        cmpw    $ASK_VGA, %ax                   # End of the list?
-        jz      setbad
-        
-        lodsw
-        cmpw    %bx, %ax
-        jnz     setr1
-        
-        movw    -4(%si), %ax                    # Fetch mode ID
-        jmp     _m_s
-
-check_vesa:
-#ifdef CONFIG_FIRMWARE_EDID
-        leaw    modelist+1024, %di
-        movw    $0x4f00, %ax
-        int     $0x10
-        cmpw    $0x004f, %ax
-        jnz     setbad
-
-        movw    4(%di), %ax
-        movw    %ax, vbe_version
-#endif
-        leaw    modelist+1024, %di
-        subb    $VIDEO_FIRST_VESA>>8, %bh
-        movw    %bx, %cx                        # Get mode information structure
-        movw    $0x4f01, %ax
-        int     $0x10
-        addb    $VIDEO_FIRST_VESA>>8, %bh
-        cmpw    $0x004f, %ax
-        jnz     setbad
-
-        movb    (%di), %al                      # Check capabilities.
-        andb    $0x19, %al
-        cmpb    $0x09, %al
-        jz      setvesa                         # This is a text mode
-
-        movb    (%di), %al                      # Check capabilities.
-        andb    $0x99, %al
-        cmpb    $0x99, %al
-        jnz     _setbad                         # Doh! No linear frame buffer.
-
-        subb    $VIDEO_FIRST_VESA>>8, %bh
-        orw     $0x4000, %bx                    # Use linear frame buffer
-        movw    $0x4f02, %ax                    # VESA BIOS mode set call
-        int     $0x10
-        cmpw    $0x004f, %ax                    # AL=4f if implemented
-        jnz     _setbad                         # AH=0 if OK
-
-        movb    $1, graphic_mode                # flag graphic mode
-        movb    $0, do_restore                  # no screen restore
-        stc
-        ret
-
-_setbad:        jmp     setbad                  # Ugly...
-
-# Recalculate vertical display end registers -- this fixes various
-# inconsistencies of extended modes on many adapters. Called when
-# the VIDEO_RECALC flag is set in the mode ID.
-
-setrec: subb    $VIDEO_RECALC>>8, %ah           # Set the base mode
-        call    mode_set
-        jnc     rct3
-
-        movw    %gs:(0x485), %ax                # Font size in pixels
-        movb    %gs:(0x484), %bl                # Number of rows
-        incb    %bl
-        mulb    %bl                             # Number of visible
-        decw    %ax                             # scan lines - 1
-        movw    $0x3d4, %dx
-        movw    %ax, %bx
-        movb    $0x12, %al                      # Lower 8 bits
-        movb    %bl, %ah
-        outw    %ax, %dx
-        movb    $0x07, %al              # Bits 8 and 9 in the overflow register
-        call    inidx
-        xchgb   %al, %ah
-        andb    $0xbd, %ah
-        shrb    %bh
-        jnc     rct1
-        orb     $0x02, %ah
-rct1:   shrb    %bh
-        jnc     rct2
-        orb     $0x40, %ah
-rct2:   movb    $0x07, %al
-        outw    %ax, %dx
-        stc
-rct3:   ret
-
-# Table of routines for setting of the special modes.
-spec_inits:
-        .word   set_80x25
-        .word   set_8pixel
-        .word   set_80x43
-        .word   set_80x28
-        .word   set_current
-        .word   set_80x30
-        .word   set_80x34
-        .word   set_80x60
-        .word   set_gfx
-
-# Set the 80x25 mode. If already set, do nothing.
-set_80x25:
-        movw    $0x5019, force_size             # Override possibly broken BIOS
-use_80x25:
-#ifdef CONFIG_VIDEO_400_HACK
-        movw    $0x1202, %ax                    # Force 400 scan lines
-        movb    $0x30, %bl
-        int     $0x10
-#else
-        movb    $0x0f, %ah                      # Get current mode ID
-        int     $0x10
-        cmpw    $0x5007, %ax    # Mode 7 (80x25 mono) is the only one available
-        jz      st80            # on CGA/MDA/HGA and is also available on EGAM
-
-        cmpw    $0x5003, %ax    # Unknown mode, force 80x25 color
-        jnz     force3
-
-st80:   cmpb    $0, adapter     # CGA/MDA/HGA => mode 3/7 is always 80x25
-        jz      set80
-
-        movb    %gs:(0x0484), %al       # This is EGA+ -- beware of 80x50 etc.
-        orb     %al, %al                # Some buggy BIOS'es set 0 rows
-        jz      set80
-        
-        cmpb    $24, %al                # It's hopefully correct
-        jz      set80
-#endif /* CONFIG_VIDEO_400_HACK */
-force3: DO_STORE
-        movw    $0x0003, %ax                    # Forced set
-        int     $0x10
-set80:  stc
-        ret
-
-# Set the 80x50/80x43 8-pixel mode. Simple BIOS calls.
-set_8pixel:
-        DO_STORE
-        call    use_80x25                       # The base is 80x25
-set_8pt:
-        movw    $0x1112, %ax                    # Use 8x8 font
-        xorb    %bl, %bl
-        int     $0x10
-        movw    $0x1200, %ax                    # Use alternate print screen
-        movb    $0x20, %bl
-        int     $0x10
-        movw    $0x1201, %ax                    # Turn off cursor emulation
-        movb    $0x34, %bl
-        int     $0x10
-        movb    $0x01, %ah                      # Define cursor scan lines 6-7
-        movw    $0x0607, %cx
-        int     $0x10
-set_current:
-        stc
-        ret
-
-# Set the 80x28 mode. This mode works on all VGA's, because it's a standard
-# 80x25 mode with 14-point fonts instead of 16-point.
-set_80x28:
-        DO_STORE
-        call    use_80x25                       # The base is 80x25
-set14:  movw    $0x1111, %ax                    # Use 9x14 font
-        xorb    %bl, %bl
-        int     $0x10
-        movb    $0x01, %ah                      # Define cursor scan lines 11-12
-        movw    $0x0b0c, %cx
-        int     $0x10
-        stc
-        ret
-
-# Set the 80x43 mode. This mode is works on all VGA's.
-# It's a 350-scanline mode with 8-pixel font.
-set_80x43:
-        DO_STORE
-        movw    $0x1201, %ax                    # Set 350 scans
-        movb    $0x30, %bl
-        int     $0x10
-        movw    $0x0003, %ax                    # Reset video mode
-        int     $0x10
-        jmp     set_8pt                         # Use 8-pixel font
-
-# Set the 80x30 mode (all VGA's). 480 scanlines, 16-pixel font.
-set_80x30:
-        call    use_80x25                       # Start with real 80x25
-        DO_STORE
-        movw    $0x3cc, %dx                     # Get CRTC port
-        inb     %dx, %al
-        movb    $0xd4, %dl
-        rorb    %al                             # Mono or color?
-        jc      set48a
-
-        movb    $0xb4, %dl
-set48a: movw    $0x0c11, %ax            # Vertical sync end (also unlocks CR0-7)
-        call    outidx
-        movw    $0x0b06, %ax                    # Vertical total
-        call    outidx
-        movw    $0x3e07, %ax                    # (Vertical) overflow
-        call    outidx
-        movw    $0xea10, %ax                    # Vertical sync start
-        call    outidx
-        movw    $0xdf12, %ax                    # Vertical display end
-        call    outidx
-        movw    $0xe715, %ax                    # Vertical blank start
-        call    outidx
-        movw    $0x0416, %ax                    # Vertical blank end
-        call    outidx
-        pushw   %dx
-        movb    $0xcc, %dl                      # Misc output register (read)
-        inb     %dx, %al
-        movb    $0xc2, %dl                      # (write)
-        andb    $0x0d, %al      # Preserve clock select bits and color bit
-        orb     $0xe2, %al                      # Set correct sync polarity
-        outb    %al, %dx
-        popw    %dx
-        movw    $0x501e, force_size
-        stc                                     # That's all.
-        ret
-
-# Set the 80x34 mode (all VGA's). 480 scans, 14-pixel font.
-set_80x34:
-        call    set_80x30                       # Set 480 scans
-        call    set14                           # And 14-pt font
-        movw    $0xdb12, %ax                    # VGA vertical display end
-        movw    $0x5022, force_size
-setvde: call    outidx
-        stc
-        ret
-
-# Set the 80x60 mode (all VGA's). 480 scans, 8-pixel font.
-set_80x60:
-        call    set_80x30                       # Set 480 scans
-        call    set_8pt                         # And 8-pt font
-        movw    $0xdf12, %ax                    # VGA vertical display end
-        movw    $0x503c, force_size
-        jmp     setvde
-
-# Special hack for ThinkPad graphics
-set_gfx:
-#ifdef CONFIG_VIDEO_GFX_HACK
-        movw    $VIDEO_GFX_BIOS_AX, %ax
-        movw    $VIDEO_GFX_BIOS_BX, %bx
-        int     $0x10
-        movw    $VIDEO_GFX_DUMMY_RESOLUTION, force_size
-        stc
-#endif
-        ret
-
-#ifdef CONFIG_VIDEO_RETAIN
-
-# Store screen contents to temporary buffer.
-store_screen:
-        cmpb    $0, do_restore                  # Already stored?
-        jnz     stsr
-
-        testb   $CAN_USE_HEAP, loadflags        # Have we space for storing?
-        jz      stsr
-        
-        pushw   %ax
-        pushw   %bx
-        pushw   force_size                      # Don't force specific size
-        movw    $0, force_size
-        call    mode_params                     # Obtain params of current mode
-        popw    force_size
-        movb    %fs:(PARAM_VIDEO_LINES), %ah
-        movb    %fs:(PARAM_VIDEO_COLS), %al
-        movw    %ax, %bx                        # BX=dimensions
-        mulb    %ah
-        movw    %ax, %cx                        # CX=number of characters
-        addw    %ax, %ax                        # Calculate image size
-        addw    $modelist+1024+4, %ax
-        cmpw    heap_end_ptr, %ax
-        jnc     sts1                            # Unfortunately, out of memory
-
-        movw    %fs:(PARAM_CURSOR_POS), %ax     # Store mode params
-        leaw    modelist+1024, %di
-        stosw
-        movw    %bx, %ax
-        stosw
-        pushw   %ds                             # Store the screen
-        movw    video_segment, %ds
-        xorw    %si, %si
-        rep
-        movsw
-        popw    %ds
-        incb    do_restore                      # Screen will be restored later
-sts1:   popw    %bx
-        popw    %ax
-stsr:   ret
-
-# Restore screen contents from temporary buffer.
-restore_screen:
-        cmpb    $0, do_restore                  # Has the screen been stored?
-        jz      res1
-
-        call    mode_params                     # Get parameters of current mode
-        movb    %fs:(PARAM_VIDEO_LINES), %cl
-        movb    %fs:(PARAM_VIDEO_COLS), %ch
-        leaw    modelist+1024, %si              # Screen buffer
-        lodsw                                   # Set cursor position
-        movw    %ax, %dx
-        cmpb    %cl, %dh
-        jc      res2
-        
-        movb    %cl, %dh
-        decb    %dh
-res2:   cmpb    %ch, %dl
-        jc      res3
-        
-        movb    %ch, %dl
-        decb    %dl
-res3:   movb    $0x02, %ah
-        movb    $0x00, %bh
-        int     $0x10
-        lodsw                                   # Display size
-        movb    %ah, %dl                        # DL=number of lines
-        movb    $0, %ah                         # BX=phys. length of orig. line
-        movw    %ax, %bx
-        cmpb    %cl, %dl                        # Too many?
-        jc      res4
-
-        pushw   %ax
-        movb    %dl, %al
-        subb    %cl, %al
-        mulb    %bl
-        addw    %ax, %si
-        addw    %ax, %si
-        popw    %ax
-        movb    %cl, %dl
-res4:   cmpb    %ch, %al                        # Too wide?
-        jc      res5
-        
-        movb    %ch, %al                        # AX=width of src. line
-res5:   movb    $0, %cl
-        xchgb   %ch, %cl
-        movw    %cx, %bp                        # BP=width of dest. line
-        pushw   %es
-        movw    video_segment, %es
-        xorw    %di, %di                        # Move the data
-        addw    %bx, %bx                        # Convert BX and BP to _bytes_
-        addw    %bp, %bp
-res6:   pushw   %si
-        pushw   %di
-        movw    %ax, %cx
-        rep
-        movsw
-        popw    %di
-        popw    %si
-        addw    %bp, %di
-        addw    %bx, %si
-        decb    %dl
-        jnz     res6
-        
-        popw    %es                             # Done
-res1:   ret
-#endif /* CONFIG_VIDEO_RETAIN */
-
-# Write to indexed VGA register (AL=index, AH=data, DX=index reg. port)
-outidx: outb    %al, %dx
-        pushw   %ax
-        movb    %ah, %al
-        incw    %dx
-        outb    %al, %dx
-        decw    %dx
-        popw    %ax
-        ret
-
-# Build the table of video modes (stored after the setup.S code at the
-# `modelist' label. Each video mode record looks like:
-#       .word   MODE-ID         (our special mode ID (see above))
-#       .byte   rows            (number of rows)
-#       .byte   columns         (number of columns)
-# Returns address of the end of the table in DI, the end is marked
-# with a ASK_VGA ID.
-mode_table:
-        movw    mt_end, %di                     # Already filled?
-        orw     %di, %di
-        jnz     mtab1x
-        
-        leaw    modelist, %di                   # Store standard modes:
-        movl    $VIDEO_80x25 + 0x50190000, %eax # The 80x25 mode (ALL)
-        stosl
-        movb    adapter, %al                    # CGA/MDA/HGA -- no more modes
-        orb     %al, %al
-        jz      mtabe
-        
-        decb    %al
-        jnz     mtabv
-        
-        movl    $VIDEO_8POINT + 0x502b0000, %eax        # The 80x43 EGA mode
-        stosl
-        jmp     mtabe
-
-mtab1x: jmp     mtab1
-
-mtabv:  leaw    vga_modes, %si                  # All modes for std VGA
-        movw    $vga_modes_end-vga_modes, %cx
-        rep     # I'm unable to use movsw as I don't know how to store a half
-        movsb   # of the expression above to cx without using explicit shr.
-
-        cmpb    $0, scanning                    # Mode scan requested?
-        jz      mscan1
-        
-        call    mode_scan
-mscan1:
-
-#ifdef CONFIG_VIDEO_LOCAL
-        call    local_modes
-#endif /* CONFIG_VIDEO_LOCAL */
-
-#ifdef CONFIG_VIDEO_VESA
-        call    vesa_modes                      # Detect VESA VGA modes
-#endif /* CONFIG_VIDEO_VESA */
-
-#ifdef CONFIG_VIDEO_SVGA
-        cmpb    $0, scanning                    # Bypass when scanning
-        jnz     mscan2
-        
-        call    svga_modes                      # Detect SVGA cards & modes
-mscan2:
-#endif /* CONFIG_VIDEO_SVGA */
-
-mtabe:
-
-#ifdef CONFIG_VIDEO_COMPACT
-        leaw    modelist, %si
-        movw    %di, %dx
-        movw    %si, %di
-cmt1:   cmpw    %dx, %si                        # Scan all modes
-        jz      cmt2
-
-        leaw    modelist, %bx                   # Find in previous entries
-        movw    2(%si), %cx
-cmt3:   cmpw    %bx, %si
-        jz      cmt4
-
-        cmpw    2(%bx), %cx                     # Found => don't copy this entry
-        jz      cmt5
-
-        addw    $4, %bx
-        jmp     cmt3
-
-cmt4:   movsl                                   # Copy entry
-        jmp     cmt1
-
-cmt5:   addw    $4, %si                         # Skip entry
-        jmp     cmt1
-
-cmt2:
-#endif  /* CONFIG_VIDEO_COMPACT */
-
-        movw    $ASK_VGA, (%di)                 # End marker
-        movw    %di, mt_end
-mtab1:  leaw    modelist, %si                   # SI=mode list, DI=list end
-ret0:   ret
-
-# Modes usable on all standard VGAs
-vga_modes:
-        .word   VIDEO_8POINT
-        .word   0x5032                          # 80x50
-        .word   VIDEO_80x43
-        .word   0x502b                          # 80x43
-        .word   VIDEO_80x28
-        .word   0x501c                          # 80x28
-        .word   VIDEO_80x30
-        .word   0x501e                          # 80x30
-        .word   VIDEO_80x34
-        .word   0x5022                          # 80x34
-        .word   VIDEO_80x60
-        .word   0x503c                          # 80x60
-#ifdef CONFIG_VIDEO_GFX_HACK
-        .word   VIDEO_GFX_HACK
-        .word   VIDEO_GFX_DUMMY_RESOLUTION
-#endif
-
-vga_modes_end:
-# Detect VESA modes.
-
-#ifdef CONFIG_VIDEO_VESA
-vesa_modes:
-        cmpb    $2, adapter                     # VGA only
-        jnz     ret0
-
-        movw    %di, %bp                        # BP=original mode table end
-        addw    $0x200, %di                     # Buffer space
-        movw    $0x4f00, %ax                    # VESA Get card info call
-        int     $0x10
-        movw    %bp, %di
-        cmpw    $0x004f, %ax                    # Successful?
-        jnz     ret0
-        
-        cmpw    $0x4556, 0x200(%di)
-        jnz     ret0
-        
-        cmpw    $0x4153, 0x202(%di)
-        jnz     ret0
-        
-        movw    $vesa_name, card_name           # Set name to "VESA VGA"
-        pushw   %gs
-        lgsw    0x20e(%di), %si                 # GS:SI=mode list
-        movw    $128, %cx                       # Iteration limit
-vesa1:
-# gas version 2.9.1, using BFD version 2.9.1.0.23 buggers the next inst.
-# XXX:  lodsw   %gs:(%si), %ax                  # Get next mode in the list
-        gs; lodsw
-        cmpw    $0xffff, %ax                    # End of the table?
-        jz      vesar
-        
-        cmpw    $0x0080, %ax                    # Check validity of mode ID
-        jc      vesa2
-        
-        orb     %ah, %ah                # Valid IDs: 0x0000-0x007f/0x0100-0x07ff
-        jz      vesan                   # Certain BIOSes report 0x80-0xff!
-
-        cmpw    $0x0800, %ax
-        jnc     vesae
-
-vesa2:  pushw   %cx
-        movw    %ax, %cx                        # Get mode information structure
-        movw    $0x4f01, %ax
-        int     $0x10
-        movw    %cx, %bx                        # BX=mode number
-        addb    $VIDEO_FIRST_VESA>>8, %bh
-        popw    %cx
-        cmpw    $0x004f, %ax
-        jnz     vesan                   # Don't report errors (buggy BIOSES)
-
-        movb    (%di), %al                      # Check capabilities. We require
-        andb    $0x19, %al                      # a color text mode.
-        cmpb    $0x09, %al
-        jnz     vesan
-        
-        cmpw    $0xb800, 8(%di)         # Standard video memory address required
-        jnz     vesan
-
-        testb   $2, (%di)                       # Mode characteristics supplied?
-        movw    %bx, (%di)                      # Store mode number
-        jz      vesa3
-        
-        xorw    %dx, %dx
-        movw    0x12(%di), %bx                  # Width
-        orb     %bh, %bh
-        jnz     vesan
-        
-        movb    %bl, 0x3(%di)
-        movw    0x14(%di), %ax                  # Height
-        orb     %ah, %ah
-        jnz     vesan
-        
-        movb    %al, 2(%di)
-        mulb    %bl
-        cmpw    $8193, %ax              # Small enough for Linux console driver?
-        jnc     vesan
-
-        jmp     vesaok
-
-vesa3:  subw    $0x8108, %bx    # This mode has no detailed info specified,
-        jc      vesan           # so it must be a standard VESA mode.
-
-        cmpw    $5, %bx
-        jnc     vesan
-
-        movw    vesa_text_mode_table(%bx), %ax
-        movw    %ax, 2(%di)
-vesaok: addw    $4, %di                         # The mode is valid. Store it.
-vesan:  loop    vesa1                   # Next mode. Limit exceeded => error
-vesae:  leaw    vesaer, %si
-        call    prtstr
-        movw    %bp, %di                        # Discard already found modes.
-vesar:  popw    %gs
-        ret
-
-# Dimensions of standard VESA text modes
-vesa_text_mode_table:
-        .byte   60, 80                          # 0108
-        .byte   25, 132                         # 0109
-        .byte   43, 132                         # 010A
-        .byte   50, 132                         # 010B
-        .byte   60, 132                         # 010C
-#endif  /* CONFIG_VIDEO_VESA */
-
-# Scan for video modes. A bit dirty, but should work.
-mode_scan:
-        movw    $0x0100, %cx                    # Start with mode 0
-scm1:   movb    $0, %ah                         # Test the mode
-        movb    %cl, %al
-        int     $0x10
-        movb    $0x0f, %ah
-        int     $0x10
-        cmpb    %cl, %al
-        jnz     scm2                            # Mode not set
-
-        movw    $0x3c0, %dx                     # Test if it's a text mode
-        movb    $0x10, %al                      # Mode bits
-        call    inidx
-        andb    $0x03, %al
-        jnz     scm2
-        
-        movb    $0xce, %dl                      # Another set of mode bits
-        movb    $0x06, %al
-        call    inidx
-        shrb    %al
-        jc      scm2
-        
-        movb    $0xd4, %dl                      # Cursor location
-        movb    $0x0f, %al
-        call    inidx
-        orb     %al, %al
-        jnz     scm2
-        
-        movw    %cx, %ax                        # Ok, store the mode
-        stosw
-        movb    %gs:(0x484), %al                # Number of rows
-        incb    %al
-        stosb
-        movw    %gs:(0x44a), %ax                # Number of columns
-        stosb
-scm2:   incb    %cl
-        jns     scm1
-        
-        movw    $0x0003, %ax                    # Return back to mode 3
-        int     $0x10
-        ret
-
-tstidx: outw    %ax, %dx                        # OUT DX,AX and inidx
-inidx:  outb    %al, %dx                        # Read from indexed VGA register
-        incw    %dx                     # AL=index, DX=index reg port -> AL=data
-        inb     %dx, %al
-        decw    %dx
-        ret
-
-# Try to detect type of SVGA card and supply (usually approximate) video
-# mode table for it.
-
-#ifdef CONFIG_VIDEO_SVGA
-svga_modes:
-        leaw    svga_table, %si                 # Test all known SVGA adapters
-dosvga: lodsw
-        movw    %ax, %bp                        # Default mode table
-        orw     %ax, %ax
-        jz      didsv1
-
-        lodsw                                   # Pointer to test routine
-        pushw   %si
-        pushw   %di
-        pushw   %es
-        movw    $0xc000, %bx
-        movw    %bx, %es
-        call    *%ax                            # Call test routine
-        popw    %es
-        popw    %di
-        popw    %si
-        orw     %bp, %bp
-        jz      dosvga
-        
-        movw    %bp, %si                        # Found, copy the modes
-        movb    svga_prefix, %ah
-cpsvga: lodsb
-        orb     %al, %al
-        jz      didsv
-        
-        stosw
-        movsw
-        jmp     cpsvga
-
-didsv:  movw    %si, card_name                  # Store pointer to card name
-didsv1: ret
-
-# Table of all known SVGA cards. For each card, we store a pointer to
-# a table of video modes supported by the card and a pointer to a routine
-# used for testing of presence of the card. The video mode table is always
-# followed by the name of the card or the chipset.
-svga_table:
-        .word   ati_md, ati_test
-        .word   oak_md, oak_test
-        .word   paradise_md, paradise_test
-        .word   realtek_md, realtek_test
-        .word   s3_md, s3_test
-        .word   chips_md, chips_test
-        .word   video7_md, video7_test
-        .word   cirrus5_md, cirrus5_test
-        .word   cirrus6_md, cirrus6_test
-        .word   cirrus1_md, cirrus1_test
-        .word   ahead_md, ahead_test
-        .word   everex_md, everex_test
-        .word   genoa_md, genoa_test
-        .word   trident_md, trident_test
-        .word   tseng_md, tseng_test
-        .word   0
-
-# Test routines and mode tables:
-
-# S3 - The test algorithm was taken from the SuperProbe package
-# for XFree86 1.2.1. Report bugs to Christoph.Niemann@linux.org
-s3_test:
-        movw    $0x0f35, %cx    # we store some constants in cl/ch
-        movw    $0x03d4, %dx
-        movb    $0x38, %al
-        call    inidx
-        movb    %al, %bh        # store current CRT-register 0x38
-        movw    $0x0038, %ax
-        call    outidx          # disable writing to special regs
-        movb    %cl, %al        # check whether we can write special reg 0x35
-        call    inidx
-        movb    %al, %bl        # save the current value of CRT reg 0x35
-        andb    $0xf0, %al      # clear bits 0-3
-        movb    %al, %ah
-        movb    %cl, %al        # and write it to CRT reg 0x35
-        call    outidx
-        call    inidx           # now read it back
-        andb    %ch, %al        # clear the upper 4 bits
-        jz      s3_2            # the first test failed. But we have a
-
-        movb    %bl, %ah        # second chance
-        movb    %cl, %al
-        call    outidx
-        jmp     s3_1            # do the other tests
-
-s3_2:   movw    %cx, %ax        # load ah with 0xf and al with 0x35
-        orb     %bl, %ah        # set the upper 4 bits of ah with the orig value
-        call    outidx          # write ...
-        call    inidx           # ... and reread 
-        andb    %cl, %al        # turn off the upper 4 bits
-        pushw   %ax
-        movb    %bl, %ah        # restore old value in register 0x35
-        movb    %cl, %al
-        call    outidx
-        popw    %ax
-        cmpb    %ch, %al        # setting lower 4 bits was successful => bad
-        je      no_s3           # writing is allowed => this is not an S3
-
-s3_1:   movw    $0x4838, %ax    # allow writing to special regs by putting
-        call    outidx          # magic number into CRT-register 0x38
-        movb    %cl, %al        # check whether we can write special reg 0x35
-        call    inidx
-        movb    %al, %bl
-        andb    $0xf0, %al
-        movb    %al, %ah
-        movb    %cl, %al
-        call    outidx
-        call    inidx
-        andb    %ch, %al
-        jnz     no_s3           # no, we can't write => no S3
-
-        movw    %cx, %ax
-        orb     %bl, %ah
-        call    outidx
-        call    inidx
-        andb    %ch, %al
-        pushw   %ax
-        movb    %bl, %ah        # restore old value in register 0x35
-        movb    %cl, %al
-        call    outidx
-        popw    %ax
-        cmpb    %ch, %al
-        jne     no_s31          # writing not possible => no S3
-        movb    $0x30, %al
-        call    inidx           # now get the S3 id ...
-        leaw    idS3, %di
-        movw    $0x10, %cx
-        repne
-        scasb
-        je      no_s31
-
-        movb    %bh, %ah
-        movb    $0x38, %al
-        jmp     s3rest
-
-no_s3:  movb    $0x35, %al      # restore CRT register 0x35
-        movb    %bl, %ah
-        call    outidx
-no_s31: xorw    %bp, %bp        # Detection failed
-s3rest: movb    %bh, %ah
-        movb    $0x38, %al      # restore old value of CRT register 0x38
-        jmp     outidx
-
-idS3:   .byte   0x81, 0x82, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95
-        .byte   0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa8, 0xb0
-
-s3_md:  .byte   0x54, 0x2b, 0x84
-        .byte   0x55, 0x19, 0x84
-        .byte   0
-        .ascii  "S3"
-        .byte   0
-
-# ATI cards.
-ati_test:
-        leaw    idati, %si
-        movw    $0x31, %di
-        movw    $0x09, %cx
-        repe
-        cmpsb
-        je      atiok
-
-        xorw    %bp, %bp
-atiok:  ret
-
-idati:  .ascii  "761295520"
-
-ati_md: .byte   0x23, 0x19, 0x84
-        .byte   0x33, 0x2c, 0x84
-        .byte   0x22, 0x1e, 0x64
-        .byte   0x21, 0x19, 0x64
-        .byte   0x58, 0x21, 0x50
-        .byte   0x5b, 0x1e, 0x50
-        .byte   0
-        .ascii  "ATI"
-        .byte   0
-
-# AHEAD
-ahead_test:
-        movw    $0x200f, %ax
-        movw    $0x3ce, %dx
-        outw    %ax, %dx
-        incw    %dx
-        inb     %dx, %al
-        cmpb    $0x20, %al
-        je      isahed
-
-        cmpb    $0x21, %al
-        je      isahed
-        
-        xorw    %bp, %bp
-isahed: ret
-
-ahead_md:
-        .byte   0x22, 0x2c, 0x84
-        .byte   0x23, 0x19, 0x84
-        .byte   0x24, 0x1c, 0x84
-        .byte   0x2f, 0x32, 0xa0
-        .byte   0x32, 0x22, 0x50
-        .byte   0x34, 0x42, 0x50
-        .byte   0
-        .ascii  "Ahead"
-        .byte   0
-
-# Chips & Tech.
-chips_test:
-        movw    $0x3c3, %dx
-        inb     %dx, %al
-        orb     $0x10, %al
-        outb    %al, %dx
-        movw    $0x104, %dx
-        inb     %dx, %al
-        movb    %al, %bl
-        movw    $0x3c3, %dx
-        inb     %dx, %al
-        andb    $0xef, %al
-        outb    %al, %dx
-        cmpb    $0xa5, %bl
-        je      cantok
-        
-        xorw    %bp, %bp
-cantok: ret
-
-chips_md:
-        .byte   0x60, 0x19, 0x84
-        .byte   0x61, 0x32, 0x84
-        .byte   0
-        .ascii  "Chips & Technologies"
-        .byte   0
-
-# Cirrus Logic 5X0
-cirrus1_test:
-        movw    $0x3d4, %dx
-        movb    $0x0c, %al
-        outb    %al, %dx
-        incw    %dx
-        inb     %dx, %al
-        movb    %al, %bl
-        xorb    %al, %al
-        outb    %al, %dx
-        decw    %dx
-        movb    $0x1f, %al
-        outb    %al, %dx
-        incw    %dx
-        inb     %dx, %al
-        movb    %al, %bh
-        xorb    %ah, %ah
-        shlb    $4, %al
-        movw    %ax, %cx
-        movb    %bh, %al
-        shrb    $4, %al
-        addw    %ax, %cx
-        shlw    $8, %cx
-        addw    $6, %cx
-        movw    %cx, %ax
-        movw    $0x3c4, %dx
-        outw    %ax, %dx
-        incw    %dx
-        inb     %dx, %al
-        andb    %al, %al
-        jnz     nocirr
-        
-        movb    %bh, %al
-        outb    %al, %dx
-        inb     %dx, %al
-        cmpb    $0x01, %al
-        je      iscirr
-
-nocirr: xorw    %bp, %bp
-iscirr: movw    $0x3d4, %dx
-        movb    %bl, %al
-        xorb    %ah, %ah
-        shlw    $8, %ax
-        addw    $0x0c, %ax
-        outw    %ax, %dx
-        ret
-
-cirrus1_md:
-        .byte   0x1f, 0x19, 0x84
-        .byte   0x20, 0x2c, 0x84
-        .byte   0x22, 0x1e, 0x84
-        .byte   0x31, 0x25, 0x64
-        .byte   0
-        .ascii  "Cirrus Logic 5X0"
-        .byte   0
-
-# Cirrus Logic 54XX
-cirrus5_test:
-        movw    $0x3c4, %dx
-        movb    $6, %al
-        call    inidx
-        movb    %al, %bl                        # BL=backup
-        movw    $6, %ax
-        call    tstidx
-        cmpb    $0x0f, %al
-        jne     c5fail
-        
-        movw    $0x1206, %ax
-        call    tstidx
-        cmpb    $0x12, %al
-        jne     c5fail
-        
-        movb    $0x1e, %al
-        call    inidx
-        movb    %al, %bh
-        movb    %bh, %ah
-        andb    $0xc0, %ah
-        movb    $0x1e, %al
-        call    tstidx
-        andb    $0x3f, %al
-        jne     c5xx
-        
-        movb    $0x1e, %al
-        movb    %bh, %ah
-        orb     $0x3f, %ah
-        call    tstidx
-        xorb    $0x3f, %al
-        andb    $0x3f, %al
-c5xx:   pushf
-        movb    $0x1e, %al
-        movb    %bh, %ah
-        outw    %ax, %dx
-        popf
-        je      c5done
-
-c5fail: xorw    %bp, %bp
-c5done: movb    $6, %al
-        movb    %bl, %ah
-        outw    %ax, %dx
-        ret
-
-cirrus5_md:
-        .byte   0x14, 0x19, 0x84
-        .byte   0x54, 0x2b, 0x84
-        .byte   0
-        .ascii  "Cirrus Logic 54XX"
-        .byte   0
-
-# Cirrus Logic 64XX -- no known extra modes, but must be identified, because
-# it's misidentified by the Ahead test.
-cirrus6_test:
-        movw    $0x3ce, %dx
-        movb    $0x0a, %al
-        call    inidx
-        movb    %al, %bl        # BL=backup
-        movw    $0xce0a, %ax
-        call    tstidx
-        orb     %al, %al
-        jne     c2fail
-        
-        movw    $0xec0a, %ax
-        call    tstidx
-        cmpb    $0x01, %al
-        jne     c2fail
-        
-        movb    $0xaa, %al
-        call    inidx           # 4X, 5X, 7X and 8X are valid 64XX chip ID's. 
-        shrb    $4, %al
-        subb    $4, %al
-        jz      c6done
-        
-        decb    %al
-        jz      c6done
-        
-        subb    $2, %al
-        jz      c6done
-        
-        decb    %al
-        jz      c6done
-        
-c2fail: xorw    %bp, %bp
-c6done: movb    $0x0a, %al
-        movb    %bl, %ah
-        outw    %ax, %dx
-        ret
-
-cirrus6_md:
-        .byte   0
-        .ascii  "Cirrus Logic 64XX"
-        .byte   0
-
-# Everex / Trident
-everex_test:
-        movw    $0x7000, %ax
-        xorw    %bx, %bx
-        int     $0x10
-        cmpb    $0x70, %al
-        jne     noevrx
-        
-        shrw    $4, %dx
-        cmpw    $0x678, %dx
-        je      evtrid
-        
-        cmpw    $0x236, %dx
-        jne     evrxok
-
-evtrid: leaw    trident_md, %bp
-evrxok: ret
-
-noevrx: xorw    %bp, %bp
-        ret
-
-everex_md:
-        .byte   0x03, 0x22, 0x50
-        .byte   0x04, 0x3c, 0x50
-        .byte   0x07, 0x2b, 0x64
-        .byte   0x08, 0x4b, 0x64
-        .byte   0x0a, 0x19, 0x84
-        .byte   0x0b, 0x2c, 0x84
-        .byte   0x16, 0x1e, 0x50
-        .byte   0x18, 0x1b, 0x64
-        .byte   0x21, 0x40, 0xa0
-        .byte   0x40, 0x1e, 0x84
-        .byte   0
-        .ascii  "Everex/Trident"
-        .byte   0
-
-# Genoa.
-genoa_test:
-        leaw    idgenoa, %si                    # Check Genoa 'clues'
-        xorw    %ax, %ax
-        movb    %es:(0x37), %al
-        movw    %ax, %di
-        movw    $0x04, %cx
-        decw    %si
-        decw    %di
-l1:     incw    %si
-        incw    %di
-        movb    (%si), %al
-        testb   %al, %al
-        jz      l2
-
-        cmpb    %es:(%di), %al
-l2:     loope   l1
-        orw     %cx, %cx
-        je      isgen
-        
-        xorw    %bp, %bp
-isgen:  ret
-
-idgenoa: .byte  0x77, 0x00, 0x99, 0x66
-
-genoa_md:
-        .byte   0x58, 0x20, 0x50
-        .byte   0x5a, 0x2a, 0x64
-        .byte   0x60, 0x19, 0x84
-        .byte   0x61, 0x1d, 0x84
-        .byte   0x62, 0x20, 0x84
-        .byte   0x63, 0x2c, 0x84
-        .byte   0x64, 0x3c, 0x84
-        .byte   0x6b, 0x4f, 0x64
-        .byte   0x72, 0x3c, 0x50
-        .byte   0x74, 0x42, 0x50
-        .byte   0x78, 0x4b, 0x64
-        .byte   0
-        .ascii  "Genoa"
-        .byte   0
-
-# OAK
-oak_test:
-        leaw    idoakvga, %si
-        movw    $0x08, %di
-        movw    $0x08, %cx
-        repe
-        cmpsb
-        je      isoak
-        
-        xorw    %bp, %bp
-isoak:  ret
-
-idoakvga: .ascii  "OAK VGA "
-
-oak_md: .byte   0x4e, 0x3c, 0x50
-        .byte   0x4f, 0x3c, 0x84
-        .byte   0x50, 0x19, 0x84
-        .byte   0x51, 0x2b, 0x84
-        .byte   0
-        .ascii  "OAK"
-        .byte   0
-
-# WD Paradise.
-paradise_test:
-        leaw    idparadise, %si
-        movw    $0x7d, %di
-        movw    $0x04, %cx
-        repe
-        cmpsb
-        je      ispara
-        
-        xorw    %bp, %bp
-ispara: ret
-
-idparadise:     .ascii  "VGA="
-
-paradise_md:
-        .byte   0x41, 0x22, 0x50
-        .byte   0x47, 0x1c, 0x84
-        .byte   0x55, 0x19, 0x84
-        .byte   0x54, 0x2c, 0x84
-        .byte   0
-        .ascii  "Paradise"
-        .byte   0
-
-# Trident.
-trident_test:
-        movw    $0x3c4, %dx
-        movb    $0x0e, %al
-        outb    %al, %dx
-        incw    %dx
-        inb     %dx, %al
-        xchgb   %al, %ah
-        xorb    %al, %al
-        outb    %al, %dx
-        inb     %dx, %al
-        xchgb   %ah, %al
-        movb    %al, %bl        # Strange thing ... in the book this wasn't
-        andb    $0x02, %bl      # necessary but it worked on my card which
-        jz      setb2           # is a trident. Without it the screen goes
-                                # blurred ...
-        andb    $0xfd, %al
-        jmp     clrb2           
-
-setb2:  orb     $0x02, %al      
-clrb2:  outb    %al, %dx
-        andb    $0x0f, %ah
-        cmpb    $0x02, %ah
-        je      istrid
-
-        xorw    %bp, %bp
-istrid: ret
-
-trident_md:
-        .byte   0x50, 0x1e, 0x50
-        .byte   0x51, 0x2b, 0x50
-        .byte   0x52, 0x3c, 0x50
-        .byte   0x57, 0x19, 0x84
-        .byte   0x58, 0x1e, 0x84
-        .byte   0x59, 0x2b, 0x84
-        .byte   0x5a, 0x3c, 0x84
-        .byte   0
-        .ascii  "Trident"
-        .byte   0
-
-# Tseng.
-tseng_test:
-        movw    $0x3cd, %dx
-        inb     %dx, %al        # Could things be this simple ! :-)
-        movb    %al, %bl
-        movb    $0x55, %al
-        outb    %al, %dx
-        inb     %dx, %al
-        movb    %al, %ah
-        movb    %bl, %al
-        outb    %al, %dx
-        cmpb    $0x55, %ah
-        je      istsen
-
-isnot:  xorw    %bp, %bp
-istsen: ret
-
-tseng_md:
-        .byte   0x26, 0x3c, 0x50
-        .byte   0x2a, 0x28, 0x64
-        .byte   0x23, 0x19, 0x84
-        .byte   0x24, 0x1c, 0x84
-        .byte   0x22, 0x2c, 0x84
-        .byte   0x21, 0x3c, 0x84
-        .byte   0
-        .ascii  "Tseng"
-        .byte   0
-
-# Video7.
-video7_test:
-        movw    $0x3cc, %dx
-        inb     %dx, %al
-        movw    $0x3b4, %dx
-        andb    $0x01, %al
-        jz      even7
-
-        movw    $0x3d4, %dx
-even7:  movb    $0x0c, %al
-        outb    %al, %dx
-        incw    %dx
-        inb     %dx, %al
-        movb    %al, %bl
-        movb    $0x55, %al
-        outb    %al, %dx
-        inb     %dx, %al
-        decw    %dx
-        movb    $0x1f, %al
-        outb    %al, %dx
-        incw    %dx
-        inb     %dx, %al
-        movb    %al, %bh
-        decw    %dx
-        movb    $0x0c, %al
-        outb    %al, %dx
-        incw    %dx
-        movb    %bl, %al
-        outb    %al, %dx
-        movb    $0x55, %al
-        xorb    $0xea, %al
-        cmpb    %bh, %al
-        jne     isnot
-        
-        movb    $VIDEO_FIRST_V7>>8, svga_prefix # Use special mode switching
-        ret
-
-video7_md:
-        .byte   0x40, 0x2b, 0x50
-        .byte   0x43, 0x3c, 0x50
-        .byte   0x44, 0x3c, 0x64
-        .byte   0x41, 0x19, 0x84
-        .byte   0x42, 0x2c, 0x84
-        .byte   0x45, 0x1c, 0x84
-        .byte   0
-        .ascii  "Video 7"
-        .byte   0
-
-# Realtek VGA
-realtek_test:
-        leaw    idrtvga, %si
-        movw    $0x45, %di
-        movw    $0x0b, %cx
-        repe
-        cmpsb
-        je      isrt
-        
-        xorw    %bp, %bp
-isrt:   ret
-
-idrtvga:        .ascii  "REALTEK VGA"
-
-realtek_md:
-        .byte   0x1a, 0x3c, 0x50
-        .byte   0x1b, 0x19, 0x84
-        .byte   0x1c, 0x1e, 0x84
-        .byte   0x1d, 0x2b, 0x84
-        .byte   0x1e, 0x3c, 0x84
-        .byte   0
-        .ascii  "REALTEK"
-        .byte   0
-
-#endif  /* CONFIG_VIDEO_SVGA */
-
-# User-defined local mode table (VGA only)
-#ifdef CONFIG_VIDEO_LOCAL
-local_modes:
-        leaw    local_mode_table, %si
-locm1:  lodsw
-        orw     %ax, %ax
-        jz      locm2
-        
-        stosw
-        movsw
-        jmp     locm1
-
-locm2:  ret
-
-# This is the table of local video modes which can be supplied manually
-# by the user. Each entry consists of mode ID (word) and dimensions
-# (byte for column count and another byte for row count). These modes
-# are placed before all SVGA and VESA modes and override them if table
-# compacting is enabled. The table must end with a zero word followed
-# by NUL-terminated video adapter name.
-local_mode_table:
-        .word   0x0100                          # Example: 40x25
-        .byte   25,40
-        .word   0
-        .ascii  "Local"
-        .byte   0
-#endif  /* CONFIG_VIDEO_LOCAL */
-
-# Read a key and return the ASCII code in al, scan code in ah
-getkey: xorb    %ah, %ah
-        int     $0x16
-        ret
-
-# Read a key with a timeout of 30 seconds.
-# The hardware clock is used to get the time.
-getkt:  call    gettime
-        addb    $30, %al                        # Wait 30 seconds
-        cmpb    $60, %al
-        jl      lminute
-
-        subb    $60, %al
-lminute:
-        movb    %al, %cl
-again:  movb    $0x01, %ah
-        int     $0x16
-        jnz     getkey                          # key pressed, so get it
-
-        call    gettime
-        cmpb    %cl, %al
-        jne     again
-
-        movb    $0x20, %al                      # timeout, return `space'
-        ret
-
-# Flush the keyboard buffer
-flush:  movb    $0x01, %ah
-        int     $0x16
-        jz      empty
-        
-        xorb    %ah, %ah
-        int     $0x16
-        jmp     flush
-
-empty:  ret
-
-# Print hexadecimal number.
-prthw:  pushw   %ax
-        movb    %ah, %al
-        call    prthb
-        popw    %ax
-prthb:  pushw   %ax
-        shrb    $4, %al
-        call    prthn
-        popw    %ax
-        andb    $0x0f, %al
-prthn:  cmpb    $0x0a, %al
-        jc      prth1
-
-        addb    $0x07, %al
-prth1:  addb    $0x30, %al
-        jmp     prtchr
-
-# Print decimal number in al
-prtdec: pushw   %ax
-        pushw   %cx
-        xorb    %ah, %ah
-        movb    $0x0a, %cl
-        idivb   %cl
-        cmpb    $0x09, %al
-        jbe     lt100
-
-        call    prtdec
-        jmp     skip10
-
-lt100:  addb    $0x30, %al
-        call    prtchr
-skip10: movb    %ah, %al
-        addb    $0x30, %al
-        call    prtchr  
-        popw    %cx
-        popw    %ax
-        ret
-
-store_edid:
-#ifdef CONFIG_FIRMWARE_EDID
-        pushw   %es                             # just save all registers
-        pushw   %ax
-        pushw   %bx
-        pushw   %cx
-        pushw   %dx
-        pushw   %di
-
-        pushw   %fs
-        popw    %es
-
-        movl    $0x13131313, %eax               # memset block with 0x13
-        movw    $32, %cx
-        movw    $0x140, %di
-        cld
-        rep
-        stosl
-
-        cmpw    $0x0200, vbe_version            # only do EDID on >= VBE2.0
-        jl      no_edid
-
-        pushw   %es                             # save ES
-        xorw    %di, %di                        # Report Capability
-        pushw   %di
-        popw    %es                             # ES:DI must be 0:0
-        movw    $0x4f15, %ax
-        xorw    %bx, %bx
-        xorw    %cx, %cx
-        int     $0x10
-        popw    %es                             # restore ES
-
-        cmpb    $0x00, %ah                      # call successful
-        jne     no_edid
-
-        cmpb    $0x4f, %al                      # function supported
-        jne     no_edid
-
-        movw    $0x4f15, %ax                    # do VBE/DDC
-        movw    $0x01, %bx
-        movw    $0x00, %cx
-        movw    $0x00, %dx
-        movw    $0x140, %di
-        int     $0x10
-
-no_edid:
-        popw    %di                             # restore all registers
-        popw    %dx
-        popw    %cx
-        popw    %bx
-        popw    %ax
-        popw    %es
-#endif
-        ret
-
-# VIDEO_SELECT-only variables
-mt_end:         .word   0       # End of video mode table if built
-edit_buf:       .space  6       # Line editor buffer
-card_name:      .word   0       # Pointer to adapter name
-scanning:       .byte   0       # Performing mode scan
-do_restore:     .byte   0       # Screen contents altered during mode change
-svga_prefix:    .byte   VIDEO_FIRST_BIOS>>8     # Default prefix for BIOS modes
-graphic_mode:   .byte   0       # Graphic mode with a linear frame buffer
-dac_size:       .byte   6       # DAC bit depth
-vbe_version:    .word   0       # VBE bios version
-
-# Status messages
-keymsg:         .ascii  "Press <RETURN> to see video modes available, "
-                .ascii  "<SPACE> to continue or wait 30 secs"
-                .byte   0x0d, 0x0a, 0
-
-listhdr:        .byte   0x0d, 0x0a
-                .ascii  "Mode:    COLSxROWS:"
-
-crlft:          .byte   0x0d, 0x0a, 0
-
-prompt:         .byte   0x0d, 0x0a
-                .asciz  "Enter mode number or `scan': "
-
-unknt:          .asciz  "Unknown mode ID. Try again."
-
-badmdt:         .ascii  "You passed an undefined mode number."
-                .byte   0x0d, 0x0a, 0
-
-vesaer:         .ascii  "Error: Scanning of VESA modes failed. Please "
-                .ascii  "report to <mj@ucw.cz>."
-                .byte   0x0d, 0x0a, 0
-
-old_name:       .asciz  "CGA/MDA/HGA"
-
-ega_name:       .asciz  "EGA"
-
-svga_name:      .ascii  " "
-
-vga_name:       .asciz  "VGA"
-
-vesa_name:      .asciz  "VESA"
-
-name_bann:      .asciz  "Video adapter: "
-#endif /* CONFIG_VIDEO_SELECT */
-
-# Other variables:
-adapter:        .byte   0       # Video adapter: 0=CGA/MDA/HGA,1=EGA,2=VGA
-video_segment:  .word   0xb800  # Video memory segment
-force_size:     .word   0       # Use this size instead of the one in BIOS vars
diff --git a/arch/i386/boot/video.c b/arch/i386/boot/video.c
new file mode 100644
index 000000000000..3bb3573cd6a1
--- /dev/null
+++ b/arch/i386/boot/video.c
@@ -0,0 +1,456 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/video.c
+ *
+ * Select video mode
+ */
+
+#include "boot.h"
+#include "video.h"
+#include "vesa.h"
+
+/*
+ * Mode list variables
+ */
+static struct card_info cards[];    /* List of cards to probe for */
+
+/*
+ * Common variables
+ */
+int adapter;                    /* 0=CGA/MDA/HGC, 1=EGA, 2=VGA+ */
+u16 video_segment;
+int force_x, force_y;   /* Don't query the BIOS for cols/rows */
+
+int do_restore = 0;     /* Screen contents changed during mode flip */
+int graphic_mode;       /* Graphic mode with linear frame buffer */
+
+static void store_cursor_position(void)
+{
+        u16 curpos;
+        u16 ax, bx;
+
+        ax = 0x0300;
+        bx = 0;
+        asm(INT10
+            : "=d" (curpos), "+a" (ax), "+b" (bx)
+            : : "ecx", "esi", "edi");
+
+        boot_params.screen_info.orig_x = curpos;
+        boot_params.screen_info.orig_y = curpos >> 8;
+}
+
+static void store_video_mode(void)
+{
+        u16 ax, page;
+
+        /* N.B.: the saving of the video page here is a bit silly,
+           since we pretty much assume page 0 everywhere. */
+        ax = 0x0f00;
+        asm(INT10
+            : "+a" (ax), "=b" (page)
+            : : "ecx", "edx", "esi", "edi");
+
+        /* Not all BIOSes are clean with respect to the top bit */
+        boot_params.screen_info.orig_video_mode = ax & 0x7f;
+        boot_params.screen_info.orig_video_page = page;
+}
+
+/*
+ * Store the video mode parameters for later usage by the kernel.
+ * This is done by asking the BIOS except for the rows/columns
+ * parameters in the default 80x25 mode -- these are set directly,
+ * because some very obscure BIOSes supply insane values.
+ */
+static void store_mode_params(void)
+{
+        u16 font_size;
+        int x, y;
+
+        /* For graphics mode, it is up to the mode-setting driver
+           (currently only video-vesa.c) to store the parameters */
+        if (graphic_mode)
+                return;
+
+        store_cursor_position();
+        store_video_mode();
+
+        if (boot_params.screen_info.orig_video_mode == 0x07) {
+                /* MDA, HGC, or VGA in monochrome mode */
+                video_segment = 0xb000;
+        } else {
+                /* CGA, EGA, VGA and so forth */
+                video_segment = 0xb800;
+        }
+
+        set_fs(0);
+        font_size = rdfs16(0x485); /* Font size, BIOS area */
+        boot_params.screen_info.orig_video_points = font_size;
+
+        x = rdfs16(0x44a);
+        y = (adapter == ADAPTER_CGA) ? 25 : rdfs8(0x484)+1;
+
+        if (force_x)
+                x = force_x;
+        if (force_y)
+                y = force_y;
+
+        boot_params.screen_info.orig_video_cols  = x;
+        boot_params.screen_info.orig_video_lines = y;
+}
+
+/* Probe the video drivers and have them generate their mode lists. */
+static void probe_cards(int unsafe)
+{
+        struct card_info *card;
+        static u8 probed[2];
+
+        if (probed[unsafe])
+                return;
+
+        probed[unsafe] = 1;
+
+        for (card = video_cards; card < video_cards_end; card++) {
+                if (card->unsafe == unsafe) {
+                        if (card->probe)
+                                card->nmodes = card->probe();
+                        else
+                                card->nmodes = 0;
+                }
+        }
+}
+
+/* Test if a mode is defined */
+int mode_defined(u16 mode)
+{
+        struct card_info *card;
+        struct mode_info *mi;
+        int i;
+
+        for (card = video_cards; card < video_cards_end; card++) {
+                mi = card->modes;
+                for (i = 0; i < card->nmodes; i++, mi++) {
+                        if (mi->mode == mode)
+                                return 1;
+                }
+        }
+
+        return 0;
+}
+
+/* Set mode (without recalc) */
+static int raw_set_mode(u16 mode)
+{
+        int nmode, i;
+        struct card_info *card;
+        struct mode_info *mi;
+
+        /* Drop the recalc bit if set */
+        mode &= ~VIDEO_RECALC;
+
+        /* Scan for mode based on fixed ID, position, or resolution */
+        nmode = 0;
+        for (card = video_cards; card < video_cards_end; card++) {
+                mi = card->modes;
+                for (i = 0; i < card->nmodes; i++, mi++) {
+                        int visible = mi->x || mi->y;
+
+                        if ((mode == nmode && visible) ||
+                            mode == mi->mode ||
+                            mode == (mi->y << 8)+mi->x)
+                                return card->set_mode(mi);
+
+                        if (visible)
+                                nmode++;
+                }
+        }
+
+        /* Nothing found?  Is it an "exceptional" (unprobed) mode? */
+        for (card = video_cards; card < video_cards_end; card++) {
+                if (mode >= card->xmode_first &&
+                    mode < card->xmode_first+card->xmode_n) {
+                        struct mode_info mix;
+                        mix.mode = mode;
+                        mix.x = mix.y = 0;
+                        return card->set_mode(&mix);
+                }
+        }
+
+        /* Otherwise, failure... */
+        return -1;
+}
+
+/*
+ * Recalculate the vertical video cutoff (hack!)
+ */
+static void vga_recalc_vertical(void)
+{
+        unsigned int font_size, rows;
+        u16 crtc;
+        u8 ov;
+
+        set_fs(0);
+        font_size = rdfs8(0x485); /* BIOS: font size (pixels) */
+        rows = force_y ? force_y : rdfs8(0x484)+1; /* Text rows */
+
+        rows *= font_size;      /* Visible scan lines */
+        rows--;                 /* ... minus one */
+
+        crtc = vga_crtc();
+
+        out_idx((u8)rows, crtc, 0x12); /* Lower height register */
+        ov = in_idx(crtc, 0x07); /* Overflow register */
+        ov &= 0xbd;
+        ov |= (rows >> (8-1)) & 0x02;
+        ov |= (rows >> (9-6)) & 0x40;
+        out_idx(ov, crtc, 0x07);
+}
+
+/* Set mode (with recalc if specified) */
+static int set_mode(u16 mode)
+{
+        int rv;
+
+        /* Very special mode numbers... */
+        if (mode == VIDEO_CURRENT_MODE)
+                return 0;       /* Nothing to do... */
+        else if (mode == NORMAL_VGA)
+                mode = VIDEO_80x25;
+        else if (mode == EXTENDED_VGA)
+                mode = VIDEO_8POINT;
+
+        rv = raw_set_mode(mode);
+        if (rv)
+                return rv;
+
+        if (mode & VIDEO_RECALC)
+                vga_recalc_vertical();
+
+        return 0;
+}
+
+static unsigned int get_entry(void)
+{
+        char entry_buf[4];
+        int i, len = 0;
+        int key;
+        unsigned int v;
+
+        do {
+                key = getchar();
+
+                if (key == '\b') {
+                        if (len > 0) {
+                                puts("\b \b");
+                                len--;
+                        }
+                } else if ((key >= '0' && key <= '9') ||
+                           (key >= 'A' && key <= 'Z') ||
+                           (key >= 'a' && key <= 'z')) {
+                        if (len < sizeof entry_buf) {
+                                entry_buf[len++] = key;
+                                putchar(key);
+                        }
+                }
+        } while (key != '\r');
+        putchar('\n');
+
+        if (len == 0)
+                return VIDEO_CURRENT_MODE; /* Default */
+
+        v = 0;
+        for (i = 0; i < len; i++) {
+                v <<= 4;
+                key = entry_buf[i] | 0x20;
+                v += (key > '9') ? key-'a'+10 : key-'0';
+        }
+
+        return v;
+}
+
+static void display_menu(void)
+{
+        struct card_info *card;
+        struct mode_info *mi;
+        char ch;
+        int i;
+
+        puts("Mode:    COLSxROWS:\n");
+
+        ch = '0';
+        for (card = video_cards; card < video_cards_end; card++) {
+                mi = card->modes;
+                for (i = 0; i < card->nmodes; i++, mi++) {
+                        int visible = mi->x && mi->y;
+                        u16 mode_id = mi->mode ? mi->mode :
+                                (mi->y << 8)+mi->x;
+
+                        if (!visible)
+                                continue; /* Hidden mode */
+
+                        printf("%c  %04X  %3dx%-3d  %s\n",
+                               ch, mode_id, mi->x, mi->y, card->card_name);
+
+                        if (ch == '9')
+                                ch = 'a';
+                        else if (ch == 'z' || ch == ' ')
+                                ch = ' '; /* Out of keys... */
+                        else
+                                ch++;
+                }
+        }
+}
+
+#define H(x)    ((x)-'a'+10)
+#define SCAN    ((H('s')<<12)+(H('c')<<8)+(H('a')<<4)+H('n'))
+
+static unsigned int mode_menu(void)
+{
+        int key;
+        unsigned int sel;
+
+        puts("Press <ENTER> to see video modes available, "
+             "<SPACE> to continue, or wait 30 sec\n");
+
+        kbd_flush();
+        while (1) {
+                key = getchar_timeout();
+                if (key == ' ' || key == 0)
+                        return VIDEO_CURRENT_MODE; /* Default */
+                if (key == '\r')
+                        break;
+                putchar('\a');  /* Beep! */
+        }
+
+
+        for (;;) {
+                display_menu();
+
+                puts("Enter a video mode or \"scan\" to scan for "
+                     "additional modes: ");
+                sel = get_entry();
+                if (sel != SCAN)
+                        return sel;
+
+                probe_cards(1);
+        }
+}
+
+#ifdef CONFIG_VIDEO_RETAIN
+/* Save screen content to the heap */
+struct saved_screen {
+        int x, y;
+        int curx, cury;
+        u16 *data;
+} saved;
+
+static void save_screen(void)
+{
+        /* Should be called after store_mode_params() */
+        saved.x = boot_params.screen_info.orig_video_cols;
+        saved.y = boot_params.screen_info.orig_video_lines;
+        saved.curx = boot_params.screen_info.orig_x;
+        saved.cury = boot_params.screen_info.orig_y;
+
+        if (heap_free() < saved.x*saved.y*sizeof(u16)+512)
+                return;         /* Not enough heap to save the screen */
+
+        saved.data = GET_HEAP(u16, saved.x*saved.y);
+
+        set_fs(video_segment);
+        copy_from_fs(saved.data, 0, saved.x*saved.y*sizeof(u16));
+}
+
+static void restore_screen(void)
+{
+        /* Should be called after store_mode_params() */
+        int xs = boot_params.screen_info.orig_video_cols;
+        int ys = boot_params.screen_info.orig_video_lines;
+        int y;
+        addr_t dst = 0;
+        u16 *src = saved.data;
+        u16 ax, bx, dx;
+
+        if (graphic_mode)
+                return;         /* Can't restore onto a graphic mode */
+
+        if (!src)
+                return;         /* No saved screen contents */
+
+        /* Restore screen contents */
+
+        set_fs(video_segment);
+        for (y = 0; y < ys; y++) {
+                int npad;
+
+                if (y < saved.y) {
+                        int copy = (xs < saved.x) ? xs : saved.x;
+                        copy_to_fs(dst, src, copy*sizeof(u16));
+                        dst += copy*sizeof(u16);
+                        src += saved.x;
+                        npad = (xs < saved.x) ? 0 : xs-saved.x;
+                } else {
+                        npad = xs;
+                }
+
+                /* Writes "npad" blank characters to
+                   video_segment:dst and advances dst */
+                asm volatile("pushw %%es ; "
+                             "movw %2,%%es ; "
+                             "shrw %%cx ; "
+                             "jnc 1f ; "
+                             "stosw \n\t"
+                             "1: rep;stosl ; "
+                             "popw %%es"
+                             : "+D" (dst), "+c" (npad)
+                             : "bdSm" (video_segment),
+                               "a" (0x07200720));
+        }
+
+        /* Restore cursor position */
+        ax = 0x0200;            /* Set cursor position */
+        bx = 0;                 /* Page number (<< 8) */
+        dx = (saved.cury << 8)+saved.curx;
+        asm volatile(INT10
+                     : "+a" (ax), "+b" (bx), "+d" (dx)
+                     : : "ecx", "esi", "edi");
+}
+#else
+#define save_screen()           ((void)0)
+#define restore_screen()        ((void)0)
+#endif
+
+void set_video(void)
+{
+        u16 mode = boot_params.hdr.vid_mode;
+
+        RESET_HEAP();
+
+        store_mode_params();
+        save_screen();
+        probe_cards(0);
+
+        for (;;) {
+                if (mode == ASK_VGA)
+                        mode = mode_menu();
+
+                if (!set_mode(mode))
+                        break;
+
+                printf("Undefined video mode number: %x\n", mode);
+                mode = ASK_VGA;
+        }
+        vesa_store_edid();
+        store_mode_params();
+
+        if (do_restore)
+                restore_screen();
+}
diff --git a/arch/i386/boot/video.h b/arch/i386/boot/video.h
new file mode 100644
index 000000000000..29eca1710b2c
--- /dev/null
+++ b/arch/i386/boot/video.h
@@ -0,0 +1,145 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/video.h
+ *
+ * Header file for the real-mode video probing code
+ */
+
+#ifndef BOOT_VIDEO_H
+#define BOOT_VIDEO_H
+
+#include <linux/types.h>
+
+/* Enable autodetection of SVGA adapters and modes. */
+#undef CONFIG_VIDEO_SVGA
+
+/* Enable autodetection of VESA modes */
+#define CONFIG_VIDEO_VESA
+
+/* Retain screen contents when switching modes */
+#define CONFIG_VIDEO_RETAIN
+
+/* Force 400 scan lines for standard modes (hack to fix bad BIOS behaviour */
+#undef CONFIG_VIDEO_400_HACK
+
+/* This code uses an extended set of video mode numbers. These include:
+ * Aliases for standard modes
+ *      NORMAL_VGA (-1)
+ *      EXTENDED_VGA (-2)
+ *      ASK_VGA (-3)
+ * Video modes numbered by menu position -- NOT RECOMMENDED because of lack
+ * of compatibility when extending the table. These are between 0x00 and 0xff.
+ */
+#define VIDEO_FIRST_MENU 0x0000
+
+/* Standard BIOS video modes (BIOS number + 0x0100) */
+#define VIDEO_FIRST_BIOS 0x0100
+
+/* VESA BIOS video modes (VESA number + 0x0200) */
+#define VIDEO_FIRST_VESA 0x0200
+
+/* Video7 special modes (BIOS number + 0x0900) */
+#define VIDEO_FIRST_V7 0x0900
+
+/* Special video modes */
+#define VIDEO_FIRST_SPECIAL 0x0f00
+#define VIDEO_80x25 0x0f00
+#define VIDEO_8POINT 0x0f01
+#define VIDEO_80x43 0x0f02
+#define VIDEO_80x28 0x0f03
+#define VIDEO_CURRENT_MODE 0x0f04
+#define VIDEO_80x30 0x0f05
+#define VIDEO_80x34 0x0f06
+#define VIDEO_80x60 0x0f07
+#define VIDEO_GFX_HACK 0x0f08
+#define VIDEO_LAST_SPECIAL 0x0f09
+
+/* Video modes given by resolution */
+#define VIDEO_FIRST_RESOLUTION 0x1000
+
+/* The "recalculate timings" flag */
+#define VIDEO_RECALC 0x8000
+
+/* Define DO_STORE according to CONFIG_VIDEO_RETAIN */
+#ifdef CONFIG_VIDEO_RETAIN
+void store_screen(void);
+#define DO_STORE() store_screen()
+#else
+#define DO_STORE() ((void)0)
+#endif /* CONFIG_VIDEO_RETAIN */
+
+/*
+ * Mode table structures
+ */
+
+struct mode_info {
+        u16 mode;               /* Mode number (vga= style) */
+        u8  x, y;               /* Width, height */
+};
+
+struct card_info {
+        const char *card_name;
+        int (*set_mode)(struct mode_info *mode);
+        int (*probe)(void);
+        struct mode_info *modes;
+        int nmodes;             /* Number of probed modes so far */
+        int unsafe;             /* Probing is unsafe, only do after "scan" */
+        u16 xmode_first;        /* Unprobed modes to try to call anyway */
+        u16 xmode_n;            /* Size of unprobed mode range */
+};
+
+#define __videocard struct card_info __attribute__((section(".videocards")))
+extern struct card_info video_cards[], video_cards_end[];
+
+int mode_defined(u16 mode);     /* video.c */
+
+/* Basic video information */
+#define ADAPTER_CGA     0       /* CGA/MDA/HGC */
+#define ADAPTER_EGA     1
+#define ADAPTER_VGA     2
+
+extern int adapter;
+extern u16 video_segment;
+extern int force_x, force_y;    /* Don't query the BIOS for cols/rows */
+extern int do_restore;          /* Restore screen contents */
+extern int graphic_mode;        /* Graphics mode with linear frame buffer */
+
+/*
+ * int $0x10 is notorious for touching registers it shouldn't.
+ * gcc doesn't like %ebp being clobbered, so define it as a push/pop
+ * sequence here.
+ */
+#define INT10 "pushl %%ebp; int $0x10; popl %%ebp"
+
+/* Accessing VGA indexed registers */
+static inline u8 in_idx(u16 port, u8 index)
+{
+        outb(index, port);
+        return inb(port+1);
+}
+
+static inline void out_idx(u8 v, u16 port, u8 index)
+{
+        outw(index+(v << 8), port);
+}
+
+/* Writes a value to an indexed port and then reads the port again */
+static inline u8 tst_idx(u8 v, u16 port, u8 index)
+{
+        out_idx(port, index, v);
+        return in_idx(port, index);
+}
+
+/* Get the I/O port of the VGA CRTC */
+u16 vga_crtc(void);             /* video-vga.c */
+
+#endif /* BOOT_VIDEO_H */
diff --git a/arch/i386/boot/voyager.c b/arch/i386/boot/voyager.c
new file mode 100644
index 000000000000..9221614d0db8
--- /dev/null
+++ b/arch/i386/boot/voyager.c
@@ -0,0 +1,46 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 1991, 1992 Linus Torvalds
+ *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * arch/i386/boot/voyager.c
+ *
+ * Get the Voyager config information
+ */
+
+#include "boot.h"
+
+#ifdef CONFIG_X86_VOYAGER
+
+int query_voyager(void)
+{
+        u8 err;
+        u16 es, di;
+        /* Abuse the apm_bios_info area for this */
+        u8 *data_ptr = (u8 *)&boot_params.apm_bios_info;
+
+        data_ptr[0] = 0xff;     /* Flag on config not found(?) */
+
+        asm("pushw %%es ; "
+            "int $0x15 ; "
+            "setc %0 ; "
+            "movw %%es, %1 ; "
+            "popw %%es"
+            : "=qm" (err), "=rm" (es), "=D" (di)
+            : "a" (0xffc0));
+
+        if (err)
+                return -1;      /* Not Voyager */
+
+        set_fs(es);
+        copy_from_fs(data_ptr, di, 7);  /* Table is 7 bytes apparently */
+        return 0;
+}
+
+#endif /* CONFIG_X86_VOYAGER */
diff --git a/arch/i386/kernel/cpu/Makefile b/arch/i386/kernel/cpu/Makefile
index 74f27a463db0..0b6a8551e9e2 100644
--- a/arch/i386/kernel/cpu/Makefile
+++ b/arch/i386/kernel/cpu/Makefile
@@ -8,7 +8,7 @@ obj-y	+=	amd.o
 obj-y   +=      cyrix.o
 obj-y   +=      centaur.o
 obj-y   +=      transmeta.o
-obj-y   +=      intel.o intel_cacheinfo.o
+obj-y   +=      intel.o intel_cacheinfo.o addon_cpuid_features.o
 obj-y   +=      rise.o
 obj-y   +=      nexgen.o
 obj-y   +=      umc.o
diff --git a/arch/i386/kernel/cpu/addon_cpuid_features.c b/arch/i386/kernel/cpu/addon_cpuid_features.c
new file mode 100644
index 000000000000..3e91d3ee26ec
--- /dev/null
+++ b/arch/i386/kernel/cpu/addon_cpuid_features.c
@@ -0,0 +1,50 @@
+
+/*
+ *      Routines to indentify additional cpu features that are scattered in
+ *      cpuid space.
+ */
+
+#include <linux/cpu.h>
+
+#include <asm/processor.h>
+
+struct cpuid_bit {
+        u16 feature;
+        u8 reg;
+        u8 bit;
+        u32 level;
+};
+
+enum cpuid_regs {
+        CR_EAX = 0,
+        CR_ECX,
+        CR_EDX,
+        CR_EBX
+};
+
+void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
+{
+        u32 max_level;
+        u32 regs[4];
+        const struct cpuid_bit *cb;
+
+        static const struct cpuid_bit cpuid_bits[] = {
+                { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
+                { 0, 0, 0, 0 }
+        };
+
+        for (cb = cpuid_bits; cb->feature; cb++) {
+
+                /* Verify that the level is valid */
+                max_level = cpuid_eax(cb->level & 0xffff0000);
+                if (max_level < cb->level ||
+                    max_level > (cb->level | 0xffff))
+                        continue;
+
+                cpuid(cb->level, &regs[CR_EAX], &regs[CR_EBX],
+                        &regs[CR_ECX], &regs[CR_EDX]);
+
+                if (regs[cb->reg] & (1 << cb->bit))
+                        set_bit(cb->feature, c->x86_capability);
+        }
+}
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 794d593c47eb..e5419a9dec88 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -353,6 +353,8 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
                         if ( xlvl >= 0x80000004 )
                                 get_model_name(c); /* Default name */
                 }
+
+                init_scattered_cpuid_features(c);
         }
 
         early_intel_workaround(c);
diff --git a/arch/i386/kernel/cpu/proc.c b/arch/i386/kernel/cpu/proc.c
index 89d91e6cc972..1e31b6caffb1 100644
--- a/arch/i386/kernel/cpu/proc.c
+++ b/arch/i386/kernel/cpu/proc.c
@@ -29,7 +29,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
-                NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow",
+                NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
+                "3dnowext", "3dnow",
 
                 /* Transmeta-defined */
                 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
@@ -40,8 +41,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 /* Other (Linux-defined) */
                 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
                 NULL, NULL, NULL, NULL,
-                "constant_tsc", "up", NULL, NULL, NULL, NULL, NULL, NULL,
-                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                "constant_tsc", "up", NULL, "arch_perfmon",
+                "pebs", "bts", NULL, "sync_rdtsc",
+                "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
                 /* Intel-defined (#2) */
@@ -57,9 +59,16 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
                 /* AMD-defined (#2) */
-                "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8legacy", "abm",
-                "sse4a", "misalignsse",
-                "3dnowprefetch", "osvw", "ibs", NULL, NULL, NULL, NULL, NULL,
+                "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
+                "altmovcr8", "abm", "sse4a",
+                "misalignsse", "3dnowprefetch",
+                "osvw", "ibs", NULL, NULL, NULL, NULL,
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+
+                /* Auxiliary (Linux-defined) */
+                "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
         };
diff --git a/arch/i386/kernel/e820.c b/arch/i386/kernel/e820.c
index 9645bb51f76a..fc822a46897a 100644
--- a/arch/i386/kernel/e820.c
+++ b/arch/i386/kernel/e820.c
@@ -734,7 +734,7 @@ void __init print_memory_map(char *who)
                 case E820_NVS:
                                 printk("(ACPI NVS)\n");
                                 break;
-                default:        printk("type %lu\n", e820.map[i].type);
+                default:        printk("type %u\n", e820.map[i].type);
                                 break;
                 }
         }
diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c
index 698c24fe482e..2d61e65eeb50 100644
--- a/arch/i386/kernel/setup.c
+++ b/arch/i386/kernel/setup.c
@@ -102,19 +102,10 @@ static unsigned int highmem_pages = -1;
 /*
  * Setup options
  */
-struct drive_info_struct { char dummy[32]; } drive_info;
-#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_HD) || \
-    defined(CONFIG_BLK_DEV_IDE_MODULE) || defined(CONFIG_BLK_DEV_HD_MODULE)
-EXPORT_SYMBOL(drive_info);
-#endif
 struct screen_info screen_info;
 EXPORT_SYMBOL(screen_info);
 struct apm_info apm_info;
 EXPORT_SYMBOL(apm_info);
-struct sys_desc_table_struct {
-        unsigned short length;
-        unsigned char table[0];
-};
 struct edid_info edid_info;
 EXPORT_SYMBOL_GPL(edid_info);
 struct ist_info ist_info;
@@ -134,7 +125,7 @@ unsigned long saved_videomode;
 
 static char __initdata command_line[COMMAND_LINE_SIZE];
 
-unsigned char __initdata boot_params[PARAM_SIZE];
+struct boot_params __initdata boot_params;
 
 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 struct edd edd;
@@ -528,7 +519,6 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
         ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
-        drive_info = DRIVE_INFO;
         screen_info = SCREEN_INFO;
         edid_info = EDID_INFO;
         apm_info.bios = APM_BIOS_INFO;
diff --git a/arch/i386/kernel/verify_cpu.S b/arch/i386/kernel/verify_cpu.S
deleted file mode 100644
index f1d1eacf4ab0..000000000000
--- a/arch/i386/kernel/verify_cpu.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Check if CPU has some minimum CPUID bits
-   This runs in 16bit mode so that the caller can still use the BIOS
-   to output errors on the screen */
-#include <asm/cpufeature.h>
-#include <asm/msr.h>
-
-verify_cpu:
-        pushfl                          # Save caller passed flags
-        pushl   $0                      # Kill any dangerous flags
-        popfl
-
-#if CONFIG_X86_MINIMUM_CPU_MODEL >= 4
-        pushfl
-        pop     %eax
-        orl     $(1<<18),%eax           # try setting AC
-        push    %eax
-        popfl
-        pushfl
-        popl    %eax
-        testl   $(1<<18),%eax
-        jz      bad
-#endif
-#if REQUIRED_MASK1 != 0
-        pushfl                          # standard way to check for cpuid
-        popl    %eax
-        movl    %eax,%ebx
-        xorl    $0x200000,%eax
-        pushl   %eax
-        popfl
-        pushfl
-        popl    %eax
-        cmpl    %eax,%ebx
-        pushfl                          # standard way to check for cpuid
-        popl    %eax
-        movl    %eax,%ebx
-        xorl    $0x200000,%eax
-        pushl   %eax
-        popfl
-        pushfl
-        popl    %eax
-        cmpl    %eax,%ebx
-        jz      bad                     # REQUIRED_MASK1 != 0 requires CPUID
-
-        movl    $0x0,%eax               # See if cpuid 1 is implemented
-        cpuid
-        cmpl    $0x1,%eax
-        jb      bad                     # no cpuid 1
-
-#if REQUIRED_MASK1 & NEED_CMPXCHG64
-        /* Some VIA C3s need magic MSRs to enable CX64. Do this here */
-        cmpl    $0x746e6543,%ebx        # Cent
-        jne     1f
-        cmpl    $0x48727561,%edx        # aurH
-        jne     1f
-        cmpl    $0x736c7561,%ecx        # auls
-        jne     1f
-        movl    $1,%eax                 # check model
-        cpuid
-        movl    %eax,%ebx
-        shr     $8,%ebx
-        andl    $0xf,%ebx
-        cmp     $6,%ebx                 # check family == 6
-        jne     1f
-        shr     $4,%eax
-        andl    $0xf,%eax
-        cmpl    $6,%eax                 # check model >= 6
-        jb      1f
-        # assume models >= 6 all support this MSR
-        movl    $MSR_VIA_FCR,%ecx
-        rdmsr
-        orl     $((1<<1)|(1<<7)),%eax   # enable CMPXCHG64 and PGE
-        wrmsr
-1:
-#endif
-        movl    $0x1,%eax               # Does the cpu have what it takes
-        cpuid
-
-#if CONFIG_X86_MINIMUM_CPU_MODEL > 4
-#error  add proper model checking here
-#endif
-
-        andl    $REQUIRED_MASK1,%edx
-        xorl    $REQUIRED_MASK1,%edx
-        jnz     bad
-#endif /* REQUIRED_MASK1 */
-
-        popfl
-        xor     %eax,%eax
-        ret
-
-bad:
-        popfl
-        movl    $1,%eax
-        ret
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a00fabe2e4e0..5c863bcd5614 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -117,9 +117,9 @@ config MACH_JAZZ
         select ARC32
         select ARCH_MAY_HAVE_PC_FDC
         select GENERIC_ISA_DMA
-        select I8253
         select I8259
         select ISA
+        select PCSPEAKER
         select SYS_HAS_CPU_R4X00
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
@@ -347,9 +347,9 @@ config QEMU
         select DMA_COHERENT
         select GENERIC_ISA_DMA
         select HAVE_STD_PC_SERIAL_PORT
-        select I8253
         select I8259
         select ISA
+        select PCSPEAKER
         select SWAP_IO_SPACE
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
@@ -562,9 +562,9 @@ config SNI_RM
         select HW_HAS_EISA
         select HW_HAS_PCI
         select IRQ_CPU
-        select I8253
         select I8259
         select ISA
+        select PCSPEAKER
         select SWAP_IO_SPACE if CPU_BIG_ENDIAN
         select SYS_HAS_CPU_R4X00
         select SYS_HAS_CPU_R5000
@@ -1404,6 +1404,19 @@ config MIPS_MT_SMTC_INSTANT_REPLAY
           it off), but ensures that IPIs are handled promptly even under
           heavy I/O interrupt load.
 
+config MIPS_MT_SMTC_IM_BACKSTOP
+        bool "Use per-TC register bits as backstop for inhibited IM bits"
+        depends on MIPS_MT_SMTC
+        default y
+        help
+          To support multiple TC microthreads acting as "CPUs" within
+          a VPE, VPE-wide interrupt mask bits must be specially manipulated
+          during interrupt handling. To support legacy drivers and interrupt
+          controller management code, SMTC has a "backstop" to track and
+          if necessary restore the interrupt mask. This has some performance
+          impact on interrupt service overhead. Disable it only if you know
+          what you are doing.
+
 config MIPS_VPE_LOADER_TOM
         bool "Load VPE program into memory hidden from linux"
         depends on MIPS_VPE_LOADER
@@ -1851,7 +1864,7 @@ config MMU
         bool
         default y
 
-config I8253
+config PCSPEAKER
         bool
 
 source "drivers/pcmcia/Kconfig"
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 13fe187f35d6..fdf2b85a69c8 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -100,9 +100,6 @@ void __init plat_mem_setup(void)
         argptr = prom_getcmdline();
         /* default panel */
         /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
-#ifdef CONFIG_MIPS_HYDROGEN3
-         strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
-#endif
     }
 #endif
 
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index dd04eece9fd3..8a0b4ac5283d 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -241,7 +241,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 #
 CONFIG_ISA=y
 CONFIG_MMU=y
-CONFIG_I8253=y
+CONFIG_PCSPEAKER=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 6cca105832ca..703de002e372 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -221,7 +221,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
 #
 CONFIG_ISA=y
 CONFIG_MMU=y
-CONFIG_I8253=y
+CONFIG_PCSPEAKER=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 1a67a85aabbb..a5dc5cb97aae 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -251,7 +251,7 @@ CONFIG_PCI=y
 CONFIG_ISA=y
 # CONFIG_EISA is not set
 CONFIG_MMU=y
-CONFIG_I8253=y
+CONFIG_PCSPEAKER=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index f1cdb12f7925..f342d8c887b8 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -592,8 +592,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_RTC is not set
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 961594cb5214..5c8085b6d7ab 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -63,7 +63,7 @@ obj-$(CONFIG_PROC_FS)		+= proc.o
 
 obj-$(CONFIG_64BIT)             += cpu-bugs64.o
 
-obj-$(CONFIG_I8253)             += i8253.o
+obj-$(CONFIG_PCSPEAKER)         += pcspeaker.o
 
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 686249c5c328..e29598ae939d 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -84,6 +84,7 @@ FEXPORT(restore_all)			# restore full frame
         LONG_S  sp, TI_REGS($28)
         jal     deferred_smtc_ipi
         LONG_S  s0, TI_REGS($28)
+#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 /* Re-arm any temporarily masked interrupts not explicitly "acked" */
         mfc0    v0, CP0_TCSTATUS
         ori     v1, v0, TCSTATUS_IXMT
@@ -110,6 +111,7 @@ FEXPORT(restore_all)			# restore full frame
         _ehb
         xor     t0, t0, t3
         mtc0    t0, CP0_TCCONTEXT
+#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
 #endif /* CONFIG_MIPS_MT_SMTC */
         .set    noat
         RESTORE_TEMP
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 297bd56c2347..c0f19d638b98 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -243,9 +243,11 @@ NESTED(except_vec_vi_handler, 0, sp)
          */
         mfc0    t1, CP0_STATUS
         and     t0, a0, t1
+#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
         mfc0    t2, CP0_TCCONTEXT
         or      t0, t0, t2
         mtc0    t0, CP0_TCCONTEXT
+#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
         xor     t1, t1, t0
         mtc0    t1, CP0_STATUS
         _ehb
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/pcspeaker.c
index 475df6904219..475df6904219 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/pcspeaker.c
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 06729596812f..d9bfae53c43f 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -85,12 +85,7 @@
         move    $28, a2
         cpu_restore_nonscratch a1
 
-#if (_THREAD_SIZE - 32) < 0x10000
-        PTR_ADDIU       t0, $28, _THREAD_SIZE - 32
-#else
-        PTR_LI          t0, _THREAD_SIZE - 32
-        PTR_ADDU        t0, $28
-#endif
+        PTR_ADDU        t0, $28, _THREAD_SIZE - 32
         set_saved_sp    t0, t1, t2
 #ifdef CONFIG_MIPS_MT_SMTC
         /* Read-modify-writes of Status must be atomic on a VPE */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 80ea4fa95bd9..5e9fa83c4ef0 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -373,7 +373,7 @@ asmlinkage void do_be(struct pt_regs *regs)
                 action = MIPS_BE_FIXUP;
 
         if (board_be_handler)
-                action = board_be_handler(regs, fixup != 0);
+                action = board_be_handler(regs, fixup != NULL);
 
         switch (action) {
         case MIPS_BE_DISCARD:
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 1a4db7dc77cb..465ff0ec85b9 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -10,6 +10,7 @@
 #include <asm/mipsregs.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
+#include <asm/tlbdebug.h>
 
 static inline const char *msk2str(unsigned int mask)
 {
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
index 52f87795ecc3..9cee907975ae 100644
--- a/arch/mips/lib/r3k_dump_tlb.c
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -11,6 +11,7 @@
 #include <asm/mipsregs.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
+#include <asm/tlbdebug.h>
 
 extern int r3k_have_wired_reg;  /* defined in tlb-r3k.c */
 
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 2388f7f3ffde..58d14f4d9349 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -12,6 +12,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/bug.h>
+#include <asm/cacheflush.h>
 
 #ifndef CKSEG2
 #define CKSEG2 CKSSEG
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
index d86b37235cf6..5cbc3509ab52 100644
--- a/arch/mips/mipssim/sim_int.c
+++ b/arch/mips/mipssim/sim_int.c
@@ -77,7 +77,7 @@ asmlinkage void plat_irq_dispatch(void)
         irq = irq_ffs(pending);
 
         if (irq > 0)
-                do_IRQ(MIPSCPU_INT_BASE + irq);
+                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
 }
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 3643582bdade..60e66906be65 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -84,7 +84,7 @@ static void __init serial_init(void)
         /* hardware int 4 - the serial int, is CPU int 6
          but poll for now */
         s.irq =  0;
-        s.uartclk = BASE_BAUD * 16;
+        s.uartclk = 1843200;
         s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
         s.iotype = UPIO_PORT;
         s.regshift = 0;
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index 874a18e8ac24..a0f5a5dca1b2 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -5,7 +5,6 @@
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/mc146818rtc.h>
-#include <linux/mipsregs.h>
 #include <linux/smp.h>
 #include <linux/timex.h>
 
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 8108231f2e20..99d8f4fd3ff4 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -269,7 +269,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
         }
 
         for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
-                struct pci_dev *dev = pci_dev_b(ln);
+                dev = pci_dev_b(ln);
 
                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
                         pcibios_fixup_device_resources(dev, bus);
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c
deleted file mode 100644
index 97c73c793c35..000000000000
--- a/arch/mips/sibyte/swarm/time.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Copyright (C) 2000, 2001 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-/*
- * Time routines for the swarm board.  We pass all the hard stuff
- * through to the sb1250 handling code.  Only thing we really keep
- * track of here is what time of day we think it is.  And we don't
- * really even do a good job of that...
- */
-
-
-#include <linux/bcd.h>
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <asm/system.h>
-#include <asm/addrspace.h>
-#include <asm/io.h>
-
-#include <asm/sibyte/sb1250.h>
-#include <asm/sibyte/sb1250_regs.h>
-#include <asm/sibyte/sb1250_smbus.h>
-
-static unsigned long long sec_bias = 0;
-static unsigned int usec_bias = 0;
-
-/* Xicor 1241 definitions */
-
-/*
- * Register bits
- */
-
-#define X1241REG_SR_BAT 0x80            /* currently on battery power */
-#define X1241REG_SR_RWEL 0x04           /* r/w latch is enabled, can write RTC */
-#define X1241REG_SR_WEL 0x02            /* r/w latch is unlocked, can enable r/w now */
-#define X1241REG_SR_RTCF 0x01           /* clock failed */
-#define X1241REG_BL_BP2 0x80            /* block protect 2 */
-#define X1241REG_BL_BP1 0x40            /* block protect 1 */
-#define X1241REG_BL_BP0 0x20            /* block protect 0 */
-#define X1241REG_BL_WD1 0x10
-#define X1241REG_BL_WD0 0x08
-#define X1241REG_HR_MIL 0x80            /* military time format */
-
-/*
- * Register numbers
- */
-
-#define X1241REG_BL     0x10            /* block protect bits */
-#define X1241REG_INT    0x11            /*  */
-#define X1241REG_SC     0x30            /* Seconds */
-#define X1241REG_MN     0x31            /* Minutes */
-#define X1241REG_HR     0x32            /* Hours */
-#define X1241REG_DT     0x33            /* Day of month */
-#define X1241REG_MO     0x34            /* Month */
-#define X1241REG_YR     0x35            /* Year */
-#define X1241REG_DW     0x36            /* Day of Week */
-#define X1241REG_Y2K    0x37            /* Year 2K */
-#define X1241REG_SR     0x3F            /* Status register */
-
-#define X1241_CCR_ADDRESS       0x6F
-
-#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg)))
-
-static int xicor_read(uint8_t addr)
-{
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
-
-        __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
-        __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
-        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
-                     SMB_CSR(R_SMB_START));
-
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
-
-        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
-                     SMB_CSR(R_SMB_START));
-
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
-
-        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-                /* Clear error bit by writing a 1 */
-                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-                return -1;
-        }
-
-        return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
-}
-
-static int xicor_write(uint8_t addr, int b)
-{
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
-
-        __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
-        __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
-        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
-                     SMB_CSR(R_SMB_START));
-
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
-
-        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-                /* Clear error bit by writing a 1 */
-                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-                return -1;
-        } else {
-                return 0;
-        }
-}
-
-/*
- * In order to set the CMOS clock precisely, set_rtc_mmss has to be
- * called 500 ms after the second nowtime has started, because when
- * nowtime is written into the registers of the CMOS clock, it will
- * jump to the next second precisely 500 ms later. Check the Motorola
- * MC146818A or Dallas DS12887 data sheet for details.
- *
- * BUG: This routine does not handle hour overflow properly; it just
- *      sets the minutes. Usually you'll only notice that after reboot!
- */
-int set_rtc_mmss(unsigned long nowtime)
-{
-        int retval = 0;
-        int real_seconds, real_minutes, cmos_minutes;
-
-        cmos_minutes = xicor_read(X1241REG_MN);
-        cmos_minutes = BCD2BIN(cmos_minutes);
-
-        /*
-         * since we're only adjusting minutes and seconds,
-         * don't interfere with hour overflow. This avoids
-         * messing with unknown time zones but requires your
-         * RTC not to be off by more than 15 minutes
-         */
-        real_seconds = nowtime % 60;
-        real_minutes = nowtime / 60;
-        if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
-                real_minutes += 30;             /* correct for half hour time zone */
-        real_minutes %= 60;
-
-        /* unlock writes to the CCR */
-        xicor_write(X1241REG_SR, X1241REG_SR_WEL);
-        xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
-
-        if (abs(real_minutes - cmos_minutes) < 30) {
-                real_seconds = BIN2BCD(real_seconds);
-                real_minutes = BIN2BCD(real_minutes);
-                xicor_write(X1241REG_SC, real_seconds);
-                xicor_write(X1241REG_MN, real_minutes);
-        } else {
-                printk(KERN_WARNING
-                       "set_rtc_mmss: can't update from %d to %d\n",
-                       cmos_minutes, real_minutes);
-                retval = -1;
-        }
-
-        xicor_write(X1241REG_SR, 0);
-
-        printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds);
-
-        return retval;
-}
-
-static unsigned long __init get_swarm_time(void)
-{
-        unsigned int year, mon, day, hour, min, sec, y2k;
-
-        sec = xicor_read(X1241REG_SC);
-        min = xicor_read(X1241REG_MN);
-        hour = xicor_read(X1241REG_HR);
-
-        if (hour & X1241REG_HR_MIL) {
-                hour &= 0x3f;
-        } else {
-                if (hour & 0x20)
-                        hour = (hour & 0xf) + 0x12;
-        }
-
-        sec = BCD2BIN(sec);
-        min = BCD2BIN(min);
-        hour = BCD2BIN(hour);
-
-        day = xicor_read(X1241REG_DT);
-        mon = xicor_read(X1241REG_MO);
-        year = xicor_read(X1241REG_YR);
-        y2k = xicor_read(X1241REG_Y2K);
-
-        day = BCD2BIN(day);
-        mon = BCD2BIN(mon);
-        year = BCD2BIN(year);
-        y2k = BCD2BIN(y2k);
-
-        year += (y2k * 100);
-
-        return mktime(year, mon, day, hour, min, sec);
-}
-
-/*
- *  Bring up the timer at 100 Hz.
- */
-void __init swarm_time_init(void)
-{
-        unsigned int flags;
-        int status;
-
-        /* Set up the scd general purpose timer 0 to cpu 0 */
-        sb1250_time_init();
-
-        /* Establish communication with the Xicor 1241 RTC */
-        /* XXXKW how do I share the SMBus with the I2C subsystem? */
-
-        __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
-        __raw_writeq(0, SMB_CSR(R_SMB_CONTROL));
-
-        if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
-                printk("x1241: couldn't detect on SWARM SMBus 1\n");
-        } else {
-                if (status & X1241REG_SR_RTCF)
-                        printk("x1241: battery failed -- time is probably wrong\n");
-                write_seqlock_irqsave(&xtime_lock, flags);
-                xtime.tv_sec = get_swarm_time();
-                xtime.tv_nsec = 0;
-                write_sequnlock_irqrestore(&xtime_lock, flags);
-        }
-}
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 6850a29defcd..acc9ba76c1a9 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -87,8 +87,8 @@ static struct platform_device snirm_82596_pdev = {
 
 static struct resource snirm_53c710_rsrc[] = {
         {
-                .start = 0xb9000000,
-                .end   = 0xb90fffff,
+                .start = 0x19000000,
+                .end   = 0x190fffff,
                 .flags = IORESOURCE_MEM
         },
         {
@@ -106,8 +106,8 @@ static struct platform_device snirm_53c710_pdev = {
 
 static struct resource sc26xx_rsrc[] = {
         {
-                .start = 0xbc070000,
-                .end   = 0xbc0700ff,
+                .start = 0x1c070000,
+                .end   = 0x1c0700ff,
                 .flags = IORESOURCE_MEM
         },
         {
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 4bfda020fdc7..28a11d8605ce 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -88,8 +88,8 @@ static struct platform_device snirm_82596_rm200_pdev = {
 
 static struct resource snirm_53c710_rm200_rsrc[] = {
         {
-                .start = 0xb9000000,
-                .end   = 0xb90fffff,
+                .start = 0x19000000,
+                .end   = 0x190fffff,
                 .flags = IORESOURCE_MEM
         },
         {
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index f842783acd86..d0d84ec8d63d 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -2,4 +2,4 @@
 # Makefile for common code of the NEC VR4100 series.
 #
 
-obj-y   += bcu.o cmu.o icu.o init.o irq.o pmu.o type.o
+obj-y   += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o
diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c
new file mode 100644
index 000000000000..d21f6f2d22a3
--- /dev/null
+++ b/arch/mips/vr41xx/common/giu.c
@@ -0,0 +1,122 @@
+/*
+ *  NEC VR4100 series GIU platform device.
+ *
+ *  Copyright (C) 2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/cpu.h>
+#include <asm/vr41xx/giu.h>
+#include <asm/vr41xx/irq.h>
+
+static struct resource giu_50pins_pullupdown_resource[] __initdata = {
+        {
+                .start  = 0x0b000100,
+                .end    = 0x0b00011f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x0b0002e0,
+                .end    = 0x0b0002e3,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = GIUINT_IRQ,
+                .end    = GIUINT_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource giu_36pins_resource[] __initdata = {
+        {
+                .start  = 0x0f000140,
+                .end    = 0x0f00015f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = GIUINT_IRQ,
+                .end    = GIUINT_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource giu_48pins_resource[] __initdata = {
+        {
+                .start  = 0x0f000140,
+                .end    = 0x0f000167,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = GIUINT_IRQ,
+                .end    = GIUINT_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static int __init vr41xx_giu_add(void)
+{
+        struct platform_device *pdev;
+        struct resource *res;
+        unsigned int num;
+        int retval;
+
+        pdev = platform_device_alloc("GIU", -1);
+        if (!pdev)
+                return -ENOMEM;
+
+        switch (current_cpu_data.cputype) {
+        case CPU_VR4111:
+        case CPU_VR4121:
+                pdev->id = GPIO_50PINS_PULLUPDOWN;
+                res = giu_50pins_pullupdown_resource;
+                num = ARRAY_SIZE(giu_50pins_pullupdown_resource);
+                break;
+        case CPU_VR4122:
+        case CPU_VR4131:
+                pdev->id = GPIO_36PINS;
+                res = giu_36pins_resource;
+                num = ARRAY_SIZE(giu_36pins_resource);
+                break;
+        case CPU_VR4133:
+                pdev->id = GPIO_48PINS_EDGE_SELECT;
+                res = giu_48pins_resource;
+                num = ARRAY_SIZE(giu_48pins_resource);
+                break;
+        default:
+                retval = -ENODEV;
+                goto err_free_device;
+        }
+
+        retval = platform_device_add_resources(pdev, res, num);
+        if (retval)
+                goto err_free_device;
+
+        retval = platform_device_add(pdev);
+        if (retval)
+                goto err_free_device;
+
+        return 0;
+
+err_free_device:
+        platform_device_put(pdev);
+
+        return retval;
+}
+device_initcall(vr41xx_giu_add);
diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c
new file mode 100644
index 000000000000..cce605b3d688
--- /dev/null
+++ b/arch/mips/vr41xx/common/rtc.c
@@ -0,0 +1,117 @@
+/*
+ *  NEC VR4100 series RTC platform device.
+ *
+ *  Copyright (C) 2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/cpu.h>
+#include <asm/vr41xx/irq.h>
+
+static struct resource rtc_type1_resource[] __initdata = {
+        {
+                .start  = 0x0b0000c0,
+                .end    = 0x0b0000df,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x0b0001c0,
+                .end    = 0x0b0001df,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = ELAPSEDTIME_IRQ,
+                .end    = ELAPSEDTIME_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = RTCLONG1_IRQ,
+                .end    = RTCLONG1_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource rtc_type2_resource[] __initdata = {
+        {
+                .start  = 0x0f000100,
+                .end    = 0x0f00011f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x0f000120,
+                .end    = 0x0f00013f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = ELAPSEDTIME_IRQ,
+                .end    = ELAPSEDTIME_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = RTCLONG1_IRQ,
+                .end    = RTCLONG1_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static int __init vr41xx_rtc_add(void)
+{
+        struct platform_device *pdev;
+        struct resource *res;
+        unsigned int num;
+        int retval;
+
+        pdev = platform_device_alloc("RTC", -1);
+        if (!pdev)
+                return -ENOMEM;
+
+        switch (current_cpu_data.cputype) {
+        case CPU_VR4111:
+        case CPU_VR4121:
+                res = rtc_type1_resource;
+                num = ARRAY_SIZE(rtc_type1_resource);
+                break;
+        case CPU_VR4122:
+        case CPU_VR4131:
+        case CPU_VR4133:
+                res = rtc_type2_resource;
+                num = ARRAY_SIZE(rtc_type2_resource);
+                break;
+        default:
+                retval = -ENODEV;
+                goto err_free_device;
+        }
+
+        retval = platform_device_add_resources(pdev, res, num);
+        if (retval)
+                goto err_free_device;
+
+        retval = platform_device_add(pdev);
+        if (retval)
+                goto err_free_device;
+
+        return 0;
+
+err_free_device:
+        platform_device_put(pdev);
+
+        return retval;
+}
+device_initcall(vr41xx_rtc_add);
diff --git a/arch/mips/vr41xx/common/siu.c b/arch/mips/vr41xx/common/siu.c
new file mode 100644
index 000000000000..a1e774142163
--- /dev/null
+++ b/arch/mips/vr41xx/common/siu.c
@@ -0,0 +1,120 @@
+/*
+ *  NEC VR4100 series SIU platform device.
+ *
+ *  Copyright (C) 2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+
+#include <asm/cpu.h>
+#include <asm/vr41xx/siu.h>
+
+static unsigned int siu_type1_ports[SIU_PORTS_MAX] __initdata = {
+        PORT_VR41XX_SIU,
+        PORT_UNKNOWN,
+};
+
+static struct resource siu_type1_resource[] __initdata = {
+        {
+                .start  = 0x0c000000,
+                .end    = 0x0c00000a,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = SIU_IRQ,
+                .end    = SIU_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static unsigned int siu_type2_ports[SIU_PORTS_MAX] __initdata = {
+        PORT_VR41XX_SIU,
+        PORT_VR41XX_DSIU,
+};
+
+static struct resource siu_type2_resource[] __initdata = {
+        {
+                .start  = 0x0f000800,
+                .end    = 0x0f00080a,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x0f000820,
+                .end    = 0x0f000829,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = SIU_IRQ,
+                .end    = SIU_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = DSIU_IRQ,
+                .end    = DSIU_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static int __init vr41xx_siu_add(void)
+{
+        struct platform_device *pdev;
+        struct resource *res;
+        unsigned int num;
+        int retval;
+
+        pdev = platform_device_alloc("SIU", -1);
+        if (!pdev)
+                return -ENOMEM;
+
+        switch (current_cpu_data.cputype) {
+        case CPU_VR4111:
+        case CPU_VR4121:
+                pdev->dev.platform_data = siu_type1_ports;
+                res = siu_type1_resource;
+                num = ARRAY_SIZE(siu_type1_resource);
+                break;
+        case CPU_VR4122:
+        case CPU_VR4131:
+        case CPU_VR4133:
+                pdev->dev.platform_data = siu_type2_ports;
+                res = siu_type2_resource;
+                num = ARRAY_SIZE(siu_type2_resource);
+                break;
+        default:
+                retval = -ENODEV;
+                goto err_free_device;
+        }
+
+        retval = platform_device_add_resources(pdev, res, num);
+        if (retval)
+                goto err_free_device;
+
+        retval = platform_device_add(pdev);
+        if (retval)
+                goto err_free_device;
+
+        return 0;
+
+err_free_device:
+        platform_device_put(pdev);
+
+        return retval;
+}
+device_initcall(vr41xx_siu_add);
diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig
index 5ce94430c019..8bdd25ac1542 100644
--- a/arch/x86_64/Kconfig
+++ b/arch/x86_64/Kconfig
@@ -427,6 +427,10 @@ config NR_CPUS
           This is purely to save memory - each supported CPU requires
           memory in the static kernel configuration.
 
+config PHYSICAL_ALIGN
+        hex
+        default "0x200000"
+
 config HOTPLUG_CPU
         bool "Support for suspend on SMP and hot-pluggable CPUs (EXPERIMENTAL)"
         depends on SMP && HOTPLUG && EXPERIMENTAL
diff --git a/arch/x86_64/boot/Makefile b/arch/x86_64/boot/Makefile
index ee6f6505f95f..67096389de1f 100644
--- a/arch/x86_64/boot/Makefile
+++ b/arch/x86_64/boot/Makefile
@@ -1,135 +1,9 @@
 #
 # arch/x86_64/boot/Makefile
 #
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1994 by Linus Torvalds
-#
-
-# ROOT_DEV specifies the default root-device when making the image.
-# This can be either FLOPPY, CURRENT, /dev/xxxx or empty, in which case
-# the default of FLOPPY is used by 'build'.
-
-ROOT_DEV := CURRENT
-
-# If you want to preset the SVGA mode, uncomment the next line and
-# set SVGA_MODE to whatever number you want.
-# Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode.
-# The number is the same as you would ordinarily press at bootup.
-
-SVGA_MODE := -DSVGA_MODE=NORMAL_VGA
-
-# If you want the RAM disk device, define this to be the size in blocks.
-
-#RAMDISK := -DRAMDISK=512
-
-targets         := vmlinux.bin bootsect bootsect.o \
-                   setup setup.o bzImage mtools.conf
-
-EXTRA_CFLAGS := -m32
-
-hostprogs-y     := tools/build
-HOST_EXTRACFLAGS += $(LINUXINCLUDE)
-subdir-         := compressed/  #Let make clean descend in compressed/
-# ---------------------------------------------------------------------------
-
-$(obj)/bzImage: IMAGE_OFFSET := 0x100000
-$(obj)/bzImage: EXTRA_AFLAGS := $(SVGA_MODE) $(RAMDISK) -D__BIG_KERNEL__
-$(obj)/bzImage: BUILDFLAGS   := -b
-
-quiet_cmd_image = BUILD   $@
-cmd_image = $(obj)/tools/build $(BUILDFLAGS) $(obj)/bootsect $(obj)/setup \
-            $(obj)/vmlinux.bin $(ROOT_DEV) > $@
-
-$(obj)/bzImage: $(obj)/bootsect $(obj)/setup \
-                              $(obj)/vmlinux.bin $(obj)/tools/build FORCE
-        $(call if_changed,image)
-        @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
-
-$(obj)/vmlinux.bin: $(obj)/compressed/vmlinux FORCE
-        $(call if_changed,objcopy)
-
-LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
-LDFLAGS_setup    := -Ttext 0x0 -s --oformat binary -e begtext
-
-$(obj)/setup $(obj)/bootsect: %: %.o FORCE
-        $(call if_changed,ld)
-
-$(obj)/compressed/vmlinux: FORCE
-        $(Q)$(MAKE) $(build)=$(obj)/compressed IMAGE_OFFSET=$(IMAGE_OFFSET) $@
-
-# Set this if you want to pass append arguments to the zdisk/fdimage/isoimage kernel
-FDARGS = 
-# Set this if you want an initrd included with the zdisk/fdimage/isoimage kernel
-FDINITRD =
-
-image_cmdline = default linux $(FDARGS) $(if $(FDINITRD),initrd=initrd.img,)
-
-$(obj)/mtools.conf: $(src)/mtools.conf.in
-        sed -e 's|@OBJ@|$(obj)|g' < $< > $@
-
-# This requires write access to /dev/fd0
-zdisk: $(BOOTIMAGE) $(obj)/mtools.conf
-        MTOOLSRC=$(obj)/mtools.conf mformat a:                  ; sync
-        syslinux /dev/fd0                                       ; sync
-        echo '$(image_cmdline)' | \
-                MTOOLSRC=$(obj)/mtools.conf mcopy - a:syslinux.cfg
-        if [ -f '$(FDINITRD)' ] ; then \
-                MTOOLSRC=$(obj)/mtools.conf mcopy '$(FDINITRD)' a:initrd.img ; \
-        fi
-        MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) a:linux  ; sync
-
-# These require being root or having syslinux 2.02 or higher installed
-fdimage fdimage144: $(BOOTIMAGE) $(obj)/mtools.conf
-        dd if=/dev/zero of=$(obj)/fdimage bs=1024 count=1440
-        MTOOLSRC=$(obj)/mtools.conf mformat v:                  ; sync
-        syslinux $(obj)/fdimage                                 ; sync
-        echo '$(image_cmdline)' | \
-                MTOOLSRC=$(obj)/mtools.conf mcopy - v:syslinux.cfg
-        if [ -f '$(FDINITRD)' ] ; then \
-                MTOOLSRC=$(obj)/mtools.conf mcopy '$(FDINITRD)' v:initrd.img ; \
-        fi
-        MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) v:linux  ; sync
-
-fdimage288: $(BOOTIMAGE) $(obj)/mtools.conf
-        dd if=/dev/zero of=$(obj)/fdimage bs=1024 count=2880
-        MTOOLSRC=$(obj)/mtools.conf mformat w:                  ; sync
-        syslinux $(obj)/fdimage                                 ; sync
-        echo '$(image_cmdline)' | \
-                MTOOLSRC=$(obj)/mtools.conf mcopy - w:syslinux.cfg
-        if [ -f '$(FDINITRD)' ] ; then \
-                MTOOLSRC=$(obj)/mtools.conf mcopy '$(FDINITRD)' w:initrd.img ; \
-        fi
-        MTOOLSRC=$(obj)/mtools.conf mcopy $(BOOTIMAGE) w:linux  ; sync
-
-isoimage: $(BOOTIMAGE)
-        -rm -rf $(obj)/isoimage
-        mkdir $(obj)/isoimage
-        for i in lib lib64 share end ; do \
-                if [ -f /usr/$$i/syslinux/isolinux.bin ] ; then \
-                        cp /usr/$$i/syslinux/isolinux.bin $(obj)/isoimage ; \
-                        break ; \
-                fi ; \
-                if [ $$i = end ] ; then exit 1 ; fi ; \
-        done
-        cp $(BOOTIMAGE) $(obj)/isoimage/linux
-        echo '$(image_cmdline)' > $(obj)/isoimage/isolinux.cfg
-        if [ -f '$(FDINITRD)' ] ; then \
-                cp '$(FDINITRD)' $(obj)/isoimage/initrd.img ; \
-        fi
-        mkisofs -J -r -o $(obj)/image.iso -b isolinux.bin -c boot.cat \
-                -no-emul-boot -boot-load-size 4 -boot-info-table \
-                $(obj)/isoimage
-        rm -rf $(obj)/isoimage
-
-zlilo: $(BOOTIMAGE)
-        if [ -f $(INSTALL_PATH)/vmlinuz ]; then mv $(INSTALL_PATH)/vmlinuz $(INSTALL_PATH)/vmlinuz.old; fi
-        if [ -f $(INSTALL_PATH)/System.map ]; then mv $(INSTALL_PATH)/System.map $(INSTALL_PATH)/System.old; fi
-        cat $(BOOTIMAGE) > $(INSTALL_PATH)/vmlinuz
-        cp System.map $(INSTALL_PATH)/
-        if [ -x /sbin/lilo ]; then /sbin/lilo; else /etc/lilo/install; fi
+# The actual boot code is shared with i386 including the Makefile.
+# So tell kbuild that we fetch the code from i386 and include the
+# Makefile from i386 too.
 
-install:
-        sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
+src := arch/i386/boot
+include $(src)/Makefile
diff --git a/arch/x86_64/boot/bootsect.S b/arch/x86_64/boot/bootsect.S
deleted file mode 100644
index 011b7a4993d4..000000000000
--- a/arch/x86_64/boot/bootsect.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *      bootsect.S              Copyright (C) 1991, 1992 Linus Torvalds
- *
- *      modified by Drew Eckhardt
- *      modified by Bruce Evans (bde)
- *      modified by Chris Noe (May 1999) (as86 -> gas)
- *      gutted by H. Peter Anvin (Jan 2003)
- *
- * BIG FAT NOTE: We're in real mode using 64k segments.  Therefore segment
- * addresses must be multiplied by 16 to obtain their respective linear
- * addresses. To avoid confusion, linear addresses are written using leading
- * hex while segment addresses are written as segment:offset.
- *
- */
-
-#include <asm/boot.h>
-
-SETUPSECTS      = 4                     /* default nr of setup-sectors */
-BOOTSEG         = 0x07C0                /* original address of boot-sector */
-INITSEG         = DEF_INITSEG           /* we move boot here - out of the way */
-SETUPSEG        = DEF_SETUPSEG          /* setup starts here */
-SYSSEG          = DEF_SYSSEG            /* system loaded at 0x10000 (65536) */
-SYSSIZE         = DEF_SYSSIZE           /* system size: # of 16-byte clicks */
-                                        /* to be loaded */
-ROOT_DEV        = 0                     /* ROOT_DEV is now written by "build" */
-SWAP_DEV        = 0                     /* SWAP_DEV is now written by "build" */
-
-#ifndef SVGA_MODE
-#define SVGA_MODE ASK_VGA
-#endif
-
-#ifndef RAMDISK
-#define RAMDISK 0
-#endif
-
-#ifndef ROOT_RDONLY
-#define ROOT_RDONLY 1
-#endif
-
-.code16
-.text
-
-.global _start
-_start:
-
-        # Normalize the start address
-        jmpl    $BOOTSEG, $start2
-
-start2:
-        movw    %cs, %ax
-        movw    %ax, %ds
-        movw    %ax, %es
-        movw    %ax, %ss
-        movw    $0x7c00, %sp
-        sti
-        cld
-
-        movw    $bugger_off_msg, %si
-
-msg_loop:
-        lodsb
-        andb    %al, %al
-        jz      die
-        movb    $0xe, %ah
-        movw    $7, %bx
-        int     $0x10
-        jmp     msg_loop
-
-die:
-        # Allow the user to press a key, then reboot
-        xorw    %ax, %ax
-        int     $0x16
-        int     $0x19
-
-        # int 0x19 should never return.  In case it does anyway,
-        # invoke the BIOS reset code...
-        ljmp    $0xf000,$0xfff0
-
-
-bugger_off_msg:
-        .ascii  "Direct booting from floppy is no longer supported.\r\n"
-        .ascii  "Please use a boot loader program instead.\r\n"
-        .ascii  "\n"
-        .ascii  "Remove disk and press any key to reboot . . .\r\n"
-        .byte   0
-
-
-        # Kernel attributes; used by setup
-
-        .org 497
-setup_sects:    .byte SETUPSECTS
-root_flags:     .word ROOT_RDONLY
-syssize:        .word SYSSIZE
-swap_dev:       .word SWAP_DEV
-ram_size:       .word RAMDISK
-vid_mode:       .word SVGA_MODE
-root_dev:       .word ROOT_DEV
-boot_flag:      .word 0xAA55
diff --git a/arch/x86_64/boot/compressed/Makefile b/arch/x86_64/boot/compressed/Makefile
index 705a3e33d7e1..c9f2da7496c1 100644
--- a/arch/x86_64/boot/compressed/Makefile
+++ b/arch/x86_64/boot/compressed/Makefile
@@ -7,11 +7,12 @@
 #
 
 targets         := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o
-EXTRA_AFLAGS    := -traditional
 
-# cannot use EXTRA_CFLAGS because base CFLAGS contains -mkernel which conflicts with
-# -m32
-CFLAGS := -m64 -D__KERNEL__ -Iinclude -O2  -fno-strict-aliasing -fPIC -mcmodel=small -fno-builtin
+CFLAGS := -m64 -D__KERNEL__ $(LINUXINCLUDE) -O2  \
+          -fno-strict-aliasing -fPIC -mcmodel=small \
+           $(call cc-option, -ffreestanding) \
+           $(call cc-option, -fno-stack-protector)
+AFLAGS  := $(CFLAGS) -D__ASSEMBLY__
 LDFLAGS := -m elf_x86_64
 
 LDFLAGS_vmlinux := -T
diff --git a/arch/x86_64/boot/compressed/head.S b/arch/x86_64/boot/compressed/head.S
index f9d5692a0106..1312bfaff306 100644
--- a/arch/x86_64/boot/compressed/head.S
+++ b/arch/x86_64/boot/compressed/head.S
@@ -46,10 +46,10 @@ startup_32:
  * at and where we were actually loaded at.  This can only be done
  * with a short local call on x86.  Nothing  else will tell us what
  * address we are running at.  The reserved chunk of the real-mode
- * data at 0x34-0x3f are used as the stack for this calculation.
- * Only 4 bytes are needed.
+ * data at 0x1e4 (defined as a scratch field) are used as the stack
+ * for this calculation. Only 4 bytes are needed.
  */
-        leal    0x40(%esi), %esp
+        leal    (0x1e4+4)(%esi), %esp
         call    1f
 1:      popl    %ebp
         subl    $1b, %ebp
diff --git a/arch/x86_64/boot/install.sh b/arch/x86_64/boot/install.sh
deleted file mode 100644
index baaa2369bdb8..000000000000
--- a/arch/x86_64/boot/install.sh
+++ /dev/null
@@ -1,2 +0,0 @@
-#!/bin/sh
-. $srctree/arch/i386/boot/install.sh
diff --git a/arch/x86_64/boot/mtools.conf.in b/arch/x86_64/boot/mtools.conf.in
deleted file mode 100644
index efd6d2490c1d..000000000000
--- a/arch/x86_64/boot/mtools.conf.in
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# mtools configuration file for "make (b)zdisk"
-#
-
-# Actual floppy drive
-drive a:
-  file="/dev/fd0"
-
-# 1.44 MB floppy disk image
-drive v:
-  file="@OBJ@/fdimage" cylinders=80 heads=2 sectors=18 filter
-
-# 2.88 MB floppy disk image (mostly for virtual uses)
-drive w:
-  file="@OBJ@/fdimage" cylinders=80 heads=2 sectors=36 filter
-
-
diff --git a/arch/x86_64/boot/setup.S b/arch/x86_64/boot/setup.S
deleted file mode 100644
index e9e33f949697..000000000000
--- a/arch/x86_64/boot/setup.S
+++ /dev/null
@@ -1,826 +0,0 @@
-/*
- *      setup.S         Copyright (C) 1991, 1992 Linus Torvalds
- *
- * setup.s is responsible for getting the system data from the BIOS,
- * and putting them into the appropriate places in system memory.
- * both setup.s and system has been loaded by the bootblock.
- *
- * This code asks the bios for memory/disk/other parameters, and
- * puts them in a "safe" place: 0x90000-0x901FF, ie where the
- * boot-block used to be. It is then up to the protected mode
- * system to read them from there before the area is overwritten
- * for buffer-blocks.
- *
- * Move PS/2 aux init code to psaux.c
- * (troyer@saifr00.cfsat.Honeywell.COM) 03Oct92
- *
- * some changes and additional features by Christoph Niemann,
- * March 1993/June 1994 (Christoph.Niemann@linux.org)
- *
- * add APM BIOS checking by Stephen Rothwell, May 1994
- * (sfr@canb.auug.org.au)
- *
- * High load stuff, initrd support and position independency
- * by Hans Lermen & Werner Almesberger, February 1996
- * <lermen@elserv.ffm.fgan.de>, <almesber@lrc.epfl.ch>
- *
- * Video handling moved to video.S by Martin Mares, March 1996
- * <mj@k332.feld.cvut.cz>
- *
- * Extended memory detection scheme retwiddled by orc@pell.chi.il.us (david
- * parsons) to avoid loadlin confusion, July 1997
- *
- * Transcribed from Intel (as86) -> AT&T (gas) by Chris Noe, May 1999.
- * <stiker@northlink.com>
- *
- * Fix to work around buggy BIOSes which don't use carry bit correctly
- * and/or report extended memory in CX/DX for e801h memory size detection 
- * call.  As a result the kernel got wrong figures.  The int15/e801h docs
- * from Ralf Brown interrupt list seem to indicate AX/BX should be used
- * anyway.  So to avoid breaking many machines (presumably there was a reason
- * to orginally use CX/DX instead of AX/BX), we do a kludge to see
- * if CX/DX have been changed in the e801 call and if so use AX/BX .
- * Michael Miller, April 2001 <michaelm@mjmm.org>
- *
- * Added long mode checking and SSE force. March 2003, Andi Kleen.              
- */
-
-#include <asm/segment.h>
-#include <linux/utsrelease.h>
-#include <linux/compile.h>
-#include <asm/boot.h>
-#include <asm/e820.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-
-/* Signature words to ensure LILO loaded us right */
-#define SIG1    0xAA55
-#define SIG2    0x5A5A
-
-INITSEG  = DEF_INITSEG          # 0x9000, we move boot here, out of the way
-SYSSEG   = DEF_SYSSEG           # 0x1000, system loaded at 0x10000 (65536).
-SETUPSEG = DEF_SETUPSEG         # 0x9020, this is the current segment
-                                # ... and the former contents of CS
-
-DELTA_INITSEG = SETUPSEG - INITSEG      # 0x0020
-
-.code16
-.globl begtext, begdata, begbss, endtext, enddata, endbss
-
-.text
-begtext:
-.data
-begdata:
-.bss
-begbss:
-.text
-
-start:
-        jmp     trampoline
-
-# This is the setup header, and it must start at %cs:2 (old 0x9020:2)
-
-                .ascii  "HdrS"          # header signature
-                .word   0x0206          # header version number (>= 0x0105)
-                                        # or else old loadlin-1.5 will fail)
-realmode_swtch: .word   0, 0            # default_switch, SETUPSEG
-start_sys_seg:  .word   SYSSEG
-                .word   kernel_version  # pointing to kernel version string
-                                        # above section of header is compatible
-                                        # with loadlin-1.5 (header v1.5). Don't
-                                        # change it.
-
-type_of_loader: .byte   0               # = 0, old one (LILO, Loadlin,
-                                        #      Bootlin, SYSLX, bootsect...)
-                                        # See Documentation/i386/boot.txt for
-                                        # assigned ids
-        
-# flags, unused bits must be zero (RFU) bit within loadflags
-loadflags:
-LOADED_HIGH     = 1                     # If set, the kernel is loaded high
-CAN_USE_HEAP    = 0x80                  # If set, the loader also has set
-                                        # heap_end_ptr to tell how much
-                                        # space behind setup.S can be used for
-                                        # heap purposes.
-                                        # Only the loader knows what is free
-#ifndef __BIG_KERNEL__
-                .byte   0
-#else
-                .byte   LOADED_HIGH
-#endif
-
-setup_move_size: .word  0x8000          # size to move, when setup is not
-                                        # loaded at 0x90000. We will move setup 
-                                        # to 0x90000 then just before jumping
-                                        # into the kernel. However, only the
-                                        # loader knows how much data behind
-                                        # us also needs to be loaded.
-
-code32_start:                           # here loaders can put a different
-                                        # start address for 32-bit code.
-#ifndef __BIG_KERNEL__
-                .long   0x1000          #   0x1000 = default for zImage
-#else
-                .long   0x100000        # 0x100000 = default for big kernel
-#endif
-
-ramdisk_image:  .long   0               # address of loaded ramdisk image
-                                        # Here the loader puts the 32-bit
-                                        # address where it loaded the image.
-                                        # This only will be read by the kernel.
-
-ramdisk_size:   .long   0               # its size in bytes
-
-bootsect_kludge:
-                .long   0               # obsolete
-
-heap_end_ptr:   .word   modelist+1024   # (Header version 0x0201 or later)
-                                        # space from here (exclusive) down to
-                                        # end of setup code can be used by setup
-                                        # for local heap purposes.
-
-pad1:           .word   0
-cmd_line_ptr:   .long 0                 # (Header version 0x0202 or later)
-                                        # If nonzero, a 32-bit pointer
-                                        # to the kernel command line.
-                                        # The command line should be
-                                        # located between the start of
-                                        # setup and the end of low
-                                        # memory (0xa0000), or it may
-                                        # get overwritten before it
-                                        # gets read.  If this field is
-                                        # used, there is no longer
-                                        # anything magical about the
-                                        # 0x90000 segment; the setup
-                                        # can be located anywhere in
-                                        # low memory 0x10000 or higher.
-
-ramdisk_max:    .long 0xffffffff
-kernel_alignment:  .long 0x200000       # physical addr alignment required for
-                                        # protected mode relocatable kernel
-#ifdef CONFIG_RELOCATABLE
-relocatable_kernel:    .byte 1
-#else
-relocatable_kernel:    .byte 0
-#endif
-pad2:                  .byte 0
-pad3:                  .word 0
-
-cmdline_size:   .long   COMMAND_LINE_SIZE-1     #length of the command line,
-                                                #added with boot protocol
-                                                #version 2.06
-
-trampoline:     call    start_of_setup
-                .align 16
-                                        # The offset at this point is 0x240
-                .space  (0xeff-0x240+1) # E820 & EDD space (ending at 0xeff)
-# End of setup header #####################################################
-
-start_of_setup:
-# Bootlin depends on this being done early
-        movw    $0x01500, %ax
-        movb    $0x81, %dl
-        int     $0x13
-
-#ifdef SAFE_RESET_DISK_CONTROLLER
-# Reset the disk controller.
-        movw    $0x0000, %ax
-        movb    $0x80, %dl
-        int     $0x13
-#endif
-
-# Set %ds = %cs, we know that SETUPSEG = %cs at this point
-        movw    %cs, %ax                # aka SETUPSEG
-        movw    %ax, %ds
-# Check signature at end of setup
-        cmpw    $SIG1, setup_sig1
-        jne     bad_sig
-
-        cmpw    $SIG2, setup_sig2
-        jne     bad_sig
-
-        jmp     good_sig1
-
-# Routine to print asciiz string at ds:si
-prtstr:
-        lodsb
-        andb    %al, %al
-        jz      fin
-
-        call    prtchr
-        jmp     prtstr
-
-fin:    ret
-
-# Space printing
-prtsp2: call    prtspc          # Print double space
-prtspc: movb    $0x20, %al      # Print single space (note: fall-thru)
-
-prtchr: 
-        pushw   %ax
-        pushw   %cx
-        movw    $0007,%bx
-        movw    $0x01, %cx
-        movb    $0x0e, %ah
-        int     $0x10
-        popw    %cx
-        popw    %ax
-        ret
-
-beep:   movb    $0x07, %al
-        jmp     prtchr
-        
-no_sig_mess: .string    "No setup signature found ..."
-
-good_sig1:
-        jmp     good_sig
-
-# We now have to find the rest of the setup code/data
-bad_sig:
-        movw    %cs, %ax                        # SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # INITSEG
-        movw    %ax, %ds
-        xorb    %bh, %bh
-        movb    (497), %bl                      # get setup sect from bootsect
-        subw    $4, %bx                         # LILO loads 4 sectors of setup
-        shlw    $8, %bx                         # convert to words (1sect=2^8 words)
-        movw    %bx, %cx
-        shrw    $3, %bx                         # convert to segment
-        addw    $SYSSEG, %bx
-        movw    %bx, %cs:start_sys_seg
-# Move rest of setup code/data to here
-        movw    $2048, %di                      # four sectors loaded by LILO
-        subw    %si, %si
-        movw    %cs, %ax                        # aka SETUPSEG
-        movw    %ax, %es
-        movw    $SYSSEG, %ax
-        movw    %ax, %ds
-        rep
-        movsw
-        movw    %cs, %ax                        # aka SETUPSEG
-        movw    %ax, %ds
-        cmpw    $SIG1, setup_sig1
-        jne     no_sig
-
-        cmpw    $SIG2, setup_sig2
-        jne     no_sig
-
-        jmp     good_sig
-
-no_sig:
-        lea     no_sig_mess, %si
-        call    prtstr
-
-no_sig_loop:
-        jmp     no_sig_loop
-
-good_sig:
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %ds
-# Check if an old loader tries to load a big-kernel
-        testb   $LOADED_HIGH, %cs:loadflags     # Do we have a big kernel?
-        jz      loader_ok                       # No, no danger for old loaders.
-
-        cmpb    $0, %cs:type_of_loader          # Do we have a loader that
-                                                # can deal with us?
-        jnz     loader_ok                       # Yes, continue.
-
-        pushw   %cs                             # No, we have an old loader,
-        popw    %ds                             # die. 
-        lea     loader_panic_mess, %si
-        call    prtstr
-
-        jmp     no_sig_loop
-
-loader_panic_mess: .string "Wrong loader, giving up..."
-
-loader_ok:
-        /* check for long mode. */
-        /* we have to do this before the VESA setup, otherwise the user
-           can't see the error message. */
-        
-        pushw   %ds
-        movw    %cs,%ax
-        movw    %ax,%ds
-        
-        call verify_cpu
-        testl %eax,%eax
-        jz sse_ok
-
-no_longmode:
-        call    beep
-        lea     long_mode_panic,%si
-        call    prtstr
-no_longmode_loop:               
-        jmp     no_longmode_loop
-long_mode_panic:
-        .string "Your CPU does not support long mode. Use a 32bit distribution."
-        .byte 0
-
-#include "../kernel/verify_cpu.S"
-sse_ok:
-        popw    %ds
-        
-# tell BIOS we want to go to long mode
-        movl  $0xec00,%eax      # declare target operating mode
-        movl  $2,%ebx           # long mode
-        int $0x15                       
-        
-# Get memory size (extended mem, kB)
-
-        xorl    %eax, %eax
-        movl    %eax, (0x1e0)
-#ifndef STANDARD_MEMORY_BIOS_CALL
-        movb    %al, (E820NR)
-# Try three different memory detection schemes.  First, try
-# e820h, which lets us assemble a memory map, then try e801h,
-# which returns a 32-bit memory size, and finally 88h, which
-# returns 0-64m
-
-# method E820H:
-# the memory map from hell.  e820h returns memory classified into
-# a whole bunch of different types, and allows memory holes and
-# everything.  We scan through this memory map and build a list
-# of the first 32 memory areas, which we return at [E820MAP].
-# This is documented at http://www.acpi.info/, in the ACPI 2.0 specification.
-
-#define SMAP  0x534d4150
-
-meme820:
-        xorl    %ebx, %ebx                      # continuation counter
-        movw    $E820MAP, %di                   # point into the whitelist
-                                                # so we can have the bios
-                                                # directly write into it.
-
-jmpe820:
-        movl    $0x0000e820, %eax               # e820, upper word zeroed
-        movl    $SMAP, %edx                     # ascii 'SMAP'
-        movl    $20, %ecx                       # size of the e820rec
-        pushw   %ds                             # data record.
-        popw    %es
-        int     $0x15                           # make the call
-        jc      bail820                         # fall to e801 if it fails
-
-        cmpl    $SMAP, %eax                     # check the return is `SMAP'
-        jne     bail820                         # fall to e801 if it fails
-
-#       cmpl    $1, 16(%di)                     # is this usable memory?
-#       jne     again820
-
-        # If this is usable memory, we save it by simply advancing %di by
-        # sizeof(e820rec).
-        #
-good820:
-        movb    (E820NR), %al                   # up to 128 entries
-        cmpb    $E820MAX, %al
-        jae     bail820
-
-        incb    (E820NR)
-        movw    %di, %ax
-        addw    $20, %ax
-        movw    %ax, %di
-again820:
-        cmpl    $0, %ebx                        # check to see if
-        jne     jmpe820                         # %ebx is set to EOF
-bail820:
-
-
-# method E801H:
-# memory size is in 1k chunksizes, to avoid confusing loadlin.
-# we store the 0xe801 memory size in a completely different place,
-# because it will most likely be longer than 16 bits.
-# (use 1e0 because that's what Larry Augustine uses in his
-# alternative new memory detection scheme, and it's sensible
-# to write everything into the same place.)
-
-meme801:
-        stc                                     # fix to work around buggy
-        xorw    %cx,%cx                         # BIOSes which don't clear/set
-        xorw    %dx,%dx                         # carry on pass/error of
-                                                # e801h memory size call
-                                                # or merely pass cx,dx though
-                                                # without changing them.
-        movw    $0xe801, %ax
-        int     $0x15
-        jc      mem88
-
-        cmpw    $0x0, %cx                       # Kludge to handle BIOSes
-        jne     e801usecxdx                     # which report their extended
-        cmpw    $0x0, %dx                       # memory in AX/BX rather than
-        jne     e801usecxdx                     # CX/DX.  The spec I have read
-        movw    %ax, %cx                        # seems to indicate AX/BX 
-        movw    %bx, %dx                        # are more reasonable anyway...
-
-e801usecxdx:
-        andl    $0xffff, %edx                   # clear sign extend
-        shll    $6, %edx                        # and go from 64k to 1k chunks
-        movl    %edx, (0x1e0)                   # store extended memory size
-        andl    $0xffff, %ecx                   # clear sign extend
-        addl    %ecx, (0x1e0)                   # and add lower memory into
-                                                # total size.
-
-# Ye Olde Traditional Methode.  Returns the memory size (up to 16mb or
-# 64mb, depending on the bios) in ax.
-mem88:
-
-#endif
-        movb    $0x88, %ah
-        int     $0x15
-        movw    %ax, (2)
-
-# Set the keyboard repeat rate to the max
-        movw    $0x0305, %ax
-        xorw    %bx, %bx
-        int     $0x16
-
-# Check for video adapter and its parameters and allow the
-# user to browse video modes.
-        call    video                           # NOTE: we need %ds pointing
-                                                # to bootsector
-
-# Get hd0 data...
-        xorw    %ax, %ax
-        movw    %ax, %ds
-        ldsw    (4 * 0x41), %si
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        pushw   %ax
-        movw    %ax, %es
-        movw    $0x0080, %di
-        movw    $0x10, %cx
-        pushw   %cx
-        cld
-        rep
-        movsb
-# Get hd1 data...
-        xorw    %ax, %ax
-        movw    %ax, %ds
-        ldsw    (4 * 0x46), %si
-        popw    %cx
-        popw    %es
-        movw    $0x0090, %di
-        rep
-        movsb
-# Check that there IS a hd1 :-)
-        movw    $0x01500, %ax
-        movb    $0x81, %dl
-        int     $0x13
-        jc      no_disk1
-        
-        cmpb    $3, %ah
-        je      is_disk1
-
-no_disk1:
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %es
-        movw    $0x0090, %di
-        movw    $0x10, %cx
-        xorw    %ax, %ax
-        cld
-        rep
-        stosb
-is_disk1:
-
-# Check for PS/2 pointing device
-        movw    %cs, %ax                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ax, %ds
-        movb    $0, (0x1ff)                     # default is no pointing device
-        int     $0x11                           # int 0x11: equipment list
-        testb   $0x04, %al                      # check if mouse installed
-        jz      no_psmouse
-
-        movb    $0xAA, (0x1ff)                  # device present
-no_psmouse:
-
-#include "../../i386/boot/edd.S"
-
-# Now we want to move to protected mode ...
-        cmpw    $0, %cs:realmode_swtch
-        jz      rmodeswtch_normal
-
-        lcall   *%cs:realmode_swtch
-
-        jmp     rmodeswtch_end
-
-rmodeswtch_normal:
-        pushw   %cs
-        call    default_switch
-
-rmodeswtch_end:
-# we get the code32 start address and modify the below 'jmpi'
-# (loader may have changed it)
-        movl    %cs:code32_start, %eax
-        movl    %eax, %cs:code32
-
-# Now we move the system to its rightful place ... but we check if we have a
-# big-kernel. In that case we *must* not move it ...
-        testb   $LOADED_HIGH, %cs:loadflags
-        jz      do_move0                        # .. then we have a normal low
-                                                # loaded zImage
-                                                # .. or else we have a high
-                                                # loaded bzImage
-        jmp     end_move                        # ... and we skip moving
-
-do_move0:
-        movw    $0x100, %ax                     # start of destination segment
-        movw    %cs, %bp                        # aka SETUPSEG
-        subw    $DELTA_INITSEG, %bp             # aka INITSEG
-        movw    %cs:start_sys_seg, %bx          # start of source segment
-        cld
-do_move:
-        movw    %ax, %es                        # destination segment
-        incb    %ah                             # instead of add ax,#0x100
-        movw    %bx, %ds                        # source segment
-        addw    $0x100, %bx
-        subw    %di, %di
-        subw    %si, %si
-        movw    $0x800, %cx
-        rep
-        movsw
-        cmpw    %bp, %bx                        # assume start_sys_seg > 0x200,
-                                                # so we will perhaps read one
-                                                # page more than needed, but
-                                                # never overwrite INITSEG
-                                                # because destination is a
-                                                # minimum one page below source
-        jb      do_move
-
-end_move:
-# then we load the segment descriptors
-        movw    %cs, %ax                        # aka SETUPSEG
-        movw    %ax, %ds
-                
-# Check whether we need to be downward compatible with version <=201
-        cmpl    $0, cmd_line_ptr
-        jne     end_move_self           # loader uses version >=202 features
-        cmpb    $0x20, type_of_loader
-        je      end_move_self           # bootsect loader, we know of it
-
-# Boot loader doesnt support boot protocol version 2.02.
-# If we have our code not at 0x90000, we need to move it there now.
-# We also then need to move the params behind it (commandline)
-# Because we would overwrite the code on the current IP, we move
-# it in two steps, jumping high after the first one.
-        movw    %cs, %ax
-        cmpw    $SETUPSEG, %ax
-        je      end_move_self
-
-        cli                                     # make sure we really have
-                                                # interrupts disabled !
-                                                # because after this the stack
-                                                # should not be used
-        subw    $DELTA_INITSEG, %ax             # aka INITSEG
-        movw    %ss, %dx
-        cmpw    %ax, %dx
-        jb      move_self_1
-
-        addw    $INITSEG, %dx
-        subw    %ax, %dx                        # this will go into %ss after
-                                                # the move
-move_self_1:
-        movw    %ax, %ds
-        movw    $INITSEG, %ax                   # real INITSEG
-        movw    %ax, %es
-        movw    %cs:setup_move_size, %cx
-        std                                     # we have to move up, so we use
-                                                # direction down because the
-                                                # areas may overlap
-        movw    %cx, %di
-        decw    %di
-        movw    %di, %si
-        subw    $move_self_here+0x200, %cx
-        rep
-        movsb
-        ljmp    $SETUPSEG, $move_self_here
-
-move_self_here:
-        movw    $move_self_here+0x200, %cx
-        rep
-        movsb
-        movw    $SETUPSEG, %ax
-        movw    %ax, %ds
-        movw    %dx, %ss
-end_move_self:                                  # now we are at the right place
-        lidt    idt_48                          # load idt with 0,0
-        xorl    %eax, %eax                      # Compute gdt_base
-        movw    %ds, %ax                        # (Convert %ds:gdt to a linear ptr)
-        shll    $4, %eax
-        addl    $gdt, %eax
-        movl    %eax, (gdt_48+2)
-        lgdt    gdt_48                          # load gdt with whatever is
-                                                # appropriate
-
-# that was painless, now we enable a20
-        call    empty_8042
-
-        movb    $0xD1, %al                      # command write
-        outb    %al, $0x64
-        call    empty_8042
-
-        movb    $0xDF, %al                      # A20 on
-        outb    %al, $0x60
-        call    empty_8042
-
-#
-#       You must preserve the other bits here. Otherwise embarrasing things
-#       like laptops powering off on boot happen. Corrected version by Kira
-#       Brown from Linux 2.2
-#
-        inb     $0x92, %al                      # 
-        orb     $02, %al                        # "fast A20" version
-        outb    %al, $0x92                      # some chips have only this
-
-# wait until a20 really *is* enabled; it can take a fair amount of
-# time on certain systems; Toshiba Tecras are known to have this
-# problem.  The memory location used here (0x200) is the int 0x80
-# vector, which should be safe to use.
-
-        xorw    %ax, %ax                        # segment 0x0000
-        movw    %ax, %fs
-        decw    %ax                             # segment 0xffff (HMA)
-        movw    %ax, %gs
-a20_wait:
-        incw    %ax                             # unused memory location <0xfff0
-        movw    %ax, %fs:(0x200)                # we use the "int 0x80" vector
-        cmpw    %gs:(0x210), %ax                # and its corresponding HMA addr
-        je      a20_wait                        # loop until no longer aliased
-
-# make sure any possible coprocessor is properly reset..
-        xorw    %ax, %ax
-        outb    %al, $0xf0
-        call    delay
-
-        outb    %al, $0xf1
-        call    delay
-
-# well, that went ok, I hope. Now we mask all interrupts - the rest
-# is done in init_IRQ().
-        movb    $0xFF, %al                      # mask all interrupts for now
-        outb    %al, $0xA1
-        call    delay
-        
-        movb    $0xFB, %al                      # mask all irq's but irq2 which
-        outb    %al, $0x21                      # is cascaded
-
-# Well, that certainly wasn't fun :-(. Hopefully it works, and we don't
-# need no steenking BIOS anyway (except for the initial loading :-).
-# The BIOS-routine wants lots of unnecessary data, and it's less
-# "interesting" anyway. This is how REAL programmers do it.
-#
-# Well, now's the time to actually move into protected mode. To make
-# things as simple as possible, we do no register set-up or anything,
-# we let the gnu-compiled 32-bit programs do that. We just jump to
-# absolute address 0x1000 (or the loader supplied one),
-# in 32-bit protected mode.
-#
-# Note that the short jump isn't strictly needed, although there are
-# reasons why it might be a good idea. It won't hurt in any case.
-        movw    $1, %ax                         # protected mode (PE) bit
-        lmsw    %ax                             # This is it!
-        jmp     flush_instr
-
-flush_instr:
-        xorw    %bx, %bx                        # Flag to indicate a boot
-        xorl    %esi, %esi                      # Pointer to real-mode code
-        movw    %cs, %si
-        subw    $DELTA_INITSEG, %si
-        shll    $4, %esi                        # Convert to 32-bit pointer
-# NOTE: For high loaded big kernels we need a
-#       jmpi    0x100000,__KERNEL_CS
-#
-#       but we yet haven't reloaded the CS register, so the default size 
-#       of the target offset still is 16 bit.
-#       However, using an operand prefix (0x66), the CPU will properly
-#       take our 48 bit far pointer. (INTeL 80386 Programmer's Reference
-#       Manual, Mixing 16-bit and 32-bit code, page 16-6)
-
-        .byte 0x66, 0xea                        # prefix + jmpi-opcode
-code32: .long   0x1000                          # will be set to 0x100000
-                                                # for big kernels
-        .word   __KERNEL_CS
-
-# Here's a bunch of information about your current kernel..
-kernel_version: .ascii  UTS_RELEASE
-                .ascii  " ("
-                .ascii  LINUX_COMPILE_BY
-                .ascii  "@"
-                .ascii  LINUX_COMPILE_HOST
-                .ascii  ") "
-                .ascii  UTS_VERSION
-                .byte   0
-
-# This is the default real mode switch routine.
-# to be called just before protected mode transition
-default_switch:
-        cli                                     # no interrupts allowed !
-        movb    $0x80, %al                      # disable NMI for bootup
-                                                # sequence
-        outb    %al, $0x70
-        lret
-
-
-# This routine checks that the keyboard command queue is empty
-# (after emptying the output buffers)
-#
-# Some machines have delusions that the keyboard buffer is always full
-# with no keyboard attached...
-#
-# If there is no keyboard controller, we will usually get 0xff
-# to all the reads.  With each IO taking a microsecond and
-# a timeout of 100,000 iterations, this can take about half a
-# second ("delay" == outb to port 0x80). That should be ok,
-# and should also be plenty of time for a real keyboard controller
-# to empty.
-#
-
-empty_8042:
-        pushl   %ecx
-        movl    $100000, %ecx
-
-empty_8042_loop:
-        decl    %ecx
-        jz      empty_8042_end_loop
-
-        call    delay
-
-        inb     $0x64, %al                      # 8042 status port
-        testb   $1, %al                         # output buffer?
-        jz      no_output
-
-        call    delay
-        inb     $0x60, %al                      # read it
-        jmp     empty_8042_loop
-
-no_output:
-        testb   $2, %al                         # is input buffer full?
-        jnz     empty_8042_loop                 # yes - loop
-empty_8042_end_loop:
-        popl    %ecx
-        ret
-
-# Read the cmos clock. Return the seconds in al
-gettime:
-        pushw   %cx
-        movb    $0x02, %ah
-        int     $0x1a
-        movb    %dh, %al                        # %dh contains the seconds
-        andb    $0x0f, %al
-        movb    %dh, %ah
-        movb    $0x04, %cl
-        shrb    %cl, %ah
-        aad
-        popw    %cx
-        ret
-
-# Delay is needed after doing I/O
-delay:
-        outb    %al,$0x80
-        ret
-
-# Descriptor tables
-gdt:
-        .word   0, 0, 0, 0                      # dummy
-
-        .word   0, 0, 0, 0                      # unused
-
-        .word   0xFFFF                          # 4Gb - (0x100000*0x1000 = 4Gb)
-        .word   0                               # base address = 0
-        .word   0x9A00                          # code read/exec
-        .word   0x00CF                          # granularity = 4096, 386
-                                                #  (+5th nibble of limit)
-
-        .word   0xFFFF                          # 4Gb - (0x100000*0x1000 = 4Gb)
-        .word   0                               # base address = 0
-        .word   0x9200                          # data read/write
-        .word   0x00CF                          # granularity = 4096, 386
-                                                #  (+5th nibble of limit)
-gdt_end:
-idt_48:
-        .word   0                               # idt limit = 0
-        .word   0, 0                            # idt base = 0L
-gdt_48:
-        .word   gdt_end-gdt-1                   # gdt limit
-        .word   0, 0                            # gdt base (filled in later)
-
-# Include video setup & detection code
-
-#include "../../i386/boot/video.S"
-
-# Setup signature -- must be last
-setup_sig1:     .word   SIG1
-setup_sig2:     .word   SIG2
-
-# After this point, there is some free space which is used by the video mode
-# handling code to store the temporary mode table (not used by the kernel).
-
-modelist:
-
-.text
-endtext:
-.data
-enddata:
-.bss
-endbss:
diff --git a/arch/x86_64/boot/tools/build.c b/arch/x86_64/boot/tools/build.c
deleted file mode 100644
index eae86691709a..000000000000
--- a/arch/x86_64/boot/tools/build.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- *  Copyright (C) 1991, 1992  Linus Torvalds
- *  Copyright (C) 1997 Martin Mares
- */
-
-/*
- * This file builds a disk-image from three different files:
- *
- * - bootsect: compatibility mbr which prints an error message if
- *             someone tries to boot the kernel directly.
- * - setup: 8086 machine code, sets up system parm
- * - system: 80386 code for actual system
- *
- * It does some checking that all files are of the correct type, and
- * just writes the result to stdout, removing headers and padding to
- * the right amount. It also writes some system data to stderr.
- */
-
-/*
- * Changes by tytso to allow root device specification
- * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
- * Cross compiling fixes by Gertjan van Wingerde, July 1996
- * Rewritten by Martin Mares, April 1997
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/sysmacros.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <asm/boot.h>
-
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long u32;
-
-#define DEFAULT_MAJOR_ROOT 0
-#define DEFAULT_MINOR_ROOT 0
-
-/* Minimal number of setup sectors (see also bootsect.S) */
-#define SETUP_SECTS 4
-
-byte buf[1024];
-int fd;
-int is_big_kernel;
-
-void die(const char * str, ...)
-{
-        va_list args;
-        va_start(args, str);
-        vfprintf(stderr, str, args);
-        fputc('\n', stderr);
-        exit(1);
-}
-
-void file_open(const char *name)
-{
-        if ((fd = open(name, O_RDONLY, 0)) < 0)
-                die("Unable to open `%s': %m", name);
-}
-
-void usage(void)
-{
-        die("Usage: build [-b] bootsect setup system [rootdev] [> image]");
-}
-
-int main(int argc, char ** argv)
-{
-        unsigned int i, c, sz, setup_sectors;
-        u32 sys_size;
-        byte major_root, minor_root;
-        struct stat sb;
-
-        if (argc > 2 && !strcmp(argv[1], "-b"))
-          {
-            is_big_kernel = 1;
-            argc--, argv++;
-          }
-        if ((argc < 4) || (argc > 5))
-                usage();
-        if (argc > 4) {
-                if (!strcmp(argv[4], "CURRENT")) {
-                        if (stat("/", &sb)) {
-                                perror("/");
-                                die("Couldn't stat /");
-                        }
-                        major_root = major(sb.st_dev);
-                        minor_root = minor(sb.st_dev);
-                } else if (strcmp(argv[4], "FLOPPY")) {
-                        if (stat(argv[4], &sb)) {
-                                perror(argv[4]);
-                                die("Couldn't stat root device.");
-                        }
-                        major_root = major(sb.st_rdev);
-                        minor_root = minor(sb.st_rdev);
-                } else {
-                        major_root = 0;
-                        minor_root = 0;
-                }
-        } else {
-                major_root = DEFAULT_MAJOR_ROOT;
-                minor_root = DEFAULT_MINOR_ROOT;
-        }
-        fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
-
-        file_open(argv[1]);
-        i = read(fd, buf, sizeof(buf));
-        fprintf(stderr,"Boot sector %d bytes.\n",i);
-        if (i != 512)
-                die("Boot block must be exactly 512 bytes");
-        if (buf[510] != 0x55 || buf[511] != 0xaa)
-                die("Boot block hasn't got boot flag (0xAA55)");
-        buf[508] = minor_root;
-        buf[509] = major_root;
-        if (write(1, buf, 512) != 512)
-                die("Write call failed");
-        close (fd);
-
-        file_open(argv[2]);                                 /* Copy the setup code */
-        for (i=0 ; (c=read(fd, buf, sizeof(buf)))>0 ; i+=c )
-                if (write(1, buf, c) != c)
-                        die("Write call failed");
-        if (c != 0)
-                die("read-error on `setup'");
-        close (fd);
-
-        setup_sectors = (i + 511) / 512;        /* Pad unused space with zeros */
-        /* for compatibility with ancient versions of LILO. */
-        if (setup_sectors < SETUP_SECTS)
-                setup_sectors = SETUP_SECTS;
-        fprintf(stderr, "Setup is %d bytes.\n", i);
-        memset(buf, 0, sizeof(buf));
-        while (i < setup_sectors * 512) {
-                c = setup_sectors * 512 - i;
-                if (c > sizeof(buf))
-                        c = sizeof(buf);
-                if (write(1, buf, c) != c)
-                        die("Write call failed");
-                i += c;
-        }
-
-        file_open(argv[3]);
-        if (fstat (fd, &sb))
-                die("Unable to stat `%s': %m", argv[3]);
-        sz = sb.st_size;
-        fprintf (stderr, "System is %d kB\n", sz/1024);
-        sys_size = (sz + 15) / 16;
-        if (!is_big_kernel && sys_size > DEF_SYSSIZE)
-                die("System is too big. Try using bzImage or modules.");
-        while (sz > 0) {
-                int l, n;
-
-                l = (sz > sizeof(buf)) ? sizeof(buf) : sz;
-                if ((n=read(fd, buf, l)) != l) {
-                        if (n < 0)
-                                die("Error reading %s: %m", argv[3]);
-                        else
-                                die("%s: Unexpected EOF", argv[3]);
-                }
-                if (write(1, buf, l) != l)
-                        die("Write failed");
-                sz -= l;
-        }
-        close(fd);
-
-        if (lseek(1, 497, SEEK_SET) != 497)                 /* Write sizes to the bootsector */
-                die("Output: seek failed");
-        buf[0] = setup_sectors;
-        if (write(1, buf, 1) != 1)
-                die("Write of setup sector count failed");
-        if (lseek(1, 500, SEEK_SET) != 500)
-                die("Output: seek failed");
-        buf[0] = (sys_size & 0xff);
-        buf[1] = ((sys_size >> 8) & 0xff);
-        buf[2] = ((sys_size >> 16) & 0xff);
-        buf[3] = ((sys_size >> 24) & 0xff);
-        if (write(1, buf, 4) != 4)
-                die("Write of image length failed");
-
-        return 0;                                           /* Everything is OK */
-}
diff --git a/arch/x86_64/kernel/Makefile b/arch/x86_64/kernel/Makefile
index de1de8a2fd84..47f1dc30bf56 100644
--- a/arch/x86_64/kernel/Makefile
+++ b/arch/x86_64/kernel/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_PCI)		+= early-quirks.o
 
 obj-y                           += topology.o
 obj-y                           += intel_cacheinfo.o
+obj-y                           += addon_cpuid_features.o
 obj-y                           += pcspeaker.o
 
 CFLAGS_vsyscall.o               := $(PROFILING) -g0
@@ -55,6 +56,7 @@ cpuid-$(subst m,y,$(CONFIG_X86_CPUID))  += ../../i386/kernel/cpuid.o
 topology-y                     += ../../i386/kernel/topology.o
 microcode-$(subst m,y,$(CONFIG_MICROCODE))  += ../../i386/kernel/microcode.o
 intel_cacheinfo-y               += ../../i386/kernel/cpu/intel_cacheinfo.o
+addon_cpuid_features-y          += ../../i386/kernel/cpu/addon_cpuid_features.o
 quirks-y                        += ../../i386/kernel/quirks.o
 i8237-y                         += ../../i386/kernel/i8237.o
 msr-$(subst m,y,$(CONFIG_X86_MSR))  += ../../i386/kernel/msr.o
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index eb6524f3ac29..33ef718f8cb5 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -846,6 +846,8 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                         c->x86_capability[2] = cpuid_edx(0x80860001);
         }
 
+        init_scattered_cpuid_features(c);
+
         c->apicid = phys_pkg_id(0);
 
         /*
@@ -931,7 +933,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
                 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
                 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
-                "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
+                "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
 
                 /* AMD-defined */
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -947,10 +949,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
                 /* Other (Linux-defined) */
-                "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
-                "constant_tsc", NULL, NULL,
-                "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
+                NULL, NULL, NULL, NULL,
+                "constant_tsc", "up", NULL, "arch_perfmon",
+                "pebs", "bts", NULL, "sync_rdtsc",
+                "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
                 /* Intel-defined (#2) */
@@ -961,7 +964,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 
                 /* VIA/Cyrix/Centaur-defined */
                 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
-                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
@@ -972,6 +975,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 "osvw", "ibs", NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+
+                /* Auxiliary (Linux-defined) */
+                "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
         };
         static char *x86_power_flags[] = { 
                 "ts",   /* temperature sensor */
diff --git a/arch/x86_64/kernel/verify_cpu.S b/arch/x86_64/kernel/verify_cpu.S
index e035f5948199..45b6f8a975a1 100644
--- a/arch/x86_64/kernel/verify_cpu.S
+++ b/arch/x86_64/kernel/verify_cpu.S
@@ -37,20 +37,6 @@ verify_cpu:
         pushl   $0                      # Kill any dangerous flags
         popfl
 
-        /* minimum CPUID flags for x86-64 as defined by AMD */
-#define M(x) (1<<(x))
-#define M2(a,b) M(a)|M(b)
-#define M4(a,b,c,d) M(a)|M(b)|M(c)|M(d)
-
-#define SSE_MASK \
-        (M2(X86_FEATURE_XMM,X86_FEATURE_XMM2))
-#define REQUIRED_MASK1 \
-        (M4(X86_FEATURE_FPU,X86_FEATURE_PSE,X86_FEATURE_TSC,X86_FEATURE_MSR)|\
-         M4(X86_FEATURE_PAE,X86_FEATURE_CX8,X86_FEATURE_PGE,X86_FEATURE_CMOV)|\
-         M(X86_FEATURE_FXSR))
-#define REQUIRED_MASK2 \
-        (M(X86_FEATURE_LM - 32))
-
         pushfl                          # standard way to check for cpuid
         popl    %eax
         movl    %eax,%ebx
@@ -79,8 +65,8 @@ verify_cpu:
 verify_cpu_noamd:
         movl    $0x1,%eax               # Does the cpu have what it takes
         cpuid
-        andl    $REQUIRED_MASK1,%edx
-        xorl    $REQUIRED_MASK1,%edx
+        andl    $REQUIRED_MASK0,%edx
+        xorl    $REQUIRED_MASK0,%edx
         jnz     verify_cpu_no_longmode
 
         movl    $0x80000000,%eax        # See if extended cpuid is implemented
@@ -90,8 +76,8 @@ verify_cpu_noamd:
 
         movl    $0x80000001,%eax        # Does the cpu have what it takes
         cpuid
-        andl    $REQUIRED_MASK2,%edx
-        xorl    $REQUIRED_MASK2,%edx
+        andl    $REQUIRED_MASK1,%edx
+        xorl    $REQUIRED_MASK1,%edx
         jnz     verify_cpu_no_longmode
 
 verify_cpu_sse_test:
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index ef683ebd367c..a31c6d2c061f 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -815,7 +815,7 @@ config SGI_IP27_RTC
 
 config GEN_RTC
         tristate "Generic /dev/rtc emulation"
-        depends on RTC!=y && !IA64 && !ARM && !M32R && !SPARC && !FRV && !S390 && !SUPERH
+        depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH
         ---help---
           If you say Y here and create a character special file /dev/rtc with
           major number 10 and minor number 135 using mknod ("man mknod"), you
diff --git a/drivers/char/vr41xx_giu.c b/drivers/char/vr41xx_giu.c
index 0cea8d4907df..e5ed09192be8 100644
--- a/drivers/char/vr41xx_giu.c
+++ b/drivers/char/vr41xx_giu.c
@@ -19,18 +19,17 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <linux/platform_device.h>
 #include <linux/errno.h>
 #include <linux/fs.h>
 #include <linux/init.h>
-#include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
-#include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/vr41xx/giu.h>
 #include <asm/vr41xx/irq.h>
@@ -44,18 +43,6 @@ static int major;	/* default is dynamic major device number */
 module_param(major, int, 0);
 MODULE_PARM_DESC(major, "Major device number");
 
-#define GIU_TYPE1_START         0x0b000100UL
-#define GIU_TYPE1_SIZE          0x20UL
-
-#define GIU_TYPE2_START         0x0f000140UL
-#define GIU_TYPE2_SIZE          0x20UL
-
-#define GIU_TYPE3_START         0x0f000140UL
-#define GIU_TYPE3_SIZE          0x28UL
-
-#define GIU_PULLUPDOWN_START    0x0b0002e0UL
-#define GIU_PULLUPDOWN_SIZE     0x04UL
-
 #define GIUIOSELL       0x00
 #define GIUIOSELH       0x02
 #define GIUPIODL        0x04
@@ -89,8 +76,6 @@ MODULE_PARM_DESC(major, "Major device number");
 #define GPIO_HAS_INTERRUPT_EDGE_SELECT  0x0100
 
 static spinlock_t giu_lock;
-static struct resource *giu_resource1;
-static struct resource *giu_resource2;
 static unsigned long giu_flags;
 static unsigned int giu_nr_pins;
 
@@ -234,7 +219,7 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
                                 giu_set(GIUINTHTSELL, mask);
                         else
                                 giu_clear(GIUINTHTSELL, mask);
-                        if (current_cpu_data.cputype == CPU_VR4133) {
+                        if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
                                 switch (trigger) {
                                 case IRQ_TRIGGER_EDGE_FALLING:
                                         giu_set(GIUFEDGEINHL, mask);
@@ -269,7 +254,7 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
                                 giu_set(GIUINTHTSELH, mask);
                         else
                                 giu_clear(GIUINTHTSELH, mask);
-                        if (current_cpu_data.cputype == CPU_VR4133) {
+                        if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
                                 switch (trigger) {
                                 case IRQ_TRIGGER_EDGE_FALLING:
                                         giu_set(GIUFEDGEINHH, mask);
@@ -298,7 +283,6 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
                 giu_write(GIUINTSTATH, mask);
         }
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
 
 void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
@@ -321,7 +305,6 @@ void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
                 giu_write(GIUINTSTATH, mask);
         }
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
 
 gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
@@ -350,7 +333,6 @@ gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
 
         return GPIO_DATA_LOW;
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);
 
 int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
@@ -388,7 +370,6 @@ int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
 
         return 0;
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);
 
 int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
@@ -438,7 +419,6 @@ int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
 
         return 0;
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);
 
 int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
@@ -477,7 +457,6 @@ int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
 
         return 0;
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
 
 static ssize_t gpio_read(struct file *file, char __user *buf, size_t len,
@@ -596,61 +575,40 @@ static const struct file_operations gpio_fops = {
 
 static int __devinit giu_probe(struct platform_device *dev)
 {
-        unsigned long start, size, flags = 0;
-        unsigned int nr_pins = 0, trigger, i, pin;
-        struct resource *res1, *res2 = NULL;
-        void *base;
+        struct resource *res;
+        unsigned int trigger, i, pin;
         struct irq_chip *chip;
-        int retval;
-
-        switch (current_cpu_data.cputype) {
-        case CPU_VR4111:
-        case CPU_VR4121:
-                start = GIU_TYPE1_START;
-                size = GIU_TYPE1_SIZE;
-                flags = GPIO_HAS_PULLUPDOWN_IO;
-                nr_pins = 50;
+        int irq, retval;
+
+        switch (dev->id) {
+        case GPIO_50PINS_PULLUPDOWN:
+                giu_flags = GPIO_HAS_PULLUPDOWN_IO;
+                giu_nr_pins = 50;
                 break;
-        case CPU_VR4122:
-        case CPU_VR4131:
-                start = GIU_TYPE2_START;
-                size = GIU_TYPE2_SIZE;
-                nr_pins = 36;
+        case GPIO_36PINS:
+                giu_nr_pins = 36;
                 break;
-        case CPU_VR4133:
-                start = GIU_TYPE3_START;
-                size = GIU_TYPE3_SIZE;
-                flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
-                nr_pins = 48;
+        case GPIO_48PINS_EDGE_SELECT:
+                giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
+                giu_nr_pins = 48;
                 break;
         default:
+                printk(KERN_ERR "GIU: unknown ID %d\n", dev->id);
                 return -ENODEV;
         }
 
-        res1 = request_mem_region(start, size, "GIU");
-        if (res1 == NULL)
+        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+        if (!res)
                 return -EBUSY;
 
-        base = ioremap(start, size);
-        if (base == NULL) {
-                release_resource(res1);
+        giu_base = ioremap(res->start, res->end - res->start + 1);
+        if (!giu_base)
                 return -ENOMEM;
-        }
-
-        if (flags & GPIO_HAS_PULLUPDOWN_IO) {
-                res2 = request_mem_region(GIU_PULLUPDOWN_START, GIU_PULLUPDOWN_SIZE, "GIU");
-                if (res2 == NULL) {
-                        iounmap(base);
-                        release_resource(res1);
-                        return -EBUSY;
-                }
-        }
 
         retval = register_chrdev(major, "GIU", &gpio_fops);
         if (retval < 0) {
-                iounmap(base);
-                release_resource(res1);
-                release_resource(res2);
+                iounmap(giu_base);
+                giu_base = NULL;
                 return retval;
         }
 
@@ -660,11 +618,6 @@ static int __devinit giu_probe(struct platform_device *dev)
         }
 
         spin_lock_init(&giu_lock);
-        giu_base = base;
-        giu_resource1 = res1;
-        giu_resource2 = res2;
-        giu_flags = flags;
-        giu_nr_pins = nr_pins;
 
         giu_write(GIUINTENL, 0);
         giu_write(GIUINTENH, 0);
@@ -685,22 +638,23 @@ static int __devinit giu_probe(struct platform_device *dev)
 
         }
 
-        return cascade_irq(GIUINT_IRQ, giu_get_irq);
+        irq = platform_get_irq(dev, 0);
+        if (irq < 0 || irq >= NR_IRQS)
+                return -EBUSY;
+
+        return cascade_irq(irq, giu_get_irq);
 }
 
 static int __devexit giu_remove(struct platform_device *dev)
 {
-        iounmap(giu_base);
-
-        release_resource(giu_resource1);
-        if (giu_flags & GPIO_HAS_PULLUPDOWN_IO)
-                release_resource(giu_resource2);
+        if (giu_base) {
+                iounmap(giu_base);
+                giu_base = NULL;
+        }
 
         return 0;
 }
 
-static struct platform_device *giu_platform_device;
-
 static struct platform_driver giu_device_driver = {
         .probe          = giu_probe,
         .remove         = __devexit_p(giu_remove),
@@ -712,30 +666,12 @@ static struct platform_driver giu_device_driver = {
 
 static int __init vr41xx_giu_init(void)
 {
-        int retval;
-
-        giu_platform_device = platform_device_alloc("GIU", -1);
-        if (!giu_platform_device)
-                return -ENOMEM;
-
-        retval = platform_device_add(giu_platform_device);
-        if (retval < 0) {
-                platform_device_put(giu_platform_device);
-                return retval;
-        }
-
-        retval = platform_driver_register(&giu_device_driver);
-        if (retval < 0)
-                platform_device_unregister(giu_platform_device);
-
-        return retval;
+        return platform_driver_register(&giu_device_driver);
 }
 
 static void __exit vr41xx_giu_exit(void)
 {
         platform_driver_unregister(&giu_device_driver);
-
-        platform_device_unregister(giu_platform_device);
 }
 
 module_init(vr41xx_giu_init);
diff --git a/drivers/i2c/algos/Kconfig b/drivers/i2c/algos/Kconfig
index 58899078810b..014dfa575be7 100644
--- a/drivers/i2c/algos/Kconfig
+++ b/drivers/i2c/algos/Kconfig
@@ -34,10 +34,6 @@ config I2C_ALGOPCA
           This support is also available as a module.  If so, the module 
           will be called i2c-algo-pca.
 
-config I2C_ALGO8XX
-        tristate "MPC8xx CPM I2C interface"
-        depends on 8xx
-
 config I2C_ALGO_SGI
         tristate "I2C SGI interfaces"
         depends on SGI_IP22 || SGI_IP32 || X86_VISWS
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 838dc1c19d61..fcde9bab5b96 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -207,6 +207,7 @@ config I2C_PIIX4
             ATI IXP300
             ATI IXP400
             ATI SB600
+            ATI SB700
             Serverworks OSB4
             Serverworks CSB5
             Serverworks CSB6
@@ -390,11 +391,6 @@ config I2C_PROSAVAGE
           This support is also available as a module.  If so, the module 
           will be called i2c-prosavage.
 
-config I2C_RPXLITE
-        tristate "Embedded Planet RPX Lite/Classic support"
-        depends on RPXLITE || RPXCLASSIC
-        select I2C_ALGO8XX
-
 config I2C_S3C2410
         tristate "S3C2410 I2C Driver"
         depends on ARCH_S3C2410
@@ -512,6 +508,22 @@ config I2C_SIS96X
           This driver can also be built as a module.  If so, the module
           will be called i2c-sis96x.
 
+config I2C_TAOS_EVM
+        tristate "TAOS evaluation module"
+        depends on EXPERIMENTAL
+        select SERIO
+        select SERIO_SERPORT
+        default n
+        help
+          This supports TAOS evaluation modules on serial port. In order to
+          use this driver, you will need the inputattach tool, which is part
+          of the input-utils package.
+
+          If unsure, say N.
+
+          This support is also available as a module.  If so, the module
+          will be called i2c-taos-evm.
+
 config I2C_STUB
         tristate "I2C/SMBus Test Stub"
         depends on EXPERIMENTAL && m
@@ -635,4 +647,13 @@ config I2C_PNX
           This driver can also be built as a module.  If so, the module
           will be called i2c-pnx.
 
+config I2C_PMCMSP
+        tristate "PMC MSP I2C TWI Controller"
+        depends on PMC_MSP
+        help
+          This driver supports the PMC TWI controller on MSP devices.
+
+          This driver can also be built as module. If so, the module
+          will be called i2c-pmcmsp.
+
 endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 14d1432f698b..a6db4e38bda8 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -32,10 +32,10 @@ obj-$(CONFIG_I2C_PARPORT_LIGHT)	+= i2c-parport-light.o
 obj-$(CONFIG_I2C_PASEMI)        += i2c-pasemi.o
 obj-$(CONFIG_I2C_PCA_ISA)       += i2c-pca-isa.o
 obj-$(CONFIG_I2C_PIIX4)         += i2c-piix4.o
+obj-$(CONFIG_I2C_PMCMSP)        += i2c-pmcmsp.o
 obj-$(CONFIG_I2C_PNX)           += i2c-pnx.o
 obj-$(CONFIG_I2C_PROSAVAGE)     += i2c-prosavage.o
 obj-$(CONFIG_I2C_PXA)           += i2c-pxa.o
-obj-$(CONFIG_I2C_RPXLITE)       += i2c-rpx.o
 obj-$(CONFIG_I2C_S3C2410)       += i2c-s3c2410.o
 obj-$(CONFIG_I2C_SAVAGE4)       += i2c-savage4.o
 obj-$(CONFIG_I2C_SIBYTE)        += i2c-sibyte.o
@@ -44,6 +44,7 @@ obj-$(CONFIG_I2C_SIS5595)	+= i2c-sis5595.o
 obj-$(CONFIG_I2C_SIS630)        += i2c-sis630.o
 obj-$(CONFIG_I2C_SIS96X)        += i2c-sis96x.o
 obj-$(CONFIG_I2C_STUB)          += i2c-stub.o
+obj-$(CONFIG_I2C_TAOS_EVM)      += i2c-taos-evm.o
 obj-$(CONFIG_I2C_TINY_USB)      += i2c-tiny-usb.o
 obj-$(CONFIG_I2C_VERSATILE)     += i2c-versatile.o
 obj-$(CONFIG_I2C_ACORN)         += i2c-acorn.o
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index a7dd54654a9a..025f19423faf 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -63,14 +63,14 @@ static void i2c_gpio_setscl_val(void *data, int state)
         gpio_set_value(pdata->scl_pin, state);
 }
 
-int i2c_gpio_getsda(void *data)
+static int i2c_gpio_getsda(void *data)
 {
         struct i2c_gpio_platform_data *pdata = data;
 
         return gpio_get_value(pdata->sda_pin);
 }
 
-int i2c_gpio_getscl(void *data)
+static int i2c_gpio_getscl(void *data)
 {
         struct i2c_gpio_platform_data *pdata = data;
 
@@ -142,7 +142,13 @@ static int __init i2c_gpio_probe(struct platform_device *pdev)
         adap->algo_data = bit_data;
         adap->dev.parent = &pdev->dev;
 
-        ret = i2c_bit_add_bus(adap);
+        /*
+         * If "dev->id" is negative we consider it as zero.
+         * The reason to do so is to avoid sysfs names that only make
+         * sense when there are multiple adapters.
+         */
+        adap->nr = pdev->id >= 0 ? pdev->id : 0;
+        ret = i2c_bit_add_numbered_bus(adap);
         if (ret)
                 goto err_add_bus;
 
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 611b57192c96..8f5c686123b8 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -22,12 +22,12 @@
 
 /*
     SUPPORTED DEVICES   PCI ID
-    82801AA             2413           
-    82801AB             2423           
-    82801BA             2443           
-    82801CA/CAM         2483           
-    82801DB             24C3   (HW PEC supported, 32 byte buffer not supported)
-    82801EB             24D3   (HW PEC supported, 32 byte buffer not supported)
+    82801AA             2413
+    82801AB             2423
+    82801BA             2443
+    82801CA/CAM         2483
+    82801DB             24C3   (HW PEC supported)
+    82801EB             24D3   (HW PEC supported)
     6300ESB             25A4
     ICH6                266A
     ICH7                27DA
@@ -74,6 +74,13 @@
 #define SMBHSTCFG_SMB_SMI_EN    2
 #define SMBHSTCFG_I2C_EN        4
 
+/* Auxillary control register bits, ICH4+ only */
+#define SMBAUXCTL_CRC           1
+#define SMBAUXCTL_E32B          2
+
+/* kill bit for SMBHSTCNT */
+#define SMBHSTCNT_KILL          2
+
 /* Other settings */
 #define MAX_TIMEOUT             100
 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
@@ -91,10 +98,15 @@
 #define I801_START              0x40
 #define I801_PEC_EN             0x80    /* ICH4 only */
 
-
-static int i801_transaction(void);
-static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
-                                  int command, int hwpec);
+/* I801 Hosts Status register bits */
+#define SMBHSTSTS_BYTE_DONE     0x80
+#define SMBHSTSTS_INUSE_STS     0x40
+#define SMBHSTSTS_SMBALERT_STS  0x20
+#define SMBHSTSTS_FAILED        0x10
+#define SMBHSTSTS_BUS_ERR       0x08
+#define SMBHSTSTS_DEV_ERR       0x04
+#define SMBHSTSTS_INTR          0x02
+#define SMBHSTSTS_HOST_BUSY     0x01
 
 static unsigned long i801_smba;
 static unsigned char i801_original_hstcfg;
@@ -102,7 +114,7 @@ static struct pci_driver i801_driver;
 static struct pci_dev *I801_dev;
 static int isich4;
 
-static int i801_transaction(void)
+static int i801_transaction(int xact)
 {
         int temp;
         int result = 0;
@@ -127,33 +139,40 @@ static int i801_transaction(void)
                 }
         }
 
-        outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
+        /* the current contents of SMBHSTCNT can be overwritten, since PEC,
+         * INTREN, SMBSCMD are passed in xact */
+        outb_p(xact | I801_START, SMBHSTCNT);
 
         /* We will always wait for a fraction of a second! */
         do {
                 msleep(1);
                 temp = inb_p(SMBHSTSTS);
-        } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
+        } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 
         /* If the SMBus is still busy, we give up */
         if (timeout >= MAX_TIMEOUT) {
                 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
                 result = -1;
+                /* try to stop the current command */
+                dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
+                outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
+                msleep(1);
+                outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
         }
 
-        if (temp & 0x10) {
+        if (temp & SMBHSTSTS_FAILED) {
                 result = -1;
                 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
         }
 
-        if (temp & 0x08) {
+        if (temp & SMBHSTSTS_BUS_ERR) {
                 result = -1;
                 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
                         "until next hard reset. (sorry!)\n");
                 /* Clock stops and slave is stuck in mid-transmission */
         }
 
-        if (temp & 0x04) {
+        if (temp & SMBHSTSTS_DEV_ERR) {
                 result = -1;
                 dev_dbg(&I801_dev->dev, "Error: no response!\n");
         }
@@ -172,44 +191,70 @@ static int i801_transaction(void)
         return result;
 }
 
-/* All-inclusive block transaction function */
-static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
-                                  int command, int hwpec)
+/* wait for INTR bit as advised by Intel */
+static void i801_wait_hwpec(void)
+{
+        int timeout = 0;
+        int temp;
+
+        do {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        } while ((!(temp & SMBHSTSTS_INTR))
+                 && (timeout++ < MAX_TIMEOUT));
+
+        if (timeout >= MAX_TIMEOUT) {
+                dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
+        }
+        outb_p(temp, SMBHSTSTS);
+}
+
+static int i801_block_transaction_by_block(union i2c_smbus_data *data,
+                                           char read_write, int hwpec)
+{
+        int i, len;
+
+        inb_p(SMBHSTCNT); /* reset the data buffer index */
+
+        /* Use 32-byte buffer to process this transaction */
+        if (read_write == I2C_SMBUS_WRITE) {
+                len = data->block[0];
+                outb_p(len, SMBHSTDAT0);
+                for (i = 0; i < len; i++)
+                        outb_p(data->block[i+1], SMBBLKDAT);
+        }
+
+        if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
+                             I801_PEC_EN * hwpec))
+                return -1;
+
+        if (read_write == I2C_SMBUS_READ) {
+                len = inb_p(SMBHSTDAT0);
+                if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
+                        return -1;
+
+                data->block[0] = len;
+                for (i = 0; i < len; i++)
+                        data->block[i + 1] = inb_p(SMBBLKDAT);
+        }
+        return 0;
+}
+
+static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
+                                               char read_write, int hwpec)
 {
         int i, len;
         int smbcmd;
         int temp;
         int result = 0;
         int timeout;
-        unsigned char hostc, errmask;
+        unsigned char errmask;
 
-        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
-                if (read_write == I2C_SMBUS_WRITE) {
-                        /* set I2C_EN bit in configuration register */
-                        pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
-                        pci_write_config_byte(I801_dev, SMBHSTCFG,
-                                              hostc | SMBHSTCFG_I2C_EN);
-                } else {
-                        dev_err(&I801_dev->dev,
-                                "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
-                        return -1;
-                }
-        }
+        len = data->block[0];
 
         if (read_write == I2C_SMBUS_WRITE) {
-                len = data->block[0];
-                if (len < 1)
-                        len = 1;
-                if (len > 32)
-                        len = 32;
                 outb_p(len, SMBHSTDAT0);
                 outb_p(data->block[1], SMBBLKDAT);
-        } else {
-                len = 32;       /* max for reads */
-        }
-
-        if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
-                /* set 32 byte buffer */
         }
 
         for (i = 1; i <= len; i++) {
@@ -227,13 +272,13 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
                 /* Make sure the SMBus host is ready to start transmitting */
                 temp = inb_p(SMBHSTSTS);
                 if (i == 1) {
-                        /* Erronenous conditions before transaction: 
+                        /* Erronenous conditions before transaction:
                          * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
-                        errmask=0x9f; 
+                        errmask = 0x9f;
                 } else {
-                        /* Erronenous conditions during transaction: 
+                        /* Erronenous conditions during transaction:
                          * Failed, Bus_Err, Dev_Err, Intr */
-                        errmask=0x1e; 
+                        errmask = 0x1e;
                 }
                 if (temp & errmask) {
                         dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
@@ -242,14 +287,11 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
                         if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
                                 dev_err(&I801_dev->dev,
                                         "Reset failed! (%02x)\n", temp);
-                                result = -1;
-                                goto END;
+                                return -1;
                         }
-                        if (i != 1) {
+                        if (i != 1)
                                 /* if die in middle of block transaction, fail */
-                                result = -1;
-                                goto END;
-                        }
+                                return -1;
                 }
 
                 if (i == 1)
@@ -261,33 +303,38 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
                         msleep(1);
                         temp = inb_p(SMBHSTSTS);
                 }
-                    while ((!(temp & 0x80))
-                           && (timeout++ < MAX_TIMEOUT));
+                while ((!(temp & SMBHSTSTS_BYTE_DONE))
+                       && (timeout++ < MAX_TIMEOUT));
 
                 /* If the SMBus is still busy, we give up */
                 if (timeout >= MAX_TIMEOUT) {
+                        /* try to stop the current command */
+                        dev_dbg(&I801_dev->dev, "Terminating the current "
+                                                "operation\n");
+                        outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
+                        msleep(1);
+                        outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
+                                SMBHSTCNT);
                         result = -1;
                         dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
                 }
 
-                if (temp & 0x10) {
+                if (temp & SMBHSTSTS_FAILED) {
                         result = -1;
                         dev_dbg(&I801_dev->dev,
                                 "Error: Failed bus transaction\n");
-                } else if (temp & 0x08) {
+                } else if (temp & SMBHSTSTS_BUS_ERR) {
                         result = -1;
                         dev_err(&I801_dev->dev, "Bus collision!\n");
-                } else if (temp & 0x04) {
+                } else if (temp & SMBHSTSTS_DEV_ERR) {
                         result = -1;
                         dev_dbg(&I801_dev->dev, "Error: no response!\n");
                 }
 
                 if (i == 1 && read_write == I2C_SMBUS_READ) {
                         len = inb_p(SMBHSTDAT0);
-                        if (len < 1)
-                                len = 1;
-                        if (len > 32)
-                                len = 32;
+                        if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
+                                return -1;
                         data->block[0] = len;
                 }
 
@@ -310,25 +357,58 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
                         inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
 
                 if (result < 0)
-                        goto END;
+                        return result;
         }
+        return result;
+}
 
-        if (hwpec) {
-                /* wait for INTR bit as advised by Intel */
-                timeout = 0;
-                do {
-                        msleep(1);
-                        temp = inb_p(SMBHSTSTS);
-                } while ((!(temp & 0x02))
-                           && (timeout++ < MAX_TIMEOUT));
+static int i801_set_block_buffer_mode(void)
+{
+        outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
+        if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
+                return -1;
+        return 0;
+}
 
-                if (timeout >= MAX_TIMEOUT) {
-                        dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
+/* Block transaction function */
+static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
+                                  int command, int hwpec)
+{
+        int result = 0;
+        unsigned char hostc;
+
+        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
+                if (read_write == I2C_SMBUS_WRITE) {
+                        /* set I2C_EN bit in configuration register */
+                        pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
+                        pci_write_config_byte(I801_dev, SMBHSTCFG,
+                                              hostc | SMBHSTCFG_I2C_EN);
+                } else {
+                        dev_err(&I801_dev->dev,
+                                "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
+                        return -1;
                 }
-                outb_p(temp, SMBHSTSTS); 
         }
-        result = 0;
-END:
+
+        if (read_write == I2C_SMBUS_WRITE) {
+                if (data->block[0] < 1)
+                        data->block[0] = 1;
+                if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
+                        data->block[0] = I2C_SMBUS_BLOCK_MAX;
+        } else {
+                data->block[0] = 32;    /* max for reads */
+        }
+
+        if (isich4 && i801_set_block_buffer_mode() == 0 )
+                result = i801_block_transaction_by_block(data, read_write,
+                                                         hwpec);
+        else
+                result = i801_block_transaction_byte_by_byte(data, read_write,
+                                                             hwpec);
+
+        if (result == 0 && hwpec)
+                i801_wait_hwpec();
+
         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
                 /* restore saved configuration register value */
                 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
@@ -393,19 +473,22 @@ static s32 i801_access(struct i2c_adapter * adap, u16 addr,
                 return -1;
         }
 
-        outb_p(hwpec, SMBAUXCTL);       /* enable/disable hardware PEC */
+        if (hwpec)      /* enable/disable hardware PEC */
+                outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
+        else
+                outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
 
         if(block)
                 ret = i801_block_transaction(data, read_write, size, hwpec);
-        else {
-                outb_p(xact | ENABLE_INT9, SMBHSTCNT);
-                ret = i801_transaction();
-        }
+        else
+                ret = i801_transaction(xact | ENABLE_INT9);
 
         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
-           time, so we forcibly disable it after every transaction. */
+           time, so we forcibly disable it after every transaction. Turn off
+           E32B for the same reason. */
         if (hwpec)
-                outb_p(0, SMBAUXCTL);
+                outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
+                       SMBAUXCTL);
 
         if(block)
                 return ret;
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 90e2d9350c1b..440342bc62e1 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -491,6 +491,7 @@ iop3xx_i2c_probe(struct platform_device *pdev)
         new_adapter->id = I2C_HW_IOP3XX;
         new_adapter->owner = THIS_MODULE;
         new_adapter->dev.parent = &pdev->dev;
+        new_adapter->nr = pdev->id;
 
         /*
          * Default values...should these come in from board code?
@@ -508,7 +509,7 @@ iop3xx_i2c_probe(struct platform_device *pdev)
         platform_set_drvdata(pdev, new_adapter);
         new_adapter->algo_data = adapter_data;
 
-        i2c_add_adapter(new_adapter);
+        i2c_add_numbered_adapter(new_adapter);
 
         return 0;
 
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index c6b6898592b1..851c3ed513d0 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -74,6 +74,25 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
+/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
+ * the bus, because it wants to send ACK.
+ * Following sequence of enabling/disabling and sending start/stop generates
+ * the pulse, so it's all OK.
+ */
+static void mpc_i2c_fixup(struct mpc_i2c *i2c)
+{
+        writeccr(i2c, 0);
+        udelay(30);
+        writeccr(i2c, CCR_MEN);
+        udelay(30);
+        writeccr(i2c, CCR_MSTA | CCR_MTX);
+        udelay(30);
+        writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
+        udelay(30);
+        writeccr(i2c, CCR_MEN);
+        udelay(30);
+}
+
 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
 {
         unsigned long orig_jiffies = jiffies;
@@ -153,6 +172,7 @@ static void mpc_i2c_start(struct mpc_i2c *i2c)
 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 {
         writeccr(i2c, CCR_MEN);
+        writeccr(i2c, 0);
 }
 
 static int mpc_write(struct mpc_i2c *i2c, int target,
@@ -245,6 +265,9 @@ static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
                 }
                 if (time_after(jiffies, orig_jiffies + HZ)) {
                         pr_debug("I2C: timeout\n");
+                        if (readb(i2c->base + MPC_I2C_SR) ==
+                            (CSR_MCF | CSR_MBB | CSR_RXAK))
+                                mpc_i2c_fixup(i2c);
                         return -EIO;
                 }
                 schedule();
@@ -327,9 +350,10 @@ static int fsl_i2c_probe(struct platform_device *pdev)
         platform_set_drvdata(pdev, i2c);
 
         i2c->adap = mpc_ops;
+        i2c->adap.nr = pdev->id;
         i2c_set_adapdata(&i2c->adap, i2c);
         i2c->adap.dev.parent = &pdev->dev;
-        if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
+        if ((result = i2c_add_numbered_adapter(&i2c->adap)) < 0) {
                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
                 goto fail_add;
         }
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index a55b3335d1be..251154ae5d97 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -527,6 +527,7 @@ mv64xxx_i2c_probe(struct platform_device *pd)
         drv_data->adapter.class = I2C_CLASS_HWMON;
         drv_data->adapter.timeout = pdata->timeout;
         drv_data->adapter.retries = pdata->retries;
+        drv_data->adapter.nr = pd->id;
         platform_set_drvdata(pd, drv_data);
         i2c_set_adapdata(&drv_data->adapter, drv_data);
 
@@ -539,7 +540,7 @@ mv64xxx_i2c_probe(struct platform_device *pd)
                         drv_data->irq);
                 rc = -EINVAL;
                 goto exit_unmap_regs;
-        } else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) {
+        } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
                 dev_err(&drv_data->adapter.dev,
                         "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
                 goto exit_free_irq;
diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c
index 3cd0d63e7b50..c48140f782d0 100644
--- a/drivers/i2c/busses/i2c-nforce2.c
+++ b/drivers/i2c/busses/i2c-nforce2.c
@@ -61,6 +61,7 @@ struct nforce2_smbus {
         struct i2c_adapter adapter;
         int base;
         int size;
+        int blockops;
 };
 
 
@@ -80,6 +81,8 @@ struct nforce2_smbus {
 #define NVIDIA_SMB_ADDR         (smbus->base + 0x02)    /* address */
 #define NVIDIA_SMB_CMD          (smbus->base + 0x03)    /* command */
 #define NVIDIA_SMB_DATA         (smbus->base + 0x04)    /* 32 data registers */
+#define NVIDIA_SMB_BCNT         (smbus->base + 0x24)    /* number of data
+                                                           bytes */
 
 #define NVIDIA_SMB_STS_DONE     0x80
 #define NVIDIA_SMB_STS_ALRM     0x40
@@ -92,6 +95,7 @@ struct nforce2_smbus {
 #define NVIDIA_SMB_PRTCL_BYTE                   0x04
 #define NVIDIA_SMB_PRTCL_BYTE_DATA              0x06
 #define NVIDIA_SMB_PRTCL_WORD_DATA              0x08
+#define NVIDIA_SMB_PRTCL_BLOCK_DATA             0x0a
 #define NVIDIA_SMB_PRTCL_PEC                    0x80
 
 static struct pci_driver nforce2_driver;
@@ -103,6 +107,8 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
 {
         struct nforce2_smbus *smbus = adap->algo_data;
         unsigned char protocol, pec, temp;
+        u8 len;
+        int i;
 
         protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
                 NVIDIA_SMB_PRTCL_WRITE;
@@ -137,6 +143,25 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
                         protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec;
                         break;
 
+                case I2C_SMBUS_BLOCK_DATA:
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        if (read_write == I2C_SMBUS_WRITE) {
+                                len = data->block[0];
+                                if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
+                                        dev_err(&adap->dev,
+                                                "Transaction failed "
+                                                "(requested block size: %d)\n",
+                                                len);
+                                        return -1;
+                                }
+                                outb_p(len, NVIDIA_SMB_BCNT);
+                                for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
+                                        outb_p(data->block[i + 1],
+                                               NVIDIA_SMB_DATA+i);
+                        }
+                        protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec;
+                        break;
+
                 default:
                         dev_err(&adap->dev, "Unsupported transaction %d\n", size);
                         return -1;
@@ -174,6 +199,14 @@ static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
                 case I2C_SMBUS_WORD_DATA:
                         data->word = inb_p(NVIDIA_SMB_DATA) | (inb_p(NVIDIA_SMB_DATA+1) << 8);
                         break;
+
+                case I2C_SMBUS_BLOCK_DATA:
+                        len = inb_p(NVIDIA_SMB_BCNT);
+                        len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
+                        for (i = 0; i < len; i++)
+                                data->block[i+1] = inb_p(NVIDIA_SMB_DATA + i);
+                        data->block[0] = len;
+                        break;
         }
 
         return 0;
@@ -184,7 +217,9 @@ static u32 nforce2_func(struct i2c_adapter *adapter)
 {
         /* other functionality might be possible, but is not tested */
         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
-            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA;
+               I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+               (((struct nforce2_smbus*)adapter->algo_data)->blockops ?
+                I2C_FUNC_SMBUS_BLOCK_DATA : 0);
 }
 
 static struct i2c_algorithm smbus_algorithm = {
@@ -268,6 +303,13 @@ static int __devinit nforce2_probe(struct pci_dev *dev, const struct pci_device_
                 return -ENOMEM;
         pci_set_drvdata(dev, smbuses);
 
+        switch(dev->device) {
+        case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
+        case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
+                smbuses[0].blockops = 1;
+                smbuses[1].blockops = 1;
+        }
+
         /* SMBus adapter 1 */
         res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
         if (res1 < 0) {
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 5a52bf5e3fb0..debc76cd2161 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -23,7 +23,7 @@
    Supports:
         Intel PIIX4, 440MX
         Serverworks OSB4, CSB5, CSB6, HT-1000
-        ATI IXP200, IXP300, IXP400, SB600
+        ATI IXP200, IXP300, IXP400, SB600, SB700
         SMSC Victory66
 
    Note: we assume there can only be one device, with one SMBus interface.
@@ -399,6 +399,8 @@ static struct pci_device_id piix4_ids[] = {
           .driver_data = 0 },
         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SMBUS),
           .driver_data = 0 },
+        { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SMBUS),
+          .driver_data = 0 },
         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4),
           .driver_data = 0 },
         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5),
diff --git a/drivers/i2c/busses/i2c-pmcmsp.c b/drivers/i2c/busses/i2c-pmcmsp.c
new file mode 100644
index 000000000000..03188d277af1
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pmcmsp.c
@@ -0,0 +1,653 @@
+/*
+ * Specific bus support for PMC-TWI compliant implementation on MSP71xx.
+ *
+ * Copyright 2005-2007 PMC-Sierra, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#define DRV_NAME        "pmcmsptwi"
+
+#define MSP_TWI_SF_CLK_REG_OFFSET       0x00
+#define MSP_TWI_HS_CLK_REG_OFFSET       0x04
+#define MSP_TWI_CFG_REG_OFFSET          0x08
+#define MSP_TWI_CMD_REG_OFFSET          0x0c
+#define MSP_TWI_ADD_REG_OFFSET          0x10
+#define MSP_TWI_DAT_0_REG_OFFSET        0x14
+#define MSP_TWI_DAT_1_REG_OFFSET        0x18
+#define MSP_TWI_INT_STS_REG_OFFSET      0x1c
+#define MSP_TWI_INT_MSK_REG_OFFSET      0x20
+#define MSP_TWI_BUSY_REG_OFFSET         0x24
+
+#define MSP_TWI_INT_STS_DONE                    (1 << 0)
+#define MSP_TWI_INT_STS_LOST_ARBITRATION        (1 << 1)
+#define MSP_TWI_INT_STS_NO_RESPONSE             (1 << 2)
+#define MSP_TWI_INT_STS_DATA_COLLISION          (1 << 3)
+#define MSP_TWI_INT_STS_BUSY                    (1 << 4)
+#define MSP_TWI_INT_STS_ALL                     0x1f
+
+#define MSP_MAX_BYTES_PER_RW            8
+#define MSP_MAX_POLL                    5
+#define MSP_POLL_DELAY                  10
+#define MSP_IRQ_TIMEOUT                 (MSP_MAX_POLL * MSP_POLL_DELAY)
+
+/* IO Operation macros */
+#define pmcmsptwi_readl         __raw_readl
+#define pmcmsptwi_writel        __raw_writel
+
+/* TWI command type */
+enum pmcmsptwi_cmd_type {
+        MSP_TWI_CMD_WRITE       = 0,    /* Write only */
+        MSP_TWI_CMD_READ        = 1,    /* Read only */
+        MSP_TWI_CMD_WRITE_READ  = 2,    /* Write then Read */
+};
+
+/* The possible results of the xferCmd */
+enum pmcmsptwi_xfer_result {
+        MSP_TWI_XFER_OK = 0,
+        MSP_TWI_XFER_TIMEOUT,
+        MSP_TWI_XFER_BUSY,
+        MSP_TWI_XFER_DATA_COLLISION,
+        MSP_TWI_XFER_NO_RESPONSE,
+        MSP_TWI_XFER_LOST_ARBITRATION,
+};
+
+/* Corresponds to a PMCTWI clock configuration register */
+struct pmcmsptwi_clock {
+        u8 filter;      /* Bits 15:12,  default = 0x03 */
+        u16 clock;      /* Bits 9:0,    default = 0x001f */
+};
+
+struct pmcmsptwi_clockcfg {
+        struct pmcmsptwi_clock standard;  /* The standard/fast clock config */
+        struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
+};
+
+/* Corresponds to the main TWI configuration register */
+struct pmcmsptwi_cfg {
+        u8 arbf;        /* Bits 15:12,  default=0x03 */
+        u8 nak;         /* Bits 11:8,   default=0x03 */
+        u8 add10;       /* Bit 7,       default=0x00 */
+        u8 mst_code;    /* Bits 6:4,    default=0x00 */
+        u8 arb;         /* Bit 1,       default=0x01 */
+        u8 highspeed;   /* Bit 0,       default=0x00 */
+};
+
+/* A single pmctwi command to issue */
+struct pmcmsptwi_cmd {
+        u16 addr;       /* The slave address (7 or 10 bits) */
+        enum pmcmsptwi_cmd_type type;   /* The command type */
+        u8 write_len;   /* Number of bytes in the write buffer */
+        u8 read_len;    /* Number of bytes in the read buffer */
+        u8 *write_data; /* Buffer of characters to send */
+        u8 *read_data;  /* Buffer to fill with incoming data */
+};
+
+/* The private data */
+struct pmcmsptwi_data {
+        void __iomem *iobase;                   /* iomapped base for IO */
+        int irq;                                /* IRQ to use (0 disables) */
+        struct completion wait;                 /* Completion for xfer */
+        struct mutex lock;                      /* Used for threadsafeness */
+        enum pmcmsptwi_xfer_result last_result; /* result of last xfer */
+};
+
+/* The default settings */
+const static struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
+        .standard = {
+                .filter = 0x3,
+                .clock  = 0x1f,
+        },
+        .highspeed = {
+                .filter = 0x3,
+                .clock  = 0x1f,
+        },
+};
+
+const static struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
+        .arbf           = 0x03,
+        .nak            = 0x03,
+        .add10          = 0x00,
+        .mst_code       = 0x00,
+        .arb            = 0x01,
+        .highspeed      = 0x00,
+};
+
+static struct pmcmsptwi_data pmcmsptwi_data;
+
+static struct i2c_adapter pmcmsptwi_adapter;
+
+/* inline helper functions */
+static inline u32 pmcmsptwi_clock_to_reg(
+                        const struct pmcmsptwi_clock *clock)
+{
+        return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
+}
+
+static inline void pmcmsptwi_reg_to_clock(
+                        u32 reg, struct pmcmsptwi_clock *clock)
+{
+        clock->filter = (reg >> 12) & 0xf;
+        clock->clock = reg & 0x03ff;
+}
+
+static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
+{
+        return ((cfg->arbf & 0xf) << 12) |
+                ((cfg->nak & 0xf) << 8) |
+                ((cfg->add10 & 0x1) << 7) |
+                ((cfg->mst_code & 0x7) << 4) |
+                ((cfg->arb & 0x1) << 1) |
+                (cfg->highspeed & 0x1);
+}
+
+static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg)
+{
+        cfg->arbf = (reg >> 12) & 0xf;
+        cfg->nak = (reg >> 8) & 0xf;
+        cfg->add10 = (reg >> 7) & 0x1;
+        cfg->mst_code = (reg >> 4) & 0x7;
+        cfg->arb = (reg >> 1) & 0x1;
+        cfg->highspeed = reg & 0x1;
+}
+
+/*
+ * Sets the current clock configuration
+ */
+static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg *cfg,
+                                        struct pmcmsptwi_data *data)
+{
+        mutex_lock(&data->lock);
+        pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
+                                data->iobase + MSP_TWI_SF_CLK_REG_OFFSET);
+        pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
+                                data->iobase + MSP_TWI_HS_CLK_REG_OFFSET);
+        mutex_unlock(&data->lock);
+}
+
+/*
+ * Gets the current TWI bus configuration
+ */
+static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg *cfg,
+                                        struct pmcmsptwi_data *data)
+{
+        mutex_lock(&data->lock);
+        pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
+                                data->iobase + MSP_TWI_CFG_REG_OFFSET), cfg);
+        mutex_unlock(&data->lock);
+}
+
+/*
+ * Sets the current TWI bus configuration
+ */
+static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg *cfg,
+                                        struct pmcmsptwi_data *data)
+{
+        mutex_lock(&data->lock);
+        pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
+                                data->iobase + MSP_TWI_CFG_REG_OFFSET);
+        mutex_unlock(&data->lock);
+}
+
+/*
+ * Parses the 'int_sts' register and returns a well-defined error code
+ */
+static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg)
+{
+        if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) {
+                dev_dbg(&pmcmsptwi_adapter.dev,
+                        "Result: Lost arbitration\n");
+                return MSP_TWI_XFER_LOST_ARBITRATION;
+        } else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) {
+                dev_dbg(&pmcmsptwi_adapter.dev,
+                        "Result: No response\n");
+                return MSP_TWI_XFER_NO_RESPONSE;
+        } else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) {
+                dev_dbg(&pmcmsptwi_adapter.dev,
+                        "Result: Data collision\n");
+                return MSP_TWI_XFER_DATA_COLLISION;
+        } else if (reg & MSP_TWI_INT_STS_BUSY) {
+                dev_dbg(&pmcmsptwi_adapter.dev,
+                        "Result: Bus busy\n");
+                return MSP_TWI_XFER_BUSY;
+        }
+
+        dev_dbg(&pmcmsptwi_adapter.dev, "Result: Operation succeeded\n");
+        return MSP_TWI_XFER_OK;
+}
+
+/*
+ * In interrupt mode, handle the interrupt.
+ * NOTE: Assumes data->lock is held.
+ */
+static irqreturn_t pmcmsptwi_interrupt(int irq, void *ptr)
+{
+        struct pmcmsptwi_data *data = ptr;
+
+        u32 reason = pmcmsptwi_readl(data->iobase +
+                                        MSP_TWI_INT_STS_REG_OFFSET);
+        pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
+
+        dev_dbg(&pmcmsptwi_adapter.dev, "Got interrupt 0x%08x\n", reason);
+        if (!(reason & MSP_TWI_INT_STS_DONE))
+                return IRQ_NONE;
+
+        data->last_result = pmcmsptwi_get_result(reason);
+        complete(&data->wait);
+
+        return IRQ_HANDLED;
+}
+
+/*
+ * Probe for and register the device and return 0 if there is one.
+ */
+static int __devinit pmcmsptwi_probe(struct platform_device *pldev)
+{
+        struct resource *res;
+        int rc = -ENODEV;
+
+        /* get the static platform resources */
+        res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pldev->dev, "IOMEM resource not found\n");
+                goto ret_err;
+        }
+
+        /* reserve the memory region */
+        if (!request_mem_region(res->start, res->end - res->start + 1,
+                                pldev->name)) {
+                dev_err(&pldev->dev,
+                        "Unable to get memory/io address region 0x%08x\n",
+                        res->start);
+                rc = -EBUSY;
+                goto ret_err;
+        }
+
+        /* remap the memory */
+        pmcmsptwi_data.iobase = ioremap_nocache(res->start,
+                                                res->end - res->start + 1);
+        if (!pmcmsptwi_data.iobase) {
+                dev_err(&pldev->dev,
+                        "Unable to ioremap address 0x%08x\n", res->start);
+                rc = -EIO;
+                goto ret_unreserve;
+        }
+
+        /* request the irq */
+        pmcmsptwi_data.irq = platform_get_irq(pldev, 0);
+        if (pmcmsptwi_data.irq) {
+                rc = request_irq(pmcmsptwi_data.irq, &pmcmsptwi_interrupt,
+                        IRQF_SHARED | IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+                        pldev->name, &pmcmsptwi_data);
+                if (rc == 0) {
+                        /*
+                         * Enable 'DONE' interrupt only.
+                         *
+                         * If you enable all interrupts, you will get one on
+                         * error and another when the operation completes.
+                         * This way you only have to handle one interrupt,
+                         * but you can still check all result flags.
+                         */
+                        pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
+                                        pmcmsptwi_data.iobase +
+                                        MSP_TWI_INT_MSK_REG_OFFSET);
+                } else {
+                        dev_warn(&pldev->dev,
+                                "Could not assign TWI IRQ handler "
+                                "to irq %d (continuing with poll)\n",
+                                pmcmsptwi_data.irq);
+                        pmcmsptwi_data.irq = 0;
+                }
+        }
+
+        init_completion(&pmcmsptwi_data.wait);
+        mutex_init(&pmcmsptwi_data.lock);
+
+        pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg, &pmcmsptwi_data);
+        pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg, &pmcmsptwi_data);
+
+        printk(KERN_INFO DRV_NAME ": Registering MSP71xx I2C adapter\n");
+
+        pmcmsptwi_adapter.dev.parent = &pldev->dev;
+        platform_set_drvdata(pldev, &pmcmsptwi_adapter);
+        i2c_set_adapdata(&pmcmsptwi_adapter, &pmcmsptwi_data);
+
+        rc = i2c_add_adapter(&pmcmsptwi_adapter);
+        if (rc) {
+                dev_err(&pldev->dev, "Unable to register I2C adapter\n");
+                goto ret_unmap;
+        }
+
+        return 0;
+
+ret_unmap:
+        platform_set_drvdata(pldev, NULL);
+        if (pmcmsptwi_data.irq) {
+                pmcmsptwi_writel(0,
+                        pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
+                free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
+        }
+
+        iounmap(pmcmsptwi_data.iobase);
+
+ret_unreserve:
+        release_mem_region(res->start, res->end - res->start + 1);
+
+ret_err:
+        return rc;
+}
+
+/*
+ * Release the device and return 0 if there is one.
+ */
+static int __devexit pmcmsptwi_remove(struct platform_device *pldev)
+{
+        struct resource *res;
+
+        i2c_del_adapter(&pmcmsptwi_adapter);
+
+        platform_set_drvdata(pldev, NULL);
+        if (pmcmsptwi_data.irq) {
+                pmcmsptwi_writel(0,
+                        pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
+                free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
+        }
+
+        iounmap(pmcmsptwi_data.iobase);
+
+        res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
+        release_mem_region(res->start, res->end - res->start + 1);
+
+        return 0;
+}
+
+/*
+ * Polls the 'busy' register until the command is complete.
+ * NOTE: Assumes data->lock is held.
+ */
+static void pmcmsptwi_poll_complete(struct pmcmsptwi_data *data)
+{
+        int i;
+
+        for (i = 0; i < MSP_MAX_POLL; i++) {
+                u32 val = pmcmsptwi_readl(data->iobase +
+                                                MSP_TWI_BUSY_REG_OFFSET);
+                if (val == 0) {
+                        u32 reason = pmcmsptwi_readl(data->iobase +
+                                                MSP_TWI_INT_STS_REG_OFFSET);
+                        pmcmsptwi_writel(reason, data->iobase +
+                                                MSP_TWI_INT_STS_REG_OFFSET);
+                        data->last_result = pmcmsptwi_get_result(reason);
+                        return;
+                }
+                udelay(MSP_POLL_DELAY);
+        }
+
+        dev_dbg(&pmcmsptwi_adapter.dev, "Result: Poll timeout\n");
+        data->last_result = MSP_TWI_XFER_TIMEOUT;
+}
+
+/*
+ * Do the transfer (low level):
+ *   May use interrupt-driven or polling, depending on if an IRQ is
+ *   presently registered.
+ * NOTE: Assumes data->lock is held.
+ */
+static enum pmcmsptwi_xfer_result pmcmsptwi_do_xfer(
+                        u32 reg, struct pmcmsptwi_data *data)
+{
+        dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg);
+        pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
+        if (data->irq) {
+                unsigned long timeleft = wait_for_completion_timeout(
+                                                &data->wait, MSP_IRQ_TIMEOUT);
+                if (timeleft == 0) {
+                        dev_dbg(&pmcmsptwi_adapter.dev,
+                                "Result: IRQ timeout\n");
+                        complete(&data->wait);
+                        data->last_result = MSP_TWI_XFER_TIMEOUT;
+                }
+        } else
+                pmcmsptwi_poll_complete(data);
+
+        return data->last_result;
+}
+
+/*
+ * Helper routine, converts 'pmctwi_cmd' struct to register format
+ */
+static inline u32 pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd *cmd)
+{
+        return ((cmd->type & 0x3) << 8) |
+                (((cmd->write_len - 1) & 0x7) << 4) |
+                ((cmd->read_len - 1) & 0x7);
+}
+
+/*
+ * Do the transfer (high level)
+ */
+static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
+                        struct pmcmsptwi_cmd *cmd,
+                        struct pmcmsptwi_data *data)
+{
+        enum pmcmsptwi_xfer_result retval;
+
+        if ((cmd->type == MSP_TWI_CMD_WRITE && cmd->write_len == 0) ||
+            (cmd->type == MSP_TWI_CMD_READ && cmd->read_len == 0) ||
+            (cmd->type == MSP_TWI_CMD_WRITE_READ &&
+            (cmd->read_len == 0 || cmd->write_len == 0))) {
+                dev_err(&pmcmsptwi_adapter.dev,
+                        "%s: Cannot transfer less than 1 byte\n",
+                        __FUNCTION__);
+                return -EINVAL;
+        }
+
+        if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
+            cmd->write_len > MSP_MAX_BYTES_PER_RW) {
+                dev_err(&pmcmsptwi_adapter.dev,
+                        "%s: Cannot transfer more than %d bytes\n",
+                        __FUNCTION__, MSP_MAX_BYTES_PER_RW);
+                return -EINVAL;
+        }
+
+        mutex_lock(&data->lock);
+        dev_dbg(&pmcmsptwi_adapter.dev,
+                "Setting address to 0x%04x\n", cmd->addr);
+        pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
+
+        if (cmd->type == MSP_TWI_CMD_WRITE ||
+            cmd->type == MSP_TWI_CMD_WRITE_READ) {
+                __be64 tmp = cpu_to_be64p((u64 *)cmd->write_data);
+                tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
+                dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
+                pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
+                                data->iobase + MSP_TWI_DAT_0_REG_OFFSET);
+                if (cmd->write_len > 4)
+                        pmcmsptwi_writel(tmp >> 32,
+                                data->iobase + MSP_TWI_DAT_1_REG_OFFSET);
+        }
+
+        retval = pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd), data);
+        if (retval != MSP_TWI_XFER_OK)
+                goto xfer_err;
+
+        if (cmd->type == MSP_TWI_CMD_READ ||
+            cmd->type == MSP_TWI_CMD_WRITE_READ) {
+                int i;
+                u64 rmsk = ~(0xffffffffffffffffLL << (cmd->read_len * 8));
+                u64 tmp = (u64)pmcmsptwi_readl(data->iobase +
+                                        MSP_TWI_DAT_0_REG_OFFSET);
+                if (cmd->read_len > 4)
+                        tmp |= (u64)pmcmsptwi_readl(data->iobase +
+                                        MSP_TWI_DAT_1_REG_OFFSET) << 32;
+                tmp &= rmsk;
+                dev_dbg(&pmcmsptwi_adapter.dev, "Read 0x%016llx\n", tmp);
+
+                for (i = 0; i < cmd->read_len; i++)
+                        cmd->read_data[i] = tmp >> i;
+        }
+
+xfer_err:
+        mutex_unlock(&data->lock);
+
+        return retval;
+}
+
+/* -- Algorithm functions -- */
+
+/*
+ * Sends an i2c command out on the adapter
+ */
+static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
+                                struct i2c_msg *msg, int num)
+{
+        struct pmcmsptwi_data *data = i2c_get_adapdata(adap);
+        struct pmcmsptwi_cmd cmd;
+        struct pmcmsptwi_cfg oldcfg, newcfg;
+        int ret;
+
+        if (num > 2) {
+                dev_dbg(&adap->dev, "%d messages unsupported\n", num);
+                return -EINVAL;
+        } else if (num == 2) {
+                /* Check for a dual write-then-read command */
+                struct i2c_msg *nextmsg = msg + 1;
+                if (!(msg->flags & I2C_M_RD) &&
+                    (nextmsg->flags & I2C_M_RD) &&
+                    msg->addr == nextmsg->addr) {
+                        cmd.type = MSP_TWI_CMD_WRITE_READ;
+                        cmd.write_len = msg->len;
+                        cmd.write_data = msg->buf;
+                        cmd.read_len = nextmsg->len;
+                        cmd.read_data = nextmsg->buf;
+                } else {
+                        dev_dbg(&adap->dev,
+                                "Non write-read dual messages unsupported\n");
+                        return -EINVAL;
+                }
+        } else if (msg->flags & I2C_M_RD) {
+                cmd.type = MSP_TWI_CMD_READ;
+                cmd.read_len = msg->len;
+                cmd.read_data = msg->buf;
+                cmd.write_len = 0;
+                cmd.write_data = NULL;
+        } else {
+                cmd.type = MSP_TWI_CMD_WRITE;
+                cmd.read_len = 0;
+                cmd.read_data = NULL;
+                cmd.write_len = msg->len;
+                cmd.write_data = msg->buf;
+        }
+
+        if (msg->len == 0) {
+                dev_err(&adap->dev, "Zero-byte messages unsupported\n");
+                return -EINVAL;
+        }
+
+        cmd.addr = msg->addr;
+
+        if (msg->flags & I2C_M_TEN) {
+                pmcmsptwi_get_twi_config(&newcfg, data);
+                memcpy(&oldcfg, &newcfg, sizeof(oldcfg));
+
+                /* Set the special 10-bit address flag */
+                newcfg.add10 = 1;
+
+                pmcmsptwi_set_twi_config(&newcfg, data);
+        }
+
+        /* Execute the command */
+        ret = pmcmsptwi_xfer_cmd(&cmd, data);
+
+        if (msg->flags & I2C_M_TEN)
+                pmcmsptwi_set_twi_config(&oldcfg, data);
+
+        dev_dbg(&adap->dev, "I2C %s of %d bytes ",
+                (msg->flags & I2C_M_RD) ? "read" : "write", msg->len);
+        if (ret != MSP_TWI_XFER_OK) {
+                /*
+                 * TODO: We could potentially loop and retry in the case
+                 * of MSP_TWI_XFER_TIMEOUT.
+                 */
+                dev_dbg(&adap->dev, "failed\n");
+                return -1;
+        }
+
+        dev_dbg(&adap->dev, "succeeded\n");
+        return 0;
+}
+
+static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
+                I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
+                I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
+}
+
+/* -- Initialization -- */
+
+static struct i2c_algorithm pmcmsptwi_algo = {
+        .master_xfer    = pmcmsptwi_master_xfer,
+        .functionality  = pmcmsptwi_i2c_func,
+};
+
+static struct i2c_adapter pmcmsptwi_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &pmcmsptwi_algo,
+        .name           = DRV_NAME,
+};
+
+static struct platform_driver pmcmsptwi_driver = {
+        .probe  = pmcmsptwi_probe,
+        .remove = __devexit_p(pmcmsptwi_remove),
+        .driver {
+                .name   = DRV_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init pmcmsptwi_init(void)
+{
+        return platform_driver_register(&pmcmsptwi_driver);
+}
+
+static void __exit pmcmsptwi_exit(void)
+{
+        platform_driver_unregister(&pmcmsptwi_driver);
+}
+
+MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
+MODULE_LICENSE("GPL");
+
+module_init(pmcmsptwi_init);
+module_exit(pmcmsptwi_exit);
diff --git a/drivers/i2c/busses/i2c-powermac.c b/drivers/i2c/busses/i2c-powermac.c
index 1425d2245c82..0ab4f2627c26 100644
--- a/drivers/i2c/busses/i2c-powermac.c
+++ b/drivers/i2c/busses/i2c-powermac.c
@@ -121,8 +121,7 @@ static s32 i2c_powermac_smbus_xfer(	struct i2c_adapter*	adap,
                 if (rc)
                         goto bail;
                 rc = pmac_i2c_xfer(bus, addrdir, 1, command,
-                                   read ? data->block : &data->block[1],
-                                   data->block[0]);
+                                   &data->block[1], data->block[0]);
                 break;
 
         default:
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 28e7b91a4553..9d6b790d4321 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -921,7 +921,14 @@ static int i2c_pxa_probe(struct platform_device *dev)
                 i2c->adap.class = plat->class;
         }
 
-        ret = i2c_add_adapter(&i2c->adap);
+        /*
+         * If "dev->id" is negative we consider it as zero.
+         * The reason to do so is to avoid sysfs names that only make
+         * sense when there are multiple adapters.
+         */
+        i2c->adap.nr = dev->id >= 0 ? dev->id : 0;
+
+        ret = i2c_add_numbered_adapter(&i2c->adap);
         if (ret < 0) {
                 printk(KERN_INFO "I2C: Failed to add bus\n");
                 goto eadapt;
diff --git a/drivers/i2c/busses/i2c-rpx.c b/drivers/i2c/busses/i2c-rpx.c
deleted file mode 100644
index 8764df06f51d..000000000000
--- a/drivers/i2c/busses/i2c-rpx.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Embedded Planet RPX Lite MPC8xx CPM I2C interface.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
- *
- * moved into proper i2c interface;
- * Brad Parker (brad@heeltoe.com)
- *
- * RPX lite specific parts of the i2c interface
- * Update:  There actually isn't anything RPXLite-specific about this module.
- * This should work for most any 8xx board.  The console messages have been 
- * changed to eliminate RPXLite references.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/i2c.h>
-#include <linux/i2c-algo-8xx.h>
-#include <asm/mpc8xx.h>
-#include <asm/commproc.h>
-
-
-static void
-rpx_iic_init(struct i2c_algo_8xx_data *data)
-{
-        volatile cpm8xx_t *cp;
-        volatile immap_t *immap;
-
-        cp = cpmp;      /* Get pointer to Communication Processor */
-        immap = (immap_t *)IMAP_ADDR;   /* and to internal registers */
-
-        data->iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
-
-        /* Check for and use a microcode relocation patch.
-        */
-        if ((data->reloc = data->iip->iic_rpbase))
-                data->iip = (iic_t *)&cp->cp_dpmem[data->iip->iic_rpbase];
-                
-        data->i2c = (i2c8xx_t *)&(immap->im_i2c);
-        data->cp = cp;
-
-        /* Initialize Port B IIC pins.
-        */
-        cp->cp_pbpar |= 0x00000030;
-        cp->cp_pbdir |= 0x00000030;
-        cp->cp_pbodr |= 0x00000030;
-
-        /* Allocate space for two transmit and two receive buffer
-         * descriptors in the DP ram.
-         */
-        data->dp_addr = cpm_dpalloc(sizeof(cbd_t) * 4, 8);
-                
-        /* ptr to i2c area */
-        data->i2c = (i2c8xx_t *)&(((immap_t *)IMAP_ADDR)->im_i2c);
-}
-
-static int rpx_install_isr(int irq, void (*func)(void *), void *data)
-{
-        /* install interrupt handler */
-        cpm_install_handler(irq, func, data);
-
-        return 0;
-}
-
-static struct i2c_algo_8xx_data rpx_data = {
-        .setisr = rpx_install_isr
-};
-
-static struct i2c_adapter rpx_ops = {
-        .owner          = THIS_MODULE,
-        .name           = "m8xx",
-        .id             = I2C_HW_MPC8XX_EPON,
-        .algo_data      = &rpx_data,
-};
-
-int __init i2c_rpx_init(void)
-{
-        printk(KERN_INFO "i2c-rpx: i2c MPC8xx driver\n");
-
-        /* reset hardware to sane state */
-        rpx_iic_init(&rpx_data);
-
-        if (i2c_8xx_add_bus(&rpx_ops) < 0) {
-                printk(KERN_ERR "i2c-rpx: Unable to register with I2C\n");
-                return -ENODEV;
-        }
-
-        return 0;
-}
-
-void __exit i2c_rpx_exit(void)
-{
-        i2c_8xx_del_bus(&rpx_ops);
-}
-
-MODULE_AUTHOR("Dan Malek <dmalek@jlc.net>");
-MODULE_DESCRIPTION("I2C-Bus adapter routines for MPC8xx boards");
-
-module_init(i2c_rpx_init);
-module_exit(i2c_rpx_exit);
diff --git a/drivers/i2c/busses/i2c-savage4.c b/drivers/i2c/busses/i2c-savage4.c
index b7fb65c30112..8adf4abaa035 100644
--- a/drivers/i2c/busses/i2c-savage4.c
+++ b/drivers/i2c/busses/i2c-savage4.c
@@ -25,8 +25,6 @@
 /* This interfaces to the I2C bus of the Savage4 to gain access to
    the BT869 and possibly other I2C devices. The DDC bus is not
    yet supported because its register is not memory-mapped.
-   However we leave the DDC code here, commented out, to make
-   it easier to add later.
 */
 
 #include <linux/kernel.h>
@@ -37,36 +35,19 @@
 #include <linux/i2c-algo-bit.h>
 #include <asm/io.h>
 
-/* 3DFX defines */
-#define PCI_CHIP_SAVAGE3D       0x8A20
-#define PCI_CHIP_SAVAGE3D_MV    0x8A21
+/* device IDs */
 #define PCI_CHIP_SAVAGE4        0x8A22
 #define PCI_CHIP_SAVAGE2000     0x9102
-#define PCI_CHIP_PROSAVAGE_PM   0x8A25
-#define PCI_CHIP_PROSAVAGE_KM   0x8A26
-#define PCI_CHIP_SAVAGE_MX_MV   0x8c10
-#define PCI_CHIP_SAVAGE_MX      0x8c11
-#define PCI_CHIP_SAVAGE_IX_MV   0x8c12
-#define PCI_CHIP_SAVAGE_IX      0x8c13
 
 #define REG                     0xff20  /* Serial Port 1 Register */
 
 /* bit locations in the register */
-#define DDC_ENAB                0x00040000
-#define DDC_SCL_OUT             0x00080000
-#define DDC_SDA_OUT             0x00100000
-#define DDC_SCL_IN              0x00200000
-#define DDC_SDA_IN              0x00400000
 #define I2C_ENAB                0x00000020
 #define I2C_SCL_OUT             0x00000001
 #define I2C_SDA_OUT             0x00000002
 #define I2C_SCL_IN              0x00000008
 #define I2C_SDA_IN              0x00000010
 
-/* initialization states */
-#define INIT2                   0x20
-#define INIT3                   0x04
-
 /* delays */
 #define CYCLE_DELAY             10
 #define TIMEOUT                 (HZ / 2)
diff --git a/drivers/i2c/busses/i2c-sis5595.c b/drivers/i2c/busses/i2c-sis5595.c
index a6feed449dbe..283769cecee2 100644
--- a/drivers/i2c/busses/i2c-sis5595.c
+++ b/drivers/i2c/busses/i2c-sis5595.c
@@ -129,6 +129,7 @@ MODULE_PARM_DESC(force_addr, "Initialize the base address of the i2c controller"
 
 static struct pci_driver sis5595_driver;
 static unsigned short sis5595_base;
+static struct pci_dev *sis5595_pdev;
 
 static u8 sis5595_read(u8 reg)
 {
@@ -379,6 +380,8 @@ MODULE_DEVICE_TABLE (pci, sis5595_ids);
 
 static int __devinit sis5595_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
+        int err;
+
         if (sis5595_setup(dev)) {
                 dev_err(&dev->dev, "SIS5595 not detected, module not inserted.\n");
                 return -ENODEV;
@@ -389,20 +392,24 @@ static int __devinit sis5595_probe(struct pci_dev *dev, const struct pci_device_
 
         sprintf(sis5595_adapter.name, "SMBus SIS5595 adapter at %04x",
                 sis5595_base + SMB_INDEX);
-        return i2c_add_adapter(&sis5595_adapter);
-}
+        err = i2c_add_adapter(&sis5595_adapter);
+        if (err) {
+                release_region(sis5595_base + SMB_INDEX, 2);
+                return err;
+        }
 
-static void __devexit sis5595_remove(struct pci_dev *dev)
-{
-        i2c_del_adapter(&sis5595_adapter);
-        release_region(sis5595_base + SMB_INDEX, 2);
+        /* Always return failure here.  This is to allow other drivers to bind
+         * to this pci device.  We don't really want to have control over the
+         * pci device, we only wanted to read as few register values from it.
+         */
+        sis5595_pdev =  pci_dev_get(dev);
+        return -ENODEV;
 }
 
 static struct pci_driver sis5595_driver = {
         .name           = "sis5595_smbus",
         .id_table       = sis5595_ids,
         .probe          = sis5595_probe,
-        .remove         = __devexit_p(sis5595_remove),
 };
 
 static int __init i2c_sis5595_init(void)
@@ -413,6 +420,12 @@ static int __init i2c_sis5595_init(void)
 static void __exit i2c_sis5595_exit(void)
 {
         pci_unregister_driver(&sis5595_driver);
+        if (sis5595_pdev) {
+                i2c_del_adapter(&sis5595_adapter);
+                release_region(sis5595_base + SMB_INDEX, 2);
+                pci_dev_put(sis5595_pdev);
+                sis5595_pdev = NULL;
+        }
 }
 
 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
diff --git a/drivers/i2c/busses/i2c-taos-evm.c b/drivers/i2c/busses/i2c-taos-evm.c
new file mode 100644
index 000000000000..1b0cfd5472fd
--- /dev/null
+++ b/drivers/i2c/busses/i2c-taos-evm.c
@@ -0,0 +1,330 @@
+/*
+ * Driver for the TAOS evaluation modules
+ * These devices include an I2C master which can be controlled over the
+ * serial port.
+ *
+ * Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/serio.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+
+#define TAOS_BUFFER_SIZE        63
+
+#define TAOS_STATE_INIT         0
+#define TAOS_STATE_IDLE         1
+#define TAOS_STATE_SEND         2
+#define TAOS_STATE_RECV         3
+
+#define TAOS_CMD_RESET          0x12
+
+static DECLARE_WAIT_QUEUE_HEAD(wq);
+
+struct taos_data {
+        struct i2c_adapter adapter;
+        struct i2c_client *client;
+        int state;
+        u8 addr;                /* last used address */
+        unsigned char buffer[TAOS_BUFFER_SIZE];
+        unsigned int pos;       /* position inside the buffer */
+};
+
+/* TAOS TSL2550 EVM */
+static struct i2c_board_info tsl2550_info = {
+        I2C_BOARD_INFO("tsl2550", 0x39),
+        .type   = "tsl2550",
+};
+
+/* Instantiate i2c devices based on the adapter name */
+static struct i2c_client *taos_instantiate_device(struct i2c_adapter *adapter)
+{
+        if (!strncmp(adapter->name, "TAOS TSL2550 EVM", 16)) {
+                dev_info(&adapter->dev, "Instantiating device %s at 0x%02x\n",
+                        tsl2550_info.driver_name, tsl2550_info.addr);
+                return i2c_new_device(adapter, &tsl2550_info);
+        }
+
+        return NULL;
+}
+
+static int taos_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
+                           unsigned short flags, char read_write, u8 command,
+                           int size, union i2c_smbus_data *data)
+{
+        struct serio *serio = adapter->algo_data;
+        struct taos_data *taos = serio_get_drvdata(serio);
+        char *p;
+
+        /* Encode our transaction. "@" is for the device address, "$" for the
+           SMBus command and "#" for the data. */
+        p = taos->buffer;
+
+        /* The device remembers the last used address, no need to send it
+           again if it's the same */
+        if (addr != taos->addr)
+                p += sprintf(p, "@%02X", addr);
+
+        switch (size) {
+        case I2C_SMBUS_BYTE:
+                if (read_write == I2C_SMBUS_WRITE)
+                        sprintf(p, "$#%02X", command);
+                else
+                        sprintf(p, "$");
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                if (read_write == I2C_SMBUS_WRITE)
+                        sprintf(p, "$%02X#%02X", command, data->byte);
+                else
+                        sprintf(p, "$%02X", command);
+                break;
+        default:
+                dev_dbg(&adapter->dev, "Unsupported transaction size %d\n",
+                        size);
+                return -EINVAL;
+        }
+
+        /* Send the transaction to the TAOS EVM */
+        dev_dbg(&adapter->dev, "Command buffer: %s\n", taos->buffer);
+        taos->pos = 0;
+        taos->state = TAOS_STATE_SEND;
+        serio_write(serio, taos->buffer[0]);
+        wait_event_interruptible_timeout(wq, taos->state == TAOS_STATE_IDLE,
+                                         msecs_to_jiffies(250));
+        if (taos->state != TAOS_STATE_IDLE) {
+                dev_err(&adapter->dev, "Transaction failed "
+                        "(state=%d, pos=%d)\n", taos->state, taos->pos);
+                taos->addr = 0;
+                return -EIO;
+        }
+        taos->addr = addr;
+
+        /* Start the transaction and read the answer */
+        taos->pos = 0;
+        taos->state = TAOS_STATE_RECV;
+        serio_write(serio, read_write == I2C_SMBUS_WRITE ? '>' : '<');
+        wait_event_interruptible_timeout(wq, taos->state == TAOS_STATE_IDLE,
+                                         msecs_to_jiffies(150));
+        if (taos->state != TAOS_STATE_IDLE
+         || taos->pos != 6) {
+                dev_err(&adapter->dev, "Transaction timeout (pos=%d)\n",
+                        taos->pos);
+                return -EIO;
+        }
+        dev_dbg(&adapter->dev, "Answer buffer: %s\n", taos->buffer);
+
+        /* Interpret the returned string */
+        p = taos->buffer + 2;
+        p[3] = '\0';
+        if (!strcmp(p, "NAK"))
+                return -ENODEV;
+
+        if (read_write == I2C_SMBUS_WRITE) {
+                if (!strcmp(p, "ACK"))
+                        return 0;
+        } else {
+                if (p[0] == 'x') {
+                        data->byte = simple_strtol(p + 1, NULL, 16);
+                        return 0;
+                }
+        }
+
+        return -EIO;
+}
+
+static u32 taos_smbus_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA;
+}
+
+static const struct i2c_algorithm taos_algorithm = {
+        .smbus_xfer     = taos_smbus_xfer,
+        .functionality  = taos_smbus_func,
+};
+
+static irqreturn_t taos_interrupt(struct serio *serio, unsigned char data,
+                                  unsigned int flags)
+{
+        struct taos_data *taos = serio_get_drvdata(serio);
+
+        switch (taos->state) {
+        case TAOS_STATE_INIT:
+                taos->buffer[taos->pos++] = data;
+                if (data == ':'
+                 || taos->pos == TAOS_BUFFER_SIZE - 1) {
+                        taos->buffer[taos->pos] = '\0';
+                        taos->state = TAOS_STATE_IDLE;
+                        wake_up_interruptible(&wq);
+                }
+                break;
+        case TAOS_STATE_SEND:
+                if (taos->buffer[++taos->pos])
+                        serio_write(serio, taos->buffer[taos->pos]);
+                else {
+                        taos->state = TAOS_STATE_IDLE;
+                        wake_up_interruptible(&wq);
+                }
+                break;
+        case TAOS_STATE_RECV:
+                taos->buffer[taos->pos++] = data;
+                if (data == ']') {
+                        taos->buffer[taos->pos] = '\0';
+                        taos->state = TAOS_STATE_IDLE;
+                        wake_up_interruptible(&wq);
+                }
+                break;
+        }
+
+        return IRQ_HANDLED;
+}
+
+/* Extract the adapter name from the buffer received after reset.
+   The buffer is modified and a pointer inside the buffer is returned. */
+static char *taos_adapter_name(char *buffer)
+{
+        char *start, *end;
+
+        start = strstr(buffer, "TAOS ");
+        if (!start)
+                return NULL;
+
+        end = strchr(start, '\r');
+        if (!end)
+                return NULL;
+        *end = '\0';
+
+        return start;
+}
+
+static int taos_connect(struct serio *serio, struct serio_driver *drv)
+{
+        struct taos_data *taos;
+        struct i2c_adapter *adapter;
+        char *name;
+        int err;
+
+        taos = kzalloc(sizeof(struct taos_data), GFP_KERNEL);
+        if (!taos) {
+                err = -ENOMEM;
+                goto exit;
+        }
+        taos->state = TAOS_STATE_INIT;
+        serio_set_drvdata(serio, taos);
+
+        err = serio_open(serio, drv);
+        if (err)
+                goto exit_kfree;
+
+        adapter = &taos->adapter;
+        adapter->owner = THIS_MODULE;
+        adapter->algo = &taos_algorithm;
+        adapter->algo_data = serio;
+        adapter->dev.parent = &serio->dev;
+
+        /* Reset the TAOS evaluation module to identify it */
+        serio_write(serio, TAOS_CMD_RESET);
+        wait_event_interruptible_timeout(wq, taos->state == TAOS_STATE_IDLE,
+                                         msecs_to_jiffies(2000));
+
+        if (taos->state != TAOS_STATE_IDLE) {
+                err = -ENODEV;
+                dev_dbg(&serio->dev, "TAOS EVM reset failed (state=%d, "
+                        "pos=%d)\n", taos->state, taos->pos);
+                goto exit_close;
+        }
+
+        name = taos_adapter_name(taos->buffer);
+        if (!name) {
+                err = -ENODEV;
+                dev_err(&serio->dev, "TAOS EVM identification failed\n");
+                goto exit_close;
+        }
+        strlcpy(adapter->name, name, sizeof(adapter->name));
+
+        err = i2c_add_adapter(adapter);
+        if (err)
+                goto exit_close;
+        dev_dbg(&serio->dev, "Connected to TAOS EVM\n");
+
+        taos->client = taos_instantiate_device(adapter);
+        return 0;
+
+ exit_close:
+        serio_close(serio);
+ exit_kfree:
+        serio_set_drvdata(serio, NULL);
+        kfree(taos);
+ exit:
+        return err;
+}
+
+static void taos_disconnect(struct serio *serio)
+{
+        struct taos_data *taos = serio_get_drvdata(serio);
+
+        if (taos->client)
+                i2c_unregister_device(taos->client);
+        i2c_del_adapter(&taos->adapter);
+        serio_close(serio);
+        serio_set_drvdata(serio, NULL);
+        kfree(taos);
+
+        dev_dbg(&serio->dev, "Disconnected from TAOS EVM\n");
+}
+
+static struct serio_device_id taos_serio_ids[] = {
+        {
+                .type   = SERIO_RS232,
+                .proto  = SERIO_TAOSEVM,
+                .id     = SERIO_ANY,
+                .extra  = SERIO_ANY,
+        },
+        { 0 }
+};
+MODULE_DEVICE_TABLE(serio, taos_serio_ids);
+
+static struct serio_driver taos_drv = {
+        .driver         = {
+                .name   = "taos-evm",
+        },
+        .description    = "TAOS evaluation module driver",
+        .id_table       = taos_serio_ids,
+        .connect        = taos_connect,
+        .disconnect     = taos_disconnect,
+        .interrupt      = taos_interrupt,
+};
+
+static int __init taos_init(void)
+{
+        return serio_register_driver(&taos_drv);
+}
+
+static void __exit taos_exit(void)
+{
+        serio_unregister_driver(&taos_drv);
+}
+
+MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
+MODULE_DESCRIPTION("TAOS evaluation module driver");
+MODULE_LICENSE("GPL");
+
+module_init(taos_init);
+module_exit(taos_exit);
diff --git a/drivers/i2c/busses/i2c-viapro.c b/drivers/i2c/busses/i2c-viapro.c
index 7a2bc06304fc..a0f7e4a303b5 100644
--- a/drivers/i2c/busses/i2c-viapro.c
+++ b/drivers/i2c/busses/i2c-viapro.c
@@ -235,7 +235,7 @@ static s32 vt596_access(struct i2c_adapter *adap, u16 addr,
                 if (!(vt596_features & FEATURE_I2CBLOCK))
                         goto exit_unsupported;
                 if (read_write == I2C_SMBUS_READ)
-                        outb_p(I2C_SMBUS_BLOCK_MAX, SMBHSTDAT0);
+                        outb_p(data->block[0], SMBHSTDAT0);
                 /* Fall through */
         case I2C_SMBUS_BLOCK_DATA:
                 outb_p(command, SMBHSTCMD);
diff --git a/drivers/i2c/busses/scx200_acb.c b/drivers/i2c/busses/scx200_acb.c
index 0d6bd4f7b7fa..e6c4a2b762ec 100644
--- a/drivers/i2c/busses/scx200_acb.c
+++ b/drivers/i2c/busses/scx200_acb.c
@@ -310,8 +310,6 @@ static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
                 break;
 
         case I2C_SMBUS_I2C_BLOCK_DATA:
-                if (rw == I2C_SMBUS_READ)
-                        data->block[0] = I2C_SMBUS_BLOCK_MAX; /* For now */
                 len = data->block[0];
                 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
                         return -EINVAL;
@@ -388,7 +386,7 @@ static const struct i2c_algorithm scx200_acb_algorithm = {
 };
 
 static struct scx200_acb_iface *scx200_acb_list;
-static DECLARE_MUTEX(scx200_acb_list_mutex);
+static DEFINE_MUTEX(scx200_acb_list_mutex);
 
 static __init int scx200_acb_probe(struct scx200_acb_iface *iface)
 {
@@ -472,10 +470,10 @@ static int __init scx200_acb_create(struct scx200_acb_iface *iface)
                 return -ENODEV;
         }
 
-        down(&scx200_acb_list_mutex);
+        mutex_lock(&scx200_acb_list_mutex);
         iface->next = scx200_acb_list;
         scx200_acb_list = iface;
-        up(&scx200_acb_list_mutex);
+        mutex_unlock(&scx200_acb_list_mutex);
 
         return 0;
 }
@@ -633,10 +631,10 @@ static void __exit scx200_acb_cleanup(void)
 {
         struct scx200_acb_iface *iface;
 
-        down(&scx200_acb_list_mutex);
+        mutex_lock(&scx200_acb_list_mutex);
         while ((iface = scx200_acb_list) != NULL) {
                 scx200_acb_list = iface->next;
-                up(&scx200_acb_list_mutex);
+                mutex_unlock(&scx200_acb_list_mutex);
 
                 i2c_del_adapter(&iface->adapter);
 
@@ -648,9 +646,9 @@ static void __exit scx200_acb_cleanup(void)
                         release_region(iface->base, 8);
 
                 kfree(iface);
-                down(&scx200_acb_list_mutex);
+                mutex_lock(&scx200_acb_list_mutex);
         }
-        up(&scx200_acb_list_mutex);
+        mutex_unlock(&scx200_acb_list_mutex);
 }
 
 module_init(scx200_acb_init);
diff --git a/drivers/i2c/chips/Kconfig b/drivers/i2c/chips/Kconfig
index ea085a006ead..3944e889cb21 100644
--- a/drivers/i2c/chips/Kconfig
+++ b/drivers/i2c/chips/Kconfig
@@ -5,7 +5,7 @@
 menu "Miscellaneous I2C Chip support"
 
 config SENSORS_DS1337
-        tristate "Dallas Semiconductor DS1337 and DS1339 Real Time Clock"
+        tristate "Dallas DS1337 and DS1339 Real Time Clock (DEPRECATED)"
         depends on EXPERIMENTAL
         help
           If you say yes here you get support for Dallas Semiconductor
@@ -14,8 +14,11 @@ config SENSORS_DS1337
           This driver can also be built as a module.  If so, the module
           will be called ds1337.
 
+          This driver is deprecated and will be dropped soon. Use
+          rtc-ds1307 instead.
+
 config SENSORS_DS1374
-        tristate "Maxim/Dallas Semiconductor DS1374 Real Time Clock"
+        tristate "Dallas DS1374 Real Time Clock (DEPRECATED)"
         depends on EXPERIMENTAL
         help
           If you say yes here you get support for Dallas Semiconductor
@@ -24,6 +27,19 @@ config SENSORS_DS1374
           This driver can also be built as a module.  If so, the module
           will be called ds1374.
 
+          This driver is deprecated and will be dropped soon. Use
+          rtc-ds1374 instead.
+
+config DS1682
+        tristate "Dallas DS1682 Total Elapsed Time Recorder with Alarm"
+        depends on EXPERIMENTAL
+        help
+          If you say yes here you get support for Dallas Semiconductor
+          DS1682 Total Elapsed Time Recorder.
+
+          This driver can also be built as a module.  If so, the module
+          will be called ds1682.
+
 config SENSORS_EEPROM
         tristate "EEPROM reader"
         depends on EXPERIMENTAL
@@ -101,7 +117,7 @@ config TPS65010
           will be called tps65010.
 
 config SENSORS_M41T00
-        tristate "ST M41T00 RTC chip"
+        tristate "ST M41T00 RTC chip (DEPRECATED)"
         depends on PPC32
         help
           If you say yes here you get support for the ST M41T00 RTC chip.
@@ -109,6 +125,9 @@ config SENSORS_M41T00
           This driver can also be built as a module.  If so, the module
           will be called m41t00.
 
+          This driver is deprecated and will be dropped soon. Use
+          rtc-ds1307 or rtc-m41t80 instead.
+
 config SENSORS_MAX6875
         tristate "Maxim MAX6875 Power supply supervisor"
         depends on EXPERIMENTAL
@@ -124,4 +143,14 @@ config SENSORS_MAX6875
           This driver can also be built as a module.  If so, the module
           will be called max6875.
 
+config SENSORS_TSL2550
+        tristate "Taos TSL2550 ambient light sensor"
+        depends on EXPERIMENTAL
+        help
+          If you say yes here you get support for the Taos TSL2550
+          ambient light sensor.
+
+          This driver can also be built as a module.  If so, the module
+          will be called tsl2550.
+
 endmenu
diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 779868ef2e26..d8cbeb3f4b63 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -4,6 +4,7 @@
 
 obj-$(CONFIG_SENSORS_DS1337)    += ds1337.o
 obj-$(CONFIG_SENSORS_DS1374)    += ds1374.o
+obj-$(CONFIG_DS1682)            += ds1682.o
 obj-$(CONFIG_SENSORS_EEPROM)    += eeprom.o
 obj-$(CONFIG_SENSORS_MAX6875)   += max6875.o
 obj-$(CONFIG_SENSORS_M41T00)    += m41t00.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_SENSORS_PCF8574)	+= pcf8574.o
 obj-$(CONFIG_SENSORS_PCF8591)   += pcf8591.o
 obj-$(CONFIG_ISP1301_OMAP)      += isp1301_omap.o
 obj-$(CONFIG_TPS65010)          += tps65010.o
+obj-$(CONFIG_SENSORS_TSL2550)   += tsl2550.o
 
 ifeq ($(CONFIG_I2C_DEBUG_CHIP),y)
 EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/i2c/chips/ds1682.c b/drivers/i2c/chips/ds1682.c
new file mode 100644
index 000000000000..25fd4676fb17
--- /dev/null
+++ b/drivers/i2c/chips/ds1682.c
@@ -0,0 +1,259 @@
+/*
+ * Dallas Semiconductor DS1682 Elapsed Time Recorder device driver
+ *
+ * Written by: Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright (C) 2007 Secret Lab Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The DS1682 elapsed timer recorder is a simple device that implements
+ * one elapsed time counter, one event counter, an alarm signal and 10
+ * bytes of general purpose EEPROM.
+ *
+ * This driver provides access to the DS1682 counters and user data via
+ * the sysfs.  The following attributes are added to the device node:
+ *     elapsed_time (u32): Total elapsed event time in ms resolution
+ *     alarm_time (u32): When elapsed time exceeds the value in alarm_time,
+ *                       then the alarm pin is asserted.
+ *     event_count (u16): number of times the event pin has gone low.
+ *     eeprom (u8[10]): general purpose EEPROM
+ *
+ * Counter registers and user data are both read/write unless the device
+ * has been write protected.  This driver does not support turning off write
+ * protection.  Once write protection is turned on, it is impossible to
+ * turn it off again, so I have left the feature out of this driver to avoid
+ * accidental enabling, but it is trivial to add write protect support.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/sysfs.h>
+#include <linux/ctype.h>
+#include <linux/hwmon-sysfs.h>
+
+/* Device registers */
+#define DS1682_REG_CONFIG               0x00
+#define DS1682_REG_ALARM                0x01
+#define DS1682_REG_ELAPSED              0x05
+#define DS1682_REG_EVT_CNTR             0x09
+#define DS1682_REG_EEPROM               0x0b
+#define DS1682_REG_RESET                0x1d
+#define DS1682_REG_WRITE_DISABLE        0x1e
+#define DS1682_REG_WRITE_MEM_DISABLE    0x1f
+
+#define DS1682_EEPROM_SIZE              10
+
+/*
+ * Generic counter attributes
+ */
+static ssize_t ds1682_show(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
+        struct i2c_client *client = to_i2c_client(dev);
+        __le32 val = 0;
+        int rc;
+
+        dev_dbg(dev, "ds1682_show() called on %s\n", attr->attr.name);
+
+        /* Read the register */
+        rc = i2c_smbus_read_i2c_block_data(client, sattr->index, sattr->nr,
+                                           (u8 *) & val);
+        if (rc < 0)
+                return -EIO;
+
+        /* Special case: the 32 bit regs are time values with 1/4s
+         * resolution, scale them up to milliseconds */
+        if (sattr->nr == 4)
+                return sprintf(buf, "%llu\n", ((u64) le32_to_cpu(val)) * 250);
+
+        /* Format the output string and return # of bytes */
+        return sprintf(buf, "%li\n", (long)le32_to_cpu(val));
+}
+
+static ssize_t ds1682_store(struct device *dev, struct device_attribute *attr,
+                            const char *buf, size_t count)
+{
+        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
+        struct i2c_client *client = to_i2c_client(dev);
+        char *endp;
+        u64 val;
+        __le32 val_le;
+        int rc;
+
+        dev_dbg(dev, "ds1682_store() called on %s\n", attr->attr.name);
+
+        /* Decode input */
+        val = simple_strtoull(buf, &endp, 0);
+        if (buf == endp) {
+                dev_dbg(dev, "input string not a number\n");
+                return -EINVAL;
+        }
+
+        /* Special case: the 32 bit regs are time values with 1/4s
+         * resolution, scale input down to quarter-seconds */
+        if (sattr->nr == 4)
+                do_div(val, 250);
+
+        /* write out the value */
+        val_le = cpu_to_le32(val);
+        rc = i2c_smbus_write_i2c_block_data(client, sattr->index, sattr->nr,
+                                            (u8 *) & val_le);
+        if (rc < 0) {
+                dev_err(dev, "register write failed; reg=0x%x, size=%i\n",
+                        sattr->index, sattr->nr);
+                return -EIO;
+        }
+
+        return count;
+}
+
+/*
+ * Simple register attributes
+ */
+static SENSOR_DEVICE_ATTR_2(elapsed_time, S_IRUGO | S_IWUSR, ds1682_show,
+                            ds1682_store, 4, DS1682_REG_ELAPSED);
+static SENSOR_DEVICE_ATTR_2(alarm_time, S_IRUGO | S_IWUSR, ds1682_show,
+                            ds1682_store, 4, DS1682_REG_ALARM);
+static SENSOR_DEVICE_ATTR_2(event_count, S_IRUGO | S_IWUSR, ds1682_show,
+                            ds1682_store, 2, DS1682_REG_EVT_CNTR);
+
+static const struct attribute_group ds1682_group = {
+        .attrs = (struct attribute *[]) {
+                &sensor_dev_attr_elapsed_time.dev_attr.attr,
+                &sensor_dev_attr_alarm_time.dev_attr.attr,
+                &sensor_dev_attr_event_count.dev_attr.attr,
+                NULL,
+        },
+};
+
+/*
+ * User data attribute
+ */
+static ssize_t ds1682_eeprom_read(struct kobject *kobj, char *buf, loff_t off,
+                                  size_t count)
+{
+        struct i2c_client *client = kobj_to_i2c_client(kobj);
+        int rc;
+
+        dev_dbg(&client->dev, "ds1682_eeprom_read(p=%p, off=%lli, c=%zi)\n",
+                buf, off, count);
+
+        if (off >= DS1682_EEPROM_SIZE)
+                return 0;
+
+        if (off + count > DS1682_EEPROM_SIZE)
+                count = DS1682_EEPROM_SIZE - off;
+
+        rc = i2c_smbus_read_i2c_block_data(client, DS1682_REG_EEPROM + off,
+                                           count, buf);
+        if (rc < 0)
+                return -EIO;
+
+        return count;
+}
+
+static ssize_t ds1682_eeprom_write(struct kobject *kobj, char *buf, loff_t off,
+                                   size_t count)
+{
+        struct i2c_client *client = kobj_to_i2c_client(kobj);
+
+        dev_dbg(&client->dev, "ds1682_eeprom_write(p=%p, off=%lli, c=%zi)\n",
+                buf, off, count);
+
+        if (off >= DS1682_EEPROM_SIZE)
+                return -ENOSPC;
+
+        if (off + count > DS1682_EEPROM_SIZE)
+                count = DS1682_EEPROM_SIZE - off;
+
+        /* Write out to the device */
+        if (i2c_smbus_write_i2c_block_data(client, DS1682_REG_EEPROM + off,
+                                           count, buf) < 0)
+                return -EIO;
+
+        return count;
+}
+
+static struct bin_attribute ds1682_eeprom_attr = {
+        .attr = {
+                .name = "eeprom",
+                .mode = S_IRUGO | S_IWUSR,
+                .owner = THIS_MODULE,
+        },
+        .size = DS1682_EEPROM_SIZE,
+        .read = ds1682_eeprom_read,
+        .write = ds1682_eeprom_write,
+};
+
+/*
+ * Called when a ds1682 device is matched with this driver
+ */
+static int ds1682_probe(struct i2c_client *client)
+{
+        int rc;
+
+        if (!i2c_check_functionality(client->adapter,
+                                     I2C_FUNC_SMBUS_I2C_BLOCK)) {
+                dev_err(&client->dev, "i2c bus does not support the ds1682\n");
+                rc = -ENODEV;
+                goto exit;
+        }
+
+        rc = sysfs_create_group(&client->dev.kobj, &ds1682_group);
+        if (rc)
+                goto exit;
+
+        rc = sysfs_create_bin_file(&client->dev.kobj, &ds1682_eeprom_attr);
+        if (rc)
+                goto exit_bin_attr;
+
+        return 0;
+
+ exit_bin_attr:
+        sysfs_remove_group(&client->dev.kobj, &ds1682_group);
+ exit:
+        return rc;
+}
+
+static int ds1682_remove(struct i2c_client *client)
+{
+        sysfs_remove_bin_file(&client->dev.kobj, &ds1682_eeprom_attr);
+        sysfs_remove_group(&client->dev.kobj, &ds1682_group);
+        return 0;
+}
+
+static struct i2c_driver ds1682_driver = {
+        .driver = {
+                .name = "ds1682",
+        },
+        .probe = ds1682_probe,
+        .remove = ds1682_remove,
+};
+
+static int __init ds1682_init(void)
+{
+        return i2c_add_driver(&ds1682_driver);
+}
+
+static void __exit ds1682_exit(void)
+{
+        i2c_del_driver(&ds1682_driver);
+}
+
+MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
+MODULE_DESCRIPTION("DS1682 Elapsed Time Indicator driver");
+MODULE_LICENSE("GPL");
+
+module_init(ds1682_init);
+module_exit(ds1682_exit);
diff --git a/drivers/i2c/chips/eeprom.c b/drivers/i2c/chips/eeprom.c
index bfce13c8f1ff..48f857ae8748 100644
--- a/drivers/i2c/chips/eeprom.c
+++ b/drivers/i2c/chips/eeprom.c
@@ -88,8 +88,10 @@ static void eeprom_update_client(struct i2c_client *client, u8 slice)
                 dev_dbg(&client->dev, "Starting eeprom update, slice %u\n", slice);
 
                 if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
-                        for (i = slice << 5; i < (slice + 1) << 5; i += I2C_SMBUS_BLOCK_MAX)
-                                if (i2c_smbus_read_i2c_block_data(client, i, data->data + i) != I2C_SMBUS_BLOCK_MAX)
+                        for (i = slice << 5; i < (slice + 1) << 5; i += 32)
+                                if (i2c_smbus_read_i2c_block_data(client, i,
+                                                        32, data->data + i)
+                                                        != 32)
                                         goto exit;
                 } else {
                         if (i2c_smbus_write_byte(client, slice << 5)) {
diff --git a/drivers/i2c/chips/max6875.c b/drivers/i2c/chips/max6875.c
index 76645c142977..e9e9e5171b53 100644
--- a/drivers/i2c/chips/max6875.c
+++ b/drivers/i2c/chips/max6875.c
@@ -106,6 +106,7 @@ static void max6875_update_slice(struct i2c_client *client, int slice)
                                             I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
                         if (i2c_smbus_read_i2c_block_data(client,
                                                           MAX6875_CMD_BLK_READ,
+                                                          SLICE_SIZE,
                                                           buf) != SLICE_SIZE) {
                                 goto exit_up;
                         }
diff --git a/drivers/i2c/chips/tsl2550.c b/drivers/i2c/chips/tsl2550.c
new file mode 100644
index 000000000000..3de4b19ba08f
--- /dev/null
+++ b/drivers/i2c/chips/tsl2550.c
@@ -0,0 +1,460 @@
+/*
+ *  tsl2550.c - Linux kernel modules for ambient light sensor
+ *
+ *  Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ *  Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+
+#define TSL2550_DRV_NAME        "tsl2550"
+#define DRIVER_VERSION          "1.1.1"
+
+/*
+ * Defines
+ */
+
+#define TSL2550_POWER_DOWN              0x00
+#define TSL2550_POWER_UP                0x03
+#define TSL2550_STANDARD_RANGE          0x18
+#define TSL2550_EXTENDED_RANGE          0x1d
+#define TSL2550_READ_ADC0               0x43
+#define TSL2550_READ_ADC1               0x83
+
+/*
+ * Structs
+ */
+
+struct tsl2550_data {
+        struct i2c_client *client;
+        struct mutex update_lock;
+
+        unsigned int power_state : 1;
+        unsigned int operating_mode : 1;
+};
+
+/*
+ * Global data
+ */
+
+static const u8 TSL2550_MODE_RANGE[2] = {
+        TSL2550_STANDARD_RANGE, TSL2550_EXTENDED_RANGE,
+};
+
+/*
+ * Management functions
+ */
+
+static int tsl2550_set_operating_mode(struct i2c_client *client, int mode)
+{
+        struct tsl2550_data *data = i2c_get_clientdata(client);
+
+        int ret = i2c_smbus_write_byte(client, TSL2550_MODE_RANGE[mode]);
+
+        data->operating_mode = mode;
+
+        return ret;
+}
+
+static int tsl2550_set_power_state(struct i2c_client *client, int state)
+{
+        struct tsl2550_data *data = i2c_get_clientdata(client);
+        int ret;
+
+        if (state == 0)
+                ret = i2c_smbus_write_byte(client, TSL2550_POWER_DOWN);
+        else {
+                ret = i2c_smbus_write_byte(client, TSL2550_POWER_UP);
+
+                /* On power up we should reset operating mode also... */
+                tsl2550_set_operating_mode(client, data->operating_mode);
+        }
+
+        data->power_state = state;
+
+        return ret;
+}
+
+static int tsl2550_get_adc_value(struct i2c_client *client, u8 cmd)
+{
+        unsigned long end;
+        int loop = 0, ret = 0;
+
+        /*
+         * Read ADC channel waiting at most 400ms (see data sheet for further
+         * info).
+         * To avoid long busy wait we spin for few milliseconds then
+         * start sleeping.
+         */
+        end = jiffies + msecs_to_jiffies(400);
+        while (time_before(jiffies, end)) {
+                i2c_smbus_write_byte(client, cmd);
+
+                if (loop++ < 5)
+                        mdelay(1);
+                else
+                        msleep(1);
+
+                ret = i2c_smbus_read_byte(client);
+                if (ret < 0)
+                        return ret;
+                else if (ret & 0x0080)
+                        break;
+        }
+        if (!(ret & 0x80))
+                return -EIO;
+        return ret & 0x7f;      /* remove the "valid" bit */
+}
+
+/*
+ * LUX calculation
+ */
+
+#define TSL2550_MAX_LUX         1846
+
+static const u8 ratio_lut[] = {
+        100, 100, 100, 100, 100, 100, 100, 100,
+        100, 100, 100, 100, 100, 100, 99, 99,
+        99, 99, 99, 99, 99, 99, 99, 99,
+        99, 99, 99, 98, 98, 98, 98, 98,
+        98, 98, 97, 97, 97, 97, 97, 96,
+        96, 96, 96, 95, 95, 95, 94, 94,
+        93, 93, 93, 92, 92, 91, 91, 90,
+        89, 89, 88, 87, 87, 86, 85, 84,
+        83, 82, 81, 80, 79, 78, 77, 75,
+        74, 73, 71, 69, 68, 66, 64, 62,
+        60, 58, 56, 54, 52, 49, 47, 44,
+        42, 41, 40, 40, 39, 39, 38, 38,
+        37, 37, 37, 36, 36, 36, 35, 35,
+        35, 35, 34, 34, 34, 34, 33, 33,
+        33, 33, 32, 32, 32, 32, 32, 31,
+        31, 31, 31, 31, 30, 30, 30, 30,
+        30,
+};
+
+static const u16 count_lut[] = {
+        0, 1, 2, 3, 4, 5, 6, 7,
+        8, 9, 10, 11, 12, 13, 14, 15,
+        16, 18, 20, 22, 24, 26, 28, 30,
+        32, 34, 36, 38, 40, 42, 44, 46,
+        49, 53, 57, 61, 65, 69, 73, 77,
+        81, 85, 89, 93, 97, 101, 105, 109,
+        115, 123, 131, 139, 147, 155, 163, 171,
+        179, 187, 195, 203, 211, 219, 227, 235,
+        247, 263, 279, 295, 311, 327, 343, 359,
+        375, 391, 407, 423, 439, 455, 471, 487,
+        511, 543, 575, 607, 639, 671, 703, 735,
+        767, 799, 831, 863, 895, 927, 959, 991,
+        1039, 1103, 1167, 1231, 1295, 1359, 1423, 1487,
+        1551, 1615, 1679, 1743, 1807, 1871, 1935, 1999,
+        2095, 2223, 2351, 2479, 2607, 2735, 2863, 2991,
+        3119, 3247, 3375, 3503, 3631, 3759, 3887, 4015,
+};
+
+/*
+ * This function is described into Taos TSL2550 Designer's Notebook
+ * pages 2, 3.
+ */
+static int tsl2550_calculate_lux(u8 ch0, u8 ch1)
+{
+        unsigned int lux;
+
+        /* Look up count from channel values */
+        u16 c0 = count_lut[ch0];
+        u16 c1 = count_lut[ch1];
+
+        /*
+         * Calculate ratio.
+         * Note: the "128" is a scaling factor
+         */
+        u8 r = 128;
+
+        /* Avoid division by 0 and count 1 cannot be greater than count 0 */
+        if (c0 && (c1 <= c0))
+                r = c1 * 128 / c0;
+        else
+                return -1;
+
+        /* Calculate LUX */
+        lux = ((c0 - c1) * ratio_lut[r]) / 256;
+
+        /* LUX range check */
+        return lux > TSL2550_MAX_LUX ? TSL2550_MAX_LUX : lux;
+}
+
+/*
+ * SysFS support
+ */
+
+static ssize_t tsl2550_show_power_state(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct tsl2550_data *data = i2c_get_clientdata(to_i2c_client(dev));
+
+        return sprintf(buf, "%u\n", data->power_state);
+}
+
+static ssize_t tsl2550_store_power_state(struct device *dev,
+                struct device_attribute *attr, const char *buf, size_t count)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct tsl2550_data *data = i2c_get_clientdata(client);
+        unsigned long val = simple_strtoul(buf, NULL, 10);
+        int ret;
+
+        if (val < 0 || val > 1)
+                return -EINVAL;
+
+        mutex_lock(&data->update_lock);
+        ret = tsl2550_set_power_state(client, val);
+        mutex_unlock(&data->update_lock);
+
+        if (ret < 0)
+                return ret;
+
+        return count;
+}
+
+static DEVICE_ATTR(power_state, S_IWUSR | S_IRUGO,
+                   tsl2550_show_power_state, tsl2550_store_power_state);
+
+static ssize_t tsl2550_show_operating_mode(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct tsl2550_data *data = i2c_get_clientdata(to_i2c_client(dev));
+
+        return sprintf(buf, "%u\n", data->operating_mode);
+}
+
+static ssize_t tsl2550_store_operating_mode(struct device *dev,
+                struct device_attribute *attr, const char *buf, size_t count)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct tsl2550_data *data = i2c_get_clientdata(client);
+        unsigned long val = simple_strtoul(buf, NULL, 10);
+        int ret;
+
+        if (val < 0 || val > 1)
+                return -EINVAL;
+
+        if (data->power_state == 0)
+                return -EBUSY;
+
+        mutex_lock(&data->update_lock);
+        ret = tsl2550_set_operating_mode(client, val);
+        mutex_unlock(&data->update_lock);
+
+        if (ret < 0)
+                return ret;
+
+        return count;
+}
+
+static DEVICE_ATTR(operating_mode, S_IWUSR | S_IRUGO,
+                   tsl2550_show_operating_mode, tsl2550_store_operating_mode);
+
+static ssize_t __tsl2550_show_lux(struct i2c_client *client, char *buf)
+{
+        u8 ch0, ch1;
+        int ret;
+
+        ret = tsl2550_get_adc_value(client, TSL2550_READ_ADC0);
+        if (ret < 0)
+                return ret;
+        ch0 = ret;
+
+        mdelay(1);
+
+        ret = tsl2550_get_adc_value(client, TSL2550_READ_ADC1);
+        if (ret < 0)
+                return ret;
+        ch1 = ret;
+
+        /* Do the job */
+        ret = tsl2550_calculate_lux(ch0, ch1);
+        if (ret < 0)
+                return ret;
+
+        return sprintf(buf, "%d\n", ret);
+}
+
+static ssize_t tsl2550_show_lux1_input(struct device *dev,
+                        struct device_attribute *attr, char *buf)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct tsl2550_data *data = i2c_get_clientdata(client);
+        int ret;
+
+        /* No LUX data if not operational */
+        if (!data->power_state)
+                return -EBUSY;
+
+        mutex_lock(&data->update_lock);
+        ret = __tsl2550_show_lux(client, buf);
+        mutex_unlock(&data->update_lock);
+
+        return ret;
+}
+
+static DEVICE_ATTR(lux1_input, S_IRUGO,
+                   tsl2550_show_lux1_input, NULL);
+
+static struct attribute *tsl2550_attributes[] = {
+        &dev_attr_power_state.attr,
+        &dev_attr_operating_mode.attr,
+        &dev_attr_lux1_input.attr,
+        NULL
+};
+
+static const struct attribute_group tsl2550_attr_group = {
+        .attrs = tsl2550_attributes,
+};
+
+/*
+ * Initialization function
+ */
+
+static int tsl2550_init_client(struct i2c_client *client)
+{
+        struct tsl2550_data *data = i2c_get_clientdata(client);
+        int err;
+
+        /*
+         * Probe the chip. To do so we try to power up the device and then to
+         * read back the 0x03 code
+         */
+        err = i2c_smbus_write_byte(client, TSL2550_POWER_UP);
+        if (err < 0)
+                return err;
+        mdelay(1);
+        if (i2c_smbus_read_byte(client) != TSL2550_POWER_UP)
+                return -ENODEV;
+        data->power_state = 1;
+
+        /* Set the default operating mode */
+        err = i2c_smbus_write_byte(client,
+                                   TSL2550_MODE_RANGE[data->operating_mode]);
+        if (err < 0)
+                return err;
+
+        return 0;
+}
+
+/*
+ * I2C init/probing/exit functions
+ */
+
+static struct i2c_driver tsl2550_driver;
+static int __devinit tsl2550_probe(struct i2c_client *client)
+{
+        struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
+        struct tsl2550_data *data;
+        int *opmode, err = 0;
+
+        if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE)) {
+                err = -EIO;
+                goto exit;
+        }
+
+        data = kzalloc(sizeof(struct tsl2550_data), GFP_KERNEL);
+        if (!data) {
+                err = -ENOMEM;
+                goto exit;
+        }
+        data->client = client;
+        i2c_set_clientdata(client, data);
+
+        /* Check platform data */
+        opmode = client->dev.platform_data;
+        if (opmode) {
+                if (*opmode < 0 || *opmode > 1) {
+                        dev_err(&client->dev, "invalid operating_mode (%d)\n",
+                                        *opmode);
+                        err = -EINVAL;
+                        goto exit_kfree;
+                }
+                data->operating_mode = *opmode;
+        } else
+                data->operating_mode = 0;       /* default mode is standard */
+        dev_info(&client->dev, "%s operating mode\n",
+                        data->operating_mode ? "extended" : "standard");
+
+        mutex_init(&data->update_lock);
+
+        /* Initialize the TSL2550 chip */
+        err = tsl2550_init_client(client);
+        if (err)
+                goto exit_kfree;
+
+        /* Register sysfs hooks */
+        err = sysfs_create_group(&client->dev.kobj, &tsl2550_attr_group);
+        if (err)
+                goto exit_kfree;
+
+        dev_info(&client->dev, "support ver. %s enabled\n", DRIVER_VERSION);
+
+        return 0;
+
+exit_kfree:
+        kfree(data);
+exit:
+        return err;
+}
+
+static int __devexit tsl2550_remove(struct i2c_client *client)
+{
+        sysfs_remove_group(&client->dev.kobj, &tsl2550_attr_group);
+
+        /* Power down the device */
+        tsl2550_set_power_state(client, 0);
+
+        kfree(i2c_get_clientdata(client));
+
+        return 0;
+}
+
+static struct i2c_driver tsl2550_driver = {
+        .driver = {
+                .name   = TSL2550_DRV_NAME,
+                .owner  = THIS_MODULE,
+        },
+        .probe  = tsl2550_probe,
+        .remove = __devexit_p(tsl2550_remove),
+};
+
+static int __init tsl2550_init(void)
+{
+        return i2c_add_driver(&tsl2550_driver);
+}
+
+static void __exit tsl2550_exit(void)
+{
+        i2c_del_driver(&tsl2550_driver);
+}
+
+MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
+MODULE_DESCRIPTION("TSL2550 ambient light sensor driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRIVER_VERSION);
+
+module_init(tsl2550_init);
+module_exit(tsl2550_exit);
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 435925eba437..6971a62397db 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -207,6 +207,7 @@ EXPORT_SYMBOL_GPL(i2c_bus_type);
  * i2c_new_device - instantiate an i2c device for use with a new style driver
  * @adap: the adapter managing the device
  * @info: describes one I2C device; bus_num is ignored
+ * Context: can sleep
  *
  * Create a device to work with a new style i2c driver, where binding is
  * handled through driver model probe()/remove() methods.  This call is not
@@ -255,6 +256,7 @@ EXPORT_SYMBOL_GPL(i2c_new_device);
 /**
  * i2c_unregister_device - reverse effect of i2c_new_device()
  * @client: value returned from i2c_new_device()
+ * Context: can sleep
  */
 void i2c_unregister_device(struct i2c_client *client)
 {
@@ -379,6 +381,7 @@ out_list:
 /**
  * i2c_add_adapter - declare i2c adapter, use dynamic bus number
  * @adapter: the adapter to add
+ * Context: can sleep
  *
  * This routine is used to declare an I2C adapter when its bus number
  * doesn't matter.  Examples: for I2C adapters dynamically added by
@@ -416,6 +419,7 @@ EXPORT_SYMBOL(i2c_add_adapter);
 /**
  * i2c_add_numbered_adapter - declare i2c adapter, use static bus number
  * @adap: the adapter to register (with adap->nr initialized)
+ * Context: can sleep
  *
  * This routine is used to declare an I2C adapter when its bus number
  * matters.  Example: for I2C adapters from system-on-chip CPUs, or
@@ -463,6 +467,14 @@ retry:
 }
 EXPORT_SYMBOL_GPL(i2c_add_numbered_adapter);
 
+/**
+ * i2c_del_adapter - unregister I2C adapter
+ * @adap: the adapter being unregistered
+ * Context: can sleep
+ *
+ * This unregisters an I2C adapter which was previously registered
+ * by @i2c_add_adapter or @i2c_add_numbered_adapter.
+ */
 int i2c_del_adapter(struct i2c_adapter *adap)
 {
         struct list_head  *item, *_n;
@@ -598,6 +610,7 @@ EXPORT_SYMBOL(i2c_register_driver);
 /**
  * i2c_del_driver - unregister I2C driver
  * @driver: the driver being unregistered
+ * Context: can sleep
  */
 void i2c_del_driver(struct i2c_driver *driver)
 {
@@ -1331,10 +1344,14 @@ s32 i2c_smbus_write_block_data(struct i2c_client *client, u8 command,
 EXPORT_SYMBOL(i2c_smbus_write_block_data);
 
 /* Returns the number of read bytes */
-s32 i2c_smbus_read_i2c_block_data(struct i2c_client *client, u8 command, u8 *values)
+s32 i2c_smbus_read_i2c_block_data(struct i2c_client *client, u8 command,
+                                  u8 length, u8 *values)
 {
         union i2c_smbus_data data;
 
+        if (length > I2C_SMBUS_BLOCK_MAX)
+                length = I2C_SMBUS_BLOCK_MAX;
+        data.block[0] = length;
         if (i2c_smbus_xfer(client->adapter,client->addr,client->flags,
                               I2C_SMBUS_READ,command,
                               I2C_SMBUS_I2C_BLOCK_DATA,&data))
@@ -1455,7 +1472,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter * adapter, u16 addr,
                 break;
         case I2C_SMBUS_I2C_BLOCK_DATA:
                 if (read_write == I2C_SMBUS_READ) {
-                        msg[1].len = I2C_SMBUS_BLOCK_MAX;
+                        msg[1].len = data->block[0];
                 } else {
                         msg[0].len = data->block[0] + 1;
                         if (msg[0].len > I2C_SMBUS_BLOCK_MAX + 1) {
@@ -1511,9 +1528,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter * adapter, u16 addr,
                                 data->word = msgbuf1[0] | (msgbuf1[1] << 8);
                                 break;
                         case I2C_SMBUS_I2C_BLOCK_DATA:
-                                /* fixed at 32 for now */
-                                data->block[0] = I2C_SMBUS_BLOCK_MAX;
-                                for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
+                                for (i = 0; i < data->block[0]; i++)
                                         data->block[i+1] = msgbuf1[i];
                                 break;
                         case I2C_SMBUS_BLOCK_DATA:
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index e7a709710592..64eee9551b22 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -283,6 +283,7 @@ static int i2cdev_ioctl(struct inode *inode, struct file *file,
                     (data_arg.size != I2C_SMBUS_WORD_DATA) &&
                     (data_arg.size != I2C_SMBUS_PROC_CALL) &&
                     (data_arg.size != I2C_SMBUS_BLOCK_DATA) &&
+                    (data_arg.size != I2C_SMBUS_I2C_BLOCK_BROKEN) &&
                     (data_arg.size != I2C_SMBUS_I2C_BLOCK_DATA) &&
                     (data_arg.size != I2C_SMBUS_BLOCK_PROC_CALL)) {
                         dev_dbg(&client->adapter->dev,
@@ -329,10 +330,18 @@ static int i2cdev_ioctl(struct inode *inode, struct file *file,
 
                 if ((data_arg.size == I2C_SMBUS_PROC_CALL) ||
                     (data_arg.size == I2C_SMBUS_BLOCK_PROC_CALL) ||
+                    (data_arg.size == I2C_SMBUS_I2C_BLOCK_DATA) ||
                     (data_arg.read_write == I2C_SMBUS_WRITE)) {
                         if (copy_from_user(&temp, data_arg.data, datasize))
                                 return -EFAULT;
                 }
+                if (data_arg.size == I2C_SMBUS_I2C_BLOCK_BROKEN) {
+                        /* Convert old I2C block commands to the new
+                           convention. This preserves binary compatibility. */
+                        data_arg.size = I2C_SMBUS_I2C_BLOCK_DATA;
+                        if (data_arg.read_write == I2C_SMBUS_READ)
+                                temp.block[0] = I2C_SMBUS_BLOCK_MAX;
+                }
                 res = i2c_smbus_xfer(client->adapter,client->addr,client->flags,
                       data_arg.read_write,
                       data_arg.command,data_arg.size,&temp);
diff --git a/drivers/ide/legacy/hd.c b/drivers/ide/legacy/hd.c
index 7f4c0a5050a1..8f2db8dd35f7 100644
--- a/drivers/ide/legacy/hd.c
+++ b/drivers/ide/legacy/hd.c
@@ -719,74 +719,25 @@ static int __init hd_init(void)
         device_timer.function = hd_times_out;
         blk_queue_hardsect_size(hd_queue, 512);
 
-#ifdef __i386__
         if (!NR_HD) {
-                extern struct drive_info drive_info;
-                unsigned char *BIOS = (unsigned char *) &drive_info;
-                unsigned long flags;
-                int cmos_disks;
-
-                for (drive=0 ; drive<2 ; drive++) {
-                        hd_info[drive].cyl = *(unsigned short *) BIOS;
-                        hd_info[drive].head = *(2+BIOS);
-                        hd_info[drive].wpcom = *(unsigned short *) (5+BIOS);
-                        hd_info[drive].ctl = *(8+BIOS);
-                        hd_info[drive].lzone = *(unsigned short *) (12+BIOS);
-                        hd_info[drive].sect = *(14+BIOS);
-#ifdef does_not_work_for_everybody_with_scsi_but_helps_ibm_vp
-                        if (hd_info[drive].cyl && NR_HD == drive)
-                                NR_HD++;
-#endif
-                        BIOS += 16;
-                }
-
-        /*
-                We query CMOS about hard disks : it could be that 
-                we have a SCSI/ESDI/etc controller that is BIOS
-                compatible with ST-506, and thus showing up in our
-                BIOS table, but not register compatible, and therefore
-                not present in CMOS.
-
-                Furthermore, we will assume that our ST-506 drives
-                <if any> are the primary drives in the system, and 
-                the ones reflected as drive 1 or 2.
-
-                The first drive is stored in the high nibble of CMOS
-                byte 0x12, the second in the low nibble.  This will be
-                either a 4 bit drive type or 0xf indicating use byte 0x19 
-                for an 8 bit type, drive 1, 0x1a for drive 2 in CMOS.
-
-                Needless to say, a non-zero value means we have 
-                an AT controller hard disk for that drive.
-
-                Currently the rtc_lock is a bit academic since this
-                driver is non-modular, but someday... ?         Paul G.
-        */
-
-                spin_lock_irqsave(&rtc_lock, flags);
-                cmos_disks = CMOS_READ(0x12);
-                spin_unlock_irqrestore(&rtc_lock, flags);
-
-                if (cmos_disks & 0xf0) {
-                        if (cmos_disks & 0x0f)
-                                NR_HD = 2;
-                        else
-                                NR_HD = 1;
-                }
-        }
-#endif /* __i386__ */
-#ifdef __arm__
-        if (!NR_HD) {
-                /* We don't know anything about the drive.  This means
+                /*
+                 * We don't know anything about the drive.  This means
                  * that you *MUST* specify the drive parameters to the
                  * kernel yourself.
+                 *
+                 * If we were on an i386, we used to read this info from
+                 * the BIOS or CMOS.  This doesn't work all that well,
+                 * since this assumes that this is a primary or secondary
+                 * drive, and if we're using this legacy driver, it's
+                 * probably an auxilliary controller added to recover
+                 * legacy data off an ST-506 drive.  Either way, it's
+                 * definitely safest to have the user explicitly specify
+                 * the information.
                  */
                 printk("hd: no drives specified - use hd=cyl,head,sectors"
                         " on kernel command line\n");
-        }
-#endif
-        if (!NR_HD)
                 goto out;
+        }
 
         for (drive=0 ; drive < NR_HD ; drive++) {
                 struct gendisk *disk = alloc_disk(64);
diff --git a/drivers/macintosh/windfarm_smu_sat.c b/drivers/macintosh/windfarm_smu_sat.c
index 1043b39aa123..351982bcec1b 100644
--- a/drivers/macintosh/windfarm_smu_sat.c
+++ b/drivers/macintosh/windfarm_smu_sat.c
@@ -67,26 +67,6 @@ static struct i2c_driver wf_sat_driver = {
         .detach_client  = wf_sat_detach,
 };
 
-/*
- * XXX i2c_smbus_read_i2c_block_data doesn't pass the requested
- * length down to the low-level driver, so we use this, which
- * works well enough with the SMU i2c driver code...
- */
-static int sat_read_block(struct i2c_client *client, u8 command,
-                          u8 *values, int len)
-{
-        union i2c_smbus_data data;
-        int err;
-
-        data.block[0] = len;
-        err = i2c_smbus_xfer(client->adapter, client->addr, client->flags,
-                             I2C_SMBUS_READ, command, I2C_SMBUS_I2C_BLOCK_DATA,
-                             &data);
-        if (!err)
-                memcpy(values, data.block, len);
-        return err;
-}
-
 struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id, int id,
                                                   unsigned int *size)
 {
@@ -124,8 +104,8 @@ struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id, int id,
                 return NULL;
 
         for (i = 0; i < len; i += 4) {
-                err = sat_read_block(&sat->i2c, 0xa, data, 4);
-                if (err) {
+                err = i2c_smbus_read_i2c_block_data(&sat->i2c, 0xa, 4, data);
+                if (err < 0) {
                         printk(KERN_ERR "smu_sat_get_sdb_part rd err %d\n",
                                err);
                         goto fail;
@@ -157,8 +137,8 @@ static int wf_sat_read_cache(struct wf_sat *sat)
 {
         int err;
 
-        err = sat_read_block(&sat->i2c, 0x3f, sat->cache, 16);
-        if (err)
+        err = i2c_smbus_read_i2c_block_data(&sat->i2c, 0x3f, 16, sat->cache);
+        if (err < 0)
                 return err;
         sat->last_read = jiffies;
 #ifdef LOTSA_DEBUG
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index d4e39ff1545b..ba314adf68b8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -885,7 +885,7 @@ config NET_NETX
 
 config DM9000
         tristate "DM9000 support"
-        depends on ARM || MIPS
+        depends on ARM || BLACKFIN || MIPS
         select CRC32
         select MII
         ---help---
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 264fa0e2e075..c3de81bf090a 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -104,6 +104,18 @@
 #define PRINTK(args...)   printk(KERN_DEBUG args)
 #endif
 
+#ifdef CONFIG_BLACKFIN
+#define readsb  insb
+#define readsw  insw
+#define readsl  insl
+#define writesb outsb
+#define writesw outsw
+#define writesl outsl
+#define DM9000_IRQ_FLAGS        (IRQF_SHARED | IRQF_TRIGGER_HIGH)
+#else
+#define DM9000_IRQ_FLAGS        IRQF_SHARED
+#endif
+
 /*
  * Transmit timeout, default 5 seconds.
  */
@@ -431,6 +443,9 @@ dm9000_probe(struct platform_device *pdev)
                 db->io_addr = (void __iomem *)base;
                 db->io_data = (void __iomem *)(base + 4);
 
+                /* ensure at least we have a default set of IO routines */
+                dm9000_set_io(db, 2);
+
         } else {
                 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
                 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
@@ -614,7 +629,7 @@ dm9000_open(struct net_device *dev)
 
         PRINTK2("entering dm9000_open\n");
 
-        if (request_irq(dev->irq, &dm9000_interrupt, IRQF_SHARED, dev->name, dev))
+        if (request_irq(dev->irq, &dm9000_interrupt, DM9000_IRQ_FLAGS, dev->name, dev))
                 return -EAGAIN;
 
         /* Initialize DM9000 board */
diff --git a/drivers/rtc/rtc-vr41xx.c b/drivers/rtc/rtc-vr41xx.c
index af7596ef29e2..ce2f78de7a80 100644
--- a/drivers/rtc/rtc-vr41xx.c
+++ b/drivers/rtc/rtc-vr41xx.c
@@ -17,10 +17,11 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+#include <linux/err.h>
 #include <linux/fs.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/rtc.h>
@@ -30,25 +31,11 @@
 #include <asm/div64.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
-#include <asm/vr41xx/irq.h>
 
 MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
 MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
 MODULE_LICENSE("GPL");
 
-#define RTC1_TYPE1_START        0x0b0000c0UL
-#define RTC1_TYPE1_END          0x0b0000dfUL
-#define RTC2_TYPE1_START        0x0b0001c0UL
-#define RTC2_TYPE1_END          0x0b0001dfUL
-
-#define RTC1_TYPE2_START        0x0f000100UL
-#define RTC1_TYPE2_END          0x0f00011fUL
-#define RTC2_TYPE2_START        0x0f000120UL
-#define RTC2_TYPE2_END          0x0f00013fUL
-
-#define RTC1_SIZE               0x20
-#define RTC2_SIZE               0x20
-
 /* RTC 1 registers */
 #define ETIMELREG               0x00
 #define ETIMEMREG               0x02
@@ -98,13 +85,8 @@ static char rtc_name[] = "RTC";
 static unsigned long periodic_frequency;
 static unsigned long periodic_count;
 static unsigned int alarm_enabled;
-
-struct resource rtc_resource[2] = {
-        {       .name   = rtc_name,
-                .flags  = IORESOURCE_MEM,       },
-        {       .name   = rtc_name,
-                .flags  = IORESOURCE_MEM,       },
-};
+static int aie_irq = -1;
+static int pie_irq = -1;
 
 static inline unsigned long read_elapsed_second(void)
 {
@@ -150,8 +132,8 @@ static void vr41xx_rtc_release(struct device *dev)
 
         spin_unlock_irq(&rtc_lock);
 
-        disable_irq(ELAPSEDTIME_IRQ);
-        disable_irq(RTCLONG1_IRQ);
+        disable_irq(aie_irq);
+        disable_irq(pie_irq);
 }
 
 static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
@@ -209,14 +191,14 @@ static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
         spin_lock_irq(&rtc_lock);
 
         if (alarm_enabled)
-                disable_irq(ELAPSEDTIME_IRQ);
+                disable_irq(aie_irq);
 
         rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
         rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
         rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
 
         if (wkalrm->enabled)
-                enable_irq(ELAPSEDTIME_IRQ);
+                enable_irq(aie_irq);
 
         alarm_enabled = wkalrm->enabled;
 
@@ -234,7 +216,7 @@ static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long
                 spin_lock_irq(&rtc_lock);
 
                 if (!alarm_enabled) {
-                        enable_irq(ELAPSEDTIME_IRQ);
+                        enable_irq(aie_irq);
                         alarm_enabled = 1;
                 }
 
@@ -244,17 +226,17 @@ static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long
                 spin_lock_irq(&rtc_lock);
 
                 if (alarm_enabled) {
-                        disable_irq(ELAPSEDTIME_IRQ);
+                        disable_irq(aie_irq);
                         alarm_enabled = 0;
                 }
 
                 spin_unlock_irq(&rtc_lock);
                 break;
         case RTC_PIE_ON:
-                enable_irq(RTCLONG1_IRQ);
+                enable_irq(pie_irq);
                 break;
         case RTC_PIE_OFF:
-                disable_irq(RTCLONG1_IRQ);
+                disable_irq(pie_irq);
                 break;
         case RTC_IRQP_READ:
                 return put_user(periodic_frequency, (unsigned long __user *)arg);
@@ -331,31 +313,37 @@ static const struct rtc_class_ops vr41xx_rtc_ops = {
 
 static int __devinit rtc_probe(struct platform_device *pdev)
 {
+        struct resource *res;
         struct rtc_device *rtc;
-        unsigned int irq;
         int retval;
 
-        if (pdev->num_resources != 2)
+        if (pdev->num_resources != 4)
                 return -EBUSY;
 
-        rtc1_base = ioremap(pdev->resource[0].start, RTC1_SIZE);
-        if (rtc1_base == NULL)
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
                 return -EBUSY;
 
-        rtc2_base = ioremap(pdev->resource[1].start, RTC2_SIZE);
-        if (rtc2_base == NULL) {
-                iounmap(rtc1_base);
-                rtc1_base = NULL;
+        rtc1_base = ioremap(res->start, res->end - res->start + 1);
+        if (!rtc1_base)
                 return -EBUSY;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                retval = -EBUSY;
+                goto err_rtc1_iounmap;
+        }
+
+        rtc2_base = ioremap(res->start, res->end - res->start + 1);
+        if (!rtc2_base) {
+                retval = -EBUSY;
+                goto err_rtc1_iounmap;
         }
 
         rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
         if (IS_ERR(rtc)) {
-                iounmap(rtc1_base);
-                iounmap(rtc2_base);
-                rtc1_base = NULL;
-                rtc2_base = NULL;
-                return PTR_ERR(rtc);
+                retval = PTR_ERR(rtc);
+                goto err_iounmap_all;
         }
 
         spin_lock_irq(&rtc_lock);
@@ -368,35 +356,50 @@ static int __devinit rtc_probe(struct platform_device *pdev)
 
         spin_unlock_irq(&rtc_lock);
 
-        irq = ELAPSEDTIME_IRQ;
-        retval = request_irq(irq, elapsedtime_interrupt, IRQF_DISABLED,
-                             "elapsed_time", pdev);
-        if (retval == 0) {
-                irq = RTCLONG1_IRQ;
-                retval = request_irq(irq, rtclong1_interrupt, IRQF_DISABLED,
-                                     "rtclong1", pdev);
+        aie_irq = platform_get_irq(pdev, 0);
+        if (aie_irq < 0 || aie_irq >= NR_IRQS) {
+                retval = -EBUSY;
+                goto err_device_unregister;
         }
 
-        if (retval < 0) {
-                printk(KERN_ERR "rtc: IRQ%d is busy\n", irq);
-                rtc_device_unregister(rtc);
-                if (irq == RTCLONG1_IRQ)
-                        free_irq(ELAPSEDTIME_IRQ, NULL);
-                iounmap(rtc1_base);
-                iounmap(rtc2_base);
-                rtc1_base = NULL;
-                rtc2_base = NULL;
-                return retval;
-        }
+        retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
+                             "elapsed_time", pdev);
+        if (retval < 0)
+                goto err_device_unregister;
+
+        pie_irq = platform_get_irq(pdev, 1);
+        if (pie_irq < 0 || pie_irq >= NR_IRQS)
+                goto err_free_irq;
+
+        retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
+                             "rtclong1", pdev);
+        if (retval < 0)
+                goto err_free_irq;
 
         platform_set_drvdata(pdev, rtc);
 
-        disable_irq(ELAPSEDTIME_IRQ);
-        disable_irq(RTCLONG1_IRQ);
+        disable_irq(aie_irq);
+        disable_irq(pie_irq);
 
         printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
 
         return 0;
+
+err_free_irq:
+        free_irq(aie_irq, pdev);
+
+err_device_unregister:
+        rtc_device_unregister(rtc);
+
+err_iounmap_all:
+        iounmap(rtc2_base);
+        rtc2_base = NULL;
+
+err_rtc1_iounmap:
+        iounmap(rtc1_base);
+        rtc1_base = NULL;
+
+        return retval;
 }
 
 static int __devexit rtc_remove(struct platform_device *pdev)
@@ -404,23 +407,21 @@ static int __devexit rtc_remove(struct platform_device *pdev)
         struct rtc_device *rtc;
 
         rtc = platform_get_drvdata(pdev);
-        if (rtc != NULL)
+        if (rtc)
                 rtc_device_unregister(rtc);
 
         platform_set_drvdata(pdev, NULL);
 
-        free_irq(ELAPSEDTIME_IRQ, NULL);
-        free_irq(RTCLONG1_IRQ, NULL);
-        if (rtc1_base != NULL)
+        free_irq(aie_irq, pdev);
+        free_irq(pie_irq, pdev);
+        if (rtc1_base)
                 iounmap(rtc1_base);
-        if (rtc2_base != NULL)
+        if (rtc2_base)
                 iounmap(rtc2_base);
 
         return 0;
 }
 
-static struct platform_device *rtc_platform_device;
-
 static struct platform_driver rtc_platform_driver = {
         .probe          = rtc_probe,
         .remove         = __devexit_p(rtc_remove),
@@ -432,55 +433,12 @@ static struct platform_driver rtc_platform_driver = {
 
 static int __init vr41xx_rtc_init(void)
 {
-        int retval;
-
-        switch (current_cpu_data.cputype) {
-        case CPU_VR4111:
-        case CPU_VR4121:
-                rtc_resource[0].start = RTC1_TYPE1_START;
-                rtc_resource[0].end = RTC1_TYPE1_END;
-                rtc_resource[1].start = RTC2_TYPE1_START;
-                rtc_resource[1].end = RTC2_TYPE1_END;
-                break;
-        case CPU_VR4122:
-        case CPU_VR4131:
-        case CPU_VR4133:
-                rtc_resource[0].start = RTC1_TYPE2_START;
-                rtc_resource[0].end = RTC1_TYPE2_END;
-                rtc_resource[1].start = RTC2_TYPE2_START;
-                rtc_resource[1].end = RTC2_TYPE2_END;
-                break;
-        default:
-                return -ENODEV;
-                break;
-        }
-
-        rtc_platform_device = platform_device_alloc("RTC", -1);
-        if (rtc_platform_device == NULL)
-                return -ENOMEM;
-
-        retval = platform_device_add_resources(rtc_platform_device,
-                                rtc_resource, ARRAY_SIZE(rtc_resource));
-
-        if (retval == 0)
-                retval = platform_device_add(rtc_platform_device);
-
-        if (retval < 0) {
-                platform_device_put(rtc_platform_device);
-                return retval;
-        }
-
-        retval = platform_driver_register(&rtc_platform_driver);
-        if (retval < 0)
-                platform_device_unregister(rtc_platform_device);
-
-        return retval;
+        return platform_driver_register(&rtc_platform_driver);
 }
 
 static void __exit vr41xx_rtc_exit(void)
 {
         platform_driver_unregister(&rtc_platform_driver);
-        platform_device_unregister(rtc_platform_device);
 }
 
 module_init(vr41xx_rtc_init);
diff --git a/drivers/rtc/rtc-x1205.c b/drivers/rtc/rtc-x1205.c
index 513d1a611aab..b3fae357ca49 100644
--- a/drivers/rtc/rtc-x1205.c
+++ b/drivers/rtc/rtc-x1205.c
@@ -9,6 +9,9 @@
  *
  * based on a lot of other RTC drivers.
  *
+ * Information and datasheet:
+ * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -26,7 +29,7 @@
  * Two bytes need to be written to read a single register,
  * while most other chips just require one and take the second
  * one as the data to be written. To prevent corrupting
- * unknown chips, the user must explicitely set the probe parameter.
+ * unknown chips, the user must explicitly set the probe parameter.
  */
 
 static unsigned short normal_i2c[] = { I2C_CLIENT_END };
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 315ea9916456..2adbed4e10f3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -556,7 +556,7 @@ choice
 
 config SERIAL_BFIN_DMA
         bool "DMA mode"
-        depends on DMA_UNCACHED_1M
+        depends on DMA_UNCACHED_1M && !KGDB_UART
         help
           This driver works under DMA mode. If this option is selected, the
           blackfin simple dma driver is also enabled.
@@ -599,7 +599,7 @@ config UART0_RTS_PIN
 
 config SERIAL_BFIN_UART1
         bool "Enable UART1"
-        depends on SERIAL_BFIN && (BF534 || BF536 || BF537)
+        depends on SERIAL_BFIN && (BF534 || BF536 || BF537 || BF54x)
         help
           Enable UART1
 
@@ -612,18 +612,58 @@ config BFIN_UART1_CTSRTS
 
 config UART1_CTS_PIN
         int "UART1 CTS pin"
-        depends on BFIN_UART1_CTSRTS
+        depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
         default -1
         help
           Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
 
 config UART1_RTS_PIN
         int "UART1 RTS pin"
-        depends on BFIN_UART1_CTSRTS
+        depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
         default -1
         help
           Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
 
+config SERIAL_BFIN_UART2
+        bool "Enable UART2"
+        depends on SERIAL_BFIN && (BF54x)
+        help
+          Enable UART2
+
+config BFIN_UART2_CTSRTS
+        bool "Enable UART2 hardware flow control"
+        depends on SERIAL_BFIN_UART2
+        help
+          Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
+          signal.
+
+config UART2_CTS_PIN
+        int "UART2 CTS pin"
+        depends on BFIN_UART2_CTSRTS
+        default -1
+        help
+          Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
+
+config UART2_RTS_PIN
+        int "UART2 RTS pin"
+        depends on BFIN_UART2_CTSRTS
+        default -1
+        help
+          Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
+
+config SERIAL_BFIN_UART3
+        bool "Enable UART3"
+        depends on SERIAL_BFIN && (BF54x)
+        help
+          Enable UART3
+
+config BFIN_UART3_CTSRTS
+        bool "Enable UART3 hardware flow control"
+        depends on SERIAL_BFIN_UART3
+        help
+          Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
+          signal.
+
 config SERIAL_IMX
         bool "IMX serial port support"
         depends on ARM && ARCH_IMX
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 22569bd5d821..66c92bc36f3d 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -41,6 +41,11 @@
 #include <linux/tty_flip.h>
 #include <linux/serial_core.h>
 
+#ifdef CONFIG_KGDB_UART
+#include <linux/kgdb.h>
+#include <asm/irq_regs.h>
+#endif
+
 #include <asm/gpio.h>
 #include <asm/mach/bfin_serial_5xx.h>
 
@@ -81,15 +86,29 @@ static void bfin_serial_stop_tx(struct uart_port *port)
 {
         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 
+#ifdef CONFIG_BF54x
+        while (!(UART_GET_LSR(uart) & TEMT))
+                continue;
+#endif
+
 #ifdef CONFIG_SERIAL_BFIN_DMA
         disable_dma(uart->tx_dma_channel);
 #else
+#ifdef CONFIG_BF54x
+        /* Waiting for Transmission Finished */
+        while (!(UART_GET_LSR(uart) & TFI))
+                continue;
+        /* Clear TFI bit */
+        UART_PUT_LSR(uart, TFI);
+        UART_CLEAR_IER(uart, ETBEI);
+#else
         unsigned short ier;
 
         ier = UART_GET_IER(uart);
         ier &= ~ETBEI;
         UART_PUT_IER(uart, ier);
 #endif
+#endif
 }
 
 /*
@@ -102,12 +121,16 @@ static void bfin_serial_start_tx(struct uart_port *port)
 #ifdef CONFIG_SERIAL_BFIN_DMA
         bfin_serial_dma_tx_chars(uart);
 #else
+#ifdef CONFIG_BF54x
+        UART_SET_IER(uart, ETBEI);
+#else
         unsigned short ier;
         ier = UART_GET_IER(uart);
         ier |= ETBEI;
         UART_PUT_IER(uart, ier);
         bfin_serial_tx_chars(uart);
 #endif
+#endif
 }
 
 /*
@@ -116,11 +139,18 @@ static void bfin_serial_start_tx(struct uart_port *port)
 static void bfin_serial_stop_rx(struct uart_port *port)
 {
         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+#ifdef CONFIG_BF54x
+        UART_CLEAR_IER(uart, ERBFI);
+#else
         unsigned short ier;
 
         ier = UART_GET_IER(uart);
+#ifdef  CONFIG_KGDB_UART
+        if (uart->port.line != CONFIG_KGDB_UART_PORT)
+#endif
         ier &= ~ERBFI;
         UART_PUT_IER(uart, ier);
+#endif
 }
 
 /*
@@ -130,6 +160,49 @@ static void bfin_serial_enable_ms(struct uart_port *port)
 {
 }
 
+#ifdef CONFIG_KGDB_UART
+static int kgdb_entry_state;
+
+void kgdb_put_debug_char(int chr)
+{
+        struct bfin_serial_port *uart;
+        
+        if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
+                uart = &bfin_serial_ports[0];
+        else
+                uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
+        
+        while (!(UART_GET_LSR(uart) & THRE)) {
+                __builtin_bfin_ssync();
+        }
+        UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
+        __builtin_bfin_ssync();
+        UART_PUT_CHAR(uart, (unsigned char)chr);
+        __builtin_bfin_ssync();
+}
+
+int kgdb_get_debug_char(void)
+{
+        struct bfin_serial_port *uart;
+        unsigned char chr;
+
+        if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
+                uart = &bfin_serial_ports[0];
+        else
+                uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
+        
+        while(!(UART_GET_LSR(uart) & DR)) {
+                __builtin_bfin_ssync();
+        }
+        UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
+        __builtin_bfin_ssync();
+        chr = UART_GET_CHAR(uart);
+        __builtin_bfin_ssync();
+
+        return chr;
+}
+#endif
+
 #ifdef CONFIG_SERIAL_BFIN_PIO
 static void local_put_char(struct bfin_serial_port *uart, char ch)
 {
@@ -152,6 +225,9 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
 {
         struct tty_struct *tty = uart->port.info->tty;
         unsigned int status, ch, flg;
+#ifdef CONFIG_KGDB_UART
+        struct pt_regs *regs = get_irq_regs();
+#endif
 #ifdef BF533_FAMILY
         static int in_break = 0;
 #endif
@@ -160,6 +236,27 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
         ch = UART_GET_CHAR(uart);
         uart->port.icount.rx++;
 
+#ifdef CONFIG_KGDB_UART
+        if (uart->port.line == CONFIG_KGDB_UART_PORT) {
+                if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
+                        kgdb_breakkey_pressed(regs);
+                        return;
+                } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
+                        kgdb_entry_state = 1;
+                } else if (kgdb_entry_state == 1 && ch == 'q') {
+                        kgdb_entry_state = 0;
+                        kgdb_breakkey_pressed(regs);
+                        return;
+                } else if (ch == 0x3) {/* Ctrl + C */
+                        kgdb_entry_state = 0;
+                        kgdb_breakkey_pressed(regs);
+                        return;
+                } else {
+                        kgdb_entry_state = 0;
+                }
+        }
+#endif
+ 
 #ifdef BF533_FAMILY
         /* The BF533 family of processors have a nice misbehavior where
          * they continuously generate characters for a "single" break.
@@ -250,10 +347,21 @@ static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
 {
         struct bfin_serial_port *uart = dev_id;
 
+#ifdef CONFIG_BF54x
+        unsigned short status;
+        spin_lock(&uart->port.lock);
+        status = UART_GET_LSR(uart);
+        while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) {
+                bfin_serial_rx_chars(uart);
+                status = UART_GET_LSR(uart);
+        }
+        spin_unlock(&uart->port.lock);
+#else
         spin_lock(&uart->port.lock);
         while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY)
                 bfin_serial_rx_chars(uart);
         spin_unlock(&uart->port.lock);
+#endif
         return IRQ_HANDLED;
 }
 
@@ -261,10 +369,21 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
 {
         struct bfin_serial_port *uart = dev_id;
 
+#ifdef CONFIG_BF54x
+        unsigned short status;
+        spin_lock(&uart->port.lock);
+        status = UART_GET_LSR(uart);
+        while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) {
+                bfin_serial_tx_chars(uart);
+                status = UART_GET_LSR(uart);
+        }
+        spin_unlock(&uart->port.lock);
+#else
         spin_lock(&uart->port.lock);
         while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY)
                 bfin_serial_tx_chars(uart);
         spin_unlock(&uart->port.lock);
+#endif
         return IRQ_HANDLED;
 }
 
@@ -275,7 +394,6 @@ static void bfin_serial_do_work(struct work_struct *work)
 
         bfin_serial_mctrl_check(uart);
 }
-
 #endif
 
 #ifdef CONFIG_SERIAL_BFIN_DMA
@@ -324,9 +442,13 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
         set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
         set_dma_x_modify(uart->tx_dma_channel, 1);
         enable_dma(uart->tx_dma_channel);
+#ifdef CONFIG_BF54x
+        UART_SET_IER(uart, ETBEI);
+#else
         ier = UART_GET_IER(uart);
         ier |= ETBEI;
         UART_PUT_IER(uart, ier);
+#endif
         spin_unlock_irqrestore(&uart->port.lock, flags);
 }
 
@@ -406,9 +528,13 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
         if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
                 clear_dma_irqstat(uart->tx_dma_channel);
                 disable_dma(uart->tx_dma_channel);
+#ifdef CONFIG_BF54x
+                UART_CLEAR_IER(uart, ETBEI);
+#else
                 ier = UART_GET_IER(uart);
                 ier &= ~ETBEI;
                 UART_PUT_IER(uart, ier);
+#endif
                 xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1);
                 uart->port.icount.tx+=uart->tx_count;
 
@@ -571,7 +697,11 @@ static int bfin_serial_startup(struct uart_port *port)
         uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
         add_timer(&(uart->rx_dma_timer));
 #else
+# ifdef CONFIG_KGDB_UART
+        if (uart->port.line != CONFIG_KGDB_UART_PORT && request_irq
+# else
         if (request_irq
+# endif
             (uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
              "BFIN_UART_RX", uart)) {
                 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
@@ -586,7 +716,11 @@ static int bfin_serial_startup(struct uart_port *port)
                 return -EBUSY;
         }
 #endif
+#ifdef CONFIG_BF54x
+        UART_SET_IER(uart, ERBFI);
+#else
         UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
+#endif
         return 0;
 }
 
@@ -601,6 +735,9 @@ static void bfin_serial_shutdown(struct uart_port *port)
         free_dma(uart->rx_dma_channel);
         del_timer(&(uart->rx_dma_timer));
 #else
+#ifdef  CONFIG_KGDB_UART
+        if (uart->port.line != CONFIG_KGDB_UART_PORT)
+#endif
         free_irq(uart->port.irq, uart);
         free_irq(uart->port.irq+1, uart);
 #endif
@@ -674,29 +811,41 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
 
         /* Disable UART */
         ier = UART_GET_IER(uart);
+#ifdef CONFIG_BF54x
+        UART_CLEAR_IER(uart, 0xF);
+#else
         UART_PUT_IER(uart, 0);
+#endif
 
+#ifndef CONFIG_BF54x
         /* Set DLAB in LCR to Access DLL and DLH */
         val = UART_GET_LCR(uart);
         val |= DLAB;
         UART_PUT_LCR(uart, val);
         SSYNC();
+#endif
 
         UART_PUT_DLL(uart, quot & 0xFF);
         SSYNC();
         UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
         SSYNC();
 
+#ifndef CONFIG_BF54x
         /* Clear DLAB in LCR to Access THR RBR IER */
         val = UART_GET_LCR(uart);
         val &= ~DLAB;
         UART_PUT_LCR(uart, val);
         SSYNC();
+#endif
 
         UART_PUT_LCR(uart, lcr);
 
         /* Enable UART */
+#ifdef CONFIG_BF54x
+        UART_SET_IER(uart, ier);
+#else
         UART_PUT_IER(uart, ier);
+#endif
 
         val = UART_GET_GCTL(uart);
         val |= UCEN;
@@ -808,15 +957,15 @@ static void __init bfin_serial_init_ports(void)
                         bfin_serial_resource[i].uart_rts_pin;
 #endif
                 bfin_serial_hw_init(&bfin_serial_ports[i]);
-
         }
+
 }
 
 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
 {
         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-        while (!(UART_GET_LSR(uart)))
+        while (!(UART_GET_LSR(uart) & THRE))
                 barrier();
         UART_PUT_CHAR(uart, ch);
         SSYNC();
@@ -868,18 +1017,22 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
                         case 2: *bits = 7; break;
                         case 3: *bits = 8; break;
                 }
+#ifndef CONFIG_BF54x
                 /* Set DLAB in LCR to Access DLL and DLH */
                 val = UART_GET_LCR(uart);
                 val |= DLAB;
                 UART_PUT_LCR(uart, val);
+#endif
 
                 dll = UART_GET_DLL(uart);
                 dlh = UART_GET_DLH(uart);
 
+#ifndef CONFIG_BF54x
                 /* Clear DLAB in LCR to Access THR RBR IER */
                 val = UART_GET_LCR(uart);
                 val &= ~DLAB;
                 UART_PUT_LCR(uart, val);
+#endif
 
                 *baud = get_sclk() / (16*(dll | dlh << 8));
         }
@@ -931,6 +1084,10 @@ static int __init bfin_serial_rs_console_init(void)
 {
         bfin_serial_init_ports();
         register_console(&bfin_serial_console);
+#ifdef CONFIG_KGDB_UART
+        kgdb_entry_state = 0;
+        init_kgdb_uart();
+#endif
         return 0;
 }
 console_initcall(bfin_serial_rs_console_init);
@@ -1023,6 +1180,10 @@ static struct platform_driver bfin_serial_driver = {
 static int __init bfin_serial_init(void)
 {
         int ret;
+#ifdef CONFIG_KGDB_UART
+        struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
+        struct termios t;
+#endif
 
         pr_info("Serial: Blackfin serial driver\n");
 
@@ -1036,6 +1197,21 @@ static int __init bfin_serial_init(void)
                         uart_unregister_driver(&bfin_serial_reg);
                 }
         }
+#ifdef CONFIG_KGDB_UART
+        if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
+                request_irq(uart->port.irq, bfin_serial_int,
+                        IRQF_DISABLED, "BFIN_UART_RX", uart);
+                pr_info("Request irq for kgdb uart port\n");
+                UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
+                __builtin_bfin_ssync();
+                t.c_cflag = CS8|B57600;
+                t.c_iflag = 0;
+                t.c_oflag = 0;
+                t.c_lflag = ICANON;
+                t.c_line = CONFIG_KGDB_UART_PORT;
+                bfin_serial_set_termios(&uart->port, &t, &t);
+        }
+#endif
         return ret;
 }
 
diff --git a/drivers/serial/vr41xx_siu.c b/drivers/serial/vr41xx_siu.c
index cf0e663b42ed..85309acb75f6 100644
--- a/drivers/serial/vr41xx_siu.c
+++ b/drivers/serial/vr41xx_siu.c
@@ -1,7 +1,7 @@
 /*
  *  Driver for NEC VR4100 series Serial Interface Unit.
  *
- *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *  Copyright (C) 2004-2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
  *
  *  Based on drivers/serial/8250.c, by Russell King.
  *
@@ -25,12 +25,12 @@
 #endif
 
 #include <linux/console.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/ioport.h>
+#include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/serial_reg.h>
@@ -38,11 +38,9 @@
 #include <linux/tty_flip.h>
 
 #include <asm/io.h>
-#include <asm/vr41xx/irq.h>
 #include <asm/vr41xx/siu.h>
 #include <asm/vr41xx/vr41xx.h>
 
-#define SIU_PORTS_MAX   2
 #define SIU_BAUD_BASE   1152000
 #define SIU_MAJOR       204
 #define SIU_MINOR_BASE  82
@@ -60,32 +58,13 @@
  #define IRUSESEL       0x02
  #define SIRSEL         0x01
 
-struct siu_port {
-        unsigned int type;
-        unsigned int irq;
-        unsigned long start;
-};
-
-static const struct siu_port siu_type1_ports[] = {
-        {       .type           = PORT_VR41XX_SIU,
-                .irq            = SIU_IRQ,
-                .start          = 0x0c000000UL,         },
-};
-
-#define SIU_TYPE1_NR_PORTS      (sizeof(siu_type1_ports) / sizeof(struct siu_port))
-
-static const struct siu_port siu_type2_ports[] = {
-        {       .type           = PORT_VR41XX_SIU,
-                .irq            = SIU_IRQ,
-                .start          = 0x0f000800UL,         },
-        {       .type           = PORT_VR41XX_DSIU,
-                .irq            = DSIU_IRQ,
-                .start          = 0x0f000820UL,         },
+static struct uart_port siu_uart_ports[SIU_PORTS_MAX] = {
+        [0 ... SIU_PORTS_MAX-1] = {
+                .lock   = __SPIN_LOCK_UNLOCKED(siu_uart_ports->lock),
+                .irq    = -1,
+        },
 };
 
-#define SIU_TYPE2_NR_PORTS      (sizeof(siu_type2_ports) / sizeof(struct siu_port))
-
-static struct uart_port siu_uart_ports[SIU_PORTS_MAX];
 static uint8_t lsr_break_flag[SIU_PORTS_MAX];
 
 #define siu_read(port, offset)          readb((port)->membase + (offset))
@@ -110,7 +89,6 @@ void vr41xx_select_siu_interface(siu_interface_t interface)
 
         spin_unlock_irqrestore(&port->lock, flags);
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface);
 
 void vr41xx_use_irda(irda_use_t use)
@@ -132,7 +110,6 @@ void vr41xx_use_irda(irda_use_t use)
 
         spin_unlock_irqrestore(&port->lock, flags);
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_use_irda);
 
 void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
@@ -166,7 +143,6 @@ void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
 
         spin_unlock_irqrestore(&port->lock, flags);
 }
-
 EXPORT_SYMBOL_GPL(vr41xx_select_irda_module);
 
 static inline void siu_clear_fifo(struct uart_port *port)
@@ -177,21 +153,6 @@ static inline void siu_clear_fifo(struct uart_port *port)
         siu_write(port, UART_FCR, 0);
 }
 
-static inline int siu_probe_ports(void)
-{
-        switch (current_cpu_data.cputype) {
-        case CPU_VR4111:
-        case CPU_VR4121:
-                return SIU_TYPE1_NR_PORTS;
-        case CPU_VR4122:
-        case CPU_VR4131:
-        case CPU_VR4133:
-                return SIU_TYPE2_NR_PORTS;
-        }
-
-        return 0;
-}
-
 static inline unsigned long siu_port_size(struct uart_port *port)
 {
         switch (port->type) {
@@ -206,21 +167,10 @@ static inline unsigned long siu_port_size(struct uart_port *port)
 
 static inline unsigned int siu_check_type(struct uart_port *port)
 {
-        switch (current_cpu_data.cputype) {
-        case CPU_VR4111:
-        case CPU_VR4121:
-                if (port->line == 0)
-                        return PORT_VR41XX_SIU;
-                break;
-        case CPU_VR4122:
-        case CPU_VR4131:
-        case CPU_VR4133:
-                if (port->line == 0)
-                        return PORT_VR41XX_SIU;
-                else if (port->line == 1)
-                        return PORT_VR41XX_DSIU;
-                break;
-        }
+        if (port->line == 0)
+                return PORT_VR41XX_SIU;
+        if (port->line == 1 && port->irq != -1)
+                return PORT_VR41XX_DSIU;
 
         return PORT_UNKNOWN;
 }
@@ -751,44 +701,34 @@ static struct uart_ops siu_uart_ops = {
         .verify_port    = siu_verify_port,
 };
 
-static int siu_init_ports(void)
+static int siu_init_ports(struct platform_device *pdev)
 {
-        const struct siu_port *siu;
         struct uart_port *port;
-        int i, num;
+        struct resource *res;
+        int *type = pdev->dev.platform_data;
+        int i;
 
-        switch (current_cpu_data.cputype) {
-        case CPU_VR4111:
-        case CPU_VR4121:
-                siu = siu_type1_ports;
-                break;
-        case CPU_VR4122:
-        case CPU_VR4131:
-        case CPU_VR4133:
-                siu = siu_type2_ports;
-                break;
-        default:
+        if (!type)
                 return 0;
-        }
 
         port = siu_uart_ports;
-        num = siu_probe_ports();
-        for (i = 0; i < num; i++) {
-                spin_lock_init(&port->lock);
-                port->irq = siu->irq;
+        for (i = 0; i < SIU_PORTS_MAX; i++) {
+                port->type = type[i];
+                if (port->type == PORT_UNKNOWN)
+                        continue;
+                port->irq = platform_get_irq(pdev, i);
                 port->uartclk = SIU_BAUD_BASE * 16;
                 port->fifosize = 16;
                 port->regshift = 0;
                 port->iotype = UPIO_MEM;
                 port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
-                port->type = siu->type;
                 port->line = i;
-                port->mapbase = siu->start;
-                siu++;
+                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+                port->mapbase = res->start;
                 port++;
         }
 
-        return num;
+        return i;
 }
 
 #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
@@ -883,13 +823,9 @@ static struct console siu_console = {
 static int __devinit siu_console_init(void)
 {
         struct uart_port *port;
-        int num, i;
-
-        num = siu_init_ports();
-        if (num <= 0)
-                return -ENODEV;
+        int i;
 
-        for (i = 0; i < num; i++) {
+        for (i = 0; i < SIU_PORTS_MAX; i++) {
                 port = &siu_uart_ports[i];
                 port->ops = &siu_uart_ops;
         }
@@ -920,7 +856,7 @@ static int __devinit siu_probe(struct platform_device *dev)
         struct uart_port *port;
         int num, i, retval;
 
-        num = siu_init_ports();
+        num = siu_init_ports(dev);
         if (num <= 0)
                 return -ENODEV;
 
@@ -998,8 +934,6 @@ static int siu_resume(struct platform_device *dev)
         return 0;
 }
 
-static struct platform_device *siu_platform_device;
-
 static struct platform_driver siu_device_driver = {
         .probe          = siu_probe,
         .remove         = __devexit_p(siu_remove),
@@ -1013,29 +947,12 @@ static struct platform_driver siu_device_driver = {
 
 static int __init vr41xx_siu_init(void)
 {
-        int retval;
-
-        siu_platform_device = platform_device_alloc("SIU", -1);
-        if (!siu_platform_device)
-                return -ENOMEM;
-
-        retval = platform_device_add(siu_platform_device);
-        if (retval < 0) {
-                platform_device_put(siu_platform_device);
-                return retval;
-        }
-
-        retval = platform_driver_register(&siu_device_driver);
-        if (retval < 0)
-                platform_device_unregister(siu_platform_device);
-
-        return retval;
+        return platform_driver_register(&siu_device_driver);
 }
 
 static void __exit vr41xx_siu_exit(void)
 {
         platform_driver_unregister(&siu_device_driver);
-        platform_device_unregister(siu_platform_device);
 }
 
 module_init(vr41xx_siu_init);
diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c
index 4fff61b32dcb..ed979f13908a 100644
--- a/drivers/tc/zs.c
+++ b/drivers/tc/zs.c
@@ -136,14 +136,14 @@ struct dec_serial *zs_chain;	/* list of all channels */
 struct tty_struct zs_ttys[NUM_CHANNELS];
 
 #ifdef CONFIG_SERIAL_DEC_CONSOLE
-static struct console sercons;
+static struct console zs_console;
 #endif
 #if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \
    !defined(MODULE)
 static unsigned long break_pressed; /* break, really ... */
 #endif
 
-static unsigned char zs_init_regs[16] = {
+static unsigned char zs_init_regs[16] __initdata = {
         0,                              /* write 0 */
         0,                              /* write 1 */
         0,                              /* write 2 */
@@ -383,7 +383,7 @@ static void receive_chars(struct dec_serial *info)
 
 #if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \
    !defined(MODULE)
-                if (break_pressed && info->line == sercons.index) {
+                if (break_pressed && info->line == zs_console.index) {
                         /* Ignore the null char got when BREAK is removed.  */
                         if (ch == 0)
                                 continue;
@@ -446,7 +446,7 @@ static void status_handle(struct dec_serial *info)
         if ((stat & BRK_ABRT) && !(info->read_reg_zero & BRK_ABRT)) {
 #if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \
    !defined(MODULE)
-                if (info->line == sercons.index) {
+                if (info->line == zs_console.index) {
                         if (!break_pressed)
                                 break_pressed = jiffies;
                 } else
@@ -1557,9 +1557,9 @@ static int rs_open(struct tty_struct *tty, struct file * filp)
         }
 
 #ifdef CONFIG_SERIAL_DEC_CONSOLE
-        if (sercons.cflag && sercons.index == line) {
-                tty->termios->c_cflag = sercons.cflag;
-                sercons.cflag = 0;
+        if (zs_console.cflag && zs_console.index == line) {
+                tty->termios->c_cflag = zs_console.cflag;
+                zs_console.cflag = 0;
                 change_speed(info);
         }
 #endif
@@ -1581,7 +1581,7 @@ static void __init show_serial_version(void)
 /*  Initialize Z8530s zs_channels
  */
 
-static void probe_sccs(void)
+static void __init probe_sccs(void)
 {
         struct dec_serial **pp;
         int i, n, n_chips = 0, n_channels, chip, channel;
@@ -1923,7 +1923,7 @@ static struct tty_driver *serial_console_device(struct console *c, int *index)
  *      - initialize the serial port
  *      Return non-zero if we didn't find a serial port.
  */
-static int serial_console_setup(struct console *co, char *options)
+static int __init serial_console_setup(struct console *co, char *options)
 {
         struct dec_serial *info;
         int baud = 9600;
@@ -2069,7 +2069,7 @@ static int serial_console_setup(struct console *co, char *options)
         return 0;
 }
 
-static struct console sercons = {
+static struct console zs_console = {
         .name           = "ttyS",
         .write          = serial_console_write,
         .device         = serial_console_device,
@@ -2083,7 +2083,7 @@ static struct console sercons = {
  */
 void __init zs_serial_console_init(void)
 {
-        register_console(&sercons);
+        register_console(&zs_console);
 }
 #endif /* ifdef CONFIG_SERIAL_DEC_CONSOLE */
 
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 63b85bf81a65..d3b8a6be2916 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -6,7 +6,7 @@ menu "Console display driver support"
 
 config VGA_CONSOLE
         bool "VGA text console" if EMBEDDED || !X86
-        depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH
+        depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BFIN
         default y
         help
           Saying Y here will allow you to use Linux in text mode through a
diff --git a/drivers/video/matrox/matroxfb_crtc2.h b/drivers/video/matrox/matroxfb_crtc2.h
index 608e40bb20e9..177177609be7 100644
--- a/drivers/video/matrox/matroxfb_crtc2.h
+++ b/drivers/video/matrox/matroxfb_crtc2.h
@@ -2,8 +2,6 @@
 #define __MATROXFB_CRTC2_H__
 
 #include <linux/ioctl.h>
-#include <linux/i2c.h>
-#include <linux/i2c-algo-bit.h>
 #include "matroxfb_base.h"
 
 struct matroxfb_dh_fb_info {
diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild
index c68e1680da01..71f8fe783258 100644
--- a/include/asm-blackfin/Kbuild
+++ b/include/asm-blackfin/Kbuild
@@ -1 +1,3 @@
 include include/asm-generic/Kbuild.asm
+
+header-y += fixed_code.h
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 57f37ccdcdf1..c4d6cbbf96d4 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -67,6 +67,18 @@ extern void evt14_softirq(void);
 extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
 extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
 
+extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
+extern char fixed_code_start;
+extern char fixed_code_end;
+extern int atomic_xchg32(void);
+extern int atomic_cas32(void);
+extern int atomic_add32(void);
+extern int atomic_sub32(void);
+extern int atomic_ior32(void);
+extern int atomic_and32(void);
+extern int atomic_xor32(void);
+extern void sigreturn_stub(void);
+
 extern void *l1_data_A_sram_alloc(size_t);
 extern void *l1_data_B_sram_alloc(size_t);
 extern void *l1_inst_sram_alloc(size_t);
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index 3bad2d1e6a8c..bec6ecdf1bdb 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -57,8 +57,8 @@ struct cplb_tab {
         u16 size;
 };
 
-u_long icplb_table[MAX_CPLBS+1];
-u_long dcplb_table[MAX_CPLBS+1];
+extern u_long icplb_table[MAX_CPLBS+1];
+extern u_long dcplb_table[MAX_CPLBS+1];
 
 /* Till here we are discussing about the static memory management model.
  * However, the operating envoronments commonly define more CPLB
@@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1];
  */
 
 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
-u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
-u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
+extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
+extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
 
 #ifdef CONFIG_CPLB_INFO
-u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
-u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
+extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
+extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
 #endif /* CONFIG_CPLB_INFO */
 
 #else
 
-u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
-u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
+extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
+extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
 
 #ifdef CONFIG_CPLB_INFO
-u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
-u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
+extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
+extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
 #endif /* CONFIG_CPLB_INFO */
 
 #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
 
-struct s_cplb {
-        struct cplb_tab init_i;
-        struct cplb_tab init_d;
-        struct cplb_tab switch_i;
-        struct cplb_tab switch_d;
-};
+extern unsigned long reserved_mem_dcache_on;
+extern unsigned long reserved_mem_icache_on;
 
-#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
-static struct cplb_desc cplb_data[] = {
-        {
-                .start = 0,
-                .end = SIZE_4K,
-                .psize = SIZE_4K,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = SDRAM_OOPS,
-                .d_conf = SDRAM_OOPS,
-#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "ZERO Pointer Saveguard",
-        },
-        {
-                .start = L1_CODE_START,
-                .end = L1_CODE_START + L1_CODE_LENGTH,
-                .psize = SIZE_4M,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB,
-                .i_conf = L1_IMEMORY,
-                .d_conf = 0,
-                .valid = 1,
-                .name = "L1 I-Memory",
-        },
-        {
-                .start = L1_DATA_A_START,
-                .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
-                .psize = SIZE_4M,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .i_conf = 0,
-                .d_conf = L1_DMEMORY,
-#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "L1 D-Memory",
-        },
-        {
-                .start = 0,
-                .end = 0,  /* dynamic */
-                .psize = 0,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf =  SDRAM_IGENERIC,
-                .d_conf =  SDRAM_DGENERIC,
-                .valid = 1,
-                .name = "SDRAM Kernel",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0, /* dynamic */
-                .psize = 0,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .i_conf =  SDRAM_IGENERIC,
-                .d_conf =  SDRAM_DNON_CHBL,
-                .valid = 1,
-                .name = "SDRAM RAM MTD",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0,   /* dynamic */
-                .psize = SIZE_1M,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .d_conf = SDRAM_DNON_CHBL,
-                .valid = 1,//(DMA_UNCACHED_REGION > 0),
-                .name = "SDRAM Uncached DMA ZONE",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0, /* dynamic */
-                .psize = 0,
-                .attr = SWITCH_T | D_CPLB,
-                .i_conf = 0, /* dynamic */
-                .d_conf = 0, /* dynamic */
-                .valid = 1,
-                .name = "SDRAM Reserved Memory",
-        },
-        {
-                .start = ASYNC_BANK0_BASE,
-                .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
-                .psize = 0,
-                .attr = SWITCH_T | D_CPLB,
-                .d_conf = SDRAM_EBIU,
-                .valid = 1,
-                .name = "ASYNC Memory",
-        },
-        {
-#if defined(CONFIG_BF561)
-                .start = L2_SRAM,
-                .end = L2_SRAM_END,
-                .psize = SIZE_1M,
-                .attr = SWITCH_T | D_CPLB,
-                .i_conf = L2_MEMORY,
-                .d_conf = L2_MEMORY,
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "L2 Memory",
-        }
-};
-#endif
+extern void generate_cpl_tables(void);
diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h
new file mode 100644
index 000000000000..e6df84ee1557
--- /dev/null
+++ b/include/asm-blackfin/fixed_code.h
@@ -0,0 +1,20 @@
+/* This file defines the fixed addresses where userspace programs can find
+   atomic code sequences.  */
+
+#define FIXED_CODE_START        0x400
+
+#define SIGRETURN_STUB          0x400
+
+#define ATOMIC_SEQS_START       0x410
+
+#define ATOMIC_XCHG32           0x410
+#define ATOMIC_CAS32            0x420
+#define ATOMIC_ADD32            0x430
+#define ATOMIC_SUB32            0x440
+#define ATOMIC_IOR32            0x450
+#define ATOMIC_AND32            0x460
+#define ATOMIC_XOR32            0x470
+
+#define ATOMIC_SEQS_END         0x480
+
+#define FIXED_CODE_END          0x480
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index d98d77ad71f7..7480cfa7e2d6 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -204,8 +204,62 @@
 
 #endif
 
+#ifdef BF548_FAMILY
+#include <asm-blackfin/mach-bf548/gpio.h>
+#endif
+
 #ifdef BF561_FAMILY
 #define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PF16       16
+#define GPIO_PF17       17
+#define GPIO_PF18       18
+#define GPIO_PF19       19
+#define GPIO_PF20       20
+#define GPIO_PF21       21
+#define GPIO_PF22       22
+#define GPIO_PF23       23
+#define GPIO_PF24       24
+#define GPIO_PF25       25
+#define GPIO_PF26       26
+#define GPIO_PF27       27
+#define GPIO_PF28       28
+#define GPIO_PF29       29
+#define GPIO_PF30       30
+#define GPIO_PF31       31
+#define GPIO_PF32       32
+#define GPIO_PF33       33
+#define GPIO_PF34       34
+#define GPIO_PF35       35
+#define GPIO_PF36       36
+#define GPIO_PF37       37
+#define GPIO_PF38       38
+#define GPIO_PF39       39
+#define GPIO_PF40       40
+#define GPIO_PF41       41
+#define GPIO_PF42       42
+#define GPIO_PF43       43
+#define GPIO_PF44       44
+#define GPIO_PF45       45
+#define GPIO_PF46       46
+#define GPIO_PF47       47
+
 #define PORT_FIO0 GPIO_0
 #define PORT_FIO1 GPIO_16
 #define PORT_FIO2 GPIO_32
@@ -230,6 +284,7 @@
 * MODIFICATION HISTORY :
 **************************************************************/
 
+#ifndef BF548_FAMILY
 void set_gpio_dir(unsigned short, unsigned short);
 void set_gpio_inen(unsigned short, unsigned short);
 void set_gpio_polar(unsigned short, unsigned short);
@@ -299,6 +354,7 @@ struct gpio_port_t {
         unsigned short dummy16;
         unsigned short inen;
 };
+#endif
 
 #ifdef CONFIG_PM
 #define PM_WAKE_RISING  0x1
@@ -357,8 +413,10 @@ void gpio_free(unsigned short);
 void gpio_set_value(unsigned short gpio, unsigned short arg);
 unsigned short gpio_get_value(unsigned short gpio);
 
+#ifndef BF548_FAMILY
 #define gpio_get_value(gpio)            get_gpio_data(gpio)
 #define gpio_set_value(gpio, value)     set_gpio_data(gpio, value)
+#endif
 
 void gpio_direction_input(unsigned short gpio);
 void gpio_direction_output(unsigned short gpio);
diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h
index 0cab0d35badc..b6b19f1b9dab 100644
--- a/include/asm-blackfin/hardirq.h
+++ b/include/asm-blackfin/hardirq.h
@@ -28,7 +28,11 @@ typedef struct {
  * SOFTIRQ_MASK: 0x00ff0000
  */
 
+#if NR_IRQS > 256
+#define HARDIRQ_BITS    9
+#else
 #define HARDIRQ_BITS    8
+#endif
 
 #ifdef NR_IRQS
 # if (1 << HARDIRQ_BITS) < NR_IRQS
diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h
new file mode 100644
index 000000000000..532bd9052004
--- /dev/null
+++ b/include/asm-blackfin/kgdb.h
@@ -0,0 +1,183 @@
+/*
+ * File:         include/asm-blackfin/kgdb.h
+ * Based on:
+ * Author:       Sonic Zhang
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:          $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
+ *
+ * Modified:
+ *               Copyright 2005-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_BLACKFIN_KGDB_H__
+#define __ASM_BLACKFIN_KGDB_H__
+
+#include <linux/ptrace.h>
+
+/* gdb locks */
+#define KGDB_MAX_NO_CPUS 8
+
+/************************************************************************/
+/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
+/* at least NUMREGBYTES*2 are needed for register packets */
+/* Longer buffer is needed to list all threads */
+#define BUFMAX 2048
+
+/*
+ *  Note that this register image is different from
+ *  the register image that Linux produces at interrupt time.
+ *  
+ *  Linux's register image is defined by struct pt_regs in ptrace.h.
+ */
+enum regnames {
+  /* Core Registers */
+  BFIN_R0 = 0,
+  BFIN_R1,
+  BFIN_R2,
+  BFIN_R3,
+  BFIN_R4,
+  BFIN_R5,
+  BFIN_R6,
+  BFIN_R7,
+  BFIN_P0,
+  BFIN_P1,
+  BFIN_P2,
+  BFIN_P3,
+  BFIN_P4,
+  BFIN_P5,
+  BFIN_SP,
+  BFIN_FP,
+  BFIN_I0,
+  BFIN_I1,
+  BFIN_I2,
+  BFIN_I3,
+  BFIN_M0,
+  BFIN_M1,
+  BFIN_M2,
+  BFIN_M3,
+  BFIN_B0,
+  BFIN_B1,
+  BFIN_B2,
+  BFIN_B3,
+  BFIN_L0,
+  BFIN_L1,
+  BFIN_L2,
+  BFIN_L3,
+  BFIN_A0_DOT_X,
+  BFIN_A0_DOT_W,
+  BFIN_A1_DOT_X,
+  BFIN_A1_DOT_W,
+  BFIN_ASTAT,
+  BFIN_RETS,
+  BFIN_LC0,
+  BFIN_LT0,
+  BFIN_LB0,
+  BFIN_LC1,
+  BFIN_LT1,
+  BFIN_LB1,
+  BFIN_CYCLES,
+  BFIN_CYCLES2,
+  BFIN_USP,
+  BFIN_SEQSTAT,
+  BFIN_SYSCFG,
+  BFIN_RETI,
+  BFIN_RETX,
+  BFIN_RETN,
+  BFIN_RETE,
+  
+  /* Pseudo Registers */
+  BFIN_PC,
+  BFIN_CC,
+  BFIN_EXTRA1,          /* Address of .text section.  */
+  BFIN_EXTRA2,          /* Address of .data section.  */
+  BFIN_EXTRA3,          /* Address of .bss section.  */
+  BFIN_FDPIC_EXEC, 
+  BFIN_FDPIC_INTERP,
+
+  /* MMRs */
+  BFIN_IPEND,
+
+  /* LAST ENTRY SHOULD NOT BE CHANGED.  */
+  BFIN_NUM_REGS         /* The number of all registers.  */
+};
+
+/* Number of bytes of registers.  */
+#define NUMREGBYTES BFIN_NUM_REGS*4
+
+#define BREAKPOINT() asm("   EXCPT 2;");
+#define BREAK_INSTR_SIZE       2
+#define HW_BREAKPOINT_NUM               6
+
+/* Instruction watchpoint address control register bits mask */
+#define WPPWR           0x1
+#define WPIREN01        0x2
+#define WPIRINV01       0x4
+#define WPIAEN0         0x8
+#define WPIAEN1         0x10
+#define WPICNTEN0       0x20
+#define WPICNTEN1       0x40
+#define EMUSW0          0x80
+#define EMUSW1          0x100
+#define WPIREN23        0x200
+#define WPIRINV23       0x400
+#define WPIAEN2         0x800
+#define WPIAEN3         0x1000
+#define WPICNTEN2       0x2000
+#define WPICNTEN3       0x4000
+#define EMUSW2          0x8000
+#define EMUSW3          0x10000
+#define WPIREN45        0x20000
+#define WPIRINV45       0x40000
+#define WPIAEN4         0x80000
+#define WPIAEN5         0x100000
+#define WPICNTEN4       0x200000
+#define WPICNTEN5       0x400000
+#define EMUSW4          0x800000
+#define EMUSW5          0x1000000
+#define WPAND           0x2000000
+
+/* Data watchpoint address control register bits mask */
+#define WPDREN01        0x1
+#define WPDRINV01       0x2
+#define WPDAEN0         0x4
+#define WPDAEN1         0x8
+#define WPDCNTEN0       0x10
+#define WPDCNTEN1       0x20
+#define WPDSRC0         0xc0
+#define WPDACC0         0x300
+#define WPDSRC1         0xc00
+#define WPDACC1         0x3000
+
+/* Watchpoint status register bits mask */
+#define STATIA0         0x1
+#define STATIA1         0x2
+#define STATIA2         0x4
+#define STATIA3         0x8
+#define STATIA4         0x10
+#define STATIA5         0x20
+#define STATDA0         0x40
+#define STATDA1         0x80
+
+extern void kgdb_print(const char *fmt, ...);
+
+#endif
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
index bd9d5e94307d..16c672c01d80 100644
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -51,4 +51,7 @@
 #define CH_MEM_STREAM1_DEST     10       /* TX */
 #define CH_MEM_STREAM1_SRC      11       /* RX */
 
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+
 #endif
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
new file mode 100644
index 000000000000..b88d7a03ee3e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -0,0 +1,65 @@
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define P_PPI0_CLK      (P_DONTCARE)
+#define P_PPI0_FS1      (P_DONTCARE)
+#define P_PPI0_FS2      (P_DONTCARE)
+#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF8))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF9))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF10))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF11))
+#define P_PPI0_D0       (P_DONTCARE)
+#define P_PPI0_D1       (P_DONTCARE)
+#define P_PPI0_D2       (P_DONTCARE)
+#define P_PPI0_D3       (P_DONTCARE)
+#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF15))
+#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF14))
+#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF13))
+#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF12))
+
+#define P_SPORT1_TSCLK  (P_DONTCARE)
+#define P_SPORT1_RSCLK  (P_DONTCARE)
+#define P_SPORT0_TSCLK  (P_DONTCARE)
+#define P_SPORT0_RSCLK  (P_DONTCARE)
+#define P_UART0_RX      (P_DONTCARE)
+#define P_UART0_TX      (P_DONTCARE)
+#define P_SPORT1_DRSEC  (P_DONTCARE)
+#define P_SPORT1_RFS    (P_DONTCARE)
+#define P_SPORT1_DTPRI  (P_DONTCARE)
+#define P_SPORT1_DTSEC  (P_DONTCARE)
+#define P_SPORT1_TFS    (P_DONTCARE)
+#define P_SPORT1_DRPRI  (P_DONTCARE)
+#define P_SPORT0_DRSEC  (P_DONTCARE)
+#define P_SPORT0_RFS    (P_DONTCARE)
+#define P_SPORT0_DTPRI  (P_DONTCARE)
+#define P_SPORT0_DTSEC  (P_DONTCARE)
+#define P_SPORT0_TFS    (P_DONTCARE)
+#define P_SPORT0_DRPRI  (P_DONTCARE)
+
+#define P_SPI0_MOSI     (P_DONTCARE)
+#define P_SPI0_MIS0     (P_DONTCARE)
+#define P_SPI0_SCK      (P_DONTCARE)
+#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
+
+#define P_TMR2          (P_DONTCARE)
+#define P_TMR1          (P_DONTCARE)
+#define P_TMR0          (P_DONTCARE)
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF1))
+
+
+
+
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
index 7a964040870a..021991984e6e 100644
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -52,4 +52,7 @@
 #define CH_MEM_STREAM1_DEST     14       /* TX */
 #define CH_MEM_STREAM1_SRC      15       /* RX */
 
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+
 #endif
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
new file mode 100644
index 000000000000..23e13c5abc4d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -0,0 +1,109 @@
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_TACLK0        (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+
+#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
+#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+
+#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
+#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
+#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
+#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
+#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
+#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
+#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
+#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
+#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
+#define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
+
+#define PORT_PJ0        (GPIO_PH15 + 1)
+#define PORT_PJ1        (GPIO_PH15 + 2)
+#define PORT_PJ2        (GPIO_PH15 + 3)
+#define PORT_PJ3        (GPIO_PH15 + 4)
+#define PORT_PJ4        (GPIO_PH15 + 5)
+#define PORT_PJ5        (GPIO_PH15 + 6)
+#define PORT_PJ6        (GPIO_PH15 + 7)
+#define PORT_PJ7        (GPIO_PH15 + 8)
+#define PORT_PJ8        (GPIO_PH15 + 9)
+#define PORT_PJ9        (GPIO_PH15 + 10)
+#define PORT_PJ10       (GPIO_PH15 + 11)
+#define PORT_PJ11       (GPIO_PH15 + 12)
+
+#define P_MDC           (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
+#define P_MDIO          (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
+#define P_TWI0_SCL      (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
+#define P_TWI0_SDA      (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
+#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
+#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
+#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
+#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
+#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
+#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
+#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
+#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
+#define P_CAN0_RX       (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
+#define P_CAN0_TX       (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
+#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
new file mode 100644
index 000000000000..aca1d4ba145c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -0,0 +1,74 @@
+
+/*
+ * File:         include/asm-blackfin/mach-bf548/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+                            slot1 and store of a P register in slot 2 is not
+                            supported */
+#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+                            Channel DMA stops */
+#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+                            registers. */
+#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
+                            Shadow of a Conditional Branch */
+#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+                            interrupt not functional */
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+                            SPORT external receive and transmit clocks. */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+                            VDDint <=0.9V */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+                            not restored */
+#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
+                            Boundary of Reserved Memory */
+#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
+                            LC Registers Are Interrupted */
+#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
+#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
+                            the USB FIFO Simultaneously */
+#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
+                            function */
+#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
+                            */
+#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
+#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
+                            Skew */
+#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
+                            of Host DMA Port */
+#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
+                            Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+
+#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
new file mode 100644
index 000000000000..9498313a2cb7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -0,0 +1,271 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/bf548.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  System MMR register and memory map for ADSP-BF548
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __MACH_BF548_H__
+#define __MACH_BF548_H__
+
+#define SUPPORTED_REVID 0
+
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR    0x0040
+#define IMASK_IVGHW             0x0020
+
+/***************************/
+
+
+#define BLKFIN_DSUBBANKS        4
+#define BLKFIN_DWAYS            2
+#define BLKFIN_DLINES           64
+#define BLKFIN_ISUBBANKS        4
+#define BLKFIN_IWAYS            4
+#define BLKFIN_ILINES           32
+
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+
+/********************************* EBIU Settings ************************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+
+#ifdef CONFIG_C_AMBEN_ALL
+#define V_AMBEN AMBEN_ALL
+#endif
+#ifdef CONFIG_C_AMBEN
+#define V_AMBEN 0x0
+#endif
+#ifdef CONFIG_C_AMBEN_B0
+#define V_AMBEN AMBEN_B0
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1
+#define V_AMBEN AMBEN_B0_B1
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1_B2
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
+
+#define MAX_VC  650000000
+#define MIN_VC  50000000
+
+/********************************PLL Settings **************************************/
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
+#if (CONFIG_VCO_MULT < 0)
+#error "VCO Multiplier is less than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT == 0)
+#error "VCO Multiplier should be greater than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT > 64)
+#error "VCO Multiplier is more than 64. Please select a different value"
+#endif
+
+#ifndef CONFIG_CLKIN_HALF
+#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+#else
+#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
+#endif
+
+#ifndef CONFIG_PLL_BYPASS
+#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
+#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
+#else
+#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
+#endif
+
+#if (CONFIG_SCLK_DIV < 1)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_SCLK_DIV > 15)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_CCLK_DIV != 1)
+#if (CONFIG_CCLK_DIV != 2)
+#if (CONFIG_CCLK_DIV != 4)
+#if (CONFIG_CCLK_DIV != 8)
+#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
+#endif
+#endif
+#endif
+#endif
+
+#if (CONFIG_VCO_HZ > MAX_VC)
+#error "VCO selected is more than maximum value. Please change the VCO multipler"
+#endif
+
+#if (CONFIG_SCLK_HZ > 133000000)
+#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ < 27000000)
+#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
+#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
+#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
+#error "Please select sclk less than cclk"
+#endif
+#endif
+#endif
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+#endif  /* CONFIG_BFIN_KERNEL_CLOCK */
+
+#ifdef CONFIG_BF542
+#define CPU "BF542"
+#define CPUID 0x027c8000
+#endif
+#ifdef CONFIG_BF544
+#define CPU "BF544"
+#define CPUID 0x027c8000
+#endif
+#ifdef CONFIG_BF548
+#define CPU "BF548"
+#define CPUID 0x027c6000
+#endif
+#ifdef CONFIG_BF549
+#define CPU "BF549"
+#endif
+#ifndef CPU
+#define CPU "UNKNOWN"
+#define CPUID 0x0
+#endif
+
+#if (CONFIG_MEM_SIZE % 4)
+#error "SDRAM mem size must be multible of 4MB"
+#endif
+
+#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
+#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
+#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158_WORKAROUND             0x200
+#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else                           /*Write Through */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
+#endif
+
+
+#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
+#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
+#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
+#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
+
+#define SIZE_1K 0x00000400      /* 1K */
+#define SIZE_4K 0x00001000      /* 4K */
+#define SIZE_1M 0x00100000      /* 1M */
+#define SIZE_4M 0x00400000      /* 4M */
+
+#define MAX_CPLBS (16 * 2)
+
+/*
+* Number of required data CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 16 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Data Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+* 1 for ASYNC Memory
+*/
+
+
+#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
+
+/*
+* Number of required instruction CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 12 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Instruction Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+*/
+
+#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
+
+#endif  /* __MACH_BF48_H__  */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
new file mode 100644
index 000000000000..2f4afc90db11
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -0,0 +1,193 @@
+#include <linux/serial.h>
+#include <asm/dma.h>
+
+#define NR_PORTS                4
+
+#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
+#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
+#define OFFSET_GCTL             0x08    /* Global Control Register              */
+#define OFFSET_LCR              0x0C    /* Line Control Register                */
+#define OFFSET_MCR              0x10    /* Modem Control Register               */
+#define OFFSET_LSR              0x14    /* Line Status Register                 */
+#define OFFSET_MSR              0x18    /* Modem Status Register                */
+#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
+#define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
+#define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
+#define OFFSET_THR              0x28    /* Transmit Holding register            */
+#define OFFSET_RBR              0x2C    /* Receive Buffer register              */
+
+#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
+#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
+#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
+#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
+#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
+#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
+#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+
+#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
+#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
+#define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
+#define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
+#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
+#define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
+#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
+#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
+# define CONFIG_SERIAL_BFIN_CTSRTS
+
+# ifndef CONFIG_UART0_CTS_PIN
+#  define CONFIG_UART0_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART0_RTS_PIN
+#  define CONFIG_UART0_RTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_CTS_PIN
+#  define CONFIG_UART1_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_RTS_PIN
+#  define CONFIG_UART1_RTS_PIN -1
+# endif
+#endif
+/*
+ * The pin configuration is different from schematic
+ */
+struct bfin_serial_port {
+        struct uart_port        port;
+        unsigned int            old_status;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int                     tx_done;
+        int                     tx_count;
+        struct circ_buf         rx_dma_buf;
+        struct timer_list       rx_dma_timer;
+        int                     rx_dma_nrows;
+        unsigned int            tx_dma_channel;
+        unsigned int            rx_dma_channel;
+        struct work_struct      tx_dma_workqueue;
+#else
+        struct work_struct      cts_workqueue;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int             cts_pin;
+        int             rts_pin;
+#endif
+};
+
+struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_res {
+        unsigned long   uart_base_addr;
+        int             uart_irq;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        unsigned int    uart_tx_dma_channel;
+        unsigned int    uart_rx_dma_channel;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int     uart_cts_pin;
+        int     uart_rts_pin;
+#endif
+};
+
+struct bfin_serial_res bfin_serial_resource[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+        0xFFC00400,
+        IRQ_UART0_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART0_TX,
+        CH_UART0_RX,
+#endif
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        CONFIG_UART0_CTS_PIN,
+        CONFIG_UART0_RTS_PIN,
+#endif
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+        0xFFC02000,
+        IRQ_UART1_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART1_TX,
+        CH_UART1_RX,
+#endif
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART2
+        {
+        0xFFC02100,
+        IRQ_UART2_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART2_TX,
+        CH_UART2_RX,
+#endif
+#ifdef CONFIG_BFIN_UART2_CTSRTS
+        CONFIG_UART2_CTS_PIN,
+        CONFIG_UART2_RTS_PIN,
+#endif
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART3
+        {
+        0xFFC03100,
+        IRQ_UART3_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART3_TX,
+        CH_UART3_RX,
+#endif
+        },
+#endif
+};
+
+int nr_ports = ARRAY_SIZE(bfin_serial_resource);
+
+static void bfin_serial_hw_init(struct bfin_serial_port *uart)
+{
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
+        bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
+        bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
+        bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
+        bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+        /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
+        bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
+        bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
+#endif
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_UART2
+        /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
+        bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
+        bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_UART3
+        /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
+        bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
+        bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
+#ifdef CONFIG_BFIN_UART3_CTSRTS
+        /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
+        bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
+        bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
+#endif
+#endif
+        SSYNC();
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        if (uart->cts_pin >= 0) {
+                gpio_request(uart->cts_pin, NULL);
+                gpio_direction_input(uart->cts_pin);
+        }
+
+        if (uart->rts_pin >= 0) {
+                gpio_request(uart->rts_pin, NULL);
+                gpio_direction_output(uart->rts_pin);
+        }
+#endif
+}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
new file mode 100644
index 000000000000..791218fe7d94
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -0,0 +1,168 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/blackfin.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+
+#define BF548_FAMILY
+
+#include "bf548.h"
+#include "mem_map.h"
+#include "anomaly.h"
+
+#ifdef CONFIG_BF542
+#include "defBF542.h"
+#endif
+
+#ifdef CONFIG_BF544
+#include "defBF544.h"
+#endif
+
+#ifdef CONFIG_BF548
+#include "defBF548.h"
+#endif
+
+#ifdef CONFIG_BF549
+#include "defBF549.h"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#ifdef CONFIG_BF542
+#include "cdefBF542.h"
+#endif
+
+#ifdef CONFIG_BF544
+#include "cdefBF544.h"
+#endif
+#ifdef CONFIG_BF548
+#include "cdefBF548.h"
+#endif
+#ifdef CONFIG_BF549
+#include "cdefBF549.h"
+#endif
+
+/* UART 1*/
+#define bfin_read_UART_THR()            bfin_read_UART1_THR()
+#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
+#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
+#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
+#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
+#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
+#define bfin_read_UART_IER()            bfin_read_UART1_IER()
+#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
+#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
+#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
+#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
+#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
+#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
+#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
+#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
+#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
+#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
+#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
+#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
+#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
+#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
+#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
+
+#endif
+
+/* MAP used DEFINES from BF533 to BF54x - so we don't need to change 
+ * them in the driver, kernel, etc. */
+
+/* UART_IIR Register */
+#define STATUS(x)       ((x << 1) & 0x06)
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+
+/* UART 0*/
+
+/* DMA Channnel */
+#define bfin_read_CH_UART_RX()          bfin_read_CH_UART1_RX()
+#define bfin_write_CH_UART_RX(val)      bfin_write_CH_UART1_RX(val)
+#define bfin_read_CH_UART_TX()          bfin_read_CH_UART1_TX()
+#define bfin_write_CH_UART_TX(val)      bfin_write_CH_UART1_TX(val)
+#define CH_UART_RX                      CH_UART1_RX
+#define CH_UART_TX                      CH_UART1_TX
+
+/* System Interrupt Controller */
+#define bfin_read_IRQ_UART_RX()         bfin_read_IRQ_UART1_RX()
+#define bfin_write_IRQ_UART_RX(val)     bfin_write_IRQ_UART1_RX(val)
+#define bfin_read_IRQ_UART_TX()         bfin_read_IRQ_UART1_TX()
+#define bfin_write_IRQ_UART_TX(val)     bfin_write_IRQ_UART1_TX(val)
+#define bfin_read_IRQ_UART_ERROR()      bfin_read_IRQ_UART1_ERROR()
+#define bfin_write_IRQ_UART_ERROR(val)  bfin_write_IRQ_UART1_ERROR(val)
+#define IRQ_UART_RX                     IRQ_UART1_RX
+#define IRQ_UART_TX                     IRQ_UART1_TX
+#define IRQ_UART_ERROR                  IRQ_UART1_ERROR
+
+/* MMR Registers*/
+#define bfin_read_UART_THR()            bfin_read_UART1_THR()
+#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
+#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
+#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
+#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
+#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
+#define bfin_read_UART_IER()            bfin_read_UART1_IER()
+#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
+#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
+#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
+#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
+#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
+#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
+#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
+#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
+#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
+#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
+#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
+#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
+#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
+#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
+#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
+#define UART_THR                        UART1_THR
+#define UART_RBR                        UART1_RBR
+#define UART_DLL                        UART1_DLL
+#define UART_IER                        UART1_IER
+#define UART_DLH                        UART1_DLH
+#define UART_IIR                        UART1_IIR
+#define UART_LCR                        UART1_LCR
+#define UART_MCR                        UART1_MCR
+#define UART_LSR                        UART1_LSR
+#define UART_SCR                        UART1_SCR
+#define UART_GCTL                       UART1_GCTL
+
+/* PLL_DIV Masks */
+#define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
+#define CCLK_DIV2 CSEL_DIV2     /* CCLK = VCO / 2 */
+#define CCLK_DIV4 CSEL_DIV4     /* CCLK = VCO / 4 */
+#define CCLK_DIV8 CSEL_DIV8     /* CCLK = VCO / 8 */
+
+#endif
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 6bbcefeb3627..98d35a929116 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -31,7 +31,8 @@
 #ifndef _CDEF_BF54X_H
 #define _CDEF_BF54X_H
 
-#include <defBF54x_base.h>
+#include "defBF54x_base.h"
+#include <asm/system.h>
 
 /* ************************************************************** */
 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
@@ -44,7 +45,30 @@
 #define bfin_read_PLL_DIV()             bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)         bfin_write16(PLL_DIV, val)
 #define bfin_read_VR_CTL()              bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)          bfin_write16(VR_CTL, val)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1, iwr2;
+
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        iwr2 = bfin_read32(SIC_IWR2);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+        bfin_write32(SIC_IWR2, 0);
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+
+        local_irq_save(flags);
+        asm("IDLE;");
+        local_irq_restore(flags);
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        bfin_write32(SIC_IWR2, iwr2);
+}
 #define bfin_read_PLL_STAT()            bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)        bfin_write16(PLL_STAT, val)
 #define bfin_read_PLL_LOCKCNT()         bfin_read16(PLL_LOCKCNT)
@@ -70,12 +94,18 @@
 #define bfin_write_SIC_IMASK1(val)      bfin_write32(SIC_IMASK1, val)
 #define bfin_read_SIC_IMASK2()          bfin_read32(SIC_IMASK2)
 #define bfin_write_SIC_IMASK2(val)      bfin_write32(SIC_IMASK2, val)
+#define bfin_read_SIC_IMASK(x)          bfin_read32(SIC_IMASK0 + (x << 2))
+#define bfin_write_SIC_IMASK(x, val)    bfin_write32((SIC_IMASK0 + (x << 2)), val)
+
 #define bfin_read_SIC_ISR0()            bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)        bfin_write32(SIC_ISR0, val)
 #define bfin_read_SIC_ISR1()            bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)        bfin_write32(SIC_ISR1, val)
 #define bfin_read_SIC_ISR2()            bfin_read32(SIC_ISR2)
 #define bfin_write_SIC_ISR2(val)        bfin_write32(SIC_ISR2, val)
+#define bfin_read_SIC_ISR(x)            bfin_read32(SIC_ISR0 + (x << 2))
+#define bfin_write_SIC_ISR(x, val)      bfin_write32((SIC_ISR0 + (x << 2)), val)
+
 #define bfin_read_SIC_IWR0()            bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)        bfin_write32(SIC_IWR0, val)
 #define bfin_read_SIC_IWR1()            bfin_read32(SIC_IWR1)
@@ -710,21 +740,21 @@
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
 #define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
 #define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
 #define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
 #define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
 #define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
 #define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
 #define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
 #define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
@@ -734,23 +764,23 @@
 #define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
 #define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
 #define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
 #define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
 #define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
 #define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
 #define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
 #define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
 #define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
 #define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
@@ -763,9 +793,9 @@
 /* MDMA Stream 1 Registers */
 
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
 #define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
 #define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
 #define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
@@ -777,9 +807,9 @@
 #define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY)
 #define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
 #define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
 #define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
@@ -789,9 +819,9 @@
 #define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
 #define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
 #define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
 #define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
@@ -803,9 +833,9 @@
 #define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY)
 #define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
 #define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
 #define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index ac968fca5cc5..32d07130200c 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -362,7 +362,6 @@
 /* Bit masks for KPAD_CTL */
 
 #define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0       
 #define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
 #define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
 #define                KPAD_COLEN  0xe000     /* Column Enable Width */
@@ -384,29 +383,21 @@
 /* Bit masks for KPAD_STAT */
 
 #define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0       
 #define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
 #define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0       
 
 /* Bit masks for KPAD_SOFTEVAL */
 
 #define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0       
 
 /* Bit masks for SDH_COMMAND */
 
 #define                   CMD_IDX  0x3f       /* Command Index */
 #define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0       
 #define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0       
 #define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0       
 #define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0       
 #define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0       
 
 /* Bit masks for SDH_PWR_CTL */
 
@@ -415,21 +406,15 @@
 #define                       TBD  0x3c       /* TBD */
 #endif
 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0       
 #define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0       
 
 /* Bit masks for SDH_CLK_CTL */
 
 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0       
 #define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0       
 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0       
 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0       
 
 /* Bit masks for SDH_RESP_CMD */
 
@@ -438,133 +423,74 @@
 /* Bit masks for SDH_DATA_CTL */
 
 #define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0       
 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0       
 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0       
 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0       
 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 
 /* Bit masks for SDH_STATUS */
 
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0       
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0       
 #define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0       
 #define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0       
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0       
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0       
 #define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0       
 #define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0       
 #define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0       
 #define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0       
 #define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0       
 #define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0       
 #define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0       
 #define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0       
 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0       
 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0       
 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0       
 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0       
 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0       
 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0       
 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0       
 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0       
 
 /* Bit masks for SDH_STATUS_CLR */
 
 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0       
 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0       
 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0       
 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0       
 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0       
 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0       
 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0       
 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0       
 #define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0       
 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0       
 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0       
 
 /* Bit masks for SDH_MASK0 */
 
 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0       
 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0       
 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0       
 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0       
 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0       
 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0       
 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0       
 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0       
 #define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0       
 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0       
 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0       
 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0       
 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0       
 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0       
 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0       
 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0       
 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0       
 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0       
 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0       
 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0       
 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0       
 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0       
 
 /* Bit masks for SDH_FIFO_CNT */
 
@@ -573,73 +499,47 @@
 /* Bit masks for SDH_E_STATUS */
 
 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0       
 #define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0       
 
 /* Bit masks for SDH_E_MASK */
 
 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0       
 #define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0       
 
 /* Bit masks for SDH_CFG */
 
 #define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0       
 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0       
 #define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0       
 #define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0       
 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0       
 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0       
 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0       
 
 /* Bit masks for SDH_RD_WAIT_EN */
 
 #define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0       
 
 /* Bit masks for ATAPI_CONTROL */
 
 #define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0       
 #define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0       
 #define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0       
 #define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0       
 #define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0       
 #define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0       
 #define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0       
 #define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0       
 #define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0       
 #define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0       
 #define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0       
 #define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
 
 /* Bit masks for ATAPI_STATUS */
 
 #define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0       
 #define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0       
 #define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0       
 #define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
 
 /* Bit masks for ATAPI_DEV_ADDR */
@@ -649,66 +549,39 @@
 /* Bit masks for ATAPI_INT_MASK */
 
 #define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0       
 #define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0       
 #define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0       
 #define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0       
 #define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0       
 #define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0       
 #define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0       
 #define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0       
 #define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0       
 
 /* Bit masks for ATAPI_INT_STATUS */
 
 #define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0       
 #define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0       
 #define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0       
 #define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0       
 #define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0       
 #define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0       
 #define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0       
 #define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0       
 #define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0       
 
 /* Bit masks for ATAPI_LINE_STATUS */
 
 #define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0       
 #define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0       
 #define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0       
 #define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0       
 #define                ATAPI_ADDR  0x70       /* ATAPI address line status */
 #define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0       
 #define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0       
 #define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0       
 #define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0       
 #define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0       
 
 /* Bit masks for ATAPI_SM_STATE */
 
@@ -720,7 +593,6 @@
 /* Bit masks for ATAPI_TERMINATE */
 
 #define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0       
 
 /* Bit masks for ATAPI_REG_TIM_0 */
 
@@ -779,131 +651,77 @@
 /* Bit masks for USB_POWER */
 
 #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
 #define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
 #define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
 #define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
 #define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
 #define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
 #define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
 #define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
 
 /* Bit masks for USB_INTRTX */
 
 #define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
 #define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
 #define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
 #define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
 #define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
 #define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
 #define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
 #define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
 
 /* Bit masks for USB_INTRRX */
 
 #define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
 #define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
 #define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
 #define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
 #define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
 #define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
 #define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
 
 /* Bit masks for USB_INTRTXE */
 
 #define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
 #define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
 #define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
 #define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
 #define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
 #define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
 #define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
 #define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
 
 /* Bit masks for USB_INTRRXE */
 
 #define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
 #define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
 #define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
 #define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
 #define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
 #define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
 #define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
 
 /* Bit masks for USB_INTRUSB */
 
 #define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
 #define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
 #define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
 #define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
 #define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
 #define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
 #define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
 #define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
 
 /* Bit masks for USB_INTRUSBE */
 
 #define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
 #define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
 #define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
 #define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
 #define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
 #define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
 #define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
 #define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
 
 /* Bit masks for USB_FRAME */
 
@@ -916,117 +734,67 @@
 /* Bit masks for USB_GLOBAL_CTL */
 
 #define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
 #define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
 #define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
 #define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
 #define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
 #define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
 #define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
 #define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
 #define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
 #define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
 #define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
 #define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
 #define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
 #define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
 #define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
 
 /* Bit masks for USB_OTG_DEV_CTL */
 
 #define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
 #define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
 #define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
 #define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
 #define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
 #define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
 #define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
 #define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
 
 /* Bit masks for USB_OTG_VBUS_IRQ */
 
 #define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
 #define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
 #define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
 #define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
 #define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
 #define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
 
 /* Bit masks for USB_OTG_VBUS_MASK */
 
 #define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
 #define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
 #define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
 #define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
 #define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
 #define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
 
 /* Bit masks for USB_CSR0 */
 
 #define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
 #define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
 #define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
 #define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
 #define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
 #define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
 #define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
 #define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
 #define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
 #define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
 #define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
 #define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
 #define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
 #define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
 #define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
 
 /* Bit masks for USB_COUNT0 */
 
@@ -1047,37 +815,21 @@
 /* Bit masks for USB_TXCSR */
 
 #define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
 #define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
 #define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
 #define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
 #define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
 #define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
 #define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
 #define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
 #define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
 #define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
 #define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
 #define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
 #define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
 #define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
 #define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
 #define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
 
 /* Bit masks for USB_TXCOUNT */
 
@@ -1086,45 +838,25 @@
 /* Bit masks for USB_RXCSR */
 
 #define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
 #define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
 #define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
 #define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
 #define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
 #define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
 #define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
 #define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
 #define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
 #define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
 #define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
 #define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
 #define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
 #define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
 #define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
 #define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
 #define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
 #define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
 #define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
 #define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
 
 /* Bit masks for USB_RXCOUNT */
 
@@ -1151,35 +883,22 @@
 /* Bit masks for USB_DMA_INTERRUPT */
 
 #define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
 #define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
 #define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
 #define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
 #define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
 #define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
 #define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
 #define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
 
 /* Bit masks for USB_DMAxCONTROL */
 
 #define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
 #define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
 #define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
 #define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
 #define                     EPNUM  0xf0       /* EP number */
 #define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
 
 /* Bit masks for USB_DMAxADDRHIGH */
 
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 8fc77ea12aa9..dd955dcd39b8 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -538,21 +538,13 @@
 /* Bit masks for PIXC_CTL */
 
 #define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0       
 #define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0       
 #define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0       
 #define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0       
 #define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0       
 #define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0       
 #define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0       
 #define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0       
 #define                  IMG_STAT  0x300      /* Image FIFO Status */
 #define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
 #define                    WM_LVL  0x3000     /* FIFO Watermark Level */
@@ -600,13 +592,9 @@
 /* Bit masks for PIXC_INTRSTAT */
 
 #define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0       
 #define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0       
 #define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0       
 #define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0       
 
 /* Bit masks for PIXC_RYCON */
 
@@ -614,7 +602,6 @@
 #define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
 #define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
 #define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0       
 
 /* Bit masks for PIXC_GUCON */
 
@@ -622,7 +609,6 @@
 #define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
 #define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
 #define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0       
 
 /* Bit masks for PIXC_BVCON */
 
@@ -630,7 +616,6 @@
 #define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
 #define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
 #define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0       
 
 /* Bit masks for PIXC_CCBIAS */
 
@@ -647,48 +632,28 @@
 /* Bit masks for HOST_CONTROL */
 
 #define                   HOST_EN  0x1        /* Host Enable */
-#define                  nHOST_EN  0x0       
 #define                  HOST_END  0x2        /* Host Endianess */
-#define                 nHOST_END  0x0       
 #define                 DATA_SIZE  0x4        /* Data Size */
-#define                nDATA_SIZE  0x0       
 #define                  HOST_RST  0x8        /* Host Reset */
-#define                 nHOST_RST  0x0       
 #define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                 nHRDY_OVR  0x0       
 #define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0       
 #define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0       
 #define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0       
 #define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0       
 #define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0       
 
 /* Bit masks for HOST_STATUS */
 
 #define                     READY  0x1        /* DMA Ready */
-#define                    nREADY  0x0       
 #define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0       
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0       
 #define                  COMPLETE  0x8        /* DMA Complete */
-#define                 nCOMPLETE  0x0       
 #define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0       
 #define                   TIMEOUT  0x20       /* Host Timeout */
-#define                  nTIMEOUT  0x0       
 #define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0       
 #define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0       
 #define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0       
 #define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0       
 
 /* Bit masks for HOST_TIMEOUT */
 
@@ -697,67 +662,42 @@
 /* Bit masks for TIMER_ENABLE1 */
 
 #define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0       
 #define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0       
 #define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0       
 
 /* Bit masks for TIMER_DISABLE1 */
 
 #define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0       
 #define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0       
 #define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0       
 
 /* Bit masks for TIMER_STATUS1 */
 
 #define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0       
 #define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0       
 #define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0       
 #define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0       
 #define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0       
 #define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0       
 #define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0       
 #define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0       
 #define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0       
 
 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
 
 /* Bit masks for HMDMAx_CONTROL */
 
 #define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                  nHMDMAEN  0x0       
 #define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                      nREP  0x0       
 #define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                      nUTE  0x0       
 #define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      nOIE  0x0       
 #define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                     nBDIE  0x0       
 #define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                     nMBDI  0x0       
 #define                       DRQ  0x300      /* Handshake MDMA Request Type */
 #define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                      nRBC  0x0       
 #define                        PS  0x2000     /* Pin Status */
-#define                       nPS  0x0       
 #define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       nOI  0x0       
 #define                       BDI  0x8000     /* Block Done Interrupt Generated */
-#define                      nBDI  0x0       
 
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index d9e3062a9117..8d4214e0807c 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -899,21 +899,13 @@
 /* Bit masks for PIXC_CTL */
 
 #define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0       
 #define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0       
 #define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0       
 #define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0       
 #define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0       
 #define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0       
 #define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0       
 #define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0       
 #define                  IMG_STAT  0x300      /* Image FIFO Status */
 #define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
 #define                    WM_LVL  0x3000     /* FIFO Watermark Level */
@@ -961,13 +953,9 @@
 /* Bit masks for PIXC_INTRSTAT */
 
 #define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0       
 #define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0       
 #define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0       
 #define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0       
 
 /* Bit masks for PIXC_RYCON */
 
@@ -975,7 +963,6 @@
 #define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
 #define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
 #define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0       
 
 /* Bit masks for PIXC_GUCON */
 
@@ -983,7 +970,6 @@
 #define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
 #define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
 #define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0       
 
 /* Bit masks for PIXC_BVCON */
 
@@ -991,7 +977,6 @@
 #define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
 #define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
 #define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0       
 
 /* Bit masks for PIXC_CCBIAS */
 
@@ -1008,48 +993,28 @@
 /* Bit masks for HOST_CONTROL */
 
 #define                   HOST_EN  0x1        /* Host Enable */
-#define                  nHOST_EN  0x0       
 #define                  HOST_END  0x2        /* Host Endianess */
-#define                 nHOST_END  0x0       
 #define                 DATA_SIZE  0x4        /* Data Size */
-#define                nDATA_SIZE  0x0       
 #define                  HOST_RST  0x8        /* Host Reset */
-#define                 nHOST_RST  0x0       
 #define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                 nHRDY_OVR  0x0       
 #define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0       
 #define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0       
 #define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0       
 #define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0       
 #define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0       
 
 /* Bit masks for HOST_STATUS */
 
 #define                     READY  0x1        /* DMA Ready */
-#define                    nREADY  0x0       
 #define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0       
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0       
 #define                  COMPLETE  0x8        /* DMA Complete */
-#define                 nCOMPLETE  0x0       
 #define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0       
 #define                   TIMEOUT  0x20       /* Host Timeout */
-#define                  nTIMEOUT  0x0       
 #define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0       
 #define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0       
 #define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0       
 #define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0       
 
 /* Bit masks for HOST_TIMEOUT */
 
@@ -1058,7 +1023,6 @@
 /* Bit masks for KPAD_CTL */
 
 #define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0       
 #define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
 #define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
 #define                KPAD_COLEN  0xe000     /* Column Enable Width */
@@ -1080,29 +1044,21 @@
 /* Bit masks for KPAD_STAT */
 
 #define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0       
 #define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
 #define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0       
 
 /* Bit masks for KPAD_SOFTEVAL */
 
 #define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0       
 
 /* Bit masks for SDH_COMMAND */
 
 #define                   CMD_IDX  0x3f       /* Command Index */
 #define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0       
 #define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0       
 #define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0       
 #define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0       
 #define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0       
 
 /* Bit masks for SDH_PWR_CTL */
 
@@ -1111,21 +1067,15 @@
 #define                       TBD  0x3c       /* TBD */
 #endif
 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0       
 #define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0       
 
 /* Bit masks for SDH_CLK_CTL */
 
 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0       
 #define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0       
 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0       
 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0       
 
 /* Bit masks for SDH_RESP_CMD */
 
@@ -1134,133 +1084,74 @@
 /* Bit masks for SDH_DATA_CTL */
 
 #define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0       
 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0       
 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0       
 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0       
 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 
 /* Bit masks for SDH_STATUS */
 
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0       
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0       
 #define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0       
 #define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0       
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0       
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0       
 #define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0       
 #define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0       
 #define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0       
 #define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0       
 #define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0       
 #define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0       
 #define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0       
 #define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0       
 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0       
 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0       
 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0       
 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0       
 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0       
 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0       
 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0       
 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0       
 
 /* Bit masks for SDH_STATUS_CLR */
 
 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0       
 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0       
 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0       
 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0       
 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0       
 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0       
 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0       
 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0       
 #define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0       
 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0       
 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0       
 
 /* Bit masks for SDH_MASK0 */
 
 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0       
 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0       
 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0       
 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0       
 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0       
 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0       
 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0       
 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0       
 #define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0       
 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0       
 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0       
 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0       
 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0       
 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0       
 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0       
 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0       
 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0       
 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0       
 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0       
 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0       
 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0       
 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0       
 
 /* Bit masks for SDH_FIFO_CNT */
 
@@ -1269,73 +1160,47 @@
 /* Bit masks for SDH_E_STATUS */
 
 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0       
 #define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0       
 
 /* Bit masks for SDH_E_MASK */
 
 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0       
 #define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0       
 
 /* Bit masks for SDH_CFG */
 
 #define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0       
 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0       
 #define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0       
 #define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0       
 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0       
 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0       
 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0       
 
 /* Bit masks for SDH_RD_WAIT_EN */
 
 #define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0       
 
 /* Bit masks for ATAPI_CONTROL */
 
 #define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0       
 #define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0       
 #define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0       
 #define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0       
 #define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0       
 #define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0       
 #define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0       
 #define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0       
 #define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0       
 #define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0       
 #define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0       
 #define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
 
 /* Bit masks for ATAPI_STATUS */
 
 #define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0       
 #define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0       
 #define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0       
 #define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
 
 /* Bit masks for ATAPI_DEV_ADDR */
@@ -1345,66 +1210,39 @@
 /* Bit masks for ATAPI_INT_MASK */
 
 #define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0       
 #define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0       
 #define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0       
 #define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0       
 #define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0       
 #define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0       
 #define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0       
 #define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0       
 #define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0       
 
 /* Bit masks for ATAPI_INT_STATUS */
 
 #define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0       
 #define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0       
 #define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0       
 #define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0       
 #define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0       
 #define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0       
 #define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0       
 #define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0       
 #define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0       
 
 /* Bit masks for ATAPI_LINE_STATUS */
 
 #define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0       
 #define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0       
 #define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0       
 #define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0       
 #define                ATAPI_ADDR  0x70       /* ATAPI address line status */
 #define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0       
 #define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0       
 #define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0       
 #define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0       
 #define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0       
 
 /* Bit masks for ATAPI_SM_STATE */
 
@@ -1416,7 +1254,6 @@
 /* Bit masks for ATAPI_TERMINATE */
 
 #define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0       
 
 /* Bit masks for ATAPI_REG_TIM_0 */
 
@@ -1471,41 +1308,26 @@
 /* Bit masks for TIMER_ENABLE1 */
 
 #define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0       
 #define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0       
 #define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0       
 
 /* Bit masks for TIMER_DISABLE1 */
 
 #define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0       
 #define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0       
 #define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0       
 
 /* Bit masks for TIMER_STATUS1 */
 
 #define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0       
 #define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0       
 #define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0       
 #define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0       
 #define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0       
 #define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0       
 #define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0       
 #define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0       
 #define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0       
 
 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
 
@@ -1516,131 +1338,77 @@
 /* Bit masks for USB_POWER */
 
 #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
 #define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
 #define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
 #define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
 #define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
 #define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
 #define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
 #define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
 
 /* Bit masks for USB_INTRTX */
 
 #define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
 #define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
 #define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
 #define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
 #define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
 #define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
 #define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
 #define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
 
 /* Bit masks for USB_INTRRX */
 
 #define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
 #define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
 #define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
 #define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
 #define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
 #define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
 #define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
 
 /* Bit masks for USB_INTRTXE */
 
 #define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
 #define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
 #define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
 #define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
 #define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
 #define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
 #define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
 #define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
 
 /* Bit masks for USB_INTRRXE */
 
 #define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
 #define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
 #define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
 #define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
 #define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
 #define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
 #define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
 
 /* Bit masks for USB_INTRUSB */
 
 #define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
 #define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
 #define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
 #define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
 #define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
 #define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
 #define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
 #define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
 
 /* Bit masks for USB_INTRUSBE */
 
 #define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
 #define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
 #define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
 #define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
 #define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
 #define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
 #define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
 #define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
 
 /* Bit masks for USB_FRAME */
 
@@ -1653,117 +1421,67 @@
 /* Bit masks for USB_GLOBAL_CTL */
 
 #define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
 #define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
 #define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
 #define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
 #define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
 #define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
 #define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
 #define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
 #define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
 #define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
 #define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
 #define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
 #define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
 #define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
 #define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
 
 /* Bit masks for USB_OTG_DEV_CTL */
 
 #define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
 #define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
 #define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
 #define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
 #define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
 #define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
 #define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
 #define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
 
 /* Bit masks for USB_OTG_VBUS_IRQ */
 
 #define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
 #define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
 #define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
 #define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
 #define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
 #define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
 
 /* Bit masks for USB_OTG_VBUS_MASK */
 
 #define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
 #define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
 #define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
 #define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
 #define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
 #define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
 
 /* Bit masks for USB_CSR0 */
 
 #define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
 #define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
 #define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
 #define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
 #define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
 #define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
 #define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
 #define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
 #define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
 #define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
 #define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
 #define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
 #define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
 #define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
 #define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
 
 /* Bit masks for USB_COUNT0 */
 
@@ -1784,37 +1502,21 @@
 /* Bit masks for USB_TXCSR */
 
 #define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
 #define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
 #define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
 #define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
 #define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
 #define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
 #define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
 #define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
 #define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
 #define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
 #define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
 #define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
 #define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
 #define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
 #define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
 #define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
 
 /* Bit masks for USB_TXCOUNT */
 
@@ -1823,45 +1525,25 @@
 /* Bit masks for USB_RXCSR */
 
 #define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
 #define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
 #define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
 #define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
 #define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
 #define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
 #define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
 #define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
 #define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
 #define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
 #define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
 #define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
 #define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
 #define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
 #define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
 #define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
 #define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
 #define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
 #define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
 #define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
 
 /* Bit masks for USB_RXCOUNT */
 
@@ -1888,35 +1570,22 @@
 /* Bit masks for USB_DMA_INTERRUPT */
 
 #define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
 #define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
 #define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
 #define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
 #define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
 #define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
 #define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
 #define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
 
 /* Bit masks for USB_DMAxCONTROL */
 
 #define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
 #define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
 #define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
 #define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
 #define                     EPNUM  0xf0       /* EP number */
 #define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
 
 /* Bit masks for USB_DMAxADDRHIGH */
 
@@ -1937,26 +1606,16 @@
 /* Bit masks for HMDMAx_CONTROL */
 
 #define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                  nHMDMAEN  0x0       
 #define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                      nREP  0x0       
 #define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                      nUTE  0x0       
 #define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      nOIE  0x0       
 #define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                     nBDIE  0x0       
 #define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                     nMBDI  0x0       
 #define                       DRQ  0x300      /* Handshake MDMA Request Type */
 #define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                      nRBC  0x0       
 #define                        PS  0x2000     /* Pin Status */
-#define                       nPS  0x0       
 #define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       nOI  0x0       
 #define                       BDI  0x8000     /* Block Done Interrupt Generated */
-#define                      nBDI  0x0       
 
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index b1cc1c073b41..c2f4734da48d 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -1070,21 +1070,13 @@
 /* Bit masks for PIXC_CTL */
 
 #define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0       
 #define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0       
 #define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0       
 #define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0       
 #define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0       
 #define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0       
 #define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0       
 #define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0       
 #define                  IMG_STAT  0x300      /* Image FIFO Status */
 #define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
 #define                    WM_LVL  0x3000     /* FIFO Watermark Level */
@@ -1132,13 +1124,9 @@
 /* Bit masks for PIXC_INTRSTAT */
 
 #define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0       
 #define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0       
 #define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0       
 #define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0       
 
 /* Bit masks for PIXC_RYCON */
 
@@ -1146,7 +1134,6 @@
 #define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
 #define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
 #define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0       
 
 /* Bit masks for PIXC_GUCON */
 
@@ -1154,7 +1141,6 @@
 #define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
 #define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
 #define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0       
 
 /* Bit masks for PIXC_BVCON */
 
@@ -1162,7 +1148,6 @@
 #define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
 #define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
 #define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0       
 
 /* Bit masks for PIXC_CCBIAS */
 
@@ -1179,48 +1164,28 @@
 /* Bit masks for HOST_CONTROL */
 
 #define                   HOST_EN  0x1        /* Host Enable */
-#define                  nHOST_EN  0x0       
 #define                  HOST_END  0x2        /* Host Endianess */
-#define                 nHOST_END  0x0       
 #define                 DATA_SIZE  0x4        /* Data Size */
-#define                nDATA_SIZE  0x0       
 #define                  HOST_RST  0x8        /* Host Reset */
-#define                 nHOST_RST  0x0       
 #define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                 nHRDY_OVR  0x0       
 #define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0       
 #define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0       
 #define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0       
 #define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0       
 #define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0       
 
 /* Bit masks for HOST_STATUS */
 
 #define                     READY  0x1        /* DMA Ready */
-#define                    nREADY  0x0       
 #define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0       
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0       
-#define                  COMPLETE  0x8        /* DMA Complete */
-#define                 nCOMPLETE  0x0       
+#define              DMA_COMPLETE  0x8        /* DMA Complete */
 #define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0       
 #define                   TIMEOUT  0x20       /* Host Timeout */
-#define                  nTIMEOUT  0x0       
 #define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0       
 #define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0       
 #define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0       
 #define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0       
 
 /* Bit masks for HOST_TIMEOUT */
 
@@ -1229,71 +1194,41 @@
 /* Bit masks for MXVR_CONFIG */
 
 #define                    MXVREN  0x1        /* MXVR Enable */
-#define                   nMXVREN  0x0       
 #define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
-#define                     nMMSM  0x0       
 #define                    ACTIVE  0x4        /* Active Mode */
-#define                   nACTIVE  0x0       
 #define                    SDELAY  0x8        /* Synchronous Data Delay */
-#define                   nSDELAY  0x0       
 #define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
-#define                  nNCMRXEN  0x0       
 #define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
-#define                  nRWRRXEN  0x0       
 #define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
-#define                    nMTXEN  0x0       
 #define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
-#define                   nMTXONB  0x0       
 #define                   EPARITY  0x100      /* Even Parity Select */
-#define                  nEPARITY  0x0       
 #define                       MSB  0x1e00     /* Master Synchronous Boundary */
 #define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
-#define                   nAPRXEN  0x0       
 #define                    WAKEUP  0x4000     /* Wake-Up */
-#define                   nWAKEUP  0x0       
 #define                     LMECH  0x8000     /* Lock Mechanism Select */
-#define                    nLMECH  0x0       
 
 /* Bit masks for MXVR_STATE_0 */
 
 #define                      NACT  0x1        /* Network Activity */
-#define                     nNACT  0x0       
 #define                    SBLOCK  0x2        /* Super Block Lock */
-#define                   nSBLOCK  0x0       
 #define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
 #define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
 #define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
-#define                    nAPBSY  0x0       
 #define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
-#define                    nAPARB  0x0       
 #define                      APTX  0x400      /* Asynchronous Packet Transmitting */
-#define                     nAPTX  0x0       
 #define                      APRX  0x800      /* Receiving Asynchronous Packet */
-#define                     nAPRX  0x0       
 #define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
-#define                    nCMBSY  0x0       
 #define                     CMARB  0x2000     /* Control Message Arbitrating */
-#define                    nCMARB  0x0       
 #define                      CMTX  0x4000     /* Control Message Transmitting */
-#define                     nCMTX  0x0       
 #define                      CMRX  0x8000     /* Receiving Control Message */
-#define                     nCMRX  0x0       
 #define                    MRXONB  0x10000    /* MRXONB Pin State */
-#define                   nMRXONB  0x0       
 #define                     RGSIP  0x20000    /* Remote Get Source In Progress */
-#define                    nRGSIP  0x0       
 #define                     DALIP  0x40000    /* Resource Deallocate In Progress */
-#define                    nDALIP  0x0       
 #define                      ALIP  0x80000    /* Resource Allocate In Progress */
-#define                     nALIP  0x0       
 #define                     RRDIP  0x100000   /* Remote Read In Progress */
-#define                    nRRDIP  0x0       
 #define                     RWRIP  0x200000   /* Remote Write In Progress */
-#define                    nRWRIP  0x0       
 #define                     FLOCK  0x400000   /* Frame Lock */
-#define                    nFLOCK  0x0       
 #define                     BLOCK  0x800000   /* Block Lock */
-#define                    nBLOCK  0x0       
 #define                       RSB  0xf000000  /* Received Synchronous Boundary */
 #define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
 
@@ -1302,535 +1237,343 @@
 #define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
 #define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
 #define                    APCONT  0x100      /* Asynchronous Packet Continuation */
-#define                   nAPCONT  0x0       
 #define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
 #define                DMAACTIVE0  0x10000    /* DMA0 Active */
-#define               nDMAACTIVE0  0x0       
 #define                DMAACTIVE1  0x20000    /* DMA1 Active */
-#define               nDMAACTIVE1  0x0       
 #define                DMAACTIVE2  0x40000    /* DMA2 Active */
-#define               nDMAACTIVE2  0x0       
 #define                DMAACTIVE3  0x80000    /* DMA3 Active */
-#define               nDMAACTIVE3  0x0       
 #define                DMAACTIVE4  0x100000   /* DMA4 Active */
-#define               nDMAACTIVE4  0x0       
 #define                DMAACTIVE5  0x200000   /* DMA5 Active */
-#define               nDMAACTIVE5  0x0       
 #define                DMAACTIVE6  0x400000   /* DMA6 Active */
-#define               nDMAACTIVE6  0x0       
 #define                DMAACTIVE7  0x800000   /* DMA7 Active */
-#define               nDMAACTIVE7  0x0       
 #define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
-#define                 nDMAPMEN0  0x0       
 #define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
-#define                 nDMAPMEN1  0x0       
 #define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
-#define                 nDMAPMEN2  0x0       
 #define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
-#define                 nDMAPMEN3  0x0       
 #define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
-#define                 nDMAPMEN4  0x0       
 #define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
-#define                 nDMAPMEN5  0x0       
 #define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
-#define                 nDMAPMEN6  0x0       
 #define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
-#define                 nDMAPMEN7  0x0       
 
 /* Bit masks for MXVR_INT_STAT_0 */
 
 #define                      NI2A  0x1        /* Network Inactive to Active */
-#define                     nNI2A  0x0       
 #define                      NA2I  0x2        /* Network Active to Inactive */
-#define                     nNA2I  0x0       
 #define                     SBU2L  0x4        /* Super Block Unlock to Lock */
-#define                    nSBU2L  0x0       
 #define                     SBL2U  0x8        /* Super Block Lock to Unlock */
-#define                    nSBL2U  0x0       
 #define                       PRU  0x10       /* Position Register Updated */
-#define                      nPRU  0x0       
 #define                      MPRU  0x20       /* Maximum Position Register Updated */
-#define                     nMPRU  0x0       
 #define                       DRU  0x40       /* Delay Register Updated */
-#define                      nDRU  0x0       
 #define                      MDRU  0x80       /* Maximum Delay Register Updated */
-#define                     nMDRU  0x0       
 #define                       SBU  0x100      /* Synchronous Boundary Updated */
-#define                      nSBU  0x0       
 #define                       ATU  0x200      /* Allocation Table Updated */
-#define                      nATU  0x0       
 #define                      FCZ0  0x400      /* Frame Counter 0 Zero */
-#define                     nFCZ0  0x0       
 #define                      FCZ1  0x800      /* Frame Counter 1 Zero */
-#define                     nFCZ1  0x0       
 #define                      PERR  0x1000     /* Parity Error */
-#define                     nPERR  0x0       
 #define                      MH2L  0x2000     /* MRXONB High to Low */
-#define                     nMH2L  0x0       
 #define                      ML2H  0x4000     /* MRXONB Low to High */
-#define                     nML2H  0x0       
 #define                       WUP  0x8000     /* Wake-Up Preamble Received */
-#define                      nWUP  0x0       
 #define                      FU2L  0x10000    /* Frame Unlock to Lock */
-#define                     nFU2L  0x0       
 #define                      FL2U  0x20000    /* Frame Lock to Unlock */
-#define                     nFL2U  0x0       
 #define                      BU2L  0x40000    /* Block Unlock to Lock */
-#define                     nBU2L  0x0       
 #define                      BL2U  0x80000    /* Block Lock to Unlock */
-#define                     nBL2U  0x0       
 #define                     OBERR  0x100000   /* DMA Out of Bounds Error */
-#define                    nOBERR  0x0       
 #define                       PFL  0x200000   /* PLL Frequency Locked */
-#define                      nPFL  0x0       
 #define                       SCZ  0x400000   /* System Clock Counter Zero */
-#define                      nSCZ  0x0       
 #define                      FERR  0x800000   /* FIFO Error */
-#define                     nFERR  0x0       
 #define                       CMR  0x1000000  /* Control Message Received */
-#define                      nCMR  0x0       
 #define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
-#define                    nCMROF  0x0       
 #define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
-#define                     nCMTS  0x0       
 #define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
-#define                     nCMTC  0x0       
 #define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
-#define                     nRWRC  0x0       
 #define                       BCZ  0x20000000 /* Block Counter Zero */
-#define                      nBCZ  0x0       
 #define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
-#define                    nBMERR  0x0       
 #define                      DERR  0x80000000 /* DMA Error */
-#define                     nDERR  0x0       
 
 /* Bit masks for MXVR_INT_STAT_1 */
 
 #define                    HDONE0  0x1        /* DMA0 Half Done */
-#define                   nHDONE0  0x0       
 #define                     DONE0  0x2        /* DMA0 Done */
-#define                    nDONE0  0x0       
 #define                       APR  0x4        /* Asynchronous Packet Received */
-#define                      nAPR  0x0       
 #define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
-#define                    nAPROF  0x0       
 #define                    HDONE1  0x10       /* DMA1 Half Done */
-#define                   nHDONE1  0x0       
 #define                     DONE1  0x20       /* DMA1 Done */
-#define                    nDONE1  0x0       
 #define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define                     nAPTS  0x0       
 #define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define                     nAPTC  0x0       
 #define                    HDONE2  0x100      /* DMA2 Half Done */
-#define                   nHDONE2  0x0       
 #define                     DONE2  0x200      /* DMA2 Done */
-#define                    nDONE2  0x0       
 #define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
-#define                    nAPRCE  0x0       
 #define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
-#define                    nAPRPE  0x0       
 #define                    HDONE3  0x1000     /* DMA3 Half Done */
-#define                   nHDONE3  0x0       
 #define                     DONE3  0x2000     /* DMA3 Done */
-#define                    nDONE3  0x0       
 #define                    HDONE4  0x10000    /* DMA4 Half Done */
-#define                   nHDONE4  0x0       
 #define                     DONE4  0x20000    /* DMA4 Done */
-#define                    nDONE4  0x0       
 #define                    HDONE5  0x100000   /* DMA5 Half Done */
-#define                   nHDONE5  0x0       
 #define                     DONE5  0x200000   /* DMA5 Done */
-#define                    nDONE5  0x0       
 #define                    HDONE6  0x1000000  /* DMA6 Half Done */
-#define                   nHDONE6  0x0       
 #define                     DONE6  0x2000000  /* DMA6 Done */
-#define                    nDONE6  0x0       
 #define                    HDONE7  0x10000000 /* DMA7 Half Done */
-#define                   nHDONE7  0x0       
 #define                     DONE7  0x20000000 /* DMA7 Done */
-#define                    nDONE7  0x0       
 
 /* Bit masks for MXVR_INT_EN_0 */
 
 #define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
-#define                   nNI2AEN  0x0       
 #define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
-#define                   nNA2IEN  0x0       
 #define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
-#define                  nSBU2LEN  0x0       
 #define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
-#define                  nSBL2UEN  0x0       
 #define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
-#define                    nPRUEN  0x0       
 #define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
-#define                   nMPRUEN  0x0       
 #define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
-#define                    nDRUEN  0x0       
 #define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
-#define                   nMDRUEN  0x0       
 #define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
-#define                    nSBUEN  0x0       
 #define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
-#define                    nATUEN  0x0       
 #define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
-#define                   nFCZ0EN  0x0       
 #define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
-#define                   nFCZ1EN  0x0       
 #define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
-#define                   nPERREN  0x0       
 #define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
-#define                   nMH2LEN  0x0       
 #define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
-#define                   nML2HEN  0x0       
 #define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
-#define                    nWUPEN  0x0       
 #define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
-#define                   nFU2LEN  0x0       
 #define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
-#define                   nFL2UEN  0x0       
 #define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
-#define                   nBU2LEN  0x0       
 #define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
-#define                   nBL2UEN  0x0       
 #define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
-#define                  nOBERREN  0x0       
 #define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
-#define                    nPFLEN  0x0       
 #define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
-#define                    nSCZEN  0x0       
 #define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
-#define                   nFERREN  0x0       
 #define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
-#define                    nCMREN  0x0       
 #define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define                  nCMROFEN  0x0       
 #define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define                   nCMTSEN  0x0       
 #define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                   nCMTCEN  0x0       
 #define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define                   nRWRCEN  0x0       
 #define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
-#define                    nBCZEN  0x0       
 #define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define                  nBMERREN  0x0       
 #define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
-#define                   nDERREN  0x0       
 
 /* Bit masks for MXVR_INT_EN_1 */
 
 #define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
-#define                 nHDONEEN0  0x0       
 #define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
-#define                  nDONEEN0  0x0       
 #define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
-#define                    nAPREN  0x0       
 #define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define                  nAPROFEN  0x0       
 #define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
-#define                 nHDONEEN1  0x0       
 #define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
-#define                  nDONEEN1  0x0       
 #define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define                   nAPTSEN  0x0       
 #define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                   nAPTCEN  0x0       
 #define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
-#define                 nHDONEEN2  0x0       
 #define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
-#define                  nDONEEN2  0x0       
 #define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define                  nAPRCEEN  0x0       
 #define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define                  nAPRPEEN  0x0       
 #define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
-#define                 nHDONEEN3  0x0       
 #define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
-#define                  nDONEEN3  0x0       
 #define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
-#define                 nHDONEEN4  0x0       
 #define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
-#define                  nDONEEN4  0x0       
 #define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
-#define                 nHDONEEN5  0x0       
 #define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
-#define                  nDONEEN5  0x0       
 #define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
-#define                 nHDONEEN6  0x0       
 #define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
-#define                  nDONEEN6  0x0       
 #define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define                 nHDONEEN7  0x0       
 #define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
-#define                  nDONEEN7  0x0       
 
 /* Bit masks for MXVR_POSITION */
 
 #define                  POSITION  0x3f       /* Node Position */
 #define                    PVALID  0x8000     /* Node Position Valid */
-#define                   nPVALID  0x0       
 
 /* Bit masks for MXVR_MAX_POSITION */
 
 #define                 MPOSITION  0x3f       /* Maximum Node Position */
 #define                   MPVALID  0x8000     /* Maximum Node Position Valid */
-#define                  nMPVALID  0x0       
 
 /* Bit masks for MXVR_DELAY */
 
 #define                     DELAY  0x3f       /* Node Frame Delay */
 #define                    DVALID  0x8000     /* Node Frame Delay Valid */
-#define                   nDVALID  0x0       
 
 /* Bit masks for MXVR_MAX_DELAY */
 
 #define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
 #define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
-#define                  nMDVALID  0x0       
 
 /* Bit masks for MXVR_LADDR */
 
 #define                     LADDR  0xffff     /* Logical Address */
 #define                    LVALID  0x80000000 /* Logical Address Valid */
-#define                   nLVALID  0x0       
 
 /* Bit masks for MXVR_GADDR */
 
 #define                    GADDRL  0xff       /* Group Address Lower Byte */
 #define                    GVALID  0x8000     /* Group Address Valid */
-#define                   nGVALID  0x0       
 
 /* Bit masks for MXVR_AADDR */
 
 #define                     AADDR  0xffff     /* Alternate Address */
 #define                    AVALID  0x80000000 /* Alternate Address Valid */
-#define                   nAVALID  0x0       
 
 /* Bit masks for MXVR_ALLOC_0 */
 
 #define                       CL0  0x7f       /* Channel 0 Connection Label */
 #define                      CIU0  0x80       /* Channel 0 In Use */
-#define                     nCIU0  0x0       
 #define                       CL1  0x7f00     /* Channel 0 Connection Label */
 #define                      CIU1  0x8000     /* Channel 0 In Use */
-#define                     nCIU1  0x0       
 #define                       CL2  0x7f0000   /* Channel 0 Connection Label */
 #define                      CIU2  0x800000   /* Channel 0 In Use */
-#define                     nCIU2  0x0       
 #define                       CL3  0x7f000000 /* Channel 0 Connection Label */
 #define                      CIU3  0x80000000 /* Channel 0 In Use */
-#define                     nCIU3  0x0       
 
 /* Bit masks for MXVR_ALLOC_1 */
 
 #define                       CL4  0x7f       /* Channel 4 Connection Label */
 #define                      CIU4  0x80       /* Channel 4 In Use */
-#define                     nCIU4  0x0       
 #define                       CL5  0x7f00     /* Channel 5 Connection Label */
 #define                      CIU5  0x8000     /* Channel 5 In Use */
-#define                     nCIU5  0x0       
 #define                       CL6  0x7f0000   /* Channel 6 Connection Label */
 #define                      CIU6  0x800000   /* Channel 6 In Use */
-#define                     nCIU6  0x0       
 #define                       CL7  0x7f000000 /* Channel 7 Connection Label */
 #define                      CIU7  0x80000000 /* Channel 7 In Use */
-#define                     nCIU7  0x0       
 
 /* Bit masks for MXVR_ALLOC_2 */
 
 #define                       CL8  0x7f       /* Channel 8 Connection Label */
 #define                      CIU8  0x80       /* Channel 8 In Use */
-#define                     nCIU8  0x0       
 #define                       CL9  0x7f00     /* Channel 9 Connection Label */
 #define                      CIU9  0x8000     /* Channel 9 In Use */
-#define                     nCIU9  0x0       
 #define                      CL10  0x7f0000   /* Channel 10 Connection Label */
 #define                     CIU10  0x800000   /* Channel 10 In Use */
-#define                    nCIU10  0x0       
 #define                      CL11  0x7f000000 /* Channel 11 Connection Label */
 #define                     CIU11  0x80000000 /* Channel 11 In Use */
-#define                    nCIU11  0x0       
 
 /* Bit masks for MXVR_ALLOC_3 */
 
 #define                      CL12  0x7f       /* Channel 12 Connection Label */
 #define                     CIU12  0x80       /* Channel 12 In Use */
-#define                    nCIU12  0x0       
 #define                      CL13  0x7f00     /* Channel 13 Connection Label */
 #define                     CIU13  0x8000     /* Channel 13 In Use */
-#define                    nCIU13  0x0       
 #define                      CL14  0x7f0000   /* Channel 14 Connection Label */
 #define                     CIU14  0x800000   /* Channel 14 In Use */
-#define                    nCIU14  0x0       
 #define                      CL15  0x7f000000 /* Channel 15 Connection Label */
 #define                     CIU15  0x80000000 /* Channel 15 In Use */
-#define                    nCIU15  0x0       
 
 /* Bit masks for MXVR_ALLOC_4 */
 
 #define                      CL16  0x7f       /* Channel 16 Connection Label */
 #define                     CIU16  0x80       /* Channel 16 In Use */
-#define                    nCIU16  0x0       
 #define                      CL17  0x7f00     /* Channel 17 Connection Label */
 #define                     CIU17  0x8000     /* Channel 17 In Use */
-#define                    nCIU17  0x0       
 #define                      CL18  0x7f0000   /* Channel 18 Connection Label */
 #define                     CIU18  0x800000   /* Channel 18 In Use */
-#define                    nCIU18  0x0       
 #define                      CL19  0x7f000000 /* Channel 19 Connection Label */
 #define                     CIU19  0x80000000 /* Channel 19 In Use */
-#define                    nCIU19  0x0       
 
 /* Bit masks for MXVR_ALLOC_5 */
 
 #define                      CL20  0x7f       /* Channel 20 Connection Label */
 #define                     CIU20  0x80       /* Channel 20 In Use */
-#define                    nCIU20  0x0       
 #define                      CL21  0x7f00     /* Channel 21 Connection Label */
 #define                     CIU21  0x8000     /* Channel 21 In Use */
-#define                    nCIU21  0x0       
 #define                      CL22  0x7f0000   /* Channel 22 Connection Label */
 #define                     CIU22  0x800000   /* Channel 22 In Use */
-#define                    nCIU22  0x0       
 #define                      CL23  0x7f000000 /* Channel 23 Connection Label */
 #define                     CIU23  0x80000000 /* Channel 23 In Use */
-#define                    nCIU23  0x0       
 
 /* Bit masks for MXVR_ALLOC_6 */
 
 #define                      CL24  0x7f       /* Channel 24 Connection Label */
 #define                     CIU24  0x80       /* Channel 24 In Use */
-#define                    nCIU24  0x0       
 #define                      CL25  0x7f00     /* Channel 25 Connection Label */
 #define                     CIU25  0x8000     /* Channel 25 In Use */
-#define                    nCIU25  0x0       
 #define                      CL26  0x7f0000   /* Channel 26 Connection Label */
 #define                     CIU26  0x800000   /* Channel 26 In Use */
-#define                    nCIU26  0x0       
 #define                      CL27  0x7f000000 /* Channel 27 Connection Label */
 #define                     CIU27  0x80000000 /* Channel 27 In Use */
-#define                    nCIU27  0x0       
 
 /* Bit masks for MXVR_ALLOC_7 */
 
 #define                      CL28  0x7f       /* Channel 28 Connection Label */
 #define                     CIU28  0x80       /* Channel 28 In Use */
-#define                    nCIU28  0x0       
 #define                      CL29  0x7f00     /* Channel 29 Connection Label */
 #define                     CIU29  0x8000     /* Channel 29 In Use */
-#define                    nCIU29  0x0       
 #define                      CL30  0x7f0000   /* Channel 30 Connection Label */
 #define                     CIU30  0x800000   /* Channel 30 In Use */
-#define                    nCIU30  0x0       
 #define                      CL31  0x7f000000 /* Channel 31 Connection Label */
 #define                     CIU31  0x80000000 /* Channel 31 In Use */
-#define                    nCIU31  0x0       
 
 /* Bit masks for MXVR_ALLOC_8 */
 
 #define                      CL32  0x7f       /* Channel 32 Connection Label */
 #define                     CIU32  0x80       /* Channel 32 In Use */
-#define                    nCIU32  0x0       
 #define                      CL33  0x7f00     /* Channel 33 Connection Label */
 #define                     CIU33  0x8000     /* Channel 33 In Use */
-#define                    nCIU33  0x0       
 #define                      CL34  0x7f0000   /* Channel 34 Connection Label */
 #define                     CIU34  0x800000   /* Channel 34 In Use */
-#define                    nCIU34  0x0       
 #define                      CL35  0x7f000000 /* Channel 35 Connection Label */
 #define                     CIU35  0x80000000 /* Channel 35 In Use */
-#define                    nCIU35  0x0       
 
 /* Bit masks for MXVR_ALLOC_9 */
 
 #define                      CL36  0x7f       /* Channel 36 Connection Label */
 #define                     CIU36  0x80       /* Channel 36 In Use */
-#define                    nCIU36  0x0       
 #define                      CL37  0x7f00     /* Channel 37 Connection Label */
 #define                     CIU37  0x8000     /* Channel 37 In Use */
-#define                    nCIU37  0x0       
 #define                      CL38  0x7f0000   /* Channel 38 Connection Label */
 #define                     CIU38  0x800000   /* Channel 38 In Use */
-#define                    nCIU38  0x0       
 #define                      CL39  0x7f000000 /* Channel 39 Connection Label */
 #define                     CIU39  0x80000000 /* Channel 39 In Use */
-#define                    nCIU39  0x0       
 
 /* Bit masks for MXVR_ALLOC_10 */
 
 #define                      CL40  0x7f       /* Channel 40 Connection Label */
 #define                     CIU40  0x80       /* Channel 40 In Use */
-#define                    nCIU40  0x0       
 #define                      CL41  0x7f00     /* Channel 41 Connection Label */
 #define                     CIU41  0x8000     /* Channel 41 In Use */
-#define                    nCIU41  0x0       
 #define                      CL42  0x7f0000   /* Channel 42 Connection Label */
 #define                     CIU42  0x800000   /* Channel 42 In Use */
-#define                    nCIU42  0x0       
 #define                      CL43  0x7f000000 /* Channel 43 Connection Label */
 #define                     CIU43  0x80000000 /* Channel 43 In Use */
-#define                    nCIU43  0x0       
 
 /* Bit masks for MXVR_ALLOC_11 */
 
 #define                      CL44  0x7f       /* Channel 44 Connection Label */
 #define                     CIU44  0x80       /* Channel 44 In Use */
-#define                    nCIU44  0x0       
 #define                      CL45  0x7f00     /* Channel 45 Connection Label */
 #define                     CIU45  0x8000     /* Channel 45 In Use */
-#define                    nCIU45  0x0       
 #define                      CL46  0x7f0000   /* Channel 46 Connection Label */
 #define                     CIU46  0x800000   /* Channel 46 In Use */
-#define                    nCIU46  0x0       
 #define                      CL47  0x7f000000 /* Channel 47 Connection Label */
 #define                     CIU47  0x80000000 /* Channel 47 In Use */
-#define                    nCIU47  0x0       
 
 /* Bit masks for MXVR_ALLOC_12 */
 
 #define                      CL48  0x7f       /* Channel 48 Connection Label */
 #define                     CIU48  0x80       /* Channel 48 In Use */
-#define                    nCIU48  0x0       
 #define                      CL49  0x7f00     /* Channel 49 Connection Label */
 #define                     CIU49  0x8000     /* Channel 49 In Use */
-#define                    nCIU49  0x0       
 #define                      CL50  0x7f0000   /* Channel 50 Connection Label */
 #define                     CIU50  0x800000   /* Channel 50 In Use */
-#define                    nCIU50  0x0       
 #define                      CL51  0x7f000000 /* Channel 51 Connection Label */
 #define                     CIU51  0x80000000 /* Channel 51 In Use */
-#define                    nCIU51  0x0       
 
 /* Bit masks for MXVR_ALLOC_13 */
 
 #define                      CL52  0x7f       /* Channel 52 Connection Label */
 #define                     CIU52  0x80       /* Channel 52 In Use */
-#define                    nCIU52  0x0       
 #define                      CL53  0x7f00     /* Channel 53 Connection Label */
 #define                     CIU53  0x8000     /* Channel 53 In Use */
-#define                    nCIU53  0x0       
 #define                      CL54  0x7f0000   /* Channel 54 Connection Label */
 #define                     CIU54  0x800000   /* Channel 54 In Use */
-#define                    nCIU54  0x0       
 #define                      CL55  0x7f000000 /* Channel 55 Connection Label */
 #define                     CIU55  0x80000000 /* Channel 55 In Use */
-#define                    nCIU55  0x0       
 
 /* Bit masks for MXVR_ALLOC_14 */
 
 #define                      CL56  0x7f       /* Channel 56 Connection Label */
 #define                     CIU56  0x80       /* Channel 56 In Use */
-#define                    nCIU56  0x0       
 #define                      CL57  0x7f00     /* Channel 57 Connection Label */
 #define                     CIU57  0x8000     /* Channel 57 In Use */
-#define                    nCIU57  0x0       
 #define                      CL58  0x7f0000   /* Channel 58 Connection Label */
 #define                     CIU58  0x800000   /* Channel 58 In Use */
-#define                    nCIU58  0x0       
 #define                      CL59  0x7f000000 /* Channel 59 Connection Label */
 #define                     CIU59  0x80000000 /* Channel 59 In Use */
-#define                    nCIU59  0x0       
 
 /* MXVR_SYNC_LCHAN_0 Masks */
 
@@ -1926,19 +1669,13 @@
 /* Bit masks for MXVR_DMAx_CONFIG */
 
 #define                    MDMAEN  0x1        /* DMA Channel Enable */
-#define                   nMDMAEN  0x0       
 #define                        DD  0x2        /* DMA Channel Direction */
-#define                       nDD  0x0       
 #define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
-#define                nBY4SWAPEN  0x0       
 #define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
 #define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
-#define                nBITSWAPEN  0x0       
 #define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
-#define                nBY2SWAPEN  0x0       
 #define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
 #define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
-#define                  nFIXEDPM  0x0       
 #define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
 #define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
 #define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
@@ -1946,94 +1683,71 @@
 /* Bit masks for MXVR_AP_CTL */
 
 #define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
-#define                  nSTARTAP  0x0       
 #define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
-#define                 nCANCELAP  0x0       
 #define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
-#define                  nRESETAP  0x0       
 #define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
-#define                   nAPRBE0  0x0       
 #define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
-#define                   nAPRBE1  0x0       
 
 /* Bit masks for MXVR_APRB_START_ADDR */
 
-#define      MXVR_APRB_START_ADDR  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
+#define      MXVR_APRB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
 
 /* Bit masks for MXVR_APRB_CURR_ADDR */
 
-#define       MXVR_APRB_CURR_ADDR  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
+#define       MXVR_APRB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
 
 /* Bit masks for MXVR_APTB_START_ADDR */
 
-#define       MXVR_APTB_START_ADDR  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
+#define       MXVR_APTB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
 
 /* Bit masks for MXVR_APTB_CURR_ADDR */
 
-#define        MXVR_APTB_CURR_ADDR  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
+#define        MXVR_APTB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
 
 /* Bit masks for MXVR_CM_CTL */
 
 #define                   STARTCM  0x1        /* Start Control Message Transmission */
-#define                  nSTARTCM  0x0       
 #define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
-#define                 nCANCELCM  0x0       
 #define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
-#define                   nCMRBE0  0x0       
 #define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
-#define                   nCMRBE1  0x0       
 #define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
-#define                   nCMRBE2  0x0       
 #define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
-#define                   nCMRBE3  0x0       
 #define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
-#define                   nCMRBE4  0x0       
 #define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
-#define                   nCMRBE5  0x0       
 #define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
-#define                   nCMRBE6  0x0       
 #define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
-#define                   nCMRBE7  0x0       
 #define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
-#define                   nCMRBE8  0x0       
 #define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
-#define                   nCMRBE9  0x0       
 #define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
-#define                  nCMRBE10  0x0       
 #define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
-#define                  nCMRBE11  0x0       
 #define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define                  nCMRBE12  0x0       
 #define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define                  nCMRBE13  0x0       
 #define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define                  nCMRBE14  0x0       
 #define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
-#define                  nCMRBE15  0x0       
 
 /* Bit masks for MXVR_CMRB_START_ADDR */
 
-#define      MXVR_CMRB_START_ADDR  0x1fffffe  /* Control Message Receive Buffer Start Address */
+#define      MXVR_CMRB_START_ADDR_MASK  0x1fffffe  /* Control Message Receive Buffer Start Address */
 
 /* Bit masks for MXVR_CMRB_CURR_ADDR */
 
-#define       MXVR_CMRB_CURR_ADDR  0xffffffff /* Control Message Receive Buffer Current Address */
+#define       MXVR_CMRB_CURR_ADDR_MASK  0xffffffff /* Control Message Receive Buffer Current Address */
 
 /* Bit masks for MXVR_CMTB_START_ADDR */
 
-#define      MXVR_CMTB_START_ADDR  0x1fffffe  /* Control Message Transmit Buffer Start Address */
+#define      MXVR_CMTB_START_ADDR_MASK  0x1fffffe  /* Control Message Transmit Buffer Start Address */
 
 /* Bit masks for MXVR_CMTB_CURR_ADDR */
 
-#define       MXVR_CMTB_CURR_ADDR  0xffffffff /* Control Message Transmit Buffer Current Address */
+#define       MXVR_CMTB_CURR_ADDR_MASK  0xffffffff /* Control Message Transmit Buffer Current Address */
 
 /* Bit masks for MXVR_RRDB_START_ADDR */
 
-#define      MXVR_RRDB_START_ADDR  0x1fffffe  /* Remote Read Buffer Start Address */
+#define      MXVR_RRDB_START_ADDR_MASK  0x1fffffe  /* Remote Read Buffer Start Address */
 
 /* Bit masks for MXVR_RRDB_CURR_ADDR */
 
-#define       MXVR_RRDB_CURR_ADDR  0xffffffff /* Remote Read Buffer Current Address */
+#define       MXVR_RRDB_CURR_ADDR_MASK  0xffffffff /* Remote Read Buffer Current Address */
 
 /* Bit masks for MXVR_PAT_DATAx */
 
@@ -2045,136 +1759,72 @@
 /* Bit masks for MXVR_PAT_EN_0 */
 
 #define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define             nMATCH_EN_0_0  0x0       
 #define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define             nMATCH_EN_0_1  0x0       
 #define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define             nMATCH_EN_0_2  0x0       
 #define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define             nMATCH_EN_0_3  0x0       
 #define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define             nMATCH_EN_0_4  0x0       
 #define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define             nMATCH_EN_0_5  0x0       
 #define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define             nMATCH_EN_0_6  0x0       
 #define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define             nMATCH_EN_0_7  0x0       
 #define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define             nMATCH_EN_1_0  0x0       
 #define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define             nMATCH_EN_1_1  0x0       
 #define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define             nMATCH_EN_1_2  0x0       
 #define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define             nMATCH_EN_1_3  0x0       
 #define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define             nMATCH_EN_1_4  0x0       
 #define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define             nMATCH_EN_1_5  0x0       
 #define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define             nMATCH_EN_1_6  0x0       
 #define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define             nMATCH_EN_1_7  0x0       
 #define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define             nMATCH_EN_2_0  0x0       
 #define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define             nMATCH_EN_2_1  0x0       
 #define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define             nMATCH_EN_2_2  0x0       
 #define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define             nMATCH_EN_2_3  0x0       
 #define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define             nMATCH_EN_2_4  0x0       
 #define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define             nMATCH_EN_2_5  0x0       
 #define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define             nMATCH_EN_2_6  0x0       
 #define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define             nMATCH_EN_2_7  0x0       
 #define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define             nMATCH_EN_3_0  0x0       
 #define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define             nMATCH_EN_3_1  0x0       
 #define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define             nMATCH_EN_3_2  0x0       
 #define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define             nMATCH_EN_3_3  0x0       
 #define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define             nMATCH_EN_3_4  0x0       
 #define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define             nMATCH_EN_3_5  0x0       
 #define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define             nMATCH_EN_3_6  0x0       
 #define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define             nMATCH_EN_3_7  0x0       
 
 /* Bit masks for MXVR_PAT_EN_1 */
 
 #define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define             nMATCH_EN_0_0  0x0       
 #define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define             nMATCH_EN_0_1  0x0       
 #define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define             nMATCH_EN_0_2  0x0       
 #define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define             nMATCH_EN_0_3  0x0       
 #define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define             nMATCH_EN_0_4  0x0       
 #define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define             nMATCH_EN_0_5  0x0       
 #define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define             nMATCH_EN_0_6  0x0       
 #define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define             nMATCH_EN_0_7  0x0       
 #define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define             nMATCH_EN_1_0  0x0       
 #define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define             nMATCH_EN_1_1  0x0       
 #define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define             nMATCH_EN_1_2  0x0       
 #define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define             nMATCH_EN_1_3  0x0       
 #define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define             nMATCH_EN_1_4  0x0       
 #define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define             nMATCH_EN_1_5  0x0       
 #define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define             nMATCH_EN_1_6  0x0       
 #define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define             nMATCH_EN_1_7  0x0       
 #define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define             nMATCH_EN_2_0  0x0       
 #define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define             nMATCH_EN_2_1  0x0       
 #define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define             nMATCH_EN_2_2  0x0       
 #define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define             nMATCH_EN_2_3  0x0       
 #define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define             nMATCH_EN_2_4  0x0       
 #define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define             nMATCH_EN_2_5  0x0       
 #define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define             nMATCH_EN_2_6  0x0       
 #define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define             nMATCH_EN_2_7  0x0       
 #define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define             nMATCH_EN_3_0  0x0       
 #define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define             nMATCH_EN_3_1  0x0       
 #define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define             nMATCH_EN_3_2  0x0       
 #define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define             nMATCH_EN_3_3  0x0       
 #define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define             nMATCH_EN_3_4  0x0       
 #define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define             nMATCH_EN_3_5  0x0       
 #define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define             nMATCH_EN_3_6  0x0       
 #define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define             nMATCH_EN_3_7  0x0       
 
 /* Bit masks for MXVR_FRAME_CNT_0 */
 
@@ -2188,226 +1838,166 @@
 
 #define                    TX_CH0  0x3f       /* Transmit Channel 0 */
 #define                  MUTE_CH0  0x80       /* Mute Channel 0 */
-#define                 nMUTE_CH0  0x0       
 #define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
 #define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
-#define                 nMUTE_CH1  0x0       
 #define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
 #define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
-#define                 nMUTE_CH2  0x0       
 #define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
 #define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
-#define                 nMUTE_CH3  0x0       
 
 /* Bit masks for MXVR_ROUTING_1 */
 
 #define                    TX_CH4  0x3f       /* Transmit Channel 4 */
 #define                  MUTE_CH4  0x80       /* Mute Channel 4 */
-#define                 nMUTE_CH4  0x0       
 #define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
 #define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
-#define                 nMUTE_CH5  0x0       
 #define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
 #define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
-#define                 nMUTE_CH6  0x0       
 #define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
 #define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
-#define                 nMUTE_CH7  0x0       
 
 /* Bit masks for MXVR_ROUTING_2 */
 
 #define                    TX_CH8  0x3f       /* Transmit Channel 8 */
 #define                  MUTE_CH8  0x80       /* Mute Channel 8 */
-#define                 nMUTE_CH8  0x0       
 #define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
 #define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
-#define                 nMUTE_CH9  0x0       
 #define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
 #define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
-#define                nMUTE_CH10  0x0       
 #define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
 #define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
-#define                nMUTE_CH11  0x0       
 
 /* Bit masks for MXVR_ROUTING_3 */
 
 #define                   TX_CH12  0x3f       /* Transmit Channel 12 */
 #define                 MUTE_CH12  0x80       /* Mute Channel 12 */
-#define                nMUTE_CH12  0x0       
 #define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
 #define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
-#define                nMUTE_CH13  0x0       
 #define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
 #define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
-#define                nMUTE_CH14  0x0       
 #define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
 #define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
-#define                nMUTE_CH15  0x0       
 
 /* Bit masks for MXVR_ROUTING_4 */
 
 #define                   TX_CH16  0x3f       /* Transmit Channel 16 */
 #define                 MUTE_CH16  0x80       /* Mute Channel 16 */
-#define                nMUTE_CH16  0x0       
 #define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
 #define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
-#define                nMUTE_CH17  0x0       
 #define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
 #define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
-#define                nMUTE_CH18  0x0       
 #define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
 #define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
-#define                nMUTE_CH19  0x0       
 
 /* Bit masks for MXVR_ROUTING_5 */
 
 #define                   TX_CH20  0x3f       /* Transmit Channel 20 */
 #define                 MUTE_CH20  0x80       /* Mute Channel 20 */
-#define                nMUTE_CH20  0x0       
 #define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
 #define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
-#define                nMUTE_CH21  0x0       
 #define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
 #define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
-#define                nMUTE_CH22  0x0       
 #define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
 #define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
-#define                nMUTE_CH23  0x0       
 
 /* Bit masks for MXVR_ROUTING_6 */
 
 #define                   TX_CH24  0x3f       /* Transmit Channel 24 */
 #define                 MUTE_CH24  0x80       /* Mute Channel 24 */
-#define                nMUTE_CH24  0x0       
 #define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
 #define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
-#define                nMUTE_CH25  0x0       
 #define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
 #define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
-#define                nMUTE_CH26  0x0       
 #define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
 #define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
-#define                nMUTE_CH27  0x0       
 
 /* Bit masks for MXVR_ROUTING_7 */
 
 #define                   TX_CH28  0x3f       /* Transmit Channel 28 */
 #define                 MUTE_CH28  0x80       /* Mute Channel 28 */
-#define                nMUTE_CH28  0x0       
 #define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
 #define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
-#define                nMUTE_CH29  0x0       
 #define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
 #define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
-#define                nMUTE_CH30  0x0       
 #define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
 #define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
-#define                nMUTE_CH31  0x0       
 
 /* Bit masks for MXVR_ROUTING_8 */
 
 #define                   TX_CH32  0x3f       /* Transmit Channel 32 */
 #define                 MUTE_CH32  0x80       /* Mute Channel 32 */
-#define                nMUTE_CH32  0x0       
 #define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
 #define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
-#define                nMUTE_CH33  0x0       
 #define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
 #define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
-#define                nMUTE_CH34  0x0       
 #define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
 #define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
-#define                nMUTE_CH35  0x0       
 
 /* Bit masks for MXVR_ROUTING_9 */
 
 #define                   TX_CH36  0x3f       /* Transmit Channel 36 */
 #define                 MUTE_CH36  0x80       /* Mute Channel 36 */
-#define                nMUTE_CH36  0x0       
 #define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
 #define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
-#define                nMUTE_CH37  0x0       
 #define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
 #define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
-#define                nMUTE_CH38  0x0       
 #define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
 #define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
-#define                nMUTE_CH39  0x0       
 
 /* Bit masks for MXVR_ROUTING_10 */
 
 #define                   TX_CH40  0x3f       /* Transmit Channel 40 */
 #define                 MUTE_CH40  0x80       /* Mute Channel 40 */
-#define                nMUTE_CH40  0x0       
 #define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
 #define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
-#define                nMUTE_CH41  0x0       
 #define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
 #define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
-#define                nMUTE_CH42  0x0       
 #define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
 #define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
-#define                nMUTE_CH43  0x0       
 
 /* Bit masks for MXVR_ROUTING_11 */
 
 #define                   TX_CH44  0x3f       /* Transmit Channel 44 */
 #define                 MUTE_CH44  0x80       /* Mute Channel 44 */
-#define                nMUTE_CH44  0x0       
 #define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
 #define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
-#define                nMUTE_CH45  0x0       
 #define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
 #define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
-#define                nMUTE_CH46  0x0       
 #define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
 #define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
-#define                nMUTE_CH47  0x0       
 
 /* Bit masks for MXVR_ROUTING_12 */
 
 #define                   TX_CH48  0x3f       /* Transmit Channel 48 */
 #define                 MUTE_CH48  0x80       /* Mute Channel 48 */
-#define                nMUTE_CH48  0x0       
 #define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
 #define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
-#define                nMUTE_CH49  0x0       
 #define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
 #define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
-#define                nMUTE_CH50  0x0       
 #define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
 #define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
-#define                nMUTE_CH51  0x0       
 
 /* Bit masks for MXVR_ROUTING_13 */
 
 #define                   TX_CH52  0x3f       /* Transmit Channel 52 */
 #define                 MUTE_CH52  0x80       /* Mute Channel 52 */
-#define                nMUTE_CH52  0x0       
 #define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
 #define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
-#define                nMUTE_CH53  0x0       
 #define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
 #define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
-#define                nMUTE_CH54  0x0       
 #define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
 #define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
-#define                nMUTE_CH55  0x0       
 
 /* Bit masks for MXVR_ROUTING_14 */
 
 #define                   TX_CH56  0x3f       /* Transmit Channel 56 */
 #define                 MUTE_CH56  0x80       /* Mute Channel 56 */
-#define                nMUTE_CH56  0x0       
 #define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
 #define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
-#define                nMUTE_CH57  0x0       
 #define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
 #define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
-#define                nMUTE_CH58  0x0       
 #define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
 #define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
-#define                nMUTE_CH59  0x0       
 
 /* Bit masks for MXVR_BLOCK_CNT */
 
@@ -2416,53 +2006,37 @@
 /* Bit masks for MXVR_CLK_CTL */
 
 #define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
-#define                 nMXTALCEN  0x0       
 #define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
-#define                 nMXTALFEN  0x0       
 #define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
 #define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
-#define                 nCLKX3SEL  0x0       
 #define                   MMCLKEN  0x100      /* Master Clock Enable */
-#define                  nMMCLKEN  0x0       
 #define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
 #define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
 #define                   MBCLKEN  0x10000    /* Bit Clock Enable */
-#define                  nMBCLKEN  0x0       
 #define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
 #define                     INVRX  0x800000   /* Invert Receive Data */
-#define                    nINVRX  0x0       
 #define                     MFSEN  0x1000000  /* Frame Sync Enable */
-#define                    nMFSEN  0x0       
 #define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
 #define                    MFSSEL  0x60000000 /* Frame Sync Select */
 #define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
-#define                  nMFSSYNC  0x0       
 
 /* Bit masks for MXVR_CDRPLL_CTL */
 
 #define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
-#define                  nCDRSMEN  0x0       
 #define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
-#define                  nCDRRSTB  0x0       
 #define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
-#define                  nCDRSVCO  0x0       
 #define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
-#define                  nCDRMODE  0x0       
 #define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
 #define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
 #define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
 #define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
-#define                 nCDRSHPEN  0x0       
 #define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
 
 /* Bit masks for MXVR_FMPLL_CTL */
 
 #define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
-#define                   nFMSMEN  0x0       
 #define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
-#define                   nFMRSTB  0x0       
 #define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
-#define                   nFMSVCO  0x0       
 #define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
 #define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
 #define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
@@ -2470,15 +2044,10 @@
 /* Bit masks for MXVR_PIN_CTL */
 
 #define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
-#define                 nMTXONBOD  0x0       
 #define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
-#define                  nMTXONBG  0x0       
 #define                     MFSOE  0x10       /* MFS Output Enable */
-#define                    nMFSOE  0x0       
 #define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
-#define                 nMFSGPSEL  0x0       
 #define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
-#define                 nMFSGPDAT  0x0       
 
 /* Bit masks for MXVR_SCLK_CNT */
 
@@ -2487,7 +2056,6 @@
 /* Bit masks for KPAD_CTL */
 
 #define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0       
 #define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
 #define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
 #define                KPAD_COLEN  0xe000     /* Column Enable Width */
@@ -2509,29 +2077,21 @@
 /* Bit masks for KPAD_STAT */
 
 #define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0       
 #define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
 #define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0       
 
 /* Bit masks for KPAD_SOFTEVAL */
 
 #define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0       
 
 /* Bit masks for SDH_COMMAND */
 
 #define                   CMD_IDX  0x3f       /* Command Index */
 #define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0       
 #define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0       
 #define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0       
 #define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0       
 #define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0       
 
 /* Bit masks for SDH_PWR_CTL */
 
@@ -2540,21 +2100,15 @@
 #define                       TBD  0x3c       /* TBD */
 #endif
 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0       
 #define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0       
 
 /* Bit masks for SDH_CLK_CTL */
 
 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0       
 #define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0       
 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0       
 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0       
 
 /* Bit masks for SDH_RESP_CMD */
 
@@ -2563,133 +2117,74 @@
 /* Bit masks for SDH_DATA_CTL */
 
 #define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0       
 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0       
 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0       
 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0       
 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 
 /* Bit masks for SDH_STATUS */
 
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0       
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0       
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0       
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0       
+#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
+#define               DAT_TIME_OUT  0x8        /* Data Time Out */
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0       
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0       
 #define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0       
 #define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0       
 #define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0       
 #define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0       
 #define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0       
 #define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0       
 #define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0       
 #define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0       
 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0       
 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0       
 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0       
 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0       
 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0       
 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0       
 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0       
 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0       
 
 /* Bit masks for SDH_STATUS_CLR */
 
 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0       
 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0       
 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0       
 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0       
 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0       
 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0       
 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0       
 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0       
 #define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0       
 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0       
 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0       
 
 /* Bit masks for SDH_MASK0 */
 
 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0       
 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0       
 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0       
 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0       
 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0       
 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0       
 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0       
 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0       
 #define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0       
 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0       
 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0       
 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0       
 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0       
 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0       
 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0       
 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0       
 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0       
 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0       
 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0       
 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0       
 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0       
 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0       
 
 /* Bit masks for SDH_FIFO_CNT */
 
@@ -2698,73 +2193,47 @@
 /* Bit masks for SDH_E_STATUS */
 
 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0       
 #define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0       
 
 /* Bit masks for SDH_E_MASK */
 
 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0       
 #define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0       
 
 /* Bit masks for SDH_CFG */
 
 #define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0       
 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0       
 #define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0       
 #define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0       
 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0       
 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0       
 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0       
 
 /* Bit masks for SDH_RD_WAIT_EN */
 
 #define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0       
 
 /* Bit masks for ATAPI_CONTROL */
 
 #define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0       
 #define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0       
 #define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0       
 #define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0       
 #define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0       
 #define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0       
 #define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0       
 #define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0       
 #define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0       
 #define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0       
 #define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0       
 #define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
 
 /* Bit masks for ATAPI_STATUS */
 
 #define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0       
 #define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0       
 #define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0       
 #define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
 
 /* Bit masks for ATAPI_DEV_ADDR */
@@ -2774,66 +2243,39 @@
 /* Bit masks for ATAPI_INT_MASK */
 
 #define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0       
 #define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0       
 #define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0       
 #define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0       
 #define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0       
 #define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0       
 #define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0       
 #define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0       
 #define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0       
 
 /* Bit masks for ATAPI_INT_STATUS */
 
 #define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0       
 #define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0       
 #define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0       
 #define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0       
 #define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0       
 #define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0       
 #define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0       
 #define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0       
 #define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0       
 
 /* Bit masks for ATAPI_LINE_STATUS */
 
 #define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0       
 #define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0       
 #define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0       
 #define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0       
 #define                ATAPI_ADDR  0x70       /* ATAPI address line status */
 #define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0       
 #define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0       
 #define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0       
 #define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0       
 #define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0       
 
 /* Bit masks for ATAPI_SM_STATE */
 
@@ -2845,7 +2287,6 @@
 /* Bit masks for ATAPI_TERMINATE */
 
 #define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0       
 
 /* Bit masks for ATAPI_REG_TIM_0 */
 
@@ -2900,41 +2341,26 @@
 /* Bit masks for TIMER_ENABLE1 */
 
 #define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0       
 #define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0       
 #define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0       
 
 /* Bit masks for TIMER_DISABLE1 */
 
 #define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0       
 #define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0       
 #define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0       
 
 /* Bit masks for TIMER_STATUS1 */
 
 #define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0       
 #define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0       
 #define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0       
 #define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0       
 #define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0       
 #define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0       
 #define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0       
 #define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0       
 #define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0       
 
 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
 
@@ -2945,131 +2371,77 @@
 /* Bit masks for USB_POWER */
 
 #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
 #define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
 #define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
 #define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
 #define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
 #define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
 #define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
 #define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
 
 /* Bit masks for USB_INTRTX */
 
 #define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
 #define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
 #define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
 #define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
 #define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
 #define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
 #define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
 #define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
 
 /* Bit masks for USB_INTRRX */
 
 #define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
 #define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
 #define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
 #define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
 #define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
 #define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
 #define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
 
 /* Bit masks for USB_INTRTXE */
 
 #define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
 #define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
 #define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
 #define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
 #define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
 #define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
 #define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
 #define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
 
 /* Bit masks for USB_INTRRXE */
 
 #define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
 #define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
 #define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
 #define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
 #define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
 #define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
 #define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
 
 /* Bit masks for USB_INTRUSB */
 
 #define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
 #define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
 #define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
 #define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
 #define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
 #define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
 #define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
 #define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
 
 /* Bit masks for USB_INTRUSBE */
 
 #define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
 #define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
 #define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
 #define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
 #define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
 #define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
 #define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
 #define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
 
 /* Bit masks for USB_FRAME */
 
@@ -3082,117 +2454,67 @@
 /* Bit masks for USB_GLOBAL_CTL */
 
 #define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
 #define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
 #define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
 #define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
 #define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
 #define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
 #define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
 #define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
 #define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
 #define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
 #define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
 #define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
 #define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
 #define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
 #define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
 
 /* Bit masks for USB_OTG_DEV_CTL */
 
 #define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
 #define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
 #define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
 #define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
 #define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
 #define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
 #define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
 #define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
 
 /* Bit masks for USB_OTG_VBUS_IRQ */
 
 #define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
 #define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
 #define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
 #define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
 #define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
 #define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
 
 /* Bit masks for USB_OTG_VBUS_MASK */
 
 #define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
 #define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
 #define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
 #define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
 #define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
 #define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
 
 /* Bit masks for USB_CSR0 */
 
 #define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
 #define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
 #define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
 #define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
 #define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
 #define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
 #define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
 #define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
 #define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
 #define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
 #define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
 #define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
 #define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
 #define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
 #define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
 
 /* Bit masks for USB_COUNT0 */
 
@@ -3213,37 +2535,21 @@
 /* Bit masks for USB_TXCSR */
 
 #define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
 #define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
 #define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
 #define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
 #define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
 #define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
 #define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
 #define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
 #define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
 #define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
 #define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
 #define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
 #define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
 #define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
 #define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
 #define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
 
 /* Bit masks for USB_TXCOUNT */
 
@@ -3252,45 +2558,25 @@
 /* Bit masks for USB_RXCSR */
 
 #define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
 #define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
 #define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
 #define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
 #define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
 #define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
 #define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
 #define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
 #define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
 #define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
 #define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
 #define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
 #define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
 #define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
 #define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
 #define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
 #define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
 #define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
 #define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
 #define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
 
 /* Bit masks for USB_RXCOUNT */
 
@@ -3317,35 +2603,22 @@
 /* Bit masks for USB_DMA_INTERRUPT */
 
 #define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
 #define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
 #define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
 #define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
 #define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
 #define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
 #define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
 #define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
 
 /* Bit masks for USB_DMAxCONTROL */
 
 #define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
 #define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
 #define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
 #define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
 #define                     EPNUM  0xf0       /* EP number */
 #define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
 
 /* Bit masks for USB_DMAxADDRHIGH */
 
@@ -3366,26 +2639,16 @@
 /* Bit masks for HMDMAx_CONTROL */
 
 #define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                  nHMDMAEN  0x0       
 #define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                      nREP  0x0       
 #define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                      nUTE  0x0       
 #define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      nOIE  0x0       
 #define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                     nBDIE  0x0       
 #define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                     nMBDI  0x0       
 #define                       DRQ  0x300      /* Handshake MDMA Request Type */
 #define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                      nRBC  0x0       
 #define                        PS  0x2000     /* Pin Status */
-#define                       nPS  0x0       
 #define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       nOI  0x0       
 #define                       BDI  0x8000     /* Block Done Interrupt Generated */
-#define                      nBDI  0x0       
 
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index a1b200fe6a1f..895ddd40a838 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -46,7 +46,7 @@
 
 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
 
-#define                           CHIPID  0xffc00014   
+#define                           CHIPID  0xffc00014
 
 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
 
@@ -1512,231 +1512,144 @@
 /*     and MULTI BIT READ MACROS                              */
 /* ********************************************************** */
 
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
+#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
+
 /* Bit masks for SIC_IAR0 */
 
-#define            IRQ_PLL_WAKEUP  0x1        /* PLL Wakeup */
-#define           nIRQ_PLL_WAKEUP  0x0       
+#define            PLL_WAKEUP  0x1        /* PLL Wakeup */
 
 /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
 
-#define              IRQ_DMA0_ERR  0x2        /* DMA Controller 0 Error */
-#define             nIRQ_DMA0_ERR  0x0       
-#define             IRQ_EPPI0_ERR  0x4        /* EPPI0 Error */
-#define            nIRQ_EPPI0_ERR  0x0       
-#define            IRQ_SPORT0_ERR  0x8        /* SPORT0 Error */
-#define           nIRQ_SPORT0_ERR  0x0       
-#define            IRQ_SPORT1_ERR  0x10       /* SPORT1 Error */
-#define           nIRQ_SPORT1_ERR  0x0       
-#define              IRQ_SPI0_ERR  0x20       /* SPI0 Error */
-#define             nIRQ_SPI0_ERR  0x0       
-#define             IRQ_UART0_ERR  0x40       /* UART0 Error */
-#define            nIRQ_UART0_ERR  0x0       
-#define                   IRQ_RTC  0x80       /* Real-Time Clock */
-#define                  nIRQ_RTC  0x0       
-#define                 IRQ_DMA12  0x100      /* DMA Channel 12 */
-#define                nIRQ_DMA12  0x0       
-#define                  IRQ_DMA0  0x200      /* DMA Channel 0 */
-#define                 nIRQ_DMA0  0x0       
-#define                  IRQ_DMA1  0x400      /* DMA Channel 1 */
-#define                 nIRQ_DMA1  0x0       
-#define                  IRQ_DMA2  0x800      /* DMA Channel 2 */
-#define                 nIRQ_DMA2  0x0       
-#define                  IRQ_DMA3  0x1000     /* DMA Channel 3 */
-#define                 nIRQ_DMA3  0x0       
-#define                  IRQ_DMA4  0x2000     /* DMA Channel 4 */
-#define                 nIRQ_DMA4  0x0       
-#define                  IRQ_DMA6  0x4000     /* DMA Channel 6 */
-#define                 nIRQ_DMA6  0x0       
-#define                  IRQ_DMA7  0x8000     /* DMA Channel 7 */
-#define                 nIRQ_DMA7  0x0       
-#define                 IRQ_PINT0  0x80000    /* Pin Interrupt 0 */
-#define                nIRQ_PINT0  0x0       
-#define                 IRQ_PINT1  0x100000   /* Pin Interrupt 1 */
-#define                nIRQ_PINT1  0x0       
-#define                 IRQ_MDMA0  0x200000   /* Memory DMA Stream 0 */
-#define                nIRQ_MDMA0  0x0       
-#define                 IRQ_MDMA1  0x400000   /* Memory DMA Stream 1 */
-#define                nIRQ_MDMA1  0x0       
-#define                  IRQ_WDOG  0x800000   /* Watchdog Timer */
-#define                 nIRQ_WDOG  0x0       
-#define              IRQ_DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
-#define             nIRQ_DMA1_ERR  0x0       
-#define            IRQ_SPORT2_ERR  0x2000000  /* SPORT2 Error */
-#define           nIRQ_SPORT2_ERR  0x0       
-#define            IRQ_SPORT3_ERR  0x4000000  /* SPORT3 Error */
-#define           nIRQ_SPORT3_ERR  0x0       
-#define               IRQ_MXVR_SD  0x8000000  /* MXVR Synchronous Data */
-#define              nIRQ_MXVR_SD  0x0       
-#define              IRQ_SPI1_ERR  0x10000000 /* SPI1 Error */
-#define             nIRQ_SPI1_ERR  0x0       
-#define              IRQ_SPI2_ERR  0x20000000 /* SPI2 Error */
-#define             nIRQ_SPI2_ERR  0x0       
-#define             IRQ_UART1_ERR  0x40000000 /* UART1 Error */
-#define            nIRQ_UART1_ERR  0x0       
-#define             IRQ_UART2_ERR  0x80000000 /* UART2 Error */
-#define            nIRQ_UART2_ERR  0x0       
+#define              DMA0_ERR  0x2        /* DMA Controller 0 Error */
+#define             EPPI0_ERR  0x4        /* EPPI0 Error */
+#define            SPORT0_ERR  0x8        /* SPORT0 Error */
+#define            SPORT1_ERR  0x10       /* SPORT1 Error */
+#define              SPI0_ERR  0x20       /* SPI0 Error */
+#define             UART0_ERR  0x40       /* UART0 Error */
+#define                   RTC  0x80       /* Real-Time Clock */
+#define                 DMA12  0x100      /* DMA Channel 12 */
+#define                  DMA0  0x200      /* DMA Channel 0 */
+#define                  DMA1  0x400      /* DMA Channel 1 */
+#define                  DMA2  0x800      /* DMA Channel 2 */
+#define                  DMA3  0x1000     /* DMA Channel 3 */
+#define                  DMA4  0x2000     /* DMA Channel 4 */
+#define                  DMA6  0x4000     /* DMA Channel 6 */
+#define                  DMA7  0x8000     /* DMA Channel 7 */
+#define                 PINT0  0x80000    /* Pin Interrupt 0 */
+#define                 PINT1  0x100000   /* Pin Interrupt 1 */
+#define                 MDMA0  0x200000   /* Memory DMA Stream 0 */
+#define                 MDMA1  0x400000   /* Memory DMA Stream 1 */
+#define                  WDOG  0x800000   /* Watchdog Timer */
+#define              DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
+#define            SPORT2_ERR  0x2000000  /* SPORT2 Error */
+#define            SPORT3_ERR  0x4000000  /* SPORT3 Error */
+#define               MXVR_SD  0x8000000  /* MXVR Synchronous Data */
+#define              SPI1_ERR  0x10000000 /* SPI1 Error */
+#define              SPI2_ERR  0x20000000 /* SPI2 Error */
+#define             UART1_ERR  0x40000000 /* UART1 Error */
+#define             UART2_ERR  0x80000000 /* UART2 Error */
 
 /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
 
-#define              IRQ_CAN0_ERR  0x1        /* CAN0 Error */
-#define             nIRQ_CAN0_ERR  0x0       
-#define                 IRQ_DMA18  0x2        /* DMA Channel 18 */
-#define                nIRQ_DMA18  0x0       
-#define                 IRQ_DMA19  0x4        /* DMA Channel 19 */
-#define                nIRQ_DMA19  0x0       
-#define                 IRQ_DMA20  0x8        /* DMA Channel 20 */
-#define                nIRQ_DMA20  0x0       
-#define                 IRQ_DMA21  0x10       /* DMA Channel 21 */
-#define                nIRQ_DMA21  0x0       
-#define                 IRQ_DMA13  0x20       /* DMA Channel 13 */
-#define                nIRQ_DMA13  0x0       
-#define                 IRQ_DMA14  0x40       /* DMA Channel 14 */
-#define                nIRQ_DMA14  0x0       
-#define                  IRQ_DMA5  0x80       /* DMA Channel 5 */
-#define                 nIRQ_DMA5  0x0       
-#define                 IRQ_DMA23  0x100      /* DMA Channel 23 */
-#define                nIRQ_DMA23  0x0       
-#define                  IRQ_DMA8  0x200      /* DMA Channel 8 */
-#define                 nIRQ_DMA8  0x0       
-#define                  IRQ_DMA9  0x400      /* DMA Channel 9 */
-#define                 nIRQ_DMA9  0x0       
-#define                 IRQ_DMA10  0x800      /* DMA Channel 10 */
-#define                nIRQ_DMA10  0x0       
-#define                 IRQ_DMA11  0x1000     /* DMA Channel 11 */
-#define                nIRQ_DMA11  0x0       
-#define                  IRQ_TWI0  0x2000     /* TWI0 */
-#define                 nIRQ_TWI0  0x0       
-#define                  IRQ_TWI1  0x4000     /* TWI1 */
-#define                 nIRQ_TWI1  0x0       
-#define               IRQ_CAN0_RX  0x8000     /* CAN0 Receive */
-#define              nIRQ_CAN0_RX  0x0       
-#define               IRQ_CAN0_TX  0x10000    /* CAN0 Transmit */
-#define              nIRQ_CAN0_TX  0x0       
-#define                 IRQ_MDMA2  0x20000    /* Memory DMA Stream 0 */
-#define                nIRQ_MDMA2  0x0       
-#define                 IRQ_MDMA3  0x40000    /* Memory DMA Stream 1 */
-#define                nIRQ_MDMA3  0x0       
-#define             IRQ_MXVR_STAT  0x80000    /* MXVR Status */
-#define            nIRQ_MXVR_STAT  0x0       
-#define               IRQ_MXVR_CM  0x100000   /* MXVR Control Message */
-#define              nIRQ_MXVR_CM  0x0       
-#define               IRQ_MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
-#define              nIRQ_MXVR_AP  0x0       
-#define             IRQ_EPPI1_ERR  0x400000   /* EPPI1 Error */
-#define            nIRQ_EPPI1_ERR  0x0       
-#define             IRQ_EPPI2_ERR  0x800000   /* EPPI2 Error */
-#define            nIRQ_EPPI2_ERR  0x0       
-#define             IRQ_UART3_ERR  0x1000000  /* UART3 Error */
-#define            nIRQ_UART3_ERR  0x0       
-#define              IRQ_HOST_ERR  0x2000000  /* Host DMA Port Error */
-#define             nIRQ_HOST_ERR  0x0       
-#define               IRQ_USB_ERR  0x4000000  /* USB Error */
-#define              nIRQ_USB_ERR  0x0       
-#define              IRQ_PIXC_ERR  0x8000000  /* Pixel Compositor Error */
-#define             nIRQ_PIXC_ERR  0x0       
-#define               IRQ_NFC_ERR  0x10000000 /* Nand Flash Controller Error */
-#define              nIRQ_NFC_ERR  0x0       
-#define             IRQ_ATAPI_ERR  0x20000000 /* ATAPI Error */
-#define            nIRQ_ATAPI_ERR  0x0       
-#define              IRQ_CAN1_ERR  0x40000000 /* CAN1 Error */
-#define             nIRQ_CAN1_ERR  0x0       
-#define             IRQ_DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
-#define            nIRQ_DMAR0_ERR  0x0       
-#define             IRQ_DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
-#define            nIRQ_DMAR1_ERR  0x0       
-#define                 IRQ_DMAR0  0x80000000 /* DMAR0 Block */
-#define                nIRQ_DMAR0  0x0       
-#define                 IRQ_DMAR1  0x80000000 /* DMAR1 Block */
-#define                nIRQ_DMAR1  0x0       
+#define              CAN0_ERR  0x1        /* CAN0 Error */
+#define                 DMA18  0x2        /* DMA Channel 18 */
+#define                 DMA19  0x4        /* DMA Channel 19 */
+#define                 DMA20  0x8        /* DMA Channel 20 */
+#define                 DMA21  0x10       /* DMA Channel 21 */
+#define                 DMA13  0x20       /* DMA Channel 13 */
+#define                 DMA14  0x40       /* DMA Channel 14 */
+#define                  DMA5  0x80       /* DMA Channel 5 */
+#define                 DMA23  0x100      /* DMA Channel 23 */
+#define                  DMA8  0x200      /* DMA Channel 8 */
+#define                  DMA9  0x400      /* DMA Channel 9 */
+#define                 DMA10  0x800      /* DMA Channel 10 */
+#define                 DMA11  0x1000     /* DMA Channel 11 */
+#define                  TWI0  0x2000     /* TWI0 */
+#define                  TWI1  0x4000     /* TWI1 */
+#define               CAN0_RX  0x8000     /* CAN0 Receive */
+#define               CAN0_TX  0x10000    /* CAN0 Transmit */
+#define                 MDMA2  0x20000    /* Memory DMA Stream 0 */
+#define                 MDMA3  0x40000    /* Memory DMA Stream 1 */
+#define             MXVR_STAT  0x80000    /* MXVR Status */
+#define               MXVR_CM  0x100000   /* MXVR Control Message */
+#define               MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
+#define             EPPI1_ERR  0x400000   /* EPPI1 Error */
+#define             EPPI2_ERR  0x800000   /* EPPI2 Error */
+#define             UART3_ERR  0x1000000  /* UART3 Error */
+#define              HOST_ERR  0x2000000  /* Host DMA Port Error */
+#define               USB_ERR  0x4000000  /* USB Error */
+#define              PIXC_ERR  0x8000000  /* Pixel Compositor Error */
+#define               NFC_ERR  0x10000000 /* Nand Flash Controller Error */
+#define             ATAPI_ERR  0x20000000 /* ATAPI Error */
+#define              CAN1_ERR  0x40000000 /* CAN1 Error */
+#define             DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
+#define             DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
+#define                 DMAR0  0x80000000 /* DMAR0 Block */
+#define                 DMAR1  0x80000000 /* DMAR1 Block */
 
 /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
 
-#define                 IRQ_DMA15  0x1        /* DMA Channel 15 */
-#define                nIRQ_DMA15  0x0       
-#define                 IRQ_DMA16  0x2        /* DMA Channel 16 */
-#define                nIRQ_DMA16  0x0       
-#define                 IRQ_DMA17  0x4        /* DMA Channel 17 */
-#define                nIRQ_DMA17  0x0       
-#define                 IRQ_DMA22  0x8        /* DMA Channel 22 */
-#define                nIRQ_DMA22  0x0       
-#define                   IRQ_CNT  0x10       /* Counter */
-#define                  nIRQ_CNT  0x0       
-#define                   IRQ_KEY  0x20       /* Keypad */
-#define                  nIRQ_KEY  0x0       
-#define               IRQ_CAN1_RX  0x40       /* CAN1 Receive */
-#define              nIRQ_CAN1_RX  0x0       
-#define               IRQ_CAN1_TX  0x80       /* CAN1 Transmit */
-#define              nIRQ_CAN1_TX  0x0       
-#define             IRQ_SDH_MASK0  0x100      /* SDH Mask 0 */
-#define            nIRQ_SDH_MASK0  0x0       
-#define             IRQ_SDH_MASK1  0x200      /* SDH Mask 1 */
-#define            nIRQ_SDH_MASK1  0x0       
-#define              IRQ_USB_EINT  0x400      /* USB Exception */
-#define             nIRQ_USB_EINT  0x0       
-#define              IRQ_USB_INT0  0x800      /* USB Interrupt 0 */
-#define             nIRQ_USB_INT0  0x0       
-#define              IRQ_USB_INT1  0x1000     /* USB Interrupt 1 */
-#define             nIRQ_USB_INT1  0x0       
-#define              IRQ_USB_INT2  0x2000     /* USB Interrupt 2 */
-#define             nIRQ_USB_INT2  0x0       
-#define            IRQ_USB_DMAINT  0x4000     /* USB DMA */
-#define           nIRQ_USB_DMAINT  0x0       
-#define                IRQ_OTPSEC  0x8000     /* OTP Access Complete */
-#define               nIRQ_OTPSEC  0x0       
-#define                IRQ_TIMER0  0x400000   /* Timer 0 */
-#define               nIRQ_TIMER0  0x0       
-#define                IRQ_TIMER1  0x800000   /* Timer 1 */
-#define               nIRQ_TIMER1  0x0       
-#define                IRQ_TIMER2  0x1000000  /* Timer 2 */
-#define               nIRQ_TIMER2  0x0       
-#define                IRQ_TIMER3  0x2000000  /* Timer 3 */
-#define               nIRQ_TIMER3  0x0       
-#define                IRQ_TIMER4  0x4000000  /* Timer 4 */
-#define               nIRQ_TIMER4  0x0       
-#define                IRQ_TIMER5  0x8000000  /* Timer 5 */
-#define               nIRQ_TIMER5  0x0       
-#define                IRQ_TIMER6  0x10000000 /* Timer 6 */
-#define               nIRQ_TIMER6  0x0       
-#define                IRQ_TIMER7  0x20000000 /* Timer 7 */
-#define               nIRQ_TIMER7  0x0       
-#define                 IRQ_PINT2  0x40000000 /* Pin Interrupt 2 */
-#define                nIRQ_PINT2  0x0       
-#define                 IRQ_PINT3  0x80000000 /* Pin Interrupt 3 */
-#define                nIRQ_PINT3  0x0       
+#define                 DMA15  0x1        /* DMA Channel 15 */
+#define                 DMA16  0x2        /* DMA Channel 16 */
+#define                 DMA17  0x4        /* DMA Channel 17 */
+#define                 DMA22  0x8        /* DMA Channel 22 */
+#define                   CNT  0x10       /* Counter */
+#define                   KEY  0x20       /* Keypad */
+#define               CAN1_RX  0x40       /* CAN1 Receive */
+#define               CAN1_TX  0x80       /* CAN1 Transmit */
+#define             SDH_INT_MASK0  0x100      /* SDH Mask 0 */
+#define             SDH_INT_MASK1  0x200      /* SDH Mask 1 */
+#define              USB_EINT  0x400      /* USB Exception */
+#define              USB_INT0  0x800      /* USB Interrupt 0 */
+#define              USB_INT1  0x1000     /* USB Interrupt 1 */
+#define              USB_INT2  0x2000     /* USB Interrupt 2 */
+#define            USB_DMAINT  0x4000     /* USB DMA */
+#define                OTPSEC  0x8000     /* OTP Access Complete */
+#define                TIMER0  0x400000   /* Timer 0 */
+#define                TIMER1  0x800000   /* Timer 1 */
+#define                TIMER2  0x1000000  /* Timer 2 */
+#define                TIMER3  0x2000000  /* Timer 3 */
+#define                TIMER4  0x4000000  /* Timer 4 */
+#define                TIMER5  0x8000000  /* Timer 5 */
+#define                TIMER6  0x10000000 /* Timer 6 */
+#define                TIMER7  0x20000000 /* Timer 7 */
+#define                 PINT2  0x40000000 /* Pin Interrupt 2 */
+#define                 PINT3  0x80000000 /* Pin Interrupt 3 */
 
 /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
 
 #define                     DMAEN  0x1        /* DMA Channel Enable */
-#define                    nDMAEN  0x0       
 #define                       WNR  0x2        /* DMA Direction */
-#define                      nWNR  0x0       
-#define                    WDSIZE  0xc        /* Transfer Word Size */
+#define                  WDSIZE_8  0x0        /* Transfer Word Size = 8 */
+#define                 WDSIZE_16  0x4        /* Transfer Word Size = 16 */
+#define                 WDSIZE_32  0x8        /* Transfer Word Size = 32 */
 #define                     DMA2D  0x10       /* DMA Mode */
-#define                    nDMA2D  0x0       
 #define                   RESTART  0x20       /* Work Unit Transitions */
-#define                  nRESTART  0x0       
 #define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
-#define                   nDI_SEL  0x0       
 #define                     DI_EN  0x80       /* Data Interrupt Enable */
-#define                    nDI_EN  0x0       
 #define                    NDSIZE  0xf00      /* Flex Descriptor Size */
 #define                   DMAFLOW  0xf000     /* Next Operation */
 
 /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
 
 #define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
-#define                 nDMA_DONE  0x0       
 #define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
-#define                  nDMA_ERR  0x0       
 #define                    DFETCH  0x4        /* DMA Descriptor Fetch */
-#define                   nDFETCH  0x0       
 #define                   DMA_RUN  0x8        /* DMA Channel Running */
-#define                  nDMA_RUN  0x0       
 
 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
 
 #define                     CTYPE  0x40       /* DMA Channel Type */
-#define                    nCTYPE  0x0       
 #define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
 
 /* Bit masks for DMACx_TCPER */
@@ -1756,29 +1669,28 @@
 /* Bit masks for DMAC1_PERIMUX */
 
 #define                   PMUXSDH  0x1        /* Peripheral Select for DMA22 channel */
-#define                  nPMUXSDH  0x0       
 
-/* Bit masks for EBIU_AMGCTL */
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
 
-#define                    AMCKEN  0x1        /* Async Memory Enable */
-#define                   nAMCKEN  0x0       
-#define                     AMBEN  0xe        /* Async bank enable */
 
 /* Bit masks for EBIU_AMBCTL0 */
 
 #define                   B0RDYEN  0x1        /* Bank 0 ARDY Enable */
-#define                  nB0RDYEN  0x0       
 #define                  B0RDYPOL  0x2        /* Bank 0 ARDY Polarity */
-#define                 nB0RDYPOL  0x0       
 #define                      B0TT  0xc        /* Bank 0 transition time */
 #define                      B0ST  0x30       /* Bank 0 Setup time */
 #define                      B0HT  0xc0       /* Bank 0 Hold time */
 #define                     B0RAT  0xf00      /* Bank 0 Read access time */
 #define                     B0WAT  0xf000     /* Bank 0 write access time */
 #define                   B1RDYEN  0x10000    /* Bank 1 ARDY Enable */
-#define                  nB1RDYEN  0x0       
 #define                  B1RDYPOL  0x20000    /* Bank 1 ARDY Polarity */
-#define                 nB1RDYPOL  0x0       
 #define                      B1TT  0xc0000    /* Bank 1 transition time */
 #define                      B1ST  0x300000   /* Bank 1 Setup time */
 #define                      B1HT  0xc00000   /* Bank 1 Hold time */
@@ -1788,18 +1700,14 @@
 /* Bit masks for EBIU_AMBCTL1 */
 
 #define                   B2RDYEN  0x1        /* Bank 2 ARDY Enable */
-#define                  nB2RDYEN  0x0       
 #define                  B2RDYPOL  0x2        /* Bank 2 ARDY Polarity */
-#define                 nB2RDYPOL  0x0       
 #define                      B2TT  0xc        /* Bank 2 transition time */
 #define                      B2ST  0x30       /* Bank 2 Setup time */
 #define                      B2HT  0xc0       /* Bank 2 Hold time */
 #define                     B2RAT  0xf00      /* Bank 2 Read access time */
 #define                     B2WAT  0xf000     /* Bank 2 write access time */
 #define                   B3RDYEN  0x10000    /* Bank 3 ARDY Enable */
-#define                  nB3RDYEN  0x0       
 #define                  B3RDYPOL  0x20000    /* Bank 3 ARDY Polarity */
-#define                 nB3RDYPOL  0x0       
 #define                      B3TT  0xc0000    /* Bank 3 transition time */
 #define                      B3ST  0x300000   /* Bank 3 Setup time */
 #define                      B3HT  0xc00000   /* Bank 3 Hold time */
@@ -1823,19 +1731,15 @@
 /* Bit masks for EBIU_FCTL */
 
 #define               TESTSETLOCK  0x1        /* Test set lock */
-#define              nTESTSETLOCK  0x0       
 #define                      BCLK  0x6        /* Burst clock frequency */
 #define                      PGWS  0x38       /* Page wait states */
 #define                      PGSZ  0x40       /* Page size */
-#define                     nPGSZ  0x0       
 #define                      RDDL  0x380      /* Read data delay */
 
 /* Bit masks for EBIU_ARBSTAT */
 
 #define                   ARBSTAT  0x1        /* Arbitration status */
-#define                  nARBSTAT  0x0       
 #define                    BGSTAT  0x2        /* Bus grant status */
-#define                   nBGSTAT  0x0       
 
 /* Bit masks for EBIU_DDRCTL0 */
 
@@ -1861,9 +1765,7 @@
 #define               BURSTLENGTH  0x7        /* Burst length */
 #define                CASLATENCY  0x70       /* CAS latency */
 #define                  DLLRESET  0x100      /* DLL Reset */
-#define                 nDLLRESET  0x0       
 #define                      REGE  0x1000     /* Register mode enable */
-#define                     nREGE  0x0       
 
 /* Bit masks for EBIU_DDRCTL3 */
 
@@ -1876,30 +1778,19 @@
 #define                DEB3_PFLEN  0x30       /* Pre fetch length for DEB3 accesses */
 #define          DEB_ARB_PRIORITY  0x700      /* Arbitration between DEB busses */
 #define               DEB1_URGENT  0x1000     /* DEB1 Urgent */
-#define              nDEB1_URGENT  0x0       
 #define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
-#define              nDEB2_URGENT  0x0       
 #define               DEB3_URGENT  0x4000     /* DEB3 Urgent */
-#define              nDEB3_URGENT  0x0       
 
 /* Bit masks for EBIU_ERRMST */
 
 #define                DEB1_ERROR  0x1        /* DEB1 Error */
-#define               nDEB1_ERROR  0x0       
 #define                DEB2_ERROR  0x2        /* DEB2 Error */
-#define               nDEB2_ERROR  0x0       
 #define                DEB3_ERROR  0x4        /* DEB3 Error */
-#define               nDEB3_ERROR  0x0       
 #define                CORE_ERROR  0x8        /* Core error */
-#define               nCORE_ERROR  0x0       
 #define                DEB_MERROR  0x10       /* DEB1 Error (2nd) */
-#define               nDEB_MERROR  0x0       
 #define               DEB2_MERROR  0x20       /* DEB2 Error (2nd) */
-#define              nDEB2_MERROR  0x0       
 #define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
-#define              nDEB3_MERROR  0x0       
 #define               CORE_MERROR  0x80       /* Core Error (2nd) */
-#define              nCORE_MERROR  0x0       
 
 /* Bit masks for EBIU_ERRADD */
 
@@ -1908,15 +1799,10 @@
 /* Bit masks for EBIU_RSTCTL */
 
 #define                 DDRSRESET  0x1        /* DDR soft reset */
-#define                nDDRSRESET  0x0       
 #define               PFTCHSRESET  0x4        /* DDR prefetch reset */
-#define              nPFTCHSRESET  0x0       
 #define                     SRREQ  0x8        /* Self-refresh request */
-#define                    nSRREQ  0x0       
 #define                     SRACK  0x10       /* Self-refresh acknowledge */
-#define                    nSRACK  0x0       
 #define                MDDRENABLE  0x20       /* Mobile DDR enable */
-#define               nMDDRENABLE  0x0       
 
 /* Bit masks for EBIU_DDRBRC0 */
 
@@ -2013,136 +1899,74 @@
 /* Bit masks for EBIU_DDRMCEN */
 
 #define                B0WCENABLE  0x1        /* Bank 0 write count enable */
-#define               nB0WCENABLE  0x0       
 #define                B1WCENABLE  0x2        /* Bank 1 write count enable */
-#define               nB1WCENABLE  0x0       
 #define                B2WCENABLE  0x4        /* Bank 2 write count enable */
-#define               nB2WCENABLE  0x0       
 #define                B3WCENABLE  0x8        /* Bank 3 write count enable */
-#define               nB3WCENABLE  0x0       
 #define                B4WCENABLE  0x10       /* Bank 4 write count enable */
-#define               nB4WCENABLE  0x0       
 #define                B5WCENABLE  0x20       /* Bank 5 write count enable */
-#define               nB5WCENABLE  0x0       
 #define                B6WCENABLE  0x40       /* Bank 6 write count enable */
-#define               nB6WCENABLE  0x0       
 #define                B7WCENABLE  0x80       /* Bank 7 write count enable */
-#define               nB7WCENABLE  0x0       
 #define                B0RCENABLE  0x100      /* Bank 0 read count enable */
-#define               nB0RCENABLE  0x0       
 #define                B1RCENABLE  0x200      /* Bank 1 read count enable */
-#define               nB1RCENABLE  0x0       
 #define                B2RCENABLE  0x400      /* Bank 2 read count enable */
-#define               nB2RCENABLE  0x0       
 #define                B3RCENABLE  0x800      /* Bank 3 read count enable */
-#define               nB3RCENABLE  0x0       
 #define                B4RCENABLE  0x1000     /* Bank 4 read count enable */
-#define               nB4RCENABLE  0x0       
 #define                B5RCENABLE  0x2000     /* Bank 5 read count enable */
-#define               nB5RCENABLE  0x0       
 #define                B6RCENABLE  0x4000     /* Bank 6 read count enable */
-#define               nB6RCENABLE  0x0       
 #define                B7RCENABLE  0x8000     /* Bank 7 read count enable */
-#define               nB7RCENABLE  0x0       
 #define             ROWACTCENABLE  0x10000    /* DDR Row activate count enable */
-#define            nROWACTCENABLE  0x0       
 #define                RWTCENABLE  0x20000    /* DDR R/W Turn around count enable */
-#define               nRWTCENABLE  0x0       
 #define                 ARCENABLE  0x40000    /* DDR Auto-refresh count enable */
-#define                nARCENABLE  0x0       
 #define                 GC0ENABLE  0x100000   /* DDR Grant count 0 enable */
-#define                nGC0ENABLE  0x0       
 #define                 GC1ENABLE  0x200000   /* DDR Grant count 1 enable */
-#define                nGC1ENABLE  0x0       
 #define                 GC2ENABLE  0x400000   /* DDR Grant count 2 enable */
-#define                nGC2ENABLE  0x0       
 #define                 GC3ENABLE  0x800000   /* DDR Grant count 3 enable */
-#define                nGC3ENABLE  0x0       
 #define                 GCCONTROL  0x3000000  /* DDR Grant Count Control */
 
 /* Bit masks for EBIU_DDRMCCL */
 
 #define                 CB0WCOUNT  0x1        /* Clear write count 0 */
-#define                nCB0WCOUNT  0x0       
 #define                 CB1WCOUNT  0x2        /* Clear write count 1 */
-#define                nCB1WCOUNT  0x0       
 #define                 CB2WCOUNT  0x4        /* Clear write count 2 */
-#define                nCB2WCOUNT  0x0       
 #define                 CB3WCOUNT  0x8        /* Clear write count 3 */
-#define                nCB3WCOUNT  0x0       
 #define                 CB4WCOUNT  0x10       /* Clear write count 4 */
-#define                nCB4WCOUNT  0x0       
 #define                 CB5WCOUNT  0x20       /* Clear write count 5 */
-#define                nCB5WCOUNT  0x0       
 #define                 CB6WCOUNT  0x40       /* Clear write count 6 */
-#define                nCB6WCOUNT  0x0       
 #define                 CB7WCOUNT  0x80       /* Clear write count 7 */
-#define                nCB7WCOUNT  0x0       
 #define                  CBRCOUNT  0x100      /* Clear read count 0 */
-#define                 nCBRCOUNT  0x0       
 #define                 CB1RCOUNT  0x200      /* Clear read count 1 */
-#define                nCB1RCOUNT  0x0       
 #define                 CB2RCOUNT  0x400      /* Clear read count 2 */
-#define                nCB2RCOUNT  0x0       
 #define                 CB3RCOUNT  0x800      /* Clear read count 3 */
-#define                nCB3RCOUNT  0x0       
 #define                 CB4RCOUNT  0x1000     /* Clear read count 4 */
-#define                nCB4RCOUNT  0x0       
 #define                 CB5RCOUNT  0x2000     /* Clear read count 5 */
-#define                nCB5RCOUNT  0x0       
 #define                 CB6RCOUNT  0x4000     /* Clear read count 6 */
-#define                nCB6RCOUNT  0x0       
 #define                 CB7RCOUNT  0x8000     /* Clear read count 7 */
-#define                nCB7RCOUNT  0x0       
 #define                  CRACOUNT  0x10000    /* Clear row activation count */
-#define                 nCRACOUNT  0x0       
 #define                CRWTACOUNT  0x20000    /* Clear R/W turn-around count */
-#define               nCRWTACOUNT  0x0       
 #define                  CARCOUNT  0x40000    /* Clear auto-refresh count */
-#define                 nCARCOUNT  0x0       
 #define                  CG0COUNT  0x100000   /* Clear grant count 0 */
-#define                 nCG0COUNT  0x0       
 #define                  CG1COUNT  0x200000   /* Clear grant count 1 */
-#define                 nCG1COUNT  0x0       
 #define                  CG2COUNT  0x400000   /* Clear grant count 2 */
-#define                 nCG2COUNT  0x0       
 #define                  CG3COUNT  0x800000   /* Clear grant count 3 */
-#define                 nCG3COUNT  0x0       
 
 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
 
 #define                       Px0  0x1        /* GPIO 0 */
-#define                      nPx0  0x0       
 #define                       Px1  0x2        /* GPIO 1 */
-#define                      nPx1  0x0       
 #define                       Px2  0x4        /* GPIO 2 */
-#define                      nPx2  0x0       
 #define                       Px3  0x8        /* GPIO 3 */
-#define                      nPx3  0x0       
 #define                       Px4  0x10       /* GPIO 4 */
-#define                      nPx4  0x0       
 #define                       Px5  0x20       /* GPIO 5 */
-#define                      nPx5  0x0       
 #define                       Px6  0x40       /* GPIO 6 */
-#define                      nPx6  0x0       
 #define                       Px7  0x80       /* GPIO 7 */
-#define                      nPx7  0x0       
 #define                       Px8  0x100      /* GPIO 8 */
-#define                      nPx8  0x0       
 #define                       Px9  0x200      /* GPIO 9 */
-#define                      nPx9  0x0       
 #define                      Px10  0x400      /* GPIO 10 */
-#define                     nPx10  0x0       
 #define                      Px11  0x800      /* GPIO 11 */
-#define                     nPx11  0x0       
 #define                      Px12  0x1000     /* GPIO 12 */
-#define                     nPx12  0x0       
 #define                      Px13  0x2000     /* GPIO 13 */
-#define                     nPx13  0x0       
 #define                      Px14  0x4000     /* GPIO 14 */
-#define                     nPx14  0x0       
 #define                      Px15  0x8000     /* GPIO 15 */
-#define                     nPx15  0x0       
 
 /* Bit masks for PORTA_MUX - PORTJ_MUX */
 
@@ -2167,223 +1991,129 @@
 /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
 
 #define                       IB0  0x1        /* Interrupt Bit 0 */
-#define                      nIB0  0x0       
 #define                       IB1  0x2        /* Interrupt Bit 1 */
-#define                      nIB1  0x0       
 #define                       IB2  0x4        /* Interrupt Bit 2 */
-#define                      nIB2  0x0       
 #define                       IB3  0x8        /* Interrupt Bit 3 */
-#define                      nIB3  0x0       
 #define                       IB4  0x10       /* Interrupt Bit 4 */
-#define                      nIB4  0x0       
 #define                       IB5  0x20       /* Interrupt Bit 5 */
-#define                      nIB5  0x0       
 #define                       IB6  0x40       /* Interrupt Bit 6 */
-#define                      nIB6  0x0       
 #define                       IB7  0x80       /* Interrupt Bit 7 */
-#define                      nIB7  0x0       
 #define                       IB8  0x100      /* Interrupt Bit 8 */
-#define                      nIB8  0x0       
 #define                       IB9  0x200      /* Interrupt Bit 9 */
-#define                      nIB9  0x0       
 #define                      IB10  0x400      /* Interrupt Bit 10 */
-#define                     nIB10  0x0       
 #define                      IB11  0x800      /* Interrupt Bit 11 */
-#define                     nIB11  0x0       
 #define                      IB12  0x1000     /* Interrupt Bit 12 */
-#define                     nIB12  0x0       
 #define                      IB13  0x2000     /* Interrupt Bit 13 */
-#define                     nIB13  0x0       
 #define                      IB14  0x4000     /* Interrupt Bit 14 */
-#define                     nIB14  0x0       
 #define                      IB15  0x8000     /* Interrupt Bit 15 */
-#define                     nIB15  0x0       
 
 /* Bit masks for TIMERx_CONFIG */
 
 #define                     TMODE  0x3        /* Timer Mode */
 #define                  PULSE_HI  0x4        /* Pulse Polarity */
-#define                 nPULSE_HI  0x0       
 #define                PERIOD_CNT  0x8        /* Period Count */
-#define               nPERIOD_CNT  0x0       
 #define                   IRQ_ENA  0x10       /* Interrupt Request Enable */
-#define                  nIRQ_ENA  0x0       
 #define                   TIN_SEL  0x20       /* Timer Input Select */
-#define                  nTIN_SEL  0x0       
 #define                   OUT_DIS  0x40       /* Output Pad Disable */
-#define                  nOUT_DIS  0x0       
 #define                   CLK_SEL  0x80       /* Timer Clock Select */
-#define                  nCLK_SEL  0x0       
 #define                 TOGGLE_HI  0x100      /* Toggle Mode */
-#define                nTOGGLE_HI  0x0       
 #define                   EMU_RUN  0x200      /* Emulation Behavior Select */
-#define                  nEMU_RUN  0x0       
 #define                   ERR_TYP  0xc000     /* Error Type */
 
 /* Bit masks for TIMER_ENABLE0 */
 
 #define                    TIMEN0  0x1        /* Timer 0 Enable */
-#define                   nTIMEN0  0x0       
 #define                    TIMEN1  0x2        /* Timer 1 Enable */
-#define                   nTIMEN1  0x0       
 #define                    TIMEN2  0x4        /* Timer 2 Enable */
-#define                   nTIMEN2  0x0       
 #define                    TIMEN3  0x8        /* Timer 3 Enable */
-#define                   nTIMEN3  0x0       
 #define                    TIMEN4  0x10       /* Timer 4 Enable */
-#define                   nTIMEN4  0x0       
 #define                    TIMEN5  0x20       /* Timer 5 Enable */
-#define                   nTIMEN5  0x0       
 #define                    TIMEN6  0x40       /* Timer 6 Enable */
-#define                   nTIMEN6  0x0       
 #define                    TIMEN7  0x80       /* Timer 7 Enable */
-#define                   nTIMEN7  0x0       
 
 /* Bit masks for TIMER_DISABLE0 */
 
 #define                   TIMDIS0  0x1        /* Timer 0 Disable */
-#define                  nTIMDIS0  0x0       
 #define                   TIMDIS1  0x2        /* Timer 1 Disable */
-#define                  nTIMDIS1  0x0       
 #define                   TIMDIS2  0x4        /* Timer 2 Disable */
-#define                  nTIMDIS2  0x0       
 #define                   TIMDIS3  0x8        /* Timer 3 Disable */
-#define                  nTIMDIS3  0x0       
 #define                   TIMDIS4  0x10       /* Timer 4 Disable */
-#define                  nTIMDIS4  0x0       
 #define                   TIMDIS5  0x20       /* Timer 5 Disable */
-#define                  nTIMDIS5  0x0       
 #define                   TIMDIS6  0x40       /* Timer 6 Disable */
-#define                  nTIMDIS6  0x0       
 #define                   TIMDIS7  0x80       /* Timer 7 Disable */
-#define                  nTIMDIS7  0x0       
 
 /* Bit masks for TIMER_STATUS0 */
 
 #define                    TIMIL0  0x1        /* Timer 0 Interrupt */
-#define                   nTIMIL0  0x0       
 #define                    TIMIL1  0x2        /* Timer 1 Interrupt */
-#define                   nTIMIL1  0x0       
 #define                    TIMIL2  0x4        /* Timer 2 Interrupt */
-#define                   nTIMIL2  0x0       
 #define                    TIMIL3  0x8        /* Timer 3 Interrupt */
-#define                   nTIMIL3  0x0       
 #define                 TOVF_ERR0  0x10       /* Timer 0 Counter Overflow */
-#define                nTOVF_ERR0  0x0       
 #define                 TOVF_ERR1  0x20       /* Timer 1 Counter Overflow */
-#define                nTOVF_ERR1  0x0       
 #define                 TOVF_ERR2  0x40       /* Timer 2 Counter Overflow */
-#define                nTOVF_ERR2  0x0       
 #define                 TOVF_ERR3  0x80       /* Timer 3 Counter Overflow */
-#define                nTOVF_ERR3  0x0       
 #define                     TRUN0  0x1000     /* Timer 0 Slave Enable Status */
-#define                    nTRUN0  0x0       
 #define                     TRUN1  0x2000     /* Timer 1 Slave Enable Status */
-#define                    nTRUN1  0x0       
 #define                     TRUN2  0x4000     /* Timer 2 Slave Enable Status */
-#define                    nTRUN2  0x0       
 #define                     TRUN3  0x8000     /* Timer 3 Slave Enable Status */
-#define                    nTRUN3  0x0       
 #define                    TIMIL4  0x10000    /* Timer 4 Interrupt */
-#define                   nTIMIL4  0x0       
 #define                    TIMIL5  0x20000    /* Timer 5 Interrupt */
-#define                   nTIMIL5  0x0       
 #define                    TIMIL6  0x40000    /* Timer 6 Interrupt */
-#define                   nTIMIL6  0x0       
 #define                    TIMIL7  0x80000    /* Timer 7 Interrupt */
-#define                   nTIMIL7  0x0       
 #define                 TOVF_ERR4  0x100000   /* Timer 4 Counter Overflow */
-#define                nTOVF_ERR4  0x0       
 #define                 TOVF_ERR5  0x200000   /* Timer 5 Counter Overflow */
-#define                nTOVF_ERR5  0x0       
 #define                 TOVF_ERR6  0x400000   /* Timer 6 Counter Overflow */
-#define                nTOVF_ERR6  0x0       
 #define                 TOVF_ERR7  0x800000   /* Timer 7 Counter Overflow */
-#define                nTOVF_ERR7  0x0       
 #define                     TRUN4  0x10000000 /* Timer 4 Slave Enable Status */
-#define                    nTRUN4  0x0       
 #define                     TRUN5  0x20000000 /* Timer 5 Slave Enable Status */
-#define                    nTRUN5  0x0       
 #define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
-#define                    nTRUN6  0x0       
 #define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
-#define                    nTRUN7  0x0       
 
 /* Bit masks for WDOG_CTL */
 
 #define                      WDEV  0x6        /* Watchdog Event */
 #define                      WDEN  0xff0      /* Watchdog Enable */
 #define                      WDRO  0x8000     /* Watchdog Rolled Over */
-#define                     nWDRO  0x0       
 
 /* Bit masks for CNT_CONFIG */
 
 #define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0       
 #define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0       
 #define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0       
 #define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0       
 #define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0       
 #define                   CNTMODE  0x700      /* Counter Operating Mode */
 #define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0       
 #define                   BNDMODE  0x3000     /* Boundary register Mode */
 #define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0       
 
 /* Bit masks for CNT_IMASK */
 
 #define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0       
 #define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0       
 #define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0       
 #define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0       
 #define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0       
 #define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0       
 #define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0       
 #define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0       
 #define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0       
 #define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0       
 #define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0       
 
 /* Bit masks for CNT_STATUS */
 
 #define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0       
 #define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0       
 #define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0       
 #define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0       
 #define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0       
 #define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0       
 #define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0       
 #define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0       
 #define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0       
 #define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0       
 #define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0       
 
 /* Bit masks for CNT_COMMAND */
 
@@ -2391,7 +2121,6 @@
 #define                    W1LMIN  0xf0       /* Load Min Register */
 #define                    W1LMAX  0xf00      /* Load Max Register */
 #define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0       
 
 /* Bit masks for CNT_DEBOUNCE */
 
@@ -2407,42 +2136,25 @@
 /* Bit masks for RTC_ICTL */
 
 #define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
-#define nSTOPWATCH_INTERRUPT_ENABLE  0x0       
 #define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
-#define   nALARM_INTERRUPT_ENABLE  0x0       
 #define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
-#define nSECONDS_INTERRUPT_ENABLE  0x0       
 #define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
-#define nMINUTES_INTERRUPT_ENABLE  0x0       
 #define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
-#define   nHOURS_INTERRUPT_ENABLE  0x0       
 #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
-#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x0       
 #define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
-#define nDAY_ALARM_INTERRUPT_ENABLE  0x0       
 #define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
-#define nWRITE_COMPLETE_INTERRUPT_ENABLE  0x0       
 
 /* Bit masks for RTC_ISTAT */
 
 #define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
-#define     nSTOPWATCH_EVENT_FLAG  0x0       
 #define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
-#define         nALARM_EVENT_FLAG  0x0       
 #define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
-#define       nSECONDS_EVENT_FLAG  0x0       
 #define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
-#define       nMINUTES_EVENT_FLAG  0x0       
 #define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
-#define         nHOURS_EVENT_FLAG  0x0       
 #define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
-#define nTWENTY_FOUR_HOURS_EVENT_FLAG  0x0       
 #define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
-#define     nDAY_ALARM_EVENT_FLAG  0x0       
 #define     WRITE_PENDING__STATUS  0x4000     /* Write Pending  Status */
-#define    nWRITE_PENDING__STATUS  0x0       
 #define            WRITE_COMPLETE  0x8000     /* Write Complete */
-#define           nWRITE_COMPLETE  0x0       
 
 /* Bit masks for RTC_SWCNT */
 
@@ -2458,21 +2170,15 @@
 /* Bit masks for RTC_PREN */
 
 #define                      PREN  0x1        /* Prescaler Enable */
-#define                     nPREN  0x0       
 
 /* Bit masks for OTP_CONTROL */
 
 #define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
 #define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                     nFIEN  0x0       
 #define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                 nFTESTDEC  0x0       
 #define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                  nFWRTEST  0x0       
 #define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                    nFRDEN  0x0       
 #define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-#define                    nFWREN  0x0       
 
 /* Bit masks for OTP_BEN */
 
@@ -2481,15 +2187,10 @@
 /* Bit masks for OTP_STATUS */
 
 #define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    nFCOMP  0x0       
 #define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                   nFERROR  0x0       
 #define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                 nMMRGLOAD  0x0       
 #define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                 nMMRGLOCK  0x0       
 #define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-#define                   nFPGMEN  0x0       
 
 /* Bit masks for OTP_TIMING */
 
@@ -2503,42 +2204,29 @@
 /* Bit masks for SECURE_SYSSWT */
 
 #define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0       
 #define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0       
 #define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
 #define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
 #define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
 #define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0       
 #define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0       
 #define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0       
 #define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0       
 #define                    L2DABL  0x70000    /* L2 Memory Disable. */
 
 /* Bit masks for SECURE_CONTROL */
 
 #define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0       
 #define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0       
 #define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0       
 #define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0       
 
 /* Bit masks for SECURE_STATUS */
 
 #define                   SECMODE  0x3        /* Secured Mode Control State */
 #define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0       
 #define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0       
 #define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0       
 #define                   SECSTAT  0xe0       /* Secure Status */
 
 /* Bit masks for PLL_DIV */
@@ -2550,42 +2238,25 @@
 
 #define                      MSEL  0x7e00     /* Multiplier Select */
 #define                    BYPASS  0x100      /* PLL Bypass Enable */
-#define                   nBYPASS  0x0       
 #define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
-#define             nOUTPUT_DELAY  0x0       
 #define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
-#define              nINPUT_DELAY  0x0       
 #define                      PDWN  0x20       /* Power Down */
-#define                     nPDWN  0x0       
 #define                    STOPCK  0x8        /* Stop Clock */
-#define                   nSTOPCK  0x0       
 #define                   PLL_OFF  0x2        /* Disable PLL */
-#define                  nPLL_OFF  0x0       
 #define                        DF  0x1        /* Divide Frequency */
-#define                       nDF  0x0       
 
 /* Bit masks for PLL_STAT */
 
 #define                PLL_LOCKED  0x20       /* PLL Locked Status */
-#define               nPLL_LOCKED  0x0       
 #define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
-#define       nACTIVE_PLLDISABLED  0x0       
 #define                   FULL_ON  0x2        /* Full-On Mode */
-#define                  nFULL_ON  0x0       
 #define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
-#define        nACTIVE_PLLENABLED  0x0       
 #define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
-#define                    nRTCWS  0x0       
 #define                     CANWS  0x800      /* CAN Wake-Up Status */
-#define                    nCANWS  0x0       
 #define                     USBWS  0x2000     /* USB Wake-Up Status */
-#define                    nUSBWS  0x0       
 #define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
-#define                   nKPADWS  0x0       
 #define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
-#define                    nROTWS  0x0       
 #define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
-#define                     nGPWS  0x0       
 
 /* Bit masks for VR_CTL */
 
@@ -2593,79 +2264,52 @@
 #define                      GAIN  0xc        /* Voltage Output Level Gain */
 #define                      VLEV  0xf0       /* Internal Voltage Level */
 #define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
-#define                  nSCKELOW  0x0       
 #define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
-#define                     nWAKE  0x0       
 #define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
-#define                    nCANWE  0x0       
 #define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
-#define                     nGPWE  0x0       
 #define                     USBWE  0x800      /* USB Wake-Up Enable */
-#define                    nUSBWE  0x0       
 #define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
-#define                   nKPADWE  0x0       
 #define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
-#define                    nROTWE  0x0       
 
 /* Bit masks for NFC_CTL */
 
 #define                    WR_DLY  0xf        /* Write Strobe Delay */
 #define                    RD_DLY  0xf0       /* Read Strobe Delay */
 #define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   nNWIDTH  0x0       
 #define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0       
 
 /* Bit masks for NFC_STAT */
 
 #define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0       
 #define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0       
 #define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0       
 #define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0       
 #define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0       
 
 /* Bit masks for NFC_IRQSTAT */
 
 #define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0       
 #define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0       
 #define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0       
 #define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0       
 #define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0       
 
 /* Bit masks for NFC_IRQMASK */
 
 #define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0       
 #define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0       
 #define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define             nMASK_WBEMPTY  0x0       
 #define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0       
 #define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0       
 
 /* Bit masks for NFC_RST */
 
 #define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0       
 
 /* Bit masks for NFC_PGCTL */
 
 #define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0       
 #define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0       
 
 /* Bit masks for NFC_ECC0 */
 
@@ -2690,56 +2334,34 @@
 /* Bit masks for CAN0_CONTROL */
 
 #define                       SRS  0x1        /* Software Reset */
-#define                      nSRS  0x0       
 #define                       DNM  0x2        /* DeviceNet Mode */
-#define                      nDNM  0x0       
 #define                       ABO  0x4        /* Auto Bus On */
-#define                      nABO  0x0       
 #define                       WBA  0x10       /* Wakeup On CAN Bus Activity */
-#define                      nWBA  0x0       
 #define                       SMR  0x20       /* Sleep Mode Request */
-#define                      nSMR  0x0       
 #define                       CSR  0x40       /* CAN Suspend Mode Request */
-#define                      nCSR  0x0       
 #define                       CCR  0x80       /* CAN Configuration Mode Request */
-#define                      nCCR  0x0       
 
 /* Bit masks for CAN0_STATUS */
 
 #define                        WT  0x1        /* CAN Transmit Warning Flag */
-#define                       nWT  0x0       
 #define                        WR  0x2        /* CAN Receive Warning Flag */
-#define                       nWR  0x0       
 #define                        EP  0x4        /* CAN Error Passive Mode */
-#define                       nEP  0x0       
 #define                       EBO  0x8        /* CAN Error Bus Off Mode */
-#define                      nEBO  0x0       
 #define                       CSA  0x40       /* CAN Suspend Mode Acknowledge */
-#define                      nCSA  0x0       
 #define                       CCA  0x80       /* CAN Configuration Mode Acknowledge */
-#define                      nCCA  0x0       
 #define                     MBPTR  0x1f00     /* Mailbox Pointer */
 #define                       TRM  0x4000     /* Transmit Mode Status */
-#define                      nTRM  0x0       
 #define                       REC  0x8000     /* Receive Mode Status */
-#define                      nREC  0x0       
 
 /* Bit masks for CAN0_DEBUG */
 
 #define                       DEC  0x1        /* Disable Transmit/Receive Error Counters */
-#define                      nDEC  0x0       
 #define                       DRI  0x2        /* Disable CANRX Input Pin */
-#define                      nDRI  0x0       
 #define                       DTO  0x4        /* Disable CANTX Output Pin */
-#define                      nDTO  0x0       
 #define                       DIL  0x8        /* Disable Internal Loop */
-#define                      nDIL  0x0       
 #define                       MAA  0x10       /* Mode Auto-Acknowledge */
-#define                      nMAA  0x0       
 #define                       MRB  0x20       /* Mode Read Back */
-#define                      nMRB  0x0       
 #define                       CDE  0x8000     /* CAN Debug Mode Enable */
-#define                      nCDE  0x0       
 
 /* Bit masks for CAN0_CLOCK */
 
@@ -2749,111 +2371,69 @@
 
 #define                       SJW  0x300      /* Synchronization Jump Width */
 #define                       SAM  0x80       /* Sampling */
-#define                      nSAM  0x0       
 #define                     TSEG2  0x70       /* Time Segment 2 */
 #define                     TSEG1  0xf        /* Time Segment 1 */
 
 /* Bit masks for CAN0_INTR */
 
 #define                     CANRX  0x80       /* Serial Input From Transceiver */
-#define                    nCANRX  0x0       
 #define                     CANTX  0x40       /* Serial Output To Transceiver */
-#define                    nCANTX  0x0       
 #define                     SMACK  0x8        /* Sleep Mode Acknowledge */
-#define                    nSMACK  0x0       
 #define                      GIRQ  0x4        /* Global Interrupt Request Status */
-#define                     nGIRQ  0x0       
 #define                    MBTIRQ  0x2        /* Mailbox Transmit Interrupt Request */
-#define                   nMBTIRQ  0x0       
 #define                    MBRIRQ  0x1        /* Mailbox Receive Interrupt Request */
-#define                   nMBRIRQ  0x0       
 
 /* Bit masks for CAN0_GIM */
 
 #define                     EWTIM  0x1        /* Error Warning Transmit Interrupt Mask */
-#define                    nEWTIM  0x0       
 #define                     EWRIM  0x2        /* Error Warning Receive Interrupt Mask */
-#define                    nEWRIM  0x0       
 #define                      EPIM  0x4        /* Error Passive Interrupt Mask */
-#define                     nEPIM  0x0       
 #define                      BOIM  0x8        /* Bus Off Interrupt Mask */
-#define                     nBOIM  0x0       
 #define                      WUIM  0x10       /* Wakeup Interrupt Mask */
-#define                     nWUIM  0x0       
 #define                     UIAIM  0x20       /* Unimplemented Address Interrupt Mask */
-#define                    nUIAIM  0x0       
 #define                      AAIM  0x40       /* Abort Acknowledge Interrupt Mask */
-#define                     nAAIM  0x0       
 #define                     RMLIM  0x80       /* Receive Message Lost Interrupt Mask */
-#define                    nRMLIM  0x0       
 #define                     UCEIM  0x100      /* Universal Counter Exceeded Interrupt Mask */
-#define                    nUCEIM  0x0       
 #define                      ADIM  0x400      /* Access Denied Interrupt Mask */
-#define                     nADIM  0x0       
 
 /* Bit masks for CAN0_GIS */
 
 #define                     EWTIS  0x1        /* Error Warning Transmit Interrupt Status */
-#define                    nEWTIS  0x0       
 #define                     EWRIS  0x2        /* Error Warning Receive Interrupt Status */
-#define                    nEWRIS  0x0       
 #define                      EPIS  0x4        /* Error Passive Interrupt Status */
-#define                     nEPIS  0x0       
 #define                      BOIS  0x8        /* Bus Off Interrupt Status */
-#define                     nBOIS  0x0       
 #define                      WUIS  0x10       /* Wakeup Interrupt Status */
-#define                     nWUIS  0x0       
 #define                     UIAIS  0x20       /* Unimplemented Address Interrupt Status */
-#define                    nUIAIS  0x0       
 #define                      AAIS  0x40       /* Abort Acknowledge Interrupt Status */
-#define                     nAAIS  0x0       
 #define                     RMLIS  0x80       /* Receive Message Lost Interrupt Status */
-#define                    nRMLIS  0x0       
 #define                     UCEIS  0x100      /* Universal Counter Exceeded Interrupt Status */
-#define                    nUCEIS  0x0       
 #define                      ADIS  0x400      /* Access Denied Interrupt Status */
-#define                     nADIS  0x0       
 
 /* Bit masks for CAN0_GIF */
 
 #define                     EWTIF  0x1        /* Error Warning Transmit Interrupt Flag */
-#define                    nEWTIF  0x0       
 #define                     EWRIF  0x2        /* Error Warning Receive Interrupt Flag */
-#define                    nEWRIF  0x0       
 #define                      EPIF  0x4        /* Error Passive Interrupt Flag */
-#define                     nEPIF  0x0       
 #define                      BOIF  0x8        /* Bus Off Interrupt Flag */
-#define                     nBOIF  0x0       
 #define                      WUIF  0x10       /* Wakeup Interrupt Flag */
-#define                     nWUIF  0x0       
 #define                     UIAIF  0x20       /* Unimplemented Address Interrupt Flag */
-#define                    nUIAIF  0x0       
 #define                      AAIF  0x40       /* Abort Acknowledge Interrupt Flag */
-#define                     nAAIF  0x0       
 #define                     RMLIF  0x80       /* Receive Message Lost Interrupt Flag */
-#define                    nRMLIF  0x0       
 #define                     UCEIF  0x100      /* Universal Counter Exceeded Interrupt Flag */
-#define                    nUCEIF  0x0       
 #define                      ADIF  0x400      /* Access Denied Interrupt Flag */
-#define                     nADIF  0x0       
 
 /* Bit masks for CAN0_MBTD */
 
 #define                       TDR  0x80       /* Temporary Disable Request */
-#define                      nTDR  0x0       
 #define                       TDA  0x40       /* Temporary Disable Acknowledge */
-#define                      nTDA  0x0       
 #define                     TDPTR  0x1f       /* Temporary Disable Pointer */
 
 /* Bit masks for CAN0_UCCNF */
 
 #define                     UCCNF  0xf        /* Universal Counter Configuration */
 #define                      UCRC  0x20       /* Universal Counter Reload/Clear */
-#define                     nUCRC  0x0       
 #define                      UCCT  0x40       /* Universal Counter CAN Trigger */
-#define                     nUCCT  0x0       
 #define                       UCE  0x80       /* Universal Counter Enable */
-#define                      nUCE  0x0       
 
 /* Bit masks for CAN0_UCCNT */
 
@@ -2871,17 +2451,11 @@
 /* Bit masks for CAN0_ESR */
 
 #define                       FER  0x80       /* Form Error */
-#define                      nFER  0x0       
 #define                       BEF  0x40       /* Bit Error Flag */
-#define                      nBEF  0x0       
 #define                       SA0  0x20       /* Stuck At Dominant */
-#define                      nSA0  0x0       
 #define                      CRCE  0x10       /* CRC Error */
-#define                     nCRCE  0x0       
 #define                       SER  0x8        /* Stuff Bit Error */
-#define                      nSER  0x0       
 #define                      ACKE  0x4        /* Acknowledge Error */
-#define                     nACKE  0x0       
 
 /* Bit masks for CAN0_EWR */
 
@@ -2891,11 +2465,8 @@
 /* Bit masks for CAN0_AMxx_H */
 
 #define                       FDF  0x8000     /* Filter On Data Field */
-#define                      nFDF  0x0       
 #define                       FMD  0x4000     /* Full Mask Data */
-#define                      nFMD  0x0       
 #define                     AMIDE  0x2000     /* Acceptance Mask Identifier Extension */
-#define                    nAMIDE  0x0       
 #define                    BASEID  0x1ffc     /* Base Identifier */
 #define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
 
@@ -2907,11 +2478,8 @@
 /* Bit masks for CAN0_MBxx_ID1 */
 
 #define                       AME  0x8000     /* Acceptance Mask Enable */
-#define                      nAME  0x0       
 #define                       RTR  0x4000     /* Remote Transmission Request */
-#define                      nRTR  0x0       
 #define                       IDE  0x2000     /* Identifier Extension */
-#define                      nIDE  0x0       
 #define                    BASEID  0x1ffc     /* Base Identifier */
 #define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
 
@@ -2951,980 +2519,546 @@
 /* Bit masks for CAN0_MC1 */
 
 #define                       MC0  0x1        /* Mailbox 0 Enable */
-#define                      nMC0  0x0       
 #define                       MC1  0x2        /* Mailbox 1 Enable */
-#define                      nMC1  0x0       
 #define                       MC2  0x4        /* Mailbox 2 Enable */
-#define                      nMC2  0x0       
 #define                       MC3  0x8        /* Mailbox 3 Enable */
-#define                      nMC3  0x0       
 #define                       MC4  0x10       /* Mailbox 4 Enable */
-#define                      nMC4  0x0       
 #define                       MC5  0x20       /* Mailbox 5 Enable */
-#define                      nMC5  0x0       
 #define                       MC6  0x40       /* Mailbox 6 Enable */
-#define                      nMC6  0x0       
 #define                       MC7  0x80       /* Mailbox 7 Enable */
-#define                      nMC7  0x0       
 #define                       MC8  0x100      /* Mailbox 8 Enable */
-#define                      nMC8  0x0       
 #define                       MC9  0x200      /* Mailbox 9 Enable */
-#define                      nMC9  0x0       
 #define                      MC10  0x400      /* Mailbox 10 Enable */
-#define                     nMC10  0x0       
 #define                      MC11  0x800      /* Mailbox 11 Enable */
-#define                     nMC11  0x0       
 #define                      MC12  0x1000     /* Mailbox 12 Enable */
-#define                     nMC12  0x0       
 #define                      MC13  0x2000     /* Mailbox 13 Enable */
-#define                     nMC13  0x0       
 #define                      MC14  0x4000     /* Mailbox 14 Enable */
-#define                     nMC14  0x0       
 #define                      MC15  0x8000     /* Mailbox 15 Enable */
-#define                     nMC15  0x0       
 
 /* Bit masks for CAN0_MC2 */
 
 #define                      MC16  0x1        /* Mailbox 16 Enable */
-#define                     nMC16  0x0       
 #define                      MC17  0x2        /* Mailbox 17 Enable */
-#define                     nMC17  0x0       
 #define                      MC18  0x4        /* Mailbox 18 Enable */
-#define                     nMC18  0x0       
 #define                      MC19  0x8        /* Mailbox 19 Enable */
-#define                     nMC19  0x0       
 #define                      MC20  0x10       /* Mailbox 20 Enable */
-#define                     nMC20  0x0       
 #define                      MC21  0x20       /* Mailbox 21 Enable */
-#define                     nMC21  0x0       
 #define                      MC22  0x40       /* Mailbox 22 Enable */
-#define                     nMC22  0x0       
 #define                      MC23  0x80       /* Mailbox 23 Enable */
-#define                     nMC23  0x0       
 #define                      MC24  0x100      /* Mailbox 24 Enable */
-#define                     nMC24  0x0       
 #define                      MC25  0x200      /* Mailbox 25 Enable */
-#define                     nMC25  0x0       
 #define                      MC26  0x400      /* Mailbox 26 Enable */
-#define                     nMC26  0x0       
 #define                      MC27  0x800      /* Mailbox 27 Enable */
-#define                     nMC27  0x0       
 #define                      MC28  0x1000     /* Mailbox 28 Enable */
-#define                     nMC28  0x0       
 #define                      MC29  0x2000     /* Mailbox 29 Enable */
-#define                     nMC29  0x0       
 #define                      MC30  0x4000     /* Mailbox 30 Enable */
-#define                     nMC30  0x0       
 #define                      MC31  0x8000     /* Mailbox 31 Enable */
-#define                     nMC31  0x0       
 
 /* Bit masks for CAN0_MD1 */
 
 #define                       MD0  0x1        /* Mailbox 0 Receive Enable */
-#define                      nMD0  0x0       
 #define                       MD1  0x2        /* Mailbox 1 Receive Enable */
-#define                      nMD1  0x0       
 #define                       MD2  0x4        /* Mailbox 2 Receive Enable */
-#define                      nMD2  0x0       
 #define                       MD3  0x8        /* Mailbox 3 Receive Enable */
-#define                      nMD3  0x0       
 #define                       MD4  0x10       /* Mailbox 4 Receive Enable */
-#define                      nMD4  0x0       
 #define                       MD5  0x20       /* Mailbox 5 Receive Enable */
-#define                      nMD5  0x0       
 #define                       MD6  0x40       /* Mailbox 6 Receive Enable */
-#define                      nMD6  0x0       
 #define                       MD7  0x80       /* Mailbox 7 Receive Enable */
-#define                      nMD7  0x0       
 #define                       MD8  0x100      /* Mailbox 8 Receive Enable */
-#define                      nMD8  0x0       
 #define                       MD9  0x200      /* Mailbox 9 Receive Enable */
-#define                      nMD9  0x0       
 #define                      MD10  0x400      /* Mailbox 10 Receive Enable */
-#define                     nMD10  0x0       
 #define                      MD11  0x800      /* Mailbox 11 Receive Enable */
-#define                     nMD11  0x0       
 #define                      MD12  0x1000     /* Mailbox 12 Receive Enable */
-#define                     nMD12  0x0       
 #define                      MD13  0x2000     /* Mailbox 13 Receive Enable */
-#define                     nMD13  0x0       
 #define                      MD14  0x4000     /* Mailbox 14 Receive Enable */
-#define                     nMD14  0x0       
 #define                      MD15  0x8000     /* Mailbox 15 Receive Enable */
-#define                     nMD15  0x0       
 
 /* Bit masks for CAN0_MD2 */
 
 #define                      MD16  0x1        /* Mailbox 16 Receive Enable */
-#define                     nMD16  0x0       
 #define                      MD17  0x2        /* Mailbox 17 Receive Enable */
-#define                     nMD17  0x0       
 #define                      MD18  0x4        /* Mailbox 18 Receive Enable */
-#define                     nMD18  0x0       
 #define                      MD19  0x8        /* Mailbox 19 Receive Enable */
-#define                     nMD19  0x0       
 #define                      MD20  0x10       /* Mailbox 20 Receive Enable */
-#define                     nMD20  0x0       
 #define                      MD21  0x20       /* Mailbox 21 Receive Enable */
-#define                     nMD21  0x0       
 #define                      MD22  0x40       /* Mailbox 22 Receive Enable */
-#define                     nMD22  0x0       
 #define                      MD23  0x80       /* Mailbox 23 Receive Enable */
-#define                     nMD23  0x0       
 #define                      MD24  0x100      /* Mailbox 24 Receive Enable */
-#define                     nMD24  0x0       
 #define                      MD25  0x200      /* Mailbox 25 Receive Enable */
-#define                     nMD25  0x0       
 #define                      MD26  0x400      /* Mailbox 26 Receive Enable */
-#define                     nMD26  0x0       
 #define                      MD27  0x800      /* Mailbox 27 Receive Enable */
-#define                     nMD27  0x0       
 #define                      MD28  0x1000     /* Mailbox 28 Receive Enable */
-#define                     nMD28  0x0       
 #define                      MD29  0x2000     /* Mailbox 29 Receive Enable */
-#define                     nMD29  0x0       
 #define                      MD30  0x4000     /* Mailbox 30 Receive Enable */
-#define                     nMD30  0x0       
 #define                      MD31  0x8000     /* Mailbox 31 Receive Enable */
-#define                     nMD31  0x0       
 
 /* Bit masks for CAN0_RMP1 */
 
 #define                      RMP0  0x1        /* Mailbox 0 Receive Message Pending */
-#define                     nRMP0  0x0       
 #define                      RMP1  0x2        /* Mailbox 1 Receive Message Pending */
-#define                     nRMP1  0x0       
 #define                      RMP2  0x4        /* Mailbox 2 Receive Message Pending */
-#define                     nRMP2  0x0       
 #define                      RMP3  0x8        /* Mailbox 3 Receive Message Pending */
-#define                     nRMP3  0x0       
 #define                      RMP4  0x10       /* Mailbox 4 Receive Message Pending */
-#define                     nRMP4  0x0       
 #define                      RMP5  0x20       /* Mailbox 5 Receive Message Pending */
-#define                     nRMP5  0x0       
 #define                      RMP6  0x40       /* Mailbox 6 Receive Message Pending */
-#define                     nRMP6  0x0       
 #define                      RMP7  0x80       /* Mailbox 7 Receive Message Pending */
-#define                     nRMP7  0x0       
 #define                      RMP8  0x100      /* Mailbox 8 Receive Message Pending */
-#define                     nRMP8  0x0       
 #define                      RMP9  0x200      /* Mailbox 9 Receive Message Pending */
-#define                     nRMP9  0x0       
 #define                     RMP10  0x400      /* Mailbox 10 Receive Message Pending */
-#define                    nRMP10  0x0       
 #define                     RMP11  0x800      /* Mailbox 11 Receive Message Pending */
-#define                    nRMP11  0x0       
 #define                     RMP12  0x1000     /* Mailbox 12 Receive Message Pending */
-#define                    nRMP12  0x0       
 #define                     RMP13  0x2000     /* Mailbox 13 Receive Message Pending */
-#define                    nRMP13  0x0       
 #define                     RMP14  0x4000     /* Mailbox 14 Receive Message Pending */
-#define                    nRMP14  0x0       
 #define                     RMP15  0x8000     /* Mailbox 15 Receive Message Pending */
-#define                    nRMP15  0x0       
 
 /* Bit masks for CAN0_RMP2 */
 
 #define                     RMP16  0x1        /* Mailbox 16 Receive Message Pending */
-#define                    nRMP16  0x0       
 #define                     RMP17  0x2        /* Mailbox 17 Receive Message Pending */
-#define                    nRMP17  0x0       
 #define                     RMP18  0x4        /* Mailbox 18 Receive Message Pending */
-#define                    nRMP18  0x0       
 #define                     RMP19  0x8        /* Mailbox 19 Receive Message Pending */
-#define                    nRMP19  0x0       
 #define                     RMP20  0x10       /* Mailbox 20 Receive Message Pending */
-#define                    nRMP20  0x0       
 #define                     RMP21  0x20       /* Mailbox 21 Receive Message Pending */
-#define                    nRMP21  0x0       
 #define                     RMP22  0x40       /* Mailbox 22 Receive Message Pending */
-#define                    nRMP22  0x0       
 #define                     RMP23  0x80       /* Mailbox 23 Receive Message Pending */
-#define                    nRMP23  0x0       
 #define                     RMP24  0x100      /* Mailbox 24 Receive Message Pending */
-#define                    nRMP24  0x0       
 #define                     RMP25  0x200      /* Mailbox 25 Receive Message Pending */
-#define                    nRMP25  0x0       
 #define                     RMP26  0x400      /* Mailbox 26 Receive Message Pending */
-#define                    nRMP26  0x0       
 #define                     RMP27  0x800      /* Mailbox 27 Receive Message Pending */
-#define                    nRMP27  0x0       
 #define                     RMP28  0x1000     /* Mailbox 28 Receive Message Pending */
-#define                    nRMP28  0x0       
 #define                     RMP29  0x2000     /* Mailbox 29 Receive Message Pending */
-#define                    nRMP29  0x0       
 #define                     RMP30  0x4000     /* Mailbox 30 Receive Message Pending */
-#define                    nRMP30  0x0       
 #define                     RMP31  0x8000     /* Mailbox 31 Receive Message Pending */
-#define                    nRMP31  0x0       
 
 /* Bit masks for CAN0_RML1 */
 
 #define                      RML0  0x1        /* Mailbox 0 Receive Message Lost */
-#define                     nRML0  0x0       
 #define                      RML1  0x2        /* Mailbox 1 Receive Message Lost */
-#define                     nRML1  0x0       
 #define                      RML2  0x4        /* Mailbox 2 Receive Message Lost */
-#define                     nRML2  0x0       
 #define                      RML3  0x8        /* Mailbox 3 Receive Message Lost */
-#define                     nRML3  0x0       
 #define                      RML4  0x10       /* Mailbox 4 Receive Message Lost */
-#define                     nRML4  0x0       
 #define                      RML5  0x20       /* Mailbox 5 Receive Message Lost */
-#define                     nRML5  0x0       
 #define                      RML6  0x40       /* Mailbox 6 Receive Message Lost */
-#define                     nRML6  0x0       
 #define                      RML7  0x80       /* Mailbox 7 Receive Message Lost */
-#define                     nRML7  0x0       
 #define                      RML8  0x100      /* Mailbox 8 Receive Message Lost */
-#define                     nRML8  0x0       
 #define                      RML9  0x200      /* Mailbox 9 Receive Message Lost */
-#define                     nRML9  0x0       
 #define                     RML10  0x400      /* Mailbox 10 Receive Message Lost */
-#define                    nRML10  0x0       
 #define                     RML11  0x800      /* Mailbox 11 Receive Message Lost */
-#define                    nRML11  0x0       
 #define                     RML12  0x1000     /* Mailbox 12 Receive Message Lost */
-#define                    nRML12  0x0       
 #define                     RML13  0x2000     /* Mailbox 13 Receive Message Lost */
-#define                    nRML13  0x0       
 #define                     RML14  0x4000     /* Mailbox 14 Receive Message Lost */
-#define                    nRML14  0x0       
 #define                     RML15  0x8000     /* Mailbox 15 Receive Message Lost */
-#define                    nRML15  0x0       
 
 /* Bit masks for CAN0_RML2 */
 
 #define                     RML16  0x1        /* Mailbox 16 Receive Message Lost */
-#define                    nRML16  0x0       
 #define                     RML17  0x2        /* Mailbox 17 Receive Message Lost */
-#define                    nRML17  0x0       
 #define                     RML18  0x4        /* Mailbox 18 Receive Message Lost */
-#define                    nRML18  0x0       
 #define                     RML19  0x8        /* Mailbox 19 Receive Message Lost */
-#define                    nRML19  0x0       
 #define                     RML20  0x10       /* Mailbox 20 Receive Message Lost */
-#define                    nRML20  0x0       
 #define                     RML21  0x20       /* Mailbox 21 Receive Message Lost */
-#define                    nRML21  0x0       
 #define                     RML22  0x40       /* Mailbox 22 Receive Message Lost */
-#define                    nRML22  0x0       
 #define                     RML23  0x80       /* Mailbox 23 Receive Message Lost */
-#define                    nRML23  0x0       
 #define                     RML24  0x100      /* Mailbox 24 Receive Message Lost */
-#define                    nRML24  0x0       
 #define                     RML25  0x200      /* Mailbox 25 Receive Message Lost */
-#define                    nRML25  0x0       
 #define                     RML26  0x400      /* Mailbox 26 Receive Message Lost */
-#define                    nRML26  0x0       
 #define                     RML27  0x800      /* Mailbox 27 Receive Message Lost */
-#define                    nRML27  0x0       
 #define                     RML28  0x1000     /* Mailbox 28 Receive Message Lost */
-#define                    nRML28  0x0       
 #define                     RML29  0x2000     /* Mailbox 29 Receive Message Lost */
-#define                    nRML29  0x0       
 #define                     RML30  0x4000     /* Mailbox 30 Receive Message Lost */
-#define                    nRML30  0x0       
 #define                     RML31  0x8000     /* Mailbox 31 Receive Message Lost */
-#define                    nRML31  0x0       
 
 /* Bit masks for CAN0_OPSS1 */
 
 #define                     OPSS0  0x1        /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS0  0x0       
 #define                     OPSS1  0x2        /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS1  0x0       
 #define                     OPSS2  0x4        /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS2  0x0       
 #define                     OPSS3  0x8        /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS3  0x0       
 #define                     OPSS4  0x10       /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS4  0x0       
 #define                     OPSS5  0x20       /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS5  0x0       
 #define                     OPSS6  0x40       /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS6  0x0       
 #define                     OPSS7  0x80       /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS7  0x0       
 #define                     OPSS8  0x100      /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS8  0x0       
 #define                     OPSS9  0x200      /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS9  0x0       
 #define                    OPSS10  0x400      /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS10  0x0       
 #define                    OPSS11  0x800      /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS11  0x0       
 #define                    OPSS12  0x1000     /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS12  0x0       
 #define                    OPSS13  0x2000     /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS13  0x0       
 #define                    OPSS14  0x4000     /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS14  0x0       
 #define                    OPSS15  0x8000     /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS15  0x0       
 
 /* Bit masks for CAN0_OPSS2 */
 
 #define                    OPSS16  0x1        /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS16  0x0       
 #define                    OPSS17  0x2        /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS17  0x0       
 #define                    OPSS18  0x4        /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS18  0x0       
 #define                    OPSS19  0x8        /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS19  0x0       
 #define                    OPSS20  0x10       /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS20  0x0       
 #define                    OPSS21  0x20       /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS21  0x0       
 #define                    OPSS22  0x40       /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS22  0x0       
 #define                    OPSS23  0x80       /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS23  0x0       
 #define                    OPSS24  0x100      /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS24  0x0       
 #define                    OPSS25  0x200      /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS25  0x0       
 #define                    OPSS26  0x400      /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS26  0x0       
 #define                    OPSS27  0x800      /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS27  0x0       
 #define                    OPSS28  0x1000     /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS28  0x0       
 #define                    OPSS29  0x2000     /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS29  0x0       
 #define                    OPSS30  0x4000     /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS30  0x0       
 #define                    OPSS31  0x8000     /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS31  0x0       
 
 /* Bit masks for CAN0_TRS1 */
 
 #define                      TRS0  0x1        /* Mailbox 0 Transmit Request Set */
-#define                     nTRS0  0x0       
 #define                      TRS1  0x2        /* Mailbox 1 Transmit Request Set */
-#define                     nTRS1  0x0       
 #define                      TRS2  0x4        /* Mailbox 2 Transmit Request Set */
-#define                     nTRS2  0x0       
 #define                      TRS3  0x8        /* Mailbox 3 Transmit Request Set */
-#define                     nTRS3  0x0       
 #define                      TRS4  0x10       /* Mailbox 4 Transmit Request Set */
-#define                     nTRS4  0x0       
 #define                      TRS5  0x20       /* Mailbox 5 Transmit Request Set */
-#define                     nTRS5  0x0       
 #define                      TRS6  0x40       /* Mailbox 6 Transmit Request Set */
-#define                     nTRS6  0x0       
 #define                      TRS7  0x80       /* Mailbox 7 Transmit Request Set */
-#define                     nTRS7  0x0       
 #define                      TRS8  0x100      /* Mailbox 8 Transmit Request Set */
-#define                     nTRS8  0x0       
 #define                      TRS9  0x200      /* Mailbox 9 Transmit Request Set */
-#define                     nTRS9  0x0       
 #define                     TRS10  0x400      /* Mailbox 10 Transmit Request Set */
-#define                    nTRS10  0x0       
 #define                     TRS11  0x800      /* Mailbox 11 Transmit Request Set */
-#define                    nTRS11  0x0       
 #define                     TRS12  0x1000     /* Mailbox 12 Transmit Request Set */
-#define                    nTRS12  0x0       
 #define                     TRS13  0x2000     /* Mailbox 13 Transmit Request Set */
-#define                    nTRS13  0x0       
 #define                     TRS14  0x4000     /* Mailbox 14 Transmit Request Set */
-#define                    nTRS14  0x0       
 #define                     TRS15  0x8000     /* Mailbox 15 Transmit Request Set */
-#define                    nTRS15  0x0       
 
 /* Bit masks for CAN0_TRS2 */
 
 #define                     TRS16  0x1        /* Mailbox 16 Transmit Request Set */
-#define                    nTRS16  0x0       
 #define                     TRS17  0x2        /* Mailbox 17 Transmit Request Set */
-#define                    nTRS17  0x0       
 #define                     TRS18  0x4        /* Mailbox 18 Transmit Request Set */
-#define                    nTRS18  0x0       
 #define                     TRS19  0x8        /* Mailbox 19 Transmit Request Set */
-#define                    nTRS19  0x0       
 #define                     TRS20  0x10       /* Mailbox 20 Transmit Request Set */
-#define                    nTRS20  0x0       
 #define                     TRS21  0x20       /* Mailbox 21 Transmit Request Set */
-#define                    nTRS21  0x0       
 #define                     TRS22  0x40       /* Mailbox 22 Transmit Request Set */
-#define                    nTRS22  0x0       
 #define                     TRS23  0x80       /* Mailbox 23 Transmit Request Set */
-#define                    nTRS23  0x0       
 #define                     TRS24  0x100      /* Mailbox 24 Transmit Request Set */
-#define                    nTRS24  0x0       
 #define                     TRS25  0x200      /* Mailbox 25 Transmit Request Set */
-#define                    nTRS25  0x0       
 #define                     TRS26  0x400      /* Mailbox 26 Transmit Request Set */
-#define                    nTRS26  0x0       
 #define                     TRS27  0x800      /* Mailbox 27 Transmit Request Set */
-#define                    nTRS27  0x0       
 #define                     TRS28  0x1000     /* Mailbox 28 Transmit Request Set */
-#define                    nTRS28  0x0       
 #define                     TRS29  0x2000     /* Mailbox 29 Transmit Request Set */
-#define                    nTRS29  0x0       
 #define                     TRS30  0x4000     /* Mailbox 30 Transmit Request Set */
-#define                    nTRS30  0x0       
 #define                     TRS31  0x8000     /* Mailbox 31 Transmit Request Set */
-#define                    nTRS31  0x0       
 
 /* Bit masks for CAN0_TRR1 */
 
 #define                      TRR0  0x1        /* Mailbox 0 Transmit Request Reset */
-#define                     nTRR0  0x0       
 #define                      TRR1  0x2        /* Mailbox 1 Transmit Request Reset */
-#define                     nTRR1  0x0       
 #define                      TRR2  0x4        /* Mailbox 2 Transmit Request Reset */
-#define                     nTRR2  0x0       
 #define                      TRR3  0x8        /* Mailbox 3 Transmit Request Reset */
-#define                     nTRR3  0x0       
 #define                      TRR4  0x10       /* Mailbox 4 Transmit Request Reset */
-#define                     nTRR4  0x0       
 #define                      TRR5  0x20       /* Mailbox 5 Transmit Request Reset */
-#define                     nTRR5  0x0       
 #define                      TRR6  0x40       /* Mailbox 6 Transmit Request Reset */
-#define                     nTRR6  0x0       
 #define                      TRR7  0x80       /* Mailbox 7 Transmit Request Reset */
-#define                     nTRR7  0x0       
 #define                      TRR8  0x100      /* Mailbox 8 Transmit Request Reset */
-#define                     nTRR8  0x0       
 #define                      TRR9  0x200      /* Mailbox 9 Transmit Request Reset */
-#define                     nTRR9  0x0       
 #define                     TRR10  0x400      /* Mailbox 10 Transmit Request Reset */
-#define                    nTRR10  0x0       
 #define                     TRR11  0x800      /* Mailbox 11 Transmit Request Reset */
-#define                    nTRR11  0x0       
 #define                     TRR12  0x1000     /* Mailbox 12 Transmit Request Reset */
-#define                    nTRR12  0x0       
 #define                     TRR13  0x2000     /* Mailbox 13 Transmit Request Reset */
-#define                    nTRR13  0x0       
 #define                     TRR14  0x4000     /* Mailbox 14 Transmit Request Reset */
-#define                    nTRR14  0x0       
 #define                     TRR15  0x8000     /* Mailbox 15 Transmit Request Reset */
-#define                    nTRR15  0x0       
 
 /* Bit masks for CAN0_TRR2 */
 
 #define                     TRR16  0x1        /* Mailbox 16 Transmit Request Reset */
-#define                    nTRR16  0x0       
 #define                     TRR17  0x2        /* Mailbox 17 Transmit Request Reset */
-#define                    nTRR17  0x0       
 #define                     TRR18  0x4        /* Mailbox 18 Transmit Request Reset */
-#define                    nTRR18  0x0       
 #define                     TRR19  0x8        /* Mailbox 19 Transmit Request Reset */
-#define                    nTRR19  0x0       
 #define                     TRR20  0x10       /* Mailbox 20 Transmit Request Reset */
-#define                    nTRR20  0x0       
 #define                     TRR21  0x20       /* Mailbox 21 Transmit Request Reset */
-#define                    nTRR21  0x0       
 #define                     TRR22  0x40       /* Mailbox 22 Transmit Request Reset */
-#define                    nTRR22  0x0       
 #define                     TRR23  0x80       /* Mailbox 23 Transmit Request Reset */
-#define                    nTRR23  0x0       
 #define                     TRR24  0x100      /* Mailbox 24 Transmit Request Reset */
-#define                    nTRR24  0x0       
 #define                     TRR25  0x200      /* Mailbox 25 Transmit Request Reset */
-#define                    nTRR25  0x0       
 #define                     TRR26  0x400      /* Mailbox 26 Transmit Request Reset */
-#define                    nTRR26  0x0       
 #define                     TRR27  0x800      /* Mailbox 27 Transmit Request Reset */
-#define                    nTRR27  0x0       
 #define                     TRR28  0x1000     /* Mailbox 28 Transmit Request Reset */
-#define                    nTRR28  0x0       
 #define                     TRR29  0x2000     /* Mailbox 29 Transmit Request Reset */
-#define                    nTRR29  0x0       
 #define                     TRR30  0x4000     /* Mailbox 30 Transmit Request Reset */
-#define                    nTRR30  0x0       
 #define                     TRR31  0x8000     /* Mailbox 31 Transmit Request Reset */
-#define                    nTRR31  0x0       
 
 /* Bit masks for CAN0_AA1 */
 
 #define                       AA0  0x1        /* Mailbox 0 Abort Acknowledge */
-#define                      nAA0  0x0       
 #define                       AA1  0x2        /* Mailbox 1 Abort Acknowledge */
-#define                      nAA1  0x0       
 #define                       AA2  0x4        /* Mailbox 2 Abort Acknowledge */
-#define                      nAA2  0x0       
 #define                       AA3  0x8        /* Mailbox 3 Abort Acknowledge */
-#define                      nAA3  0x0       
 #define                       AA4  0x10       /* Mailbox 4 Abort Acknowledge */
-#define                      nAA4  0x0       
 #define                       AA5  0x20       /* Mailbox 5 Abort Acknowledge */
-#define                      nAA5  0x0       
 #define                       AA6  0x40       /* Mailbox 6 Abort Acknowledge */
-#define                      nAA6  0x0       
 #define                       AA7  0x80       /* Mailbox 7 Abort Acknowledge */
-#define                      nAA7  0x0       
 #define                       AA8  0x100      /* Mailbox 8 Abort Acknowledge */
-#define                      nAA8  0x0       
 #define                       AA9  0x200      /* Mailbox 9 Abort Acknowledge */
-#define                      nAA9  0x0       
 #define                      AA10  0x400      /* Mailbox 10 Abort Acknowledge */
-#define                     nAA10  0x0       
 #define                      AA11  0x800      /* Mailbox 11 Abort Acknowledge */
-#define                     nAA11  0x0       
 #define                      AA12  0x1000     /* Mailbox 12 Abort Acknowledge */
-#define                     nAA12  0x0       
 #define                      AA13  0x2000     /* Mailbox 13 Abort Acknowledge */
-#define                     nAA13  0x0       
 #define                      AA14  0x4000     /* Mailbox 14 Abort Acknowledge */
-#define                     nAA14  0x0       
 #define                      AA15  0x8000     /* Mailbox 15 Abort Acknowledge */
-#define                     nAA15  0x0       
 
 /* Bit masks for CAN0_AA2 */
 
 #define                      AA16  0x1        /* Mailbox 16 Abort Acknowledge */
-#define                     nAA16  0x0       
 #define                      AA17  0x2        /* Mailbox 17 Abort Acknowledge */
-#define                     nAA17  0x0       
 #define                      AA18  0x4        /* Mailbox 18 Abort Acknowledge */
-#define                     nAA18  0x0       
 #define                      AA19  0x8        /* Mailbox 19 Abort Acknowledge */
-#define                     nAA19  0x0       
 #define                      AA20  0x10       /* Mailbox 20 Abort Acknowledge */
-#define                     nAA20  0x0       
 #define                      AA21  0x20       /* Mailbox 21 Abort Acknowledge */
-#define                     nAA21  0x0       
 #define                      AA22  0x40       /* Mailbox 22 Abort Acknowledge */
-#define                     nAA22  0x0       
 #define                      AA23  0x80       /* Mailbox 23 Abort Acknowledge */
-#define                     nAA23  0x0       
 #define                      AA24  0x100      /* Mailbox 24 Abort Acknowledge */
-#define                     nAA24  0x0       
 #define                      AA25  0x200      /* Mailbox 25 Abort Acknowledge */
-#define                     nAA25  0x0       
 #define                      AA26  0x400      /* Mailbox 26 Abort Acknowledge */
-#define                     nAA26  0x0       
 #define                      AA27  0x800      /* Mailbox 27 Abort Acknowledge */
-#define                     nAA27  0x0       
 #define                      AA28  0x1000     /* Mailbox 28 Abort Acknowledge */
-#define                     nAA28  0x0       
 #define                      AA29  0x2000     /* Mailbox 29 Abort Acknowledge */
-#define                     nAA29  0x0       
 #define                      AA30  0x4000     /* Mailbox 30 Abort Acknowledge */
-#define                     nAA30  0x0       
 #define                      AA31  0x8000     /* Mailbox 31 Abort Acknowledge */
-#define                     nAA31  0x0       
 
 /* Bit masks for CAN0_TA1 */
 
 #define                       TA0  0x1        /* Mailbox 0 Transmit Acknowledge */
-#define                      nTA0  0x0       
 #define                       TA1  0x2        /* Mailbox 1 Transmit Acknowledge */
-#define                      nTA1  0x0       
 #define                       TA2  0x4        /* Mailbox 2 Transmit Acknowledge */
-#define                      nTA2  0x0       
 #define                       TA3  0x8        /* Mailbox 3 Transmit Acknowledge */
-#define                      nTA3  0x0       
 #define                       TA4  0x10       /* Mailbox 4 Transmit Acknowledge */
-#define                      nTA4  0x0       
 #define                       TA5  0x20       /* Mailbox 5 Transmit Acknowledge */
-#define                      nTA5  0x0       
 #define                       TA6  0x40       /* Mailbox 6 Transmit Acknowledge */
-#define                      nTA6  0x0       
 #define                       TA7  0x80       /* Mailbox 7 Transmit Acknowledge */
-#define                      nTA7  0x0       
 #define                       TA8  0x100      /* Mailbox 8 Transmit Acknowledge */
-#define                      nTA8  0x0       
 #define                       TA9  0x200      /* Mailbox 9 Transmit Acknowledge */
-#define                      nTA9  0x0       
 #define                      TA10  0x400      /* Mailbox 10 Transmit Acknowledge */
-#define                     nTA10  0x0       
 #define                      TA11  0x800      /* Mailbox 11 Transmit Acknowledge */
-#define                     nTA11  0x0       
 #define                      TA12  0x1000     /* Mailbox 12 Transmit Acknowledge */
-#define                     nTA12  0x0       
 #define                      TA13  0x2000     /* Mailbox 13 Transmit Acknowledge */
-#define                     nTA13  0x0       
 #define                      TA14  0x4000     /* Mailbox 14 Transmit Acknowledge */
-#define                     nTA14  0x0       
 #define                      TA15  0x8000     /* Mailbox 15 Transmit Acknowledge */
-#define                     nTA15  0x0       
 
 /* Bit masks for CAN0_TA2 */
 
 #define                      TA16  0x1        /* Mailbox 16 Transmit Acknowledge */
-#define                     nTA16  0x0       
 #define                      TA17  0x2        /* Mailbox 17 Transmit Acknowledge */
-#define                     nTA17  0x0       
 #define                      TA18  0x4        /* Mailbox 18 Transmit Acknowledge */
-#define                     nTA18  0x0       
 #define                      TA19  0x8        /* Mailbox 19 Transmit Acknowledge */
-#define                     nTA19  0x0       
 #define                      TA20  0x10       /* Mailbox 20 Transmit Acknowledge */
-#define                     nTA20  0x0       
 #define                      TA21  0x20       /* Mailbox 21 Transmit Acknowledge */
-#define                     nTA21  0x0       
 #define                      TA22  0x40       /* Mailbox 22 Transmit Acknowledge */
-#define                     nTA22  0x0       
 #define                      TA23  0x80       /* Mailbox 23 Transmit Acknowledge */
-#define                     nTA23  0x0       
 #define                      TA24  0x100      /* Mailbox 24 Transmit Acknowledge */
-#define                     nTA24  0x0       
 #define                      TA25  0x200      /* Mailbox 25 Transmit Acknowledge */
-#define                     nTA25  0x0       
 #define                      TA26  0x400      /* Mailbox 26 Transmit Acknowledge */
-#define                     nTA26  0x0       
 #define                      TA27  0x800      /* Mailbox 27 Transmit Acknowledge */
-#define                     nTA27  0x0       
 #define                      TA28  0x1000     /* Mailbox 28 Transmit Acknowledge */
-#define                     nTA28  0x0       
 #define                      TA29  0x2000     /* Mailbox 29 Transmit Acknowledge */
-#define                     nTA29  0x0       
 #define                      TA30  0x4000     /* Mailbox 30 Transmit Acknowledge */
-#define                     nTA30  0x0       
 #define                      TA31  0x8000     /* Mailbox 31 Transmit Acknowledge */
-#define                     nTA31  0x0       
 
 /* Bit masks for CAN0_RFH1 */
 
 #define                      RFH0  0x1        /* Mailbox 0 Remote Frame Handling Enable */
-#define                     nRFH0  0x0       
 #define                      RFH1  0x2        /* Mailbox 1 Remote Frame Handling Enable */
-#define                     nRFH1  0x0       
 #define                      RFH2  0x4        /* Mailbox 2 Remote Frame Handling Enable */
-#define                     nRFH2  0x0       
 #define                      RFH3  0x8        /* Mailbox 3 Remote Frame Handling Enable */
-#define                     nRFH3  0x0       
 #define                      RFH4  0x10       /* Mailbox 4 Remote Frame Handling Enable */
-#define                     nRFH4  0x0       
 #define                      RFH5  0x20       /* Mailbox 5 Remote Frame Handling Enable */
-#define                     nRFH5  0x0       
 #define                      RFH6  0x40       /* Mailbox 6 Remote Frame Handling Enable */
-#define                     nRFH6  0x0       
 #define                      RFH7  0x80       /* Mailbox 7 Remote Frame Handling Enable */
-#define                     nRFH7  0x0       
 #define                      RFH8  0x100      /* Mailbox 8 Remote Frame Handling Enable */
-#define                     nRFH8  0x0       
 #define                      RFH9  0x200      /* Mailbox 9 Remote Frame Handling Enable */
-#define                     nRFH9  0x0       
 #define                     RFH10  0x400      /* Mailbox 10 Remote Frame Handling Enable */
-#define                    nRFH10  0x0       
 #define                     RFH11  0x800      /* Mailbox 11 Remote Frame Handling Enable */
-#define                    nRFH11  0x0       
 #define                     RFH12  0x1000     /* Mailbox 12 Remote Frame Handling Enable */
-#define                    nRFH12  0x0       
 #define                     RFH13  0x2000     /* Mailbox 13 Remote Frame Handling Enable */
-#define                    nRFH13  0x0       
 #define                     RFH14  0x4000     /* Mailbox 14 Remote Frame Handling Enable */
-#define                    nRFH14  0x0       
 #define                     RFH15  0x8000     /* Mailbox 15 Remote Frame Handling Enable */
-#define                    nRFH15  0x0       
 
 /* Bit masks for CAN0_RFH2 */
 
 #define                     RFH16  0x1        /* Mailbox 16 Remote Frame Handling Enable */
-#define                    nRFH16  0x0       
 #define                     RFH17  0x2        /* Mailbox 17 Remote Frame Handling Enable */
-#define                    nRFH17  0x0       
 #define                     RFH18  0x4        /* Mailbox 18 Remote Frame Handling Enable */
-#define                    nRFH18  0x0       
 #define                     RFH19  0x8        /* Mailbox 19 Remote Frame Handling Enable */
-#define                    nRFH19  0x0       
 #define                     RFH20  0x10       /* Mailbox 20 Remote Frame Handling Enable */
-#define                    nRFH20  0x0       
 #define                     RFH21  0x20       /* Mailbox 21 Remote Frame Handling Enable */
-#define                    nRFH21  0x0       
 #define                     RFH22  0x40       /* Mailbox 22 Remote Frame Handling Enable */
-#define                    nRFH22  0x0       
 #define                     RFH23  0x80       /* Mailbox 23 Remote Frame Handling Enable */
-#define                    nRFH23  0x0       
 #define                     RFH24  0x100      /* Mailbox 24 Remote Frame Handling Enable */
-#define                    nRFH24  0x0       
 #define                     RFH25  0x200      /* Mailbox 25 Remote Frame Handling Enable */
-#define                    nRFH25  0x0       
 #define                     RFH26  0x400      /* Mailbox 26 Remote Frame Handling Enable */
-#define                    nRFH26  0x0       
 #define                     RFH27  0x800      /* Mailbox 27 Remote Frame Handling Enable */
-#define                    nRFH27  0x0       
 #define                     RFH28  0x1000     /* Mailbox 28 Remote Frame Handling Enable */
-#define                    nRFH28  0x0       
 #define                     RFH29  0x2000     /* Mailbox 29 Remote Frame Handling Enable */
-#define                    nRFH29  0x0       
 #define                     RFH30  0x4000     /* Mailbox 30 Remote Frame Handling Enable */
-#define                    nRFH30  0x0       
 #define                     RFH31  0x8000     /* Mailbox 31 Remote Frame Handling Enable */
-#define                    nRFH31  0x0       
 
 /* Bit masks for CAN0_MBIM1 */
 
 #define                     MBIM0  0x1        /* Mailbox 0 Mailbox Interrupt Mask */
-#define                    nMBIM0  0x0       
 #define                     MBIM1  0x2        /* Mailbox 1 Mailbox Interrupt Mask */
-#define                    nMBIM1  0x0       
 #define                     MBIM2  0x4        /* Mailbox 2 Mailbox Interrupt Mask */
-#define                    nMBIM2  0x0       
 #define                     MBIM3  0x8        /* Mailbox 3 Mailbox Interrupt Mask */
-#define                    nMBIM3  0x0       
 #define                     MBIM4  0x10       /* Mailbox 4 Mailbox Interrupt Mask */
-#define                    nMBIM4  0x0       
 #define                     MBIM5  0x20       /* Mailbox 5 Mailbox Interrupt Mask */
-#define                    nMBIM5  0x0       
 #define                     MBIM6  0x40       /* Mailbox 6 Mailbox Interrupt Mask */
-#define                    nMBIM6  0x0       
 #define                     MBIM7  0x80       /* Mailbox 7 Mailbox Interrupt Mask */
-#define                    nMBIM7  0x0       
 #define                     MBIM8  0x100      /* Mailbox 8 Mailbox Interrupt Mask */
-#define                    nMBIM8  0x0       
 #define                     MBIM9  0x200      /* Mailbox 9 Mailbox Interrupt Mask */
-#define                    nMBIM9  0x0       
 #define                    MBIM10  0x400      /* Mailbox 10 Mailbox Interrupt Mask */
-#define                   nMBIM10  0x0       
 #define                    MBIM11  0x800      /* Mailbox 11 Mailbox Interrupt Mask */
-#define                   nMBIM11  0x0       
 #define                    MBIM12  0x1000     /* Mailbox 12 Mailbox Interrupt Mask */
-#define                   nMBIM12  0x0       
 #define                    MBIM13  0x2000     /* Mailbox 13 Mailbox Interrupt Mask */
-#define                   nMBIM13  0x0       
 #define                    MBIM14  0x4000     /* Mailbox 14 Mailbox Interrupt Mask */
-#define                   nMBIM14  0x0       
 #define                    MBIM15  0x8000     /* Mailbox 15 Mailbox Interrupt Mask */
-#define                   nMBIM15  0x0       
 
 /* Bit masks for CAN0_MBIM2 */
 
 #define                    MBIM16  0x1        /* Mailbox 16 Mailbox Interrupt Mask */
-#define                   nMBIM16  0x0       
 #define                    MBIM17  0x2        /* Mailbox 17 Mailbox Interrupt Mask */
-#define                   nMBIM17  0x0       
 #define                    MBIM18  0x4        /* Mailbox 18 Mailbox Interrupt Mask */
-#define                   nMBIM18  0x0       
 #define                    MBIM19  0x8        /* Mailbox 19 Mailbox Interrupt Mask */
-#define                   nMBIM19  0x0       
 #define                    MBIM20  0x10       /* Mailbox 20 Mailbox Interrupt Mask */
-#define                   nMBIM20  0x0       
 #define                    MBIM21  0x20       /* Mailbox 21 Mailbox Interrupt Mask */
-#define                   nMBIM21  0x0       
 #define                    MBIM22  0x40       /* Mailbox 22 Mailbox Interrupt Mask */
-#define                   nMBIM22  0x0       
 #define                    MBIM23  0x80       /* Mailbox 23 Mailbox Interrupt Mask */
-#define                   nMBIM23  0x0       
 #define                    MBIM24  0x100      /* Mailbox 24 Mailbox Interrupt Mask */
-#define                   nMBIM24  0x0       
 #define                    MBIM25  0x200      /* Mailbox 25 Mailbox Interrupt Mask */
-#define                   nMBIM25  0x0       
 #define                    MBIM26  0x400      /* Mailbox 26 Mailbox Interrupt Mask */
-#define                   nMBIM26  0x0       
 #define                    MBIM27  0x800      /* Mailbox 27 Mailbox Interrupt Mask */
-#define                   nMBIM27  0x0       
 #define                    MBIM28  0x1000     /* Mailbox 28 Mailbox Interrupt Mask */
-#define                   nMBIM28  0x0       
 #define                    MBIM29  0x2000     /* Mailbox 29 Mailbox Interrupt Mask */
-#define                   nMBIM29  0x0       
 #define                    MBIM30  0x4000     /* Mailbox 30 Mailbox Interrupt Mask */
-#define                   nMBIM30  0x0       
 #define                    MBIM31  0x8000     /* Mailbox 31 Mailbox Interrupt Mask */
-#define                   nMBIM31  0x0       
 
 /* Bit masks for CAN0_MBTIF1 */
 
 #define                    MBTIF0  0x1        /* Mailbox 0 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF0  0x0       
 #define                    MBTIF1  0x2        /* Mailbox 1 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF1  0x0       
 #define                    MBTIF2  0x4        /* Mailbox 2 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF2  0x0       
 #define                    MBTIF3  0x8        /* Mailbox 3 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF3  0x0       
 #define                    MBTIF4  0x10       /* Mailbox 4 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF4  0x0       
 #define                    MBTIF5  0x20       /* Mailbox 5 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF5  0x0       
 #define                    MBTIF6  0x40       /* Mailbox 6 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF6  0x0       
 #define                    MBTIF7  0x80       /* Mailbox 7 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF7  0x0       
 #define                    MBTIF8  0x100      /* Mailbox 8 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF8  0x0       
 #define                    MBTIF9  0x200      /* Mailbox 9 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF9  0x0       
 #define                   MBTIF10  0x400      /* Mailbox 10 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF10  0x0       
 #define                   MBTIF11  0x800      /* Mailbox 11 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF11  0x0       
 #define                   MBTIF12  0x1000     /* Mailbox 12 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF12  0x0       
 #define                   MBTIF13  0x2000     /* Mailbox 13 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF13  0x0       
 #define                   MBTIF14  0x4000     /* Mailbox 14 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF14  0x0       
 #define                   MBTIF15  0x8000     /* Mailbox 15 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF15  0x0       
 
 /* Bit masks for CAN0_MBTIF2 */
 
 #define                   MBTIF16  0x1        /* Mailbox 16 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF16  0x0       
 #define                   MBTIF17  0x2        /* Mailbox 17 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF17  0x0       
 #define                   MBTIF18  0x4        /* Mailbox 18 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF18  0x0       
 #define                   MBTIF19  0x8        /* Mailbox 19 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF19  0x0       
 #define                   MBTIF20  0x10       /* Mailbox 20 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF20  0x0       
 #define                   MBTIF21  0x20       /* Mailbox 21 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF21  0x0       
 #define                   MBTIF22  0x40       /* Mailbox 22 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF22  0x0       
 #define                   MBTIF23  0x80       /* Mailbox 23 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF23  0x0       
 #define                   MBTIF24  0x100      /* Mailbox 24 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF24  0x0       
 #define                   MBTIF25  0x200      /* Mailbox 25 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF25  0x0       
 #define                   MBTIF26  0x400      /* Mailbox 26 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF26  0x0       
 #define                   MBTIF27  0x800      /* Mailbox 27 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF27  0x0       
 #define                   MBTIF28  0x1000     /* Mailbox 28 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF28  0x0       
 #define                   MBTIF29  0x2000     /* Mailbox 29 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF29  0x0       
 #define                   MBTIF30  0x4000     /* Mailbox 30 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF30  0x0       
 #define                   MBTIF31  0x8000     /* Mailbox 31 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF31  0x0       
 
 /* Bit masks for CAN0_MBRIF1 */
 
 #define                    MBRIF0  0x1        /* Mailbox 0 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF0  0x0       
 #define                    MBRIF1  0x2        /* Mailbox 1 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF1  0x0       
 #define                    MBRIF2  0x4        /* Mailbox 2 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF2  0x0       
 #define                    MBRIF3  0x8        /* Mailbox 3 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF3  0x0       
 #define                    MBRIF4  0x10       /* Mailbox 4 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF4  0x0       
 #define                    MBRIF5  0x20       /* Mailbox 5 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF5  0x0       
 #define                    MBRIF6  0x40       /* Mailbox 6 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF6  0x0       
 #define                    MBRIF7  0x80       /* Mailbox 7 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF7  0x0       
 #define                    MBRIF8  0x100      /* Mailbox 8 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF8  0x0       
 #define                    MBRIF9  0x200      /* Mailbox 9 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF9  0x0       
 #define                   MBRIF10  0x400      /* Mailbox 10 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF10  0x0       
 #define                   MBRIF11  0x800      /* Mailbox 11 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF11  0x0       
 #define                   MBRIF12  0x1000     /* Mailbox 12 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF12  0x0       
 #define                   MBRIF13  0x2000     /* Mailbox 13 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF13  0x0       
 #define                   MBRIF14  0x4000     /* Mailbox 14 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF14  0x0       
 #define                   MBRIF15  0x8000     /* Mailbox 15 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF15  0x0       
 
 /* Bit masks for CAN0_MBRIF2 */
 
 #define                   MBRIF16  0x1        /* Mailbox 16 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF16  0x0       
 #define                   MBRIF17  0x2        /* Mailbox 17 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF17  0x0       
 #define                   MBRIF18  0x4        /* Mailbox 18 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF18  0x0       
 #define                   MBRIF19  0x8        /* Mailbox 19 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF19  0x0       
 #define                   MBRIF20  0x10       /* Mailbox 20 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF20  0x0       
 #define                   MBRIF21  0x20       /* Mailbox 21 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF21  0x0       
 #define                   MBRIF22  0x40       /* Mailbox 22 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF22  0x0       
 #define                   MBRIF23  0x80       /* Mailbox 23 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF23  0x0       
 #define                   MBRIF24  0x100      /* Mailbox 24 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF24  0x0       
 #define                   MBRIF25  0x200      /* Mailbox 25 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF25  0x0       
 #define                   MBRIF26  0x400      /* Mailbox 26 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF26  0x0       
 #define                   MBRIF27  0x800      /* Mailbox 27 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF27  0x0       
 #define                   MBRIF28  0x1000     /* Mailbox 28 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF28  0x0       
 #define                   MBRIF29  0x2000     /* Mailbox 29 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF29  0x0       
 #define                   MBRIF30  0x4000     /* Mailbox 30 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF30  0x0       
 #define                   MBRIF31  0x8000     /* Mailbox 31 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF31  0x0       
 
 /* Bit masks for EPPIx_STATUS */
 
 #define                 CFIFO_ERR  0x1        /* Chroma FIFO Error */
-#define                nCFIFO_ERR  0x0       
 #define                 YFIFO_ERR  0x2        /* Luma FIFO Error */
-#define                nYFIFO_ERR  0x0       
 #define                 LTERR_OVR  0x4        /* Line Track Overflow */
-#define                nLTERR_OVR  0x0       
 #define                LTERR_UNDR  0x8        /* Line Track Underflow */
-#define               nLTERR_UNDR  0x0       
 #define                 FTERR_OVR  0x10       /* Frame Track Overflow */
-#define                nFTERR_OVR  0x0       
 #define                FTERR_UNDR  0x20       /* Frame Track Underflow */
-#define               nFTERR_UNDR  0x0       
 #define                  ERR_NCOR  0x40       /* Preamble Error Not Corrected */
-#define                 nERR_NCOR  0x0       
 #define                   DMA1URQ  0x80       /* DMA1 Urgent Request */
-#define                  nDMA1URQ  0x0       
 #define                   DMA0URQ  0x100      /* DMA0 Urgent Request */
-#define                  nDMA0URQ  0x0       
 #define                   ERR_DET  0x4000     /* Preamble Error Detected */
-#define                  nERR_DET  0x0       
 #define                       FLD  0x8000     /* Field */
-#define                      nFLD  0x0       
 
 /* Bit masks for EPPIx_CONTROL */
 
 #define                   EPPI_EN  0x1        /* Enable */
-#define                  nEPPI_EN  0x0       
 #define                  EPPI_DIR  0x2        /* Direction */
-#define                 nEPPI_DIR  0x0       
 #define                  XFR_TYPE  0xc        /* Operating Mode */
 #define                    FS_CFG  0x30       /* Frame Sync Configuration */
 #define                   FLD_SEL  0x40       /* Field Select/Trigger */
-#define                  nFLD_SEL  0x0       
 #define                  ITU_TYPE  0x80       /* ITU Interlaced or Progressive */
-#define                 nITU_TYPE  0x0       
 #define                  BLANKGEN  0x100      /* ITU Output Mode with Internal Blanking Generation */
-#define                 nBLANKGEN  0x0       
 #define                   ICLKGEN  0x200      /* Internal Clock Generation */
-#define                  nICLKGEN  0x0       
 #define                    IFSGEN  0x400      /* Internal Frame Sync Generation */
-#define                   nIFSGEN  0x0       
 #define                      POLC  0x1800     /* Frame Sync and Data Driving/Sampling Edges */
 #define                      POLS  0x6000     /* Frame Sync Polarity */
 #define                   DLENGTH  0x38000    /* Data Length */
 #define                   SKIP_EN  0x40000    /* Skip Enable */
-#define                  nSKIP_EN  0x0       
 #define                   SKIP_EO  0x80000    /* Skip Even or Odd */
-#define                  nSKIP_EO  0x0       
 #define                    PACKEN  0x100000   /* Packing/Unpacking Enable */
-#define                   nPACKEN  0x0       
 #define                    SWAPEN  0x200000   /* Swap Enable */
-#define                   nSWAPEN  0x0       
 #define                  SIGN_EXT  0x400000   /* Sign Extension or Zero-filled / Data Split Format */
-#define                 nSIGN_EXT  0x0       
 #define             SPLT_EVEN_ODD  0x800000   /* Split Even and Odd Data Samples */
-#define            nSPLT_EVEN_ODD  0x0       
 #define               SUBSPLT_ODD  0x1000000  /* Sub-split Odd Samples */
-#define              nSUBSPLT_ODD  0x0       
 #define                    DMACFG  0x2000000  /* One or Two DMA Channels Mode */
-#define                   nDMACFG  0x0       
 #define                RGB_FMT_EN  0x4000000  /* RGB Formatting Enable */
-#define               nRGB_FMT_EN  0x0       
 #define                  FIFO_RWM  0x18000000 /* FIFO Regular Watermarks */
 #define                  FIFO_UWM  0x60000000 /* FIFO Urgent Watermarks */
 
+#define DLEN_8          (0 << 15) /* 000 - 8 bits */
+#define DLEN_10         (1 << 15) /* 001 - 10 bits */
+#define DLEN_12         (2 << 15) /* 010 - 12 bits */
+#define DLEN_14         (3 << 15) /* 011 - 14 bits */
+#define DLEN_16         (4 << 15) /* 100 - 16 bits */
+#define DLEN_18         (5 << 15) /* 101 - 18 bits */
+#define DLEN_24         (6 << 15) /* 110 - 24 bits */
+
+
 /* Bit masks for EPPIx_FS2W_LVB */
 
 #define                   F1VB_BD  0xff       /* Vertical Blanking before Field 1 Active Data */
@@ -3951,60 +3085,36 @@
 /* Bit masks for SPIx_CTL */
 
 #define                       SPE  0x4000     /* SPI Enable */
-#define                      nSPE  0x0       
 #define                       WOM  0x2000     /* Write Open Drain Master */
-#define                      nWOM  0x0       
 #define                      MSTR  0x1000     /* Master Mode */
-#define                     nMSTR  0x0       
 #define                      CPOL  0x800      /* Clock Polarity */
-#define                     nCPOL  0x0       
 #define                      CPHA  0x400      /* Clock Phase */
-#define                     nCPHA  0x0       
 #define                      LSBF  0x200      /* LSB First */
-#define                     nLSBF  0x0       
 #define                      SIZE  0x100      /* Size of Words */
-#define                     nSIZE  0x0       
 #define                     EMISO  0x20       /* Enable MISO Output */
-#define                    nEMISO  0x0       
 #define                      PSSE  0x10       /* Slave-Select Enable */
-#define                     nPSSE  0x0       
 #define                        GM  0x8        /* Get More Data */
-#define                       nGM  0x0       
 #define                        SZ  0x4        /* Send Zero */
-#define                       nSZ  0x0       
 #define                     TIMOD  0x3        /* Transfer Initiation Mode */
 
 /* Bit masks for SPIx_FLG */
 
 #define                      FLS1  0x2        /* Slave Select Enable 1 */
-#define                     nFLS1  0x0       
 #define                      FLS2  0x4        /* Slave Select Enable 2 */
-#define                     nFLS2  0x0       
 #define                      FLS3  0x8        /* Slave Select Enable 3 */
-#define                     nFLS3  0x0       
 #define                      FLG1  0x200      /* Slave Select Value 1 */
-#define                     nFLG1  0x0       
 #define                      FLG2  0x400      /* Slave Select Value 2 */
-#define                     nFLG2  0x0       
 #define                      FLG3  0x800      /* Slave Select Value 3 */
-#define                     nFLG3  0x0       
 
 /* Bit masks for SPIx_STAT */
 
 #define                     TXCOL  0x40       /* Transmit Collision Error */
-#define                    nTXCOL  0x0       
 #define                       RXS  0x20       /* RDBR Data Buffer Status */
-#define                      nRXS  0x0       
 #define                      RBSY  0x10       /* Receive Error */
-#define                     nRBSY  0x0       
 #define                       TXS  0x8        /* TDBR Data Buffer Status */
-#define                      nTXS  0x0       
 #define                       TXE  0x4        /* Transmission Error */
-#define                      nTXE  0x0       
 #define                      MODF  0x2        /* Mode Fault Error */
-#define                     nMODF  0x0       
 #define                      SPIF  0x1        /* SPI Finished */
-#define                     nSPIF  0x0       
 
 /* Bit masks for SPIx_TDBR */
 
@@ -4028,9 +3138,7 @@
 
 #define                  PRESCALE  0x7f       /* Prescale Value */
 #define                   TWI_ENA  0x80       /* TWI Enable */
-#define                  nTWI_ENA  0x0       
 #define                      SCCB  0x200      /* Serial Camera Control Bus */
-#define                     nSCCB  0x0       
 
 /* Bit maskes for TWIx_CLKDIV */
 
@@ -4040,13 +3148,9 @@
 /* Bit maskes for TWIx_SLAVE_CTL */
 
 #define                       SEN  0x1        /* Slave Enable */
-#define                      nSEN  0x0       
 #define                    STDVAL  0x4        /* Slave Transmit Data Valid */
-#define                   nSTDVAL  0x0       
 #define                       NAK  0x8        /* Not Acknowledge */
-#define                      nNAK  0x0       
 #define                       GEN  0x10       /* General Call Enable */
-#define                      nGEN  0x0       
 
 /* Bit maskes for TWIx_SLAVE_ADDR */
 
@@ -4055,27 +3159,18 @@
 /* Bit maskes for TWIx_SLAVE_STAT */
 
 #define                      SDIR  0x1        /* Slave Transfer Direction */
-#define                     nSDIR  0x0       
 #define                     GCALL  0x2        /* General Call */
-#define                    nGCALL  0x0       
 
 /* Bit maskes for TWIx_MASTER_CTL */
 
 #define                       MEN  0x1        /* Master Mode Enable */
-#define                      nMEN  0x0       
 #define                      MDIR  0x4        /* Master Transfer Direction */
-#define                     nMDIR  0x0       
 #define                      FAST  0x8        /* Fast Mode */
-#define                     nFAST  0x0       
 #define                      STOP  0x10       /* Issue Stop Condition */
-#define                     nSTOP  0x0       
 #define                    RSTART  0x20       /* Repeat Start */
-#define                   nRSTART  0x0       
 #define                      DCNT  0x3fc0     /* Data Transfer Count */
 #define                    SDAOVR  0x4000     /* Serial Data Override */
-#define                   nSDAOVR  0x0       
 #define                    SCLOVR  0x8000     /* Serial Clock Override */
-#define                   nSCLOVR  0x0       
 
 /* Bit maskes for TWIx_MASTER_ADDR */
 
@@ -4084,34 +3179,21 @@
 /* Bit maskes for TWIx_MASTER_STAT */
 
 #define                     MPROG  0x1        /* Master Transfer in Progress */
-#define                    nMPROG  0x0       
 #define                   LOSTARB  0x2        /* Lost Arbitration */
-#define                  nLOSTARB  0x0       
 #define                      ANAK  0x4        /* Address Not Acknowledged */
-#define                     nANAK  0x0       
 #define                      DNAK  0x8        /* Data Not Acknowledged */
-#define                     nDNAK  0x0       
 #define                  BUFRDERR  0x10       /* Buffer Read Error */
-#define                 nBUFRDERR  0x0       
 #define                  BUFWRERR  0x20       /* Buffer Write Error */
-#define                 nBUFWRERR  0x0       
 #define                    SDASEN  0x40       /* Serial Data Sense */
-#define                   nSDASEN  0x0       
 #define                    SCLSEN  0x80       /* Serial Clock Sense */
-#define                   nSCLSEN  0x0       
 #define                   BUSBUSY  0x100      /* Bus Busy */
-#define                  nBUSBUSY  0x0       
 
 /* Bit maskes for TWIx_FIFO_CTL */
 
 #define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
-#define                 nXMTFLUSH  0x0       
 #define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
-#define                 nRCVFLUSH  0x0       
 #define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
-#define                nXMTINTLEN  0x0       
 #define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
-#define                nRCVINTLEN  0x0       
 
 /* Bit maskes for TWIx_FIFO_STAT */
 
@@ -4121,40 +3203,24 @@
 /* Bit maskes for TWIx_INT_MASK */
 
 #define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
-#define                   nSINITM  0x0       
 #define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
-#define                   nSCOMPM  0x0       
 #define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
-#define                    nSERRM  0x0       
 #define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
-#define                    nSOVFM  0x0       
 #define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
-#define                   nMCOMPM  0x0       
 #define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
-#define                    nMERRM  0x0       
 #define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
-#define                 nXMTSERVM  0x0       
 #define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
-#define                 nRCVSERVM  0x0       
 
 /* Bit maskes for TWIx_INT_STAT */
 
 #define                     SINIT  0x1        /* Slave Transfer Initiated */
-#define                    nSINIT  0x0       
 #define                     SCOMP  0x2        /* Slave Transfer Complete */
-#define                    nSCOMP  0x0       
 #define                      SERR  0x4        /* Slave Transfer Error */
-#define                     nSERR  0x0       
 #define                      SOVF  0x8        /* Slave Overflow */
-#define                     nSOVF  0x0       
 #define                     MCOMP  0x10       /* Master Transfer Complete */
-#define                    nMCOMP  0x0       
 #define                      MERR  0x20       /* Master Transfer Error */
-#define                     nMERR  0x0       
 #define                   XMTSERV  0x40       /* Transmit FIFO Service */
-#define                  nXMTSERV  0x0       
 #define                   RCVSERV  0x80       /* Receive FIFO Service */
-#define                  nRCVSERV  0x0       
 
 /* Bit maskes for TWIx_XMT_DATA8 */
 
@@ -4175,81 +3241,51 @@
 /* Bit masks for SPORTx_TCR1 */
 
 #define                     TCKFE  0x4000     /* Clock Falling Edge Select */
-#define                    nTCKFE  0x0       
 #define                     LATFS  0x2000     /* Late Transmit Frame Sync */
-#define                    nLATFS  0x0       
 #define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
-#define                     nLTFS  0x0       
 #define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
-#define                    nDITFS  0x0       
 #define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
-#define                     nTFSR  0x0       
 #define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
-#define                     nITFS  0x0       
 #define                    TLSBIT  0x10       /* Transmit Bit Order */
-#define                   nTLSBIT  0x0       
 #define                    TDTYPE  0xc        /* Data Formatting Type Select */
 #define                     ITCLK  0x2        /* Internal Transmit Clock Select */
-#define                    nITCLK  0x0       
 #define                     TSPEN  0x1        /* Transmit Enable */
-#define                    nTSPEN  0x0       
 
 /* Bit masks for SPORTx_TCR2 */
 
 #define                     TRFST  0x400      /* Left/Right Order */
-#define                    nTRFST  0x0       
 #define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
-#define                    nTSFSE  0x0       
 #define                      TXSE  0x100      /* TxSEC Enable */
-#define                     nTXSE  0x0       
 #define                    SLEN_T  0x1f       /* SPORT Word Length */
 
 /* Bit masks for SPORTx_RCR1 */
 
 #define                     RCKFE  0x4000     /* Clock Falling Edge Select */
-#define                    nRCKFE  0x0       
 #define                     LARFS  0x2000     /* Late Receive Frame Sync */
-#define                    nLARFS  0x0       
 #define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
-#define                     nLRFS  0x0       
 #define                      RFSR  0x400      /* Receive Frame Sync Required Select */
-#define                     nRFSR  0x0       
 #define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
-#define                     nIRFS  0x0       
 #define                    RLSBIT  0x10       /* Receive Bit Order */
-#define                   nRLSBIT  0x0       
 #define                    RDTYPE  0xc        /* Data Formatting Type Select */
 #define                     IRCLK  0x2        /* Internal Receive Clock Select */
-#define                    nIRCLK  0x0       
 #define                     RSPEN  0x1        /* Receive Enable */
-#define                    nRSPEN  0x0       
 
 /* Bit masks for SPORTx_RCR2 */
 
 #define                     RRFST  0x400      /* Left/Right Order */
-#define                    nRRFST  0x0       
 #define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
-#define                    nRSFSE  0x0       
 #define                      RXSE  0x100      /* RxSEC Enable */
-#define                     nRXSE  0x0       
 #define                    SLEN_R  0x1f       /* SPORT Word Length */
 
 /* Bit masks for SPORTx_STAT */
 
 #define                     TXHRE  0x40       /* Transmit Hold Register Empty */
-#define                    nTXHRE  0x0       
 #define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
-#define                     nTOVF  0x0       
 #define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
-#define                     nTUVF  0x0       
 #define                       TXF  0x8        /* Transmit FIFO Full Status */
-#define                      nTXF  0x0       
 #define                      ROVF  0x4        /* Sticky Receive Overflow Status */
-#define                     nROVF  0x0       
 #define                      RUVF  0x2        /* Sticky Receive Underflow Status */
-#define                     nRUVF  0x0       
 #define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
-#define                     nRXNE  0x0       
 
 /* Bit masks for SPORTx_MCMC1 */
 
@@ -4260,13 +3296,9 @@
 
 #define                       MFD  0xf000     /* Multi channel Frame Delay */
 #define                      FSDR  0x80       /* Frame Sync to Data Relationship */
-#define                     nFSDR  0x0       
 #define                     MCMEM  0x10       /* Multi channel Frame Mode Enable */
-#define                    nMCMEM  0x0       
 #define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
-#define                  nMCDRXPE  0x0       
 #define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
-#define                  nMCDTXPE  0x0       
 #define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
 
 /* Bit masks for SPORTx_CHNL */
@@ -4280,115 +3312,59 @@
 #define                       WLS  0x3        /* Word Length Select */
 #endif
 #define                       STB  0x4        /* Stop Bits */
-#define                      nSTB  0x0       
 #define                       PEN  0x8        /* Parity Enable */
-#define                      nPEN  0x0       
 #define                       EPS  0x10       /* Even Parity Select */
-#define                      nEPS  0x0       
 #define                       STP  0x20       /* Sticky Parity */
-#define                      nSTP  0x0       
 #define                        SB  0x40       /* Set Break */
-#define                       nSB  0x0       
 
 /* Bit masks for UARTx_MCR */
 
 #define                      XOFF  0x1        /* Transmitter Off */
-#define                     nXOFF  0x0       
 #define                      MRTS  0x2        /* Manual Request To Send */
-#define                     nMRTS  0x0       
 #define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                     nRFIT  0x0       
 #define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                     nRFRT  0x0       
 #define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                 nLOOP_ENA  0x0       
 #define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                    nFCPOL  0x0       
 #define                      ARTS  0x40       /* Automatic Request To Send */
-#define                     nARTS  0x0       
 #define                      ACTS  0x80       /* Automatic Clear To Send */
-#define                     nACTS  0x0       
 
 /* Bit masks for UARTx_LSR */
 
 #define                        DR  0x1        /* Data Ready */
-#define                       nDR  0x0       
 #define                        OE  0x2        /* Overrun Error */
-#define                       nOE  0x0       
 #define                        PE  0x4        /* Parity Error */
-#define                       nPE  0x0       
 #define                        FE  0x8        /* Framing Error */
-#define                       nFE  0x0       
 #define                        BI  0x10       /* Break Interrupt */
-#define                       nBI  0x0       
 #define                      THRE  0x20       /* THR Empty */
-#define                     nTHRE  0x0       
 #define                      TEMT  0x40       /* Transmitter Empty */
-#define                     nTEMT  0x0       
 #define                       TFI  0x80       /* Transmission Finished Indicator */
-#define                      nTFI  0x0       
 
 /* Bit masks for UARTx_MSR */
 
 #define                      SCTS  0x1        /* Sticky CTS */
-#define                     nSCTS  0x0       
 #define                       CTS  0x10       /* Clear To Send */
-#define                      nCTS  0x0       
 #define                      RFCS  0x20       /* Receive FIFO Count Status */
-#define                     nRFCS  0x0       
-
-/* Bit masks for UARTx_IER_SET */
-
-#define                   ERBFI_S  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                  nERBFI_S  0x0       
-#define                   ETBEI_S  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                  nETBEI_S  0x0       
-#define                    ELSI_S  0x4        /* Enable Receive Status Interrupt */
-#define                   nELSI_S  0x0       
-#define                   EDSSI_S  0x8        /* Enable Modem Status Interrupt */
-#define                  nEDSSI_S  0x0       
-#define                  EDTPTI_S  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                 nEDTPTI_S  0x0       
-#define                    ETFI_S  0x20       /* Enable Transmission Finished Interrupt */
-#define                   nETFI_S  0x0       
-#define                   ERFCI_S  0x40       /* Enable Receive FIFO Count Interrupt */
-#define                  nERFCI_S  0x0       
-
-/* Bit masks for UARTx_IER_CLEAR */
-
-#define                   ERBFI_C  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                  nERBFI_C  0x0       
-#define                   ETBEI_C  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                  nETBEI_C  0x0       
-#define                    ELSI_C  0x4        /* Enable Receive Status Interrupt */
-#define                   nELSI_C  0x0       
-#define                   EDSSI_C  0x8        /* Enable Modem Status Interrupt */
-#define                  nEDSSI_C  0x0       
-#define                  EDTPTI_C  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                 nEDTPTI_C  0x0       
-#define                    ETFI_C  0x20       /* Enable Transmission Finished Interrupt */
-#define                   nETFI_C  0x0       
-#define                   ERFCI_C  0x40       /* Enable Receive FIFO Count Interrupt */
-#define                  nERFCI_C  0x0       
+
+/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
+
+#define                   ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
+#define                   ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
+#define                    ELSI  0x4        /* Enable Receive Status Interrupt */
+#define                   EDSSI  0x8        /* Enable Modem Status Interrupt */
+#define                  EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
+#define                    ETFI  0x20       /* Enable Transmission Finished Interrupt */
+#define                   ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
 
 /* Bit masks for UARTx_GCTL */
 
 #define                      UCEN  0x1        /* UART Enable */
-#define                     nUCEN  0x0       
 #define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     nIREN  0x0       
 #define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                    nTPOLC  0x0       
 #define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                    nRPOLC  0x0       
 #define                       FPE  0x10       /* Force Parity Error */
-#define                      nFPE  0x0       
 #define                       FFE  0x20       /* Force Framing Error */
-#define                      nFFE  0x0       
 #define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     nEDBO  0x0       
 #define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-#define                    nEGLSI  0x0       
 
 
 /* ******************************************* */
@@ -4398,32 +3374,32 @@
 /* BCODE bit field options (SYSCFG register) */
 
 #define BCODE_WAKEUP    0x0000  /* boot according to wake-up condition */
-#define BCODE_FULLBOOT  0x0010  /* always perform full boot */ 
+#define BCODE_FULLBOOT  0x0010  /* always perform full boot */
 #define BCODE_QUICKBOOT 0x0020  /* always perform quick boot */
 #define BCODE_NOBOOT    0x0030  /* always perform full boot */
 
 /* CNT_COMMAND bit field options */
- 
+
 #define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
 #define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
 #define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
- 
+
 #define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
 #define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
 #define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
- 
+
 #define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
 #define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
 #define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
- 
+
 /* CNT_CONFIG bit field options */
- 
+
 #define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
 #define CNTMODE_BINENC   0x0100  /* binary encoder mode */
 #define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
 #define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
 #define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
- 
+
 #define BNDMODE_COMP     0x0000  /* boundary compare mode */
 #define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
 #define BNDMODE_CAPT     0x2000  /* boundary capture mode */
@@ -4436,7 +3412,7 @@
 #define EXT_CLK  0x0003
 
 /* UARTx_LCR bit field options */
- 
+
 #define WLS_5   0x0000    /* 5 data bits */
 #define WLS_6   0x0001    /* 6 data bits */
 #define WLS_7   0x0002    /* 7 data bits */
@@ -4484,7 +3460,7 @@
 #define PIQ30 0x40000000
 #define PIQ31 0x80000000
 
-/* PORT A Bit Definitions for the registers 
+/* PORT A Bit Definitions for the registers
 PORTA, PORTA_SET, PORTA_CLEAR,
 PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
 PORTA_FER registers
@@ -4507,7 +3483,7 @@ PORTA_FER registers
 #define PA14 0x4000
 #define PA15 0x8000
 
-/* PORT B Bit Definitions for the registers 
+/* PORT B Bit Definitions for the registers
 PORTB, PORTB_SET, PORTB_CLEAR,
 PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
 PORTB_FER registers
@@ -4530,7 +3506,7 @@ PORTB_FER registers
 #define PB14 0x4000
 
 
-/* PORT C Bit Definitions for the registers 
+/* PORT C Bit Definitions for the registers
 PORTC, PORTC_SET, PORTC_CLEAR,
 PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
 PORTC_FER registers
@@ -4553,7 +3529,7 @@ PORTC_FER registers
 #define PC13 0x2000
 
 
-/* PORT D Bit Definitions for the registers 
+/* PORT D Bit Definitions for the registers
 PORTD, PORTD_SET, PORTD_CLEAR,
 PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
 PORTD_FER registers
@@ -4576,7 +3552,7 @@ PORTD_FER registers
 #define PD14 0x4000
 #define PD15 0x8000
 
-/* PORT E Bit Definitions for the registers 
+/* PORT E Bit Definitions for the registers
 PORTE, PORTE_SET, PORTE_CLEAR,
 PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
 PORTE_FER registers
@@ -4600,7 +3576,7 @@ PORTE_FER registers
 #define PE14 0x4000
 #define PE15 0x8000
 
-/* PORT F Bit Definitions for the registers 
+/* PORT F Bit Definitions for the registers
 PORTF, PORTF_SET, PORTF_CLEAR,
 PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
 PORTF_FER registers
@@ -4624,7 +3600,7 @@ PORTF_FER registers
 #define PF14 0x4000
 #define PF15 0x8000
 
-/* PORT G Bit Definitions for the registers 
+/* PORT G Bit Definitions for the registers
 PORTG, PORTG_SET, PORTG_CLEAR,
 PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
 PORTG_FER registers
@@ -4648,7 +3624,7 @@ PORTG_FER registers
 #define PG14 0x4000
 #define PG15 0x8000
 
-/* PORT H Bit Definitions for the registers 
+/* PORT H Bit Definitions for the registers
 PORTH, PORTH_SET, PORTH_CLEAR,
 PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
 PORTH_FER registers
@@ -4671,7 +3647,7 @@ PORTH_FER registers
 #define PH13 0x2000
 
 
-/* PORT I Bit Definitions for the registers 
+/* PORT I Bit Definitions for the registers
 PORTI, PORTI_SET, PORTI_CLEAR,
 PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
 PORTI_FER registers
@@ -4695,7 +3671,7 @@ PORTI_FER registers
 #define PI14 0x4000
 #define PI15 0x8000
 
-/* PORT J Bit Definitions for the registers 
+/* PORT J Bit Definitions for the registers
 PORTJ, PORTJ_SET, PORTJ_CLEAR,
 PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
 PORTJ_FER registers
@@ -4716,7 +3692,7 @@ PORTJ_FER registers
 #define PJ11 0x0800
 #define PJ12 0x1000
 #define PJ13 0x2000
- 
+
 
 /* Port Muxing Bit Fields for PORTx_MUX Registers */
 
@@ -4860,7 +3836,7 @@ PORTJ_FER registers
 #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
 #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
 
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ 
+#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
 #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
 #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
 #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
@@ -4869,27 +3845,27 @@ PORTJ_FER registers
 #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
 #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
 
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ 
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ 
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ 
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ 
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ 
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ 
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ 
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ 
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ 
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ 
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ 
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ 
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ 
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ 
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ 
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ 
+#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
+#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
+#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
+#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
+#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
+#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
+#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
+#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
+
+#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
+#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
+#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
+#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
+#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
+#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
+#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
+#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
 
 
 /* for legacy compatibility */
- 
+
 #define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
 #define W1LMAX_MAX W1LMAX_MIN
 #define EBIU_AMCBCTL0 EBIU_AMBCTL0
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
new file mode 100644
index 000000000000..fcc8b4c34c6a
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -0,0 +1,73 @@
+/*
+ * file:         include/asm-blackfin/mach-bf548/dma.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+
+#define CH_SPORT0_RX            0
+#define CH_SPORT0_TX            1
+#define CH_SPORT1_RX            2
+#define CH_SPORT1_TX            3
+#define CH_SPI0                 4
+#define CH_SPI1                 5
+#define CH_UART0_RX             6
+#define CH_UART0_TX             7
+#define CH_UART1_RX             8
+#define CH_UART1_TX             9
+#define CH_ATAPI_RX             10
+#define CH_ATAPI_TX             11
+#define CH_EPPI0                12
+#define CH_EPPI1                13
+#define CH_EPPI2                14
+#define CH_PIXC_IMAGE           15
+#define CH_PIXC_OVERLAY         16
+#define CH_PIXC_OUTPUT          17
+#define CH_SPORT2_RX            18
+#define CH_SPORT2_TX            19
+#define CH_SPORT3_RX            20
+#define CH_SPORT3_TX            21
+#define CH_SDH                  22
+#define CH_SPI2                 23
+
+#define CH_MEM_STREAM0_DEST     24
+#define CH_MEM_STREAM0_SRC      25
+#define CH_MEM_STREAM1_DEST     26
+#define CH_MEM_STREAM1_SRC      27
+#define CH_MEM_STREAM2_DEST     28
+#define CH_MEM_STREAM2_SRC      29
+#define CH_MEM_STREAM3_DEST     30
+#define CH_MEM_STREAM3_SRC      31
+
+#define MAX_BLACKFIN_DMA_CHANNEL 32
+
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+#endif
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
new file mode 100644
index 000000000000..dbf66bcabe35
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/gpio.h
@@ -0,0 +1,216 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/gpio.h
+ * Based on:
+ * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+
+
+#define GPIO_PA0        0
+#define GPIO_PA1        1
+#define GPIO_PA2        2
+#define GPIO_PA3        3
+#define GPIO_PA4        4
+#define GPIO_PA5        5
+#define GPIO_PA6        6
+#define GPIO_PA7        7
+#define GPIO_PA8        8
+#define GPIO_PA9        9
+#define GPIO_PA10       10
+#define GPIO_PA11       11
+#define GPIO_PA12       12
+#define GPIO_PA13       13
+#define GPIO_PA14       14
+#define GPIO_PA15       15
+#define GPIO_PB0        16
+#define GPIO_PB1        17
+#define GPIO_PB2        18
+#define GPIO_PB3        19
+#define GPIO_PB4        20
+#define GPIO_PB5        21
+#define GPIO_PB6        22
+#define GPIO_PB7        23
+#define GPIO_PB8        24
+#define GPIO_PB9        25
+#define GPIO_PB10       26
+#define GPIO_PB11       27
+#define GPIO_PB12       28
+#define GPIO_PB13       29
+#define GPIO_PB14       30
+#define GPIO_PB15       31      /* N/A */
+#define GPIO_PC0        32
+#define GPIO_PC1        33
+#define GPIO_PC2        34
+#define GPIO_PC3        35
+#define GPIO_PC4        36
+#define GPIO_PC5        37
+#define GPIO_PC6        38
+#define GPIO_PC7        39
+#define GPIO_PC8        40
+#define GPIO_PC9        41
+#define GPIO_PC10       42
+#define GPIO_PC11       43
+#define GPIO_PC12       44
+#define GPIO_PC13       45
+#define GPIO_PC14       46      /* N/A */
+#define GPIO_PC15       47      /* N/A */
+#define GPIO_PD0        48
+#define GPIO_PD1        49
+#define GPIO_PD2        50
+#define GPIO_PD3        51
+#define GPIO_PD4        52
+#define GPIO_PD5        53
+#define GPIO_PD6        54
+#define GPIO_PD7        55
+#define GPIO_PD8        56
+#define GPIO_PD9        57
+#define GPIO_PD10       58
+#define GPIO_PD11       59
+#define GPIO_PD12       60
+#define GPIO_PD13       61
+#define GPIO_PD14       62
+#define GPIO_PD15       63
+#define GPIO_PE0        64
+#define GPIO_PE1        65
+#define GPIO_PE2        66
+#define GPIO_PE3        67
+#define GPIO_PE4        68
+#define GPIO_PE5        69
+#define GPIO_PE6        70
+#define GPIO_PE7        71
+#define GPIO_PE8        72
+#define GPIO_PE9        73
+#define GPIO_PE10       74
+#define GPIO_PE11       75
+#define GPIO_PE12       76
+#define GPIO_PE13       77
+#define GPIO_PE14       78
+#define GPIO_PE15       79
+#define GPIO_PF0        80
+#define GPIO_PF1        81
+#define GPIO_PF2        82
+#define GPIO_PF3        83
+#define GPIO_PF4        84
+#define GPIO_PF5        85
+#define GPIO_PF6        86
+#define GPIO_PF7        87
+#define GPIO_PF8        88
+#define GPIO_PF9        89
+#define GPIO_PF10       90
+#define GPIO_PF11       91
+#define GPIO_PF12       92
+#define GPIO_PF13       93
+#define GPIO_PF14       94
+#define GPIO_PF15       95
+#define GPIO_PG0        96
+#define GPIO_PG1        97
+#define GPIO_PG2        98
+#define GPIO_PG3        99
+#define GPIO_PG4        100
+#define GPIO_PG5        101
+#define GPIO_PG6        102
+#define GPIO_PG7        103
+#define GPIO_PG8        104
+#define GPIO_PG9        105
+#define GPIO_PG10       106
+#define GPIO_PG11       107
+#define GPIO_PG12       108
+#define GPIO_PG13       109
+#define GPIO_PG14       110
+#define GPIO_PG15       111
+#define GPIO_PH0        112
+#define GPIO_PH1        113
+#define GPIO_PH2        114
+#define GPIO_PH3        115
+#define GPIO_PH4        116
+#define GPIO_PH5        117
+#define GPIO_PH6        118
+#define GPIO_PH7        119
+#define GPIO_PH8        120
+#define GPIO_PH9        121
+#define GPIO_PH10       122
+#define GPIO_PH11       123
+#define GPIO_PH12       124
+#define GPIO_PH13       125
+#define GPIO_PH14       126     /* N/A */
+#define GPIO_PH15       127     /* N/A */
+#define GPIO_PI0        128
+#define GPIO_PI1        129
+#define GPIO_PI2        130
+#define GPIO_PI3        131
+#define GPIO_PI4        132
+#define GPIO_PI5        133
+#define GPIO_PI6        134
+#define GPIO_PI7        135
+#define GPIO_PI8        136
+#define GPIO_PI9        137
+#define GPIO_PI10       138
+#define GPIO_PI11       139
+#define GPIO_PI12       140
+#define GPIO_PI13       141
+#define GPIO_PI14       142
+#define GPIO_PI15       143
+#define GPIO_PJ0        144
+#define GPIO_PJ1        145
+#define GPIO_PJ2        146
+#define GPIO_PJ3        147
+#define GPIO_PJ4        148
+#define GPIO_PJ5        149
+#define GPIO_PJ6        150
+#define GPIO_PJ7        151
+#define GPIO_PJ8        152
+#define GPIO_PJ9        153
+#define GPIO_PJ10       154
+#define GPIO_PJ11       155
+#define GPIO_PJ12       156
+#define GPIO_PJ13       157
+#define GPIO_PJ14       158     /* N/A */
+#define GPIO_PJ15       159     /* N/A */
+
+#define MAX_BLACKFIN_GPIOS 160
+
+struct gpio_port_t {
+        unsigned short port_fer;
+        unsigned short dummy1;
+        unsigned short port_data;
+        unsigned short dummy2;
+        unsigned short port_set;
+        unsigned short dummy3;
+        unsigned short port_clear;
+        unsigned short dummy4;
+        unsigned short port_dir_set;
+        unsigned short dummy5;
+        unsigned short port_dir_clear;
+        unsigned short dummy6;
+        unsigned short port_inen;
+        unsigned short dummy7;
+        unsigned int port_mux;
+};
+
+int gpio_request(unsigned short gpio, const char *label);
+void peripheral_free(unsigned short per);
+int peripheral_request_list(unsigned short per[], const char *label);
+void peripheral_free_list(unsigned short per[]);
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
new file mode 100644
index 000000000000..0b3325bb1fff
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -0,0 +1,467 @@
+/*
+ * file:        include/asm-blackfin/mach-bf548/irq.h
+ * based on:    include/asm-blackfin/mach-bf537/irq.h
+ * author:      Roy Huang (roy.huang@analog.com)
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _BF548_IRQ_H_
+#define _BF548_IRQ_H_
+
+/*
+ * Interrupt source definitions
+            Event Source    Core Event Name
+Core        Emulation               **
+Events         (highest priority)  EMU         0
+            Reset                   RST         1
+            NMI                     NMI         2
+            Exception               EVX         3
+            Reserved                --          4
+            Hardware Error          IVHW        5
+            Core Timer              IVTMR       6 *
+
+.....
+
+            Software Interrupt 1    IVG14       31
+            Software Interrupt 2    --
+                 (lowest priority)  IVG15       32 *
+ */
+
+#define NR_PERI_INTS    (32 * 3)
+
+/* The ABSTRACT IRQ definitions */
+/** the first seven of the following are fixed, the rest you change if you need to **/
+#define IRQ_EMU         0       /* Emulation */
+#define IRQ_RST         1       /* reset */
+#define IRQ_NMI         2       /* Non Maskable */
+#define IRQ_EVX         3       /* Exception */
+#define IRQ_UNUSED      4       /* - unused interrupt*/
+#define IRQ_HWERR       5       /* Hardware Error */
+#define IRQ_CORETMR     6       /* Core timer */
+
+#define BFIN_IRQ(x)     ((x) + 7)
+
+#define IRQ_PLL_WAKEUP  BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_DMAC0_ERR   BFIN_IRQ(1)     /* DMAC0 Status Interrupt */
+#define IRQ_EPPI0_ERR   BFIN_IRQ(2)     /* EPPI0 Error Interrupt */
+#define IRQ_SPORT0_ERR  BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERR  BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
+#define IRQ_SPI0_ERR    BFIN_IRQ(5)     /* SPI0 Status(Error) Interrupt */
+#define IRQ_UART0_ERR   BFIN_IRQ(6)     /* UART0 Status(Error) Interrupt */
+#define IRQ_RTC         BFIN_IRQ(7)     /* RTC Interrupt */
+#define IRQ_EPPI0       BFIN_IRQ(8)     /* EPPI0 Interrupt (DMA12) */
+#define IRQ_SPORT0_RX   BFIN_IRQ(9)     /* SPORT0 RX Interrupt (DMA0) */
+#define IRQ_SPORT0_TX   BFIN_IRQ(10)    /* SPORT0 TX Interrupt (DMA1) */
+#define IRQ_SPORT1_RX   BFIN_IRQ(11)    /* SPORT1 RX Interrupt (DMA2) */
+#define IRQ_SPORT1_TX   BFIN_IRQ(12)    /* SPORT1 TX Interrupt (DMA3) */
+#define IRQ_SPI0        BFIN_IRQ(13)    /* SPI0 Interrupt (DMA4) */
+#define IRQ_UART0_RX    BFIN_IRQ(14)    /* UART0 RX Interrupt (DMA6) */
+#define IRQ_UART0_TX    BFIN_IRQ(15)    /* UART0 TX Interrupt (DMA7) */
+#define IRQ_TIMER8      BFIN_IRQ(16)    /* TIMER 8 Interrupt */
+#define IRQ_TIMER9      BFIN_IRQ(17)    /* TIMER 9 Interrupt */
+#define IRQ_TIMER10     BFIN_IRQ(18)    /* TIMER 10 Interrupt */
+#define IRQ_PINT0       BFIN_IRQ(19)    /* PINT0 Interrupt */
+#define IRQ_PINT1       BFIN_IRQ(20)    /* PINT1 Interrupt */
+#define IRQ_MDMAS0      BFIN_IRQ(21)    /* MDMA Stream 0 Interrupt */
+#define IRQ_MDMAS1      BFIN_IRQ(22)    /* MDMA Stream 1 Interrupt */
+#define IRQ_WATCHDOG    BFIN_IRQ(23)    /* Watchdog Interrupt */
+#define IRQ_DMAC1_ERR   BFIN_IRQ(24)    /* DMAC1 Status (Error) Interrupt */
+#define IRQ_SPORT2_ERR  BFIN_IRQ(25)    /* SPORT2 Error Interrupt */
+#define IRQ_SPORT3_ERR  BFIN_IRQ(26)    /* SPORT3 Error Interrupt */
+#define IRQ_MXVR_DATA   BFIN_IRQ(27)    /* MXVR Data Interrupt */
+#define IRQ_SPI1_ERR    BFIN_IRQ(28)    /* SPI1 Status (Error) Interrupt */
+#define IRQ_SPI2_ERR    BFIN_IRQ(29)    /* SPI2 Status (Error) Interrupt */
+#define IRQ_UART1_ERR   BFIN_IRQ(30)    /* UART1 Status (Error) Interrupt */
+#define IRQ_UART2_ERR   BFIN_IRQ(31)    /* UART2 Status (Error) Interrupt */
+#define IRQ_CAN0_ERR    BFIN_IRQ(32)    /* CAN0 Status (Error) Interrupt */
+#define IRQ_SPORT2_RX   BFIN_IRQ(33)    /* SPORT2 RX (DMA18) Interrupt */
+#define IRQ_SPORT2_TX   BFIN_IRQ(34)    /* SPORT2 TX (DMA19) Interrupt */
+#define IRQ_SPORT3_RX   BFIN_IRQ(35)    /* SPORT3 RX (DMA20) Interrupt */
+#define IRQ_SPORT3_TX   BFIN_IRQ(36)    /* SPORT3 TX (DMA21) Interrupt */
+#define IRQ_EPPI1       BFIN_IRQ(37)    /* EPP1 (DMA13) Interrupt */
+#define IRQ_EPPI2       BFIN_IRQ(38)    /* EPP2 (DMA14) Interrupt */
+#define IRQ_SPI1        BFIN_IRQ(39)    /* SPI1 (DMA5) Interrupt */
+#define IRQ_SPI2        BFIN_IRQ(40)    /* SPI2 (DMA23) Interrupt */
+#define IRQ_UART1_RX    BFIN_IRQ(41)    /* UART1 RX (DMA8) Interrupt */
+#define IRQ_UART1_TX    BFIN_IRQ(42)    /* UART1 TX (DMA9) Interrupt */
+#define IRQ_ATAPI_RX    BFIN_IRQ(43)    /* ATAPI RX (DMA10) Interrupt */
+#define IRQ_ATAPI_TX    BFIN_IRQ(44)    /* ATAPI TX (DMA11) Interrupt */
+#define IRQ_TWI0        BFIN_IRQ(45)    /* TWI0 Interrupt */
+#define IRQ_TWI1        BFIN_IRQ(46)    /* TWI1 Interrupt */
+#define IRQ_CAN0_RX     BFIN_IRQ(47)    /* CAN0 Receive Interrupt */
+#define IRQ_CAN0_TX     BFIN_IRQ(48)    /* CAN0 Transmit Interrupt */
+#define IRQ_MDMAS2      BFIN_IRQ(49)    /* MDMA Stream 2 Interrupt */
+#define IRQ_MDMAS3      BFIN_IRQ(50)    /* MDMA Stream 3 Interrupt */
+#define IRQ_MXVR_ERR    BFIN_IRQ(51)    /* MXVR Status (Error) Interrupt */
+#define IRQ_MXVR_MSG    BFIN_IRQ(52)    /* MXVR Message Interrupt */
+#define IRQ_MXVR_PKT    BFIN_IRQ(53)    /* MXVR Packet Interrupt */
+#define IRQ_EPP1_ERR    BFIN_IRQ(54)    /* EPPI1 Error Interrupt */
+#define IRQ_EPP2_ERR    BFIN_IRQ(55)    /* EPPI2 Error Interrupt */
+#define IRQ_UART3_ERR   BFIN_IRQ(56)    /* UART3 Status (Error) Interrupt */
+#define IRQ_HOST_ERR    BFIN_IRQ(57)    /* HOST Status (Error) Interrupt */
+#define IRQ_PIXC_ERR    BFIN_IRQ(59)    /* PIXC Status (Error) Interrupt */
+#define IRQ_NFC_ERR     BFIN_IRQ(60)    /* NFC Error Interrupt */
+#define IRQ_ATAPI_ERR   BFIN_IRQ(61)    /* ATAPI Error Interrupt */
+#define IRQ_CAN1_ERR    BFIN_IRQ(62)    /* CAN1 Status (Error) Interrupt */
+#define IRQ_HS_DMA_ERR  BFIN_IRQ(63)    /* Handshake DMA Status Interrupt */
+#define IRQ_PIXC_IN0    BFIN_IRQ(64)    /* PIXC IN0 (DMA15) Interrupt */
+#define IRQ_PIXC_IN1    BFIN_IRQ(65)    /* PIXC IN1 (DMA16) Interrupt */
+#define IRQ_PIXC_OUT    BFIN_IRQ(66)    /* PIXC OUT (DMA17) Interrupt */
+#define IRQ_SDH         BFIN_IRQ(67)    /* SDH/NFC (DMA22) Interrupt */
+#define IRQ_CNT         BFIN_IRQ(68)    /* CNT Interrupt */
+#define IRQ_KEY         BFIN_IRQ(69)    /* KEY Interrupt */
+#define IRQ_CAN1_RX     BFIN_IRQ(70)    /* CAN1 RX Interrupt */
+#define IRQ_CAN1_TX     BFIN_IRQ(71)    /* CAN1 TX Interrupt */
+#define IRQ_SDH_MASK0   BFIN_IRQ(72)    /* SDH Mask 0 Interrupt */
+#define IRQ_SDH_MASK1   BFIN_IRQ(73)    /* SDH Mask 1 Interrupt */
+#define IRQ_USB_INT0    BFIN_IRQ(75)    /* USB INT0 Interrupt */
+#define IRQ_USB_INT1    BFIN_IRQ(76)    /* USB INT1 Interrupt */
+#define IRQ_USB_INT2    BFIN_IRQ(77)    /* USB INT2 Interrupt */
+#define IRQ_USB_DMA     BFIN_IRQ(78)    /* USB DMA Interrupt */
+#define IRQ_OPTSEC      BFIN_IRQ(79)    /* OTPSEC Interrupt */
+#define IRQ_TIMER0      BFIN_IRQ(86)    /* Timer 0 Interrupt */
+#define IRQ_TIMER1      BFIN_IRQ(87)    /* Timer 1 Interrupt */
+#define IRQ_TIMER2      BFIN_IRQ(88)    /* Timer 2 Interrupt */
+#define IRQ_TIMER3      BFIN_IRQ(89)    /* Timer 3 Interrupt */
+#define IRQ_TIMER4      BFIN_IRQ(90)    /* Timer 4 Interrupt */
+#define IRQ_TIMER5      BFIN_IRQ(91)    /* Timer 5 Interrupt */
+#define IRQ_TIMER6      BFIN_IRQ(92)    /* Timer 6 Interrupt */
+#define IRQ_TIMER7      BFIN_IRQ(93)    /* Timer 7 Interrupt */
+#define IRQ_PINT2       BFIN_IRQ(94)    /* PINT2 Interrupt */
+#define IRQ_PINT3       BFIN_IRQ(95)    /* PINT3 Interrupt */
+
+#define SYS_IRQS        IRQ_PINT3
+
+#define BFIN_PA_IRQ(x)  ((x) + SYS_IRQS + 1)
+#define IRQ_PA0         BFIN_PA_IRQ(0)
+#define IRQ_PA1         BFIN_PA_IRQ(1)
+#define IRQ_PA2         BFIN_PA_IRQ(2)
+#define IRQ_PA3         BFIN_PA_IRQ(3)
+#define IRQ_PA4         BFIN_PA_IRQ(4)
+#define IRQ_PA5         BFIN_PA_IRQ(5)
+#define IRQ_PA6         BFIN_PA_IRQ(6)
+#define IRQ_PA7         BFIN_PA_IRQ(7)
+#define IRQ_PA8         BFIN_PA_IRQ(8)
+#define IRQ_PA9         BFIN_PA_IRQ(9)
+#define IRQ_PA10        BFIN_PA_IRQ(10)
+#define IRQ_PA11        BFIN_PA_IRQ(11)
+#define IRQ_PA12        BFIN_PA_IRQ(12)
+#define IRQ_PA13        BFIN_PA_IRQ(13)
+#define IRQ_PA14        BFIN_PA_IRQ(14)
+#define IRQ_PA15        BFIN_PA_IRQ(15)
+
+#define BFIN_PB_IRQ(x)  ((x) + IRQ_PA15 + 1)
+#define IRQ_PB0         BFIN_PB_IRQ(0)
+#define IRQ_PB1         BFIN_PB_IRQ(1)
+#define IRQ_PB2         BFIN_PB_IRQ(2)
+#define IRQ_PB3         BFIN_PB_IRQ(3)
+#define IRQ_PB4         BFIN_PB_IRQ(4)
+#define IRQ_PB5         BFIN_PB_IRQ(5)
+#define IRQ_PB6         BFIN_PB_IRQ(6)
+#define IRQ_PB7         BFIN_PB_IRQ(7)
+#define IRQ_PB8         BFIN_PB_IRQ(8)
+#define IRQ_PB9         BFIN_PB_IRQ(9)
+#define IRQ_PB10        BFIN_PB_IRQ(10)
+#define IRQ_PB11        BFIN_PB_IRQ(11)
+#define IRQ_PB12        BFIN_PB_IRQ(12)
+#define IRQ_PB13        BFIN_PB_IRQ(13)
+#define IRQ_PB14        BFIN_PB_IRQ(14)
+#define IRQ_PB15        BFIN_PB_IRQ(15)         /* N/A */
+
+#define BFIN_PC_IRQ(x)  ((x) + IRQ_PB15 + 1)
+#define IRQ_PC0         BFIN_PC_IRQ(0)
+#define IRQ_PC1         BFIN_PC_IRQ(1)
+#define IRQ_PC2         BFIN_PC_IRQ(2)
+#define IRQ_PC3         BFIN_PC_IRQ(3)
+#define IRQ_PC4         BFIN_PC_IRQ(4)
+#define IRQ_PC5         BFIN_PC_IRQ(5)
+#define IRQ_PC6         BFIN_PC_IRQ(6)
+#define IRQ_PC7         BFIN_PC_IRQ(7)
+#define IRQ_PC8         BFIN_PC_IRQ(8)
+#define IRQ_PC9         BFIN_PC_IRQ(9)
+#define IRQ_PC10        BFIN_PC_IRQ(10)
+#define IRQ_PC11        BFIN_PC_IRQ(11)
+#define IRQ_PC12        BFIN_PC_IRQ(12)
+#define IRQ_PC13        BFIN_PC_IRQ(13)
+#define IRQ_PC14        BFIN_PC_IRQ(14)         /* N/A */
+#define IRQ_PC15        BFIN_PC_IRQ(15)         /* N/A */
+
+#define BFIN_PD_IRQ(x)  ((x) + IRQ_PC15 + 1)
+#define IRQ_PD0         BFIN_PD_IRQ(0)
+#define IRQ_PD1         BFIN_PD_IRQ(1)
+#define IRQ_PD2         BFIN_PD_IRQ(2)
+#define IRQ_PD3         BFIN_PD_IRQ(3)
+#define IRQ_PD4         BFIN_PD_IRQ(4)
+#define IRQ_PD5         BFIN_PD_IRQ(5)
+#define IRQ_PD6         BFIN_PD_IRQ(6)
+#define IRQ_PD7         BFIN_PD_IRQ(7)
+#define IRQ_PD8         BFIN_PD_IRQ(8)
+#define IRQ_PD9         BFIN_PD_IRQ(9)
+#define IRQ_PD10        BFIN_PD_IRQ(10)
+#define IRQ_PD11        BFIN_PD_IRQ(11)
+#define IRQ_PD12        BFIN_PD_IRQ(12)
+#define IRQ_PD13        BFIN_PD_IRQ(13)
+#define IRQ_PD14        BFIN_PD_IRQ(14)
+#define IRQ_PD15        BFIN_PD_IRQ(15)
+
+#define BFIN_PE_IRQ(x)  ((x) + IRQ_PD15 + 1)
+#define IRQ_PE0         BFIN_PE_IRQ(0)
+#define IRQ_PE1         BFIN_PE_IRQ(1)
+#define IRQ_PE2         BFIN_PE_IRQ(2)
+#define IRQ_PE3         BFIN_PE_IRQ(3)
+#define IRQ_PE4         BFIN_PE_IRQ(4)
+#define IRQ_PE5         BFIN_PE_IRQ(5)
+#define IRQ_PE6         BFIN_PE_IRQ(6)
+#define IRQ_PE7         BFIN_PE_IRQ(7)
+#define IRQ_PE8         BFIN_PE_IRQ(8)
+#define IRQ_PE9         BFIN_PE_IRQ(9)
+#define IRQ_PE10        BFIN_PE_IRQ(10)
+#define IRQ_PE11        BFIN_PE_IRQ(11)
+#define IRQ_PE12        BFIN_PE_IRQ(12)
+#define IRQ_PE13        BFIN_PE_IRQ(13)
+#define IRQ_PE14        BFIN_PE_IRQ(14)
+#define IRQ_PE15        BFIN_PE_IRQ(15)
+
+#define BFIN_PF_IRQ(x)  ((x) + IRQ_PE15 + 1)
+#define IRQ_PF0         BFIN_PF_IRQ(0)
+#define IRQ_PF1         BFIN_PF_IRQ(1)
+#define IRQ_PF2         BFIN_PF_IRQ(2)
+#define IRQ_PF3         BFIN_PF_IRQ(3)
+#define IRQ_PF4         BFIN_PF_IRQ(4)
+#define IRQ_PF5         BFIN_PF_IRQ(5)
+#define IRQ_PF6         BFIN_PF_IRQ(6)
+#define IRQ_PF7         BFIN_PF_IRQ(7)
+#define IRQ_PF8         BFIN_PF_IRQ(8)
+#define IRQ_PF9         BFIN_PF_IRQ(9)
+#define IRQ_PF10        BFIN_PF_IRQ(10)
+#define IRQ_PF11        BFIN_PF_IRQ(11)
+#define IRQ_PF12        BFIN_PF_IRQ(12)
+#define IRQ_PF13        BFIN_PF_IRQ(13)
+#define IRQ_PF14        BFIN_PF_IRQ(14)
+#define IRQ_PF15        BFIN_PF_IRQ(15)
+
+#define BFIN_PG_IRQ(x)  ((x) + IRQ_PF15 + 1)
+#define IRQ_PG0         BFIN_PG_IRQ(0)
+#define IRQ_PG1         BFIN_PG_IRQ(1)
+#define IRQ_PG2         BFIN_PG_IRQ(2)
+#define IRQ_PG3         BFIN_PG_IRQ(3)
+#define IRQ_PG4         BFIN_PG_IRQ(4)
+#define IRQ_PG5         BFIN_PG_IRQ(5)
+#define IRQ_PG6         BFIN_PG_IRQ(6)
+#define IRQ_PG7         BFIN_PG_IRQ(7)
+#define IRQ_PG8         BFIN_PG_IRQ(8)
+#define IRQ_PG9         BFIN_PG_IRQ(9)
+#define IRQ_PG10        BFIN_PG_IRQ(10)
+#define IRQ_PG11        BFIN_PG_IRQ(11)
+#define IRQ_PG12        BFIN_PG_IRQ(12)
+#define IRQ_PG13        BFIN_PG_IRQ(13)
+#define IRQ_PG14        BFIN_PG_IRQ(14)
+#define IRQ_PG15        BFIN_PG_IRQ(15)
+
+#define BFIN_PH_IRQ(x)  ((x) + IRQ_PG15 + 1)
+#define IRQ_PH0         BFIN_PH_IRQ(0)
+#define IRQ_PH1         BFIN_PH_IRQ(1)
+#define IRQ_PH2         BFIN_PH_IRQ(2)
+#define IRQ_PH3         BFIN_PH_IRQ(3)
+#define IRQ_PH4         BFIN_PH_IRQ(4)
+#define IRQ_PH5         BFIN_PH_IRQ(5)
+#define IRQ_PH6         BFIN_PH_IRQ(6)
+#define IRQ_PH7         BFIN_PH_IRQ(7)
+#define IRQ_PH8         BFIN_PH_IRQ(8)
+#define IRQ_PH9         BFIN_PH_IRQ(9)
+#define IRQ_PH10        BFIN_PH_IRQ(10)
+#define IRQ_PH11        BFIN_PH_IRQ(11)
+#define IRQ_PH12        BFIN_PH_IRQ(12)
+#define IRQ_PH13        BFIN_PH_IRQ(13)
+#define IRQ_PH14        BFIN_PH_IRQ(14)         /* N/A */
+#define IRQ_PH15        BFIN_PH_IRQ(15)         /* N/A */
+
+#define BFIN_PI_IRQ(x)  ((x) + IRQ_PH15 + 1)
+#define IRQ_PI0         BFIN_PI_IRQ(0)
+#define IRQ_PI1         BFIN_PI_IRQ(1)
+#define IRQ_PI2         BFIN_PI_IRQ(2)
+#define IRQ_PI3         BFIN_PI_IRQ(3)
+#define IRQ_PI4         BFIN_PI_IRQ(4)
+#define IRQ_PI5         BFIN_PI_IRQ(5)
+#define IRQ_PI6         BFIN_PI_IRQ(6)
+#define IRQ_PI7         BFIN_PI_IRQ(7)
+#define IRQ_PI8         BFIN_PI_IRQ(8)
+#define IRQ_PI9         BFIN_PI_IRQ(9)
+#define IRQ_PI10        BFIN_PI_IRQ(10)
+#define IRQ_PI11        BFIN_PI_IRQ(11)
+#define IRQ_PI12        BFIN_PI_IRQ(12)
+#define IRQ_PI13        BFIN_PI_IRQ(13)
+#define IRQ_PI14        BFIN_PI_IRQ(14)
+#define IRQ_PI15        BFIN_PI_IRQ(15)
+
+#define BFIN_PJ_IRQ(x)  ((x) + IRQ_PI15 + 1)
+#define IRQ_PJ0         BFIN_PJ_IRQ(0)
+#define IRQ_PJ1         BFIN_PJ_IRQ(1)
+#define IRQ_PJ2         BFIN_PJ_IRQ(2)
+#define IRQ_PJ3         BFIN_PJ_IRQ(3)
+#define IRQ_PJ4         BFIN_PJ_IRQ(4)
+#define IRQ_PJ5         BFIN_PJ_IRQ(5)
+#define IRQ_PJ6         BFIN_PJ_IRQ(6)
+#define IRQ_PJ7         BFIN_PJ_IRQ(7)
+#define IRQ_PJ8         BFIN_PJ_IRQ(8)
+#define IRQ_PJ9         BFIN_PJ_IRQ(9)
+#define IRQ_PJ10        BFIN_PJ_IRQ(10)
+#define IRQ_PJ11        BFIN_PJ_IRQ(11)
+#define IRQ_PJ12        BFIN_PJ_IRQ(12)
+#define IRQ_PJ13        BFIN_PJ_IRQ(13)
+#define IRQ_PJ14        BFIN_PJ_IRQ(14)         /* N/A */
+#define IRQ_PJ15        BFIN_PJ_IRQ(15)         /* N/A */
+
+#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+#define NR_IRQS     (IRQ_PJ15+1)
+#else
+#define NR_IRQS     (SYS_IRQS+1)
+#endif
+
+#define IVG7            7
+#define IVG8            8
+#define IVG9            9
+#define IVG10           10
+#define IVG11           11
+#define IVG12           12
+#define IVG13           13
+#define IVG14           14
+#define IVG15           15
+
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS      0
+#define IRQ_DMAC0_ERR_POS       4
+#define IRQ_EPPI0_ERR_POS       8
+#define IRQ_SPORT0_ERR_POS      12
+#define IRQ_SPORT1_ERR_POS      16
+#define IRQ_SPI0_ERR_POS        20
+#define IRQ_UART0_ERR_POS       24
+#define IRQ_RTC_POS             28
+
+/* IAR1 BIT FIELDS */
+#define IRQ_EPPI0_POS           0
+#define IRQ_SPORT0_RX_POS       4
+#define IRQ_SPORT0_TX_POS       8
+#define IRQ_SPORT1_RX_POS       12
+#define IRQ_SPORT1_TX_POS       16
+#define IRQ_SPI0_POS            20
+#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_TX_POS        28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_TIMER8_POS          0
+#define IRQ_TIMER9_POS          4
+#define IRQ_TIMER10_POS         8
+#define IRQ_PINT0_POS           12
+#define IRQ_PINT1_POS           16
+#define IRQ_MDMAS0_POS          20
+#define IRQ_MDMAS1_POS          24
+#define IRQ_WATCHDOG_POS        28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_DMAC1_ERR_POS       0
+#define IRQ_SPORT2_ERR_POS      4
+#define IRQ_SPORT3_ERR_POS      8
+#define IRQ_MXVR_DATA_POS       12
+#define IRQ_SPI1_ERR_POS        16
+#define IRQ_SPI2_ERR_POS        20
+#define IRQ_UART1_ERR_POS       24
+#define IRQ_UART2_ERR_POS       28
+
+/* IAR4 BIT FILEDS */
+#define IRQ_CAN0_ERR_POS        0
+#define IRQ_SPORT2_RX_POS       4
+#define IRQ_SPORT2_TX_POS       8
+#define IRQ_SPORT3_RX_POS       12
+#define IRQ_SPORT3_TX_POS       16
+#define IRQ_EPPI1_POS           20
+#define IRQ_EPPI2_POS           24
+#define IRQ_SPI1_POS            28
+
+/* IAR5 BIT FIELDS */
+#define IRQ_SPI2_POS            0
+#define IRQ_UART1_RX_POS        4
+#define IRQ_UART1_TX_POS        8
+#define IRQ_ATAPI_RX_POS        12
+#define IRQ_ATAPI_TX_POS        16
+#define IRQ_TWI0_POS            20
+#define IRQ_TWI1_POS            24
+#define IRQ_CAN0_RX_POS         28
+
+/* IAR6 BIT FIELDS */
+#define IRQ_CAN0_TX_POS         0
+#define IRQ_MDMAS2_POS          4
+#define IRQ_MDMAS3_POS          8
+#define IRQ_MXVR_ERR_POS        12
+#define IRQ_MXVR_MSG_POS        16
+#define IRQ_MXVR_PKT_POS        20
+#define IRQ_EPPI1_ERR_POS       24
+#define IRQ_EPPI2_ERR_POS       28
+
+/* IAR7 BIT FIELDS */
+#define IRQ_UART3_ERR_POS       0
+#define IRQ_HOST_ERR_POS        4
+#define IRQ_PIXC_ERR_POS        12
+#define IRQ_NFC_ERR_POS         16
+#define IRQ_ATAPI_ERR_POS       20
+#define IRQ_CAN1_ERR_POS        24
+#define IRQ_HS_DMA_ERR_POS      28
+
+/* IAR8 BIT FIELDS */
+#define IRQ_PIXC_IN0_POS        0
+#define IRQ_PIXC_IN1_POS        4
+#define IRQ_PIXC_OUT_POS        8
+#define IRQ_SDH_POS             12
+#define IRQ_CNT_POS             16
+#define IRQ_KEY_POS             20
+#define IRQ_CAN1_RX_POS         24
+#define IRQ_CAN1_TX_POS         28
+
+/* IAR9 BIT FIELDS */
+#define IRQ_SDH_MASK0_POS       0
+#define IRQ_SDH_MASK1_POS       4
+#define IRQ_USB_INT0_POS        12
+#define IRQ_USB_INT1_POS        16
+#define IRQ_USB_INT2_POS        20
+#define IRQ_USB_DMA_POS         24
+#define IRQ_OTPSEC_POS          28
+
+/* IAR10 BIT FIELDS */
+#define IRQ_TIMER0_POS          24
+#define IRQ_TIMER1_POS          28
+
+/* IAR11 BIT FIELDS */
+#define IRQ_TIMER2_POS          0
+#define IRQ_TIMER3_POS          4
+#define IRQ_TIMER4_POS          8
+#define IRQ_TIMER5_POS          12
+#define IRQ_TIMER6_POS          16
+#define IRQ_TIMER7_POS          20
+#define IRQ_PINT2_POS           24
+#define IRQ_PINT3_POS           28
+
+#endif /* _BF548_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
new file mode 100644
index 000000000000..0cb279e973d7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -0,0 +1,189 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/mem_init.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#if (CONFIG_MEM_MT46V32M16)
+
+#if defined CONFIG_CLKIN_HALF
+#define CLKIN_HALF       1
+#else
+#define CLKIN_HALF       0
+#endif
+
+#if defined CONFIG_PLL_BYPASS
+#define PLL_BYPASS      1
+#else
+#define PLL_BYPASS       0
+#endif
+
+/***************************************Currently Not Being Used *********************************/
+#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
+#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0  \
+        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
+         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
new file mode 100644
index 000000000000..72d80e8a6e81
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -0,0 +1,97 @@
+/*
+ * file:         include/asm-blackfin/mach-bf548/mem_map.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
+ * rev:
+ *
+ * modified:
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _MEM_MAP_548_H_
+#define _MEM_MAP_548_H_
+
+#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
+#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
+
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+
+/* Level 1 Memory */
+
+/* Memory Map for ADSP-BF548 processors */
+#ifdef CONFIG_BLKFIN_ICACHE
+#define BLKFIN_ICACHESIZE       (16*1024)
+#else
+#define BLKFIN_ICACHESIZE       (0*1024)
+#endif
+
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+
+#define L1_CODE_LENGTH      0xC000
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+
+/* Scratch Pad Memory */
+
+#if defined(CONFIG_BF54x)
+#define L1_SCRATCH_START        0xFFB00000
+#define L1_SCRATCH_LENGTH       0x1000
+#endif
+
+#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
new file mode 100644
index 000000000000..b382deb501a7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -0,0 +1,270 @@
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define P_SPORT2_TFS    (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
+#define P_SPORT2_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
+#define P_SPORT2_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
+#define P_SPORT2_TSCLK  (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
+#define P_SPORT2_RFS    (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
+#define P_SPORT2_DRSEC  (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
+#define P_SPORT2_DRPRI  (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
+#define P_SPORT2_RSCLK  (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
+#define P_SPORT3_TFS    (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
+#define P_SPORT3_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
+#define P_SPORT3_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
+#define P_SPORT3_TSCLK  (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
+#define P_SPORT3_RFS    (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
+#define P_SPORT3_DRSEC  (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
+#define P_SPORT3_DRPRI  (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
+#define P_SPORT3_RSCLK  (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
+#define P_TMR4  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
+#define P_TMR5  (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
+#define P_TMR6  (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
+#define P_TMR7  (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
+
+#define P_TWI1_SCL      (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
+#define P_TWI1_SDA      (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
+#define P_UART3_RTS     (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
+#define P_UART3_CTS     (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
+#define P_UART2_TX      (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
+#define P_UART2_RX      (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
+#define P_UART3_TX      (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
+#define P_UART3_RX      (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
+#define P_SPI2_SS       (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
+#define P_SPI2_SSEL1    (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
+#define P_SPI2_SSEL2    (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
+#define P_SPI2_SSEL3    (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
+#define P_SPI2_SCK      (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
+#define P_SPI2_MOSI     (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
+#define P_SPI2_MISO     (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+#define P_TMR0  (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
+#define P_TMR1  (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
+#define P_TMR2  (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
+#define P_TMR3  (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
+
+#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
+#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
+#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
+#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
+#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
+#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
+#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
+#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
+#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
+#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
+#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
+#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
+#define P_SD_CLK        (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
+#define P_SD_CMD        (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
+#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
+#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
+
+#define P_PPI1_D0       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
+#define P_PPI1_D1       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
+#define P_PPI1_D2       (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
+#define P_PPI1_D3       (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
+#define P_PPI1_D4       (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
+#define P_PPI1_D5       (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
+#define P_PPI1_D6       (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
+#define P_PPI1_D7       (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
+#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
+#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
+#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
+#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
+#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
+#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
+#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
+#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
+
+#define P_HOST_D8       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
+#define P_HOST_D9       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
+#define P_HOST_D10      (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
+#define P_HOST_D11      (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
+#define P_HOST_D12      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
+#define P_HOST_D13      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
+#define P_HOST_D14      (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
+#define P_HOST_D15      (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
+#define P_HOST_D0       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
+#define P_HOST_D1       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
+#define P_HOST_D2       (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
+#define P_HOST_D3       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
+#define P_HOST_D4       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
+#define P_HOST_D5       (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
+#define P_HOST_D6       (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
+#define P_HOST_D7       (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
+#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
+#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
+#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
+#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
+#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
+#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
+#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
+#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
+#define P_PPI2_D0       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
+#define P_PPI2_D1       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
+#define P_PPI2_D2       (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
+#define P_PPI2_D3       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
+#define P_PPI2_D4       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
+#define P_PPI2_D5       (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
+#define P_PPI2_D6       (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
+#define P_PPI2_D7       (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_PPI0_D18      (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
+#define P_PPI0_D19      (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
+#define P_PPI0_D20      (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
+#define P_PPI0_D21      (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
+#define P_PPI0_D22      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
+#define P_PPI0_D23      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
+#define P_KEY_ROW0      (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
+#define P_KEY_ROW1      (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
+#define P_KEY_ROW2      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
+#define P_KEY_ROW3      (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
+#define P_KEY_COL0      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
+#define P_KEY_COL1      (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
+#define P_KEY_COL2      (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
+#define P_KEY_COL3      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
+
+#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
+#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
+#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
+#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
+#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
+#define P_UART1_RTS     (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
+#define P_UART1_CTS     (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
+#define P_PPI1_CLK      (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
+#define P_PPI1_FS1      (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
+#define P_PPI1_FS2      (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
+#define P_TWI0_SCL      (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
+#define P_TWI0_SDA      (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
+#define P_KEY_COL7      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
+#define P_KEY_ROW6      (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
+#define P_KEY_COL6      (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
+#define P_KEY_ROW5      (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
+#define P_KEY_COL5      (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
+#define P_KEY_ROW4      (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
+#define P_KEY_COL4      (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
+#define P_KEY_ROW7      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
+
+#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+#define P_ATAPI_D0A     (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_ATAPI_D1A     (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_ATAPI_D2A     (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_ATAPI_D3A     (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_ATAPI_D4A     (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_ATAPI_D5A     (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_ATAPI_D6A     (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_ATAPI_D7A     (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_ATAPI_D8A     (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_ATAPI_D9A     (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_ATAPI_D10A    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_ATAPI_D11A    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_ATAPI_D12A    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_ATAPI_D13A    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_ATAPI_D14A    (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_ATAPI_D15A    (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+
+#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_PPI0_D16      (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_PPI0_D17      (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_SPI1_SSEL2    (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_SPI1_SSEL3    (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_CAN0_TX       (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_CAN0_RX       (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_CAN1_TX       (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_CAN1_RX       (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_ATAPI_A0A     (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
+#define P_ATAPI_A1A     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
+#define P_ATAPI_A2A     (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_HOST_CE       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_HOST_RD       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_HOST_WR       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_MTXONB        (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_PPI2_FS2      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
+#define P_PPI2_FS1      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+#define P_PPI2_CLK      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#define P_CNT_CZM       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
+
+#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_ATAPI_RESET   (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_HOST_ADDR     (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_HOST_ACK      (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_MTX   (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_MRX   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_MRXONB        (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+#define P_A4    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
+#define P_A5    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
+#define P_A6    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
+#define P_A7    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
+#define P_A8    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
+#define P_A9    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
+#define P_PPI1_FS3      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_PPI2_FS3      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
+#define P_TMR8  (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
+#define P_TMR9  (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
+#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
+#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
+#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
+#define P_CNT_CDG       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
+#define P_CNT_CUD       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
+
+#define P_A10   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
+#define P_A11   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
+#define P_A12   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
+#define P_A13   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
+#define P_A14   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
+#define P_A15   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
+#define P_A16   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
+#define P_A17   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
+#define P_A18   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
+#define P_A19   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
+#define P_A20   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
+#define P_A21   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
+#define P_A22   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
+#define P_A23   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
+#define P_A24   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
+#define P_A25   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
+#define P_NOR_CLK       (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
+
+#define P_AMC_ARDY_NOR_WAIT     (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
+#define P_NAND_CE       (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
+#define P_NAND_RB       (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
+#define P_ATAPI_DIOR    (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
+#define P_ATAPI_DIOW    (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
+#define P_ATAPI_CS0     (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
+#define P_ATAPI_CS1     (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
+#define P_ATAPI_DMACK   (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
+#define P_ATAPI_DMARQ   (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
+#define P_ATAPI_INTRQ   (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
+#define P_ATAPI_IORDY   (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
+#define P_AMC_BR        (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
+#define P_AMC_BG        (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
+#define P_AMC_BGH       (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index b14f872e5703..1a8ec9e46922 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -57,12 +57,14 @@
 /* Writing to VR_CTL initiates a PLL relock sequence. */
 static __inline__ void bfin_write_VR_CTL(unsigned int val)
 {
-        unsigned long flags, iwr;
+        unsigned long flags, iwr0, iwr1;
 
         /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SICA_IWR0);
+        iwr0 = bfin_read32(SICA_IWR0);
+        iwr1 = bfin_read32(SICA_IWR1);
         /* Only allow PPL Wakeup) */
         bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+        bfin_write32(SICA_IWR1, 0);
 
         bfin_write16(VR_CTL, val);
         __builtin_bfin_ssync();
@@ -70,7 +72,8 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
         local_irq_save(flags);
         asm("IDLE;");
         local_irq_restore(flags);
-        bfin_write32(SICA_IWR0, iwr);
+        bfin_write32(SICA_IWR0, iwr0);
+        bfin_write32(SICA_IWR1, iwr1);
 }
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
index 21d982003e75..766334b7d8ab 100644
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -32,4 +32,7 @@
 #define CH_IMEM_STREAM1_SRC     34
 #define CH_IMEM_STREAM1_DEST    35
 
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+
 #endif
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
new file mode 100644
index 000000000000..10d11d5ffe23
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -0,0 +1,87 @@
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define P_PPI0_CLK      (P_DONTCARE)
+#define P_PPI0_FS1      (P_DONTCARE)
+#define P_PPI0_FS2      (P_DONTCARE)
+#define P_PPI0_FS3      (P_DONTCARE)
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF47))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF46))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF45))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF44))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF43))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF42))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF41))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF40))
+#define P_PPI0_D0       (P_DONTCARE)
+#define P_PPI0_D1       (P_DONTCARE)
+#define P_PPI0_D2       (P_DONTCARE)
+#define P_PPI0_D3       (P_DONTCARE)
+#define P_PPI0_D4       (P_DONTCARE)
+#define P_PPI0_D5       (P_DONTCARE)
+#define P_PPI0_D6       (P_DONTCARE)
+#define P_PPI0_D7       (P_DONTCARE)
+#define P_PPI1_CLK      (P_DONTCARE)
+#define P_PPI1_FS1      (P_DONTCARE)
+#define P_PPI1_FS2      (P_DONTCARE)
+#define P_PPI1_FS3      (P_DONTCARE)
+#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PF39))
+#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PF38))
+#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PF37))
+#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PF36))
+#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PF35))
+#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PF34))
+#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PF33))
+#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PF32))
+#define P_PPI1_D0       (P_DONTCARE)
+#define P_PPI1_D1       (P_DONTCARE)
+#define P_PPI1_D2       (P_DONTCARE)
+#define P_PPI1_D3       (P_DONTCARE)
+#define P_PPI1_D4       (P_DONTCARE)
+#define P_PPI1_D5       (P_DONTCARE)
+#define P_PPI1_D6       (P_DONTCARE)
+#define P_PPI1_D7       (P_DONTCARE)
+#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF31))
+#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF30))
+#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF29))
+#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF28))
+#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF27))
+#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF26))
+#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF25))
+#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PF24))
+#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF23))
+#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF22))
+#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PF21))
+#define P_SPORT1_DRPRI  (P_DONTCARE)
+#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF20))
+#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PF19))
+#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF18))
+#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF17))
+#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PF16))
+#define P_SPORT0_DRPRI  (P_DONTCARE)
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15))
+#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
+#define P_TMR11         (P_DONTCARE)
+#define P_TMR10         (P_DONTCARE)
+#define P_TMR9          (P_DONTCARE)
+#define P_TMR8          (P_DONTCARE)
+#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF0))
+#define P_SPI0_MOSI     (P_DONTCARE)
+#define P_SPI0_MIS0     (P_DONTCARE)
+#define P_SPI0_SCK      (P_DONTCARE)
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 58f878947cbc..94ed381e5606 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -40,16 +40,7 @@
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
 #ifdef ANOMALY_05000125
-static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        local_irq_save(flags);
-        __asm__(".align 8\n");
-        bfin_write32(IMEM_CONTROL, val);
-        __builtin_bfin_ssync();
-        local_irq_restore(flags);
-}
+extern void bfin_write_DMEM_CONTROL(unsigned int val);
 #else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
 #endif
@@ -139,17 +130,7 @@ static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
 #ifdef ANOMALY_05000125
-static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        local_irq_save(flags);
-        __asm__(".align 8\n");
-        bfin_write32(IMEM_CONTROL, val);
-        __builtin_bfin_ssync();
-        local_irq_restore(flags);
-
-}
+extern void bfin_write_IMEM_CONTROL(unsigned int val);
 #else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
 #endif
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
index 4d504f908c0c..b58f5ad3f024 100644
--- a/include/asm-blackfin/mman.h
+++ b/include/asm-blackfin/mman.h
@@ -22,8 +22,6 @@
 #define MAP_NORESERVE   0x4000  /* don't check for reservations */
 #define MAP_POPULATE    0x8000  /* populate (prefault) pagetables */
 #define MAP_NONBLOCK    0x10000 /* do not block on IO */
-#define MAP_UNINITIALIZE 0x4000000  /* For anonymous mmap, memory could
-                                    be uninitialized. */
 
 #define MS_ASYNC        1       /* sync memory asynchronously */
 #define MS_INVALIDATE   2       /* invalidate the caches */
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
index ffad947f1b2a..8bc86717021c 100644
--- a/include/asm-blackfin/page.h
+++ b/include/asm-blackfin/page.h
@@ -4,7 +4,11 @@
 /* PAGE_SHIFT determines the page size */
 
 #define PAGE_SHIFT      12
+#ifdef __ASSEMBLY__
+#define PAGE_SIZE       (1 << PAGE_SHIFT)
+#else
 #define PAGE_SIZE       (1UL << PAGE_SHIFT)
+#endif
 #define PAGE_MASK       (~(PAGE_SIZE-1))
 
 #ifdef __KERNEL__
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
new file mode 100644
index 000000000000..9d3681e42111
--- /dev/null
+++ b/include/asm-blackfin/portmux.h
@@ -0,0 +1,1133 @@
+/*
+ * Common header file for blackfin family of processors.
+ *
+ */
+
+#ifndef _PORTMUX_H_
+#define _PORTMUX_H_
+
+#define P_IDENT(x)      ((x) & 0x1FF)
+#define P_FUNCT(x)      (((x) & 0x3) << 9)
+#define P_FUNCT2MUX(x)  (((x) >> 9) & 0x3)
+#define P_DEFINED       0x8000
+#define P_UNDEF         0x4000
+#define P_MAYSHARE      0x2000
+#define P_DONTCARE      0x1000
+
+#include <asm/gpio.h>
+#include <asm/mach/portmux.h>
+
+#ifndef P_SPORT2_TFS
+#define P_SPORT2_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DTSEC
+#define P_SPORT2_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DTPRI
+#define P_SPORT2_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT2_TSCLK
+#define P_SPORT2_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT2_RFS
+#define P_SPORT2_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DRSEC
+#define P_SPORT2_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DRPRI
+#define P_SPORT2_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT2_RSCLK
+#define P_SPORT2_RSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT3_TFS
+#define P_SPORT3_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DTSEC
+#define P_SPORT3_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DTPRI
+#define P_SPORT3_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT3_TSCLK
+#define P_SPORT3_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT3_RFS
+#define P_SPORT3_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DRSEC
+#define P_SPORT3_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DRPRI
+#define P_SPORT3_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT3_RSCLK
+#define P_SPORT3_RSCLK P_UNDEF
+#endif
+
+#ifndef P_TMR4
+#define P_TMR4 P_UNDEF
+#endif
+
+#ifndef P_TMR5
+#define P_TMR5 P_UNDEF
+#endif
+
+#ifndef P_TMR6
+#define P_TMR6 P_UNDEF
+#endif
+
+#ifndef P_TMR7
+#define P_TMR7 P_UNDEF
+#endif
+
+#ifndef P_TWI1_SCL
+#define P_TWI1_SCL P_UNDEF
+#endif
+
+#ifndef P_TWI1_SDA
+#define P_TWI1_SDA P_UNDEF
+#endif
+
+#ifndef P_UART3_RTS
+#define P_UART3_RTS P_UNDEF
+#endif
+
+#ifndef P_UART3_CTS
+#define P_UART3_CTS P_UNDEF
+#endif
+
+#ifndef P_UART2_TX
+#define P_UART2_TX P_UNDEF
+#endif
+
+#ifndef P_UART2_RX
+#define P_UART2_RX P_UNDEF
+#endif
+
+#ifndef P_UART3_TX
+#define P_UART3_TX P_UNDEF
+#endif
+
+#ifndef P_UART3_RX
+#define P_UART3_RX P_UNDEF
+#endif
+
+#ifndef P_SPI2_SS
+#define P_SPI2_SS P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL1
+#define P_SPI2_SSEL1 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL2
+#define P_SPI2_SSEL2 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL3
+#define P_SPI2_SSEL3 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SCK
+#define P_SPI2_SCK P_UNDEF
+#endif
+
+#ifndef P_SPI2_MOSI
+#define P_SPI2_MOSI P_UNDEF
+#endif
+
+#ifndef P_SPI2_MISO
+#define P_SPI2_MISO P_UNDEF
+#endif
+
+#ifndef P_TMR0
+#define P_TMR0 P_UNDEF
+#endif
+
+#ifndef P_TMR1
+#define P_TMR1 P_UNDEF
+#endif
+
+#ifndef P_TMR2
+#define P_TMR2 P_UNDEF
+#endif
+
+#ifndef P_TMR3
+#define P_TMR3 P_UNDEF
+#endif
+
+#ifndef P_SPORT0_TFS
+#define P_SPORT0_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DTSEC
+#define P_SPORT0_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DTPRI
+#define P_SPORT0_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT0_TSCLK
+#define P_SPORT0_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT0_RFS
+#define P_SPORT0_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DRSEC
+#define P_SPORT0_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DRPRI
+#define P_SPORT0_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT0_RSCLK
+#define P_SPORT0_RSCLK P_UNDEF
+#endif
+
+#ifndef P_SD_D0
+#define P_SD_D0 P_UNDEF
+#endif
+
+#ifndef P_SD_D1
+#define P_SD_D1 P_UNDEF
+#endif
+
+#ifndef P_SD_D2
+#define P_SD_D2 P_UNDEF
+#endif
+
+#ifndef P_SD_D3
+#define P_SD_D3 P_UNDEF
+#endif
+
+#ifndef P_SD_CLK
+#define P_SD_CLK P_UNDEF
+#endif
+
+#ifndef P_SD_CMD
+#define P_SD_CMD P_UNDEF
+#endif
+
+#ifndef P_MMCLK
+#define P_MMCLK P_UNDEF
+#endif
+
+#ifndef P_MBCLK
+#define P_MBCLK P_UNDEF
+#endif
+
+#ifndef P_PPI1_D0
+#define P_PPI1_D0 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D1
+#define P_PPI1_D1 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D2
+#define P_PPI1_D2 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D3
+#define P_PPI1_D3 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D4
+#define P_PPI1_D4 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D5
+#define P_PPI1_D5 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D6
+#define P_PPI1_D6 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D7
+#define P_PPI1_D7 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D8
+#define P_PPI1_D8 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D9
+#define P_PPI1_D9 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D10
+#define P_PPI1_D10 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D11
+#define P_PPI1_D11 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D12
+#define P_PPI1_D12 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D13
+#define P_PPI1_D13 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D14
+#define P_PPI1_D14 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D15
+#define P_PPI1_D15 P_UNDEF
+#endif
+
+#ifndef P_HOST_D8
+#define P_HOST_D8 P_UNDEF
+#endif
+
+#ifndef P_HOST_D9
+#define P_HOST_D9 P_UNDEF
+#endif
+
+#ifndef P_HOST_D10
+#define P_HOST_D10 P_UNDEF
+#endif
+
+#ifndef P_HOST_D11
+#define P_HOST_D11 P_UNDEF
+#endif
+
+#ifndef P_HOST_D12
+#define P_HOST_D12 P_UNDEF
+#endif
+
+#ifndef P_HOST_D13
+#define P_HOST_D13 P_UNDEF
+#endif
+
+#ifndef P_HOST_D14
+#define P_HOST_D14 P_UNDEF
+#endif
+
+#ifndef P_HOST_D15
+#define P_HOST_D15 P_UNDEF
+#endif
+
+#ifndef P_HOST_D0
+#define P_HOST_D0 P_UNDEF
+#endif
+
+#ifndef P_HOST_D1
+#define P_HOST_D1 P_UNDEF
+#endif
+
+#ifndef P_HOST_D2
+#define P_HOST_D2 P_UNDEF
+#endif
+
+#ifndef P_HOST_D3
+#define P_HOST_D3 P_UNDEF
+#endif
+
+#ifndef P_HOST_D4
+#define P_HOST_D4 P_UNDEF
+#endif
+
+#ifndef P_HOST_D5
+#define P_HOST_D5 P_UNDEF
+#endif
+
+#ifndef P_HOST_D6
+#define P_HOST_D6 P_UNDEF
+#endif
+
+#ifndef P_HOST_D7
+#define P_HOST_D7 P_UNDEF
+#endif
+
+#ifndef P_SPORT1_TFS
+#define P_SPORT1_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DTSEC
+#define P_SPORT1_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DTPRI
+#define P_SPORT1_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT1_TSCLK
+#define P_SPORT1_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT1_RFS
+#define P_SPORT1_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DRSEC
+#define P_SPORT1_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DRPRI
+#define P_SPORT1_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT1_RSCLK
+#define P_SPORT1_RSCLK P_UNDEF
+#endif
+
+#ifndef P_PPI2_D0
+#define P_PPI2_D0 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D1
+#define P_PPI2_D1 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D2
+#define P_PPI2_D2 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D3
+#define P_PPI2_D3 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D4
+#define P_PPI2_D4 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D5
+#define P_PPI2_D5 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D6
+#define P_PPI2_D6 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D7
+#define P_PPI2_D7 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D18
+#define P_PPI0_D18 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D19
+#define P_PPI0_D19 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D20
+#define P_PPI0_D20 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D21
+#define P_PPI0_D21 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D22
+#define P_PPI0_D22 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D23
+#define P_PPI0_D23 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW0
+#define P_KEY_ROW0 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW1
+#define P_KEY_ROW1 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW2
+#define P_KEY_ROW2 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW3
+#define P_KEY_ROW3 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL0
+#define P_KEY_COL0 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL1
+#define P_KEY_COL1 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL2
+#define P_KEY_COL2 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL3
+#define P_KEY_COL3 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SCK
+#define P_SPI0_SCK P_UNDEF
+#endif
+
+#ifndef P_SPI0_MISO
+#define P_SPI0_MISO P_UNDEF
+#endif
+
+#ifndef P_SPI0_MOSI
+#define P_SPI0_MOSI P_UNDEF
+#endif
+
+#ifndef P_SPI0_SS
+#define P_SPI0_SS P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL1
+#define P_SPI0_SSEL1 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL2
+#define P_SPI0_SSEL2 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL3
+#define P_SPI0_SSEL3 P_UNDEF
+#endif
+
+#ifndef P_UART0_TX
+#define P_UART0_TX P_UNDEF
+#endif
+
+#ifndef P_UART0_RX
+#define P_UART0_RX P_UNDEF
+#endif
+
+#ifndef P_UART1_RTS
+#define P_UART1_RTS P_UNDEF
+#endif
+
+#ifndef P_UART1_CTS
+#define P_UART1_CTS P_UNDEF
+#endif
+
+#ifndef P_PPI1_CLK
+#define P_PPI1_CLK P_UNDEF
+#endif
+
+#ifndef P_PPI1_FS1
+#define P_PPI1_FS1 P_UNDEF
+#endif
+
+#ifndef P_PPI1_FS2
+#define P_PPI1_FS2 P_UNDEF
+#endif
+
+#ifndef P_TWI0_SCL
+#define P_TWI0_SCL P_UNDEF
+#endif
+
+#ifndef P_TWI0_SDA
+#define P_TWI0_SDA P_UNDEF
+#endif
+
+#ifndef P_KEY_COL7
+#define P_KEY_COL7 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW6
+#define P_KEY_ROW6 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL6
+#define P_KEY_COL6 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW5
+#define P_KEY_ROW5 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL5
+#define P_KEY_COL5 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW4
+#define P_KEY_ROW4 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL4
+#define P_KEY_COL4 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW7
+#define P_KEY_ROW7 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D0
+#define P_PPI0_D0 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D1
+#define P_PPI0_D1 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D2
+#define P_PPI0_D2 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D3
+#define P_PPI0_D3 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D4
+#define P_PPI0_D4 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D5
+#define P_PPI0_D5 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D6
+#define P_PPI0_D6 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D7
+#define P_PPI0_D7 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D8
+#define P_PPI0_D8 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D9
+#define P_PPI0_D9 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D10
+#define P_PPI0_D10 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D11
+#define P_PPI0_D11 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D12
+#define P_PPI0_D12 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D13
+#define P_PPI0_D13 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D14
+#define P_PPI0_D14 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D15
+#define P_PPI0_D15 P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D0A
+#define P_ATAPI_D0A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D1A
+#define P_ATAPI_D1A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D2A
+#define P_ATAPI_D2A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D3A
+#define P_ATAPI_D3A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D4A
+#define P_ATAPI_D4A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D5A
+#define P_ATAPI_D5A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D6A
+#define P_ATAPI_D6A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D7A
+#define P_ATAPI_D7A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D8A
+#define P_ATAPI_D8A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D9A
+#define P_ATAPI_D9A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D10A
+#define P_ATAPI_D10A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D11A
+#define P_ATAPI_D11A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D12A
+#define P_ATAPI_D12A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D13A
+#define P_ATAPI_D13A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D14A
+#define P_ATAPI_D14A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D15A
+#define P_ATAPI_D15A P_UNDEF
+#endif
+
+#ifndef P_PPI0_CLK
+#define P_PPI0_CLK P_UNDEF
+#endif
+
+#ifndef P_PPI0_FS1
+#define P_PPI0_FS1 P_UNDEF
+#endif
+
+#ifndef P_PPI0_FS2
+#define P_PPI0_FS2 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D16
+#define P_PPI0_D16 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D17
+#define P_PPI0_D17 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL1
+#define P_SPI1_SSEL1 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL2
+#define P_SPI1_SSEL2 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL3
+#define P_SPI1_SSEL3 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SCK
+#define P_SPI1_SCK P_UNDEF
+#endif
+
+#ifndef P_SPI1_MISO
+#define P_SPI1_MISO P_UNDEF
+#endif
+
+#ifndef P_SPI1_MOSI
+#define P_SPI1_MOSI P_UNDEF
+#endif
+
+#ifndef P_SPI1_SS
+#define P_SPI1_SS P_UNDEF
+#endif
+
+#ifndef P_CAN0_TX
+#define P_CAN0_TX P_UNDEF
+#endif
+
+#ifndef P_CAN0_RX
+#define P_CAN0_RX P_UNDEF
+#endif
+
+#ifndef P_CAN1_TX
+#define P_CAN1_TX P_UNDEF
+#endif
+
+#ifndef P_CAN1_RX
+#define P_CAN1_RX P_UNDEF
+#endif
+
+#ifndef P_ATAPI_A0A
+#define P_ATAPI_A0A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_A1A
+#define P_ATAPI_A1A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_A2A
+#define P_ATAPI_A2A P_UNDEF
+#endif
+
+#ifndef P_HOST_CE
+#define P_HOST_CE P_UNDEF
+#endif
+
+#ifndef P_HOST_RD
+#define P_HOST_RD P_UNDEF
+#endif
+
+#ifndef P_HOST_WR
+#define P_HOST_WR P_UNDEF
+#endif
+
+#ifndef P_MTXONB
+#define P_MTXONB P_UNDEF
+#endif
+
+#ifndef P_PPI2_FS2
+#define P_PPI2_FS2 P_UNDEF
+#endif
+
+#ifndef P_PPI2_FS1
+#define P_PPI2_FS1 P_UNDEF
+#endif
+
+#ifndef P_PPI2_CLK
+#define P_PPI2_CLK P_UNDEF
+#endif
+
+#ifndef P_CNT_CZM
+#define P_CNT_CZM P_UNDEF
+#endif
+
+#ifndef P_UART1_TX
+#define P_UART1_TX P_UNDEF
+#endif
+
+#ifndef P_UART1_RX
+#define P_UART1_RX P_UNDEF
+#endif
+
+#ifndef P_ATAPI_RESET
+#define P_ATAPI_RESET P_UNDEF
+#endif
+
+#ifndef P_HOST_ADDR
+#define P_HOST_ADDR P_UNDEF
+#endif
+
+#ifndef P_HOST_ACK
+#define P_HOST_ACK P_UNDEF
+#endif
+
+#ifndef P_MTX
+#define P_MTX P_UNDEF
+#endif
+
+#ifndef P_MRX
+#define P_MRX P_UNDEF
+#endif
+
+#ifndef P_MRXONB
+#define P_MRXONB P_UNDEF
+#endif
+
+#ifndef P_A4
+#define P_A4 P_UNDEF
+#endif
+
+#ifndef P_A5
+#define P_A5 P_UNDEF
+#endif
+
+#ifndef P_A6
+#define P_A6 P_UNDEF
+#endif
+
+#ifndef P_A7
+#define P_A7 P_UNDEF
+#endif
+
+#ifndef P_A8
+#define P_A8 P_UNDEF
+#endif
+
+#ifndef P_A9
+#define P_A9 P_UNDEF
+#endif
+
+#ifndef P_PPI1_FS3
+#define P_PPI1_FS3 P_UNDEF
+#endif
+
+#ifndef P_PPI2_FS3
+#define P_PPI2_FS3 P_UNDEF
+#endif
+
+#ifndef P_TMR8
+#define P_TMR8 P_UNDEF
+#endif
+
+#ifndef P_TMR9
+#define P_TMR9 P_UNDEF
+#endif
+
+#ifndef P_TMR10
+#define P_TMR10 P_UNDEF
+#endif
+#ifndef P_TMR11
+#define P_TMR11 P_UNDEF
+#endif
+
+#ifndef P_DMAR0
+#define P_DMAR0 P_UNDEF
+#endif
+
+#ifndef P_DMAR1
+#define P_DMAR1 P_UNDEF
+#endif
+
+#ifndef P_PPI0_FS3
+#define P_PPI0_FS3 P_UNDEF
+#endif
+
+#ifndef P_CNT_CDG
+#define P_CNT_CDG P_UNDEF
+#endif
+
+#ifndef P_CNT_CUD
+#define P_CNT_CUD P_UNDEF
+#endif
+
+#ifndef P_A10
+#define P_A10 P_UNDEF
+#endif
+
+#ifndef P_A11
+#define P_A11 P_UNDEF
+#endif
+
+#ifndef P_A12
+#define P_A12 P_UNDEF
+#endif
+
+#ifndef P_A13
+#define P_A13 P_UNDEF
+#endif
+
+#ifndef P_A14
+#define P_A14 P_UNDEF
+#endif
+
+#ifndef P_A15
+#define P_A15 P_UNDEF
+#endif
+
+#ifndef P_A16
+#define P_A16 P_UNDEF
+#endif
+
+#ifndef P_A17
+#define P_A17 P_UNDEF
+#endif
+
+#ifndef P_A18
+#define P_A18 P_UNDEF
+#endif
+
+#ifndef P_A19
+#define P_A19 P_UNDEF
+#endif
+
+#ifndef P_A20
+#define P_A20 P_UNDEF
+#endif
+
+#ifndef P_A21
+#define P_A21 P_UNDEF
+#endif
+
+#ifndef P_A22
+#define P_A22 P_UNDEF
+#endif
+
+#ifndef P_A23
+#define P_A23 P_UNDEF
+#endif
+
+#ifndef P_A24
+#define P_A24 P_UNDEF
+#endif
+
+#ifndef P_A25
+#define P_A25 P_UNDEF
+#endif
+
+#ifndef P_NOR_CLK
+#define P_NOR_CLK P_UNDEF
+#endif
+
+#ifndef  P_TMRCLK
+#define  P_TMRCLK P_UNDEF
+#endif
+
+#ifndef P_AMC_ARDY_NOR_WAIT
+#define P_AMC_ARDY_NOR_WAIT P_UNDEF
+#endif
+
+#ifndef P_NAND_CE
+#define P_NAND_CE P_UNDEF
+#endif
+
+#ifndef P_NAND_RB
+#define P_NAND_RB P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DIOR
+#define P_ATAPI_DIOR P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DIOW
+#define P_ATAPI_DIOW P_UNDEF
+#endif
+
+#ifndef P_ATAPI_CS0
+#define P_ATAPI_CS0 P_UNDEF
+#endif
+
+#ifndef P_ATAPI_CS1
+#define P_ATAPI_CS1 P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DMACK
+#define P_ATAPI_DMACK P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DMARQ
+#define P_ATAPI_DMARQ P_UNDEF
+#endif
+
+#ifndef P_ATAPI_INTRQ
+#define P_ATAPI_INTRQ P_UNDEF
+#endif
+
+#ifndef P_ATAPI_IORDY
+#define P_ATAPI_IORDY P_UNDEF
+#endif
+
+#ifndef P_AMC_BR
+#define P_AMC_BR P_UNDEF
+#endif
+
+#ifndef P_AMC_BG
+#define P_AMC_BG P_UNDEF
+#endif
+
+#ifndef P_AMC_BGH
+#define P_AMC_BGH P_UNDEF
+#endif
+
+/* EMAC */
+
+#ifndef P_MII0_ETxD0
+#define P_MII0_ETxD0 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxD1
+#define P_MII0_ETxD1 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxD2
+#define P_MII0_ETxD2 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxD3
+#define P_MII0_ETxD3 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxEN
+#define P_MII0_ETxEN P_UNDEF
+#endif
+
+#ifndef P_MII0_TxCLK
+#define P_MII0_TxCLK P_UNDEF
+#endif
+
+#ifndef P_MII0_PHYINT
+#define P_MII0_PHYINT P_UNDEF
+#endif
+
+#ifndef P_MII0_COL
+#define P_MII0_COL P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD0
+#define P_MII0_ERxD0 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD1
+#define P_MII0_ERxD1 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD2
+#define P_MII0_ERxD2 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD3
+#define P_MII0_ERxD3 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxDV
+#define P_MII0_ERxDV P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxCLK
+#define P_MII0_ERxCLK P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxER
+#define P_MII0_ERxER P_UNDEF
+#endif
+
+#ifndef P_MII0_CRS
+#define P_MII0_CRS P_UNDEF
+#endif
+
+#ifndef P_RMII0_REF_CLK
+#define P_RMII0_REF_CLK P_UNDEF
+#endif
+
+#ifndef P_RMII0_MDINT
+#define P_RMII0_MDINT P_UNDEF
+#endif
+
+#ifndef P_RMII0_CRS_DV
+#define P_RMII0_CRS_DV P_UNDEF
+#endif
+
+#ifndef P_MDC
+#define P_MDC P_UNDEF
+#endif
+
+#ifndef P_MDIO
+#define P_MDIO P_UNDEF
+#endif
+
+#endif                          /* _PORTMUX_H_ */
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
new file mode 100644
index 000000000000..9c2474c9a589
--- /dev/null
+++ b/include/asm-blackfin/trace.h
@@ -0,0 +1,52 @@
+/*
+ * Common header file for blackfin family of processors.
+ *
+ */
+
+#ifndef _BLACKFIN_TRACE_
+#define _BLACKFIN_TRACE_
+
+#ifndef __ASSEMBLY__
+/* Trace Macros for C files */
+
+#define trace_buffer_save(x) \
+        do { \
+                (x) = bfin_read_TBUFCTL(); \
+                bfin_write_TBUFCTL((x) & ~TBUFEN); \
+        } while (0)
+
+#define trace_buffer_restore(x) \
+        do { \
+                bfin_write_TBUFCTL((x));        \
+        } while (0)
+
+#else
+/* Trace Macros for Assembly files */
+
+#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg)
+#define TRACE_BUFFER_STOP(preg, dreg)  trace_buffer_stop(preg, dreg)
+
+#define trace_buffer_stop(preg, dreg)   \
+        preg.L = LO(TBUFCTL);           \
+        preg.H = HI(TBUFCTL);           \
+        dreg = 0x1;                     \
+        [preg] = dreg;
+
+#define trace_buffer_start(preg, dreg) \
+        preg.L = LO(TBUFCTL);           \
+        preg.H = HI(TBUFCTL);           \
+        dreg = 0x13;                    \
+        [preg] = dreg;
+
+#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
+# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg)
+# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg)
+
+#else
+# define DEBUG_START_HWTRACE(preg, dreg)
+# define DEBUG_STOP_HWTRACE(preg, dreg)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif                          /* _BLACKFIN_TRACE_ */
diff --git a/include/asm-i386/boot.h b/include/asm-i386/boot.h
index bd024ab4fe53..ed8affbf96cb 100644
--- a/include/asm-i386/boot.h
+++ b/include/asm-i386/boot.h
@@ -1,5 +1,5 @@
-#ifndef _LINUX_BOOT_H
-#define _LINUX_BOOT_H
+#ifndef _ASM_BOOT_H
+#define _ASM_BOOT_H
 
 /* Don't touch these, unless you really know what you're doing. */
 #define DEF_INITSEG     0x9000
@@ -17,4 +17,4 @@
                                 + (CONFIG_PHYSICAL_ALIGN - 1)) \
                                 & ~(CONFIG_PHYSICAL_ALIGN - 1))
 
-#endif /* _LINUX_BOOT_H */
+#endif /* _ASM_BOOT_H */
diff --git a/include/asm-i386/bootparam.h b/include/asm-i386/bootparam.h
new file mode 100644
index 000000000000..427d8652bfde
--- /dev/null
+++ b/include/asm-i386/bootparam.h
@@ -0,0 +1,85 @@
+#ifndef _ASM_BOOTPARAM_H
+#define _ASM_BOOTPARAM_H
+
+#include <linux/types.h>
+#include <linux/screen_info.h>
+#include <linux/apm_bios.h>
+#include <asm/e820.h>
+#include <linux/edd.h>
+#include <video/edid.h>
+
+struct setup_header {
+        u8      setup_sects;
+        u16     root_flags;
+        u32     syssize;
+        u16     ram_size;
+        u16     vid_mode;
+        u16     root_dev;
+        u16     boot_flag;
+        u16     jump;
+        u32     header;
+        u16     version;
+        u32     realmode_swtch;
+        u16     start_sys;
+        u16     kernel_version;
+        u8      type_of_loader;
+        u8      loadflags;
+#define LOADED_HIGH     0x01
+#define CAN_USE_HEAP    0x80
+        u16     setup_move_size;
+        u32     code32_start;
+        u32     ramdisk_image;
+        u32     ramdisk_size;
+        u32     bootsect_kludge;
+        u16     heap_end_ptr;
+        u16     _pad1;
+        u32     cmd_line_ptr;
+        u32     initrd_addr_max;
+        u32     kernel_alignment;
+        u8      relocatable_kernel;
+} __attribute__((packed));
+
+struct sys_desc_table {
+        u16 length;
+        u8  table[14];
+};
+
+struct efi_info {
+        u32 _pad1;
+        u32 efi_systab;
+        u32 efi_memdesc_size;
+        u32 efi_memdec_version;
+        u32 efi_memmap;
+        u32 fi_memmap_size;
+        u32 _pad2[2];
+};
+
+/* The so-called "zeropage" */
+struct boot_params {
+        struct screen_info screen_info;                 /* 0x000 */
+        struct apm_bios_info apm_bios_info;             /* 0x040 */
+        u8  _pad2[12];                                  /* 0x054 */
+        u32 speedstep_info[4];                          /* 0x060 */
+        u8  _pad3[16];                                  /* 0x070 */
+        u8  hd0_info[16];       /* obsolete! */         /* 0x080 */
+        u8  hd1_info[16];       /* obsolete! */         /* 0x090 */
+        struct sys_desc_table sys_desc_table;           /* 0x0a0 */
+        u8  _pad4[144];                                 /* 0x0b0 */
+        struct edid_info edid_info;                     /* 0x140 */
+        struct efi_info efi_info;                       /* 0x1c0 */
+        u32 alt_mem_k;                                  /* 0x1e0 */
+        u32 scratch;            /* Scratch field! */    /* 0x1e4 */
+        u8  e820_entries;                               /* 0x1e8 */
+        u8  eddbuf_entries;                             /* 0x1e9 */
+        u8  edd_mbr_sig_buf_entries;                    /* 0x1ea */
+        u8  _pad6[6];                                   /* 0x1eb */
+        struct setup_header hdr;    /* setup header */  /* 0x1f1 */
+        u8  _pad7[0x290-0x1f1-sizeof(struct setup_header)];
+        u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX];        /* 0x290 */
+        struct e820entry e820_map[E820MAX];             /* 0x2d0 */
+        u8  _pad8[48];                                  /* 0xcd0 */
+        struct edd_info eddbuf[EDDMAXNR];               /* 0xd00 */
+        u8  _pad9[276];                                 /* 0xeec */
+} __attribute__((packed));
+
+#endif /* _ASM_BOOTPARAM_H */
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index f514e906643a..c961c03cf1e2 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -12,7 +12,7 @@
 #endif
 #include <asm/required-features.h>
 
-#define NCAPINTS        7       /* N 32-bit words worth of info */
+#define NCAPINTS        8       /* N 32-bit words worth of info */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
 #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
@@ -81,6 +81,7 @@
 #define X86_FEATURE_BTS         (3*32+13)  /* Branch Trace Store */
 #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */
 #define X86_FEATURE_SYNC_RDTSC  (3*32+15)  /* RDTSC synchronizes the CPU */
+#define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well on this CPU */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -108,11 +109,24 @@
 #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
 #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
 
-#define cpu_has(c, bit)                                 \
-        ((__builtin_constant_p(bit) && (bit) < 32 &&    \
-                (1UL << (bit)) & REQUIRED_MASK1) ?      \
-                1 :                                     \
-        test_bit(bit, (c)->x86_capability))
+/*
+ * Auxiliary flags: Linux defined - For features scattered in various
+ * CPUID levels like 0x6, 0xA etc
+ */
+#define X86_FEATURE_IDA         (7*32+ 0) /* Intel Dynamic Acceleration */
+
+#define cpu_has(c, bit)                                                 \
+        (__builtin_constant_p(bit) &&                                   \
+         ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||     \
+           (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||     \
+           (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||     \
+           (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||     \
+           (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||     \
+           (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||     \
+           (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||     \
+           (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )      \
+          ? 1 :                                                         \
+          test_bit(bit, (c)->x86_capability))
 #define boot_cpu_has(bit)       cpu_has(&boot_cpu_data, bit)
 
 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
diff --git a/include/asm-i386/e820.h b/include/asm-i386/e820.h
index 096a2a8eb1da..c03290ccecb2 100644
--- a/include/asm-i386/e820.h
+++ b/include/asm-i386/e820.h
@@ -25,13 +25,15 @@
 
 #ifndef __ASSEMBLY__
 
+struct e820entry {
+        u64 addr;       /* start of memory segment */
+        u64 size;       /* size of memory segment */
+        u32 type;       /* type of memory segment */
+} __attribute__((packed));
+
 struct e820map {
-    int nr_map;
-    struct e820entry {
-        unsigned long long addr;        /* start of memory segment */
-        unsigned long long size;        /* size of memory segment */
-        unsigned long type;             /* type of memory segment */
-    } map[E820MAX];
+        u32 nr_map;
+        struct e820entry map[E820MAX];
 };
 
 extern struct e820map e820;
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index 338668bfb0a2..94e0c147c165 100644
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -119,6 +119,7 @@ void __init cpu_detect(struct cpuinfo_x86 *c);
 extern void identify_boot_cpu(void);
 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 extern void print_cpu_info(struct cpuinfo_x86 *);
+extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
 
diff --git a/include/asm-i386/required-features.h b/include/asm-i386/required-features.h
index 9db866c1e64c..65848a007050 100644
--- a/include/asm-i386/required-features.h
+++ b/include/asm-i386/required-features.h
@@ -3,32 +3,53 @@
 
 /* Define minimum CPUID feature set for kernel These bits are checked
    really early to actually display a visible error message before the
-   kernel dies.  Only add word 0 bits here
+   kernel dies.  Make sure to assign features to the proper mask!
 
    Some requirements that are not in CPUID yet are also in the
-   CONFIG_X86_MINIMUM_CPU mode which is checked too.
+   CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too.
 
    The real information is in arch/i386/Kconfig.cpu, this just converts
    the CONFIGs into a bitmask */
 
+#ifndef CONFIG_MATH_EMULATION
+# define NEED_FPU       (1<<(X86_FEATURE_FPU & 31))
+#else
+# define NEED_FPU       0
+#endif
+
 #ifdef CONFIG_X86_PAE
-#define NEED_PAE        (1<<X86_FEATURE_PAE)
+# define NEED_PAE       (1<<(X86_FEATURE_PAE & 31))
 #else
-#define NEED_PAE        0
+# define NEED_PAE       0
 #endif
 
 #ifdef CONFIG_X86_CMOV
-#define NEED_CMOV       (1<<X86_FEATURE_CMOV)
+# define NEED_CMOV      (1<<(X86_FEATURE_CMOV & 31))
 #else
-#define NEED_CMOV       0
+# define NEED_CMOV      0
 #endif
 
 #ifdef CONFIG_X86_CMPXCHG64
-#define NEED_CMPXCHG64  (1<<X86_FEATURE_CX8)
+# define NEED_CX8       (1<<(X86_FEATURE_CX8 & 31))
+#else
+# define NEED_CX8       0
+#endif
+
+#define REQUIRED_MASK0  (NEED_FPU|NEED_PAE|NEED_CMOV|NEED_CX8)
+
+#ifdef CONFIG_X86_USE_3DNOW
+# define NEED_3DNOW     (1<<(X86_FEATURE_3DNOW & 31))
 #else
-#define NEED_CMPXCHG64  0
+# define NEED_3DNOW     0
 #endif
 
-#define REQUIRED_MASK1  (NEED_PAE|NEED_CMOV|NEED_CMPXCHG64)
+#define REQUIRED_MASK1  (NEED_3DNOW)
+
+#define REQUIRED_MASK2  0
+#define REQUIRED_MASK3  0
+#define REQUIRED_MASK4  0
+#define REQUIRED_MASK5  0
+#define REQUIRED_MASK6  0
+#define REQUIRED_MASK7  0
 
 #endif
diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h
index 0e8077cbfdac..0d5bff9dc4a5 100644
--- a/include/asm-i386/setup.h
+++ b/include/asm-i386/setup.h
@@ -26,12 +26,15 @@
 #define NEW_CL_POINTER          0x228   /* Relative to real mode data */
 
 #ifndef __ASSEMBLY__
+
+#include <asm/bootparam.h>
+
 /*
  * This is set up by the setup-routine at boot-time
  */
-extern unsigned char boot_params[PARAM_SIZE];
+extern struct boot_params boot_params;
 
-#define PARAM   (boot_params)
+#define PARAM   ((char *)&boot_params)
 #define SCREEN_INFO (*(struct screen_info *) (PARAM+0))
 #define EXT_MEM_K (*(unsigned short *) (PARAM+2))
 #define ALT_MEM_K (*(unsigned long *) (PARAM+0x1e0))
@@ -39,8 +42,7 @@ extern unsigned char boot_params[PARAM_SIZE];
 #define E820_MAP    ((struct e820entry *) (PARAM+E820MAP))
 #define APM_BIOS_INFO (*(struct apm_bios_info *) (PARAM+0x40))
 #define IST_INFO   (*(struct ist_info *) (PARAM+0x60))
-#define DRIVE_INFO (*(struct drive_info_struct *) (PARAM+0x80))
-#define SYS_DESC_TABLE (*(struct sys_desc_table_struct*)(PARAM+0xa0))
+#define SYS_DESC_TABLE (*(struct sys_desc_table *)(PARAM+0xa0))
 #define EFI_SYSTAB ((efi_system_table_t *) *((unsigned long *)(PARAM+0x1c4)))
 #define EFI_MEMDESC_SIZE (*((unsigned long *) (PARAM+0x1c8)))
 #define EFI_MEMDESC_VERSION (*((unsigned long *) (PARAM+0x1cc)))
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 12bcc1f9fba9..7ba92890ea13 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -212,7 +212,8 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
                  */
                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
                     flags == _CACHE_UNCACHED)
-                        return (void __iomem *)CKSEG1ADDR(phys_addr);
+                        return (void __iomem *)
+                                (unsigned long)CKSEG1ADDR(phys_addr);
         }
 
         return __ioremap(offset, size, flags);
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 3ca6a076124d..97102ebc54b1 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,7 +24,7 @@ static inline int irq_canonicalize(int irq)
 #define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
 #endif
 
-#ifdef CONFIG_MIPS_MT_SMTC
+#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 /*
  * Clear interrupt mask handling "backstop" if irq_hwmask
  * entry so indicates. This implies that the ack() or end()
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 706b3691f57e..18f47f1e8cd5 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -707,10 +707,10 @@ do {									\
  */
 #define __read_64bit_c0_split(source, sel)                              \
 ({                                                                      \
-        unsigned long long val;                                         \
-        unsigned long flags;                                            \
+        unsigned long long __val;                                       \
+        unsigned long __flags;                                          \
                                                                         \
-        local_irq_save(flags);                                          \
+        local_irq_save(__flags);                                        \
         if (sel == 0)                                                   \
                 __asm__ __volatile__(                                   \
                         ".set\tmips64\n\t"                              \
@@ -719,7 +719,7 @@ do {									\
                         "dsrl\t%M0, %M0, 32\n\t"                        \
                         "dsrl\t%L0, %L0, 32\n\t"                        \
                         ".set\tmips0"                                   \
-                        : "=r" (val));                                  \
+                        : "=r" (__val));                                \
         else                                                            \
                 __asm__ __volatile__(                                   \
                         ".set\tmips64\n\t"                              \
@@ -728,17 +728,17 @@ do {									\
                         "dsrl\t%M0, %M0, 32\n\t"                        \
                         "dsrl\t%L0, %L0, 32\n\t"                        \
                         ".set\tmips0"                                   \
-                        : "=r" (val));                                  \
-        local_irq_restore(flags);                                       \
+                        : "=r" (__val));                                \
+        local_irq_restore(__flags);                                     \
                                                                         \
-        val;                                                            \
+        __val;                                                          \
 })
 
 #define __write_64bit_c0_split(source, sel, val)                        \
 do {                                                                    \
-        unsigned long flags;                                            \
+        unsigned long __flags;                                          \
                                                                         \
-        local_irq_save(flags);                                          \
+        local_irq_save(__flags);                                        \
         if (sel == 0)                                                   \
                 __asm__ __volatile__(                                   \
                         ".set\tmips64\n\t"                              \
@@ -759,7 +759,7 @@ do {									\
                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
                         ".set\tmips0"                                   \
                         : : "r" (val));                                 \
-        local_irq_restore(flags);                                       \
+        local_irq_restore(__flags);                                     \
 } while (0)
 
 #define read_c0_index()         __read_32bit_c0_register($0, 0)
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
deleted file mode 100644
index 82ad401c7dca..000000000000
--- a/include/asm-mips/rtc.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * include/asm-mips/rtc.h
- *
- * (Really an interface for drivers/char/genrtc.c)
- *
- * Copyright (C) 2004 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * Please read the COPYING file for all license details.
- */
-
-#ifndef _MIPS_RTC_H
-#define _MIPS_RTC_H
-
-#ifdef __KERNEL__
-
-#include <linux/rtc.h>
-#include <asm/time.h>
-
-#define RTC_PIE 0x40            /* periodic interrupt enable */
-#define RTC_AIE 0x20            /* alarm interrupt enable */
-#define RTC_UIE 0x10            /* update-finished interrupt enable */
-
-/* some dummy definitions */
-#define RTC_BATT_BAD 0x100      /* battery bad */
-#define RTC_SQWE 0x08           /* enable square-wave output */
-#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
-#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
-#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
-
-static inline unsigned int get_rtc_time(struct rtc_time *time)
-{
-        unsigned long nowtime;
-
-        nowtime = rtc_mips_get_time();
-        to_tm(nowtime, time);
-        time->tm_year -= 1900;
-
-        return RTC_24H;
-}
-
-static inline int set_rtc_time(struct rtc_time *time)
-{
-        unsigned long nowtime;
-        int ret;
-
-        nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
-                        time->tm_mday, time->tm_hour, time->tm_min,
-                        time->tm_sec);
-        ret = rtc_mips_set_time(nowtime);
-
-        return ret;
-}
-
-static inline unsigned int get_rtc_ss(void)
-{
-        struct rtc_time h;
-
-        get_rtc_time(&h);
-        return h.tm_sec;
-}
-
-static inline int get_rtc_pll(struct rtc_pll_info *pll)
-{
-        return -EINVAL;
-}
-
-static inline int set_rtc_pll(struct rtc_pll_info *pll)
-{
-        return -EINVAL;
-}
-#endif
-#endif
diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h
index fff7a73e22d0..bb8f5c29c3d9 100644
--- a/include/asm-mips/tlbdebug.h
+++ b/include/asm-mips/tlbdebug.h
@@ -11,10 +11,6 @@
 /*
  * TLB debugging functions:
  */
-extern void dump_tlb(int first, int last);
 extern void dump_tlb_all(void);
-extern void dump_tlb_wired(void);
-extern void dump_tlb_addr(unsigned long addr);
-extern void dump_tlb_nonwired(void);
 
 #endif /* __ASM_TLBDEBUG_H */
diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h
index 8109cda557dc..0bcdd3a5c256 100644
--- a/include/asm-mips/vr41xx/giu.h
+++ b/include/asm-mips/vr41xx/giu.h
@@ -20,6 +20,15 @@
 #ifndef __NEC_VR41XX_GIU_H
 #define __NEC_VR41XX_GIU_H
 
+/*
+ * NEC VR4100 series GIU platform device IDs.
+ */
+enum {
+        GPIO_50PINS_PULLUPDOWN,
+        GPIO_36PINS,
+        GPIO_48PINS_EDGE_SELECT,
+};
+
 typedef enum {
         IRQ_TRIGGER_LEVEL,
         IRQ_TRIGGER_EDGE,
diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h
index 1fcf6e8082b4..98cdb4096485 100644
--- a/include/asm-mips/vr41xx/siu.h
+++ b/include/asm-mips/vr41xx/siu.h
@@ -20,6 +20,8 @@
 #ifndef __NEC_VR41XX_SIU_H
 #define __NEC_VR41XX_SIU_H
 
+#define SIU_PORTS_MAX 2
+
 typedef enum {
         SIU_INTERFACE_RS232C,
         SIU_INTERFACE_IRDA,
diff --git a/include/asm-x86_64/alternative.h b/include/asm-x86_64/alternative.h
index a09427640764..eea7aecfac78 100644
--- a/include/asm-x86_64/alternative.h
+++ b/include/asm-x86_64/alternative.h
@@ -5,6 +5,41 @@
 
 #include <linux/types.h>
 #include <linux/stddef.h>
+
+/*
+ * Alternative inline assembly for SMP.
+ *
+ * The LOCK_PREFIX macro defined here replaces the LOCK and
+ * LOCK_PREFIX macros used everywhere in the source tree.
+ *
+ * SMP alternatives use the same data structures as the other
+ * alternatives and the X86_FEATURE_UP flag to indicate the case of a
+ * UP system running a SMP kernel.  The existing apply_alternatives()
+ * works fine for patching a SMP kernel for UP.
+ *
+ * The SMP alternative tables can be kept after boot and contain both
+ * UP and SMP versions of the instructions to allow switching back to
+ * SMP at runtime, when hotplugging in a new CPU, which is especially
+ * useful in virtualized environments.
+ *
+ * The very common lock prefix is handled as special case in a
+ * separate table which is a pure address list without replacement ptr
+ * and size information.  That keeps the table sizes small.
+ */
+
+#ifdef CONFIG_SMP
+#define LOCK_PREFIX \
+                ".section .smp_locks,\"a\"\n"   \
+                "  .align 8\n"                  \
+                "  .quad 661f\n" /* address */  \
+                ".previous\n"                   \
+                "661:\n\tlock; "
+
+#else /* ! CONFIG_SMP */
+#define LOCK_PREFIX ""
+#endif
+
+/* This must be included *after* the definition of LOCK_PREFIX */
 #include <asm/cpufeature.h>
 
 struct alt_instr {
@@ -108,39 +143,6 @@ static inline void alternatives_smp_switch(int smp) {}
  */
 #define ASM_OUTPUT2(a, b) a, b
 
-/*
- * Alternative inline assembly for SMP.
- *
- * The LOCK_PREFIX macro defined here replaces the LOCK and
- * LOCK_PREFIX macros used everywhere in the source tree.
- *
- * SMP alternatives use the same data structures as the other
- * alternatives and the X86_FEATURE_UP flag to indicate the case of a
- * UP system running a SMP kernel.  The existing apply_alternatives()
- * works fine for patching a SMP kernel for UP.
- *
- * The SMP alternative tables can be kept after boot and contain both
- * UP and SMP versions of the instructions to allow switching back to
- * SMP at runtime, when hotplugging in a new CPU, which is especially
- * useful in virtualized environments.
- *
- * The very common lock prefix is handled as special case in a
- * separate table which is a pure address list without replacement ptr
- * and size information.  That keeps the table sizes small.
- */
-
-#ifdef CONFIG_SMP
-#define LOCK_PREFIX \
-                ".section .smp_locks,\"a\"\n"   \
-                "  .align 8\n"                  \
-                "  .quad 661f\n" /* address */  \
-                ".previous\n"                   \
-                "661:\n\tlock; "
-
-#else /* ! CONFIG_SMP */
-#define LOCK_PREFIX ""
-#endif
-
 struct paravirt_patch;
 #ifdef CONFIG_PARAVIRT
 void apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end);
diff --git a/include/asm-x86_64/boot.h b/include/asm-x86_64/boot.h
index 96b228e6e79c..3c46cea8db7f 100644
--- a/include/asm-x86_64/boot.h
+++ b/include/asm-x86_64/boot.h
@@ -1,15 +1 @@
-#ifndef _LINUX_BOOT_H
-#define _LINUX_BOOT_H
-
-/* Don't touch these, unless you really know what you're doing. */
-#define DEF_INITSEG     0x9000
-#define DEF_SYSSEG      0x1000
-#define DEF_SETUPSEG    0x9020
-#define DEF_SYSSIZE     0x7F00
-
-/* Internal svga startup constants */
-#define NORMAL_VGA      0xffff          /* 80x25 mode */
-#define EXTENDED_VGA    0xfffe          /* 80x50 mode */
-#define ASK_VGA         0xfffd          /* ask for it at bootup */
-
-#endif
+#include <asm-i386/boot.h>
diff --git a/include/asm-x86_64/bootparam.h b/include/asm-x86_64/bootparam.h
new file mode 100644
index 000000000000..aa82e5238d82
--- /dev/null
+++ b/include/asm-x86_64/bootparam.h
@@ -0,0 +1 @@
+#include <asm-i386/bootparam.h>
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h
index 0b3c686139f1..8baefc3beb2e 100644
--- a/include/asm-x86_64/cpufeature.h
+++ b/include/asm-x86_64/cpufeature.h
@@ -7,115 +7,24 @@
 #ifndef __ASM_X8664_CPUFEATURE_H
 #define __ASM_X8664_CPUFEATURE_H
 
-#define NCAPINTS        7       /* N 32-bit words worth of info */
+#include <asm-i386/cpufeature.h>
 
-/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
-#define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
-#define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
-#define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
-#define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
-#define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
-#define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
-#define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
-#define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
-#define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
-#define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
-#define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
-#define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
-#define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
-#define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
-#define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
-#define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
-#define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
-#define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
-#define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
-#define X86_FEATURE_DS          (0*32+21) /* Debug Store */
-#define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
-#define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
-#define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
-                                          /* of FPU context), and CR4.OSFXSR available */
-#define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
-#define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
-#define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
-#define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
-#define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
-#define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
-
-/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
-/* Don't duplicate feature flags which are redundant with Intel! */
-#define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
-#define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
-#define X86_FEATURE_FXSR_OPT    (1*32+25) /* FXSR optimizations */
-#define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
-#define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
-#define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
-#define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
-
-/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
-#define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
-#define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
-#define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
-
-/* Other features, Linux-defined mapping, word 3 */
-/* This range is used for feature bits which conflict or are synthesized */
-#define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
-#define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
-#define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
-#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
-#define X86_FEATURE_REP_GOOD    (3*32+ 4) /* rep microcode works well on this CPU */
-#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */
-#define X86_FEATURE_SYNC_RDTSC  (3*32+6)  /* RDTSC syncs CPU core */
-#define X86_FEATURE_FXSAVE_LEAK (3*32+7)  /* FIP/FOP/FDP leaks through FXSAVE */
-#define X86_FEATURE_UP          (3*32+8) /* SMP kernel running on UP */
-#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */
-#define X86_FEATURE_PEBS        (3*32+10) /* Precise-Event Based Sampling */
-#define X86_FEATURE_BTS         (3*32+11) /* Branch Trace Store */
-
-/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
-#define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
-#define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
-#define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
-#define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
-#define X86_FEATURE_CID         (4*32+10) /* Context ID */
-#define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
-#define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
-
-/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
-#define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
-#define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
-#define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
-#define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
-
-/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
-#define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
-#define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
-
-#define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
-#define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)
-
-#define cpu_has_fpu            1
+#undef  cpu_has_vme
 #define cpu_has_vme            0
-#define cpu_has_de             1
-#define cpu_has_pse            1
-#define cpu_has_tsc            1
+
+#undef  cpu_has_pae
 #define cpu_has_pae            ___BUG___
-#define cpu_has_pge            1
-#define cpu_has_apic           boot_cpu_has(X86_FEATURE_APIC)
-#define cpu_has_mtrr           1
-#define cpu_has_mmx            1
-#define cpu_has_fxsr           1
-#define cpu_has_xmm            1
-#define cpu_has_xmm2           1
-#define cpu_has_xmm3           boot_cpu_has(X86_FEATURE_XMM3)
-#define cpu_has_ht             boot_cpu_has(X86_FEATURE_HT)
+
+#undef  cpu_has_mp
 #define cpu_has_mp             1 /* XXX */
+
+#undef  cpu_has_k6_mtrr
 #define cpu_has_k6_mtrr        0
+
+#undef  cpu_has_cyrix_arr
 #define cpu_has_cyrix_arr      0
+
+#undef  cpu_has_centaur_mcr
 #define cpu_has_centaur_mcr    0
-#define cpu_has_clflush        boot_cpu_has(X86_FEATURE_CLFLSH)
-#define cpu_has_ds             boot_cpu_has(X86_FEATURE_DS)
-#define cpu_has_pebs           boot_cpu_has(X86_FEATURE_PEBS)
-#define cpu_has_bts            boot_cpu_has(X86_FEATURE_BTS)
 
 #endif /* __ASM_X8664_CPUFEATURE_H */
diff --git a/include/asm-x86_64/e820.h b/include/asm-x86_64/e820.h
index 6216fa3f2802..3486e701bd86 100644
--- a/include/asm-x86_64/e820.h
+++ b/include/asm-x86_64/e820.h
@@ -11,8 +11,6 @@
 #ifndef __E820_HEADER
 #define __E820_HEADER
 
-#include <linux/mmzone.h>
-
 #define E820MAP 0x2d0           /* our map */
 #define E820MAX 128             /* number of entries in E820MAP */
 #define E820NR  0x1e8           /* # entries in E820MAP */
@@ -30,7 +28,7 @@ struct e820entry {
 } __attribute__((packed));
 
 struct e820map {
-    int nr_map;
+        u32 nr_map;
         struct e820entry map[E820MAX];
 };
 
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index 461ffe4c1fcc..efc87a5aff7f 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -100,6 +100,7 @@ extern char ignore_irq13;
 
 extern void identify_cpu(struct cpuinfo_x86 *);
 extern void print_cpu_info(struct cpuinfo_x86 *);
+extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
 
@@ -368,8 +369,6 @@ static inline void sync_core(void)
         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 } 
 
-#define cpu_has_fpu 1
-
 #define ARCH_HAS_PREFETCH
 static inline void prefetch(void *x) 
 { 
diff --git a/include/asm-x86_64/required-features.h b/include/asm-x86_64/required-features.h
new file mode 100644
index 000000000000..e80d5761b00a
--- /dev/null
+++ b/include/asm-x86_64/required-features.h
@@ -0,0 +1,46 @@
+#ifndef _ASM_REQUIRED_FEATURES_H
+#define _ASM_REQUIRED_FEATURES_H 1
+
+/* Define minimum CPUID feature set for kernel These bits are checked
+   really early to actually display a visible error message before the
+   kernel dies.  Make sure to assign features to the proper mask!
+
+   The real information is in arch/x86_64/Kconfig.cpu, this just converts
+   the CONFIGs into a bitmask */
+
+/* x86-64 baseline features */
+#define NEED_FPU        (1<<(X86_FEATURE_FPU & 31))
+#define NEED_PSE        (1<<(X86_FEATURE_PSE & 31))
+#define NEED_MSR        (1<<(X86_FEATURE_MSR & 31))
+#define NEED_PAE        (1<<(X86_FEATURE_PAE & 31))
+#define NEED_CX8        (1<<(X86_FEATURE_CX8 & 31))
+#define NEED_PGE        (1<<(X86_FEATURE_PGE & 31))
+#define NEED_FXSR       (1<<(X86_FEATURE_FXSR & 31))
+#define NEED_CMOV       (1<<(X86_FEATURE_CMOV & 31))
+#define NEED_XMM        (1<<(X86_FEATURE_XMM & 31))
+#define NEED_XMM2       (1<<(X86_FEATURE_XMM2 & 31))
+
+#define REQUIRED_MASK0  (NEED_FPU|NEED_PSE|NEED_MSR|NEED_PAE|\
+                         NEED_CX8|NEED_PGE|NEED_FXSR|NEED_CMOV|\
+                         NEED_XMM|NEED_XMM2)
+#define SSE_MASK        (NEED_XMM|NEED_XMM2)
+
+/* x86-64 baseline features */
+#define NEED_LM         (1<<(X86_FEATURE_LM & 31))
+
+#ifdef CONFIG_X86_USE_3DNOW
+# define NEED_3DNOW     (1<<(X86_FEATURE_3DNOW & 31))
+#else
+# define NEED_3DNOW     0
+#endif
+
+#define REQUIRED_MASK1  (NEED_LM|NEED_3DNOW)
+
+#define REQUIRED_MASK2  0
+#define REQUIRED_MASK3  0
+#define REQUIRED_MASK4  0
+#define REQUIRED_MASK5  0
+#define REQUIRED_MASK6  0
+#define REQUIRED_MASK7  0
+
+#endif
diff --git a/include/asm-x86_64/segment.h b/include/asm-x86_64/segment.h
index adf2bf1e187c..04b8ab21328f 100644
--- a/include/asm-x86_64/segment.h
+++ b/include/asm-x86_64/segment.h
@@ -3,6 +3,14 @@
 
 #include <asm/cache.h>
 
+/* Simple and small GDT entries for booting only */
+
+#define GDT_ENTRY_BOOT_CS               2
+#define __BOOT_CS       (GDT_ENTRY_BOOT_CS * 8)
+
+#define GDT_ENTRY_BOOT_DS               (GDT_ENTRY_BOOT_CS + 1)
+#define __BOOT_DS       (GDT_ENTRY_BOOT_DS * 8)
+
 #define __KERNEL_CS     0x10
 #define __KERNEL_DS     0x18
 
diff --git a/include/linux/edd.h b/include/linux/edd.h
index b2b3e68aa512..7b647822d6dc 100644
--- a/include/linux/edd.h
+++ b/include/linux/edd.h
@@ -49,10 +49,6 @@
 #define EDD_MBR_SIG_MAX 16        /* max number of signatures to store */
 #define EDD_MBR_SIG_NR_BUF 0x1ea  /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF
                                      in boot_params - treat this as 1 byte  */
-#define EDD_CL_EQUALS   0x3d646465     /* "edd=" */
-#define EDD_CL_OFF      0x666f         /* "of" for off  */
-#define EDD_CL_SKIP     0x6b73         /* "sk" for skipmbr */
-#define EDD_CL_ON       0x6e6f         /* "on" for on */
 
 #ifndef __ASSEMBLY__
 
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index cae7d618030c..2eaba21b9b1a 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -90,7 +90,7 @@ extern s32 i2c_smbus_write_block_data(struct i2c_client * client,
                                       const u8 *values);
 /* Returns the number of read bytes */
 extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client,
-                                         u8 command, u8 *values);
+                                         u8 command, u8 length, u8 *values);
 extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client,
                                           u8 command, u8 length,
                                           const u8 *values);
@@ -150,15 +150,20 @@ struct i2c_driver {
 
 /**
  * struct i2c_client - represent an I2C slave device
+ * @flags: I2C_CLIENT_TEN indicates the device uses a ten bit chip address;
+ *      I2C_CLIENT_PEC indicates it uses SMBus Packet Error Checking
  * @addr: Address used on the I2C bus connected to the parent adapter.
  * @name: Indicates the type of the device, usually a chip name that's
  *      generic enough to hide second-sourcing and compatible revisions.
+ * @adapter: manages the bus segment hosting this I2C device
  * @dev: Driver model device node for the slave.
+ * @irq: indicates the IRQ generated by this device (if any)
  * @driver_name: Identifies new-style driver used with this device; also
  *      used as the module name for hotplug/coldplug modprobe support.
  *
  * An i2c_client identifies a single device (i.e. chip) connected to an
- * i2c bus. The behaviour is defined by the routines of the driver.
+ * i2c bus. The behaviour exposed to Linux is defined by the driver
+ * managing the device.
  */
 struct i2c_client {
         unsigned short flags;           /* div., see below              */
@@ -180,7 +185,8 @@ struct i2c_client {
 
 static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj)
 {
-        return to_i2c_client(container_of(kobj, struct device, kobj));
+        struct device * const dev = container_of(kobj, struct device, kobj);
+        return to_i2c_client(dev);
 }
 
 static inline void *i2c_get_clientdata (struct i2c_client *dev)
@@ -201,7 +207,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data)
  * @addr: stored in i2c_client.addr
  * @platform_data: stored in i2c_client.dev.platform_data
  * @irq: stored in i2c_client.irq
-
+ *
  * I2C doesn't actually support hardware probing, although controllers and
  * devices may be able to use I2C_SMBUS_QUICK to tell whether or not there's
  * a device at a given address.  Drivers commonly need more information than
@@ -210,7 +216,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data)
  * i2c_board_info is used to build tables of information listing I2C devices
  * that are present.  This information is used to grow the driver model tree
  * for "new style" I2C drivers.  For mainboards this is done statically using
- * i2c_register_board_info(), where @bus_num represents an adapter that isn't
+ * i2c_register_board_info(); bus numbers identify adapters that aren't
  * yet available.  For add-on boards, i2c_new_device() does this dynamically
  * with the adapter already known.
  */
@@ -518,8 +524,9 @@ union i2c_smbus_data {
 #define I2C_SMBUS_WORD_DATA         3
 #define I2C_SMBUS_PROC_CALL         4
 #define I2C_SMBUS_BLOCK_DATA        5
-#define I2C_SMBUS_I2C_BLOCK_DATA    6
+#define I2C_SMBUS_I2C_BLOCK_BROKEN  6
 #define I2C_SMBUS_BLOCK_PROC_CALL   7           /* SMBus 2.0 */
+#define I2C_SMBUS_I2C_BLOCK_DATA    8
 
 
 /* ----- commands for the ioctl like i2c_command call:
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 75c4d4d06892..8300001e9078 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -371,6 +371,7 @@
 #define PCI_DEVICE_ID_ATI_IXP600_SMBUS  0x4385
 #define PCI_DEVICE_ID_ATI_IXP600_IDE    0x438c
 #define PCI_DEVICE_ID_ATI_IXP700_SATA   0x4390
+#define PCI_DEVICE_ID_ATI_IXP700_SMBUS  0x4395
 #define PCI_DEVICE_ID_ATI_IXP700_IDE    0x439c
 
 #define PCI_VENDOR_ID_VLSI              0x1004
diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h
index b02308ee7667..3ee412bc00ec 100644
--- a/include/linux/screen_info.h
+++ b/include/linux/screen_info.h
@@ -10,7 +10,7 @@
 struct screen_info {
         u8  orig_x;             /* 0x00 */
         u8  orig_y;             /* 0x01 */
-        u16 dontuse1;           /* 0x02 -- EXT_MEM_K sits here */
+        u16 ext_mem_k;          /* 0x02 */
         u16 orig_video_page;    /* 0x04 */
         u8  orig_video_mode;    /* 0x06 */
         u8  orig_video_cols;    /* 0x07 */
@@ -27,7 +27,7 @@ struct screen_info {
         u16 lfb_depth;          /* 0x16 */
         u32 lfb_base;           /* 0x18 */
         u32 lfb_size;           /* 0x1c */
-        u16 dontuse2, dontuse3; /* 0x20 -- CL_MAGIC and CL_OFFSET here */
+        u16 cl_magic, cl_offset; /* 0x20 */
         u16 lfb_linelength;     /* 0x24 */
         u8  red_size;           /* 0x26 */
         u8  red_pos;            /* 0x27 */
@@ -42,9 +42,8 @@ struct screen_info {
         u16 pages;              /* 0x32 */
         u16 vesa_attributes;    /* 0x34 */
         u32 capabilities;       /* 0x36 */
-                                /* 0x3a -- 0x3b reserved for future expansion */
-                                /* 0x3c -- 0x3f micro stack for relocatable kernels */
-};
+        u8  _reserved[6];       /* 0x3a */
+} __attribute__((packed));
 
 extern struct screen_info screen_info;
 
diff --git a/include/linux/serio.h b/include/linux/serio.h
index 1ebf0455e224..d9377ce9ffd1 100644
--- a/include/linux/serio.h
+++ b/include/linux/serio.h
@@ -209,5 +209,6 @@ static inline void serio_unpin_driver(struct serio *serio)
 #define SERIO_PENMOUNT  0x31
 #define SERIO_TOUCHRIGHT        0x32
 #define SERIO_TOUCHWIN  0x33
+#define SERIO_TAOSEVM   0x34
 
 #endif