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-rw-r--r--arch/mips/Kconfig99
-rw-r--r--arch/mips/Makefile48
-rw-r--r--arch/mips/au1000/common/dbdma.c6
-rw-r--r--arch/mips/au1000/common/dbg_io.c2
-rw-r--r--arch/mips/au1000/common/irq.c15
-rw-r--r--arch/mips/au1000/common/power.c2
-rw-r--r--arch/mips/au1000/common/reset.c2
-rw-r--r--arch/mips/au1000/common/setup.c2
-rw-r--r--arch/mips/au1000/common/time.c46
-rw-r--r--arch/mips/au1000/db1x00/board_setup.c2
-rw-r--r--arch/mips/au1000/db1x00/init.c8
-rw-r--r--arch/mips/au1000/mtx-1/board_setup.c2
-rw-r--r--arch/mips/au1000/mtx-1/init.c1
-rw-r--r--arch/mips/au1000/pb1000/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1000/init.c1
-rw-r--r--arch/mips/au1000/pb1100/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1100/init.c1
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c8
-rw-r--r--arch/mips/au1000/pb1200/init.c1
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c2
-rw-r--r--arch/mips/au1000/pb1500/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1500/init.c1
-rw-r--r--arch/mips/au1000/pb1550/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1550/init.c1
-rw-r--r--arch/mips/au1000/xxs1500/board_setup.c2
-rw-r--r--arch/mips/au1000/xxs1500/init.c1
-rw-r--r--arch/mips/basler/excite/excite_prom.c1
-rw-r--r--arch/mips/basler/excite/excite_setup.c17
-rw-r--r--arch/mips/bcm47xx/Makefile6
-rw-r--r--arch/mips/bcm47xx/gpio.c79
-rw-r--r--arch/mips/bcm47xx/irq.c55
-rw-r--r--arch/mips/bcm47xx/prom.c158
-rw-r--r--arch/mips/bcm47xx/serial.c52
-rw-r--r--arch/mips/bcm47xx/setup.c123
-rw-r--r--arch/mips/bcm47xx/time.c55
-rw-r--r--arch/mips/bcm47xx/wgt634u.c64
-rw-r--r--arch/mips/boot/addinitrd.c60
-rw-r--r--arch/mips/boot/elf2ecoff.c2
-rw-r--r--arch/mips/cobalt/Makefile2
-rw-r--r--arch/mips/cobalt/console.c9
-rw-r--r--arch/mips/cobalt/irq.c116
-rw-r--r--arch/mips/cobalt/led.c62
-rw-r--r--arch/mips/cobalt/reset.c39
-rw-r--r--arch/mips/cobalt/rtc.c5
-rw-r--r--arch/mips/cobalt/serial.c7
-rw-r--r--arch/mips/cobalt/setup.c20
-rw-r--r--arch/mips/configs/bigsur_defconfig1
-rw-r--r--arch/mips/configs/cobalt_defconfig23
-rw-r--r--arch/mips/configs/lasat_defconfig828
-rw-r--r--arch/mips/configs/mtx1_defconfig3115
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/dec/ecc-berr.c2
-rw-r--r--arch/mips/dec/kn02xa-berr.c2
-rw-r--r--arch/mips/dec/prom/identify.c3
-rw-r--r--arch/mips/dec/prom/init.c8
-rw-r--r--arch/mips/dec/setup.c4
-rw-r--r--arch/mips/dec/time.c13
-rw-r--r--arch/mips/emma2rh/common/prom.c2
-rw-r--r--arch/mips/emma2rh/markeins/setup.c4
-rw-r--r--arch/mips/fw/arc/Makefile (renamed from arch/mips/arc/Makefile)0
-rw-r--r--arch/mips/fw/arc/arc_con.c (renamed from arch/mips/arc/arc_con.c)0
-rw-r--r--arch/mips/fw/arc/cmdline.c (renamed from arch/mips/arc/cmdline.c)0
-rw-r--r--arch/mips/fw/arc/env.c (renamed from arch/mips/arc/env.c)2
-rw-r--r--arch/mips/fw/arc/file.c (renamed from arch/mips/arc/file.c)2
-rw-r--r--arch/mips/fw/arc/identify.c (renamed from arch/mips/arc/identify.c)82
-rw-r--r--arch/mips/fw/arc/init.c (renamed from arch/mips/arc/init.c)0
-rw-r--r--arch/mips/fw/arc/memory.c (renamed from arch/mips/arc/memory.c)6
-rw-r--r--arch/mips/fw/arc/misc.c (renamed from arch/mips/arc/misc.c)2
-rw-r--r--arch/mips/fw/arc/promlib.c (renamed from arch/mips/arc/promlib.c)0
-rw-r--r--arch/mips/fw/arc/salone.c (renamed from arch/mips/arc/salone.c)0
-rw-r--r--arch/mips/fw/arc/time.c (renamed from arch/mips/arc/time.c)2
-rw-r--r--arch/mips/fw/arc/tree.c (renamed from arch/mips/arc/tree.c)2
-rw-r--r--arch/mips/fw/cfe/Makefile5
-rw-r--r--arch/mips/fw/cfe/cfe_api.c (renamed from arch/mips/sibyte/cfe/cfe_api.c)2
-rw-r--r--arch/mips/fw/cfe/cfe_api_int.h (renamed from arch/mips/sibyte/cfe/cfe_api_int.h)0
-rw-r--r--arch/mips/gt64120/wrppmc/Makefile2
-rw-r--r--arch/mips/gt64120/wrppmc/irq.c23
-rw-r--r--arch/mips/gt64120/wrppmc/pci.c3
-rw-r--r--arch/mips/gt64120/wrppmc/reset.c10
-rw-r--r--arch/mips/gt64120/wrppmc/serial.c80
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c39
-rw-r--r--arch/mips/gt64120/wrppmc/time.c13
-rw-r--r--arch/mips/jazz/Makefile2
-rw-r--r--arch/mips/jazz/irq.c142
-rw-r--r--arch/mips/jazz/jazz-platform.c60
-rw-r--r--arch/mips/jazz/jazzdma.c47
-rw-r--r--arch/mips/jazz/reset.c4
-rw-r--r--arch/mips/jazz/setup.c134
-rw-r--r--arch/mips/jmr3927/rbhma3100/init.c1
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c8
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c4
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c2
-rw-r--r--arch/mips/kernel/cpu-bugs64.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c129
-rw-r--r--arch/mips/kernel/gdb-stub.c26
-rw-r--r--arch/mips/kernel/i8253.c213
-rw-r--r--arch/mips/kernel/i8259.c37
-rw-r--r--arch/mips/kernel/irixelf.c40
-rw-r--r--arch/mips/kernel/irixinv.c42
-rw-r--r--arch/mips/kernel/irixioctl.c2
-rw-r--r--arch/mips/kernel/irixsig.c8
-rw-r--r--arch/mips/kernel/irq-gt641xx.c131
-rw-r--r--arch/mips/kernel/irq-msc01.c4
-rw-r--r--arch/mips/kernel/irq.c4
-rw-r--r--arch/mips/kernel/kspd.c12
-rw-r--r--arch/mips/kernel/linux32.c24
-rw-r--r--arch/mips/kernel/mips-mt.c2
-rw-r--r--arch/mips/kernel/proc.c73
-rw-r--r--arch/mips/kernel/process.c11
-rw-r--r--arch/mips/kernel/ptrace.c50
-rw-r--r--arch/mips/kernel/ptrace32.c16
-rw-r--r--arch/mips/kernel/setup.c2
-rw-r--r--arch/mips/kernel/signal.c4
-rw-r--r--arch/mips/kernel/signal32.c44
-rw-r--r--arch/mips/kernel/signal_n32.c4
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/smp.c123
-rw-r--r--arch/mips/kernel/smtc.c146
-rw-r--r--arch/mips/kernel/syscall.c60
-rw-r--r--arch/mips/kernel/sysirix.c22
-rw-r--r--arch/mips/kernel/time.c416
-rw-r--r--arch/mips/kernel/traps.c45
-rw-r--r--arch/mips/kernel/unaligned.c2
-rw-r--r--arch/mips/kernel/vmlinux.lds.S339
-rw-r--r--arch/mips/kernel/vpe.c47
-rw-r--r--arch/mips/lasat/Kconfig15
-rw-r--r--arch/mips/lasat/Makefile16
-rw-r--r--arch/mips/lasat/at93c.c149
-rw-r--r--arch/mips/lasat/at93c.h18
-rw-r--r--arch/mips/lasat/ds1603.c183
-rw-r--r--arch/mips/lasat/ds1603.h31
-rw-r--r--arch/mips/lasat/image/Makefile54
-rw-r--r--arch/mips/lasat/image/head.S31
-rw-r--r--arch/mips/lasat/image/romscript.normal23
-rw-r--r--arch/mips/lasat/interrupt.c130
-rw-r--r--arch/mips/lasat/lasat_board.c280
-rw-r--r--arch/mips/lasat/lasat_models.h67
-rw-r--r--arch/mips/lasat/picvue.c244
-rw-r--r--arch/mips/lasat/picvue.h48
-rw-r--r--arch/mips/lasat/picvue_proc.c191
-rw-r--r--arch/mips/lasat/prom.c126
-rw-r--r--arch/mips/lasat/prom.h7
-rw-r--r--arch/mips/lasat/reset.c61
-rw-r--r--arch/mips/lasat/serial.c94
-rw-r--r--arch/mips/lasat/setup.c154
-rw-r--r--arch/mips/lasat/sysctl.c456
-rw-r--r--arch/mips/lasat/sysctl.h24
-rw-r--r--arch/mips/lemote/lm2e/Makefile1
-rw-r--r--arch/mips/lemote/lm2e/prom.c1
-rw-r--r--arch/mips/lemote/lm2e/setup.c7
-rw-r--r--arch/mips/lib/ucmpdi2.c2
-rw-r--r--arch/mips/math-emu/cp1emu.c32
-rw-r--r--arch/mips/math-emu/dp_mul.c2
-rw-r--r--arch/mips/math-emu/ieee754.c12
-rw-r--r--arch/mips/math-emu/ieee754dp.h12
-rw-r--r--arch/mips/math-emu/ieee754int.h30
-rw-r--r--arch/mips/math-emu/ieee754sp.h12
-rw-r--r--arch/mips/mips-boards/atlas/atlas_gdb.c2
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c22
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c7
-rw-r--r--arch/mips/mips-boards/generic/init.c12
-rw-r--r--arch/mips/mips-boards/generic/memory.c4
-rw-r--r--arch/mips/mips-boards/generic/pci.c2
-rw-r--r--arch/mips/mips-boards/generic/time.c149
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c36
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c16
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c50
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c2
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c5
-rw-r--r--arch/mips/mipssim/sim_int.c2
-rw-r--r--arch/mips/mipssim/sim_mem.c4
-rw-r--r--arch/mips/mipssim/sim_setup.c2
-rw-r--r--arch/mips/mipssim/sim_time.c76
-rw-r--r--arch/mips/mm/Makefile2
-rw-r--r--arch/mips/mm/c-r3k.c12
-rw-r--r--arch/mips/mm/c-r4k.c116
-rw-r--r--arch/mips/mm/c-sb1.c535
-rw-r--r--arch/mips/mm/c-tx39.c6
-rw-r--r--arch/mips/mm/cache.c9
-rw-r--r--arch/mips/mm/cerr-sb1.c24
-rw-r--r--arch/mips/mm/dma-default.c4
-rw-r--r--arch/mips/mm/pg-r4k.c22
-rw-r--r--arch/mips/mm/pg-sb1.c12
-rw-r--r--arch/mips/mm/pgtable.c8
-rw-r--r--arch/mips/mm/sc-mips.c2
-rw-r--r--arch/mips/mm/tlb-r4k.c2
-rw-r--r--arch/mips/mm/tlb-r8k.c2
-rw-r--r--arch/mips/mm/tlbex.c210
-rw-r--r--arch/mips/oprofile/common.c2
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c6
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c2
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-atlas.c6
-rw-r--r--arch/mips/pci/fixup-cobalt.c40
-rw-r--r--arch/mips/pci/ops-au1000.c2
-rw-r--r--arch/mips/pci/ops-nile4.c147
-rw-r--r--arch/mips/pci/ops-sni.c22
-rw-r--r--arch/mips/pci/pci-bcm1480.c6
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c4
-rw-r--r--arch/mips/pci/pci-lasat.c91
-rw-r--r--arch/mips/pci/pci-sb1250.c4
-rw-r--r--arch/mips/pci/pci-vr41xx.c2
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c36
-rw-r--r--arch/mips/philips/pnx8550/common/setup.c3
-rw-r--r--arch/mips/philips/pnx8550/common/time.c7
-rw-r--r--arch/mips/philips/pnx8550/jbs/init.c1
-rw-r--r--arch/mips/philips/pnx8550/stb810/prom_init.c1
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c8
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c18
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c3
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c8
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht.c2
-rw-r--r--arch/mips/pmc-sierra/yosemite/prom.c1
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.c26
-rw-r--r--arch/mips/qemu/q-firmware.c2
-rw-r--r--arch/mips/qemu/q-irq.c4
-rw-r--r--arch/mips/qemu/q-setup.c10
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c7
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c35
-rw-r--r--arch/mips/sgi-ip27/ip27-berr.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c4
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c38
-rw-r--r--arch/mips/sgi-ip32/crime.c6
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c44
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c12
-rw-r--r--arch/mips/sibyte/Kconfig13
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c21
-rw-r--r--arch/mips/sibyte/bcm1480/setup.c78
-rw-r--r--arch/mips/sibyte/bcm1480/time.c118
-rw-r--r--arch/mips/sibyte/cfe/Makefile2
-rw-r--r--arch/mips/sibyte/cfe/console.c6
-rw-r--r--arch/mips/sibyte/cfe/setup.c7
-rw-r--r--arch/mips/sibyte/cfe/smp.c4
-rw-r--r--arch/mips/sibyte/common/Makefile1
-rw-r--r--arch/mips/sibyte/common/sb_tbprof.c4
-rw-r--r--arch/mips/sibyte/sb1250/irq.c58
-rw-r--r--arch/mips/sibyte/sb1250/prom.c3
-rw-r--r--arch/mips/sibyte/sb1250/setup.c74
-rw-r--r--arch/mips/sibyte/sb1250/time.c198
-rw-r--r--arch/mips/sibyte/swarm/dbg_io.c4
-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c3
-rw-r--r--arch/mips/sibyte/swarm/rtc_xicor1241.c3
-rw-r--r--arch/mips/sibyte/swarm/setup.c56
-rw-r--r--arch/mips/sni/a20r.c6
-rw-r--r--arch/mips/sni/pcimt.c5
-rw-r--r--arch/mips/sni/pcit.c27
-rw-r--r--arch/mips/sni/reset.c2
-rw-r--r--arch/mips/sni/rm200.c11
-rw-r--r--arch/mips/sni/setup.c8
-rw-r--r--arch/mips/sni/sniprom.c8
-rw-r--r--arch/mips/sni/time.c27
-rw-r--r--arch/mips/tx4927/common/tx4927_dbgio.c1
-rw-r--r--arch/mips/tx4927/common/tx4927_prom.c12
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c20
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c33
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c36
-rw-r--r--arch/mips/tx4938/common/setup.c9
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/prom.c1
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c7
-rw-r--r--arch/mips/vr41xx/common/bcu.c8
-rw-r--r--arch/mips/vr41xx/common/cmu.c16
-rw-r--r--arch/mips/vr41xx/common/giu.c2
-rw-r--r--arch/mips/vr41xx/common/icu.c76
-rw-r--r--arch/mips/vr41xx/common/init.c8
-rw-r--r--arch/mips/vr41xx/common/pmu.c40
-rw-r--r--arch/mips/vr41xx/common/rtc.c2
-rw-r--r--arch/mips/vr41xx/common/siu.c2
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/init.c6
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c6
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/setup.c1
-rw-r--r--include/asm-mips/addrspace.h6
-rw-r--r--include/asm-mips/asm.h66
-rw-r--r--include/asm-mips/asmmacro.h12
-rw-r--r--include/asm-mips/atomic.h28
-rw-r--r--include/asm-mips/bitops.h12
-rw-r--r--include/asm-mips/bootinfo.h41
-rw-r--r--include/asm-mips/byteorder.h4
-rw-r--r--include/asm-mips/cmpxchg.h4
-rw-r--r--include/asm-mips/cpu-features.h8
-rw-r--r--include/asm-mips/cpu-info.h21
-rw-r--r--include/asm-mips/cpu.h160
-rw-r--r--include/asm-mips/delay.h2
-rw-r--r--include/asm-mips/elf.h2
-rw-r--r--include/asm-mips/fixmap.h4
-rw-r--r--include/asm-mips/floppy.h6
-rw-r--r--include/asm-mips/futex.h2
-rw-r--r--include/asm-mips/fw/arc/hinv.h (renamed from include/asm-mips/arc/hinv.h)5
-rw-r--r--include/asm-mips/fw/arc/types.h (renamed from include/asm-mips/arc/types.h)0
-rw-r--r--include/asm-mips/fw/cfe/cfe_api.h (renamed from arch/mips/sibyte/cfe/cfe_api.h)24
-rw-r--r--include/asm-mips/fw/cfe/cfe_error.h (renamed from arch/mips/sibyte/cfe/cfe_error.h)0
-rw-r--r--include/asm-mips/hazards.h56
-rw-r--r--include/asm-mips/hw_irq.h7
-rw-r--r--include/asm-mips/i8253.h30
-rw-r--r--include/asm-mips/i8259.h5
-rw-r--r--include/asm-mips/inventory.h4
-rw-r--r--include/asm-mips/io.h18
-rw-r--r--include/asm-mips/ioctl.h16
-rw-r--r--include/asm-mips/ioctls.h12
-rw-r--r--include/asm-mips/ip32/machine.h20
-rw-r--r--include/asm-mips/irq.h67
-rw-r--r--include/asm-mips/irq_gt641xx.h60
-rw-r--r--include/asm-mips/irqflags.h10
-rw-r--r--include/asm-mips/jazz.h40
-rw-r--r--include/asm-mips/jazzdma.h1
-rw-r--r--include/asm-mips/jmr3927/tx3927.h32
-rw-r--r--include/asm-mips/lasat/ds1603.h18
-rw-r--r--include/asm-mips/lasat/eeprom.h17
-rw-r--r--include/asm-mips/lasat/head.h22
-rw-r--r--include/asm-mips/lasat/lasat.h256
-rw-r--r--include/asm-mips/lasat/lasatint.h12
-rw-r--r--include/asm-mips/lasat/picvue.h15
-rw-r--r--include/asm-mips/lasat/serial.h13
-rw-r--r--include/asm-mips/linkage.h2
-rw-r--r--include/asm-mips/local.h20
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h622
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h14
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h2
-rw-r--r--include/asm-mips/mach-au1x00/war.h25
-rw-r--r--include/asm-mips/mach-bcm47xx/bcm47xx.h25
-rw-r--r--include/asm-mips/mach-bcm47xx/gpio.h59
-rw-r--r--include/asm-mips/mach-bcm47xx/war.h25
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h61
-rw-r--r--include/asm-mips/mach-cobalt/cpu-feature-overrides.h1
-rw-r--r--include/asm-mips/mach-cobalt/irq.h58
-rw-r--r--include/asm-mips/mach-cobalt/war.h25
-rw-r--r--include/asm-mips/mach-dec/war.h25
-rw-r--r--include/asm-mips/mach-emma2rh/war.h25
-rw-r--r--include/asm-mips/mach-excite/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-excite/war.h25
-rw-r--r--include/asm-mips/mach-generic/mangle-port.h32
-rw-r--r--include/asm-mips/mach-ip22/war.h29
-rw-r--r--include/asm-mips/mach-ip27/irq.h2
-rw-r--r--include/asm-mips/mach-ip27/mangle-port.h16
-rw-r--r--include/asm-mips/mach-ip27/topology.h20
-rw-r--r--include/asm-mips/mach-ip27/war.h25
-rw-r--r--include/asm-mips/mach-ip32/kmalloc.h2
-rw-r--r--include/asm-mips/mach-ip32/mangle-port.h16
-rw-r--r--include/asm-mips/mach-ip32/war.h25
-rw-r--r--include/asm-mips/mach-jazz/mc146818rtc.h10
-rw-r--r--include/asm-mips/mach-jazz/war.h25
-rw-r--r--include/asm-mips/mach-jmr3927/mangle-port.h16
-rw-r--r--include/asm-mips/mach-jmr3927/war.h25
-rw-r--r--include/asm-mips/mach-lasat/mach-gt64120.h27
-rw-r--r--include/asm-mips/mach-lasat/war.h25
-rw-r--r--include/asm-mips/mach-lemote/war.h25
-rw-r--r--include/asm-mips/mach-mips/mach-gt64120.h9
-rw-r--r--include/asm-mips/mach-mips/war.h25
-rw-r--r--include/asm-mips/mach-mipssim/war.h25
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h56
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h60
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h26
-rw-r--r--include/asm-mips/mach-pnx8550/uart.h2
-rw-r--r--include/asm-mips/mach-pnx8550/war.h25
-rw-r--r--include/asm-mips/mach-qemu/war.h25
-rw-r--r--include/asm-mips/mach-rm/war.h29
-rw-r--r--include/asm-mips/mach-sibyte/cpu-feature-overrides.h7
-rw-r--r--include/asm-mips/mach-sibyte/war.h37
-rw-r--r--include/asm-mips/mach-tx49xx/war.h25
-rw-r--r--include/asm-mips/mach-vr41xx/war.h25
-rw-r--r--include/asm-mips/mach-wrppmc/mach-gt64120.h1
-rw-r--r--include/asm-mips/mach-wrppmc/war.h25
-rw-r--r--include/asm-mips/mach-yosemite/war.h25
-rw-r--r--include/asm-mips/mc146818-time.h4
-rw-r--r--include/asm-mips/mips-boards/bonito64.h20
-rw-r--r--include/asm-mips/mips-boards/malta.h2
-rw-r--r--include/asm-mips/mipsmtregs.h60
-rw-r--r--include/asm-mips/mipsregs.h4
-rw-r--r--include/asm-mips/mmu_context.h8
-rw-r--r--include/asm-mips/nile4.h310
-rw-r--r--include/asm-mips/paccess.h8
-rw-r--r--include/asm-mips/page.h2
-rw-r--r--include/asm-mips/parport.h6
-rw-r--r--include/asm-mips/pci.h4
-rw-r--r--include/asm-mips/pci/bridge.h2
-rw-r--r--include/asm-mips/pgalloc.h6
-rw-r--r--include/asm-mips/pgtable-32.h2
-rw-r--r--include/asm-mips/pgtable-64.h6
-rw-r--r--include/asm-mips/pgtable.h4
-rw-r--r--include/asm-mips/prctl.h2
-rw-r--r--include/asm-mips/qemu.h2
-rw-r--r--include/asm-mips/r4kcache.h6
-rw-r--r--include/asm-mips/semaphore.h8
-rw-r--r--include/asm-mips/sgiarcs.h36
-rw-r--r--include/asm-mips/sibyte/bcm1480_int.h22
-rw-r--r--include/asm-mips/sibyte/bcm1480_l2c.h102
-rw-r--r--include/asm-mips/sibyte/bcm1480_mc.h644
-rw-r--r--include/asm-mips/sibyte/bcm1480_regs.h18
-rw-r--r--include/asm-mips/sibyte/bcm1480_scd.h102
-rw-r--r--include/asm-mips/sibyte/board.h4
-rw-r--r--include/asm-mips/sibyte/sb1250_defs.h14
-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h246
-rw-r--r--include/asm-mips/sibyte/sb1250_genbus.h322
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h22
-rw-r--r--include/asm-mips/sibyte/sb1250_l2c.h64
-rw-r--r--include/asm-mips/sibyte/sb1250_ldt.h194
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h284
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h306
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h32
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h306
-rw-r--r--include/asm-mips/sibyte/sb1250_smbus.h62
-rw-r--r--include/asm-mips/sibyte/sb1250_syncser.h16
-rw-r--r--include/asm-mips/sibyte/sb1250_uart.h70
-rw-r--r--include/asm-mips/siginfo.h4
-rw-r--r--include/asm-mips/sim.h4
-rw-r--r--include/asm-mips/smp.h9
-rw-r--r--include/asm-mips/smtc_ipi.h1
-rw-r--r--include/asm-mips/sn/addrs.h50
-rw-r--r--include/asm-mips/sn/arch.h4
-rw-r--r--include/asm-mips/sn/io.h2
-rw-r--r--include/asm-mips/sn/klconfig.h6
-rw-r--r--include/asm-mips/sn/kldir.h2
-rw-r--r--include/asm-mips/sn/sn0/addrs.h8
-rw-r--r--include/asm-mips/sni.h18
-rw-r--r--include/asm-mips/stackframe.h20
-rw-r--r--include/asm-mips/system.h10
-rw-r--r--include/asm-mips/time.h41
-rw-r--r--include/asm-mips/timex.h2
-rw-r--r--include/asm-mips/tlbflush.h4
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h8
-rw-r--r--include/asm-mips/tx4927/tx4927.h439
-rw-r--r--include/asm-mips/tx4927/tx4927_mips.h4177
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h2
-rw-r--r--include/asm-mips/tx4938/tx4938.h44
-rw-r--r--include/asm-mips/tx4938/tx4938_mips.h8
-rw-r--r--include/asm-mips/uaccess.h58
-rw-r--r--include/asm-mips/unaligned.h27
-rw-r--r--include/asm-mips/vga.h4
-rw-r--r--include/asm-mips/war.h127
-rw-r--r--include/asm-mips/xtalk/xtalk.h2
436 files changed, 14483 insertions, 10331 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3b807b4bc7cd..f943736541cb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3,6 +3,7 @@ config MIPS
3 default y 3 default y
4 # Horrible source of confusion. Die, die, die ... 4 # Horrible source of confusion. Die, die, die ...
5 select EMBEDDED 5 select EMBEDDED
6 select RTC_LIB
6 7
7mainmenu "Linux/MIPS Kernel Configuration" 8mainmenu "Linux/MIPS Kernel Configuration"
8 9
@@ -44,12 +45,30 @@ config BASLER_EXCITE_PROTOTYPE
44 note that a kernel built with this option selected will not be 45 note that a kernel built with this option selected will not be
45 able to run on normal units. 46 able to run on normal units.
46 47
48config BCM47XX
49 bool "BCM47XX based boards"
50 select DMA_NONCOHERENT
51 select HW_HAS_PCI
52 select IRQ_CPU
53 select SYS_HAS_CPU_MIPS32_R1
54 select SYS_SUPPORTS_32BIT_KERNEL
55 select SYS_SUPPORTS_LITTLE_ENDIAN
56 select SSB
57 select SSB_DRIVER_MIPS
58 select GENERIC_GPIO
59 select SYS_HAS_EARLY_PRINTK
60 select CFE
61 help
62 Support for BCM47XX based boards
63
47config MIPS_COBALT 64config MIPS_COBALT
48 bool "Cobalt Server" 65 bool "Cobalt Server"
49 select DMA_NONCOHERENT 66 select DMA_NONCOHERENT
50 select HW_HAS_PCI 67 select HW_HAS_PCI
68 select I8253
51 select I8259 69 select I8259
52 select IRQ_CPU 70 select IRQ_CPU
71 select IRQ_GT641XX
53 select PCI_GT64XXX_PCI0 72 select PCI_GT64XXX_PCI0
54 select SYS_HAS_CPU_NEVADA 73 select SYS_HAS_CPU_NEVADA
55 select SYS_HAS_EARLY_PRINTK 74 select SYS_HAS_EARLY_PRINTK
@@ -93,6 +112,8 @@ config MACH_JAZZ
93 select ARC32 112 select ARC32
94 select ARCH_MAY_HAVE_PC_FDC 113 select ARCH_MAY_HAVE_PC_FDC
95 select GENERIC_ISA_DMA 114 select GENERIC_ISA_DMA
115 select IRQ_CPU
116 select I8253
96 select I8259 117 select I8259
97 select ISA 118 select ISA
98 select PCSPEAKER 119 select PCSPEAKER
@@ -107,6 +128,20 @@ config MACH_JAZZ
107 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and 128 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
108 Olivetti M700-10 workstations. 129 Olivetti M700-10 workstations.
109 130
131config LASAT
132 bool "LASAT Networks platforms"
133 select DMA_NONCOHERENT
134 select SYS_HAS_EARLY_PRINTK
135 select HW_HAS_PCI
136 select PCI_GT64XXX_PCI0
137 select MIPS_NILE4
138 select R5000_CPU_SCACHE
139 select SYS_HAS_CPU_R5000
140 select SYS_SUPPORTS_32BIT_KERNEL
141 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
142 select SYS_SUPPORTS_LITTLE_ENDIAN
143 select GENERIC_HARDIRQS_NO__DO_IRQ
144
110config LEMOTE_FULONG 145config LEMOTE_FULONG
111 bool "Lemote Fulong mini-PC" 146 bool "Lemote Fulong mini-PC"
112 select ARCH_SPARSEMEM_ENABLE 147 select ARCH_SPARSEMEM_ENABLE
@@ -168,6 +203,7 @@ config MIPS_MALTA
168 select GENERIC_ISA_DMA 203 select GENERIC_ISA_DMA
169 select IRQ_CPU 204 select IRQ_CPU
170 select HW_HAS_PCI 205 select HW_HAS_PCI
206 select I8253
171 select I8259 207 select I8259
172 select MIPS_BOARDS_GEN 208 select MIPS_BOARDS_GEN
173 select MIPS_BONITO64 209 select MIPS_BONITO64
@@ -301,7 +337,9 @@ config QEMU
301 select DMA_COHERENT 337 select DMA_COHERENT
302 select GENERIC_ISA_DMA 338 select GENERIC_ISA_DMA
303 select HAVE_STD_PC_SERIAL_PORT 339 select HAVE_STD_PC_SERIAL_PORT
340 select I8253
304 select I8259 341 select I8259
342 select IRQ_CPU
305 select ISA 343 select ISA
306 select PCSPEAKER 344 select PCSPEAKER
307 select SWAP_IO_SPACE 345 select SWAP_IO_SPACE
@@ -328,6 +366,7 @@ config SGI_IP22
328 select BOOT_ELF32 366 select BOOT_ELF32
329 select DMA_NONCOHERENT 367 select DMA_NONCOHERENT
330 select HW_HAS_EISA 368 select HW_HAS_EISA
369 select I8253
331 select IP22_CPU_SCACHE 370 select IP22_CPU_SCACHE
332 select IRQ_CPU 371 select IRQ_CPU
333 select GENERIC_ISA_DMA_SUPPORT_BROKEN 372 select GENERIC_ISA_DMA_SUPPORT_BROKEN
@@ -352,7 +391,6 @@ config SGI_IP27
352 select SYS_HAS_EARLY_PRINTK 391 select SYS_HAS_EARLY_PRINTK
353 select HW_HAS_PCI 392 select HW_HAS_PCI
354 select NR_CPUS_DEFAULT_64 393 select NR_CPUS_DEFAULT_64
355 select PCI_DOMAINS
356 select SYS_HAS_CPU_R10000 394 select SYS_HAS_CPU_R10000
357 select SYS_SUPPORTS_64BIT_KERNEL 395 select SYS_SUPPORTS_64BIT_KERNEL
358 select SYS_SUPPORTS_BIG_ENDIAN 396 select SYS_SUPPORTS_BIG_ENDIAN
@@ -484,7 +522,6 @@ config SIBYTE_BIGSUR
484 select BOOT_ELF32 522 select BOOT_ELF32
485 select DMA_COHERENT 523 select DMA_COHERENT
486 select NR_CPUS_DEFAULT_4 524 select NR_CPUS_DEFAULT_4
487 select PCI_DOMAINS
488 select SIBYTE_BCM1x80 525 select SIBYTE_BCM1x80
489 select SWAP_IO_SPACE 526 select SWAP_IO_SPACE
490 select SYS_HAS_CPU_SB1 527 select SYS_HAS_CPU_SB1
@@ -502,6 +539,7 @@ config SNI_RM
502 select HW_HAS_EISA 539 select HW_HAS_EISA
503 select HW_HAS_PCI 540 select HW_HAS_PCI
504 select IRQ_CPU 541 select IRQ_CPU
542 select I8253
505 select I8259 543 select I8259
506 select ISA 544 select ISA
507 select PCSPEAKER 545 select PCSPEAKER
@@ -599,6 +637,7 @@ endchoice
599 637
600source "arch/mips/au1000/Kconfig" 638source "arch/mips/au1000/Kconfig"
601source "arch/mips/jazz/Kconfig" 639source "arch/mips/jazz/Kconfig"
640source "arch/mips/lasat/Kconfig"
602source "arch/mips/pmc-sierra/Kconfig" 641source "arch/mips/pmc-sierra/Kconfig"
603source "arch/mips/sgi-ip27/Kconfig" 642source "arch/mips/sgi-ip27/Kconfig"
604source "arch/mips/sibyte/Kconfig" 643source "arch/mips/sibyte/Kconfig"
@@ -635,10 +674,18 @@ config GENERIC_CALIBRATE_DELAY
635 bool 674 bool
636 default y 675 default y
637 676
677config GENERIC_CLOCKEVENTS
678 bool
679 default y
680
638config GENERIC_TIME 681config GENERIC_TIME
639 bool 682 bool
640 default y 683 default y
641 684
685config GENERIC_CMOS_UPDATE
686 bool
687 default y
688
642config SCHED_NO_NO_OMIT_FRAME_POINTER 689config SCHED_NO_NO_OMIT_FRAME_POINTER
643 bool 690 bool
644 default y 691 default y
@@ -659,6 +706,9 @@ config ARCH_MAY_HAVE_PC_FDC
659config BOOT_RAW 706config BOOT_RAW
660 bool 707 bool
661 708
709config CFE
710 bool
711
662config DMA_COHERENT 712config DMA_COHERENT
663 bool 713 bool
664 714
@@ -706,6 +756,9 @@ config MIPS_BONITO64
706config MIPS_MSC 756config MIPS_MSC
707 bool 757 bool
708 758
759config MIPS_NILE4
760 bool
761
709config MIPS_DISABLE_OBSOLETE_IDE 762config MIPS_DISABLE_OBSOLETE_IDE
710 bool 763 bool
711 764
@@ -775,6 +828,9 @@ config IRQ_MSP_CIC
775config IRQ_TXX9 828config IRQ_TXX9
776 bool 829 bool
777 830
831config IRQ_GT641XX
832 bool
833
778config MIPS_BOARDS_GEN 834config MIPS_BOARDS_GEN
779 bool 835 bool
780 836
@@ -856,6 +912,8 @@ config BOOT_ELF64
856 912
857menu "CPU selection" 913menu "CPU selection"
858 914
915source "kernel/time/Kconfig"
916
859choice 917choice
860 prompt "CPU type" 918 prompt "CPU type"
861 default CPU_R4X00 919 default CPU_R4X00
@@ -1316,6 +1374,7 @@ config MIPS_MT_SMTC
1316 depends on CPU_MIPS32_R2 1374 depends on CPU_MIPS32_R2
1317 #depends on CPU_MIPS64_R2 # once there is hardware ... 1375 #depends on CPU_MIPS64_R2 # once there is hardware ...
1318 depends on SYS_SUPPORTS_MULTITHREADING 1376 depends on SYS_SUPPORTS_MULTITHREADING
1377 select GENERIC_CLOCKEVENTS_BROADCAST
1319 select CPU_MIPSR2_IRQ_VI 1378 select CPU_MIPSR2_IRQ_VI
1320 select CPU_MIPSR2_IRQ_EI 1379 select CPU_MIPSR2_IRQ_EI
1321 select CPU_MIPSR2_SRS 1380 select CPU_MIPSR2_SRS
@@ -1378,6 +1437,19 @@ config MIPS_MT_SMTC_IM_BACKSTOP
1378 impact on interrupt service overhead. Disable it only if you know 1437 impact on interrupt service overhead. Disable it only if you know
1379 what you are doing. 1438 what you are doing.
1380 1439
1440config MIPS_MT_SMTC_IRQAFF
1441 bool "Support IRQ affinity API"
1442 depends on MIPS_MT_SMTC
1443 default n
1444 help
1445 Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
1446 for SMTC Linux kernel. Requires platform support, of which
1447 an example can be found in the MIPS kernel i8259 and Malta
1448 platform code. It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY
1449 be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to
1450 interrupt dispatch, and should be used only if you know what
1451 you are doing.
1452
1381config MIPS_VPE_LOADER_TOM 1453config MIPS_VPE_LOADER_TOM
1382 bool "Load VPE program into memory hidden from linux" 1454 bool "Load VPE program into memory hidden from linux"
1383 depends on MIPS_VPE_LOADER 1455 depends on MIPS_VPE_LOADER
@@ -1472,6 +1544,9 @@ config CPU_HAS_SYNC
1472 depends on !CPU_R3000 1544 depends on !CPU_R3000
1473 default y 1545 default y
1474 1546
1547config GENERIC_CLOCKEVENTS_BROADCAST
1548 bool
1549
1475# 1550#
1476# Use the generic interrupt handling code in kernel/irq/: 1551# Use the generic interrupt handling code in kernel/irq/:
1477# 1552#
@@ -1762,6 +1837,7 @@ config HW_HAS_PCI
1762config PCI 1837config PCI
1763 bool "Support for PCI controller" 1838 bool "Support for PCI controller"
1764 depends on HW_HAS_PCI 1839 depends on HW_HAS_PCI
1840 select PCI_DOMAINS
1765 help 1841 help
1766 Find out whether you have a PCI motherboard. PCI is the name of a 1842 Find out whether you have a PCI motherboard. PCI is the name of a
1767 bus system, i.e. the way the CPU talks to the other stuff inside 1843 bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1775,7 +1851,6 @@ config PCI
1775 1851
1776config PCI_DOMAINS 1852config PCI_DOMAINS
1777 bool 1853 bool
1778 depends on PCI
1779 1854
1780source "drivers/pci/Kconfig" 1855source "drivers/pci/Kconfig"
1781 1856
@@ -1824,6 +1899,9 @@ config MMU
1824 bool 1899 bool
1825 default y 1900 default y
1826 1901
1902config I8253
1903 bool
1904
1827config PCSPEAKER 1905config PCSPEAKER
1828 bool 1906 bool
1829 1907
@@ -1840,21 +1918,6 @@ source "fs/Kconfig.binfmt"
1840config TRAD_SIGNALS 1918config TRAD_SIGNALS
1841 bool 1919 bool
1842 1920
1843config BUILD_ELF64
1844 bool "Use 64-bit ELF format for building"
1845 depends on 64BIT
1846 help
1847 A 64-bit kernel is usually built using the 64-bit ELF binary object
1848 format as it's one that allows arbitrary 64-bit constructs. For
1849 kernels that are loaded within the KSEG compatibility segments the
1850 32-bit ELF format can optionally be used resulting in a somewhat
1851 smaller binary, but this option is not explicitly supported by the
1852 toolchain and since binutils 2.14 it does not even work at all.
1853
1854 Say Y to use the 64-bit format or N to use the 32-bit one.
1855
1856 If unsure say Y.
1857
1858config BINFMT_IRIX 1921config BINFMT_IRIX
1859 bool "Include IRIX binary compatibility" 1922 bool "Include IRIX binary compatibility"
1860 depends on CPU_BIG_ENDIAN && 32BIT && BROKEN 1923 depends on CPU_BIG_ENDIAN && 32BIT && BROKEN
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 32c1c8fb6f98..ebd5d02a7d78 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -60,11 +60,6 @@ vmlinux-32 = vmlinux.32
60vmlinux-64 = vmlinux 60vmlinux-64 = vmlinux
61 61
62cflags-y += -mabi=64 62cflags-y += -mabi=64
63ifdef CONFIG_BUILD_ELF64
64cflags-y += $(call cc-option,-mno-explicit-relocs)
65else
66cflags-y += $(call cc-option,-msym32)
67endif
68endif 63endif
69 64
70all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) 65all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
@@ -153,7 +148,8 @@ endif
153# 148#
154# Firmware support 149# Firmware support
155# 150#
156libs-$(CONFIG_ARC) += arch/mips/arc/ 151libs-$(CONFIG_ARC) += arch/mips/fw/arc/
152libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
157libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ 153libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
158 154
159# 155#
@@ -367,6 +363,13 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
367load-$(CONFIG_BASLER_EXCITE) += 0x80100000 363load-$(CONFIG_BASLER_EXCITE) += 0x80100000
368 364
369# 365#
366# LASAT platforms
367#
368core-$(CONFIG_LASAT) += arch/mips/lasat/
369cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat
370load-$(CONFIG_LASAT) += 0xffffffff80000000
371
372#
370# Common VR41xx 373# Common VR41xx
371# 374#
372core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ 375core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
@@ -533,6 +536,13 @@ libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
533load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 536load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
534 537
535# 538#
539# Broadcom BCM47XX boards
540#
541core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
542cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
543load-$(CONFIG_BCM47XX) := 0xffffffff80001000
544
545#
536# SNI RM 546# SNI RM
537# 547#
538core-$(CONFIG_SNI_RM) += arch/mips/sni/ 548core-$(CONFIG_SNI_RM) += arch/mips/sni/
@@ -578,6 +588,26 @@ else
578JIFFIES = jiffies_64 588JIFFIES = jiffies_64
579endif 589endif
580 590
591#
592# Automatically detect the build format. By default we choose
593# the elf format according to the load address.
594# We can always force a build with a 64-bits symbol format by
595# passing 'KBUILD_SYM32=no' option to the make's command line.
596#
597ifdef CONFIG_64BIT
598 ifndef KBUILD_SYM32
599 ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0)
600 KBUILD_SYM32 = y
601 endif
602 endif
603
604 ifeq ($(KBUILD_SYM32), y)
605 ifeq ($(call cc-option-yn,-msym32), y)
606 cflags-y += -msym32 -DKBUILD_64BIT_SYM32
607 endif
608 endif
609endif
610
581AFLAGS += $(cflags-y) 611AFLAGS += $(cflags-y)
582CFLAGS += $(cflags-y) \ 612CFLAGS += $(cflags-y) \
583 -D"VMLINUX_LOAD_ADDRESS=$(load-y)" 613 -D"VMLINUX_LOAD_ADDRESS=$(load-y)"
@@ -615,6 +645,11 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
615 645
616drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 646drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
617 647
648ifdef CONFIG_LASAT
649rom.bin rom.sw: vmlinux
650 $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
651endif
652
618# 653#
619# Some machines like the Indy need 32-bit ELF binaries for booting purposes. 654# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
620# Other need ECOFF, so we build a 32-bit ELF binary for them which we then 655# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@@ -658,6 +693,7 @@ endif
658 693
659archclean: 694archclean:
660 @$(MAKE) $(clean)=arch/mips/boot 695 @$(MAKE) $(clean)=arch/mips/boot
696 @$(MAKE) $(clean)=arch/mips/lasat
661 697
662define archhelp 698define archhelp
663 echo ' vmlinux.ecoff - ECOFF boot image' 699 echo ' vmlinux.ecoff - ECOFF boot image'
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index 626de44bd888..461cf0139737 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -184,7 +184,7 @@ static dbdev_tab_t dbdev_tab[] = {
184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
185 185
186static dbdev_tab_t * 186static dbdev_tab_t *
187find_dbdev_id (u32 id) 187find_dbdev_id(u32 id)
188{ 188{
189 int i; 189 int i;
190 dbdev_tab_t *p; 190 dbdev_tab_t *p;
@@ -213,7 +213,7 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev)
213 if ( NULL != p ) 213 if ( NULL != p )
214 { 214 {
215 memcpy(p, dev, sizeof(dbdev_tab_t)); 215 memcpy(p, dev, sizeof(dbdev_tab_t));
216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); 216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
217 ret = p->dev_id; 217 ret = p->dev_id;
218 new_id++; 218 new_id++;
219#if 0 219#if 0
@@ -671,7 +671,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
671 * parts. If it is fixedin the future, these dma_cache_inv will just 671 * parts. If it is fixedin the future, these dma_cache_inv will just
672 * be nothing more than empty macros. See io.h. 672 * be nothing more than empty macros. See io.h.
673 * */ 673 * */
674 dma_cache_inv((unsigned long)buf,nbytes); 674 dma_cache_inv((unsigned long)buf, nbytes);
675 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 675 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
676 au_sync(); 676 au_sync();
677 dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); 677 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
index 0a50af7f34b8..79e0b0a51ace 100644
--- a/arch/mips/au1000/common/dbg_io.c
+++ b/arch/mips/au1000/common/dbg_io.c
@@ -53,7 +53,7 @@ typedef unsigned int uint32;
53 53
54/* memory-mapped read/write of the port */ 54/* memory-mapped read/write of the port */
55#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) 55#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
56#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y)) 56#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y))
57 57
58extern unsigned long get_au1x00_uart_baud_base(void); 58extern unsigned long get_au1x00_uart_baud_base(void);
59extern unsigned long cal_r4koff(void); 59extern unsigned long cal_r4koff(void);
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index ea6e99fbe2f7..a6640b998c6e 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -65,19 +65,6 @@
65#define EXT_INTC1_REQ1 5 /* IP 5 */ 65#define EXT_INTC1_REQ1 5 /* IP 5 */
66#define MIPS_TIMER_IP 7 /* IP 7 */ 66#define MIPS_TIMER_IP 7 /* IP 7 */
67 67
68extern void set_debug_traps(void);
69extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void);
71
72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static void end_irq(unsigned int irq_nr);
74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
76static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
77static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
78inline void local_enable_irq(unsigned int irq_nr);
79inline void local_disable_irq(unsigned int irq_nr);
80
81void (*board_init_irq)(void); 68void (*board_init_irq)(void);
82 69
83static DEFINE_SPINLOCK(irq_lock); 70static DEFINE_SPINLOCK(irq_lock);
@@ -646,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void)
646 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 633 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
647 634
648 if (pending & CAUSEF_IP7) 635 if (pending & CAUSEF_IP7)
649 mips_timer_interrupt(); 636 do_IRQ(63);
650 else if (pending & CAUSEF_IP2) 637 else if (pending & CAUSEF_IP2)
651 intc0_req0_irqdispatch(); 638 intc0_req0_irqdispatch();
652 else if (pending & CAUSEF_IP3) 639 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c
index 3901e8e04755..6f57f72a7d57 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/au1000/common/power.c
@@ -211,7 +211,7 @@ int au_sleep(void)
211 unsigned long wakeup, flags; 211 unsigned long wakeup, flags;
212 extern void save_and_sleep(void); 212 extern void save_and_sleep(void);
213 213
214 spin_lock_irqsave(&pm_lock,flags); 214 spin_lock_irqsave(&pm_lock, flags);
215 215
216 save_core_regs(); 216 save_core_regs();
217 217
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c
index de5447e83849..b8638d293cf9 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/au1000/common/reset.c
@@ -42,7 +42,7 @@ extern void (*flush_cache_all)(void);
42void au1000_restart(char *command) 42void au1000_restart(char *command)
43{ 43{
44 /* Set all integrated peripherals to disabled states */ 44 /* Set all integrated peripherals to disabled states */
45 extern void board_reset (void); 45 extern void board_reset(void);
46 u32 prid = read_c0_prid(); 46 u32 prid = read_c0_prid();
47 47
48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); 48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index a95b37773196..b212c0726125 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -50,7 +50,6 @@ extern void au1000_halt(void);
50extern void au1000_power_off(void); 50extern void au1000_power_off(void);
51extern void au1x_time_init(void); 51extern void au1x_time_init(void);
52extern void au1x_timer_setup(struct irqaction *irq); 52extern void au1x_timer_setup(struct irqaction *irq);
53extern void au1xxx_time_init(void);
54extern void set_cpuspec(void); 53extern void set_cpuspec(void);
55 54
56void __init plat_mem_setup(void) 55void __init plat_mem_setup(void)
@@ -112,7 +111,6 @@ void __init plat_mem_setup(void)
112 _machine_restart = au1000_restart; 111 _machine_restart = au1000_restart;
113 _machine_halt = au1000_halt; 112 _machine_halt = au1000_halt;
114 pm_power_off = au1000_power_off; 113 pm_power_off = au1000_power_off;
115 board_time_init = au1xxx_time_init;
116 114
117 /* IO/MEM resources. */ 115 /* IO/MEM resources. */
118 set_io_port_base(0); 116 set_io_port_base(0);
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 8fc29982d700..2556399708ba 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -64,48 +64,8 @@ static unsigned long last_pc0, last_match20;
64 64
65static DEFINE_SPINLOCK(time_lock); 65static DEFINE_SPINLOCK(time_lock);
66 66
67static inline void ack_r4ktimer(unsigned long newval)
68{
69 write_c0_compare(newval);
70}
71
72/*
73 * There are a lot of conceptually broken versions of the MIPS timer interrupt
74 * handler floating around. This one is rather different, but the algorithm
75 * is provably more robust.
76 */
77unsigned long wtimer; 67unsigned long wtimer;
78 68
79void mips_timer_interrupt(void)
80{
81 int irq = 63;
82
83 irq_enter();
84 kstat_this_cpu.irqs[irq]++;
85
86 if (r4k_offset == 0)
87 goto null;
88
89 do {
90 kstat_this_cpu.irqs[irq]++;
91 do_timer(1);
92#ifndef CONFIG_SMP
93 update_process_times(user_mode(get_irq_regs()));
94#endif
95 r4k_cur += r4k_offset;
96 ack_r4ktimer(r4k_cur);
97
98 } while (((unsigned long)read_c0_count()
99 - r4k_cur) < 0x7fffffff);
100
101 irq_exit();
102 return;
103
104null:
105 ack_r4ktimer(0);
106 irq_exit();
107}
108
109#ifdef CONFIG_PM 69#ifdef CONFIG_PM
110irqreturn_t counter0_irq(int irq, void *dev_id) 70irqreturn_t counter0_irq(int irq, void *dev_id)
111{ 71{
@@ -240,7 +200,7 @@ unsigned long cal_r4koff(void)
240 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); 200 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
241 201
242 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 202 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
243 au_writel (0, SYS_TOYWRITE); 203 au_writel(0, SYS_TOYWRITE);
244 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 204 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
245 205
246 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 206 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
@@ -329,7 +289,3 @@ void __init plat_timer_setup(struct irqaction *irq)
329 289
330#endif 290#endif
331} 291}
332
333void __init au1xxx_time_init(void)
334{
335}
diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/au1000/db1x00/board_setup.c
index 8b08edb977be..99eafeada518 100644
--- a/arch/mips/au1000/db1x00/board_setup.c
+++ b/arch/mips/au1000/db1x00/board_setup.c
@@ -46,7 +46,7 @@
46 46
47static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 47static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
48 48
49void board_reset (void) 49void board_reset(void)
50{ 50{
51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
52 bcsr->swreset = 0x0000; 52 bcsr->swreset = 0x0000;
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 0a3f025eb023..4d7bcfc8cf73 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -59,14 +59,12 @@ void __init prom_init(void)
59 prom_argv = (char **) fw_arg1; 59 prom_argv = (char **) fw_arg1;
60 prom_envp = (char **) fw_arg2; 60 prom_envp = (char **) fw_arg2;
61 61
62 mips_machgroup = MACH_GROUP_ALCHEMY;
63
64 /* Set the platform # */ 62 /* Set the platform # */
65#if defined (CONFIG_MIPS_DB1550) 63#if defined(CONFIG_MIPS_DB1550)
66 mips_machtype = MACH_DB1550; 64 mips_machtype = MACH_DB1550;
67#elif defined (CONFIG_MIPS_DB1500) 65#elif defined(CONFIG_MIPS_DB1500)
68 mips_machtype = MACH_DB1500; 66 mips_machtype = MACH_DB1500;
69#elif defined (CONFIG_MIPS_DB1100) 67#elif defined(CONFIG_MIPS_DB1100)
70 mips_machtype = MACH_DB1100; 68 mips_machtype = MACH_DB1100;
71#else 69#else
72 mips_machtype = MACH_DB1000; 70 mips_machtype = MACH_DB1000;
diff --git a/arch/mips/au1000/mtx-1/board_setup.c b/arch/mips/au1000/mtx-1/board_setup.c
index 2c460c116570..abfc4bcddf7a 100644
--- a/arch/mips/au1000/mtx-1/board_setup.c
+++ b/arch/mips/au1000/mtx-1/board_setup.c
@@ -46,7 +46,7 @@
46extern int (*board_pci_idsel)(unsigned int devsel, int assert); 46extern int (*board_pci_idsel)(unsigned int devsel, int assert);
47int mtx1_pci_idsel(unsigned int devsel, int assert); 47int mtx1_pci_idsel(unsigned int devsel, int assert);
48 48
49void board_reset (void) 49void board_reset(void)
50{ 50{
51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
52 au_writel(0x00000000, 0xAE00001C); 52 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c
index 88f2b6d97281..2aa7b2ed6a8c 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/au1000/mtx-1/init.c
@@ -56,7 +56,6 @@ void __init prom_init(void)
56 prom_argv = (char **) fw_arg1; 56 prom_argv = (char **) fw_arg1;
57 prom_envp = (char **) fw_arg2; 57 prom_envp = (char **) fw_arg2;
58 58
59 mips_machgroup = MACH_GROUP_ALCHEMY;
60 mips_machtype = MACH_MTX1; /* set the platform # */ 59 mips_machtype = MACH_MTX1; /* set the platform # */
61 60
62 prom_init_cmdline(); 61 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 0aed89114bfc..5198c4f98b43 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1000.h> 40#include <asm/mach-pb1x00/pb1000.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44} 44}
45 45
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index e9fa1bab81f3..4535f7208e18 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -54,7 +54,6 @@ void __init prom_init(void)
54 prom_argv = (char **) fw_arg1; 54 prom_argv = (char **) fw_arg1;
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machgroup = MACH_GROUP_ALCHEMY;
58 mips_machtype = MACH_PB1000; 57 mips_machtype = MACH_PB1000;
59 58
60 prom_init_cmdline(); 59 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/au1000/pb1100/board_setup.c
index 259ca05860c3..42874a6b31d1 100644
--- a/arch/mips/au1000/pb1100/board_setup.c
+++ b/arch/mips/au1000/pb1100/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1100.h> 40#include <asm/mach-pb1x00/pb1100.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c
index 6131b56f41b5..7ba6852de7cd 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/au1000/pb1100/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg3; 56 prom_envp = (char **) fw_arg3;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1100; 58 mips_machtype = MACH_PB1100;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index eea2092bde8d..2122515f79d7 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -57,7 +57,7 @@
57extern void _board_init_irq(void); 57extern void _board_init_irq(void);
58extern void (*board_init_irq)(void); 58extern void (*board_init_irq)(void);
59 59
60void board_reset (void) 60void board_reset(void)
61{ 61{
62 bcsr->resets = 0; 62 bcsr->resets = 0;
63 bcsr->system = 0; 63 bcsr->system = 0;
@@ -148,7 +148,7 @@ void __init board_setup(void)
148} 148}
149 149
150int 150int
151board_au1200fb_panel (void) 151board_au1200fb_panel(void)
152{ 152{
153 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 153 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
154 int p; 154 int p;
@@ -160,7 +160,7 @@ board_au1200fb_panel (void)
160} 160}
161 161
162int 162int
163board_au1200fb_panel_init (void) 163board_au1200fb_panel_init(void)
164{ 164{
165 /* Apply power */ 165 /* Apply power */
166 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 166 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
@@ -170,7 +170,7 @@ board_au1200fb_panel_init (void)
170} 170}
171 171
172int 172int
173board_au1200fb_panel_shutdown (void) 173board_au1200fb_panel_shutdown(void)
174{ 174{
175 /* Remove power */ 175 /* Remove power */
176 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 176 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
index 27f09e374e15..5a70029d5388 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/au1000/pb1200/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2; 56 prom_envp = (char **) fw_arg2;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1200; 58 mips_machtype = MACH_PB1200;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index b73b2d18bf56..7c708db04a88 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -132,7 +132,7 @@ static void pb1200_shutdown_irq( unsigned int irq_nr )
132 pb1200_disable_irq(irq_nr); 132 pb1200_disable_irq(irq_nr);
133 if (--pb1200_cascade_en == 0) 133 if (--pb1200_cascade_en == 0)
134 { 134 {
135 free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); 135 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler );
136 } 136 }
137 return; 137 return;
138} 138}
diff --git a/arch/mips/au1000/pb1500/board_setup.c b/arch/mips/au1000/pb1500/board_setup.c
index a2d850db8902..5446836869d6 100644
--- a/arch/mips/au1000/pb1500/board_setup.c
+++ b/arch/mips/au1000/pb1500/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1500.h> 40#include <asm/mach-pb1x00/pb1500.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/au1000/pb1500/init.c
index 733d2e469db2..e58a9d6c5021 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/au1000/pb1500/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2; 56 prom_envp = (char **) fw_arg2;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1500; 58 mips_machtype = MACH_PB1500;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/au1000/pb1550/board_setup.c
index 05fd27dc24e6..e3cfb0d73180 100644
--- a/arch/mips/au1000/pb1550/board_setup.c
+++ b/arch/mips/au1000/pb1550/board_setup.c
@@ -44,7 +44,7 @@
44#include <asm/mach-au1x00/au1000.h> 44#include <asm/mach-au1x00/au1000.h>
45#include <asm/mach-pb1x00/pb1550.h> 45#include <asm/mach-pb1x00/pb1550.h>
46 46
47void board_reset (void) 47void board_reset(void)
48{ 48{
49 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 49 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
50 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C); 50 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C);
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c
index 41daa3371be3..fad53bf5aad1 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/au1000/pb1550/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2; 56 prom_envp = (char **) fw_arg2;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1550; 58 mips_machtype = MACH_PB1550;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index ae3d6b19e94d..a9237f41933d 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/pgtable.h> 39#include <asm/pgtable.h>
40#include <asm/au1000.h> 40#include <asm/au1000.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index f1c76533b6fc..9f839c36f69e 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -54,7 +54,6 @@ void __init prom_init(void)
54 prom_argv = (char **) fw_arg1; 54 prom_argv = (char **) fw_arg1;
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machgroup = MACH_GROUP_ALCHEMY;
58 mips_machtype = MACH_XXS1500; /* set the platform # */ 57 mips_machtype = MACH_XXS1500; /* set the platform # */
59 58
60 prom_init_cmdline(); 59 prom_init_cmdline();
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
index 6ecd512b999d..2d752c2f6e59 100644
--- a/arch/mips/basler/excite/excite_prom.c
+++ b/arch/mips/basler/excite/excite_prom.c
@@ -136,7 +136,6 @@ void __init prom_init(void)
136# error 64 bit support not implemented 136# error 64 bit support not implemented
137#endif /* CONFIG_64BIT */ 137#endif /* CONFIG_64BIT */
138 138
139 mips_machgroup = MACH_GROUP_TITAN;
140 mips_machtype = MACH_TITAN_EXCITE; 139 mips_machtype = MACH_TITAN_EXCITE;
141} 140}
142 141
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 56003188f17c..404ca9284b30 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -68,7 +68,7 @@ DEFINE_SPINLOCK(titan_lock);
68int titan_irqflags; 68int titan_irqflags;
69 69
70 70
71static void excite_timer_init(void) 71void __init plat_time_init(void)
72{ 72{
73 const u32 modebit5 = ocd_readl(0x00e4); 73 const u32 modebit5 = ocd_readl(0x00e4);
74 unsigned int 74 unsigned int
@@ -216,7 +216,7 @@ static int __init excite_platform_init(void)
216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */ 216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
217 titan_writel(0x00000000, CPXCISRA); 217 titan_writel(0x00000000, CPXCISRA);
218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */ 218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
219#if defined (CONFIG_HIGHMEM) 219#if defined(CONFIG_HIGHMEM)
220# error change for HIGHMEM support! 220# error change for HIGHMEM support!
221#else 221#else
222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */ 222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
@@ -261,16 +261,13 @@ void __init plat_mem_setup(void)
261 /* Announce RAM to system */ 261 /* Announce RAM to system */
262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); 262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
263 263
264 /* Set up timer initialization hooks */
265 board_time_init = excite_timer_init;
266
267 /* Set up the peripheral address map */ 264 /* Set up the peripheral address map */
268 *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; 265 *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
269 *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; 266 *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
270 *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0; 267 *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
271 *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0; 268 *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
272 wmb(); 269 wmb();
273 *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4; 270 *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
274 wmb(); 271 wmb();
275 272
276 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5); 273 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
new file mode 100644
index 000000000000..35294b12d638
--- /dev/null
+++ b/arch/mips/bcm47xx/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the BCM47XX specific kernel interface routines
3# under Linux.
4#
5
6obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c
new file mode 100644
index 000000000000..f5a53acf995a
--- /dev/null
+++ b/arch/mips/bcm47xx/gpio.c
@@ -0,0 +1,79 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/ssb/ssb.h>
10#include <linux/ssb/ssb_driver_chipcommon.h>
11#include <linux/ssb/ssb_driver_extif.h>
12#include <asm/mach-bcm47xx/bcm47xx.h>
13#include <asm/mach-bcm47xx/gpio.h>
14
15int bcm47xx_gpio_to_irq(unsigned gpio)
16{
17 if (ssb_bcm47xx.chipco.dev)
18 return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2;
19 else if (ssb_bcm47xx.extif.dev)
20 return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2;
21 else
22 return -EINVAL;
23}
24EXPORT_SYMBOL_GPL(bcm47xx_gpio_to_irq);
25
26int bcm47xx_gpio_get_value(unsigned gpio)
27{
28 if (ssb_bcm47xx.chipco.dev)
29 return ssb_chipco_gpio_in(&ssb_bcm47xx.chipco, 1 << gpio);
30 else if (ssb_bcm47xx.extif.dev)
31 return ssb_extif_gpio_in(&ssb_bcm47xx.extif, 1 << gpio);
32 else
33 return 0;
34}
35EXPORT_SYMBOL_GPL(bcm47xx_gpio_get_value);
36
37void bcm47xx_gpio_set_value(unsigned gpio, int value)
38{
39 if (ssb_bcm47xx.chipco.dev)
40 ssb_chipco_gpio_out(&ssb_bcm47xx.chipco,
41 1 << gpio,
42 value ? 1 << gpio : 0);
43 else if (ssb_bcm47xx.extif.dev)
44 ssb_extif_gpio_out(&ssb_bcm47xx.extif,
45 1 << gpio,
46 value ? 1 << gpio : 0);
47}
48EXPORT_SYMBOL_GPL(bcm47xx_gpio_set_value);
49
50int bcm47xx_gpio_direction_input(unsigned gpio)
51{
52 if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
53 ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
54 1 << gpio, 0);
55 else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
56 ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
57 1 << gpio, 0);
58 else
59 return -EINVAL;
60 return 0;
61}
62EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_input);
63
64int bcm47xx_gpio_direction_output(unsigned gpio, int value)
65{
66 bcm47xx_gpio_set_value(gpio, value);
67
68 if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
69 ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
70 1 << gpio, 1 << gpio);
71 else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
72 ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
73 1 << gpio, 1 << gpio);
74 else
75 return -EINVAL;
76 return 0;
77}
78EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
79
diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c
new file mode 100644
index 000000000000..325757acd020
--- /dev/null
+++ b/arch/mips/bcm47xx/irq.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <asm/irq_cpu.h>
29
30void plat_irq_dispatch(void)
31{
32 u32 cause;
33
34 cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
35
36 clear_c0_status(cause);
37
38 if (cause & CAUSEF_IP7)
39 do_IRQ(7);
40 if (cause & CAUSEF_IP2)
41 do_IRQ(2);
42 if (cause & CAUSEF_IP3)
43 do_IRQ(3);
44 if (cause & CAUSEF_IP4)
45 do_IRQ(4);
46 if (cause & CAUSEF_IP5)
47 do_IRQ(5);
48 if (cause & CAUSEF_IP6)
49 do_IRQ(6);
50}
51
52void __init arch_init_irq(void)
53{
54 mips_cpu_irq_init();
55}
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
new file mode 100644
index 000000000000..079e33d52783
--- /dev/null
+++ b/arch/mips/bcm47xx/prom.c
@@ -0,0 +1,158 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/spinlock.h>
30#include <asm/bootinfo.h>
31#include <asm/fw/cfe/cfe_api.h>
32#include <asm/fw/cfe/cfe_error.h>
33
34static int cfe_cons_handle;
35
36const char *get_system_type(void)
37{
38 return "Broadcom BCM47XX";
39}
40
41void prom_putchar(char c)
42{
43 while (cfe_write(cfe_cons_handle, &c, 1) == 0)
44 ;
45}
46
47static __init void prom_init_cfe(void)
48{
49 uint32_t cfe_ept;
50 uint32_t cfe_handle;
51 uint32_t cfe_eptseal;
52 int argc = fw_arg0;
53 char **envp = (char **) fw_arg2;
54 int *prom_vec = (int *) fw_arg3;
55
56 /*
57 * Check if a loader was used; if NOT, the 4 arguments are
58 * what CFE gives us (handle, 0, EPT and EPTSEAL)
59 */
60 if (argc < 0) {
61 cfe_handle = (uint32_t)argc;
62 cfe_ept = (uint32_t)envp;
63 cfe_eptseal = (uint32_t)prom_vec;
64 } else {
65 if ((int)prom_vec < 0) {
66 /*
67 * Old loader; all it gives us is the handle,
68 * so use the "known" entrypoint and assume
69 * the seal.
70 */
71 cfe_handle = (uint32_t)prom_vec;
72 cfe_ept = 0xBFC00500;
73 cfe_eptseal = CFE_EPTSEAL;
74 } else {
75 /*
76 * Newer loaders bundle the handle/ept/eptseal
77 * Note: prom_vec is in the loader's useg
78 * which is still alive in the TLB.
79 */
80 cfe_handle = prom_vec[0];
81 cfe_ept = prom_vec[2];
82 cfe_eptseal = prom_vec[3];
83 }
84 }
85
86 if (cfe_eptseal != CFE_EPTSEAL) {
87 /* too early for panic to do any good */
88 printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
89 while (1) ;
90 }
91
92 cfe_init(cfe_handle, cfe_ept);
93}
94
95static __init void prom_init_console(void)
96{
97 /* Initialize CFE console */
98 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
99}
100
101static __init void prom_init_cmdline(void)
102{
103 char buf[CL_SIZE];
104
105 /* Get the kernel command line from CFE */
106 if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
107 buf[CL_SIZE-1] = 0;
108 strcpy(arcs_cmdline, buf);
109 }
110
111 /* Force a console handover by adding a console= argument if needed,
112 * as CFE is not available anymore later in the boot process. */
113 if ((strstr(arcs_cmdline, "console=")) == NULL) {
114 /* Try to read the default serial port used by CFE */
115 if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
116 || (strncmp("uart", buf, 4)))
117 /* Default to uart0 */
118 strcpy(buf, "uart0");
119
120 /* Compute the new command line */
121 snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
122 arcs_cmdline, buf[4]);
123 }
124}
125
126static __init void prom_init_mem(void)
127{
128 unsigned long mem;
129
130 /* Figure out memory size by finding aliases.
131 *
132 * We should theoretically use the mapping from CFE using cfe_enummem().
133 * However as the BCM47XX is mostly used on low-memory systems, we
134 * want to reuse the memory used by CFE (around 4MB). That means cfe_*
135 * functions stop to work at some point during the boot, we should only
136 * call them at the beginning of the boot.
137 */
138 for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
139 if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
140 *(unsigned long *)(prom_init))
141 break;
142 }
143
144 add_memory_region(0, mem, BOOT_MEM_RAM);
145}
146
147void __init prom_init(void)
148{
149 prom_init_cfe();
150 prom_init_console();
151 prom_init_cmdline();
152 prom_init_mem();
153}
154
155void __init prom_free_prom_memory(void)
156{
157}
158
diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c
new file mode 100644
index 000000000000..59c11afdb2ab
--- /dev/null
+++ b/arch/mips/bcm47xx/serial.c
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial.h>
12#include <linux/serial_8250.h>
13#include <linux/ssb/ssb.h>
14#include <bcm47xx.h>
15
16static struct plat_serial8250_port uart8250_data[5];
17
18static struct platform_device uart8250_device = {
19 .name = "serial8250",
20 .id = PLAT8250_DEV_PLATFORM,
21 .dev = {
22 .platform_data = uart8250_data,
23 },
24};
25
26static int __init uart8250_init(void)
27{
28 int i;
29 struct ssb_mipscore *mcore = &(ssb_bcm47xx.mipscore);
30
31 memset(&uart8250_data, 0, sizeof(uart8250_data));
32
33 for (i = 0; i < mcore->nr_serial_ports; i++) {
34 struct plat_serial8250_port *p = &(uart8250_data[i]);
35 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
36
37 p->mapbase = (unsigned int) ssb_port->regs;
38 p->membase = (void *) ssb_port->regs;
39 p->irq = ssb_port->irq + 2;
40 p->uartclk = ssb_port->baud_base;
41 p->regshift = ssb_port->reg_shift;
42 p->iotype = UPIO_MEM;
43 p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
44 }
45 return platform_device_register(&uart8250_device);
46}
47
48module_init(uart8250_init);
49
50MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
51MODULE_LICENSE("GPL");
52MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms");
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
new file mode 100644
index 000000000000..1b6b0fa5028f
--- /dev/null
+++ b/arch/mips/bcm47xx/setup.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/types.h>
29#include <linux/ssb/ssb.h>
30#include <asm/bootinfo.h>
31#include <asm/reboot.h>
32#include <asm/time.h>
33#include <bcm47xx.h>
34#include <asm/fw/cfe/cfe_api.h>
35
36struct ssb_bus ssb_bcm47xx;
37EXPORT_SYMBOL(ssb_bcm47xx);
38
39static void bcm47xx_machine_restart(char *command)
40{
41 printk(KERN_ALERT "Please stand by while rebooting the system...\n");
42 local_irq_disable();
43 /* Set the watchdog timer to reset immediately */
44 ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
45 while (1)
46 cpu_relax();
47}
48
49static void bcm47xx_machine_halt(void)
50{
51 /* Disable interrupts and watchdog and spin forever */
52 local_irq_disable();
53 ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
54 while (1)
55 cpu_relax();
56}
57
58static void str2eaddr(char *str, char *dest)
59{
60 int i = 0;
61
62 if (str == NULL) {
63 memset(dest, 0, 6);
64 return;
65 }
66
67 for (;;) {
68 dest[i++] = (char) simple_strtoul(str, NULL, 16);
69 str += 2;
70 if (!*str++ || i == 6)
71 break;
72 }
73}
74
75static int bcm47xx_get_invariants(struct ssb_bus *bus,
76 struct ssb_init_invariants *iv)
77{
78 char buf[100];
79
80 /* Fill boardinfo structure */
81 memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
82
83 if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
84 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
85 if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
86 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
87 if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
88 iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
89
90 /* Fill sprom structure */
91 memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
92 iv->sprom.revision = 3;
93
94 if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
95 str2eaddr(buf, iv->sprom.r1.et0mac);
96 if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
97 str2eaddr(buf, iv->sprom.r1.et1mac);
98 if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
99 iv->sprom.r1.et0phyaddr = simple_strtoul(buf, NULL, 10);
100 if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
101 iv->sprom.r1.et1phyaddr = simple_strtoul(buf, NULL, 10);
102 if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
103 iv->sprom.r1.et0mdcport = simple_strtoul(buf, NULL, 10);
104 if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
105 iv->sprom.r1.et1mdcport = simple_strtoul(buf, NULL, 10);
106
107 return 0;
108}
109
110void __init plat_mem_setup(void)
111{
112 int err;
113
114 err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
115 bcm47xx_get_invariants);
116 if (err)
117 panic("Failed to initialize SSB bus (err %d)\n", err);
118
119 _machine_restart = bcm47xx_machine_restart;
120 _machine_halt = bcm47xx_machine_halt;
121 pm_power_off = bcm47xx_machine_halt;
122}
123
diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
new file mode 100644
index 000000000000..0ab4676c8bd3
--- /dev/null
+++ b/arch/mips/bcm47xx/time.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25
26#include <linux/init.h>
27#include <linux/ssb/ssb.h>
28#include <asm/time.h>
29#include <bcm47xx.h>
30
31void __init plat_time_init(void)
32{
33 unsigned long hz;
34
35 /*
36 * Use deterministic values for initial counter interrupt
37 * so that calibrate delay avoids encountering a counter wrap.
38 */
39 write_c0_count(0);
40 write_c0_compare(0xffff);
41
42 hz = ssb_cpu_clock(&ssb_bcm47xx.mipscore) / 2;
43 if (!hz)
44 hz = 100000000;
45
46 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
47 mips_hpt_frequency = hz;
48}
49
50void __init
51plat_timer_setup(struct irqaction *irq)
52{
53 /* Enable the timer interrupt */
54 setup_irq(7, irq);
55}
diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c
new file mode 100644
index 000000000000..5a017eaee712
--- /dev/null
+++ b/arch/mips/bcm47xx/wgt634u.c
@@ -0,0 +1,64 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/leds.h>
12#include <linux/ssb/ssb.h>
13#include <asm/mach-bcm47xx/bcm47xx.h>
14
15/* GPIO definitions for the WGT634U */
16#define WGT634U_GPIO_LED 3
17#define WGT634U_GPIO_RESET 2
18#define WGT634U_GPIO_TP1 7
19#define WGT634U_GPIO_TP2 6
20#define WGT634U_GPIO_TP3 5
21#define WGT634U_GPIO_TP4 4
22#define WGT634U_GPIO_TP5 1
23
24static struct gpio_led wgt634u_leds[] = {
25 {
26 .name = "power",
27 .gpio = WGT634U_GPIO_LED,
28 .active_low = 1,
29 .default_trigger = "heartbeat",
30 },
31};
32
33static struct gpio_led_platform_data wgt634u_led_data = {
34 .num_leds = ARRAY_SIZE(wgt634u_leds),
35 .leds = wgt634u_leds,
36};
37
38static struct platform_device wgt634u_gpio_leds = {
39 .name = "leds-gpio",
40 .id = -1,
41 .dev = {
42 .platform_data = &wgt634u_led_data,
43 }
44};
45
46static int __init wgt634u_init(void)
47{
48 /* There is no easy way to detect that we are running on a WGT634U
49 * machine. Use the MAC address as an heuristic. Netgear Inc. has
50 * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
51 */
52
53 u8 *et0mac = ssb_bcm47xx.sprom.r1.et0mac;
54
55 if (et0mac[0] == 0x00 &&
56 ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
57 (et0mac[1] == 0x0f && et0mac[2] == 0xb5)))
58 return platform_device_register(&wgt634u_gpio_leds);
59 else
60 return -ENODEV;
61}
62
63module_init(wgt634u_init);
64
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
index 8b3033304770..b5b3febc10cc 100644
--- a/arch/mips/boot/addinitrd.c
+++ b/arch/mips/boot/addinitrd.c
@@ -32,15 +32,15 @@
32 32
33#define SWAB(a) (swab ? swab32(a) : (a)) 33#define SWAB(a) (swab ? swab32(a) : (a))
34 34
35void die (char *s) 35void die(char *s)
36{ 36{
37 perror (s); 37 perror(s);
38 exit (1); 38 exit(1);
39} 39}
40 40
41int main (int argc, char *argv[]) 41int main(int argc, char *argv[])
42{ 42{
43 int fd_vmlinux,fd_initrd,fd_outfile; 43 int fd_vmlinux, fd_initrd, fd_outfile;
44 FILHDR efile; 44 FILHDR efile;
45 AOUTHDR eaout; 45 AOUTHDR eaout;
46 SCNHDR esecs[3]; 46 SCNHDR esecs[3];
@@ -48,22 +48,22 @@ int main (int argc, char *argv[])
48 char buf[1024]; 48 char buf[1024];
49 unsigned long loadaddr; 49 unsigned long loadaddr;
50 unsigned long initrd_header[2]; 50 unsigned long initrd_header[2];
51 int i,cnt; 51 int i, cnt;
52 int swab = 0; 52 int swab = 0;
53 53
54 if (argc != 4) { 54 if (argc != 4) {
55 printf ("Usage: %s <vmlinux> <initrd> <outfile>\n",argv[0]); 55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
56 exit (1); 56 exit(1);
57 } 57 }
58 58
59 if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0) 59 if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
60 die ("open vmlinux"); 60 die("open vmlinux");
61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) 61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62 die ("read file header"); 62 die("read file header");
63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout) 63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
64 die ("read aout header"); 64 die("read aout header");
65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs) 65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
66 die ("read section headers"); 66 die("read section headers");
67 /* 67 /*
68 * check whether the file is good for us 68 * check whether the file is good for us
69 */ 69 */
@@ -82,13 +82,13 @@ int main (int argc, char *argv[])
82 82
83 /* make sure we have an empty data segment for the initrd */ 83 /* make sure we have an empty data segment for the initrd */
84 if (eaout.dsize || esecs[1].s_size) { 84 if (eaout.dsize || esecs[1].s_size) {
85 fprintf (stderr, "Data segment not empty. Giving up!\n"); 85 fprintf(stderr, "Data segment not empty. Giving up!\n");
86 exit (1); 86 exit(1);
87 } 87 }
88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0) 88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
89 die ("open initrd"); 89 die("open initrd");
90 if (fstat (fd_initrd, &st) < 0) 90 if (fstat (fd_initrd, &st) < 0)
91 die ("fstat initrd"); 91 die("fstat initrd");
92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) 92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8; 93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size))) 94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
@@ -98,34 +98,34 @@ int main (int argc, char *argv[])
98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8); 98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); 99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100 100
101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0) 101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
102 die ("open outfile"); 102 die("open outfile");
103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) 103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104 die ("write file header"); 104 die("write file header");
105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout) 105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
106 die ("write aout header"); 106 die("write aout header");
107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs) 107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
108 die ("write section headers"); 108 die("write section headers");
109 /* skip padding */ 109 /* skip padding */
110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) 110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
111 die ("lseek vmlinux"); 111 die("lseek vmlinux");
112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) 112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
113 die ("lseek outfile"); 113 die("lseek outfile");
114 /* copy text segment */ 114 /* copy text segment */
115 cnt = SWAB(eaout.tsize); 115 cnt = SWAB(eaout.tsize);
116 while (cnt) { 116 while (cnt) {
117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0) 117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
118 die ("read vmlinux"); 118 die("read vmlinux");
119 if (write (fd_outfile, buf, i) != i) 119 if (write (fd_outfile, buf, i) != i)
120 die ("write vmlinux"); 120 die("write vmlinux");
121 cnt -= i; 121 cnt -= i;
122 } 122 }
123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header) 123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
124 die ("write initrd header"); 124 die("write initrd header");
125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0) 125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
126 if (write (fd_outfile, buf, i) != i) 126 if (write (fd_outfile, buf, i) != i)
127 die ("write initrd"); 127 die("write initrd");
128 close (fd_vmlinux); 128 close(fd_vmlinux);
129 close (fd_initrd); 129 close(fd_initrd);
130 return 0; 130 return 0;
131} 131}
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index c3543d9eb266..c5a7f308c405 100644
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -467,7 +467,7 @@ int main(int argc, char *argv[])
467 esecs[0].s_scnptr = N_TXTOFF(efh, eah); 467 esecs[0].s_scnptr = N_TXTOFF(efh, eah);
468 esecs[1].s_scnptr = N_DATOFF(efh, eah); 468 esecs[1].s_scnptr = N_DATOFF(efh, eah);
469#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10 469#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10
470#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1)) 470#define ECOFF_ROUND(s, a) (((s)+(a)-1)&~((a)-1))
471 esecs[2].s_scnptr = esecs[1].s_scnptr + 471 esecs[2].s_scnptr = esecs[1].s_scnptr +
472 ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah)); 472 ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah));
473 if (addflag) { 473 if (addflag) {
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index a043f93f7d08..6b83f4ddc8fc 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the Cobalt micro systems family specific parts of the kernel 2# Makefile for the Cobalt micro systems family specific parts of the kernel
3# 3#
4 4
5obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o 5obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o
6 6
7obj-$(CONFIG_PCI) += pci.o 7obj-$(CONFIG_PCI) += pci.o
8obj-$(CONFIG_EARLY_PRINTK) += console.o 8obj-$(CONFIG_EARLY_PRINTK) += console.o
diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c
index 0485d51f7216..db330e811025 100644
--- a/arch/mips/cobalt/console.c
+++ b/arch/mips/cobalt/console.c
@@ -1,16 +1,15 @@
1/* 1/*
2 * (C) P. Horton 2006 2 * (C) P. Horton 2006
3 */ 3 */
4#include <linux/io.h>
4#include <linux/serial_reg.h> 5#include <linux/serial_reg.h>
5 6
6#include <asm/addrspace.h> 7#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
7
8#include <cobalt.h>
9 8
10void prom_putchar(char c) 9void prom_putchar(char c)
11{ 10{
12 while(!(COBALT_UART[UART_LSR] & UART_LSR_THRE)) 11 while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE))
13 ; 12 ;
14 13
15 COBALT_UART[UART_TX] = c; 14 writeb(c, UART_BASE + UART_TX);
16} 15}
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 950ad1e8be44..ac4fb912649d 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -15,102 +15,48 @@
15 15
16#include <asm/i8259.h> 16#include <asm/i8259.h>
17#include <asm/irq_cpu.h> 17#include <asm/irq_cpu.h>
18#include <asm/irq_gt641xx.h>
18#include <asm/gt64120.h> 19#include <asm/gt64120.h>
19 20
20#include <cobalt.h> 21#include <irq.h>
21
22/*
23 * We have two types of interrupts that we handle, ones that come in through
24 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
25 * mappings are:
26 *
27 * 16 - Software interrupt 0 (unused) IE_SW0
28 * 17 - Software interrupt 1 (unused) IE_SW1
29 * 18 - Galileo chip (timer) IE_IRQ0
30 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
31 * 20 - Tulip 1 IE_IRQ2
32 * 21 - 16550 UART IE_IRQ3
33 * 22 - VIA southbridge PIC IE_IRQ4
34 * 23 - unused IE_IRQ5
35 *
36 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
37 *
38 * 8 - RTC
39 * 9 - PCI
40 * 14 - IDE0
41 * 15 - IDE1
42 */
43
44static inline void galileo_irq(void)
45{
46 unsigned int mask, pending, devfn;
47
48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50
51 if (pending & GT_INTR_T0EXP_MSK) {
52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 do_IRQ(COBALT_GALILEO_IRQ);
54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
57 printk(KERN_WARNING
58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
59 PCI_SLOT(devfn), PCI_FUNC(devfn));
60 } else {
61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
62 printk(KERN_WARNING
63 "Galileo: masking unexpected interrupt %08x\n", pending);
64 }
65}
66
67static inline void via_pic_irq(void)
68{
69 int irq;
70
71 irq = i8259_irq();
72 if (irq >= 0)
73 do_IRQ(irq);
74}
75 22
76asmlinkage void plat_irq_dispatch(void) 23asmlinkage void plat_irq_dispatch(void)
77{ 24{
78 unsigned pending = read_c0_status() & read_c0_cause(); 25 unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
26 int irq;
79 27
80 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ 28 if (pending & CAUSEF_IP2)
81 galileo_irq(); 29 gt641xx_irq_dispatch();
82 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ 30 else if (pending & CAUSEF_IP6) {
83 via_pic_irq(); 31 irq = i8259_irq();
84 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ 32 if (irq < 0)
85 do_IRQ(COBALT_CPU_IRQ + 3); 33 spurious_interrupt();
86 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ 34 else
87 do_IRQ(COBALT_CPU_IRQ + 4); 35 do_IRQ(irq);
88 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ 36 } else if (pending & CAUSEF_IP3)
89 do_IRQ(COBALT_CPU_IRQ + 5); 37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
90 else if (pending & CAUSEF_IP7) /* IRQ 23 */ 38 else if (pending & CAUSEF_IP4)
91 do_IRQ(COBALT_CPU_IRQ + 7); 39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
40 else if (pending & CAUSEF_IP5)
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
42 else if (pending & CAUSEF_IP7)
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
44 else
45 spurious_interrupt();
92} 46}
93 47
94static struct irqaction irq_via = { 48static struct irqaction cascade = {
95 no_action, 0, { { 0, } }, "cascade", NULL, NULL 49 .handler = no_action,
50 .mask = CPU_MASK_NONE,
51 .name = "cascade",
96}; 52};
97 53
98void __init arch_init_irq(void) 54void __init arch_init_irq(void)
99{ 55{
100 /* 56 mips_cpu_irq_init();
101 * Mask all Galileo interrupts. The Galileo 57 gt641xx_irq_init();
102 * handler is set in cobalt_timer_setup() 58 init_i8259_irqs();
103 */
104 GT_WRITE(GT_INTRMASK_OFS, 0);
105
106 init_i8259_irqs(); /* 0 ... 15 */
107 mips_cpu_irq_init(); /* 16 ... 23 */
108
109 /*
110 * Mask all cpu interrupts
111 * (except IE4, we already masked those at VIA level)
112 */
113 change_c0_status(ST0_IM, IE_IRQ4);
114 59
115 setup_irq(COBALT_VIA_IRQ, &irq_via); 60 setup_irq(GT641XX_CASCADE_IRQ, &cascade);
61 setup_irq(I8259_CASCADE_IRQ, &cascade);
116} 62}
diff --git a/arch/mips/cobalt/led.c b/arch/mips/cobalt/led.c
new file mode 100644
index 000000000000..1c6ebd468b07
--- /dev/null
+++ b/arch/mips/cobalt/led.c
@@ -0,0 +1,62 @@
1/*
2 * Registration of Cobalt LED platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24
25#include <cobalt.h>
26
27static struct resource cobalt_led_resource __initdata = {
28 .start = 0x1c000000,
29 .end = 0x1c000000,
30 .flags = IORESOURCE_MEM,
31};
32
33static __init int cobalt_led_add(void)
34{
35 struct platform_device *pdev;
36 int retval;
37
38 if (cobalt_board_id == COBALT_BRD_ID_QUBE1 ||
39 cobalt_board_id == COBALT_BRD_ID_QUBE2)
40 pdev = platform_device_alloc("cobalt-qube-leds", -1);
41 else
42 pdev = platform_device_alloc("cobalt-raq-leds", -1);
43
44 if (!pdev)
45 return -ENOMEM;
46
47 retval = platform_device_add_resources(pdev, &cobalt_led_resource, 1);
48 if (retval)
49 goto err_free_device;
50
51 retval = platform_device_add(pdev);
52 if (retval)
53 goto err_free_device;
54
55 return 0;
56
57err_free_device:
58 platform_device_put(pdev);
59
60 return retval;
61}
62device_initcall(cobalt_led_add);
diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c
index 43cca21fdbc0..71eb4ccc4bc1 100644
--- a/arch/mips/cobalt/reset.c
+++ b/arch/mips/cobalt/reset.c
@@ -8,36 +8,46 @@
8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle 8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
9 * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) 9 * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
10 */ 10 */
11#include <linux/init.h>
12#include <linux/io.h>
11#include <linux/jiffies.h> 13#include <linux/jiffies.h>
12 14#include <linux/leds.h>
13#include <asm/io.h>
14#include <asm/reboot.h>
15 15
16#include <cobalt.h> 16#include <cobalt.h>
17 17
18#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
19#define RESET 0x0f
20
21DEFINE_LED_TRIGGER(power_off_led_trigger);
22
23static int __init ledtrig_power_off_init(void)
24{
25 led_trigger_register_simple("power-off", &power_off_led_trigger);
26 return 0;
27}
28device_initcall(ledtrig_power_off_init);
29
18void cobalt_machine_halt(void) 30void cobalt_machine_halt(void)
19{ 31{
20 int state, last, diff; 32 int state, last, diff;
21 unsigned long mark; 33 unsigned long mark;
22 34
23 /* 35 /*
24 * turn off bar on Qube, flash power off LED on RaQ (0.5Hz) 36 * turn on power off LED on RaQ
25 * 37 *
26 * restart if ENTER and SELECT are pressed 38 * restart if ENTER and SELECT are pressed
27 */ 39 */
28 40
29 last = COBALT_KEY_PORT; 41 last = COBALT_KEY_PORT;
30 42
31 for (state = 0;;) { 43 led_trigger_event(power_off_led_trigger, LED_FULL);
32
33 state ^= COBALT_LED_POWER_OFF;
34 COBALT_LED_PORT = state;
35 44
45 for (state = 0;;) {
36 diff = COBALT_KEY_PORT ^ last; 46 diff = COBALT_KEY_PORT ^ last;
37 last ^= diff; 47 last ^= diff;
38 48
39 if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) 49 if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
40 COBALT_LED_PORT = COBALT_LED_RESET; 50 writeb(RESET, RESET_PORT);
41 51
42 for (mark = jiffies; jiffies - mark < HZ;) 52 for (mark = jiffies; jiffies - mark < HZ;)
43 ; 53 ;
@@ -46,17 +56,8 @@ void cobalt_machine_halt(void)
46 56
47void cobalt_machine_restart(char *command) 57void cobalt_machine_restart(char *command)
48{ 58{
49 COBALT_LED_PORT = COBALT_LED_RESET; 59 writeb(RESET, RESET_PORT);
50 60
51 /* we should never get here */ 61 /* we should never get here */
52 cobalt_machine_halt(); 62 cobalt_machine_halt();
53} 63}
54
55/*
56 * This triggers the luser mode device driver for the power switch ;-)
57 */
58void cobalt_machine_power_off(void)
59{
60 printk("You can switch the machine off now.\n");
61 cobalt_machine_halt();
62}
diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c
index 284daefc5c55..e70794b8bcba 100644
--- a/arch/mips/cobalt/rtc.c
+++ b/arch/mips/cobalt/rtc.c
@@ -20,6 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/mc146818rtc.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24 25
25static struct resource cobalt_rtc_resource[] __initdata = { 26static struct resource cobalt_rtc_resource[] __initdata = {
@@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = {
29 .flags = IORESOURCE_IO, 30 .flags = IORESOURCE_IO,
30 }, 31 },
31 { 32 {
32 .start = 8, 33 .start = RTC_IRQ,
33 .end = 8, 34 .end = RTC_IRQ,
34 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
35 }, 36 },
36}; 37};
diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c
index 08e739704cc9..53b8d0d6da90 100644
--- a/arch/mips/cobalt/serial.c
+++ b/arch/mips/cobalt/serial.c
@@ -24,6 +24,7 @@
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <cobalt.h> 26#include <cobalt.h>
27#include <irq.h>
27 28
28static struct resource cobalt_uart_resource[] __initdata = { 29static struct resource cobalt_uart_resource[] __initdata = {
29 { 30 {
@@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = {
32 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
33 }, 34 },
34 { 35 {
35 .start = COBALT_SERIAL_IRQ, 36 .start = SERIAL_IRQ,
36 .end = COBALT_SERIAL_IRQ, 37 .end = SERIAL_IRQ,
37 .flags = IORESOURCE_IRQ, 38 .flags = IORESOURCE_IRQ,
38 }, 39 },
39}; 40};
40 41
41static struct plat_serial8250_port cobalt_serial8250_port[] = { 42static struct plat_serial8250_port cobalt_serial8250_port[] = {
42 { 43 {
43 .irq = COBALT_SERIAL_IRQ, 44 .irq = SERIAL_IRQ,
44 .uartclk = 18432000, 45 .uartclk = 18432000,
45 .iotype = UPIO_MEM, 46 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 47 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index 7abe45e78425..d11bb1bc7b6b 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -15,15 +15,16 @@
15 15
16#include <asm/bootinfo.h> 16#include <asm/bootinfo.h>
17#include <asm/time.h> 17#include <asm/time.h>
18#include <asm/i8253.h>
18#include <asm/io.h> 19#include <asm/io.h>
19#include <asm/reboot.h> 20#include <asm/reboot.h>
20#include <asm/gt64120.h> 21#include <asm/gt64120.h>
21 22
22#include <cobalt.h> 23#include <cobalt.h>
24#include <irq.h>
23 25
24extern void cobalt_machine_restart(char *command); 26extern void cobalt_machine_restart(char *command);
25extern void cobalt_machine_halt(void); 27extern void cobalt_machine_halt(void);
26extern void cobalt_machine_power_off(void);
27 28
28const char *get_system_type(void) 29const char *get_system_type(void)
29{ 30{
@@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq)
45 /* Load timer value for HZ (TCLK is 50MHz) */ 46 /* Load timer value for HZ (TCLK is 50MHz) */
46 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); 47 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
47 48
48 /* Enable timer */ 49 /* Enable timer0 */
49 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 50 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
50 51
51 /* Register interrupt */ 52 setup_irq(GT641XX_TIMER0_IRQ, irq);
52 setup_irq(COBALT_GALILEO_IRQ, irq);
53
54 /* Enable interrupt */
55 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
56} 53}
57 54
58/* 55/*
@@ -87,13 +84,18 @@ static struct resource cobalt_reserved_resources[] = {
87 }, 84 },
88}; 85};
89 86
87void __init plat_time_init(void)
88{
89 setup_pit_timer();
90}
91
90void __init plat_mem_setup(void) 92void __init plat_mem_setup(void)
91{ 93{
92 int i; 94 int i;
93 95
94 _machine_restart = cobalt_machine_restart; 96 _machine_restart = cobalt_machine_restart;
95 _machine_halt = cobalt_machine_halt; 97 _machine_halt = cobalt_machine_halt;
96 pm_power_off = cobalt_machine_power_off; 98 pm_power_off = cobalt_machine_halt;
97 99
98 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); 100 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
99 101
@@ -117,8 +119,6 @@ void __init prom_init(void)
117 unsigned long memsz; 119 unsigned long memsz;
118 char **argv; 120 char **argv;
119 121
120 mips_machgroup = MACH_GROUP_COBALT;
121
122 memsz = fw_arg0 & 0x7fff0000; 122 memsz = fw_arg0 & 0x7fff0000;
123 narg = fw_arg0 & 0x0000ffff; 123 narg = fw_arg0 & 0x0000ffff;
124 124
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 700a3a2d688e..30f3e9a2466f 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -69,7 +69,6 @@ CONFIG_SIBYTE_SB1xxx_SOC=y
69CONFIG_SIBYTE_CFE=y 69CONFIG_SIBYTE_CFE=y
70# CONFIG_SIBYTE_CFE_CONSOLE is not set 70# CONFIG_SIBYTE_CFE_CONSOLE is not set
71# CONFIG_SIBYTE_BUS_WATCHER is not set 71# CONFIG_SIBYTE_BUS_WATCHER is not set
72# CONFIG_SIBYTE_SB1250_PROF is not set
73# CONFIG_SIBYTE_TBPROF is not set 72# CONFIG_SIBYTE_TBPROF is not set
74CONFIG_RWSEM_GENERIC_SPINLOCK=y 73CONFIG_RWSEM_GENERIC_SPINLOCK=y
75# CONFIG_ARCH_HAS_ILOG2_U32 is not set 74# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index ebcb7ad8814b..36c13039e237 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc2 3# Linux kernel version: 2.6.23-rc5
4# Tue Aug 7 22:12:54 2007 4# Thu Sep 6 13:14:29 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -55,12 +55,14 @@ CONFIG_DMA_NONCOHERENT=y
55CONFIG_DMA_NEED_PCI_MAP_STATE=y 55CONFIG_DMA_NEED_PCI_MAP_STATE=y
56CONFIG_EARLY_PRINTK=y 56CONFIG_EARLY_PRINTK=y
57CONFIG_SYS_HAS_EARLY_PRINTK=y 57CONFIG_SYS_HAS_EARLY_PRINTK=y
58# CONFIG_HOTPLUG_CPU is not set
58CONFIG_I8259=y 59CONFIG_I8259=y
59# CONFIG_NO_IOPORT is not set 60# CONFIG_NO_IOPORT is not set
60# CONFIG_CPU_BIG_ENDIAN is not set 61# CONFIG_CPU_BIG_ENDIAN is not set
61CONFIG_CPU_LITTLE_ENDIAN=y 62CONFIG_CPU_LITTLE_ENDIAN=y
62CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y 63CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
63CONFIG_IRQ_CPU=y 64CONFIG_IRQ_CPU=y
65CONFIG_IRQ_GT641XX=y
64CONFIG_PCI_GT64XXX_PCI0=y 66CONFIG_PCI_GT64XXX_PCI0=y
65CONFIG_MIPS_L1_CACHE_SHIFT=5 67CONFIG_MIPS_L1_CACHE_SHIFT=5
66 68
@@ -235,6 +237,7 @@ CONFIG_TRAD_SIGNALS=y
235# Power management options 237# Power management options
236# 238#
237# CONFIG_PM is not set 239# CONFIG_PM is not set
240CONFIG_SUSPEND_UP_POSSIBLE=y
238 241
239# 242#
240# Networking 243# Networking
@@ -844,7 +847,21 @@ CONFIG_USB_MON=y
844# 847#
845# CONFIG_USB_GADGET is not set 848# CONFIG_USB_GADGET is not set
846# CONFIG_MMC is not set 849# CONFIG_MMC is not set
847# CONFIG_NEW_LEDS is not set 850CONFIG_NEW_LEDS=y
851CONFIG_LEDS_CLASS=y
852
853#
854# LED drivers
855#
856CONFIG_LEDS_COBALT_QUBE=y
857CONFIG_LEDS_COBALT_RAQ=y
858
859#
860# LED Triggers
861#
862CONFIG_LEDS_TRIGGERS=y
863# CONFIG_LEDS_TRIGGER_TIMER is not set
864# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
848# CONFIG_INFINIBAND is not set 865# CONFIG_INFINIBAND is not set
849CONFIG_RTC_LIB=y 866CONFIG_RTC_LIB=y
850CONFIG_RTC_CLASS=y 867CONFIG_RTC_CLASS=y
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
new file mode 100644
index 000000000000..2c665fcef089
--- /dev/null
+++ b/arch/mips/configs/lasat_defconfig
@@ -0,0 +1,828 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc3
4# Sat Aug 18 17:37:58 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set
16CONFIG_LASAT=y
17# CONFIG_LEMOTE_FULONG is not set
18# CONFIG_MIPS_ATLAS is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SEAD is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_PNX8550_JBS is not set
25# CONFIG_PNX8550_STB810 is not set
26# CONFIG_PMC_MSP is not set
27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP32 is not set
32# CONFIG_SIBYTE_CRHINE is not set
33# CONFIG_SIBYTE_CARMEL is not set
34# CONFIG_SIBYTE_CRHONE is not set
35# CONFIG_SIBYTE_RHONE is not set
36# CONFIG_SIBYTE_SWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_SENTOSA is not set
39# CONFIG_SIBYTE_PTSWARM is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set
43# CONFIG_TOSHIBA_RBTX4927 is not set
44# CONFIG_TOSHIBA_RBTX4938 is not set
45# CONFIG_WR_PPMC is not set
46CONFIG_PICVUE=y
47CONFIG_PICVUE_PROC=y
48CONFIG_DS1603=y
49CONFIG_LASAT_SYSCTL=y
50CONFIG_RWSEM_GENERIC_SPINLOCK=y
51# CONFIG_ARCH_HAS_ILOG2_U32 is not set
52# CONFIG_ARCH_HAS_ILOG2_U64 is not set
53CONFIG_GENERIC_FIND_NEXT_BIT=y
54CONFIG_GENERIC_HWEIGHT=y
55CONFIG_GENERIC_CALIBRATE_DELAY=y
56CONFIG_GENERIC_TIME=y
57CONFIG_GENERIC_CMOS_UPDATE=y
58CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
59CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
60CONFIG_DMA_NONCOHERENT=y
61CONFIG_DMA_NEED_PCI_MAP_STATE=y
62CONFIG_EARLY_PRINTK=y
63CONFIG_SYS_HAS_EARLY_PRINTK=y
64# CONFIG_HOTPLUG_CPU is not set
65CONFIG_MIPS_NILE4=y
66# CONFIG_NO_IOPORT is not set
67# CONFIG_CPU_BIG_ENDIAN is not set
68CONFIG_CPU_LITTLE_ENDIAN=y
69CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
70CONFIG_PCI_GT64XXX_PCI0=y
71CONFIG_MIPS_L1_CACHE_SHIFT=5
72
73#
74# CPU selection
75#
76# CONFIG_CPU_LOONGSON2 is not set
77# CONFIG_CPU_MIPS32_R1 is not set
78# CONFIG_CPU_MIPS32_R2 is not set
79# CONFIG_CPU_MIPS64_R1 is not set
80# CONFIG_CPU_MIPS64_R2 is not set
81# CONFIG_CPU_R3000 is not set
82# CONFIG_CPU_TX39XX is not set
83# CONFIG_CPU_VR41XX is not set
84# CONFIG_CPU_R4300 is not set
85# CONFIG_CPU_R4X00 is not set
86# CONFIG_CPU_TX49XX is not set
87CONFIG_CPU_R5000=y
88# CONFIG_CPU_R5432 is not set
89# CONFIG_CPU_R6000 is not set
90# CONFIG_CPU_NEVADA is not set
91# CONFIG_CPU_R8000 is not set
92# CONFIG_CPU_R10000 is not set
93# CONFIG_CPU_RM7000 is not set
94# CONFIG_CPU_RM9000 is not set
95# CONFIG_CPU_SB1 is not set
96CONFIG_SYS_HAS_CPU_R5000=y
97CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
98CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
99CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
100
101#
102# Kernel type
103#
104CONFIG_32BIT=y
105# CONFIG_64BIT is not set
106CONFIG_PAGE_SIZE_4KB=y
107# CONFIG_PAGE_SIZE_8KB is not set
108# CONFIG_PAGE_SIZE_16KB is not set
109# CONFIG_PAGE_SIZE_64KB is not set
110CONFIG_BOARD_SCACHE=y
111CONFIG_R5000_CPU_SCACHE=y
112CONFIG_MIPS_MT_DISABLED=y
113# CONFIG_MIPS_MT_SMP is not set
114# CONFIG_MIPS_MT_SMTC is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_HAS_SYNC=y
117CONFIG_GENERIC_HARDIRQS=y
118CONFIG_GENERIC_IRQ_PROBE=y
119CONFIG_ARCH_FLATMEM_ENABLE=y
120CONFIG_SELECT_MEMORY_MODEL=y
121CONFIG_FLATMEM_MANUAL=y
122# CONFIG_DISCONTIGMEM_MANUAL is not set
123# CONFIG_SPARSEMEM_MANUAL is not set
124CONFIG_FLATMEM=y
125CONFIG_FLAT_NODE_MEM_MAP=y
126# CONFIG_SPARSEMEM_STATIC is not set
127CONFIG_SPLIT_PTLOCK_CPUS=4
128# CONFIG_RESOURCES_64BIT is not set
129CONFIG_ZONE_DMA_FLAG=0
130CONFIG_VIRT_TO_BUS=y
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
140CONFIG_PREEMPT_NONE=y
141# CONFIG_PREEMPT_VOLUNTARY is not set
142# CONFIG_PREEMPT is not set
143# CONFIG_KEXEC is not set
144# CONFIG_SECCOMP is not set
145CONFIG_LOCKDEP_SUPPORT=y
146CONFIG_STACKTRACE_SUPPORT=y
147CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
148
149#
150# General setup
151#
152CONFIG_EXPERIMENTAL=y
153CONFIG_BROKEN_ON_SMP=y
154CONFIG_INIT_ENV_ARG_LIMIT=32
155CONFIG_LOCALVERSION=""
156CONFIG_LOCALVERSION_AUTO=y
157CONFIG_SWAP=y
158CONFIG_SYSVIPC=y
159CONFIG_SYSVIPC_SYSCTL=y
160# CONFIG_POSIX_MQUEUE is not set
161# CONFIG_BSD_PROCESS_ACCT is not set
162# CONFIG_TASKSTATS is not set
163# CONFIG_USER_NS is not set
164# CONFIG_AUDIT is not set
165# CONFIG_IKCONFIG is not set
166CONFIG_LOG_BUF_SHIFT=14
167# CONFIG_SYSFS_DEPRECATED is not set
168# CONFIG_RELAY is not set
169# CONFIG_BLK_DEV_INITRD is not set
170CONFIG_CC_OPTIMIZE_FOR_SIZE=y
171CONFIG_SYSCTL=y
172CONFIG_EMBEDDED=y
173# CONFIG_SYSCTL_SYSCALL is not set
174# CONFIG_KALLSYMS is not set
175# CONFIG_HOTPLUG is not set
176CONFIG_PRINTK=y
177CONFIG_BUG=y
178CONFIG_ELF_CORE=y
179CONFIG_BASE_FULL=y
180CONFIG_FUTEX=y
181# CONFIG_EPOLL is not set
182# CONFIG_SIGNALFD is not set
183# CONFIG_TIMERFD is not set
184# CONFIG_EVENTFD is not set
185CONFIG_SHMEM=y
186CONFIG_VM_EVENT_COUNTERS=y
187CONFIG_SLAB=y
188# CONFIG_SLUB is not set
189# CONFIG_SLOB is not set
190CONFIG_RT_MUTEXES=y
191# CONFIG_TINY_SHMEM is not set
192CONFIG_BASE_SMALL=0
193# CONFIG_MODULES is not set
194CONFIG_BLOCK=y
195# CONFIG_LBD is not set
196# CONFIG_BLK_DEV_IO_TRACE is not set
197# CONFIG_LSF is not set
198# CONFIG_BLK_DEV_BSG is not set
199
200#
201# IO Schedulers
202#
203CONFIG_IOSCHED_NOOP=y
204CONFIG_IOSCHED_AS=y
205# CONFIG_IOSCHED_DEADLINE is not set
206# CONFIG_IOSCHED_CFQ is not set
207CONFIG_DEFAULT_AS=y
208# CONFIG_DEFAULT_DEADLINE is not set
209# CONFIG_DEFAULT_CFQ is not set
210# CONFIG_DEFAULT_NOOP is not set
211CONFIG_DEFAULT_IOSCHED="anticipatory"
212
213#
214# Bus options (PCI, PCMCIA, EISA, ISA, TC)
215#
216CONFIG_HW_HAS_PCI=y
217CONFIG_PCI=y
218# CONFIG_ARCH_SUPPORTS_MSI is not set
219CONFIG_MMU=y
220
221#
222# PCCARD (PCMCIA/CardBus) support
223#
224
225#
226# Executable file formats
227#
228CONFIG_BINFMT_ELF=y
229# CONFIG_BINFMT_MISC is not set
230CONFIG_TRAD_SIGNALS=y
231
232#
233# Power management options
234#
235# CONFIG_PM is not set
236
237#
238# Networking
239#
240CONFIG_NET=y
241
242#
243# Networking options
244#
245CONFIG_PACKET=y
246CONFIG_PACKET_MMAP=y
247CONFIG_UNIX=y
248# CONFIG_NET_KEY is not set
249CONFIG_INET=y
250# CONFIG_IP_MULTICAST is not set
251# CONFIG_IP_ADVANCED_ROUTER is not set
252CONFIG_IP_FIB_HASH=y
253# CONFIG_IP_PNP is not set
254# CONFIG_NET_IPIP is not set
255# CONFIG_NET_IPGRE is not set
256# CONFIG_ARPD is not set
257# CONFIG_SYN_COOKIES is not set
258# CONFIG_INET_AH is not set
259# CONFIG_INET_ESP is not set
260# CONFIG_INET_IPCOMP is not set
261# CONFIG_INET_XFRM_TUNNEL is not set
262# CONFIG_INET_TUNNEL is not set
263# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
264# CONFIG_INET_XFRM_MODE_TUNNEL is not set
265# CONFIG_INET_XFRM_MODE_BEET is not set
266# CONFIG_INET_DIAG is not set
267# CONFIG_TCP_CONG_ADVANCED is not set
268CONFIG_TCP_CONG_CUBIC=y
269CONFIG_DEFAULT_TCP_CONG="cubic"
270# CONFIG_TCP_MD5SIG is not set
271# CONFIG_IPV6 is not set
272# CONFIG_INET6_XFRM_TUNNEL is not set
273# CONFIG_INET6_TUNNEL is not set
274# CONFIG_NETWORK_SECMARK is not set
275# CONFIG_NETFILTER is not set
276# CONFIG_IP_DCCP is not set
277# CONFIG_IP_SCTP is not set
278# CONFIG_TIPC is not set
279# CONFIG_ATM is not set
280# CONFIG_BRIDGE is not set
281# CONFIG_VLAN_8021Q is not set
282# CONFIG_DECNET is not set
283# CONFIG_LLC2 is not set
284# CONFIG_IPX is not set
285# CONFIG_ATALK is not set
286# CONFIG_X25 is not set
287# CONFIG_LAPB is not set
288# CONFIG_ECONET is not set
289# CONFIG_WAN_ROUTER is not set
290
291#
292# QoS and/or fair queueing
293#
294# CONFIG_NET_SCHED is not set
295
296#
297# Network testing
298#
299# CONFIG_NET_PKTGEN is not set
300# CONFIG_HAMRADIO is not set
301# CONFIG_IRDA is not set
302# CONFIG_BT is not set
303# CONFIG_AF_RXRPC is not set
304
305#
306# Wireless
307#
308# CONFIG_CFG80211 is not set
309# CONFIG_WIRELESS_EXT is not set
310# CONFIG_MAC80211 is not set
311# CONFIG_IEEE80211 is not set
312# CONFIG_RFKILL is not set
313# CONFIG_NET_9P is not set
314
315#
316# Device Drivers
317#
318
319#
320# Generic Driver Options
321#
322CONFIG_STANDALONE=y
323CONFIG_PREVENT_FIRMWARE_BUILD=y
324# CONFIG_SYS_HYPERVISOR is not set
325# CONFIG_CONNECTOR is not set
326CONFIG_MTD=y
327# CONFIG_MTD_DEBUG is not set
328# CONFIG_MTD_CONCAT is not set
329CONFIG_MTD_PARTITIONS=y
330# CONFIG_MTD_REDBOOT_PARTS is not set
331# CONFIG_MTD_CMDLINE_PARTS is not set
332
333#
334# User Modules And Translation Layers
335#
336CONFIG_MTD_CHAR=y
337CONFIG_MTD_BLKDEVS=y
338CONFIG_MTD_BLOCK=y
339# CONFIG_FTL is not set
340# CONFIG_NFTL is not set
341# CONFIG_INFTL is not set
342# CONFIG_RFD_FTL is not set
343# CONFIG_SSFDC is not set
344
345#
346# RAM/ROM/Flash chip drivers
347#
348CONFIG_MTD_CFI=y
349# CONFIG_MTD_JEDECPROBE is not set
350CONFIG_MTD_GEN_PROBE=y
351# CONFIG_MTD_CFI_ADV_OPTIONS is not set
352CONFIG_MTD_MAP_BANK_WIDTH_1=y
353CONFIG_MTD_MAP_BANK_WIDTH_2=y
354CONFIG_MTD_MAP_BANK_WIDTH_4=y
355# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
356# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
357# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
358CONFIG_MTD_CFI_I1=y
359CONFIG_MTD_CFI_I2=y
360# CONFIG_MTD_CFI_I4 is not set
361# CONFIG_MTD_CFI_I8 is not set
362# CONFIG_MTD_CFI_INTELEXT is not set
363CONFIG_MTD_CFI_AMDSTD=y
364# CONFIG_MTD_CFI_STAA is not set
365CONFIG_MTD_CFI_UTIL=y
366# CONFIG_MTD_RAM is not set
367# CONFIG_MTD_ROM is not set
368# CONFIG_MTD_ABSENT is not set
369
370#
371# Mapping drivers for chip access
372#
373# CONFIG_MTD_COMPLEX_MAPPINGS is not set
374# CONFIG_MTD_PHYSMAP is not set
375CONFIG_MTD_LASAT=y
376# CONFIG_MTD_PLATRAM is not set
377
378#
379# Self-contained MTD device drivers
380#
381# CONFIG_MTD_PMC551 is not set
382# CONFIG_MTD_SLRAM is not set
383# CONFIG_MTD_PHRAM is not set
384# CONFIG_MTD_MTDRAM is not set
385# CONFIG_MTD_BLOCK2MTD is not set
386
387#
388# Disk-On-Chip Device Drivers
389#
390# CONFIG_MTD_DOC2000 is not set
391# CONFIG_MTD_DOC2001 is not set
392# CONFIG_MTD_DOC2001PLUS is not set
393# CONFIG_MTD_NAND is not set
394# CONFIG_MTD_ONENAND is not set
395
396#
397# UBI - Unsorted block images
398#
399# CONFIG_MTD_UBI is not set
400# CONFIG_PARPORT is not set
401CONFIG_BLK_DEV=y
402# CONFIG_BLK_CPQ_DA is not set
403# CONFIG_BLK_CPQ_CISS_DA is not set
404# CONFIG_BLK_DEV_DAC960 is not set
405# CONFIG_BLK_DEV_UMEM is not set
406# CONFIG_BLK_DEV_COW_COMMON is not set
407# CONFIG_BLK_DEV_LOOP is not set
408# CONFIG_BLK_DEV_NBD is not set
409# CONFIG_BLK_DEV_SX8 is not set
410# CONFIG_BLK_DEV_RAM is not set
411# CONFIG_CDROM_PKTCDVD is not set
412# CONFIG_ATA_OVER_ETH is not set
413# CONFIG_MISC_DEVICES is not set
414CONFIG_IDE=y
415CONFIG_IDE_MAX_HWIFS=4
416CONFIG_BLK_DEV_IDE=y
417
418#
419# Please see Documentation/ide.txt for help/info on IDE drives
420#
421# CONFIG_BLK_DEV_IDE_SATA is not set
422CONFIG_BLK_DEV_IDEDISK=y
423CONFIG_IDEDISK_MULTI_MODE=y
424# CONFIG_BLK_DEV_IDECD is not set
425# CONFIG_BLK_DEV_IDETAPE is not set
426# CONFIG_BLK_DEV_IDEFLOPPY is not set
427# CONFIG_IDE_TASK_IOCTL is not set
428CONFIG_IDE_PROC_FS=y
429
430#
431# IDE chipset support/bugfixes
432#
433CONFIG_IDE_GENERIC=y
434CONFIG_BLK_DEV_IDEPCI=y
435# CONFIG_IDEPCI_SHARE_IRQ is not set
436CONFIG_IDEPCI_PCIBUS_ORDER=y
437# CONFIG_BLK_DEV_OFFBOARD is not set
438CONFIG_BLK_DEV_GENERIC=y
439# CONFIG_BLK_DEV_OPTI621 is not set
440CONFIG_BLK_DEV_IDEDMA_PCI=y
441# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
442# CONFIG_IDEDMA_ONLYDISK is not set
443# CONFIG_BLK_DEV_AEC62XX is not set
444# CONFIG_BLK_DEV_ALI15X3 is not set
445# CONFIG_BLK_DEV_AMD74XX is not set
446CONFIG_BLK_DEV_CMD64X=y
447# CONFIG_BLK_DEV_TRIFLEX is not set
448# CONFIG_BLK_DEV_CY82C693 is not set
449# CONFIG_BLK_DEV_CS5520 is not set
450# CONFIG_BLK_DEV_CS5530 is not set
451# CONFIG_BLK_DEV_HPT34X is not set
452# CONFIG_BLK_DEV_HPT366 is not set
453# CONFIG_BLK_DEV_JMICRON is not set
454# CONFIG_BLK_DEV_SC1200 is not set
455# CONFIG_BLK_DEV_PIIX is not set
456# CONFIG_BLK_DEV_IT8213 is not set
457# CONFIG_BLK_DEV_IT821X is not set
458# CONFIG_BLK_DEV_NS87415 is not set
459# CONFIG_BLK_DEV_PDC202XX_OLD is not set
460# CONFIG_BLK_DEV_PDC202XX_NEW is not set
461# CONFIG_BLK_DEV_SVWKS is not set
462# CONFIG_BLK_DEV_SIIMAGE is not set
463# CONFIG_BLK_DEV_SLC90E66 is not set
464# CONFIG_BLK_DEV_TRM290 is not set
465# CONFIG_BLK_DEV_VIA82CXXX is not set
466# CONFIG_BLK_DEV_TC86C001 is not set
467# CONFIG_IDE_ARM is not set
468CONFIG_BLK_DEV_IDEDMA=y
469# CONFIG_IDEDMA_IVB is not set
470# CONFIG_BLK_DEV_HD is not set
471
472#
473# SCSI device support
474#
475# CONFIG_RAID_ATTRS is not set
476# CONFIG_SCSI is not set
477# CONFIG_SCSI_DMA is not set
478# CONFIG_SCSI_NETLINK is not set
479# CONFIG_ATA is not set
480# CONFIG_MD is not set
481
482#
483# Fusion MPT device support
484#
485# CONFIG_FUSION is not set
486
487#
488# IEEE 1394 (FireWire) support
489#
490# CONFIG_FIREWIRE is not set
491# CONFIG_IEEE1394 is not set
492# CONFIG_I2O is not set
493CONFIG_NETDEVICES=y
494# CONFIG_NETDEVICES_MULTIQUEUE is not set
495# CONFIG_DUMMY is not set
496# CONFIG_BONDING is not set
497# CONFIG_MACVLAN is not set
498# CONFIG_EQUALIZER is not set
499# CONFIG_TUN is not set
500# CONFIG_ARCNET is not set
501# CONFIG_PHYLIB is not set
502CONFIG_NET_ETHERNET=y
503CONFIG_MII=y
504# CONFIG_AX88796 is not set
505# CONFIG_HAPPYMEAL is not set
506# CONFIG_SUNGEM is not set
507# CONFIG_CASSINI is not set
508# CONFIG_NET_VENDOR_3COM is not set
509# CONFIG_DM9000 is not set
510# CONFIG_NET_TULIP is not set
511# CONFIG_HP100 is not set
512CONFIG_NET_PCI=y
513CONFIG_PCNET32=y
514# CONFIG_PCNET32_NAPI is not set
515# CONFIG_AMD8111_ETH is not set
516# CONFIG_ADAPTEC_STARFIRE is not set
517# CONFIG_B44 is not set
518# CONFIG_FORCEDETH is not set
519# CONFIG_TC35815 is not set
520# CONFIG_DGRS is not set
521# CONFIG_EEPRO100 is not set
522# CONFIG_E100 is not set
523# CONFIG_FEALNX is not set
524# CONFIG_NATSEMI is not set
525# CONFIG_NE2K_PCI is not set
526# CONFIG_8139CP is not set
527# CONFIG_8139TOO is not set
528# CONFIG_SIS900 is not set
529# CONFIG_EPIC100 is not set
530# CONFIG_SUNDANCE is not set
531# CONFIG_TLAN is not set
532# CONFIG_VIA_RHINE is not set
533# CONFIG_SC92031 is not set
534# CONFIG_NETDEV_1000 is not set
535# CONFIG_NETDEV_10000 is not set
536# CONFIG_TR is not set
537
538#
539# Wireless LAN
540#
541# CONFIG_WLAN_PRE80211 is not set
542# CONFIG_WLAN_80211 is not set
543# CONFIG_WAN is not set
544# CONFIG_FDDI is not set
545# CONFIG_HIPPI is not set
546# CONFIG_PPP is not set
547# CONFIG_SLIP is not set
548# CONFIG_SHAPER is not set
549# CONFIG_NETCONSOLE is not set
550# CONFIG_NETPOLL is not set
551# CONFIG_NET_POLL_CONTROLLER is not set
552# CONFIG_ISDN is not set
553# CONFIG_PHONE is not set
554
555#
556# Input device support
557#
558CONFIG_INPUT=y
559# CONFIG_INPUT_FF_MEMLESS is not set
560# CONFIG_INPUT_POLLDEV is not set
561
562#
563# Userland interfaces
564#
565# CONFIG_INPUT_MOUSEDEV is not set
566# CONFIG_INPUT_JOYDEV is not set
567# CONFIG_INPUT_TSDEV is not set
568# CONFIG_INPUT_EVDEV is not set
569# CONFIG_INPUT_EVBUG is not set
570
571#
572# Input Device Drivers
573#
574# CONFIG_INPUT_KEYBOARD is not set
575# CONFIG_INPUT_MOUSE is not set
576# CONFIG_INPUT_JOYSTICK is not set
577# CONFIG_INPUT_TABLET is not set
578# CONFIG_INPUT_TOUCHSCREEN is not set
579# CONFIG_INPUT_MISC is not set
580
581#
582# Hardware I/O ports
583#
584CONFIG_SERIO=y
585CONFIG_SERIO_I8042=y
586CONFIG_SERIO_SERPORT=y
587# CONFIG_SERIO_PCIPS2 is not set
588# CONFIG_SERIO_LIBPS2 is not set
589CONFIG_SERIO_RAW=y
590# CONFIG_GAMEPORT is not set
591
592#
593# Character devices
594#
595# CONFIG_VT is not set
596# CONFIG_SERIAL_NONSTANDARD is not set
597
598#
599# Serial drivers
600#
601CONFIG_SERIAL_8250=y
602CONFIG_SERIAL_8250_CONSOLE=y
603# CONFIG_SERIAL_8250_PCI is not set
604CONFIG_SERIAL_8250_NR_UARTS=4
605CONFIG_SERIAL_8250_RUNTIME_UARTS=4
606# CONFIG_SERIAL_8250_EXTENDED is not set
607
608#
609# Non-8250 serial port support
610#
611CONFIG_SERIAL_CORE=y
612CONFIG_SERIAL_CORE_CONSOLE=y
613# CONFIG_SERIAL_JSM is not set
614CONFIG_UNIX98_PTYS=y
615CONFIG_LEGACY_PTYS=y
616CONFIG_LEGACY_PTY_COUNT=256
617# CONFIG_IPMI_HANDLER is not set
618# CONFIG_WATCHDOG is not set
619# CONFIG_HW_RANDOM is not set
620# CONFIG_RTC is not set
621# CONFIG_R3964 is not set
622# CONFIG_APPLICOM is not set
623# CONFIG_DRM is not set
624# CONFIG_RAW_DRIVER is not set
625# CONFIG_TCG_TPM is not set
626CONFIG_DEVPORT=y
627# CONFIG_I2C is not set
628
629#
630# SPI support
631#
632# CONFIG_SPI is not set
633# CONFIG_SPI_MASTER is not set
634# CONFIG_W1 is not set
635# CONFIG_POWER_SUPPLY is not set
636# CONFIG_HWMON is not set
637
638#
639# Multifunction device drivers
640#
641# CONFIG_MFD_SM501 is not set
642
643#
644# Multimedia devices
645#
646# CONFIG_VIDEO_DEV is not set
647# CONFIG_DVB_CORE is not set
648# CONFIG_DAB is not set
649
650#
651# Graphics support
652#
653# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
654
655#
656# Display device support
657#
658# CONFIG_DISPLAY_SUPPORT is not set
659# CONFIG_VGASTATE is not set
660# CONFIG_VIDEO_OUTPUT_CONTROL is not set
661# CONFIG_FB is not set
662
663#
664# Sound
665#
666# CONFIG_SOUND is not set
667# CONFIG_HID_SUPPORT is not set
668# CONFIG_USB_SUPPORT is not set
669# CONFIG_MMC is not set
670# CONFIG_NEW_LEDS is not set
671# CONFIG_INFINIBAND is not set
672# CONFIG_RTC_CLASS is not set
673
674#
675# DMA Engine support
676#
677# CONFIG_DMA_ENGINE is not set
678
679#
680# DMA Clients
681#
682
683#
684# DMA Devices
685#
686
687#
688# Userspace I/O
689#
690# CONFIG_UIO is not set
691
692#
693# File systems
694#
695CONFIG_EXT2_FS=y
696# CONFIG_EXT2_FS_XATTR is not set
697# CONFIG_EXT2_FS_XIP is not set
698CONFIG_EXT3_FS=y
699# CONFIG_EXT3_FS_XATTR is not set
700# CONFIG_EXT4DEV_FS is not set
701CONFIG_JBD=y
702# CONFIG_JBD_DEBUG is not set
703# CONFIG_REISERFS_FS is not set
704# CONFIG_JFS_FS is not set
705# CONFIG_FS_POSIX_ACL is not set
706# CONFIG_XFS_FS is not set
707# CONFIG_GFS2_FS is not set
708# CONFIG_OCFS2_FS is not set
709# CONFIG_MINIX_FS is not set
710# CONFIG_ROMFS_FS is not set
711# CONFIG_INOTIFY is not set
712# CONFIG_QUOTA is not set
713# CONFIG_DNOTIFY is not set
714# CONFIG_AUTOFS_FS is not set
715# CONFIG_AUTOFS4_FS is not set
716# CONFIG_FUSE_FS is not set
717
718#
719# CD-ROM/DVD Filesystems
720#
721# CONFIG_ISO9660_FS is not set
722# CONFIG_UDF_FS is not set
723
724#
725# DOS/FAT/NT Filesystems
726#
727# CONFIG_MSDOS_FS is not set
728# CONFIG_VFAT_FS is not set
729# CONFIG_NTFS_FS is not set
730
731#
732# Pseudo filesystems
733#
734CONFIG_PROC_FS=y
735CONFIG_PROC_KCORE=y
736CONFIG_PROC_SYSCTL=y
737CONFIG_SYSFS=y
738CONFIG_TMPFS=y
739# CONFIG_TMPFS_POSIX_ACL is not set
740# CONFIG_HUGETLB_PAGE is not set
741CONFIG_RAMFS=y
742CONFIG_CONFIGFS_FS=y
743
744#
745# Miscellaneous filesystems
746#
747# CONFIG_ADFS_FS is not set
748# CONFIG_AFFS_FS is not set
749# CONFIG_HFS_FS is not set
750# CONFIG_HFSPLUS_FS is not set
751# CONFIG_BEFS_FS is not set
752# CONFIG_BFS_FS is not set
753# CONFIG_EFS_FS is not set
754# CONFIG_JFFS2_FS is not set
755# CONFIG_CRAMFS is not set
756# CONFIG_VXFS_FS is not set
757# CONFIG_HPFS_FS is not set
758# CONFIG_QNX4FS_FS is not set
759# CONFIG_SYSV_FS is not set
760# CONFIG_UFS_FS is not set
761
762#
763# Network File Systems
764#
765# CONFIG_NFS_FS is not set
766# CONFIG_NFSD is not set
767# CONFIG_SMB_FS is not set
768# CONFIG_CIFS is not set
769# CONFIG_NCP_FS is not set
770# CONFIG_CODA_FS is not set
771# CONFIG_AFS_FS is not set
772
773#
774# Partition Types
775#
776# CONFIG_PARTITION_ADVANCED is not set
777CONFIG_MSDOS_PARTITION=y
778
779#
780# Native Language Support
781#
782# CONFIG_NLS is not set
783
784#
785# Distributed Lock Manager
786#
787# CONFIG_DLM is not set
788
789#
790# Profiling support
791#
792# CONFIG_PROFILING is not set
793
794#
795# Kernel hacking
796#
797CONFIG_TRACE_IRQFLAGS_SUPPORT=y
798# CONFIG_PRINTK_TIME is not set
799CONFIG_ENABLE_MUST_CHECK=y
800CONFIG_MAGIC_SYSRQ=y
801# CONFIG_UNUSED_SYMBOLS is not set
802# CONFIG_DEBUG_FS is not set
803# CONFIG_HEADERS_CHECK is not set
804# CONFIG_DEBUG_KERNEL is not set
805CONFIG_CROSSCOMPILE=y
806CONFIG_CMDLINE=""
807
808#
809# Security options
810#
811# CONFIG_KEYS is not set
812# CONFIG_SECURITY is not set
813# CONFIG_CRYPTO is not set
814
815#
816# Library routines
817#
818CONFIG_BITREVERSE=y
819# CONFIG_CRC_CCITT is not set
820# CONFIG_CRC16 is not set
821# CONFIG_CRC_ITU_T is not set
822CONFIG_CRC32=y
823# CONFIG_CRC7 is not set
824# CONFIG_LIBCRC32C is not set
825CONFIG_PLIST=y
826CONFIG_HAS_IOMEM=y
827CONFIG_HAS_IOPORT=y
828CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
new file mode 100644
index 000000000000..0280ef389d8d
--- /dev/null
+++ b/arch/mips/configs/mtx1_defconfig
@@ -0,0 +1,3115 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc8
4# Sun Sep 30 12:56:10 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_MACH_ALCHEMY=y
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set
16# CONFIG_LEMOTE_FULONG is not set
17# CONFIG_MIPS_ATLAS is not set
18# CONFIG_MIPS_MALTA is not set
19# CONFIG_MIPS_SEAD is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_PNX8550_JBS is not set
24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set
31# CONFIG_SIBYTE_CRHINE is not set
32# CONFIG_SIBYTE_CARMEL is not set
33# CONFIG_SIBYTE_CRHONE is not set
34# CONFIG_SIBYTE_RHONE is not set
35# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set
42# CONFIG_TOSHIBA_RBTX4927 is not set
43# CONFIG_TOSHIBA_RBTX4938 is not set
44# CONFIG_WR_PPMC is not set
45CONFIG_MIPS_MTX1=y
46# CONFIG_MIPS_BOSPORUS is not set
47# CONFIG_MIPS_DB1000 is not set
48# CONFIG_MIPS_DB1100 is not set
49# CONFIG_MIPS_DB1200 is not set
50# CONFIG_MIPS_DB1500 is not set
51# CONFIG_MIPS_DB1550 is not set
52# CONFIG_MIPS_MIRAGE is not set
53# CONFIG_MIPS_PB1000 is not set
54# CONFIG_MIPS_PB1100 is not set
55# CONFIG_MIPS_PB1200 is not set
56# CONFIG_MIPS_PB1500 is not set
57# CONFIG_MIPS_PB1550 is not set
58# CONFIG_MIPS_XXS1500 is not set
59CONFIG_SOC_AU1500=y
60CONFIG_SOC_AU1X00=y
61CONFIG_RWSEM_GENERIC_SPINLOCK=y
62# CONFIG_ARCH_HAS_ILOG2_U32 is not set
63# CONFIG_ARCH_HAS_ILOG2_U64 is not set
64CONFIG_GENERIC_FIND_NEXT_BIT=y
65CONFIG_GENERIC_HWEIGHT=y
66CONFIG_GENERIC_CALIBRATE_DELAY=y
67CONFIG_GENERIC_TIME=y
68CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
69# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
70CONFIG_DMA_NONCOHERENT=y
71CONFIG_DMA_NEED_PCI_MAP_STATE=y
72# CONFIG_HOTPLUG_CPU is not set
73# CONFIG_NO_IOPORT is not set
74# CONFIG_CPU_BIG_ENDIAN is not set
75CONFIG_CPU_LITTLE_ENDIAN=y
76CONFIG_SYS_SUPPORTS_APM_EMULATION=y
77CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
78CONFIG_MIPS_L1_CACHE_SHIFT=5
79
80#
81# CPU selection
82#
83# CONFIG_CPU_LOONGSON2 is not set
84CONFIG_CPU_MIPS32_R1=y
85# CONFIG_CPU_MIPS32_R2 is not set
86# CONFIG_CPU_MIPS64_R1 is not set
87# CONFIG_CPU_MIPS64_R2 is not set
88# CONFIG_CPU_R3000 is not set
89# CONFIG_CPU_TX39XX is not set
90# CONFIG_CPU_VR41XX is not set
91# CONFIG_CPU_R4300 is not set
92# CONFIG_CPU_R4X00 is not set
93# CONFIG_CPU_TX49XX is not set
94# CONFIG_CPU_R5000 is not set
95# CONFIG_CPU_R5432 is not set
96# CONFIG_CPU_R6000 is not set
97# CONFIG_CPU_NEVADA is not set
98# CONFIG_CPU_R8000 is not set
99# CONFIG_CPU_R10000 is not set
100# CONFIG_CPU_RM7000 is not set
101# CONFIG_CPU_RM9000 is not set
102# CONFIG_CPU_SB1 is not set
103CONFIG_SYS_HAS_CPU_MIPS32_R1=y
104CONFIG_CPU_MIPS32=y
105CONFIG_CPU_MIPSR1=y
106CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
107CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
108
109#
110# Kernel type
111#
112CONFIG_32BIT=y
113# CONFIG_64BIT is not set
114CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set
117# CONFIG_PAGE_SIZE_64KB is not set
118CONFIG_CPU_HAS_PREFETCH=y
119CONFIG_MIPS_MT_DISABLED=y
120# CONFIG_MIPS_MT_SMP is not set
121# CONFIG_MIPS_MT_SMTC is not set
122CONFIG_64BIT_PHYS_ADDR=y
123CONFIG_CPU_HAS_LLSC=y
124CONFIG_CPU_HAS_SYNC=y
125CONFIG_GENERIC_HARDIRQS=y
126CONFIG_GENERIC_IRQ_PROBE=y
127CONFIG_CPU_SUPPORTS_HIGHMEM=y
128CONFIG_ARCH_FLATMEM_ENABLE=y
129CONFIG_SELECT_MEMORY_MODEL=y
130CONFIG_FLATMEM_MANUAL=y
131# CONFIG_DISCONTIGMEM_MANUAL is not set
132# CONFIG_SPARSEMEM_MANUAL is not set
133CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4
137CONFIG_RESOURCES_64BIT=y
138CONFIG_ZONE_DMA_FLAG=0
139CONFIG_VIRT_TO_BUS=y
140# CONFIG_HZ_48 is not set
141# CONFIG_HZ_100 is not set
142# CONFIG_HZ_128 is not set
143CONFIG_HZ_250=y
144# CONFIG_HZ_256 is not set
145# CONFIG_HZ_1000 is not set
146# CONFIG_HZ_1024 is not set
147CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
148CONFIG_HZ=250
149# CONFIG_PREEMPT_NONE is not set
150CONFIG_PREEMPT_VOLUNTARY=y
151# CONFIG_PREEMPT is not set
152# CONFIG_KEXEC is not set
153CONFIG_SECCOMP=y
154CONFIG_LOCKDEP_SUPPORT=y
155CONFIG_STACKTRACE_SUPPORT=y
156CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
157
158#
159# General setup
160#
161CONFIG_EXPERIMENTAL=y
162CONFIG_BROKEN_ON_SMP=y
163CONFIG_INIT_ENV_ARG_LIMIT=32
164CONFIG_LOCALVERSION=""
165# CONFIG_LOCALVERSION_AUTO is not set
166CONFIG_SWAP=y
167CONFIG_SYSVIPC=y
168CONFIG_SYSVIPC_SYSCTL=y
169CONFIG_POSIX_MQUEUE=y
170CONFIG_BSD_PROCESS_ACCT=y
171CONFIG_BSD_PROCESS_ACCT_V3=y
172# CONFIG_TASKSTATS is not set
173# CONFIG_USER_NS is not set
174CONFIG_AUDIT=y
175# CONFIG_IKCONFIG is not set
176CONFIG_LOG_BUF_SHIFT=17
177CONFIG_SYSFS_DEPRECATED=y
178CONFIG_RELAY=y
179CONFIG_BLK_DEV_INITRD=y
180CONFIG_INITRAMFS_SOURCE=""
181# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
182CONFIG_SYSCTL=y
183CONFIG_EMBEDDED=y
184CONFIG_SYSCTL_SYSCALL=y
185CONFIG_KALLSYMS=y
186# CONFIG_KALLSYMS_EXTRA_PASS is not set
187CONFIG_HOTPLUG=y
188CONFIG_PRINTK=y
189CONFIG_BUG=y
190CONFIG_ELF_CORE=y
191CONFIG_BASE_FULL=y
192CONFIG_FUTEX=y
193CONFIG_ANON_INODES=y
194CONFIG_EPOLL=y
195CONFIG_SIGNALFD=y
196CONFIG_EVENTFD=y
197CONFIG_SHMEM=y
198CONFIG_VM_EVENT_COUNTERS=y
199CONFIG_SLAB=y
200# CONFIG_SLUB is not set
201# CONFIG_SLOB is not set
202CONFIG_RT_MUTEXES=y
203# CONFIG_TINY_SHMEM is not set
204CONFIG_BASE_SMALL=0
205CONFIG_MODULES=y
206CONFIG_MODULE_UNLOAD=y
207# CONFIG_MODULE_FORCE_UNLOAD is not set
208CONFIG_MODVERSIONS=y
209CONFIG_MODULE_SRCVERSION_ALL=y
210CONFIG_KMOD=y
211CONFIG_BLOCK=y
212CONFIG_LBD=y
213# CONFIG_BLK_DEV_IO_TRACE is not set
214# CONFIG_LSF is not set
215# CONFIG_BLK_DEV_BSG is not set
216
217#
218# IO Schedulers
219#
220CONFIG_IOSCHED_NOOP=y
221CONFIG_IOSCHED_AS=y
222CONFIG_IOSCHED_DEADLINE=y
223CONFIG_IOSCHED_CFQ=y
224# CONFIG_DEFAULT_AS is not set
225# CONFIG_DEFAULT_DEADLINE is not set
226CONFIG_DEFAULT_CFQ=y
227# CONFIG_DEFAULT_NOOP is not set
228CONFIG_DEFAULT_IOSCHED="cfq"
229
230#
231# Bus options (PCI, PCMCIA, EISA, ISA, TC)
232#
233CONFIG_HW_HAS_PCI=y
234CONFIG_PCI=y
235# CONFIG_ARCH_SUPPORTS_MSI is not set
236CONFIG_MMU=y
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241CONFIG_PCCARD=m
242# CONFIG_PCMCIA_DEBUG is not set
243CONFIG_PCMCIA=m
244CONFIG_PCMCIA_LOAD_CIS=y
245CONFIG_PCMCIA_IOCTL=y
246CONFIG_CARDBUS=y
247
248#
249# PC-card bridges
250#
251CONFIG_YENTA=m
252CONFIG_YENTA_O2=y
253CONFIG_YENTA_RICOH=y
254CONFIG_YENTA_TI=y
255CONFIG_YENTA_ENE_TUNE=y
256CONFIG_YENTA_TOSHIBA=y
257CONFIG_PD6729=m
258CONFIG_I82092=m
259# CONFIG_PCMCIA_AU1X00 is not set
260CONFIG_PCCARD_NONSTATIC=m
261# CONFIG_HOTPLUG_PCI is not set
262
263#
264# Executable file formats
265#
266CONFIG_BINFMT_ELF=y
267CONFIG_BINFMT_MISC=m
268CONFIG_TRAD_SIGNALS=y
269
270#
271# Power management options
272#
273CONFIG_PM=y
274# CONFIG_PM_LEGACY is not set
275# CONFIG_PM_DEBUG is not set
276CONFIG_PM_SLEEP=y
277CONFIG_SUSPEND_UP_POSSIBLE=y
278CONFIG_SUSPEND=y
279# CONFIG_APM_EMULATION is not set
280
281#
282# Networking
283#
284CONFIG_NET=y
285
286#
287# Networking options
288#
289CONFIG_PACKET=m
290CONFIG_PACKET_MMAP=y
291CONFIG_UNIX=y
292CONFIG_XFRM=y
293CONFIG_XFRM_USER=m
294# CONFIG_XFRM_SUB_POLICY is not set
295# CONFIG_XFRM_MIGRATE is not set
296CONFIG_NET_KEY=m
297# CONFIG_NET_KEY_MIGRATE is not set
298CONFIG_INET=y
299CONFIG_IP_MULTICAST=y
300CONFIG_IP_ADVANCED_ROUTER=y
301CONFIG_ASK_IP_FIB_HASH=y
302# CONFIG_IP_FIB_TRIE is not set
303CONFIG_IP_FIB_HASH=y
304CONFIG_IP_MULTIPLE_TABLES=y
305CONFIG_IP_ROUTE_MULTIPATH=y
306CONFIG_IP_ROUTE_VERBOSE=y
307# CONFIG_IP_PNP is not set
308CONFIG_NET_IPIP=m
309CONFIG_NET_IPGRE=m
310CONFIG_NET_IPGRE_BROADCAST=y
311CONFIG_IP_MROUTE=y
312CONFIG_IP_PIMSM_V1=y
313CONFIG_IP_PIMSM_V2=y
314# CONFIG_ARPD is not set
315CONFIG_SYN_COOKIES=y
316CONFIG_INET_AH=m
317CONFIG_INET_ESP=m
318CONFIG_INET_IPCOMP=m
319CONFIG_INET_XFRM_TUNNEL=m
320CONFIG_INET_TUNNEL=m
321CONFIG_INET_XFRM_MODE_TRANSPORT=m
322CONFIG_INET_XFRM_MODE_TUNNEL=m
323CONFIG_INET_XFRM_MODE_BEET=m
324CONFIG_INET_DIAG=y
325CONFIG_INET_TCP_DIAG=y
326# CONFIG_TCP_CONG_ADVANCED is not set
327CONFIG_TCP_CONG_CUBIC=y
328CONFIG_DEFAULT_TCP_CONG="cubic"
329# CONFIG_TCP_MD5SIG is not set
330CONFIG_IP_VS=m
331# CONFIG_IP_VS_DEBUG is not set
332CONFIG_IP_VS_TAB_BITS=12
333
334#
335# IPVS transport protocol load balancing support
336#
337CONFIG_IP_VS_PROTO_TCP=y
338CONFIG_IP_VS_PROTO_UDP=y
339CONFIG_IP_VS_PROTO_ESP=y
340CONFIG_IP_VS_PROTO_AH=y
341
342#
343# IPVS scheduler
344#
345CONFIG_IP_VS_RR=m
346CONFIG_IP_VS_WRR=m
347CONFIG_IP_VS_LC=m
348CONFIG_IP_VS_WLC=m
349CONFIG_IP_VS_LBLC=m
350CONFIG_IP_VS_LBLCR=m
351CONFIG_IP_VS_DH=m
352CONFIG_IP_VS_SH=m
353CONFIG_IP_VS_SED=m
354CONFIG_IP_VS_NQ=m
355
356#
357# IPVS application helper
358#
359CONFIG_IP_VS_FTP=m
360CONFIG_IPV6=m
361CONFIG_IPV6_PRIVACY=y
362# CONFIG_IPV6_ROUTER_PREF is not set
363# CONFIG_IPV6_OPTIMISTIC_DAD is not set
364CONFIG_INET6_AH=m
365CONFIG_INET6_ESP=m
366CONFIG_INET6_IPCOMP=m
367# CONFIG_IPV6_MIP6 is not set
368CONFIG_INET6_XFRM_TUNNEL=m
369CONFIG_INET6_TUNNEL=m
370CONFIG_INET6_XFRM_MODE_TRANSPORT=m
371CONFIG_INET6_XFRM_MODE_TUNNEL=m
372CONFIG_INET6_XFRM_MODE_BEET=m
373CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
374CONFIG_IPV6_SIT=m
375CONFIG_IPV6_TUNNEL=m
376# CONFIG_IPV6_MULTIPLE_TABLES is not set
377# CONFIG_NETLABEL is not set
378CONFIG_NETWORK_SECMARK=y
379CONFIG_NETFILTER=y
380# CONFIG_NETFILTER_DEBUG is not set
381CONFIG_BRIDGE_NETFILTER=y
382
383#
384# Core Netfilter Configuration
385#
386CONFIG_NETFILTER_NETLINK=m
387CONFIG_NETFILTER_NETLINK_QUEUE=m
388CONFIG_NETFILTER_NETLINK_LOG=m
389# CONFIG_NF_CONNTRACK_ENABLED is not set
390# CONFIG_NF_CONNTRACK is not set
391CONFIG_NETFILTER_XTABLES=m
392CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
393CONFIG_NETFILTER_XT_TARGET_DSCP=m
394CONFIG_NETFILTER_XT_TARGET_MARK=m
395CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
396# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
397# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
398CONFIG_NETFILTER_XT_TARGET_SECMARK=m
399# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
400CONFIG_NETFILTER_XT_MATCH_COMMENT=m
401CONFIG_NETFILTER_XT_MATCH_DCCP=m
402CONFIG_NETFILTER_XT_MATCH_DSCP=m
403CONFIG_NETFILTER_XT_MATCH_ESP=m
404CONFIG_NETFILTER_XT_MATCH_LENGTH=m
405CONFIG_NETFILTER_XT_MATCH_LIMIT=m
406CONFIG_NETFILTER_XT_MATCH_MAC=m
407CONFIG_NETFILTER_XT_MATCH_MARK=m
408CONFIG_NETFILTER_XT_MATCH_POLICY=m
409CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
410CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
411CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
412CONFIG_NETFILTER_XT_MATCH_QUOTA=m
413CONFIG_NETFILTER_XT_MATCH_REALM=m
414CONFIG_NETFILTER_XT_MATCH_SCTP=m
415CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
416CONFIG_NETFILTER_XT_MATCH_STRING=m
417CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
418# CONFIG_NETFILTER_XT_MATCH_U32 is not set
419# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
420
421#
422# IP: Netfilter Configuration
423#
424CONFIG_IP_NF_QUEUE=m
425CONFIG_IP_NF_IPTABLES=m
426CONFIG_IP_NF_MATCH_IPRANGE=m
427CONFIG_IP_NF_MATCH_TOS=m
428CONFIG_IP_NF_MATCH_RECENT=m
429CONFIG_IP_NF_MATCH_ECN=m
430CONFIG_IP_NF_MATCH_AH=m
431CONFIG_IP_NF_MATCH_TTL=m
432CONFIG_IP_NF_MATCH_OWNER=m
433CONFIG_IP_NF_MATCH_ADDRTYPE=m
434CONFIG_IP_NF_FILTER=m
435CONFIG_IP_NF_TARGET_REJECT=m
436CONFIG_IP_NF_TARGET_LOG=m
437CONFIG_IP_NF_TARGET_ULOG=m
438CONFIG_IP_NF_MANGLE=m
439CONFIG_IP_NF_TARGET_TOS=m
440CONFIG_IP_NF_TARGET_ECN=m
441CONFIG_IP_NF_TARGET_TTL=m
442CONFIG_IP_NF_RAW=m
443CONFIG_IP_NF_ARPTABLES=m
444CONFIG_IP_NF_ARPFILTER=m
445CONFIG_IP_NF_ARP_MANGLE=m
446
447#
448# IPv6: Netfilter Configuration (EXPERIMENTAL)
449#
450CONFIG_IP6_NF_QUEUE=m
451CONFIG_IP6_NF_IPTABLES=m
452CONFIG_IP6_NF_MATCH_RT=m
453CONFIG_IP6_NF_MATCH_OPTS=m
454CONFIG_IP6_NF_MATCH_FRAG=m
455CONFIG_IP6_NF_MATCH_HL=m
456CONFIG_IP6_NF_MATCH_OWNER=m
457CONFIG_IP6_NF_MATCH_IPV6HEADER=m
458CONFIG_IP6_NF_MATCH_AH=m
459# CONFIG_IP6_NF_MATCH_MH is not set
460CONFIG_IP6_NF_MATCH_EUI64=m
461CONFIG_IP6_NF_FILTER=m
462CONFIG_IP6_NF_TARGET_LOG=m
463CONFIG_IP6_NF_TARGET_REJECT=m
464CONFIG_IP6_NF_MANGLE=m
465CONFIG_IP6_NF_TARGET_HL=m
466CONFIG_IP6_NF_RAW=m
467
468#
469# DECnet: Netfilter Configuration
470#
471CONFIG_DECNET_NF_GRABULATOR=m
472
473#
474# Bridge: Netfilter Configuration
475#
476CONFIG_BRIDGE_NF_EBTABLES=m
477CONFIG_BRIDGE_EBT_BROUTE=m
478CONFIG_BRIDGE_EBT_T_FILTER=m
479CONFIG_BRIDGE_EBT_T_NAT=m
480CONFIG_BRIDGE_EBT_802_3=m
481CONFIG_BRIDGE_EBT_AMONG=m
482CONFIG_BRIDGE_EBT_ARP=m
483CONFIG_BRIDGE_EBT_IP=m
484CONFIG_BRIDGE_EBT_LIMIT=m
485CONFIG_BRIDGE_EBT_MARK=m
486CONFIG_BRIDGE_EBT_PKTTYPE=m
487CONFIG_BRIDGE_EBT_STP=m
488CONFIG_BRIDGE_EBT_VLAN=m
489CONFIG_BRIDGE_EBT_ARPREPLY=m
490CONFIG_BRIDGE_EBT_DNAT=m
491CONFIG_BRIDGE_EBT_MARK_T=m
492CONFIG_BRIDGE_EBT_REDIRECT=m
493CONFIG_BRIDGE_EBT_SNAT=m
494CONFIG_BRIDGE_EBT_LOG=m
495CONFIG_BRIDGE_EBT_ULOG=m
496CONFIG_IP_DCCP=m
497CONFIG_INET_DCCP_DIAG=m
498CONFIG_IP_DCCP_ACKVEC=y
499
500#
501# DCCP CCIDs Configuration (EXPERIMENTAL)
502#
503CONFIG_IP_DCCP_CCID2=m
504# CONFIG_IP_DCCP_CCID2_DEBUG is not set
505CONFIG_IP_DCCP_CCID3=m
506CONFIG_IP_DCCP_TFRC_LIB=m
507# CONFIG_IP_DCCP_CCID3_DEBUG is not set
508CONFIG_IP_DCCP_CCID3_RTO=100
509CONFIG_IP_SCTP=m
510# CONFIG_SCTP_DBG_MSG is not set
511# CONFIG_SCTP_DBG_OBJCNT is not set
512# CONFIG_SCTP_HMAC_NONE is not set
513# CONFIG_SCTP_HMAC_SHA1 is not set
514CONFIG_SCTP_HMAC_MD5=y
515CONFIG_TIPC=m
516# CONFIG_TIPC_ADVANCED is not set
517# CONFIG_TIPC_DEBUG is not set
518CONFIG_ATM=y
519CONFIG_ATM_CLIP=y
520# CONFIG_ATM_CLIP_NO_ICMP is not set
521CONFIG_ATM_LANE=m
522CONFIG_ATM_MPOA=m
523CONFIG_ATM_BR2684=m
524# CONFIG_ATM_BR2684_IPFILTER is not set
525CONFIG_BRIDGE=m
526CONFIG_VLAN_8021Q=m
527CONFIG_DECNET=m
528# CONFIG_DECNET_ROUTER is not set
529CONFIG_LLC=y
530CONFIG_LLC2=m
531CONFIG_IPX=m
532# CONFIG_IPX_INTERN is not set
533CONFIG_ATALK=m
534CONFIG_DEV_APPLETALK=m
535CONFIG_IPDDP=m
536CONFIG_IPDDP_ENCAP=y
537CONFIG_IPDDP_DECAP=y
538CONFIG_X25=m
539CONFIG_LAPB=m
540CONFIG_ECONET=m
541CONFIG_ECONET_AUNUDP=y
542CONFIG_ECONET_NATIVE=y
543CONFIG_WAN_ROUTER=m
544
545#
546# QoS and/or fair queueing
547#
548CONFIG_NET_SCHED=y
549CONFIG_NET_SCH_FIFO=y
550
551#
552# Queueing/Scheduling
553#
554CONFIG_NET_SCH_CBQ=m
555CONFIG_NET_SCH_HTB=m
556CONFIG_NET_SCH_HFSC=m
557CONFIG_NET_SCH_ATM=m
558CONFIG_NET_SCH_PRIO=m
559# CONFIG_NET_SCH_RR is not set
560CONFIG_NET_SCH_RED=m
561CONFIG_NET_SCH_SFQ=m
562CONFIG_NET_SCH_TEQL=m
563CONFIG_NET_SCH_TBF=m
564CONFIG_NET_SCH_GRED=m
565CONFIG_NET_SCH_DSMARK=m
566CONFIG_NET_SCH_NETEM=m
567CONFIG_NET_SCH_INGRESS=m
568
569#
570# Classification
571#
572CONFIG_NET_CLS=y
573CONFIG_NET_CLS_BASIC=m
574CONFIG_NET_CLS_TCINDEX=m
575CONFIG_NET_CLS_ROUTE4=m
576CONFIG_NET_CLS_ROUTE=y
577CONFIG_NET_CLS_FW=m
578CONFIG_NET_CLS_U32=m
579# CONFIG_CLS_U32_PERF is not set
580CONFIG_CLS_U32_MARK=y
581CONFIG_NET_CLS_RSVP=m
582CONFIG_NET_CLS_RSVP6=m
583CONFIG_NET_EMATCH=y
584CONFIG_NET_EMATCH_STACK=32
585CONFIG_NET_EMATCH_CMP=m
586CONFIG_NET_EMATCH_NBYTE=m
587CONFIG_NET_EMATCH_U32=m
588CONFIG_NET_EMATCH_META=m
589CONFIG_NET_EMATCH_TEXT=m
590CONFIG_NET_CLS_ACT=y
591CONFIG_NET_ACT_POLICE=y
592# CONFIG_NET_ACT_GACT is not set
593# CONFIG_NET_ACT_MIRRED is not set
594# CONFIG_NET_ACT_IPT is not set
595# CONFIG_NET_ACT_PEDIT is not set
596# CONFIG_NET_ACT_SIMP is not set
597CONFIG_NET_CLS_POLICE=y
598# CONFIG_NET_CLS_IND is not set
599
600#
601# Network testing
602#
603CONFIG_NET_PKTGEN=m
604CONFIG_HAMRADIO=y
605
606#
607# Packet Radio protocols
608#
609CONFIG_AX25=m
610# CONFIG_AX25_DAMA_SLAVE is not set
611CONFIG_NETROM=m
612CONFIG_ROSE=m
613
614#
615# AX.25 network device drivers
616#
617CONFIG_MKISS=m
618CONFIG_6PACK=m
619CONFIG_BPQETHER=m
620CONFIG_BAYCOM_SER_FDX=m
621CONFIG_BAYCOM_SER_HDX=m
622CONFIG_BAYCOM_PAR=m
623CONFIG_BAYCOM_EPP=m
624CONFIG_YAM=m
625CONFIG_IRDA=m
626
627#
628# IrDA protocols
629#
630CONFIG_IRLAN=m
631CONFIG_IRNET=m
632CONFIG_IRCOMM=m
633CONFIG_IRDA_ULTRA=y
634
635#
636# IrDA options
637#
638CONFIG_IRDA_CACHE_LAST_LSAP=y
639CONFIG_IRDA_FAST_RR=y
640CONFIG_IRDA_DEBUG=y
641
642#
643# Infrared-port device drivers
644#
645
646#
647# SIR device drivers
648#
649CONFIG_IRTTY_SIR=m
650
651#
652# Dongle support
653#
654CONFIG_DONGLE=y
655CONFIG_ESI_DONGLE=m
656CONFIG_ACTISYS_DONGLE=m
657CONFIG_TEKRAM_DONGLE=m
658# CONFIG_TOIM3232_DONGLE is not set
659CONFIG_LITELINK_DONGLE=m
660CONFIG_MA600_DONGLE=m
661CONFIG_GIRBIL_DONGLE=m
662CONFIG_MCP2120_DONGLE=m
663CONFIG_OLD_BELKIN_DONGLE=m
664CONFIG_ACT200L_DONGLE=m
665# CONFIG_KINGSUN_DONGLE is not set
666
667#
668# Old SIR device drivers
669#
670# CONFIG_IRPORT_SIR is not set
671
672#
673# Old Serial dongle support
674#
675
676#
677# FIR device drivers
678#
679CONFIG_USB_IRDA=m
680CONFIG_SIGMATEL_FIR=m
681CONFIG_TOSHIBA_FIR=m
682CONFIG_VLSI_FIR=m
683CONFIG_MCS_FIR=m
684CONFIG_BT=m
685CONFIG_BT_L2CAP=m
686CONFIG_BT_SCO=m
687CONFIG_BT_RFCOMM=m
688CONFIG_BT_RFCOMM_TTY=y
689CONFIG_BT_BNEP=m
690CONFIG_BT_BNEP_MC_FILTER=y
691CONFIG_BT_BNEP_PROTO_FILTER=y
692CONFIG_BT_CMTP=m
693CONFIG_BT_HIDP=m
694
695#
696# Bluetooth device drivers
697#
698CONFIG_BT_HCIUSB=m
699CONFIG_BT_HCIUSB_SCO=y
700CONFIG_BT_HCIUART=m
701CONFIG_BT_HCIUART_H4=y
702CONFIG_BT_HCIUART_BCSP=y
703CONFIG_BT_HCIBCM203X=m
704CONFIG_BT_HCIBPA10X=m
705CONFIG_BT_HCIBFUSB=m
706CONFIG_BT_HCIDTL1=m
707CONFIG_BT_HCIBT3C=m
708CONFIG_BT_HCIBLUECARD=m
709CONFIG_BT_HCIBTUART=m
710CONFIG_BT_HCIVHCI=m
711CONFIG_AF_RXRPC=m
712# CONFIG_AF_RXRPC_DEBUG is not set
713# CONFIG_RXKAD is not set
714CONFIG_FIB_RULES=y
715
716#
717# Wireless
718#
719# CONFIG_CFG80211 is not set
720CONFIG_WIRELESS_EXT=y
721# CONFIG_MAC80211 is not set
722CONFIG_IEEE80211=m
723# CONFIG_IEEE80211_DEBUG is not set
724CONFIG_IEEE80211_CRYPT_WEP=m
725CONFIG_IEEE80211_CRYPT_CCMP=m
726CONFIG_IEEE80211_CRYPT_TKIP=m
727CONFIG_IEEE80211_SOFTMAC=m
728# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
729# CONFIG_RFKILL is not set
730# CONFIG_NET_9P is not set
731
732#
733# Device Drivers
734#
735
736#
737# Generic Driver Options
738#
739CONFIG_STANDALONE=y
740CONFIG_PREVENT_FIRMWARE_BUILD=y
741CONFIG_FW_LOADER=y
742# CONFIG_SYS_HYPERVISOR is not set
743CONFIG_CONNECTOR=m
744CONFIG_MTD=m
745# CONFIG_MTD_DEBUG is not set
746CONFIG_MTD_CONCAT=m
747CONFIG_MTD_PARTITIONS=y
748CONFIG_MTD_REDBOOT_PARTS=m
749CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
750# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
751# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
752
753#
754# User Modules And Translation Layers
755#
756CONFIG_MTD_CHAR=m
757CONFIG_MTD_BLKDEVS=m
758CONFIG_MTD_BLOCK=m
759CONFIG_MTD_BLOCK_RO=m
760CONFIG_FTL=m
761CONFIG_NFTL=m
762CONFIG_NFTL_RW=y
763CONFIG_INFTL=m
764CONFIG_RFD_FTL=m
765CONFIG_SSFDC=m
766
767#
768# RAM/ROM/Flash chip drivers
769#
770CONFIG_MTD_CFI=m
771CONFIG_MTD_JEDECPROBE=m
772CONFIG_MTD_GEN_PROBE=m
773# CONFIG_MTD_CFI_ADV_OPTIONS is not set
774CONFIG_MTD_MAP_BANK_WIDTH_1=y
775CONFIG_MTD_MAP_BANK_WIDTH_2=y
776CONFIG_MTD_MAP_BANK_WIDTH_4=y
777# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
778# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
779# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
780CONFIG_MTD_CFI_I1=y
781CONFIG_MTD_CFI_I2=y
782# CONFIG_MTD_CFI_I4 is not set
783# CONFIG_MTD_CFI_I8 is not set
784CONFIG_MTD_CFI_INTELEXT=m
785CONFIG_MTD_CFI_AMDSTD=m
786CONFIG_MTD_CFI_STAA=m
787CONFIG_MTD_CFI_UTIL=m
788CONFIG_MTD_RAM=m
789CONFIG_MTD_ROM=m
790CONFIG_MTD_ABSENT=m
791
792#
793# Mapping drivers for chip access
794#
795CONFIG_MTD_COMPLEX_MAPPINGS=y
796CONFIG_MTD_PHYSMAP=m
797CONFIG_MTD_PHYSMAP_START=0x8000000
798CONFIG_MTD_PHYSMAP_LEN=0x4000000
799CONFIG_MTD_PHYSMAP_BANKWIDTH=2
800# CONFIG_MTD_ALCHEMY is not set
801# CONFIG_MTD_MTX1 is not set
802CONFIG_MTD_PCI=m
803CONFIG_MTD_PLATRAM=m
804
805#
806# Self-contained MTD device drivers
807#
808CONFIG_MTD_PMC551=m
809# CONFIG_MTD_PMC551_BUGFIX is not set
810# CONFIG_MTD_PMC551_DEBUG is not set
811CONFIG_MTD_DATAFLASH=m
812CONFIG_MTD_M25P80=m
813CONFIG_MTD_SLRAM=m
814CONFIG_MTD_PHRAM=m
815CONFIG_MTD_MTDRAM=m
816CONFIG_MTDRAM_TOTAL_SIZE=4096
817CONFIG_MTDRAM_ERASE_SIZE=128
818CONFIG_MTD_BLOCK2MTD=m
819
820#
821# Disk-On-Chip Device Drivers
822#
823CONFIG_MTD_DOC2000=m
824CONFIG_MTD_DOC2001=m
825CONFIG_MTD_DOC2001PLUS=m
826CONFIG_MTD_DOCPROBE=m
827CONFIG_MTD_DOCECC=m
828# CONFIG_MTD_DOCPROBE_ADVANCED is not set
829CONFIG_MTD_DOCPROBE_ADDRESS=0
830CONFIG_MTD_NAND=m
831# CONFIG_MTD_NAND_VERIFY_WRITE is not set
832# CONFIG_MTD_NAND_ECC_SMC is not set
833# CONFIG_MTD_NAND_MUSEUM_IDS is not set
834CONFIG_MTD_NAND_IDS=m
835CONFIG_MTD_NAND_DISKONCHIP=m
836# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
837CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
838# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
839# CONFIG_MTD_NAND_CAFE is not set
840CONFIG_MTD_NAND_NANDSIM=m
841# CONFIG_MTD_NAND_PLATFORM is not set
842CONFIG_MTD_ONENAND=m
843CONFIG_MTD_ONENAND_VERIFY_WRITE=y
844# CONFIG_MTD_ONENAND_OTP is not set
845
846#
847# UBI - Unsorted block images
848#
849# CONFIG_MTD_UBI is not set
850CONFIG_PARPORT=m
851CONFIG_PARPORT_PC=m
852CONFIG_PARPORT_SERIAL=m
853CONFIG_PARPORT_PC_FIFO=y
854CONFIG_PARPORT_PC_SUPERIO=y
855CONFIG_PARPORT_PC_PCMCIA=m
856# CONFIG_PARPORT_GSC is not set
857CONFIG_PARPORT_AX88796=m
858CONFIG_PARPORT_1284=y
859CONFIG_PARPORT_NOT_PC=y
860CONFIG_BLK_DEV=y
861CONFIG_PARIDE=m
862
863#
864# Parallel IDE high-level drivers
865#
866CONFIG_PARIDE_PD=m
867CONFIG_PARIDE_PCD=m
868CONFIG_PARIDE_PF=m
869CONFIG_PARIDE_PT=m
870CONFIG_PARIDE_PG=m
871
872#
873# Parallel IDE protocol modules
874#
875CONFIG_PARIDE_ATEN=m
876CONFIG_PARIDE_BPCK=m
877CONFIG_PARIDE_BPCK6=m
878CONFIG_PARIDE_COMM=m
879CONFIG_PARIDE_DSTR=m
880CONFIG_PARIDE_FIT2=m
881CONFIG_PARIDE_FIT3=m
882CONFIG_PARIDE_EPAT=m
883CONFIG_PARIDE_EPATC8=y
884CONFIG_PARIDE_EPIA=m
885CONFIG_PARIDE_FRIQ=m
886CONFIG_PARIDE_FRPW=m
887CONFIG_PARIDE_KBIC=m
888CONFIG_PARIDE_KTTI=m
889CONFIG_PARIDE_ON20=m
890CONFIG_PARIDE_ON26=m
891CONFIG_BLK_CPQ_DA=m
892CONFIG_BLK_CPQ_CISS_DA=m
893CONFIG_CISS_SCSI_TAPE=y
894CONFIG_BLK_DEV_DAC960=m
895CONFIG_BLK_DEV_UMEM=m
896# CONFIG_BLK_DEV_COW_COMMON is not set
897CONFIG_BLK_DEV_LOOP=m
898CONFIG_BLK_DEV_CRYPTOLOOP=m
899CONFIG_BLK_DEV_NBD=m
900CONFIG_BLK_DEV_SX8=m
901# CONFIG_BLK_DEV_UB is not set
902CONFIG_BLK_DEV_RAM=y
903CONFIG_BLK_DEV_RAM_COUNT=16
904CONFIG_BLK_DEV_RAM_SIZE=65536
905CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
906CONFIG_CDROM_PKTCDVD=m
907CONFIG_CDROM_PKTCDVD_BUFFERS=8
908# CONFIG_CDROM_PKTCDVD_WCACHE is not set
909CONFIG_ATA_OVER_ETH=m
910CONFIG_MISC_DEVICES=y
911# CONFIG_PHANTOM is not set
912# CONFIG_EEPROM_93CX6 is not set
913CONFIG_SGI_IOC4=m
914CONFIG_TIFM_CORE=m
915CONFIG_TIFM_7XX1=m
916CONFIG_IDE=y
917CONFIG_IDE_MAX_HWIFS=4
918CONFIG_BLK_DEV_IDE=y
919
920#
921# Please see Documentation/ide.txt for help/info on IDE drives
922#
923# CONFIG_BLK_DEV_IDE_SATA is not set
924CONFIG_BLK_DEV_IDEDISK=m
925# CONFIG_IDEDISK_MULTI_MODE is not set
926CONFIG_BLK_DEV_IDECS=m
927# CONFIG_BLK_DEV_DELKIN is not set
928CONFIG_BLK_DEV_IDECD=m
929CONFIG_BLK_DEV_IDETAPE=m
930CONFIG_BLK_DEV_IDEFLOPPY=m
931CONFIG_BLK_DEV_IDESCSI=m
932# CONFIG_IDE_TASK_IOCTL is not set
933CONFIG_IDE_PROC_FS=y
934
935#
936# IDE chipset support/bugfixes
937#
938CONFIG_IDE_GENERIC=m
939CONFIG_BLK_DEV_IDEPCI=y
940CONFIG_IDEPCI_SHARE_IRQ=y
941CONFIG_IDEPCI_PCIBUS_ORDER=y
942# CONFIG_BLK_DEV_OFFBOARD is not set
943CONFIG_BLK_DEV_GENERIC=m
944CONFIG_BLK_DEV_OPTI621=m
945CONFIG_BLK_DEV_IDEDMA_PCI=y
946# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
947# CONFIG_IDEDMA_ONLYDISK is not set
948CONFIG_BLK_DEV_AEC62XX=m
949CONFIG_BLK_DEV_ALI15X3=m
950# CONFIG_WDC_ALI15X3 is not set
951CONFIG_BLK_DEV_AMD74XX=m
952CONFIG_BLK_DEV_CMD64X=m
953CONFIG_BLK_DEV_TRIFLEX=m
954CONFIG_BLK_DEV_CY82C693=m
955# CONFIG_BLK_DEV_CS5520 is not set
956CONFIG_BLK_DEV_CS5530=m
957CONFIG_BLK_DEV_HPT34X=m
958# CONFIG_HPT34X_AUTODMA is not set
959CONFIG_BLK_DEV_HPT366=m
960# CONFIG_BLK_DEV_JMICRON is not set
961CONFIG_BLK_DEV_SC1200=m
962CONFIG_BLK_DEV_PIIX=m
963# CONFIG_BLK_DEV_IT8213 is not set
964CONFIG_BLK_DEV_IT821X=m
965CONFIG_BLK_DEV_NS87415=m
966CONFIG_BLK_DEV_PDC202XX_OLD=m
967CONFIG_PDC202XX_BURST=y
968CONFIG_BLK_DEV_PDC202XX_NEW=m
969CONFIG_BLK_DEV_SVWKS=m
970CONFIG_BLK_DEV_SIIMAGE=m
971# CONFIG_BLK_DEV_SLC90E66 is not set
972CONFIG_BLK_DEV_TRM290=m
973# CONFIG_BLK_DEV_VIA82CXXX is not set
974# CONFIG_BLK_DEV_TC86C001 is not set
975# CONFIG_IDE_ARM is not set
976CONFIG_BLK_DEV_IDEDMA=y
977# CONFIG_IDEDMA_IVB is not set
978# CONFIG_BLK_DEV_HD is not set
979
980#
981# SCSI device support
982#
983CONFIG_RAID_ATTRS=m
984CONFIG_SCSI=m
985CONFIG_SCSI_DMA=y
986# CONFIG_SCSI_TGT is not set
987CONFIG_SCSI_NETLINK=y
988CONFIG_SCSI_PROC_FS=y
989
990#
991# SCSI support type (disk, tape, CD-ROM)
992#
993CONFIG_BLK_DEV_SD=m
994CONFIG_CHR_DEV_ST=m
995CONFIG_CHR_DEV_OSST=m
996CONFIG_BLK_DEV_SR=m
997# CONFIG_BLK_DEV_SR_VENDOR is not set
998CONFIG_CHR_DEV_SG=m
999CONFIG_CHR_DEV_SCH=m
1000
1001#
1002# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1003#
1004CONFIG_SCSI_MULTI_LUN=y
1005CONFIG_SCSI_CONSTANTS=y
1006CONFIG_SCSI_LOGGING=y
1007# CONFIG_SCSI_SCAN_ASYNC is not set
1008CONFIG_SCSI_WAIT_SCAN=m
1009
1010#
1011# SCSI Transports
1012#
1013CONFIG_SCSI_SPI_ATTRS=m
1014CONFIG_SCSI_FC_ATTRS=m
1015CONFIG_SCSI_ISCSI_ATTRS=m
1016CONFIG_SCSI_SAS_ATTRS=m
1017CONFIG_SCSI_SAS_LIBSAS=m
1018# CONFIG_SCSI_SAS_ATA is not set
1019# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
1020CONFIG_SCSI_LOWLEVEL=y
1021CONFIG_ISCSI_TCP=m
1022CONFIG_BLK_DEV_3W_XXXX_RAID=m
1023CONFIG_SCSI_3W_9XXX=m
1024CONFIG_SCSI_ACARD=m
1025CONFIG_SCSI_AACRAID=m
1026CONFIG_SCSI_AIC7XXX=m
1027CONFIG_AIC7XXX_CMDS_PER_DEVICE=8
1028CONFIG_AIC7XXX_RESET_DELAY_MS=15000
1029CONFIG_AIC7XXX_DEBUG_ENABLE=y
1030CONFIG_AIC7XXX_DEBUG_MASK=0
1031CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
1032# CONFIG_SCSI_AIC7XXX_OLD is not set
1033CONFIG_SCSI_AIC79XX=m
1034CONFIG_AIC79XX_CMDS_PER_DEVICE=32
1035CONFIG_AIC79XX_RESET_DELAY_MS=15000
1036CONFIG_AIC79XX_DEBUG_ENABLE=y
1037CONFIG_AIC79XX_DEBUG_MASK=0
1038CONFIG_AIC79XX_REG_PRETTY_PRINT=y
1039CONFIG_SCSI_AIC94XX=m
1040# CONFIG_AIC94XX_DEBUG is not set
1041CONFIG_SCSI_DPT_I2O=m
1042CONFIG_SCSI_ARCMSR=m
1043CONFIG_MEGARAID_NEWGEN=y
1044CONFIG_MEGARAID_MM=m
1045CONFIG_MEGARAID_MAILBOX=m
1046CONFIG_MEGARAID_LEGACY=m
1047CONFIG_MEGARAID_SAS=m
1048CONFIG_SCSI_HPTIOP=m
1049CONFIG_SCSI_DMX3191D=m
1050CONFIG_SCSI_FUTURE_DOMAIN=m
1051CONFIG_SCSI_IPS=m
1052CONFIG_SCSI_INITIO=m
1053# CONFIG_SCSI_INIA100 is not set
1054CONFIG_SCSI_PPA=m
1055CONFIG_SCSI_IMM=m
1056# CONFIG_SCSI_IZIP_EPP16 is not set
1057# CONFIG_SCSI_IZIP_SLOW_CTR is not set
1058CONFIG_SCSI_STEX=m
1059CONFIG_SCSI_SYM53C8XX_2=m
1060CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
1061CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
1062CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
1063CONFIG_SCSI_SYM53C8XX_MMIO=y
1064CONFIG_SCSI_IPR=m
1065# CONFIG_SCSI_IPR_TRACE is not set
1066# CONFIG_SCSI_IPR_DUMP is not set
1067CONFIG_SCSI_QLOGIC_1280=m
1068CONFIG_SCSI_QLA_FC=m
1069CONFIG_SCSI_QLA_ISCSI=m
1070CONFIG_SCSI_LPFC=m
1071CONFIG_SCSI_DC395x=m
1072CONFIG_SCSI_DC390T=m
1073CONFIG_SCSI_NSP32=m
1074CONFIG_SCSI_DEBUG=m
1075# CONFIG_SCSI_SRP is not set
1076# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
1077CONFIG_ATA=m
1078# CONFIG_ATA_NONSTANDARD is not set
1079CONFIG_SATA_AHCI=m
1080CONFIG_SATA_SVW=m
1081CONFIG_ATA_PIIX=m
1082CONFIG_SATA_MV=m
1083CONFIG_SATA_NV=m
1084CONFIG_PDC_ADMA=m
1085CONFIG_SATA_QSTOR=m
1086CONFIG_SATA_PROMISE=m
1087CONFIG_SATA_SX4=m
1088CONFIG_SATA_SIL=m
1089CONFIG_SATA_SIL24=m
1090CONFIG_SATA_SIS=m
1091CONFIG_SATA_ULI=m
1092CONFIG_SATA_VIA=m
1093CONFIG_SATA_VITESSE=m
1094# CONFIG_SATA_INIC162X is not set
1095# CONFIG_PATA_ALI is not set
1096# CONFIG_PATA_AMD is not set
1097# CONFIG_PATA_ARTOP is not set
1098# CONFIG_PATA_ATIIXP is not set
1099# CONFIG_PATA_CMD640_PCI is not set
1100# CONFIG_PATA_CMD64X is not set
1101CONFIG_PATA_CS5520=m
1102# CONFIG_PATA_CS5530 is not set
1103# CONFIG_PATA_CYPRESS is not set
1104CONFIG_PATA_EFAR=m
1105CONFIG_ATA_GENERIC=m
1106# CONFIG_PATA_HPT366 is not set
1107# CONFIG_PATA_HPT37X is not set
1108# CONFIG_PATA_HPT3X2N is not set
1109# CONFIG_PATA_HPT3X3 is not set
1110# CONFIG_PATA_IT821X is not set
1111# CONFIG_PATA_IT8213 is not set
1112CONFIG_PATA_JMICRON=m
1113CONFIG_PATA_TRIFLEX=m
1114# CONFIG_PATA_MARVELL is not set
1115CONFIG_PATA_MPIIX=m
1116# CONFIG_PATA_OLDPIIX is not set
1117CONFIG_PATA_NETCELL=m
1118# CONFIG_PATA_NS87410 is not set
1119# CONFIG_PATA_OPTI is not set
1120# CONFIG_PATA_OPTIDMA is not set
1121CONFIG_PATA_PCMCIA=m
1122# CONFIG_PATA_PDC_OLD is not set
1123# CONFIG_PATA_RADISYS is not set
1124CONFIG_PATA_RZ1000=m
1125# CONFIG_PATA_SC1200 is not set
1126# CONFIG_PATA_SERVERWORKS is not set
1127CONFIG_PATA_PDC2027X=m
1128CONFIG_PATA_SIL680=m
1129CONFIG_PATA_SIS=m
1130CONFIG_PATA_VIA=m
1131CONFIG_PATA_WINBOND=m
1132# CONFIG_PATA_PLATFORM is not set
1133CONFIG_MD=y
1134CONFIG_BLK_DEV_MD=m
1135CONFIG_MD_LINEAR=m
1136CONFIG_MD_RAID0=m
1137CONFIG_MD_RAID1=m
1138CONFIG_MD_RAID10=m
1139CONFIG_MD_RAID456=m
1140# CONFIG_MD_RAID5_RESHAPE is not set
1141CONFIG_MD_MULTIPATH=m
1142CONFIG_MD_FAULTY=m
1143CONFIG_BLK_DEV_DM=m
1144# CONFIG_DM_DEBUG is not set
1145CONFIG_DM_CRYPT=m
1146CONFIG_DM_SNAPSHOT=m
1147CONFIG_DM_MIRROR=m
1148CONFIG_DM_ZERO=m
1149CONFIG_DM_MULTIPATH=m
1150CONFIG_DM_MULTIPATH_EMC=m
1151# CONFIG_DM_MULTIPATH_RDAC is not set
1152# CONFIG_DM_DELAY is not set
1153
1154#
1155# Fusion MPT device support
1156#
1157CONFIG_FUSION=y
1158CONFIG_FUSION_SPI=m
1159CONFIG_FUSION_FC=m
1160CONFIG_FUSION_SAS=m
1161CONFIG_FUSION_MAX_SGE=128
1162CONFIG_FUSION_CTL=m
1163CONFIG_FUSION_LAN=m
1164# CONFIG_FUSION_LOGGING is not set
1165
1166#
1167# IEEE 1394 (FireWire) support
1168#
1169# CONFIG_FIREWIRE is not set
1170CONFIG_IEEE1394=m
1171
1172#
1173# Subsystem Options
1174#
1175# CONFIG_IEEE1394_VERBOSEDEBUG is not set
1176
1177#
1178# Controllers
1179#
1180CONFIG_IEEE1394_PCILYNX=m
1181CONFIG_IEEE1394_OHCI1394=m
1182
1183#
1184# Protocols
1185#
1186CONFIG_IEEE1394_VIDEO1394=m
1187CONFIG_IEEE1394_SBP2=m
1188# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
1189CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y
1190CONFIG_IEEE1394_ETH1394=m
1191CONFIG_IEEE1394_DV1394=m
1192CONFIG_IEEE1394_RAWIO=m
1193CONFIG_I2O=m
1194CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y
1195CONFIG_I2O_EXT_ADAPTEC=y
1196CONFIG_I2O_CONFIG=m
1197CONFIG_I2O_CONFIG_OLD_IOCTL=y
1198CONFIG_I2O_BUS=m
1199CONFIG_I2O_BLOCK=m
1200CONFIG_I2O_SCSI=m
1201CONFIG_I2O_PROC=m
1202CONFIG_NETDEVICES=y
1203# CONFIG_NETDEVICES_MULTIQUEUE is not set
1204# CONFIG_IFB is not set
1205CONFIG_DUMMY=m
1206CONFIG_BONDING=m
1207# CONFIG_MACVLAN is not set
1208CONFIG_EQUALIZER=m
1209CONFIG_TUN=m
1210CONFIG_ARCNET=m
1211CONFIG_ARCNET_1201=m
1212CONFIG_ARCNET_1051=m
1213CONFIG_ARCNET_RAW=m
1214CONFIG_ARCNET_CAP=m
1215CONFIG_ARCNET_COM90xx=m
1216CONFIG_ARCNET_COM90xxIO=m
1217CONFIG_ARCNET_RIM_I=m
1218CONFIG_ARCNET_COM20020=m
1219CONFIG_ARCNET_COM20020_PCI=m
1220CONFIG_PHYLIB=m
1221
1222#
1223# MII PHY device drivers
1224#
1225CONFIG_MARVELL_PHY=m
1226CONFIG_DAVICOM_PHY=m
1227CONFIG_QSEMI_PHY=m
1228CONFIG_LXT_PHY=m
1229CONFIG_CICADA_PHY=m
1230CONFIG_VITESSE_PHY=m
1231CONFIG_SMSC_PHY=m
1232# CONFIG_BROADCOM_PHY is not set
1233# CONFIG_ICPLUS_PHY is not set
1234CONFIG_FIXED_PHY=m
1235# CONFIG_FIXED_MII_10_FDX is not set
1236# CONFIG_FIXED_MII_100_FDX is not set
1237CONFIG_NET_ETHERNET=y
1238CONFIG_MII=m
1239# CONFIG_AX88796 is not set
1240# CONFIG_MIPS_AU1X00_ENET is not set
1241CONFIG_HAPPYMEAL=m
1242CONFIG_SUNGEM=m
1243CONFIG_CASSINI=m
1244CONFIG_NET_VENDOR_3COM=y
1245CONFIG_VORTEX=m
1246CONFIG_TYPHOON=m
1247# CONFIG_SMC91X is not set
1248# CONFIG_DM9000 is not set
1249CONFIG_NET_TULIP=y
1250CONFIG_DE2104X=m
1251CONFIG_TULIP=m
1252# CONFIG_TULIP_MWI is not set
1253# CONFIG_TULIP_MMIO is not set
1254# CONFIG_TULIP_NAPI is not set
1255CONFIG_DE4X5=m
1256CONFIG_WINBOND_840=m
1257CONFIG_DM9102=m
1258CONFIG_ULI526X=m
1259CONFIG_PCMCIA_XIRCOM=m
1260# CONFIG_PCMCIA_XIRTULIP is not set
1261CONFIG_HP100=m
1262CONFIG_NET_PCI=y
1263CONFIG_PCNET32=m
1264# CONFIG_PCNET32_NAPI is not set
1265CONFIG_AMD8111_ETH=m
1266# CONFIG_AMD8111E_NAPI is not set
1267CONFIG_ADAPTEC_STARFIRE=m
1268# CONFIG_ADAPTEC_STARFIRE_NAPI is not set
1269CONFIG_B44=m
1270CONFIG_FORCEDETH=m
1271# CONFIG_FORCEDETH_NAPI is not set
1272# CONFIG_TC35815 is not set
1273CONFIG_DGRS=m
1274CONFIG_EEPRO100=m
1275CONFIG_E100=m
1276CONFIG_FEALNX=m
1277CONFIG_NATSEMI=m
1278CONFIG_NE2K_PCI=m
1279CONFIG_8139CP=m
1280CONFIG_8139TOO=m
1281# CONFIG_8139TOO_PIO is not set
1282# CONFIG_8139TOO_TUNE_TWISTER is not set
1283CONFIG_8139TOO_8129=y
1284# CONFIG_8139_OLD_RX_RESET is not set
1285CONFIG_SIS900=m
1286CONFIG_EPIC100=m
1287CONFIG_SUNDANCE=m
1288# CONFIG_SUNDANCE_MMIO is not set
1289CONFIG_TLAN=m
1290CONFIG_VIA_RHINE=m
1291# CONFIG_VIA_RHINE_MMIO is not set
1292# CONFIG_VIA_RHINE_NAPI is not set
1293# CONFIG_SC92031 is not set
1294CONFIG_NET_POCKET=y
1295CONFIG_DE600=m
1296CONFIG_DE620=m
1297CONFIG_NETDEV_1000=y
1298CONFIG_ACENIC=m
1299# CONFIG_ACENIC_OMIT_TIGON_I is not set
1300CONFIG_DL2K=m
1301CONFIG_E1000=m
1302# CONFIG_E1000_NAPI is not set
1303# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
1304CONFIG_NS83820=m
1305CONFIG_HAMACHI=m
1306CONFIG_YELLOWFIN=m
1307CONFIG_R8169=m
1308# CONFIG_R8169_NAPI is not set
1309CONFIG_R8169_VLAN=y
1310CONFIG_SIS190=m
1311CONFIG_SKGE=m
1312CONFIG_SKY2=m
1313CONFIG_SK98LIN=m
1314CONFIG_VIA_VELOCITY=m
1315CONFIG_TIGON3=m
1316CONFIG_BNX2=m
1317CONFIG_QLA3XXX=m
1318# CONFIG_ATL1 is not set
1319CONFIG_NETDEV_10000=y
1320CONFIG_CHELSIO_T1=m
1321# CONFIG_CHELSIO_T1_1G is not set
1322CONFIG_CHELSIO_T1_NAPI=y
1323# CONFIG_CHELSIO_T3 is not set
1324CONFIG_IXGB=m
1325# CONFIG_IXGB_NAPI is not set
1326CONFIG_S2IO=m
1327# CONFIG_S2IO_NAPI is not set
1328CONFIG_MYRI10GE=m
1329# CONFIG_NETXEN_NIC is not set
1330# CONFIG_MLX4_CORE is not set
1331CONFIG_TR=y
1332CONFIG_IBMOL=m
1333CONFIG_IBMLS=m
1334CONFIG_3C359=m
1335CONFIG_TMS380TR=m
1336CONFIG_TMSPCI=m
1337CONFIG_ABYSS=m
1338
1339#
1340# Wireless LAN
1341#
1342# CONFIG_WLAN_PRE80211 is not set
1343# CONFIG_WLAN_80211 is not set
1344
1345#
1346# USB Network Adapters
1347#
1348CONFIG_USB_CATC=m
1349CONFIG_USB_KAWETH=m
1350CONFIG_USB_PEGASUS=m
1351CONFIG_USB_RTL8150=m
1352CONFIG_USB_USBNET_MII=m
1353CONFIG_USB_USBNET=m
1354CONFIG_USB_NET_AX8817X=m
1355CONFIG_USB_NET_CDCETHER=m
1356# CONFIG_USB_NET_DM9601 is not set
1357CONFIG_USB_NET_GL620A=m
1358CONFIG_USB_NET_NET1080=m
1359CONFIG_USB_NET_PLUSB=m
1360CONFIG_USB_NET_MCS7830=m
1361CONFIG_USB_NET_RNDIS_HOST=m
1362CONFIG_USB_NET_CDC_SUBSET=m
1363CONFIG_USB_ALI_M5632=y
1364CONFIG_USB_AN2720=y
1365CONFIG_USB_BELKIN=y
1366CONFIG_USB_ARMLINUX=y
1367CONFIG_USB_EPSON2888=y
1368# CONFIG_USB_KC2190 is not set
1369CONFIG_USB_NET_ZAURUS=m
1370CONFIG_NET_PCMCIA=y
1371CONFIG_PCMCIA_3C589=m
1372CONFIG_PCMCIA_3C574=m
1373CONFIG_PCMCIA_FMVJ18X=m
1374CONFIG_PCMCIA_PCNET=m
1375CONFIG_PCMCIA_NMCLAN=m
1376CONFIG_PCMCIA_SMC91C92=m
1377CONFIG_PCMCIA_XIRC2PS=m
1378CONFIG_PCMCIA_AXNET=m
1379CONFIG_ARCNET_COM20020_CS=m
1380CONFIG_PCMCIA_IBMTR=m
1381CONFIG_WAN=y
1382CONFIG_LANMEDIA=m
1383CONFIG_HDLC=m
1384CONFIG_HDLC_RAW=m
1385CONFIG_HDLC_RAW_ETH=m
1386CONFIG_HDLC_CISCO=m
1387CONFIG_HDLC_FR=m
1388CONFIG_HDLC_PPP=m
1389CONFIG_HDLC_X25=m
1390CONFIG_PCI200SYN=m
1391CONFIG_WANXL=m
1392CONFIG_PC300=m
1393CONFIG_PC300_MLPPP=y
1394
1395#
1396# Cyclades-PC300 MLPPP support is disabled.
1397#
1398
1399#
1400# Refer to the file README.mlppp, provided by PC300 package.
1401#
1402# CONFIG_PC300TOO is not set
1403CONFIG_FARSYNC=m
1404CONFIG_DSCC4=m
1405CONFIG_DSCC4_PCISYNC=y
1406CONFIG_DSCC4_PCI_RST=y
1407CONFIG_DLCI=m
1408CONFIG_DLCI_MAX=8
1409CONFIG_WAN_ROUTER_DRIVERS=m
1410CONFIG_CYCLADES_SYNC=m
1411CONFIG_CYCLOMX_X25=y
1412CONFIG_LAPBETHER=m
1413CONFIG_X25_ASY=m
1414CONFIG_ATM_DRIVERS=y
1415# CONFIG_ATM_DUMMY is not set
1416CONFIG_ATM_TCP=m
1417CONFIG_ATM_LANAI=m
1418CONFIG_ATM_ENI=m
1419# CONFIG_ATM_ENI_DEBUG is not set
1420# CONFIG_ATM_ENI_TUNE_BURST is not set
1421CONFIG_ATM_FIRESTREAM=m
1422CONFIG_ATM_ZATM=m
1423# CONFIG_ATM_ZATM_DEBUG is not set
1424CONFIG_ATM_NICSTAR=m
1425# CONFIG_ATM_NICSTAR_USE_SUNI is not set
1426# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
1427CONFIG_ATM_IDT77252=m
1428# CONFIG_ATM_IDT77252_DEBUG is not set
1429# CONFIG_ATM_IDT77252_RCV_ALL is not set
1430CONFIG_ATM_IDT77252_USE_SUNI=y
1431CONFIG_ATM_AMBASSADOR=m
1432# CONFIG_ATM_AMBASSADOR_DEBUG is not set
1433CONFIG_ATM_HORIZON=m
1434# CONFIG_ATM_HORIZON_DEBUG is not set
1435CONFIG_ATM_IA=m
1436# CONFIG_ATM_IA_DEBUG is not set
1437CONFIG_ATM_FORE200E_MAYBE=m
1438CONFIG_ATM_FORE200E_PCA=y
1439CONFIG_ATM_FORE200E_PCA_DEFAULT_FW=y
1440# CONFIG_ATM_FORE200E_USE_TASKLET is not set
1441CONFIG_ATM_FORE200E_TX_RETRY=16
1442CONFIG_ATM_FORE200E_DEBUG=0
1443CONFIG_ATM_FORE200E=m
1444CONFIG_ATM_HE=m
1445CONFIG_ATM_HE_USE_SUNI=y
1446CONFIG_FDDI=y
1447CONFIG_DEFXX=m
1448# CONFIG_DEFXX_MMIO is not set
1449CONFIG_SKFP=m
1450CONFIG_HIPPI=y
1451CONFIG_ROADRUNNER=m
1452# CONFIG_ROADRUNNER_LARGE_RINGS is not set
1453CONFIG_PLIP=m
1454CONFIG_PPP=m
1455CONFIG_PPP_MULTILINK=y
1456CONFIG_PPP_FILTER=y
1457CONFIG_PPP_ASYNC=m
1458CONFIG_PPP_SYNC_TTY=m
1459CONFIG_PPP_DEFLATE=m
1460CONFIG_PPP_BSDCOMP=m
1461CONFIG_PPP_MPPE=m
1462CONFIG_PPPOE=m
1463CONFIG_PPPOATM=m
1464# CONFIG_PPPOL2TP is not set
1465CONFIG_SLIP=m
1466CONFIG_SLIP_COMPRESSED=y
1467CONFIG_SLHC=m
1468CONFIG_SLIP_SMART=y
1469CONFIG_SLIP_MODE_SLIP6=y
1470CONFIG_NET_FC=y
1471CONFIG_SHAPER=m
1472CONFIG_NETCONSOLE=m
1473CONFIG_NETPOLL=y
1474# CONFIG_NETPOLL_TRAP is not set
1475CONFIG_NET_POLL_CONTROLLER=y
1476CONFIG_ISDN=m
1477CONFIG_ISDN_I4L=m
1478CONFIG_ISDN_PPP=y
1479CONFIG_ISDN_PPP_VJ=y
1480CONFIG_ISDN_MPP=y
1481CONFIG_IPPP_FILTER=y
1482CONFIG_ISDN_PPP_BSDCOMP=m
1483CONFIG_ISDN_AUDIO=y
1484CONFIG_ISDN_TTY_FAX=y
1485CONFIG_ISDN_X25=y
1486
1487#
1488# ISDN feature submodules
1489#
1490# CONFIG_ISDN_DRV_LOOP is not set
1491CONFIG_ISDN_DIVERSION=m
1492
1493#
1494# ISDN4Linux hardware drivers
1495#
1496
1497#
1498# Passive cards
1499#
1500CONFIG_ISDN_DRV_HISAX=m
1501
1502#
1503# D-channel protocol features
1504#
1505CONFIG_HISAX_EURO=y
1506CONFIG_DE_AOC=y
1507# CONFIG_HISAX_NO_SENDCOMPLETE is not set
1508# CONFIG_HISAX_NO_LLC is not set
1509# CONFIG_HISAX_NO_KEYPAD is not set
1510CONFIG_HISAX_1TR6=y
1511CONFIG_HISAX_NI1=y
1512CONFIG_HISAX_MAX_CARDS=8
1513
1514#
1515# HiSax supported cards
1516#
1517CONFIG_HISAX_16_3=y
1518CONFIG_HISAX_TELESPCI=y
1519CONFIG_HISAX_S0BOX=y
1520CONFIG_HISAX_FRITZPCI=y
1521CONFIG_HISAX_AVM_A1_PCMCIA=y
1522CONFIG_HISAX_ELSA=y
1523CONFIG_HISAX_DIEHLDIVA=y
1524CONFIG_HISAX_SEDLBAUER=y
1525CONFIG_HISAX_NETJET=y
1526CONFIG_HISAX_NETJET_U=y
1527CONFIG_HISAX_NICCY=y
1528CONFIG_HISAX_BKM_A4T=y
1529CONFIG_HISAX_SCT_QUADRO=y
1530CONFIG_HISAX_GAZEL=y
1531CONFIG_HISAX_HFC_PCI=y
1532CONFIG_HISAX_W6692=y
1533CONFIG_HISAX_HFC_SX=y
1534CONFIG_HISAX_ENTERNOW_PCI=y
1535# CONFIG_HISAX_DEBUG is not set
1536
1537#
1538# HiSax PCMCIA card service modules
1539#
1540CONFIG_HISAX_SEDLBAUER_CS=m
1541CONFIG_HISAX_ELSA_CS=m
1542CONFIG_HISAX_AVM_A1_CS=m
1543CONFIG_HISAX_TELES_CS=m
1544
1545#
1546# HiSax sub driver modules
1547#
1548CONFIG_HISAX_ST5481=m
1549CONFIG_HISAX_HFCUSB=m
1550CONFIG_HISAX_HFC4S8S=m
1551CONFIG_HISAX_FRITZ_PCIPNP=m
1552CONFIG_HISAX_HDLC=y
1553
1554#
1555# Active cards
1556#
1557# CONFIG_HYSDN is not set
1558CONFIG_ISDN_DRV_GIGASET=m
1559CONFIG_GIGASET_BASE=m
1560CONFIG_GIGASET_M105=m
1561# CONFIG_GIGASET_M101 is not set
1562# CONFIG_GIGASET_DEBUG is not set
1563# CONFIG_GIGASET_UNDOCREQ is not set
1564CONFIG_ISDN_CAPI=m
1565CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
1566CONFIG_CAPI_TRACE=y
1567CONFIG_ISDN_CAPI_MIDDLEWARE=y
1568CONFIG_ISDN_CAPI_CAPI20=m
1569CONFIG_ISDN_CAPI_CAPIFS_BOOL=y
1570CONFIG_ISDN_CAPI_CAPIFS=m
1571CONFIG_ISDN_CAPI_CAPIDRV=m
1572
1573#
1574# CAPI hardware drivers
1575#
1576CONFIG_CAPI_AVM=y
1577CONFIG_ISDN_DRV_AVMB1_B1PCI=m
1578CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y
1579CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
1580CONFIG_ISDN_DRV_AVMB1_AVM_CS=m
1581CONFIG_ISDN_DRV_AVMB1_T1PCI=m
1582CONFIG_ISDN_DRV_AVMB1_C4=m
1583CONFIG_CAPI_EICON=y
1584CONFIG_ISDN_DIVAS=m
1585CONFIG_ISDN_DIVAS_BRIPCI=y
1586CONFIG_ISDN_DIVAS_PRIPCI=y
1587CONFIG_ISDN_DIVAS_DIVACAPI=m
1588CONFIG_ISDN_DIVAS_USERIDI=m
1589CONFIG_ISDN_DIVAS_MAINT=m
1590CONFIG_PHONE=m
1591CONFIG_PHONE_IXJ=m
1592CONFIG_PHONE_IXJ_PCMCIA=m
1593
1594#
1595# Input device support
1596#
1597CONFIG_INPUT=y
1598CONFIG_INPUT_FF_MEMLESS=m
1599# CONFIG_INPUT_POLLDEV is not set
1600
1601#
1602# Userland interfaces
1603#
1604CONFIG_INPUT_MOUSEDEV=y
1605CONFIG_INPUT_MOUSEDEV_PSAUX=y
1606CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1607CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1608CONFIG_INPUT_JOYDEV=m
1609CONFIG_INPUT_TSDEV=m
1610CONFIG_INPUT_TSDEV_SCREEN_X=240
1611CONFIG_INPUT_TSDEV_SCREEN_Y=320
1612CONFIG_INPUT_EVDEV=m
1613CONFIG_INPUT_EVBUG=m
1614
1615#
1616# Input Device Drivers
1617#
1618CONFIG_INPUT_KEYBOARD=y
1619CONFIG_KEYBOARD_ATKBD=y
1620CONFIG_KEYBOARD_SUNKBD=m
1621CONFIG_KEYBOARD_LKKBD=m
1622CONFIG_KEYBOARD_XTKBD=m
1623CONFIG_KEYBOARD_NEWTON=m
1624CONFIG_KEYBOARD_STOWAWAY=m
1625CONFIG_INPUT_MOUSE=y
1626CONFIG_MOUSE_PS2=m
1627CONFIG_MOUSE_PS2_ALPS=y
1628CONFIG_MOUSE_PS2_LOGIPS2PP=y
1629CONFIG_MOUSE_PS2_SYNAPTICS=y
1630CONFIG_MOUSE_PS2_LIFEBOOK=y
1631CONFIG_MOUSE_PS2_TRACKPOINT=y
1632# CONFIG_MOUSE_PS2_TOUCHKIT is not set
1633CONFIG_MOUSE_SERIAL=m
1634# CONFIG_MOUSE_APPLETOUCH is not set
1635CONFIG_MOUSE_VSXXXAA=m
1636CONFIG_INPUT_JOYSTICK=y
1637CONFIG_JOYSTICK_ANALOG=m
1638CONFIG_JOYSTICK_A3D=m
1639CONFIG_JOYSTICK_ADI=m
1640CONFIG_JOYSTICK_COBRA=m
1641CONFIG_JOYSTICK_GF2K=m
1642CONFIG_JOYSTICK_GRIP=m
1643CONFIG_JOYSTICK_GRIP_MP=m
1644CONFIG_JOYSTICK_GUILLEMOT=m
1645CONFIG_JOYSTICK_INTERACT=m
1646CONFIG_JOYSTICK_SIDEWINDER=m
1647CONFIG_JOYSTICK_TMDC=m
1648CONFIG_JOYSTICK_IFORCE=m
1649CONFIG_JOYSTICK_IFORCE_USB=y
1650CONFIG_JOYSTICK_IFORCE_232=y
1651CONFIG_JOYSTICK_WARRIOR=m
1652CONFIG_JOYSTICK_MAGELLAN=m
1653CONFIG_JOYSTICK_SPACEORB=m
1654CONFIG_JOYSTICK_SPACEBALL=m
1655CONFIG_JOYSTICK_STINGER=m
1656CONFIG_JOYSTICK_TWIDJOY=m
1657CONFIG_JOYSTICK_DB9=m
1658CONFIG_JOYSTICK_GAMECON=m
1659CONFIG_JOYSTICK_TURBOGRAFX=m
1660CONFIG_JOYSTICK_JOYDUMP=m
1661# CONFIG_JOYSTICK_XPAD is not set
1662# CONFIG_INPUT_TABLET is not set
1663CONFIG_INPUT_TOUCHSCREEN=y
1664CONFIG_TOUCHSCREEN_ADS7846=m
1665# CONFIG_TOUCHSCREEN_FUJITSU is not set
1666CONFIG_TOUCHSCREEN_GUNZE=m
1667CONFIG_TOUCHSCREEN_ELO=m
1668CONFIG_TOUCHSCREEN_MTOUCH=m
1669CONFIG_TOUCHSCREEN_MK712=m
1670CONFIG_TOUCHSCREEN_PENMOUNT=m
1671CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
1672CONFIG_TOUCHSCREEN_TOUCHWIN=m
1673# CONFIG_TOUCHSCREEN_UCB1400 is not set
1674# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1675CONFIG_INPUT_MISC=y
1676CONFIG_INPUT_PCSPKR=m
1677# CONFIG_INPUT_ATI_REMOTE is not set
1678# CONFIG_INPUT_ATI_REMOTE2 is not set
1679# CONFIG_INPUT_KEYSPAN_REMOTE is not set
1680# CONFIG_INPUT_POWERMATE is not set
1681# CONFIG_INPUT_YEALINK is not set
1682CONFIG_INPUT_UINPUT=m
1683
1684#
1685# Hardware I/O ports
1686#
1687CONFIG_SERIO=y
1688CONFIG_SERIO_I8042=y
1689CONFIG_SERIO_SERPORT=m
1690CONFIG_SERIO_PARKBD=m
1691CONFIG_SERIO_PCIPS2=m
1692CONFIG_SERIO_LIBPS2=y
1693CONFIG_SERIO_RAW=m
1694CONFIG_GAMEPORT=m
1695CONFIG_GAMEPORT_NS558=m
1696CONFIG_GAMEPORT_L4=m
1697CONFIG_GAMEPORT_EMU10K1=m
1698CONFIG_GAMEPORT_FM801=m
1699
1700#
1701# Character devices
1702#
1703CONFIG_VT=y
1704CONFIG_VT_CONSOLE=y
1705CONFIG_HW_CONSOLE=y
1706CONFIG_VT_HW_CONSOLE_BINDING=y
1707CONFIG_SERIAL_NONSTANDARD=y
1708# CONFIG_COMPUTONE is not set
1709CONFIG_ROCKETPORT=m
1710CONFIG_CYCLADES=m
1711# CONFIG_CYZ_INTR is not set
1712CONFIG_DIGIEPCA=m
1713# CONFIG_MOXA_INTELLIO is not set
1714CONFIG_MOXA_SMARTIO=m
1715# CONFIG_MOXA_SMARTIO_NEW is not set
1716# CONFIG_ISI is not set
1717CONFIG_SYNCLINKMP=m
1718CONFIG_SYNCLINK_GT=m
1719CONFIG_N_HDLC=m
1720# CONFIG_RISCOM8 is not set
1721CONFIG_SPECIALIX=m
1722# CONFIG_SPECIALIX_RTSCTS is not set
1723CONFIG_SX=m
1724# CONFIG_RIO is not set
1725CONFIG_STALDRV=y
1726# CONFIG_STALLION is not set
1727# CONFIG_ISTALLION is not set
1728
1729#
1730# Serial drivers
1731#
1732CONFIG_SERIAL_8250=m
1733CONFIG_SERIAL_8250_PCI=m
1734CONFIG_SERIAL_8250_CS=m
1735CONFIG_SERIAL_8250_NR_UARTS=48
1736CONFIG_SERIAL_8250_RUNTIME_UARTS=4
1737CONFIG_SERIAL_8250_EXTENDED=y
1738CONFIG_SERIAL_8250_MANY_PORTS=y
1739CONFIG_SERIAL_8250_SHARE_IRQ=y
1740# CONFIG_SERIAL_8250_DETECT_IRQ is not set
1741CONFIG_SERIAL_8250_RSA=y
1742# CONFIG_SERIAL_8250_AU1X00 is not set
1743
1744#
1745# Non-8250 serial port support
1746#
1747CONFIG_SERIAL_CORE=m
1748CONFIG_SERIAL_JSM=m
1749CONFIG_UNIX98_PTYS=y
1750CONFIG_LEGACY_PTYS=y
1751CONFIG_LEGACY_PTY_COUNT=256
1752CONFIG_PRINTER=m
1753# CONFIG_LP_CONSOLE is not set
1754CONFIG_PPDEV=m
1755CONFIG_TIPAR=m
1756CONFIG_IPMI_HANDLER=m
1757# CONFIG_IPMI_PANIC_EVENT is not set
1758CONFIG_IPMI_DEVICE_INTERFACE=m
1759CONFIG_IPMI_SI=m
1760CONFIG_IPMI_WATCHDOG=m
1761CONFIG_IPMI_POWEROFF=m
1762CONFIG_WATCHDOG=y
1763# CONFIG_WATCHDOG_NOWAYOUT is not set
1764
1765#
1766# Watchdog Device Drivers
1767#
1768CONFIG_SOFT_WATCHDOG=m
1769# CONFIG_WDT_MTX1 is not set
1770
1771#
1772# PCI-based Watchdog Cards
1773#
1774CONFIG_PCIPCWATCHDOG=m
1775CONFIG_WDTPCI=m
1776CONFIG_WDT_501_PCI=y
1777
1778#
1779# USB-based Watchdog Cards
1780#
1781CONFIG_USBPCWATCHDOG=m
1782CONFIG_HW_RANDOM=y
1783CONFIG_RTC=y
1784CONFIG_R3964=m
1785CONFIG_APPLICOM=m
1786CONFIG_DRM=m
1787CONFIG_DRM_TDFX=m
1788CONFIG_DRM_R128=m
1789CONFIG_DRM_RADEON=m
1790CONFIG_DRM_MGA=m
1791CONFIG_DRM_VIA=m
1792CONFIG_DRM_SAVAGE=m
1793
1794#
1795# PCMCIA character devices
1796#
1797CONFIG_SYNCLINK_CS=m
1798CONFIG_CARDMAN_4000=m
1799CONFIG_CARDMAN_4040=m
1800CONFIG_RAW_DRIVER=m
1801CONFIG_MAX_RAW_DEVS=256
1802CONFIG_TCG_TPM=m
1803CONFIG_TCG_ATMEL=m
1804CONFIG_DEVPORT=y
1805CONFIG_I2C=m
1806CONFIG_I2C_BOARDINFO=y
1807CONFIG_I2C_CHARDEV=m
1808
1809#
1810# I2C Algorithms
1811#
1812CONFIG_I2C_ALGOBIT=m
1813CONFIG_I2C_ALGOPCF=m
1814CONFIG_I2C_ALGOPCA=m
1815
1816#
1817# I2C Hardware Bus support
1818#
1819CONFIG_I2C_ALI1535=m
1820CONFIG_I2C_ALI1563=m
1821CONFIG_I2C_ALI15X3=m
1822CONFIG_I2C_AMD756=m
1823CONFIG_I2C_AMD756_S4882=m
1824CONFIG_I2C_AMD8111=m
1825CONFIG_I2C_I801=m
1826CONFIG_I2C_I810=m
1827CONFIG_I2C_PIIX4=m
1828CONFIG_I2C_NFORCE2=m
1829CONFIG_I2C_OCORES=m
1830CONFIG_I2C_PARPORT=m
1831CONFIG_I2C_PARPORT_LIGHT=m
1832CONFIG_I2C_PROSAVAGE=m
1833CONFIG_I2C_SAVAGE4=m
1834# CONFIG_I2C_SIMTEC is not set
1835CONFIG_I2C_SIS5595=m
1836CONFIG_I2C_SIS630=m
1837CONFIG_I2C_SIS96X=m
1838# CONFIG_I2C_TAOS_EVM is not set
1839CONFIG_I2C_STUB=m
1840# CONFIG_I2C_TINY_USB is not set
1841CONFIG_I2C_VIA=m
1842CONFIG_I2C_VIAPRO=m
1843CONFIG_I2C_VOODOO3=m
1844
1845#
1846# Miscellaneous I2C Chip support
1847#
1848CONFIG_SENSORS_DS1337=m
1849CONFIG_SENSORS_DS1374=m
1850# CONFIG_DS1682 is not set
1851CONFIG_SENSORS_EEPROM=m
1852CONFIG_SENSORS_PCF8574=m
1853CONFIG_SENSORS_PCA9539=m
1854CONFIG_SENSORS_PCF8591=m
1855CONFIG_SENSORS_MAX6875=m
1856# CONFIG_SENSORS_TSL2550 is not set
1857# CONFIG_I2C_DEBUG_CORE is not set
1858# CONFIG_I2C_DEBUG_ALGO is not set
1859# CONFIG_I2C_DEBUG_BUS is not set
1860# CONFIG_I2C_DEBUG_CHIP is not set
1861
1862#
1863# SPI support
1864#
1865CONFIG_SPI=y
1866CONFIG_SPI_MASTER=y
1867
1868#
1869# SPI Master Controller Drivers
1870#
1871CONFIG_SPI_BITBANG=m
1872CONFIG_SPI_BUTTERFLY=m
1873# CONFIG_SPI_LM70_LLP is not set
1874
1875#
1876# SPI Protocol Masters
1877#
1878# CONFIG_SPI_AT25 is not set
1879# CONFIG_SPI_SPIDEV is not set
1880# CONFIG_SPI_TLE62X0 is not set
1881CONFIG_W1=m
1882CONFIG_W1_CON=y
1883
1884#
1885# 1-wire Bus Masters
1886#
1887CONFIG_W1_MASTER_MATROX=m
1888CONFIG_W1_MASTER_DS2490=m
1889CONFIG_W1_MASTER_DS2482=m
1890
1891#
1892# 1-wire Slaves
1893#
1894CONFIG_W1_SLAVE_THERM=m
1895CONFIG_W1_SLAVE_SMEM=m
1896CONFIG_W1_SLAVE_DS2433=m
1897# CONFIG_W1_SLAVE_DS2433_CRC is not set
1898# CONFIG_W1_SLAVE_DS2760 is not set
1899# CONFIG_POWER_SUPPLY is not set
1900CONFIG_HWMON=y
1901CONFIG_HWMON_VID=m
1902CONFIG_SENSORS_ABITUGURU=m
1903# CONFIG_SENSORS_ABITUGURU3 is not set
1904# CONFIG_SENSORS_AD7418 is not set
1905CONFIG_SENSORS_ADM1021=m
1906CONFIG_SENSORS_ADM1025=m
1907CONFIG_SENSORS_ADM1026=m
1908# CONFIG_SENSORS_ADM1029 is not set
1909CONFIG_SENSORS_ADM1031=m
1910CONFIG_SENSORS_ADM9240=m
1911CONFIG_SENSORS_ASB100=m
1912CONFIG_SENSORS_ATXP1=m
1913CONFIG_SENSORS_DS1621=m
1914CONFIG_SENSORS_F71805F=m
1915CONFIG_SENSORS_FSCHER=m
1916CONFIG_SENSORS_FSCPOS=m
1917CONFIG_SENSORS_GL518SM=m
1918CONFIG_SENSORS_GL520SM=m
1919CONFIG_SENSORS_IT87=m
1920CONFIG_SENSORS_LM63=m
1921CONFIG_SENSORS_LM70=m
1922CONFIG_SENSORS_LM75=m
1923CONFIG_SENSORS_LM77=m
1924CONFIG_SENSORS_LM78=m
1925CONFIG_SENSORS_LM80=m
1926CONFIG_SENSORS_LM83=m
1927CONFIG_SENSORS_LM85=m
1928CONFIG_SENSORS_LM87=m
1929CONFIG_SENSORS_LM90=m
1930CONFIG_SENSORS_LM92=m
1931# CONFIG_SENSORS_LM93 is not set
1932CONFIG_SENSORS_MAX1619=m
1933# CONFIG_SENSORS_MAX6650 is not set
1934CONFIG_SENSORS_PC87360=m
1935# CONFIG_SENSORS_PC87427 is not set
1936CONFIG_SENSORS_SIS5595=m
1937# CONFIG_SENSORS_DME1737 is not set
1938CONFIG_SENSORS_SMSC47M1=m
1939CONFIG_SENSORS_SMSC47M192=m
1940CONFIG_SENSORS_SMSC47B397=m
1941# CONFIG_SENSORS_THMC50 is not set
1942CONFIG_SENSORS_VIA686A=m
1943CONFIG_SENSORS_VT1211=m
1944CONFIG_SENSORS_VT8231=m
1945CONFIG_SENSORS_W83781D=m
1946CONFIG_SENSORS_W83791D=m
1947CONFIG_SENSORS_W83792D=m
1948# CONFIG_SENSORS_W83793 is not set
1949CONFIG_SENSORS_W83L785TS=m
1950CONFIG_SENSORS_W83627HF=m
1951CONFIG_SENSORS_W83627EHF=m
1952# CONFIG_HWMON_DEBUG_CHIP is not set
1953
1954#
1955# Multifunction device drivers
1956#
1957# CONFIG_MFD_SM501 is not set
1958
1959#
1960# Multimedia devices
1961#
1962CONFIG_VIDEO_DEV=m
1963CONFIG_VIDEO_V4L1=y
1964CONFIG_VIDEO_V4L1_COMPAT=y
1965CONFIG_VIDEO_V4L2=y
1966CONFIG_VIDEO_CAPTURE_DRIVERS=y
1967# CONFIG_VIDEO_ADV_DEBUG is not set
1968CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1969CONFIG_VIDEO_TVAUDIO=m
1970CONFIG_VIDEO_TDA7432=m
1971CONFIG_VIDEO_TDA9840=m
1972CONFIG_VIDEO_TDA9875=m
1973CONFIG_VIDEO_TEA6415C=m
1974CONFIG_VIDEO_TEA6420=m
1975CONFIG_VIDEO_MSP3400=m
1976CONFIG_VIDEO_WM8775=m
1977CONFIG_VIDEO_BT819=m
1978CONFIG_VIDEO_BT856=m
1979CONFIG_VIDEO_KS0127=m
1980CONFIG_VIDEO_SAA7110=m
1981CONFIG_VIDEO_SAA7111=m
1982CONFIG_VIDEO_SAA7114=m
1983CONFIG_VIDEO_SAA711X=m
1984CONFIG_VIDEO_TVP5150=m
1985CONFIG_VIDEO_VPX3220=m
1986CONFIG_VIDEO_CX25840=m
1987CONFIG_VIDEO_CX2341X=m
1988CONFIG_VIDEO_SAA7185=m
1989CONFIG_VIDEO_ADV7170=m
1990CONFIG_VIDEO_ADV7175=m
1991CONFIG_VIDEO_VIVI=m
1992CONFIG_VIDEO_BT848=m
1993CONFIG_VIDEO_BT848_DVB=y
1994CONFIG_VIDEO_SAA6588=m
1995CONFIG_VIDEO_BWQCAM=m
1996CONFIG_VIDEO_CQCAM=m
1997CONFIG_VIDEO_W9966=m
1998CONFIG_VIDEO_CPIA=m
1999CONFIG_VIDEO_CPIA_PP=m
2000CONFIG_VIDEO_CPIA_USB=m
2001CONFIG_VIDEO_CPIA2=m
2002CONFIG_VIDEO_SAA5246A=m
2003CONFIG_VIDEO_SAA5249=m
2004CONFIG_TUNER_3036=m
2005# CONFIG_TUNER_TEA5761 is not set
2006CONFIG_VIDEO_STRADIS=m
2007CONFIG_VIDEO_ZORAN_ZR36060=m
2008CONFIG_VIDEO_ZORAN=m
2009CONFIG_VIDEO_ZORAN_BUZ=m
2010CONFIG_VIDEO_ZORAN_DC10=m
2011CONFIG_VIDEO_ZORAN_DC30=m
2012CONFIG_VIDEO_ZORAN_LML33=m
2013CONFIG_VIDEO_ZORAN_LML33R10=m
2014CONFIG_VIDEO_ZORAN_AVS6EYES=m
2015CONFIG_VIDEO_SAA7134=m
2016CONFIG_VIDEO_SAA7134_ALSA=m
2017CONFIG_VIDEO_SAA7134_OSS=m
2018CONFIG_VIDEO_SAA7134_DVB=m
2019CONFIG_VIDEO_MXB=m
2020CONFIG_VIDEO_DPC=m
2021CONFIG_VIDEO_HEXIUM_ORION=m
2022CONFIG_VIDEO_HEXIUM_GEMINI=m
2023CONFIG_VIDEO_CX88=m
2024CONFIG_VIDEO_CX88_ALSA=m
2025CONFIG_VIDEO_CX88_BLACKBIRD=m
2026CONFIG_VIDEO_CX88_DVB=m
2027CONFIG_VIDEO_CX88_VP3054=m
2028# CONFIG_VIDEO_IVTV is not set
2029# CONFIG_VIDEO_CAFE_CCIC is not set
2030CONFIG_V4L_USB_DRIVERS=y
2031CONFIG_VIDEO_PVRUSB2=m
2032CONFIG_VIDEO_PVRUSB2_29XXX=y
2033CONFIG_VIDEO_PVRUSB2_24XXX=y
2034CONFIG_VIDEO_PVRUSB2_SYSFS=y
2035# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
2036CONFIG_VIDEO_EM28XX=m
2037# CONFIG_VIDEO_USBVISION is not set
2038CONFIG_VIDEO_USBVIDEO=m
2039CONFIG_USB_VICAM=m
2040CONFIG_USB_IBMCAM=m
2041CONFIG_USB_KONICAWC=m
2042CONFIG_USB_QUICKCAM_MESSENGER=m
2043CONFIG_USB_ET61X251=m
2044CONFIG_VIDEO_OVCAMCHIP=m
2045CONFIG_USB_W9968CF=m
2046# CONFIG_USB_OV511 is not set
2047CONFIG_USB_SE401=m
2048CONFIG_USB_SN9C102=m
2049CONFIG_USB_STV680=m
2050CONFIG_USB_ZC0301=m
2051CONFIG_USB_PWC=m
2052# CONFIG_USB_PWC_DEBUG is not set
2053# CONFIG_USB_ZR364XX is not set
2054CONFIG_RADIO_ADAPTERS=y
2055CONFIG_RADIO_GEMTEK_PCI=m
2056CONFIG_RADIO_MAXIRADIO=m
2057CONFIG_RADIO_MAESTRO=m
2058CONFIG_USB_DSBR=m
2059CONFIG_DVB_CORE=m
2060CONFIG_DVB_CORE_ATTACH=y
2061CONFIG_DVB_CAPTURE_DRIVERS=y
2062
2063#
2064# Supported SAA7146 based PCI Adapters
2065#
2066CONFIG_DVB_AV7110=m
2067CONFIG_DVB_AV7110_OSD=y
2068CONFIG_DVB_BUDGET=m
2069CONFIG_DVB_BUDGET_CI=m
2070CONFIG_DVB_BUDGET_AV=m
2071CONFIG_DVB_BUDGET_PATCH=m
2072
2073#
2074# Supported USB Adapters
2075#
2076CONFIG_DVB_USB=m
2077# CONFIG_DVB_USB_DEBUG is not set
2078CONFIG_DVB_USB_A800=m
2079CONFIG_DVB_USB_DIBUSB_MB=m
2080CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
2081CONFIG_DVB_USB_DIBUSB_MC=m
2082CONFIG_DVB_USB_DIB0700=m
2083CONFIG_DVB_USB_UMT_010=m
2084CONFIG_DVB_USB_CXUSB=m
2085# CONFIG_DVB_USB_M920X is not set
2086# CONFIG_DVB_USB_GL861 is not set
2087# CONFIG_DVB_USB_AU6610 is not set
2088CONFIG_DVB_USB_DIGITV=m
2089CONFIG_DVB_USB_VP7045=m
2090CONFIG_DVB_USB_VP702X=m
2091CONFIG_DVB_USB_GP8PSK=m
2092CONFIG_DVB_USB_NOVA_T_USB2=m
2093# CONFIG_DVB_USB_TTUSB2 is not set
2094CONFIG_DVB_USB_DTT200U=m
2095# CONFIG_DVB_USB_OPERA1 is not set
2096# CONFIG_DVB_USB_AF9005 is not set
2097CONFIG_DVB_TTUSB_BUDGET=m
2098CONFIG_DVB_TTUSB_DEC=m
2099CONFIG_DVB_CINERGYT2=m
2100CONFIG_DVB_CINERGYT2_TUNING=y
2101CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32
2102CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512
2103CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250
2104CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y
2105CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100
2106
2107#
2108# Supported FlexCopII (B2C2) Adapters
2109#
2110CONFIG_DVB_B2C2_FLEXCOP=m
2111CONFIG_DVB_B2C2_FLEXCOP_PCI=m
2112CONFIG_DVB_B2C2_FLEXCOP_USB=m
2113# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
2114
2115#
2116# Supported BT878 Adapters
2117#
2118CONFIG_DVB_BT8XX=m
2119
2120#
2121# Supported Pluto2 Adapters
2122#
2123CONFIG_DVB_PLUTO2=m
2124
2125#
2126# Supported DVB Frontends
2127#
2128
2129#
2130# Customise DVB Frontends
2131#
2132# CONFIG_DVB_FE_CUSTOMISE is not set
2133
2134#
2135# DVB-S (satellite) frontends
2136#
2137CONFIG_DVB_STV0299=m
2138CONFIG_DVB_CX24110=m
2139CONFIG_DVB_CX24123=m
2140CONFIG_DVB_TDA8083=m
2141CONFIG_DVB_MT312=m
2142CONFIG_DVB_VES1X93=m
2143CONFIG_DVB_S5H1420=m
2144CONFIG_DVB_TDA10086=m
2145
2146#
2147# DVB-T (terrestrial) frontends
2148#
2149CONFIG_DVB_SP8870=m
2150CONFIG_DVB_SP887X=m
2151CONFIG_DVB_CX22700=m
2152CONFIG_DVB_CX22702=m
2153CONFIG_DVB_L64781=m
2154CONFIG_DVB_TDA1004X=m
2155CONFIG_DVB_NXT6000=m
2156CONFIG_DVB_MT352=m
2157CONFIG_DVB_ZL10353=m
2158CONFIG_DVB_DIB3000MB=m
2159CONFIG_DVB_DIB3000MC=m
2160CONFIG_DVB_DIB7000M=m
2161CONFIG_DVB_DIB7000P=m
2162
2163#
2164# DVB-C (cable) frontends
2165#
2166CONFIG_DVB_VES1820=m
2167CONFIG_DVB_TDA10021=m
2168CONFIG_DVB_TDA10023=m
2169CONFIG_DVB_STV0297=m
2170
2171#
2172# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
2173#
2174CONFIG_DVB_NXT200X=m
2175CONFIG_DVB_OR51211=m
2176CONFIG_DVB_OR51132=m
2177CONFIG_DVB_BCM3510=m
2178CONFIG_DVB_LGDT330X=m
2179
2180#
2181# Tuners/PLL support
2182#
2183CONFIG_DVB_PLL=m
2184CONFIG_DVB_TDA826X=m
2185CONFIG_DVB_TDA827X=m
2186# CONFIG_DVB_TUNER_QT1010 is not set
2187CONFIG_DVB_TUNER_MT2060=m
2188
2189#
2190# Miscellaneous devices
2191#
2192CONFIG_DVB_LNBP21=m
2193CONFIG_DVB_ISL6421=m
2194CONFIG_DVB_TUA6100=m
2195CONFIG_VIDEO_SAA7146=m
2196CONFIG_VIDEO_SAA7146_VV=m
2197CONFIG_VIDEO_TUNER=m
2198CONFIG_VIDEO_BUF=m
2199CONFIG_VIDEO_BUF_DVB=m
2200CONFIG_VIDEO_BTCX=m
2201CONFIG_VIDEO_IR_I2C=m
2202CONFIG_VIDEO_IR=m
2203CONFIG_VIDEO_TVEEPROM=m
2204CONFIG_DAB=y
2205CONFIG_USB_DABUSB=m
2206
2207#
2208# Graphics support
2209#
2210CONFIG_BACKLIGHT_LCD_SUPPORT=y
2211CONFIG_LCD_CLASS_DEVICE=m
2212CONFIG_BACKLIGHT_CLASS_DEVICE=y
2213
2214#
2215# Display device support
2216#
2217# CONFIG_DISPLAY_SUPPORT is not set
2218CONFIG_VGASTATE=m
2219CONFIG_VIDEO_OUTPUT_CONTROL=m
2220CONFIG_FB=y
2221CONFIG_FIRMWARE_EDID=y
2222CONFIG_FB_DDC=m
2223CONFIG_FB_CFB_FILLRECT=m
2224CONFIG_FB_CFB_COPYAREA=m
2225CONFIG_FB_CFB_IMAGEBLIT=m
2226# CONFIG_FB_SYS_FILLRECT is not set
2227# CONFIG_FB_SYS_COPYAREA is not set
2228# CONFIG_FB_SYS_IMAGEBLIT is not set
2229# CONFIG_FB_SYS_FOPS is not set
2230CONFIG_FB_DEFERRED_IO=y
2231# CONFIG_FB_SVGALIB is not set
2232# CONFIG_FB_MACMODES is not set
2233CONFIG_FB_BACKLIGHT=y
2234CONFIG_FB_MODE_HELPERS=y
2235CONFIG_FB_TILEBLITTING=y
2236
2237#
2238# Frame buffer hardware drivers
2239#
2240CONFIG_FB_CIRRUS=m
2241CONFIG_FB_PM2=m
2242CONFIG_FB_PM2_FIFO_DISCONNECT=y
2243CONFIG_FB_CYBER2000=m
2244# CONFIG_FB_ASILIANT is not set
2245# CONFIG_FB_IMSTT is not set
2246CONFIG_FB_S1D13XXX=m
2247CONFIG_FB_NVIDIA=m
2248CONFIG_FB_NVIDIA_I2C=y
2249# CONFIG_FB_NVIDIA_DEBUG is not set
2250CONFIG_FB_NVIDIA_BACKLIGHT=y
2251CONFIG_FB_RIVA=m
2252CONFIG_FB_RIVA_I2C=y
2253# CONFIG_FB_RIVA_DEBUG is not set
2254CONFIG_FB_RIVA_BACKLIGHT=y
2255CONFIG_FB_MATROX=m
2256CONFIG_FB_MATROX_MILLENIUM=y
2257CONFIG_FB_MATROX_MYSTIQUE=y
2258CONFIG_FB_MATROX_G=y
2259CONFIG_FB_MATROX_I2C=m
2260CONFIG_FB_MATROX_MAVEN=m
2261CONFIG_FB_MATROX_MULTIHEAD=y
2262CONFIG_FB_RADEON=m
2263CONFIG_FB_RADEON_I2C=y
2264CONFIG_FB_RADEON_BACKLIGHT=y
2265# CONFIG_FB_RADEON_DEBUG is not set
2266CONFIG_FB_ATY128=m
2267CONFIG_FB_ATY128_BACKLIGHT=y
2268CONFIG_FB_ATY=m
2269CONFIG_FB_ATY_CT=y
2270CONFIG_FB_ATY_GENERIC_LCD=y
2271CONFIG_FB_ATY_GX=y
2272CONFIG_FB_ATY_BACKLIGHT=y
2273# CONFIG_FB_S3 is not set
2274CONFIG_FB_SAVAGE=m
2275CONFIG_FB_SAVAGE_I2C=y
2276CONFIG_FB_SAVAGE_ACCEL=y
2277CONFIG_FB_SIS=m
2278CONFIG_FB_SIS_300=y
2279CONFIG_FB_SIS_315=y
2280CONFIG_FB_NEOMAGIC=m
2281CONFIG_FB_KYRO=m
2282CONFIG_FB_3DFX=m
2283# CONFIG_FB_3DFX_ACCEL is not set
2284CONFIG_FB_VOODOO1=m
2285# CONFIG_FB_VT8623 is not set
2286CONFIG_FB_TRIDENT=m
2287# CONFIG_FB_TRIDENT_ACCEL is not set
2288# CONFIG_FB_ARK is not set
2289# CONFIG_FB_PM3 is not set
2290# CONFIG_FB_VIRTUAL is not set
2291
2292#
2293# Console display driver support
2294#
2295CONFIG_VGA_CONSOLE=y
2296# CONFIG_VGACON_SOFT_SCROLLBACK is not set
2297CONFIG_DUMMY_CONSOLE=y
2298CONFIG_FRAMEBUFFER_CONSOLE=m
2299# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
2300# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
2301# CONFIG_FONTS is not set
2302CONFIG_FONT_8x8=y
2303CONFIG_FONT_8x16=y
2304# CONFIG_LOGO is not set
2305
2306#
2307# Sound
2308#
2309CONFIG_SOUND=m
2310
2311#
2312# Advanced Linux Sound Architecture
2313#
2314CONFIG_SND=m
2315CONFIG_SND_TIMER=m
2316CONFIG_SND_PCM=m
2317CONFIG_SND_HWDEP=m
2318CONFIG_SND_RAWMIDI=m
2319CONFIG_SND_SEQUENCER=m
2320CONFIG_SND_SEQ_DUMMY=m
2321CONFIG_SND_OSSEMUL=y
2322CONFIG_SND_MIXER_OSS=m
2323CONFIG_SND_PCM_OSS=m
2324CONFIG_SND_PCM_OSS_PLUGINS=y
2325CONFIG_SND_SEQUENCER_OSS=y
2326CONFIG_SND_RTCTIMER=m
2327CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y
2328CONFIG_SND_DYNAMIC_MINORS=y
2329CONFIG_SND_SUPPORT_OLD_API=y
2330CONFIG_SND_VERBOSE_PROCFS=y
2331# CONFIG_SND_VERBOSE_PRINTK is not set
2332# CONFIG_SND_DEBUG is not set
2333
2334#
2335# Generic devices
2336#
2337CONFIG_SND_MPU401_UART=m
2338CONFIG_SND_OPL3_LIB=m
2339CONFIG_SND_VX_LIB=m
2340CONFIG_SND_AC97_CODEC=m
2341CONFIG_SND_DUMMY=m
2342CONFIG_SND_VIRMIDI=m
2343CONFIG_SND_MTPAV=m
2344CONFIG_SND_MTS64=m
2345CONFIG_SND_SERIAL_U16550=m
2346CONFIG_SND_MPU401=m
2347# CONFIG_SND_PORTMAN2X4 is not set
2348
2349#
2350# PCI devices
2351#
2352CONFIG_SND_AD1889=m
2353CONFIG_SND_ALS300=m
2354CONFIG_SND_ALI5451=m
2355CONFIG_SND_ATIIXP=m
2356CONFIG_SND_ATIIXP_MODEM=m
2357CONFIG_SND_AU8810=m
2358CONFIG_SND_AU8820=m
2359CONFIG_SND_AU8830=m
2360CONFIG_SND_AZT3328=m
2361CONFIG_SND_BT87X=m
2362# CONFIG_SND_BT87X_OVERCLOCK is not set
2363CONFIG_SND_CA0106=m
2364CONFIG_SND_CMIPCI=m
2365CONFIG_SND_CS4281=m
2366CONFIG_SND_CS46XX=m
2367CONFIG_SND_CS46XX_NEW_DSP=y
2368CONFIG_SND_DARLA20=m
2369CONFIG_SND_GINA20=m
2370CONFIG_SND_LAYLA20=m
2371CONFIG_SND_DARLA24=m
2372CONFIG_SND_GINA24=m
2373CONFIG_SND_LAYLA24=m
2374CONFIG_SND_MONA=m
2375CONFIG_SND_MIA=m
2376CONFIG_SND_ECHO3G=m
2377CONFIG_SND_INDIGO=m
2378CONFIG_SND_INDIGOIO=m
2379CONFIG_SND_INDIGODJ=m
2380CONFIG_SND_EMU10K1=m
2381CONFIG_SND_EMU10K1X=m
2382CONFIG_SND_ENS1370=m
2383CONFIG_SND_ENS1371=m
2384CONFIG_SND_ES1938=m
2385CONFIG_SND_ES1968=m
2386CONFIG_SND_FM801=m
2387CONFIG_SND_FM801_TEA575X_BOOL=y
2388CONFIG_SND_FM801_TEA575X=m
2389CONFIG_SND_HDA_INTEL=m
2390CONFIG_SND_HDSP=m
2391CONFIG_SND_HDSPM=m
2392CONFIG_SND_ICE1712=m
2393CONFIG_SND_ICE1724=m
2394CONFIG_SND_INTEL8X0=m
2395CONFIG_SND_INTEL8X0M=m
2396CONFIG_SND_KORG1212=m
2397CONFIG_SND_KORG1212_FIRMWARE_IN_KERNEL=y
2398CONFIG_SND_MAESTRO3=m
2399CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL=y
2400CONFIG_SND_MIXART=m
2401CONFIG_SND_NM256=m
2402CONFIG_SND_PCXHR=m
2403CONFIG_SND_RIPTIDE=m
2404CONFIG_SND_RME32=m
2405CONFIG_SND_RME96=m
2406CONFIG_SND_RME9652=m
2407CONFIG_SND_SONICVIBES=m
2408CONFIG_SND_TRIDENT=m
2409CONFIG_SND_VIA82XX=m
2410CONFIG_SND_VIA82XX_MODEM=m
2411CONFIG_SND_VX222=m
2412CONFIG_SND_YMFPCI=m
2413CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y
2414# CONFIG_SND_AC97_POWER_SAVE is not set
2415
2416#
2417# ALSA MIPS devices
2418#
2419# CONFIG_SND_AU1X00 is not set
2420
2421#
2422# USB devices
2423#
2424CONFIG_SND_USB_AUDIO=m
2425# CONFIG_SND_USB_CAIAQ is not set
2426
2427#
2428# PCMCIA devices
2429#
2430CONFIG_SND_VXPOCKET=m
2431CONFIG_SND_PDAUDIOCF=m
2432
2433#
2434# System on Chip audio support
2435#
2436# CONFIG_SND_SOC is not set
2437
2438#
2439# SoC Audio support for SuperH
2440#
2441
2442#
2443# Open Sound System
2444#
2445CONFIG_SOUND_PRIME=m
2446CONFIG_SOUND_TRIDENT=m
2447# CONFIG_SOUND_MSNDCLAS is not set
2448# CONFIG_SOUND_MSNDPIN is not set
2449CONFIG_AC97_BUS=m
2450CONFIG_HID_SUPPORT=y
2451CONFIG_HID=y
2452# CONFIG_HID_DEBUG is not set
2453
2454#
2455# USB Input Devices
2456#
2457CONFIG_USB_HID=m
2458CONFIG_USB_HIDINPUT_POWERBOOK=y
2459# CONFIG_HID_FF is not set
2460CONFIG_USB_HIDDEV=y
2461
2462#
2463# USB HID Boot Protocol drivers
2464#
2465CONFIG_USB_KBD=m
2466CONFIG_USB_MOUSE=m
2467CONFIG_USB_SUPPORT=y
2468CONFIG_USB_ARCH_HAS_HCD=y
2469CONFIG_USB_ARCH_HAS_OHCI=y
2470CONFIG_USB_ARCH_HAS_EHCI=y
2471CONFIG_USB=m
2472# CONFIG_USB_DEBUG is not set
2473
2474#
2475# Miscellaneous USB options
2476#
2477CONFIG_USB_DEVICEFS=y
2478CONFIG_USB_DEVICE_CLASS=y
2479# CONFIG_USB_DYNAMIC_MINORS is not set
2480CONFIG_USB_SUSPEND=y
2481# CONFIG_USB_PERSIST is not set
2482# CONFIG_USB_OTG is not set
2483
2484#
2485# USB Host Controller Drivers
2486#
2487CONFIG_USB_EHCI_HCD=m
2488CONFIG_USB_EHCI_SPLIT_ISO=y
2489CONFIG_USB_EHCI_ROOT_HUB_TT=y
2490CONFIG_USB_EHCI_TT_NEWSCHED=y
2491# CONFIG_USB_ISP116X_HCD is not set
2492CONFIG_USB_OHCI_HCD=m
2493# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
2494# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
2495CONFIG_USB_OHCI_LITTLE_ENDIAN=y
2496CONFIG_USB_UHCI_HCD=m
2497CONFIG_USB_U132_HCD=m
2498CONFIG_USB_SL811_HCD=m
2499CONFIG_USB_SL811_CS=m
2500# CONFIG_USB_R8A66597_HCD is not set
2501
2502#
2503# USB Device Class drivers
2504#
2505CONFIG_USB_ACM=m
2506CONFIG_USB_PRINTER=m
2507
2508#
2509# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
2510#
2511
2512#
2513# may also be needed; see USB_STORAGE Help for more information
2514#
2515CONFIG_USB_STORAGE=m
2516# CONFIG_USB_STORAGE_DEBUG is not set
2517CONFIG_USB_STORAGE_DATAFAB=y
2518CONFIG_USB_STORAGE_FREECOM=y
2519CONFIG_USB_STORAGE_ISD200=y
2520CONFIG_USB_STORAGE_DPCM=y
2521CONFIG_USB_STORAGE_USBAT=y
2522CONFIG_USB_STORAGE_SDDR09=y
2523CONFIG_USB_STORAGE_SDDR55=y
2524CONFIG_USB_STORAGE_JUMPSHOT=y
2525CONFIG_USB_STORAGE_ALAUDA=y
2526CONFIG_USB_STORAGE_KARMA=y
2527CONFIG_USB_LIBUSUAL=y
2528
2529#
2530# USB Imaging devices
2531#
2532CONFIG_USB_MDC800=m
2533CONFIG_USB_MICROTEK=m
2534CONFIG_USB_MON=y
2535
2536#
2537# USB port drivers
2538#
2539CONFIG_USB_USS720=m
2540
2541#
2542# USB Serial Converter support
2543#
2544CONFIG_USB_SERIAL=m
2545CONFIG_USB_SERIAL_GENERIC=y
2546CONFIG_USB_SERIAL_AIRCABLE=m
2547CONFIG_USB_SERIAL_AIRPRIME=m
2548CONFIG_USB_SERIAL_ARK3116=m
2549CONFIG_USB_SERIAL_BELKIN=m
2550CONFIG_USB_SERIAL_WHITEHEAT=m
2551CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
2552CONFIG_USB_SERIAL_CP2101=m
2553CONFIG_USB_SERIAL_CYPRESS_M8=m
2554CONFIG_USB_SERIAL_EMPEG=m
2555CONFIG_USB_SERIAL_FTDI_SIO=m
2556CONFIG_USB_SERIAL_FUNSOFT=m
2557CONFIG_USB_SERIAL_VISOR=m
2558CONFIG_USB_SERIAL_IPAQ=m
2559CONFIG_USB_SERIAL_IR=m
2560CONFIG_USB_SERIAL_EDGEPORT=m
2561CONFIG_USB_SERIAL_EDGEPORT_TI=m
2562CONFIG_USB_SERIAL_GARMIN=m
2563CONFIG_USB_SERIAL_IPW=m
2564CONFIG_USB_SERIAL_KEYSPAN_PDA=m
2565CONFIG_USB_SERIAL_KEYSPAN=m
2566# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
2567# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
2568# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
2569# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
2570# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
2571# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
2572# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
2573# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
2574# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
2575# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
2576# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
2577# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
2578CONFIG_USB_SERIAL_KLSI=m
2579CONFIG_USB_SERIAL_KOBIL_SCT=m
2580CONFIG_USB_SERIAL_MCT_U232=m
2581CONFIG_USB_SERIAL_MOS7720=m
2582CONFIG_USB_SERIAL_MOS7840=m
2583CONFIG_USB_SERIAL_NAVMAN=m
2584CONFIG_USB_SERIAL_PL2303=m
2585# CONFIG_USB_SERIAL_OTI6858 is not set
2586CONFIG_USB_SERIAL_HP4X=m
2587CONFIG_USB_SERIAL_SAFE=m
2588# CONFIG_USB_SERIAL_SAFE_PADDED is not set
2589CONFIG_USB_SERIAL_SIERRAWIRELESS=m
2590CONFIG_USB_SERIAL_TI=m
2591CONFIG_USB_SERIAL_CYBERJACK=m
2592CONFIG_USB_SERIAL_XIRCOM=m
2593CONFIG_USB_SERIAL_OPTION=m
2594CONFIG_USB_SERIAL_OMNINET=m
2595# CONFIG_USB_SERIAL_DEBUG is not set
2596CONFIG_USB_EZUSB=y
2597
2598#
2599# USB Miscellaneous drivers
2600#
2601CONFIG_USB_EMI62=m
2602CONFIG_USB_EMI26=m
2603CONFIG_USB_ADUTUX=m
2604CONFIG_USB_AUERSWALD=m
2605CONFIG_USB_RIO500=m
2606CONFIG_USB_LEGOTOWER=m
2607CONFIG_USB_LCD=m
2608# CONFIG_USB_BERRY_CHARGE is not set
2609CONFIG_USB_LED=m
2610CONFIG_USB_CYPRESS_CY7C63=m
2611CONFIG_USB_CYTHERM=m
2612CONFIG_USB_PHIDGET=m
2613CONFIG_USB_PHIDGETKIT=m
2614CONFIG_USB_PHIDGETMOTORCONTROL=m
2615CONFIG_USB_PHIDGETSERVO=m
2616CONFIG_USB_IDMOUSE=m
2617CONFIG_USB_FTDI_ELAN=m
2618CONFIG_USB_APPLEDISPLAY=m
2619CONFIG_USB_SISUSBVGA=m
2620# CONFIG_USB_SISUSBVGA_CON is not set
2621CONFIG_USB_LD=m
2622CONFIG_USB_TRANCEVIBRATOR=m
2623# CONFIG_USB_IOWARRIOR is not set
2624CONFIG_USB_TEST=m
2625
2626#
2627# USB DSL modem support
2628#
2629CONFIG_USB_ATM=m
2630CONFIG_USB_SPEEDTOUCH=m
2631CONFIG_USB_CXACRU=m
2632CONFIG_USB_UEAGLEATM=m
2633CONFIG_USB_XUSBATM=m
2634
2635#
2636# USB Gadget Support
2637#
2638CONFIG_USB_GADGET=m
2639# CONFIG_USB_GADGET_DEBUG_FILES is not set
2640CONFIG_USB_GADGET_SELECTED=y
2641# CONFIG_USB_GADGET_AMD5536UDC is not set
2642# CONFIG_USB_GADGET_FSL_USB2 is not set
2643CONFIG_USB_GADGET_NET2280=y
2644CONFIG_USB_NET2280=m
2645# CONFIG_USB_GADGET_PXA2XX is not set
2646# CONFIG_USB_GADGET_M66592 is not set
2647# CONFIG_USB_GADGET_GOKU is not set
2648# CONFIG_USB_GADGET_LH7A40X is not set
2649# CONFIG_USB_GADGET_OMAP is not set
2650# CONFIG_USB_GADGET_S3C2410 is not set
2651# CONFIG_USB_GADGET_AT91 is not set
2652# CONFIG_USB_GADGET_DUMMY_HCD is not set
2653CONFIG_USB_GADGET_DUALSPEED=y
2654CONFIG_USB_ZERO=m
2655CONFIG_USB_ETH=m
2656CONFIG_USB_ETH_RNDIS=y
2657CONFIG_USB_GADGETFS=m
2658CONFIG_USB_FILE_STORAGE=m
2659# CONFIG_USB_FILE_STORAGE_TEST is not set
2660CONFIG_USB_G_SERIAL=m
2661CONFIG_USB_MIDI_GADGET=m
2662CONFIG_MMC=m
2663# CONFIG_MMC_DEBUG is not set
2664# CONFIG_MMC_UNSAFE_RESUME is not set
2665
2666#
2667# MMC/SD Card Drivers
2668#
2669CONFIG_MMC_BLOCK=m
2670CONFIG_MMC_BLOCK_BOUNCE=y
2671
2672#
2673# MMC/SD Host Controller Drivers
2674#
2675CONFIG_MMC_SDHCI=m
2676CONFIG_MMC_TIFM_SD=m
2677CONFIG_NEW_LEDS=y
2678CONFIG_LEDS_CLASS=m
2679
2680#
2681# LED drivers
2682#
2683
2684#
2685# LED Triggers
2686#
2687# CONFIG_LEDS_TRIGGERS is not set
2688CONFIG_INFINIBAND=m
2689CONFIG_INFINIBAND_USER_MAD=m
2690CONFIG_INFINIBAND_USER_ACCESS=m
2691CONFIG_INFINIBAND_USER_MEM=y
2692CONFIG_INFINIBAND_ADDR_TRANS=y
2693CONFIG_INFINIBAND_MTHCA=m
2694CONFIG_INFINIBAND_MTHCA_DEBUG=y
2695CONFIG_INFINIBAND_AMSO1100=m
2696CONFIG_INFINIBAND_AMSO1100_DEBUG=y
2697# CONFIG_MLX4_INFINIBAND is not set
2698CONFIG_INFINIBAND_IPOIB=m
2699# CONFIG_INFINIBAND_IPOIB_CM is not set
2700CONFIG_INFINIBAND_IPOIB_DEBUG=y
2701# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
2702CONFIG_INFINIBAND_SRP=m
2703CONFIG_INFINIBAND_ISER=m
2704CONFIG_RTC_LIB=m
2705CONFIG_RTC_CLASS=m
2706
2707#
2708# RTC interfaces
2709#
2710CONFIG_RTC_INTF_SYSFS=y
2711CONFIG_RTC_INTF_PROC=y
2712CONFIG_RTC_INTF_DEV=y
2713CONFIG_RTC_INTF_DEV_UIE_EMUL=y
2714CONFIG_RTC_DRV_TEST=m
2715
2716#
2717# I2C RTC drivers
2718#
2719CONFIG_RTC_DRV_DS1307=m
2720CONFIG_RTC_DRV_DS1672=m
2721# CONFIG_RTC_DRV_MAX6900 is not set
2722CONFIG_RTC_DRV_RS5C372=m
2723CONFIG_RTC_DRV_ISL1208=m
2724CONFIG_RTC_DRV_X1205=m
2725CONFIG_RTC_DRV_PCF8563=m
2726CONFIG_RTC_DRV_PCF8583=m
2727# CONFIG_RTC_DRV_M41T80 is not set
2728
2729#
2730# SPI RTC drivers
2731#
2732CONFIG_RTC_DRV_RS5C348=m
2733CONFIG_RTC_DRV_MAX6902=m
2734
2735#
2736# Platform RTC drivers
2737#
2738# CONFIG_RTC_DRV_CMOS is not set
2739CONFIG_RTC_DRV_DS1553=m
2740# CONFIG_RTC_DRV_STK17TA8 is not set
2741CONFIG_RTC_DRV_DS1742=m
2742CONFIG_RTC_DRV_M48T86=m
2743# CONFIG_RTC_DRV_M48T59 is not set
2744CONFIG_RTC_DRV_V3020=m
2745
2746#
2747# on-CPU RTC drivers
2748#
2749
2750#
2751# DMA Engine support
2752#
2753CONFIG_DMA_ENGINE=y
2754
2755#
2756# DMA Clients
2757#
2758CONFIG_NET_DMA=y
2759
2760#
2761# DMA Devices
2762#
2763CONFIG_INTEL_IOATDMA=m
2764# CONFIG_AUXDISPLAY is not set
2765
2766#
2767# Userspace I/O
2768#
2769# CONFIG_UIO is not set
2770
2771#
2772# File systems
2773#
2774CONFIG_EXT2_FS=m
2775CONFIG_EXT2_FS_XATTR=y
2776CONFIG_EXT2_FS_POSIX_ACL=y
2777CONFIG_EXT2_FS_SECURITY=y
2778# CONFIG_EXT2_FS_XIP is not set
2779CONFIG_EXT3_FS=m
2780CONFIG_EXT3_FS_XATTR=y
2781CONFIG_EXT3_FS_POSIX_ACL=y
2782CONFIG_EXT3_FS_SECURITY=y
2783# CONFIG_EXT4DEV_FS is not set
2784CONFIG_JBD=m
2785# CONFIG_JBD_DEBUG is not set
2786CONFIG_FS_MBCACHE=m
2787CONFIG_REISERFS_FS=m
2788# CONFIG_REISERFS_CHECK is not set
2789# CONFIG_REISERFS_PROC_INFO is not set
2790CONFIG_REISERFS_FS_XATTR=y
2791CONFIG_REISERFS_FS_POSIX_ACL=y
2792CONFIG_REISERFS_FS_SECURITY=y
2793CONFIG_JFS_FS=m
2794CONFIG_JFS_POSIX_ACL=y
2795CONFIG_JFS_SECURITY=y
2796# CONFIG_JFS_DEBUG is not set
2797CONFIG_JFS_STATISTICS=y
2798CONFIG_FS_POSIX_ACL=y
2799CONFIG_XFS_FS=m
2800CONFIG_XFS_QUOTA=y
2801CONFIG_XFS_SECURITY=y
2802CONFIG_XFS_POSIX_ACL=y
2803CONFIG_XFS_RT=y
2804# CONFIG_GFS2_FS is not set
2805# CONFIG_OCFS2_FS is not set
2806CONFIG_MINIX_FS=m
2807CONFIG_ROMFS_FS=m
2808CONFIG_INOTIFY=y
2809CONFIG_INOTIFY_USER=y
2810CONFIG_QUOTA=y
2811CONFIG_QFMT_V1=m
2812CONFIG_QFMT_V2=m
2813CONFIG_QUOTACTL=y
2814CONFIG_DNOTIFY=y
2815CONFIG_AUTOFS_FS=m
2816CONFIG_AUTOFS4_FS=m
2817CONFIG_FUSE_FS=m
2818
2819#
2820# CD-ROM/DVD Filesystems
2821#
2822CONFIG_ISO9660_FS=m
2823CONFIG_JOLIET=y
2824CONFIG_ZISOFS=y
2825CONFIG_UDF_FS=m
2826CONFIG_UDF_NLS=y
2827
2828#
2829# DOS/FAT/NT Filesystems
2830#
2831CONFIG_FAT_FS=m
2832CONFIG_MSDOS_FS=m
2833CONFIG_VFAT_FS=m
2834CONFIG_FAT_DEFAULT_CODEPAGE=437
2835CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
2836CONFIG_NTFS_FS=m
2837# CONFIG_NTFS_DEBUG is not set
2838# CONFIG_NTFS_RW is not set
2839
2840#
2841# Pseudo filesystems
2842#
2843CONFIG_PROC_FS=y
2844CONFIG_PROC_KCORE=y
2845CONFIG_PROC_SYSCTL=y
2846CONFIG_SYSFS=y
2847CONFIG_TMPFS=y
2848# CONFIG_TMPFS_POSIX_ACL is not set
2849# CONFIG_HUGETLB_PAGE is not set
2850CONFIG_RAMFS=y
2851CONFIG_CONFIGFS_FS=m
2852
2853#
2854# Miscellaneous filesystems
2855#
2856CONFIG_ADFS_FS=m
2857# CONFIG_ADFS_FS_RW is not set
2858CONFIG_AFFS_FS=m
2859CONFIG_ECRYPT_FS=m
2860CONFIG_HFS_FS=m
2861CONFIG_HFSPLUS_FS=m
2862CONFIG_BEFS_FS=m
2863# CONFIG_BEFS_DEBUG is not set
2864CONFIG_BFS_FS=m
2865CONFIG_EFS_FS=m
2866CONFIG_JFFS2_FS=m
2867CONFIG_JFFS2_FS_DEBUG=0
2868CONFIG_JFFS2_FS_WRITEBUFFER=y
2869# CONFIG_JFFS2_SUMMARY is not set
2870# CONFIG_JFFS2_FS_XATTR is not set
2871# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
2872CONFIG_JFFS2_ZLIB=y
2873CONFIG_JFFS2_RTIME=y
2874# CONFIG_JFFS2_RUBIN is not set
2875CONFIG_CRAMFS=y
2876CONFIG_VXFS_FS=m
2877CONFIG_HPFS_FS=m
2878CONFIG_QNX4FS_FS=m
2879CONFIG_SYSV_FS=m
2880CONFIG_UFS_FS=m
2881# CONFIG_UFS_FS_WRITE is not set
2882# CONFIG_UFS_DEBUG is not set
2883
2884#
2885# Network File Systems
2886#
2887CONFIG_NFS_FS=m
2888CONFIG_NFS_V3=y
2889# CONFIG_NFS_V3_ACL is not set
2890CONFIG_NFS_V4=y
2891CONFIG_NFS_DIRECTIO=y
2892CONFIG_NFSD=m
2893CONFIG_NFSD_V3=y
2894# CONFIG_NFSD_V3_ACL is not set
2895CONFIG_NFSD_V4=y
2896CONFIG_NFSD_TCP=y
2897CONFIG_LOCKD=m
2898CONFIG_LOCKD_V4=y
2899CONFIG_EXPORTFS=m
2900CONFIG_NFS_COMMON=y
2901CONFIG_SUNRPC=m
2902CONFIG_SUNRPC_GSS=m
2903# CONFIG_SUNRPC_BIND34 is not set
2904CONFIG_RPCSEC_GSS_KRB5=m
2905CONFIG_RPCSEC_GSS_SPKM3=m
2906CONFIG_SMB_FS=m
2907# CONFIG_SMB_NLS_DEFAULT is not set
2908CONFIG_CIFS=m
2909# CONFIG_CIFS_STATS is not set
2910# CONFIG_CIFS_WEAK_PW_HASH is not set
2911# CONFIG_CIFS_XATTR is not set
2912# CONFIG_CIFS_DEBUG2 is not set
2913# CONFIG_CIFS_EXPERIMENTAL is not set
2914CONFIG_NCP_FS=m
2915CONFIG_NCPFS_PACKET_SIGNING=y
2916CONFIG_NCPFS_IOCTL_LOCKING=y
2917CONFIG_NCPFS_STRONG=y
2918CONFIG_NCPFS_NFS_NS=y
2919CONFIG_NCPFS_OS2_NS=y
2920# CONFIG_NCPFS_SMALLDOS is not set
2921CONFIG_NCPFS_NLS=y
2922CONFIG_NCPFS_EXTRAS=y
2923CONFIG_CODA_FS=m
2924# CONFIG_CODA_FS_OLD_API is not set
2925CONFIG_AFS_FS=m
2926# CONFIG_AFS_DEBUG is not set
2927
2928#
2929# Partition Types
2930#
2931CONFIG_PARTITION_ADVANCED=y
2932CONFIG_ACORN_PARTITION=y
2933# CONFIG_ACORN_PARTITION_CUMANA is not set
2934# CONFIG_ACORN_PARTITION_EESOX is not set
2935CONFIG_ACORN_PARTITION_ICS=y
2936# CONFIG_ACORN_PARTITION_ADFS is not set
2937# CONFIG_ACORN_PARTITION_POWERTEC is not set
2938CONFIG_ACORN_PARTITION_RISCIX=y
2939CONFIG_OSF_PARTITION=y
2940CONFIG_AMIGA_PARTITION=y
2941CONFIG_ATARI_PARTITION=y
2942CONFIG_MAC_PARTITION=y
2943CONFIG_MSDOS_PARTITION=y
2944CONFIG_BSD_DISKLABEL=y
2945CONFIG_MINIX_SUBPARTITION=y
2946CONFIG_SOLARIS_X86_PARTITION=y
2947CONFIG_UNIXWARE_DISKLABEL=y
2948CONFIG_LDM_PARTITION=y
2949# CONFIG_LDM_DEBUG is not set
2950CONFIG_SGI_PARTITION=y
2951CONFIG_ULTRIX_PARTITION=y
2952CONFIG_SUN_PARTITION=y
2953CONFIG_KARMA_PARTITION=y
2954CONFIG_EFI_PARTITION=y
2955# CONFIG_SYSV68_PARTITION is not set
2956
2957#
2958# Native Language Support
2959#
2960CONFIG_NLS=y
2961CONFIG_NLS_DEFAULT="cp437"
2962CONFIG_NLS_CODEPAGE_437=m
2963CONFIG_NLS_CODEPAGE_737=m
2964CONFIG_NLS_CODEPAGE_775=m
2965CONFIG_NLS_CODEPAGE_850=m
2966CONFIG_NLS_CODEPAGE_852=m
2967CONFIG_NLS_CODEPAGE_855=m
2968CONFIG_NLS_CODEPAGE_857=m
2969CONFIG_NLS_CODEPAGE_860=m
2970CONFIG_NLS_CODEPAGE_861=m
2971CONFIG_NLS_CODEPAGE_862=m
2972CONFIG_NLS_CODEPAGE_863=m
2973CONFIG_NLS_CODEPAGE_864=m
2974CONFIG_NLS_CODEPAGE_865=m
2975CONFIG_NLS_CODEPAGE_866=m
2976CONFIG_NLS_CODEPAGE_869=m
2977CONFIG_NLS_CODEPAGE_936=m
2978CONFIG_NLS_CODEPAGE_950=m
2979CONFIG_NLS_CODEPAGE_932=m
2980CONFIG_NLS_CODEPAGE_949=m
2981CONFIG_NLS_CODEPAGE_874=m
2982CONFIG_NLS_ISO8859_8=m
2983CONFIG_NLS_CODEPAGE_1250=m
2984CONFIG_NLS_CODEPAGE_1251=m
2985CONFIG_NLS_ASCII=m
2986CONFIG_NLS_ISO8859_1=m
2987CONFIG_NLS_ISO8859_2=m
2988CONFIG_NLS_ISO8859_3=m
2989CONFIG_NLS_ISO8859_4=m
2990CONFIG_NLS_ISO8859_5=m
2991CONFIG_NLS_ISO8859_6=m
2992CONFIG_NLS_ISO8859_7=m
2993CONFIG_NLS_ISO8859_9=m
2994CONFIG_NLS_ISO8859_13=m
2995CONFIG_NLS_ISO8859_14=m
2996CONFIG_NLS_ISO8859_15=m
2997CONFIG_NLS_KOI8_R=m
2998CONFIG_NLS_KOI8_U=m
2999CONFIG_NLS_UTF8=m
3000
3001#
3002# Distributed Lock Manager
3003#
3004CONFIG_DLM=m
3005# CONFIG_DLM_DEBUG is not set
3006
3007#
3008# Profiling support
3009#
3010CONFIG_PROFILING=y
3011CONFIG_OPROFILE=m
3012
3013#
3014# Kernel hacking
3015#
3016CONFIG_TRACE_IRQFLAGS_SUPPORT=y
3017# CONFIG_PRINTK_TIME is not set
3018# CONFIG_ENABLE_MUST_CHECK is not set
3019CONFIG_MAGIC_SYSRQ=y
3020# CONFIG_UNUSED_SYMBOLS is not set
3021# CONFIG_DEBUG_FS is not set
3022# CONFIG_HEADERS_CHECK is not set
3023# CONFIG_DEBUG_KERNEL is not set
3024# CONFIG_CROSSCOMPILE is not set
3025CONFIG_CMDLINE=""
3026CONFIG_SYS_SUPPORTS_KGDB=y
3027
3028#
3029# Security options
3030#
3031CONFIG_KEYS=y
3032# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
3033CONFIG_SECURITY=y
3034CONFIG_SECURITY_NETWORK=y
3035# CONFIG_SECURITY_NETWORK_XFRM is not set
3036CONFIG_SECURITY_CAPABILITIES=m
3037CONFIG_SECURITY_ROOTPLUG=m
3038CONFIG_SECURITY_SELINUX=y
3039CONFIG_SECURITY_SELINUX_BOOTPARAM=y
3040CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
3041CONFIG_SECURITY_SELINUX_DISABLE=y
3042CONFIG_SECURITY_SELINUX_DEVELOP=y
3043CONFIG_SECURITY_SELINUX_AVC_STATS=y
3044CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
3045# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set
3046# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
3047CONFIG_XOR_BLOCKS=m
3048CONFIG_ASYNC_CORE=m
3049CONFIG_ASYNC_MEMCPY=m
3050CONFIG_ASYNC_XOR=m
3051CONFIG_CRYPTO=y
3052CONFIG_CRYPTO_ALGAPI=y
3053CONFIG_CRYPTO_BLKCIPHER=m
3054CONFIG_CRYPTO_HASH=y
3055CONFIG_CRYPTO_MANAGER=y
3056CONFIG_CRYPTO_HMAC=y
3057# CONFIG_CRYPTO_XCBC is not set
3058CONFIG_CRYPTO_NULL=m
3059CONFIG_CRYPTO_MD4=m
3060CONFIG_CRYPTO_MD5=y
3061CONFIG_CRYPTO_SHA1=m
3062CONFIG_CRYPTO_SHA256=m
3063CONFIG_CRYPTO_SHA512=m
3064CONFIG_CRYPTO_WP512=m
3065CONFIG_CRYPTO_TGR192=m
3066# CONFIG_CRYPTO_GF128MUL is not set
3067CONFIG_CRYPTO_ECB=m
3068CONFIG_CRYPTO_CBC=m
3069CONFIG_CRYPTO_PCBC=m
3070# CONFIG_CRYPTO_LRW is not set
3071# CONFIG_CRYPTO_CRYPTD is not set
3072CONFIG_CRYPTO_DES=m
3073# CONFIG_CRYPTO_FCRYPT is not set
3074CONFIG_CRYPTO_BLOWFISH=m
3075CONFIG_CRYPTO_TWOFISH=m
3076CONFIG_CRYPTO_TWOFISH_COMMON=m
3077CONFIG_CRYPTO_SERPENT=m
3078CONFIG_CRYPTO_AES=m
3079CONFIG_CRYPTO_CAST5=m
3080CONFIG_CRYPTO_CAST6=m
3081CONFIG_CRYPTO_TEA=m
3082CONFIG_CRYPTO_ARC4=m
3083CONFIG_CRYPTO_KHAZAD=m
3084CONFIG_CRYPTO_ANUBIS=m
3085CONFIG_CRYPTO_DEFLATE=m
3086CONFIG_CRYPTO_MICHAEL_MIC=m
3087CONFIG_CRYPTO_CRC32C=m
3088# CONFIG_CRYPTO_CAMELLIA is not set
3089CONFIG_CRYPTO_TEST=m
3090CONFIG_CRYPTO_HW=y
3091
3092#
3093# Library routines
3094#
3095CONFIG_BITREVERSE=y
3096CONFIG_CRC_CCITT=m
3097CONFIG_CRC16=m
3098# CONFIG_CRC_ITU_T is not set
3099CONFIG_CRC32=y
3100# CONFIG_CRC7 is not set
3101CONFIG_LIBCRC32C=m
3102CONFIG_AUDIT_GENERIC=y
3103CONFIG_ZLIB_INFLATE=y
3104CONFIG_ZLIB_DEFLATE=m
3105CONFIG_REED_SOLOMON=m
3106CONFIG_REED_SOLOMON_DEC16=y
3107CONFIG_TEXTSEARCH=y
3108CONFIG_TEXTSEARCH_KMP=m
3109CONFIG_TEXTSEARCH_BM=m
3110CONFIG_TEXTSEARCH_FSM=m
3111CONFIG_PLIST=y
3112CONFIG_HAS_IOMEM=y
3113CONFIG_HAS_IOPORT=y
3114CONFIG_HAS_DMA=y
3115CONFIG_CHECK_SIGNATURE=y
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 93f9e8331ad7..3d1b6281d887 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -70,7 +70,6 @@ CONFIG_SIBYTE_HAS_LDT=y
70CONFIG_SIBYTE_CFE=y 70CONFIG_SIBYTE_CFE=y
71# CONFIG_SIBYTE_CFE_CONSOLE is not set 71# CONFIG_SIBYTE_CFE_CONSOLE is not set
72# CONFIG_SIBYTE_BUS_WATCHER is not set 72# CONFIG_SIBYTE_BUS_WATCHER is not set
73# CONFIG_SIBYTE_SB1250_PROF is not set
74# CONFIG_SIBYTE_TBPROF is not set 73# CONFIG_SIBYTE_TBPROF is not set
75CONFIG_RWSEM_GENERIC_SPINLOCK=y 74CONFIG_RWSEM_GENERIC_SPINLOCK=y
76# CONFIG_ARCH_HAS_ILOG2_U32 is not set 75# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 6d55e8aab668..6a17c9b508ea 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void)
263 */ 263 */
264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | 264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
265 KN03_MCR_CORRECT; 265 KN03_MCR_CORRECT;
266 if (current_cpu_data.cputype == CPU_R4400SC) 266 if (current_cpu_type() == CPU_R4400SC)
267 *mbcs |= KN4K_MB_CSR_EE; 267 *mbcs |= KN4K_MB_CSR_EE;
268 fast_iob(); 268 fast_iob();
269} 269}
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index 7a053aadcd3a..5f04545c3606 100644
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void)
132 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); 132 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
133 133
134 /* For KN04 we need to make sure EE (?) is enabled in the MB. */ 134 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
135 if (current_cpu_data.cputype == CPU_R4000SC) 135 if (current_cpu_type() == CPU_R4000SC)
136 *mbcs |= KN4K_MB_CSR_EE; 136 *mbcs |= KN4K_MB_CSR_EE;
137 fast_iob(); 137 fast_iob();
138 138
diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c
index cd85924e2572..95e26f4bb38f 100644
--- a/arch/mips/dec/prom/identify.c
+++ b/arch/mips/dec/prom/identify.c
@@ -133,9 +133,6 @@ void __init prom_identify_arch(u32 magic)
133 dec_firmrev = (dec_sysid & 0xff00) >> 8; 133 dec_firmrev = (dec_sysid & 0xff00) >> 8;
134 dec_etc = dec_sysid & 0xff; 134 dec_etc = dec_sysid & 0xff;
135 135
136 /* We're obviously one of the DEC machines */
137 mips_machgroup = MACH_GROUP_DEC;
138
139 /* 136 /*
140 * FIXME: This may not be an exhaustive list of DECStations/Servers! 137 * FIXME: This may not be an exhaustive list of DECStations/Servers!
141 * Put all model-specific initialisation calls here. 138 * Put all model-specific initialisation calls here.
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 808c182fd3fa..93f1239af524 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -108,8 +108,8 @@ void __init prom_init(void)
108 108
109 /* Were we compiled with the right CPU option? */ 109 /* Were we compiled with the right CPU option? */
110#if defined(CONFIG_CPU_R3000) 110#if defined(CONFIG_CPU_R3000)
111 if ((current_cpu_data.cputype == CPU_R4000SC) || 111 if ((current_cpu_type() == CPU_R4000SC) ||
112 (current_cpu_data.cputype == CPU_R4400SC)) { 112 (current_cpu_type() == CPU_R4400SC)) {
113 static char r4k_msg[] __initdata = 113 static char r4k_msg[] __initdata =
114 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; 114 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
115 printk(cpu_msg); 115 printk(cpu_msg);
@@ -119,8 +119,8 @@ void __init prom_init(void)
119#endif 119#endif
120 120
121#if defined(CONFIG_CPU_R4X00) 121#if defined(CONFIG_CPU_R4X00)
122 if ((current_cpu_data.cputype == CPU_R3000) || 122 if ((current_cpu_type() == CPU_R3000) ||
123 (current_cpu_data.cputype == CPU_R3000A)) { 123 (current_cpu_type() == CPU_R3000A)) {
124 static char r3k_msg[] __initdata = 124 static char r3k_msg[] __initdata =
125 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; 125 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
126 printk(cpu_msg); 126 printk(cpu_msg);
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 3e634f2f5443..bd5431e1f408 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -145,13 +145,9 @@ static void __init dec_be_init(void)
145 } 145 }
146} 146}
147 147
148
149extern void dec_time_init(void);
150
151void __init plat_mem_setup(void) 148void __init plat_mem_setup(void)
152{ 149{
153 board_be_init = dec_be_init; 150 board_be_init = dec_be_init;
154 board_time_init = dec_time_init;
155 151
156 wbflush_setup(); 152 wbflush_setup();
157 153
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 8b7e0c17ac35..820e5331205f 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -24,7 +24,6 @@
24 24
25#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
26#include <asm/cpu.h> 26#include <asm/cpu.h>
27#include <asm/div64.h>
28#include <asm/io.h> 27#include <asm/io.h>
29#include <asm/irq.h> 28#include <asm/irq.h>
30#include <asm/mipsregs.h> 29#include <asm/mipsregs.h>
@@ -36,7 +35,7 @@
36#include <asm/dec/ioasic_addrs.h> 35#include <asm/dec/ioasic_addrs.h>
37#include <asm/dec/machtype.h> 36#include <asm/dec/machtype.h>
38 37
39static unsigned long dec_rtc_get_time(void) 38unsigned long read_persistent_clock(void)
40{ 39{
41 unsigned int year, mon, day, hour, min, sec, real_year; 40 unsigned int year, mon, day, hour, min, sec, real_year;
42 unsigned long flags; 41 unsigned long flags;
@@ -75,13 +74,13 @@ static unsigned long dec_rtc_get_time(void)
75} 74}
76 75
77/* 76/*
78 * In order to set the CMOS clock precisely, dec_rtc_set_mmss has to 77 * In order to set the CMOS clock precisely, rtc_mips_set_mmss has to
79 * be called 500 ms after the second nowtime has started, because when 78 * be called 500 ms after the second nowtime has started, because when
80 * nowtime is written into the registers of the CMOS clock, it will 79 * nowtime is written into the registers of the CMOS clock, it will
81 * jump to the next second precisely 500 ms later. Check the Dallas 80 * jump to the next second precisely 500 ms later. Check the Dallas
82 * DS1287 data sheet for details. 81 * DS1287 data sheet for details.
83 */ 82 */
84static int dec_rtc_set_mmss(unsigned long nowtime) 83int rtc_mips_set_mmss(unsigned long nowtime)
85{ 84{
86 int retval = 0; 85 int retval = 0;
87 int real_seconds, real_minutes, cmos_minutes; 86 int real_seconds, real_minutes, cmos_minutes;
@@ -140,7 +139,6 @@ static int dec_rtc_set_mmss(unsigned long nowtime)
140 return retval; 139 return retval;
141} 140}
142 141
143
144static int dec_timer_state(void) 142static int dec_timer_state(void)
145{ 143{
146 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; 144 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
@@ -161,11 +159,8 @@ static cycle_t dec_ioasic_hpt_read(void)
161} 159}
162 160
163 161
164void __init dec_time_init(void) 162void __init plat_time_init(void)
165{ 163{
166 rtc_mips_get_time = dec_rtc_get_time;
167 rtc_mips_set_mmss = dec_rtc_set_mmss;
168
169 mips_timer_state = dec_timer_state; 164 mips_timer_state = dec_timer_state;
170 mips_timer_ack = dec_timer_ack; 165 mips_timer_ack = dec_timer_ack;
171 166
diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c
index 7433bd8e5562..0f791eb6bb66 100644
--- a/arch/mips/emma2rh/common/prom.c
+++ b/arch/mips/emma2rh/common/prom.c
@@ -62,8 +62,6 @@ void __init prom_init(void)
62 strcat(arcs_cmdline, " "); 62 strcat(arcs_cmdline, " ");
63 } 63 }
64 64
65 mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
66
67#if defined(CONFIG_MARKEINS) 65#if defined(CONFIG_MARKEINS)
68 mips_machtype = MACH_NEC_MARKEINS; 66 mips_machtype = MACH_NEC_MARKEINS;
69 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); 67 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 2f060e1ed36c..5e1da53b04a7 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -88,7 +88,7 @@ static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
88 return clock[reg]; 88 return clock[reg];
89} 89}
90 90
91static void __init emma2rh_time_init(void) 91void __init plat_time_init(void)
92{ 92{
93 u32 reg; 93 u32 reg;
94 if (bus_frequency == 0) 94 if (bus_frequency == 0)
@@ -124,8 +124,6 @@ void __init plat_mem_setup(void)
124 124
125 set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); 125 set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
126 126
127 board_time_init = emma2rh_time_init;
128
129 _machine_restart = markeins_machine_restart; 127 _machine_restart = markeins_machine_restart;
130 _machine_halt = markeins_machine_halt; 128 _machine_halt = markeins_machine_halt;
131 pm_power_off = markeins_machine_power_off; 129 pm_power_off = markeins_machine_power_off;
diff --git a/arch/mips/arc/Makefile b/arch/mips/fw/arc/Makefile
index 4f349ec1ea2d..4f349ec1ea2d 100644
--- a/arch/mips/arc/Makefile
+++ b/arch/mips/fw/arc/Makefile
diff --git a/arch/mips/arc/arc_con.c b/arch/mips/fw/arc/arc_con.c
index bc32fe64f42a..bc32fe64f42a 100644
--- a/arch/mips/arc/arc_con.c
+++ b/arch/mips/fw/arc/arc_con.c
diff --git a/arch/mips/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index fd604ef28823..fd604ef28823 100644
--- a/arch/mips/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
diff --git a/arch/mips/arc/env.c b/arch/mips/fw/arc/env.c
index e521a6e010aa..6f5dd42b96e2 100644
--- a/arch/mips/arc/env.c
+++ b/arch/mips/fw/arc/env.c
@@ -11,7 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/string.h> 12#include <linux/string.h>
13 13
14#include <asm/arc/types.h> 14#include <asm/fw/arc/types.h>
15#include <asm/sgialib.h> 15#include <asm/sgialib.h>
16 16
17PCHAR __init 17PCHAR __init
diff --git a/arch/mips/arc/file.c b/arch/mips/fw/arc/file.c
index cb0127cf5bc1..30335341b447 100644
--- a/arch/mips/arc/file.c
+++ b/arch/mips/fw/arc/file.c
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12 12
13#include <asm/arc/types.h> 13#include <asm/fw/arc/types.h>
14#include <asm/sgialib.h> 14#include <asm/sgialib.h>
15 15
16LONG 16LONG
diff --git a/arch/mips/arc/identify.c b/arch/mips/fw/arc/identify.c
index 4b907369b0f9..28dfd2e2989a 100644
--- a/arch/mips/arc/identify.c
+++ b/arch/mips/fw/arc/identify.c
@@ -22,52 +22,51 @@
22struct smatch { 22struct smatch {
23 char *arcname; 23 char *arcname;
24 char *liname; 24 char *liname;
25 int group;
26 int type; 25 int type;
27 int flags; 26 int flags;
28}; 27};
29 28
30static struct smatch mach_table[] = { 29static struct smatch mach_table[] = {
31 { "SGI-IP22", 30 {
32 "SGI Indy", 31 .arcname = "SGI-IP22",
33 MACH_GROUP_SGI, 32 .liname = "SGI Indy",
34 MACH_SGI_IP22, 33 .type = MACH_SGI_IP22,
35 PROM_FLAG_ARCS 34 .flags = PROM_FLAG_ARCS,
36 }, { "SGI-IP27", 35 }, {
37 "SGI Origin", 36 .arcname = "SGI-IP27",
38 MACH_GROUP_SGI, 37 .liname = "SGI Origin",
39 MACH_SGI_IP27, 38 .type = MACH_SGI_IP27,
40 PROM_FLAG_ARCS 39 .flags = PROM_FLAG_ARCS,
41 }, { "SGI-IP28", 40 }, {
42 "SGI IP28", 41 .arcname = "SGI-IP28",
43 MACH_GROUP_SGI, 42 .liname = "SGI IP28",
44 MACH_SGI_IP28, 43 .type = MACH_SGI_IP28,
45 PROM_FLAG_ARCS 44 .flags = PROM_FLAG_ARCS,
46 }, { "SGI-IP30", 45 }, {
47 "SGI Octane", 46 .arcname = "SGI-IP30",
48 MACH_GROUP_SGI, 47 .liname = "SGI Octane",
49 MACH_SGI_IP30, 48 .type = MACH_SGI_IP30,
50 PROM_FLAG_ARCS 49 .flags = PROM_FLAG_ARCS,
51 }, { "SGI-IP32", 50 }, {
52 "SGI O2", 51 .arcname = "SGI-IP32",
53 MACH_GROUP_SGI, 52 .liname = "SGI O2",
54 MACH_SGI_IP32, 53 .type = MACH_SGI_IP32,
55 PROM_FLAG_ARCS 54 .flags = PROM_FLAG_ARCS,
56 }, { "Microsoft-Jazz", 55 }, {
57 "Jazz MIPS_Magnum_4000", 56 .arcname = "Microsoft-Jazz",
58 MACH_GROUP_JAZZ, 57 .liname = "Jazz MIPS_Magnum_4000",
59 MACH_MIPS_MAGNUM_4000, 58 .type = MACH_MIPS_MAGNUM_4000,
60 0 59 .flags = 0,
61 }, { "PICA-61", 60 }, {
62 "Jazz Acer_PICA_61", 61 .arcname = "PICA-61",
63 MACH_GROUP_JAZZ, 62 .liname = "Jazz Acer_PICA_61",
64 MACH_ACER_PICA_61, 63 .type = MACH_ACER_PICA_61,
65 0 64 .flags = 0,
66 }, { "RM200PCI", 65 }, {
67 "SNI RM200_PCI", 66 .arcname = "RM200PCI",
68 MACH_GROUP_SNI_RM, 67 .liname = "SNI RM200_PCI",
69 MACH_SNI_RM200_PCI, 68 .type = MACH_SNI_RM200_PCI,
70 PROM_FLAG_DONT_FREE_TEMP 69 .flags = PROM_FLAG_DONT_FREE_TEMP,
71 } 70 }
72}; 71};
73 72
@@ -117,7 +116,6 @@ void __init prom_identify_arch(void)
117 mach = string_to_mach(iname); 116 mach = string_to_mach(iname);
118 system_type = mach->liname; 117 system_type = mach->liname;
119 118
120 mips_machgroup = mach->group;
121 mips_machtype = mach->type; 119 mips_machtype = mach->type;
122 prom_flags = mach->flags; 120 prom_flags = mach->flags;
123} 121}
diff --git a/arch/mips/arc/init.c b/arch/mips/fw/arc/init.c
index e2f75b13312f..e2f75b13312f 100644
--- a/arch/mips/arc/init.c
+++ b/arch/mips/fw/arc/init.c
diff --git a/arch/mips/arc/memory.c b/arch/mips/fw/arc/memory.c
index 83d15791ef6a..8b8eea2b6cf6 100644
--- a/arch/mips/arc/memory.c
+++ b/arch/mips/fw/arc/memory.c
@@ -63,7 +63,7 @@ static char *arc_mtypes[8] = {
63 : arc_mtypes[a.arc] 63 : arc_mtypes[a.arc]
64#endif 64#endif
65 65
66static inline int memtype_classify_arcs (union linux_memtypes type) 66static inline int memtype_classify_arcs(union linux_memtypes type)
67{ 67{
68 switch (type.arcs) { 68 switch (type.arcs) {
69 case arcs_fcontig: 69 case arcs_fcontig:
@@ -83,7 +83,7 @@ static inline int memtype_classify_arcs (union linux_memtypes type)
83 while(1); /* Nuke warning. */ 83 while(1); /* Nuke warning. */
84} 84}
85 85
86static inline int memtype_classify_arc (union linux_memtypes type) 86static inline int memtype_classify_arc(union linux_memtypes type)
87{ 87{
88 switch (type.arc) { 88 switch (type.arc) {
89 case arc_free: 89 case arc_free:
@@ -103,7 +103,7 @@ static inline int memtype_classify_arc (union linux_memtypes type)
103 while(1); /* Nuke warning. */ 103 while(1); /* Nuke warning. */
104} 104}
105 105
106static int __init prom_memtype_classify (union linux_memtypes type) 106static int __init prom_memtype_classify(union linux_memtypes type)
107{ 107{
108 if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ 108 if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */
109 return memtype_classify_arcs(type); 109 return memtype_classify_arcs(type);
diff --git a/arch/mips/arc/misc.c b/arch/mips/fw/arc/misc.c
index b2e10b9e9452..e527c5fd5a32 100644
--- a/arch/mips/arc/misc.c
+++ b/arch/mips/fw/arc/misc.c
@@ -14,7 +14,7 @@
14 14
15#include <asm/bcache.h> 15#include <asm/bcache.h>
16 16
17#include <asm/arc/types.h> 17#include <asm/fw/arc/types.h>
18#include <asm/sgialib.h> 18#include <asm/sgialib.h>
19#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
20#include <asm/system.h> 20#include <asm/system.h>
diff --git a/arch/mips/arc/promlib.c b/arch/mips/fw/arc/promlib.c
index c508c00dbb64..c508c00dbb64 100644
--- a/arch/mips/arc/promlib.c
+++ b/arch/mips/fw/arc/promlib.c
diff --git a/arch/mips/arc/salone.c b/arch/mips/fw/arc/salone.c
index e6afb64723d0..e6afb64723d0 100644
--- a/arch/mips/arc/salone.c
+++ b/arch/mips/fw/arc/salone.c
diff --git a/arch/mips/arc/time.c b/arch/mips/fw/arc/time.c
index 299ff2c5c0b5..42138c837d48 100644
--- a/arch/mips/arc/time.c
+++ b/arch/mips/fw/arc/time.c
@@ -9,7 +9,7 @@
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11 11
12#include <asm/arc/types.h> 12#include <asm/fw/arc/types.h>
13#include <asm/sgialib.h> 13#include <asm/sgialib.h>
14 14
15struct linux_tinfo * __init 15struct linux_tinfo * __init
diff --git a/arch/mips/arc/tree.c b/arch/mips/fw/arc/tree.c
index abd1786ea09b..d68e5a59c1f6 100644
--- a/arch/mips/arc/tree.c
+++ b/arch/mips/fw/arc/tree.c
@@ -10,7 +10,7 @@
10 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/arc/types.h> 13#include <asm/fw/arc/types.h>
14#include <asm/sgialib.h> 14#include <asm/sgialib.h>
15 15
16#undef DEBUG_PROM_TREE 16#undef DEBUG_PROM_TREE
diff --git a/arch/mips/fw/cfe/Makefile b/arch/mips/fw/cfe/Makefile
new file mode 100644
index 000000000000..8f20044c0adf
--- /dev/null
+++ b/arch/mips/fw/cfe/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Broadcom Common Firmware Environment support
3#
4
5lib-y += cfe_api.o
diff --git a/arch/mips/sibyte/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
index c0213605e18a..a9f69e4e40ac 100644
--- a/arch/mips/sibyte/cfe/cfe_api.c
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -30,7 +30,7 @@
30 * 30 *
31 ********************************************************************* */ 31 ********************************************************************* */
32 32
33#include "cfe_api.h" 33#include <asm/fw/cfe/cfe_api.h>
34#include "cfe_api_int.h" 34#include "cfe_api_int.h"
35 35
36/* Cast from a native pointer to a cfe_xptr_t and back. */ 36/* Cast from a native pointer to a cfe_xptr_t and back. */
diff --git a/arch/mips/sibyte/cfe/cfe_api_int.h b/arch/mips/fw/cfe/cfe_api_int.h
index f7e5a64b55f3..f7e5a64b55f3 100644
--- a/arch/mips/sibyte/cfe/cfe_api_int.h
+++ b/arch/mips/fw/cfe/cfe_api_int.h
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile
index bef15c90ae15..b49d282bee8a 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/gt64120/wrppmc/Makefile
@@ -9,6 +9,6 @@
9# Makefile for the Wind River MIPS 4KC PPMC Eval Board 9# Makefile for the Wind River MIPS 4KC PPMC Eval Board
10# 10#
11 11
12obj-y += irq.o reset.o setup.o time.o pci.o 12obj-y += irq.o pci.o reset.o serial.o setup.o time.o
13 13
14EXTRA_CFLAGS += -Werror 14EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index 06177bf5b1d6..c6e706274db4 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -9,26 +9,13 @@
9 * Free Software Foundation; either version 2 of the License, or (at your 9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12#include <linux/errno.h> 12#include <linux/hardirq.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel_stat.h> 14#include <linux/irq.h>
15#include <linux/module.h> 15
16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/random.h>
24#include <linux/bitops.h>
25#include <asm/bootinfo.h>
26#include <asm/io.h>
27#include <asm/bitops.h>
28#include <asm/mipsregs.h>
29#include <asm/system.h>
30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h> 16#include <asm/gt64120.h>
17#include <asm/irq_cpu.h>
18#include <asm/mipsregs.h>
32 19
33asmlinkage void plat_irq_dispatch(void) 20asmlinkage void plat_irq_dispatch(void)
34{ 21{
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/gt64120/wrppmc/pci.c
index 0d5289bc1804..d06192faeb7c 100644
--- a/arch/mips/gt64120/wrppmc/pci.c
+++ b/arch/mips/gt64120/wrppmc/pci.c
@@ -8,9 +8,10 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/ioport.h>
11#include <linux/types.h> 12#include <linux/types.h>
12#include <linux/pci.h> 13#include <linux/pci.h>
13#include <linux/kernel.h> 14
14#include <asm/gt64120.h> 15#include <asm/gt64120.h>
15 16
16extern struct pci_ops gt64xxx_pci0_ops; 17extern struct pci_ops gt64xxx_pci0_ops;
diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/gt64120/wrppmc/reset.c
index b97039c6d3db..c355cff38f6c 100644
--- a/arch/mips/gt64120/wrppmc/reset.c
+++ b/arch/mips/gt64120/wrppmc/reset.c
@@ -5,14 +5,10 @@
5 * 5 *
6 * Copyright (C) 1997 Ralf Baechle 6 * Copyright (C) 1997 Ralf Baechle
7 */ 7 */
8#include <linux/sched.h> 8#include <linux/kernel.h>
9#include <linux/mm.h> 9
10#include <asm/io.h>
11#include <asm/pgtable.h>
12#include <asm/processor.h>
13#include <asm/reboot.h>
14#include <asm/system.h>
15#include <asm/cacheflush.h> 10#include <asm/cacheflush.h>
11#include <asm/mipsregs.h>
16 12
17void wrppmc_machine_restart(char *command) 13void wrppmc_machine_restart(char *command)
18{ 14{
diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/gt64120/wrppmc/serial.c
new file mode 100644
index 000000000000..5ec1c2ffd3a5
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/serial.c
@@ -0,0 +1,80 @@
1/*
2 * Registration of WRPPMC UART platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <asm/gt64120.h>
27
28static struct resource wrppmc_uart_resource[] __initdata = {
29 {
30 .start = WRPPMC_UART16550_BASE,
31 .end = WRPPMC_UART16550_BASE + 7,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .start = WRPPMC_UART16550_IRQ,
36 .end = WRPPMC_UART16550_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct plat_serial8250_port wrppmc_serial8250_port[] = {
42 {
43 .irq = WRPPMC_UART16550_IRQ,
44 .uartclk = WRPPMC_UART16550_CLOCK,
45 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_SKIP_TEST,
47 .mapbase = WRPPMC_UART16550_BASE,
48 },
49 {},
50};
51
52static __init int wrppmc_uart_add(void)
53{
54 struct platform_device *pdev;
55 int retval;
56
57 pdev = platform_device_alloc("serial8250", -1);
58 if (!pdev)
59 return -ENOMEM;
60
61 pdev->id = PLAT8250_DEV_PLATFORM;
62 pdev->dev.platform_data = wrppmc_serial8250_port;
63
64 retval = platform_device_add_resources(pdev, wrppmc_uart_resource,
65 ARRAY_SIZE(wrppmc_uart_resource));
66 if (retval)
67 goto err_free_device;
68
69 retval = platform_device_add(pdev);
70 if (retval)
71 goto err_free_device;
72
73 return 0;
74
75err_free_device:
76 platform_device_put(pdev);
77
78 return retval;
79}
80device_initcall(wrppmc_uart_add);
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index ed58c13b6032..51f6b7862460 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -11,10 +11,6 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/string.h> 12#include <linux/string.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/tty.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/pm.h> 14#include <linux/pm.h>
19 15
20#include <asm/io.h> 16#include <asm/io.h>
@@ -98,35 +94,8 @@ void __init prom_free_prom_memory(void)
98{ 94{
99} 95}
100 96
101#ifdef CONFIG_SERIAL_8250
102static void wrppmc_setup_serial(void)
103{
104 struct uart_port up;
105
106 memset(&up, 0x00, sizeof(struct uart_port));
107
108 /*
109 * A note about mapbase/membase
110 * -) mapbase is the physical address of the IO port.
111 * -) membase is an 'ioremapped' cookie.
112 */
113 up.line = 0;
114 up.type = PORT_16550;
115 up.iotype = UPIO_MEM;
116 up.mapbase = WRPPMC_UART16550_BASE;
117 up.membase = ioremap(up.mapbase, 8);
118 up.irq = WRPPMC_UART16550_IRQ;
119 up.uartclk = WRPPMC_UART16550_CLOCK;
120 up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
121 up.regshift = 0;
122
123 early_serial_setup(&up);
124}
125#endif
126
127void __init plat_mem_setup(void) 97void __init plat_mem_setup(void)
128{ 98{
129 extern void wrppmc_time_init(void);
130 extern void wrppmc_machine_restart(char *command); 99 extern void wrppmc_machine_restart(char *command);
131 extern void wrppmc_machine_halt(void); 100 extern void wrppmc_machine_halt(void);
132 extern void wrppmc_machine_power_off(void); 101 extern void wrppmc_machine_power_off(void);
@@ -135,17 +104,10 @@ void __init plat_mem_setup(void)
135 _machine_halt = wrppmc_machine_halt; 104 _machine_halt = wrppmc_machine_halt;
136 pm_power_off = wrppmc_machine_power_off; 105 pm_power_off = wrppmc_machine_power_off;
137 106
138 /* Use MIPS Count/Compare Timer */
139 board_time_init = wrppmc_time_init;
140
141 /* This makes the operations of 'in/out[bwl]' to the 107 /* This makes the operations of 'in/out[bwl]' to the
142 * physical address ( < KSEG0) can work via KSEG1 108 * physical address ( < KSEG0) can work via KSEG1
143 */ 109 */
144 set_io_port_base(KSEG1); 110 set_io_port_base(KSEG1);
145
146#ifdef CONFIG_SERIAL_8250
147 wrppmc_setup_serial();
148#endif
149} 111}
150 112
151const char *get_system_type(void) 113const char *get_system_type(void)
@@ -159,7 +121,6 @@ const char *get_system_type(void)
159 */ 121 */
160void __init prom_init(void) 122void __init prom_init(void)
161{ 123{
162 mips_machgroup = MACH_GROUP_WINDRIVER;
163 mips_machtype = MACH_WRPPMC; 124 mips_machtype = MACH_WRPPMC;
164 125
165 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); 126 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c
index 5b440859bcee..b207e7f1417a 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/gt64120/wrppmc/time.c
@@ -11,18 +11,11 @@
11 * Copyright (C) 2006, Wind River System Inc. 11 * Copyright (C) 2006, Wind River System Inc.
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/string.h>
15#include <linux/kernel.h>
16#include <linux/param.h> /* for HZ */
17#include <linux/irq.h>
18#include <linux/timex.h>
19#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/irq.h>
20 16
21#include <asm/reboot.h>
22#include <asm/time.h>
23#include <asm/io.h>
24#include <asm/bootinfo.h>
25#include <asm/gt64120.h> 17#include <asm/gt64120.h>
18#include <asm/time.h>
26 19
27#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ 20#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
28 21
@@ -38,7 +31,7 @@ void __init plat_timer_setup(struct irqaction *irq)
38 * NOTE: We disable all GT64120 timers, and use MIPS processor internal 31 * NOTE: We disable all GT64120 timers, and use MIPS processor internal
39 * timer as the source of kernel clock tick. 32 * timer as the source of kernel clock tick.
40 */ 33 */
41void __init wrppmc_time_init(void) 34void __init plat_time_init(void)
42{ 35{
43 /* Disable GT64120 timers */ 36 /* Disable GT64120 timers */
44 GT_WRITE(GT_TC_CONTROL_OFS, 0x00); 37 GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index 575a9442bc82..5aee0c266d18 100644
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -2,6 +2,6 @@
2# Makefile for the Jazz family specific parts of the kernel 2# Makefile for the Jazz family specific parts of the kernel
3# 3#
4 4
5obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o 5obj-y := irq.o jazzdma.o reset.o setup.o
6 6
7EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 015cf4bb51dd..835b056cea36 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -6,20 +6,23 @@
6 * Copyright (C) 1992 Linus Torvalds 6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2001, 2003 Ralf Baechle 7 * Copyright (C) 1994 - 2001, 2003 Ralf Baechle
8 */ 8 */
9#include <linux/clockchips.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/interrupt.h> 11#include <linux/interrupt.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
12#include <linux/spinlock.h> 13#include <linux/spinlock.h>
13 14
15#include <asm/irq_cpu.h>
14#include <asm/i8259.h> 16#include <asm/i8259.h>
15#include <asm/io.h> 17#include <asm/io.h>
16#include <asm/jazz.h> 18#include <asm/jazz.h>
19#include <asm/pgtable.h>
17 20
18static DEFINE_SPINLOCK(r4030_lock); 21static DEFINE_SPINLOCK(r4030_lock);
19 22
20static void enable_r4030_irq(unsigned int irq) 23static void enable_r4030_irq(unsigned int irq)
21{ 24{
22 unsigned int mask = 1 << (irq - JAZZ_PARALLEL_IRQ); 25 unsigned int mask = 1 << (irq - JAZZ_IRQ_START);
23 unsigned long flags; 26 unsigned long flags;
24 27
25 spin_lock_irqsave(&r4030_lock, flags); 28 spin_lock_irqsave(&r4030_lock, flags);
@@ -30,7 +33,7 @@ static void enable_r4030_irq(unsigned int irq)
30 33
31void disable_r4030_irq(unsigned int irq) 34void disable_r4030_irq(unsigned int irq)
32{ 35{
33 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); 36 unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START));
34 unsigned long flags; 37 unsigned long flags;
35 38
36 spin_lock_irqsave(&r4030_lock, flags); 39 spin_lock_irqsave(&r4030_lock, flags);
@@ -51,7 +54,7 @@ void __init init_r4030_ints(void)
51{ 54{
52 int i; 55 int i;
53 56
54 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) 57 for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
55 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); 58 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
56 59
57 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 60 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
@@ -66,82 +69,87 @@ void __init init_r4030_ints(void)
66 */ 69 */
67void __init arch_init_irq(void) 70void __init arch_init_irq(void)
68{ 71{
72 /*
73 * this is a hack to get back the still needed wired mapping
74 * killed by init_mm()
75 */
76
77 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
78 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
79 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
80 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
81 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
82 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
83
69 init_i8259_irqs(); /* Integrated i8259 */ 84 init_i8259_irqs(); /* Integrated i8259 */
85 mips_cpu_irq_init();
70 init_r4030_ints(); 86 init_r4030_ints();
71 87
72 change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1); 88 change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
73}
74
75static void loc_call(unsigned int irq, unsigned int mask)
76{
77 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
78 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask);
79 do_IRQ(irq);
80 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
81 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask);
82}
83
84static void ll_local_dev(void)
85{
86 switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) {
87 case 0:
88 panic("Unimplemented loc_no_irq handler");
89 break;
90 case 4:
91 loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL);
92 break;
93 case 8:
94 loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY);
95 break;
96 case 12:
97 panic("Unimplemented loc_sound handler");
98 break;
99 case 16:
100 panic("Unimplemented loc_video handler");
101 break;
102 case 20:
103 loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET);
104 break;
105 case 24:
106 loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI);
107 break;
108 case 28:
109 loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD);
110 break;
111 case 32:
112 loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE);
113 break;
114 case 36:
115 loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1);
116 break;
117 case 40:
118 loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2);
119 break;
120 }
121} 89}
122 90
123asmlinkage void plat_irq_dispatch(void) 91asmlinkage void plat_irq_dispatch(void)
124{ 92{
125 unsigned int pending = read_c0_cause() & read_c0_status(); 93 unsigned int pending = read_c0_cause() & read_c0_status();
94 unsigned int irq;
126 95
127 if (pending & IE_IRQ5) 96 if (pending & IE_IRQ4) {
128 write_c0_compare(0);
129 else if (pending & IE_IRQ4) {
130 r4030_read_reg32(JAZZ_TIMER_REGISTER); 97 r4030_read_reg32(JAZZ_TIMER_REGISTER);
131 do_IRQ(JAZZ_TIMER_IRQ); 98 do_IRQ(JAZZ_TIMER_IRQ);
132 } else if (pending & IE_IRQ3) 99 } else if (pending & IE_IRQ2)
133 panic("Unimplemented ISA NMI handler");
134 else if (pending & IE_IRQ2)
135 do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK)); 100 do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK));
136 else if (pending & IE_IRQ1) { 101 else if (pending & IE_IRQ1) {
137 ll_local_dev(); 102 irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
138 } else if (unlikely(pending & IE_IRQ0)) 103 if (likely(irq > 0))
139 panic("Unimplemented local_dma handler"); 104 do_IRQ(irq + JAZZ_IRQ_START - 1);
140 else if (pending & IE_SW1) { 105 else
141 clear_c0_cause(IE_SW1); 106 panic("Unimplemented loc_no_irq handler");
142 panic("Unimplemented sw1 handler");
143 } else if (pending & IE_SW0) {
144 clear_c0_cause(IE_SW0);
145 panic("Unimplemented sw0 handler");
146 } 107 }
147} 108}
109
110static void r4030_set_mode(enum clock_event_mode mode,
111 struct clock_event_device *evt)
112{
113 /* Nothing to do ... */
114}
115
116struct clock_event_device r4030_clockevent = {
117 .name = "r4030",
118 .features = CLOCK_EVT_FEAT_PERIODIC,
119 .rating = 100,
120 .irq = JAZZ_TIMER_IRQ,
121 .cpumask = CPU_MASK_CPU0,
122 .set_mode = r4030_set_mode,
123};
124
125static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
126{
127 r4030_clockevent.event_handler(&r4030_clockevent);
128
129 return IRQ_HANDLED;
130}
131
132static struct irqaction r4030_timer_irqaction = {
133 .handler = r4030_timer_interrupt,
134 .flags = IRQF_DISABLED,
135 .mask = CPU_MASK_CPU0,
136 .name = "timer",
137};
138
139void __init plat_timer_setup(struct irqaction *ignored)
140{
141 struct irqaction *irq = &r4030_timer_irqaction;
142
143 BUG_ON(HZ != 100);
144
145 /*
146 * Set clock to 100Hz.
147 *
148 * The R4030 timer receives an input clock of 1kHz which is divieded by
149 * a programmable 4-bit divider. This makes it fairly inflexible.
150 */
151 r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
152 setup_irq(JAZZ_TIMER_IRQ, irq);
153
154 clockevents_register_device(&r4030_clockevent);
155}
diff --git a/arch/mips/jazz/jazz-platform.c b/arch/mips/jazz/jazz-platform.c
deleted file mode 100644
index fd736703eef2..000000000000
--- a/arch/mips/jazz/jazz-platform.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/serial_8250.h>
11
12#include <asm/jazz.h>
13
14/*
15 * Confusion ... It seems the original Microsoft Jazz machine used to have a
16 * 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems
17 * had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs.
18 */
19#ifdef CONFIG_OLIVETTI_M700
20#define JAZZ_BASE_BAUD 1843200
21#else
22#define JAZZ_BASE_BAUD 8000000 /* 3072000 */
23#endif
24
25#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
26
27#define JAZZ_PORT(base, int) \
28{ \
29 .mapbase = base, \
30 .irq = int, \
31 .uartclk = JAZZ_BASE_BAUD, \
32 .iotype = UPIO_MEM, \
33 .flags = JAZZ_UART_FLAGS, \
34 .regshift = 0, \
35}
36
37static struct plat_serial8250_port uart8250_data[] = {
38 JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
39 JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
40 { },
41};
42
43static struct platform_device uart8250_device = {
44 .name = "serial8250",
45 .id = PLAT8250_DEV_PLATFORM,
46 .dev = {
47 .platform_data = uart8250_data,
48 },
49};
50
51static int __init uart8250_init(void)
52{
53 return platform_device_register(&uart8250_device);
54}
55
56module_init(uart8250_init);
57
58MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
59MODULE_LICENSE("GPL");
60MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family");
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index e8e0ffb9354d..c672c08d49e5 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -27,7 +27,7 @@
27 */ 27 */
28#define CONF_DEBUG_VDMA 0 28#define CONF_DEBUG_VDMA 0
29 29
30static unsigned long vdma_pagetable_start; 30static VDMA_PGTBL_ENTRY *pgtbl;
31 31
32static DEFINE_SPINLOCK(vdma_lock); 32static DEFINE_SPINLOCK(vdma_lock);
33 33
@@ -46,7 +46,6 @@ static int debuglvl = 3;
46 */ 46 */
47static inline void vdma_pgtbl_init(void) 47static inline void vdma_pgtbl_init(void)
48{ 48{
49 VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
50 unsigned long paddr = 0; 49 unsigned long paddr = 0;
51 int i; 50 int i;
52 51
@@ -60,31 +59,31 @@ static inline void vdma_pgtbl_init(void)
60/* 59/*
61 * Initialize the Jazz R4030 dma controller 60 * Initialize the Jazz R4030 dma controller
62 */ 61 */
63void __init vdma_init(void) 62static int __init vdma_init(void)
64{ 63{
65 /* 64 /*
66 * Allocate 32k of memory for DMA page tables. This needs to be page 65 * Allocate 32k of memory for DMA page tables. This needs to be page
67 * aligned and should be uncached to avoid cache flushing after every 66 * aligned and should be uncached to avoid cache flushing after every
68 * update. 67 * update.
69 */ 68 */
70 vdma_pagetable_start = 69 pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
71 (unsigned long) alloc_bootmem_low_pages(VDMA_PGTBL_SIZE); 70 get_order(VDMA_PGTBL_SIZE));
72 if (!vdma_pagetable_start) 71 if (!pgtbl)
73 BUG(); 72 BUG();
74 dma_cache_wback_inv(vdma_pagetable_start, VDMA_PGTBL_SIZE); 73 dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
75 vdma_pagetable_start = KSEG1ADDR(vdma_pagetable_start); 74 pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
76 75
77 /* 76 /*
78 * Clear the R4030 translation table 77 * Clear the R4030 translation table
79 */ 78 */
80 vdma_pgtbl_init(); 79 vdma_pgtbl_init();
81 80
82 r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, 81 r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
83 CPHYSADDR(vdma_pagetable_start));
84 r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE); 82 r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
85 r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0); 83 r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
86 84
87 printk("VDMA: R4030 DMA pagetables initialized.\n"); 85 printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n");
86 return 0;
88} 87}
89 88
90/* 89/*
@@ -92,7 +91,6 @@ void __init vdma_init(void)
92 */ 91 */
93unsigned long vdma_alloc(unsigned long paddr, unsigned long size) 92unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
94{ 93{
95 VDMA_PGTBL_ENTRY *entry = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
96 int first, last, pages, frame, i; 94 int first, last, pages, frame, i;
97 unsigned long laddr, flags; 95 unsigned long laddr, flags;
98 96
@@ -114,10 +112,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
114 /* 112 /*
115 * Find free chunk 113 * Find free chunk
116 */ 114 */
117 pages = (size + 4095) >> 12; /* no. of pages to allocate */ 115 pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1;
118 first = 0; 116 first = 0;
119 while (1) { 117 while (1) {
120 while (entry[first].owner != VDMA_PAGE_EMPTY && 118 while (pgtbl[first].owner != VDMA_PAGE_EMPTY &&
121 first < VDMA_PGTBL_ENTRIES) first++; 119 first < VDMA_PGTBL_ENTRIES) first++;
122 if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */ 120 if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */
123 spin_unlock_irqrestore(&vdma_lock, flags); 121 spin_unlock_irqrestore(&vdma_lock, flags);
@@ -125,12 +123,13 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
125 } 123 }
126 124
127 last = first + 1; 125 last = first + 1;
128 while (entry[last].owner == VDMA_PAGE_EMPTY 126 while (pgtbl[last].owner == VDMA_PAGE_EMPTY
129 && last - first < pages) 127 && last - first < pages)
130 last++; 128 last++;
131 129
132 if (last - first == pages) 130 if (last - first == pages)
133 break; /* found */ 131 break; /* found */
132 first = last + 1;
134 } 133 }
135 134
136 /* 135 /*
@@ -140,8 +139,8 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
140 frame = paddr & ~(VDMA_PAGESIZE - 1); 139 frame = paddr & ~(VDMA_PAGESIZE - 1);
141 140
142 for (i = first; i < last; i++) { 141 for (i = first; i < last; i++) {
143 entry[i].frame = frame; 142 pgtbl[i].frame = frame;
144 entry[i].owner = laddr; 143 pgtbl[i].owner = laddr;
145 frame += VDMA_PAGESIZE; 144 frame += VDMA_PAGESIZE;
146 } 145 }
147 146
@@ -160,10 +159,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
160 printk("%08x ", i << 12); 159 printk("%08x ", i << 12);
161 printk("\nPADDR: "); 160 printk("\nPADDR: ");
162 for (i = first; i < last; i++) 161 for (i = first; i < last; i++)
163 printk("%08x ", entry[i].frame); 162 printk("%08x ", pgtbl[i].frame);
164 printk("\nOWNER: "); 163 printk("\nOWNER: ");
165 for (i = first; i < last; i++) 164 for (i = first; i < last; i++)
166 printk("%08x ", entry[i].owner); 165 printk("%08x ", pgtbl[i].owner);
167 printk("\n"); 166 printk("\n");
168 } 167 }
169 168
@@ -181,7 +180,6 @@ EXPORT_SYMBOL(vdma_alloc);
181 */ 180 */
182int vdma_free(unsigned long laddr) 181int vdma_free(unsigned long laddr)
183{ 182{
184 VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
185 int i; 183 int i;
186 184
187 i = laddr >> 12; 185 i = laddr >> 12;
@@ -213,8 +211,6 @@ EXPORT_SYMBOL(vdma_free);
213 */ 211 */
214int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) 212int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
215{ 213{
216 VDMA_PGTBL_ENTRY *pgtbl =
217 (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
218 int first, pages, npages; 214 int first, pages, npages;
219 215
220 if (laddr > 0xffffff) { 216 if (laddr > 0xffffff) {
@@ -289,8 +285,6 @@ unsigned long vdma_phys2log(unsigned long paddr)
289{ 285{
290 int i; 286 int i;
291 int frame; 287 int frame;
292 VDMA_PGTBL_ENTRY *pgtbl =
293 (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
294 288
295 frame = paddr & ~(VDMA_PAGESIZE - 1); 289 frame = paddr & ~(VDMA_PAGESIZE - 1);
296 290
@@ -312,9 +306,6 @@ EXPORT_SYMBOL(vdma_phys2log);
312 */ 306 */
313unsigned long vdma_log2phys(unsigned long laddr) 307unsigned long vdma_log2phys(unsigned long laddr)
314{ 308{
315 VDMA_PGTBL_ENTRY *pgtbl =
316 (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
317
318 return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1)); 309 return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1));
319} 310}
320 311
@@ -564,3 +555,5 @@ int vdma_get_enable(int channel)
564 555
565 return enable; 556 return enable;
566} 557}
558
559arch_initcall(vdma_init);
diff --git a/arch/mips/jazz/reset.c b/arch/mips/jazz/reset.c
index d8ade85060b3..dd889fe86bd1 100644
--- a/arch/mips/jazz/reset.c
+++ b/arch/mips/jazz/reset.c
@@ -49,8 +49,8 @@ void jazz_machine_restart(char *command)
49{ 49{
50 while(1) { 50 while(1) {
51 kb_wait(); 51 kb_wait();
52 jazz_write_command (0xd1); 52 jazz_write_command(0xd1);
53 kb_wait(); 53 kb_wait();
54 jazz_write_output (0x00); 54 jazz_write_output(0x00);
55 } 55 }
56} 56}
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 798279e06691..cfc7dce78dab 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -7,6 +7,7 @@
7 * 7 *
8 * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle 8 * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
9 * Copyright (C) 2001 MIPS Technologies, Inc. 9 * Copyright (C) 2001 MIPS Technologies, Inc.
10 * Copyright (C) 2007 by Thomas Bogendoerfer
10 */ 11 */
11#include <linux/eisa.h> 12#include <linux/eisa.h>
12#include <linux/hdreg.h> 13#include <linux/hdreg.h>
@@ -20,8 +21,11 @@
20#include <linux/ide.h> 21#include <linux/ide.h>
21#include <linux/pm.h> 22#include <linux/pm.h>
22#include <linux/screen_info.h> 23#include <linux/screen_info.h>
24#include <linux/platform_device.h>
25#include <linux/serial_8250.h>
23 26
24#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/i8253.h>
25#include <asm/irq.h> 29#include <asm/irq.h>
26#include <asm/jazz.h> 30#include <asm/jazz.h>
27#include <asm/jazzdma.h> 31#include <asm/jazzdma.h>
@@ -30,18 +34,12 @@
30#include <asm/pgtable.h> 34#include <asm/pgtable.h>
31#include <asm/time.h> 35#include <asm/time.h>
32#include <asm/traps.h> 36#include <asm/traps.h>
37#include <asm/mc146818-time.h>
33 38
34extern asmlinkage void jazz_handle_int(void); 39extern asmlinkage void jazz_handle_int(void);
35 40
36extern void jazz_machine_restart(char *command); 41extern void jazz_machine_restart(char *command);
37 42
38void __init plat_timer_setup(struct irqaction *irq)
39{
40 /* set the clock to 100 Hz */
41 r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
42 setup_irq(JAZZ_TIMER_IRQ, irq);
43}
44
45static struct resource jazz_io_resources[] = { 43static struct resource jazz_io_resources[] = {
46 { 44 {
47 .start = 0x00, 45 .start = 0x00,
@@ -66,18 +64,21 @@ static struct resource jazz_io_resources[] = {
66 } 64 }
67}; 65};
68 66
67void __init plat_time_init(void)
68{
69 setup_pit_timer();
70}
71
69void __init plat_mem_setup(void) 72void __init plat_mem_setup(void)
70{ 73{
71 int i; 74 int i;
72 75
73 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ 76 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
74 add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K); 77 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
75
76 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ 78 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
77 add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M); 79 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
78
79 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ 80 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
80 add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M); 81 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
81 82
82 set_io_port_base(JAZZ_PORT_BASE); 83 set_io_port_base(JAZZ_PORT_BASE);
83#ifdef CONFIG_EISA 84#ifdef CONFIG_EISA
@@ -94,6 +95,7 @@ void __init plat_mem_setup(void)
94 95
95 _machine_restart = jazz_machine_restart; 96 _machine_restart = jazz_machine_restart;
96 97
98#ifdef CONFIG_VT
97 screen_info = (struct screen_info) { 99 screen_info = (struct screen_info) {
98 0, 0, /* orig-x, orig-y */ 100 0, 0, /* orig-x, orig-y */
99 0, /* unused */ 101 0, /* unused */
@@ -105,6 +107,112 @@ void __init plat_mem_setup(void)
105 0, /* orig_video_isVGA */ 107 0, /* orig_video_isVGA */
106 16 /* orig_video_points */ 108 16 /* orig_video_points */
107 }; 109 };
110#endif
108 111
109 vdma_init(); 112 add_preferred_console("ttyS", 0, "9600");
110} 113}
114
115#ifdef CONFIG_OLIVETTI_M700
116#define UART_CLK 1843200
117#else
118/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
119 exactly which ones ... XXX */
120#define UART_CLK (8000000 / 16) /* ( 3072000 / 16) */
121#endif
122
123#define MEMPORT(_base, _irq) \
124 { \
125 .mapbase = (_base), \
126 .membase = (void *)(_base), \
127 .irq = (_irq), \
128 .uartclk = UART_CLK, \
129 .iotype = UPIO_MEM, \
130 .flags = UPF_BOOT_AUTOCONF, \
131 }
132
133static struct plat_serial8250_port jazz_serial_data[] = {
134 MEMPORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
135 MEMPORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
136 { },
137};
138
139static struct platform_device jazz_serial8250_device = {
140 .name = "serial8250",
141 .id = PLAT8250_DEV_PLATFORM,
142 .dev = {
143 .platform_data = jazz_serial_data,
144 },
145};
146
147static struct resource jazz_esp_rsrc[] = {
148 {
149 .start = JAZZ_SCSI_BASE,
150 .end = JAZZ_SCSI_BASE + 31,
151 .flags = IORESOURCE_MEM
152 },
153 {
154 .start = JAZZ_SCSI_DMA,
155 .end = JAZZ_SCSI_DMA,
156 .flags = IORESOURCE_MEM
157 },
158 {
159 .start = JAZZ_SCSI_IRQ,
160 .end = JAZZ_SCSI_IRQ,
161 .flags = IORESOURCE_IRQ
162 }
163};
164
165static struct platform_device jazz_esp_pdev = {
166 .name = "jazz_esp",
167 .num_resources = ARRAY_SIZE(jazz_esp_rsrc),
168 .resource = jazz_esp_rsrc
169};
170
171static struct resource jazz_sonic_rsrc[] = {
172 {
173 .start = JAZZ_ETHERNET_BASE,
174 .end = JAZZ_ETHERNET_BASE + 0xff,
175 .flags = IORESOURCE_MEM
176 },
177 {
178 .start = JAZZ_ETHERNET_IRQ,
179 .end = JAZZ_ETHERNET_IRQ,
180 .flags = IORESOURCE_IRQ
181 }
182};
183
184static struct platform_device jazz_sonic_pdev = {
185 .name = "jazzsonic",
186 .num_resources = ARRAY_SIZE(jazz_sonic_rsrc),
187 .resource = jazz_sonic_rsrc
188};
189
190static struct resource jazz_cmos_rsrc[] = {
191 {
192 .start = 0x70,
193 .end = 0x71,
194 .flags = IORESOURCE_IO
195 },
196 {
197 .start = 8,
198 .end = 8,
199 .flags = IORESOURCE_IRQ
200 }
201};
202
203static struct platform_device jazz_cmos_pdev = {
204 .name = "rtc_cmos",
205 .num_resources = ARRAY_SIZE(jazz_cmos_rsrc),
206 .resource = jazz_cmos_rsrc
207};
208
209static int __init jazz_setup_devinit(void)
210{
211 platform_device_register(&jazz_serial8250_device);
212 platform_device_register(&jazz_esp_pdev);
213 platform_device_register(&jazz_sonic_pdev);
214 platform_device_register(&jazz_cmos_pdev);
215 return 0;
216}
217
218device_initcall(jazz_setup_devinit);
diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c
index 9169fab1773a..b643f75ec9a5 100644
--- a/arch/mips/jmr3927/rbhma3100/init.c
+++ b/arch/mips/jmr3927/rbhma3100/init.c
@@ -51,7 +51,6 @@ void __init prom_init(void)
51 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) 51 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
52 puts("Warning: TX3927 TLB off\n"); 52 puts("Warning: TX3927 TLB off\n");
53#endif 53#endif
54 mips_machgroup = MACH_GROUP_TOSHIBA;
55 54
56#ifdef CONFIG_TOSHIBA_JMR3927 55#ifdef CONFIG_TOSHIBA_JMR3927
57 mips_machtype = MACH_TOSHIBA_JMR3927; 56 mips_machtype = MACH_TOSHIBA_JMR3927;
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index d9efe692e551..3a47e8ce1196 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -104,7 +104,9 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
104} 104}
105 105
106static struct irqaction ioc_action = { 106static struct irqaction ioc_action = {
107 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, 107 .handler = jmr3927_ioc_interrupt,
108 .mask = CPU_MASK_NONE,
109 .name = "IOC",
108}; 110};
109 111
110static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 112static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
@@ -116,7 +118,9 @@ static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
116 return IRQ_HANDLED; 118 return IRQ_HANDLED;
117} 119}
118static struct irqaction pcierr_action = { 120static struct irqaction pcierr_action = {
119 jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL, 121 .handler = jmr3927_pcierr_interrupt,
122 .mask = CPU_MASK_NONE,
123 .name = "PCI error",
120}; 124};
121 125
122static void __init jmr3927_irq_init(void); 126static void __init jmr3927_irq_init(void);
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index fde56e86c2ab..7f14f70a1b88 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -109,7 +109,7 @@ static void jmr3927_timer_ack(void)
109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */ 109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
110} 110}
111 111
112static void __init jmr3927_time_init(void) 112void __init plat_time_init(void)
113{ 113{
114 clocksource_mips.read = jmr3927_hpt_read; 114 clocksource_mips.read = jmr3927_hpt_read;
115 mips_timer_ack = jmr3927_timer_ack; 115 mips_timer_ack = jmr3927_timer_ack;
@@ -141,8 +141,6 @@ void __init plat_mem_setup(void)
141 141
142 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); 142 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
143 143
144 board_time_init = jmr3927_time_init;
145
146 _machine_restart = jmr3927_machine_restart; 144 _machine_restart = jmr3927_machine_restart;
147 _machine_halt = jmr3927_machine_halt; 145 _machine_halt = jmr3927_machine_halt;
148 pm_power_off = jmr3927_machine_power_off; 146 pm_power_off = jmr3927_machine_power_off;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 2fd96d95a39c..a2689f93c160 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o 52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o 53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
54obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
54 55
55obj-$(CONFIG_32BIT) += scall32-o32.o 56obj-$(CONFIG_32BIT) += scall32-o32.o
56obj-$(CONFIG_64BIT) += scall64-64.o 57obj-$(CONFIG_64BIT) += scall64-64.o
@@ -64,6 +65,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
64 65
65obj-$(CONFIG_64BIT) += cpu-bugs64.o 66obj-$(CONFIG_64BIT) += cpu-bugs64.o
66 67
68obj-$(CONFIG_I8253) += i8253.o
67obj-$(CONFIG_PCSPEAKER) += pcspeaker.o 69obj-$(CONFIG_PCSPEAKER) += pcspeaker.o
68 70
69obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o 71obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 993f7ec70f35..da41eac195ca 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -110,7 +110,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
110} 110}
111 111
112#undef ELF_CORE_COPY_REGS 112#undef ELF_CORE_COPY_REGS
113#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); 113#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
114 114
115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) 115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
116{ 116{
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 6648fde20b96..af78456d4138 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -29,7 +29,7 @@ static inline void align_mod(const int align, const int mod)
29 ".endr\n\t" 29 ".endr\n\t"
30 ".set pop" 30 ".set pop"
31 : 31 :
32 : GCC_IMM_ASM (align), GCC_IMM_ASM (mod)); 32 : GCC_IMM_ASM(align), GCC_IMM_ASM(mod));
33} 33}
34 34
35static inline void mult_sh_align_mod(long *v1, long *v2, long *w, 35static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3e004161ebd5..c8c47a2d1972 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -159,6 +159,7 @@ static inline void check_wait(void)
159 case CPU_5KC: 159 case CPU_5KC:
160 case CPU_25KF: 160 case CPU_25KF:
161 case CPU_PR4450: 161 case CPU_PR4450:
162 case CPU_BCM3302:
162 cpu_wait = r4k_wait; 163 cpu_wait = r4k_wait;
163 break; 164 break;
164 165
@@ -745,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
745{ 746{
746 decode_configs(c); 747 decode_configs(c);
747 748
748 /*
749 * For historical reasons the SB1 comes with it's own variant of
750 * cache code which eventually will be folded into c-r4k.c. Until
751 * then we pretend it's got it's own cache architecture.
752 */
753 c->options &= ~MIPS_CPU_4K_CACHE;
754 c->options |= MIPS_CPU_SB1_CACHE;
755
756 switch (c->processor_id & 0xff00) { 749 switch (c->processor_id & 0xff00) {
757 case PRID_IMP_SB1: 750 case PRID_IMP_SB1:
758 c->cputype = CPU_SB1; 751 c->cputype = CPU_SB1;
@@ -793,9 +786,111 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c)
793} 786}
794 787
795 788
789static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
790{
791 decode_configs(c);
792 switch (c->processor_id & 0xff00) {
793 case PRID_IMP_BCM3302:
794 c->cputype = CPU_BCM3302;
795 break;
796 case PRID_IMP_BCM4710:
797 c->cputype = CPU_BCM4710;
798 break;
799 default:
800 c->cputype = CPU_UNKNOWN;
801 break;
802 }
803}
804
805const char *__cpu_name[NR_CPUS];
806
807/*
808 * Name a CPU
809 */
810static __init const char *cpu_to_name(struct cpuinfo_mips *c)
811{
812 const char *name = NULL;
813
814 switch (c->cputype) {
815 case CPU_UNKNOWN: name = "unknown"; break;
816 case CPU_R2000: name = "R2000"; break;
817 case CPU_R3000: name = "R3000"; break;
818 case CPU_R3000A: name = "R3000A"; break;
819 case CPU_R3041: name = "R3041"; break;
820 case CPU_R3051: name = "R3051"; break;
821 case CPU_R3052: name = "R3052"; break;
822 case CPU_R3081: name = "R3081"; break;
823 case CPU_R3081E: name = "R3081E"; break;
824 case CPU_R4000PC: name = "R4000PC"; break;
825 case CPU_R4000SC: name = "R4000SC"; break;
826 case CPU_R4000MC: name = "R4000MC"; break;
827 case CPU_R4200: name = "R4200"; break;
828 case CPU_R4400PC: name = "R4400PC"; break;
829 case CPU_R4400SC: name = "R4400SC"; break;
830 case CPU_R4400MC: name = "R4400MC"; break;
831 case CPU_R4600: name = "R4600"; break;
832 case CPU_R6000: name = "R6000"; break;
833 case CPU_R6000A: name = "R6000A"; break;
834 case CPU_R8000: name = "R8000"; break;
835 case CPU_R10000: name = "R10000"; break;
836 case CPU_R12000: name = "R12000"; break;
837 case CPU_R14000: name = "R14000"; break;
838 case CPU_R4300: name = "R4300"; break;
839 case CPU_R4650: name = "R4650"; break;
840 case CPU_R4700: name = "R4700"; break;
841 case CPU_R5000: name = "R5000"; break;
842 case CPU_R5000A: name = "R5000A"; break;
843 case CPU_R4640: name = "R4640"; break;
844 case CPU_NEVADA: name = "Nevada"; break;
845 case CPU_RM7000: name = "RM7000"; break;
846 case CPU_RM9000: name = "RM9000"; break;
847 case CPU_R5432: name = "R5432"; break;
848 case CPU_4KC: name = "MIPS 4Kc"; break;
849 case CPU_5KC: name = "MIPS 5Kc"; break;
850 case CPU_R4310: name = "R4310"; break;
851 case CPU_SB1: name = "SiByte SB1"; break;
852 case CPU_SB1A: name = "SiByte SB1A"; break;
853 case CPU_TX3912: name = "TX3912"; break;
854 case CPU_TX3922: name = "TX3922"; break;
855 case CPU_TX3927: name = "TX3927"; break;
856 case CPU_AU1000: name = "Au1000"; break;
857 case CPU_AU1500: name = "Au1500"; break;
858 case CPU_AU1100: name = "Au1100"; break;
859 case CPU_AU1550: name = "Au1550"; break;
860 case CPU_AU1200: name = "Au1200"; break;
861 case CPU_4KEC: name = "MIPS 4KEc"; break;
862 case CPU_4KSC: name = "MIPS 4KSc"; break;
863 case CPU_VR41XX: name = "NEC Vr41xx"; break;
864 case CPU_R5500: name = "R5500"; break;
865 case CPU_TX49XX: name = "TX49xx"; break;
866 case CPU_20KC: name = "MIPS 20Kc"; break;
867 case CPU_24K: name = "MIPS 24K"; break;
868 case CPU_25KF: name = "MIPS 25Kf"; break;
869 case CPU_34K: name = "MIPS 34K"; break;
870 case CPU_74K: name = "MIPS 74K"; break;
871 case CPU_VR4111: name = "NEC VR4111"; break;
872 case CPU_VR4121: name = "NEC VR4121"; break;
873 case CPU_VR4122: name = "NEC VR4122"; break;
874 case CPU_VR4131: name = "NEC VR4131"; break;
875 case CPU_VR4133: name = "NEC VR4133"; break;
876 case CPU_VR4181: name = "NEC VR4181"; break;
877 case CPU_VR4181A: name = "NEC VR4181A"; break;
878 case CPU_SR71000: name = "Sandcraft SR71000"; break;
879 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
880 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
881 case CPU_PR4450: name = "Philips PR4450"; break;
882 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
883 default:
884 BUG();
885 }
886
887 return name;
888}
889
796__init void cpu_probe(void) 890__init void cpu_probe(void)
797{ 891{
798 struct cpuinfo_mips *c = &current_cpu_data; 892 struct cpuinfo_mips *c = &current_cpu_data;
893 unsigned int cpu = smp_processor_id();
799 894
800 c->processor_id = PRID_IMP_UNKNOWN; 895 c->processor_id = PRID_IMP_UNKNOWN;
801 c->fpu_id = FPIR_IMP_NONE; 896 c->fpu_id = FPIR_IMP_NONE;
@@ -815,6 +910,9 @@ __init void cpu_probe(void)
815 case PRID_COMP_SIBYTE: 910 case PRID_COMP_SIBYTE:
816 cpu_probe_sibyte(c); 911 cpu_probe_sibyte(c);
817 break; 912 break;
913 case PRID_COMP_BROADCOM:
914 cpu_probe_broadcom(c);
915 break;
818 case PRID_COMP_SANDCRAFT: 916 case PRID_COMP_SANDCRAFT:
819 cpu_probe_sandcraft(c); 917 cpu_probe_sandcraft(c);
820 break; 918 break;
@@ -824,6 +922,14 @@ __init void cpu_probe(void)
824 default: 922 default:
825 c->cputype = CPU_UNKNOWN; 923 c->cputype = CPU_UNKNOWN;
826 } 924 }
925
926 /*
927 * Platform code can force the cpu type to optimize code
928 * generation. In that case be sure the cpu type is correctly
929 * manually setup otherwise it could trigger some nasty bugs.
930 */
931 BUG_ON(current_cpu_type() != c->cputype);
932
827 if (c->options & MIPS_CPU_FPU) { 933 if (c->options & MIPS_CPU_FPU) {
828 c->fpu_id = cpu_get_fpu_id(); 934 c->fpu_id = cpu_get_fpu_id();
829 935
@@ -835,13 +941,16 @@ __init void cpu_probe(void)
835 c->ases |= MIPS_ASE_MIPS3D; 941 c->ases |= MIPS_ASE_MIPS3D;
836 } 942 }
837 } 943 }
944
945 __cpu_name[cpu] = cpu_to_name(c);
838} 946}
839 947
840__init void cpu_report(void) 948__init void cpu_report(void)
841{ 949{
842 struct cpuinfo_mips *c = &current_cpu_data; 950 struct cpuinfo_mips *c = &current_cpu_data;
843 951
844 printk("CPU revision is: %08x\n", c->processor_id); 952 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
953 c->processor_id, cpu_name_string());
845 if (c->options & MIPS_CPU_FPU) 954 if (c->options & MIPS_CPU_FPU)
846 printk("FPU revision is: %08x\n", c->fpu_id); 955 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
847} 956}
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index cb5623aad552..3191afa29ad8 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -676,15 +676,18 @@ static void kgdb_wait(void *arg)
676static int kgdb_smp_call_kgdb_wait(void) 676static int kgdb_smp_call_kgdb_wait(void)
677{ 677{
678#ifdef CONFIG_SMP 678#ifdef CONFIG_SMP
679 cpumask_t mask = cpu_online_map;
679 struct call_data_struct data; 680 struct call_data_struct data;
680 int i, cpus = num_online_cpus() - 1;
681 int cpu = smp_processor_id(); 681 int cpu = smp_processor_id();
682 int cpus;
682 683
683 /* 684 /*
684 * Can die spectacularly if this CPU isn't yet marked online 685 * Can die spectacularly if this CPU isn't yet marked online
685 */ 686 */
686 BUG_ON(!cpu_online(cpu)); 687 BUG_ON(!cpu_online(cpu));
687 688
689 cpu_clear(cpu, mask);
690 cpus = cpus_weight(mask);
688 if (!cpus) 691 if (!cpus)
689 return 0; 692 return 0;
690 693
@@ -711,10 +714,7 @@ static int kgdb_smp_call_kgdb_wait(void)
711 call_data = &data; 714 call_data = &data;
712 mb(); 715 mb();
713 716
714 /* Send a message to all other CPUs and wait for them to respond */ 717 core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
715 for (i = 0; i < NR_CPUS; i++)
716 if (cpu_online(i) && i != cpu)
717 core_send_ipi(i, SMP_CALL_FUNCTION);
718 718
719 /* Wait for response */ 719 /* Wait for response */
720 /* FIXME: lock-up detection, backtrace on lock-up */ 720 /* FIXME: lock-up detection, backtrace on lock-up */
@@ -733,7 +733,7 @@ static int kgdb_smp_call_kgdb_wait(void)
733 * returns 1 if you should skip the instruction at the trap address, 0 733 * returns 1 if you should skip the instruction at the trap address, 0
734 * otherwise. 734 * otherwise.
735 */ 735 */
736void handle_exception (struct gdb_regs *regs) 736void handle_exception(struct gdb_regs *regs)
737{ 737{
738 int trap; /* Trap type */ 738 int trap; /* Trap type */
739 int sigval; 739 int sigval;
@@ -769,7 +769,7 @@ void handle_exception (struct gdb_regs *regs)
769 /* 769 /*
770 * acquire the CPU spinlocks 770 * acquire the CPU spinlocks
771 */ 771 */
772 for (i = num_online_cpus()-1; i >= 0; i--) 772 for_each_online_cpu(i)
773 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0) 773 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
774 panic("kgdb: couldn't get cpulock %d\n", i); 774 panic("kgdb: couldn't get cpulock %d\n", i);
775 775
@@ -902,7 +902,7 @@ void handle_exception (struct gdb_regs *regs)
902 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0); 902 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
903 ptr += 2*(2*sizeof(long)); 903 ptr += 2*(2*sizeof(long));
904 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0); 904 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
905 strcpy(output_buffer,"OK"); 905 strcpy(output_buffer, "OK");
906 } 906 }
907 break; 907 break;
908 908
@@ -917,9 +917,9 @@ void handle_exception (struct gdb_regs *regs)
917 && hexToInt(&ptr, &length)) { 917 && hexToInt(&ptr, &length)) {
918 if (mem2hex((char *)addr, output_buffer, length, 1)) 918 if (mem2hex((char *)addr, output_buffer, length, 1))
919 break; 919 break;
920 strcpy (output_buffer, "E03"); 920 strcpy(output_buffer, "E03");
921 } else 921 } else
922 strcpy(output_buffer,"E01"); 922 strcpy(output_buffer, "E01");
923 break; 923 break;
924 924
925 /* 925 /*
@@ -996,7 +996,7 @@ void handle_exception (struct gdb_regs *regs)
996 ptr = &input_buffer[1]; 996 ptr = &input_buffer[1];
997 if (!hexToInt(&ptr, &baudrate)) 997 if (!hexToInt(&ptr, &baudrate))
998 { 998 {
999 strcpy(output_buffer,"B01"); 999 strcpy(output_buffer, "B01");
1000 break; 1000 break;
1001 } 1001 }
1002 1002
@@ -1015,7 +1015,7 @@ void handle_exception (struct gdb_regs *regs)
1015 break; 1015 break;
1016 default: 1016 default:
1017 baudrate = 0; 1017 baudrate = 0;
1018 strcpy(output_buffer,"B02"); 1018 strcpy(output_buffer, "B02");
1019 goto x1; 1019 goto x1;
1020 } 1020 }
1021 1021
@@ -1044,7 +1044,7 @@ finish_kgdb:
1044 1044
1045exit_kgdb_exception: 1045exit_kgdb_exception:
1046 /* release locks so other CPUs can go */ 1046 /* release locks so other CPUs can go */
1047 for (i = num_online_cpus()-1; i >= 0; i--) 1047 for_each_online_cpu(i)
1048 __raw_spin_unlock(&kgdb_cpulock[i]); 1048 __raw_spin_unlock(&kgdb_cpulock[i]);
1049 spin_unlock(&kgdb_lock); 1049 spin_unlock(&kgdb_lock);
1050 1050
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
new file mode 100644
index 000000000000..5d9830df3595
--- /dev/null
+++ b/arch/mips/kernel/i8253.c
@@ -0,0 +1,213 @@
1/*
2 * i8253.c 8253/PIT functions
3 *
4 */
5#include <linux/clockchips.h>
6#include <linux/init.h>
7#include <linux/interrupt.h>
8#include <linux/jiffies.h>
9#include <linux/module.h>
10#include <linux/spinlock.h>
11
12#include <asm/delay.h>
13#include <asm/i8253.h>
14#include <asm/io.h>
15
16static DEFINE_SPINLOCK(i8253_lock);
17
18/*
19 * Initialize the PIT timer.
20 *
21 * This is also called after resume to bring the PIT into operation again.
22 */
23static void init_pit_timer(enum clock_event_mode mode,
24 struct clock_event_device *evt)
25{
26 unsigned long flags;
27
28 spin_lock_irqsave(&i8253_lock, flags);
29
30 switch(mode) {
31 case CLOCK_EVT_MODE_PERIODIC:
32 /* binary, mode 2, LSB/MSB, ch 0 */
33 outb_p(0x34, PIT_MODE);
34 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
35 outb(LATCH >> 8 , PIT_CH0); /* MSB */
36 break;
37
38 case CLOCK_EVT_MODE_SHUTDOWN:
39 case CLOCK_EVT_MODE_UNUSED:
40 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
41 evt->mode == CLOCK_EVT_MODE_ONESHOT) {
42 outb_p(0x30, PIT_MODE);
43 outb_p(0, PIT_CH0);
44 outb_p(0, PIT_CH0);
45 }
46 break;
47
48 case CLOCK_EVT_MODE_ONESHOT:
49 /* One shot setup */
50 outb_p(0x38, PIT_MODE);
51 break;
52
53 case CLOCK_EVT_MODE_RESUME:
54 /* Nothing to do here */
55 break;
56 }
57 spin_unlock_irqrestore(&i8253_lock, flags);
58}
59
60/*
61 * Program the next event in oneshot mode
62 *
63 * Delta is given in PIT ticks
64 */
65static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&i8253_lock, flags);
70 outb_p(delta & 0xff , PIT_CH0); /* LSB */
71 outb(delta >> 8 , PIT_CH0); /* MSB */
72 spin_unlock_irqrestore(&i8253_lock, flags);
73
74 return 0;
75}
76
77/*
78 * On UP the PIT can serve all of the possible timer functions. On SMP systems
79 * it can be solely used for the global tick.
80 *
81 * The profiling and update capabilites are switched off once the local apic is
82 * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
83 * !using_apic_timer decisions in do_timer_interrupt_hook()
84 */
85struct clock_event_device pit_clockevent = {
86 .name = "pit",
87 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
88 .set_mode = init_pit_timer,
89 .set_next_event = pit_next_event,
90 .shift = 32,
91 .irq = 0,
92};
93
94irqreturn_t timer_interrupt(int irq, void *dev_id)
95{
96 pit_clockevent.event_handler(&pit_clockevent);
97
98 return IRQ_HANDLED;
99}
100
101static struct irqaction irq0 = {
102 .handler = timer_interrupt,
103 .flags = IRQF_DISABLED | IRQF_NOBALANCING,
104 .mask = CPU_MASK_NONE,
105 .name = "timer"
106};
107
108/*
109 * Initialize the conversion factor and the min/max deltas of the clock event
110 * structure and register the clock event source with the framework.
111 */
112void __init setup_pit_timer(void)
113{
114 /*
115 * Start pit with the boot cpu mask and make it global after the
116 * IO_APIC has been initialized.
117 */
118 pit_clockevent.cpumask = cpumask_of_cpu(0);
119 pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
120 pit_clockevent.max_delta_ns =
121 clockevent_delta2ns(0x7FFF, &pit_clockevent);
122 pit_clockevent.min_delta_ns =
123 clockevent_delta2ns(0xF, &pit_clockevent);
124 clockevents_register_device(&pit_clockevent);
125
126 irq0.mask = cpumask_of_cpu(0);
127 setup_irq(0, &irq0);
128}
129
130/*
131 * Since the PIT overflows every tick, its not very useful
132 * to just read by itself. So use jiffies to emulate a free
133 * running counter:
134 */
135static cycle_t pit_read(void)
136{
137 unsigned long flags;
138 int count;
139 u32 jifs;
140 static int old_count;
141 static u32 old_jifs;
142
143 spin_lock_irqsave(&i8253_lock, flags);
144 /*
145 * Although our caller may have the read side of xtime_lock,
146 * this is now a seqlock, and we are cheating in this routine
147 * by having side effects on state that we cannot undo if
148 * there is a collision on the seqlock and our caller has to
149 * retry. (Namely, old_jifs and old_count.) So we must treat
150 * jiffies as volatile despite the lock. We read jiffies
151 * before latching the timer count to guarantee that although
152 * the jiffies value might be older than the count (that is,
153 * the counter may underflow between the last point where
154 * jiffies was incremented and the point where we latch the
155 * count), it cannot be newer.
156 */
157 jifs = jiffies;
158 outb_p(0x00, PIT_MODE); /* latch the count ASAP */
159 count = inb_p(PIT_CH0); /* read the latched count */
160 count |= inb_p(PIT_CH0) << 8;
161
162 /* VIA686a test code... reset the latch if count > max + 1 */
163 if (count > LATCH) {
164 outb_p(0x34, PIT_MODE);
165 outb_p(LATCH & 0xff, PIT_CH0);
166 outb(LATCH >> 8, PIT_CH0);
167 count = LATCH - 1;
168 }
169
170 /*
171 * It's possible for count to appear to go the wrong way for a
172 * couple of reasons:
173 *
174 * 1. The timer counter underflows, but we haven't handled the
175 * resulting interrupt and incremented jiffies yet.
176 * 2. Hardware problem with the timer, not giving us continuous time,
177 * the counter does small "jumps" upwards on some Pentium systems,
178 * (see c't 95/10 page 335 for Neptun bug.)
179 *
180 * Previous attempts to handle these cases intelligently were
181 * buggy, so we just do the simple thing now.
182 */
183 if (count > old_count && jifs == old_jifs) {
184 count = old_count;
185 }
186 old_count = count;
187 old_jifs = jifs;
188
189 spin_unlock_irqrestore(&i8253_lock, flags);
190
191 count = (LATCH - 1) - count;
192
193 return (cycle_t)(jifs * LATCH) + count;
194}
195
196static struct clocksource clocksource_pit = {
197 .name = "pit",
198 .rating = 110,
199 .read = pit_read,
200 .mask = CLOCKSOURCE_MASK(32),
201 .mult = 0,
202 .shift = 20,
203};
204
205static int __init init_pit_clocksource(void)
206{
207 if (num_possible_cpus() > 1) /* PIT does not scale! */
208 return 0;
209
210 clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
211 return clocksource_register(&clocksource_pit);
212}
213arch_initcall(init_pit_clocksource);
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 3a2d255361bc..471013577108 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -30,8 +30,10 @@
30 30
31static int i8259A_auto_eoi = -1; 31static int i8259A_auto_eoi = -1;
32DEFINE_SPINLOCK(i8259A_lock); 32DEFINE_SPINLOCK(i8259A_lock);
33/* some platforms call this... */ 33static void disable_8259A_irq(unsigned int irq);
34void mask_and_ack_8259A(unsigned int); 34static void enable_8259A_irq(unsigned int irq);
35static void mask_and_ack_8259A(unsigned int irq);
36static void init_8259A(int auto_eoi);
35 37
36static struct irq_chip i8259A_chip = { 38static struct irq_chip i8259A_chip = {
37 .name = "XT-PIC", 39 .name = "XT-PIC",
@@ -39,6 +41,9 @@ static struct irq_chip i8259A_chip = {
39 .disable = disable_8259A_irq, 41 .disable = disable_8259A_irq,
40 .unmask = enable_8259A_irq, 42 .unmask = enable_8259A_irq,
41 .mask_ack = mask_and_ack_8259A, 43 .mask_ack = mask_and_ack_8259A,
44#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
45 .set_affinity = plat_set_irq_affinity,
46#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
42}; 47};
43 48
44/* 49/*
@@ -53,7 +58,7 @@ static unsigned int cached_irq_mask = 0xffff;
53#define cached_master_mask (cached_irq_mask) 58#define cached_master_mask (cached_irq_mask)
54#define cached_slave_mask (cached_irq_mask >> 8) 59#define cached_slave_mask (cached_irq_mask >> 8)
55 60
56void disable_8259A_irq(unsigned int irq) 61static void disable_8259A_irq(unsigned int irq)
57{ 62{
58 unsigned int mask; 63 unsigned int mask;
59 unsigned long flags; 64 unsigned long flags;
@@ -69,7 +74,7 @@ void disable_8259A_irq(unsigned int irq)
69 spin_unlock_irqrestore(&i8259A_lock, flags); 74 spin_unlock_irqrestore(&i8259A_lock, flags);
70} 75}
71 76
72void enable_8259A_irq(unsigned int irq) 77static void enable_8259A_irq(unsigned int irq)
73{ 78{
74 unsigned int mask; 79 unsigned int mask;
75 unsigned long flags; 80 unsigned long flags;
@@ -122,14 +127,14 @@ static inline int i8259A_irq_real(unsigned int irq)
122 int irqmask = 1 << irq; 127 int irqmask = 1 << irq;
123 128
124 if (irq < 8) { 129 if (irq < 8) {
125 outb(0x0B,PIC_MASTER_CMD); /* ISR register */ 130 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
126 value = inb(PIC_MASTER_CMD) & irqmask; 131 value = inb(PIC_MASTER_CMD) & irqmask;
127 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */ 132 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
128 return value; 133 return value;
129 } 134 }
130 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */ 135 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
131 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); 136 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
132 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */ 137 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
133 return value; 138 return value;
134} 139}
135 140
@@ -139,7 +144,7 @@ static inline int i8259A_irq_real(unsigned int irq)
139 * first, _then_ send the EOI, and the order of EOI 144 * first, _then_ send the EOI, and the order of EOI
140 * to the two 8259s is important! 145 * to the two 8259s is important!
141 */ 146 */
142void mask_and_ack_8259A(unsigned int irq) 147static void mask_and_ack_8259A(unsigned int irq)
143{ 148{
144 unsigned int irqmask; 149 unsigned int irqmask;
145 unsigned long flags; 150 unsigned long flags;
@@ -170,12 +175,12 @@ handle_real_irq:
170 if (irq & 8) { 175 if (irq & 8) {
171 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ 176 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
172 outb(cached_slave_mask, PIC_SLAVE_IMR); 177 outb(cached_slave_mask, PIC_SLAVE_IMR);
173 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ 178 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
174 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ 179 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
175 } else { 180 } else {
176 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 181 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
177 outb(cached_master_mask, PIC_MASTER_IMR); 182 outb(cached_master_mask, PIC_MASTER_IMR);
178 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ 183 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
179 } 184 }
180 smtc_im_ack_irq(irq); 185 smtc_im_ack_irq(irq);
181 spin_unlock_irqrestore(&i8259A_lock, flags); 186 spin_unlock_irqrestore(&i8259A_lock, flags);
@@ -253,7 +258,7 @@ static int __init i8259A_init_sysfs(void)
253 258
254device_initcall(i8259A_init_sysfs); 259device_initcall(i8259A_init_sysfs);
255 260
256void init_8259A(int auto_eoi) 261static void init_8259A(int auto_eoi)
257{ 262{
258 unsigned long flags; 263 unsigned long flags;
259 264
@@ -300,7 +305,9 @@ void init_8259A(int auto_eoi)
300 * IRQ2 is cascade interrupt to second interrupt controller 305 * IRQ2 is cascade interrupt to second interrupt controller
301 */ 306 */
302static struct irqaction irq2 = { 307static struct irqaction irq2 = {
303 no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL 308 .handler = no_action,
309 .mask = CPU_MASK_NONE,
310 .name = "cascade",
304}; 311};
305 312
306static struct resource pic1_io_resource = { 313static struct resource pic1_io_resource = {
@@ -322,7 +329,7 @@ static struct resource pic2_io_resource = {
322 * driver compatibility reasons interrupts 0 - 15 to be the i8259 329 * driver compatibility reasons interrupts 0 - 15 to be the i8259
323 * interrupts even if the hardware uses a different interrupt numbering. 330 * interrupts even if the hardware uses a different interrupt numbering.
324 */ 331 */
325void __init init_i8259_irqs (void) 332void __init init_i8259_irqs(void)
326{ 333{
327 int i; 334 int i;
328 335
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index 403d96f99e77..8ef5cf4cc423 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -203,8 +203,8 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
203 * Put the ELF interpreter info on the stack 203 * Put the ELF interpreter info on the stack
204 */ 204 */
205#define NEW_AUX_ENT(nr, id, val) \ 205#define NEW_AUX_ENT(nr, id, val) \
206 __put_user ((id), sp+(nr*2)); \ 206 __put_user((id), sp+(nr*2)); \
207 __put_user ((val), sp+(nr*2+1)); \ 207 __put_user((val), sp+(nr*2+1)); \
208 208
209 sp -= 2; 209 sp -= 2;
210 NEW_AUX_ENT(0, AT_NULL, 0); 210 NEW_AUX_ENT(0, AT_NULL, 0);
@@ -212,17 +212,17 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
212 if (exec) { 212 if (exec) {
213 sp -= 11*2; 213 sp -= 11*2;
214 214
215 NEW_AUX_ENT (0, AT_PHDR, load_addr + exec->e_phoff); 215 NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff);
216 NEW_AUX_ENT (1, AT_PHENT, sizeof (struct elf_phdr)); 216 NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr));
217 NEW_AUX_ENT (2, AT_PHNUM, exec->e_phnum); 217 NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum);
218 NEW_AUX_ENT (3, AT_PAGESZ, ELF_EXEC_PAGESIZE); 218 NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE);
219 NEW_AUX_ENT (4, AT_BASE, interp_load_addr); 219 NEW_AUX_ENT(4, AT_BASE, interp_load_addr);
220 NEW_AUX_ENT (5, AT_FLAGS, 0); 220 NEW_AUX_ENT(5, AT_FLAGS, 0);
221 NEW_AUX_ENT (6, AT_ENTRY, (elf_addr_t) exec->e_entry); 221 NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry);
222 NEW_AUX_ENT (7, AT_UID, (elf_addr_t) current->uid); 222 NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid);
223 NEW_AUX_ENT (8, AT_EUID, (elf_addr_t) current->euid); 223 NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid);
224 NEW_AUX_ENT (9, AT_GID, (elf_addr_t) current->gid); 224 NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid);
225 NEW_AUX_ENT (10, AT_EGID, (elf_addr_t) current->egid); 225 NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid);
226 } 226 }
227#undef NEW_AUX_ENT 227#undef NEW_AUX_ENT
228 228
@@ -231,16 +231,16 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
231 sp -= argc+1; 231 sp -= argc+1;
232 argv = sp; 232 argv = sp;
233 233
234 __put_user((elf_addr_t)argc,--sp); 234 __put_user((elf_addr_t)argc, --sp);
235 current->mm->arg_start = (unsigned long) p; 235 current->mm->arg_start = (unsigned long) p;
236 while (argc-->0) { 236 while (argc-->0) {
237 __put_user((unsigned long)p,argv++); 237 __put_user((unsigned long)p, argv++);
238 p += strlen_user(p); 238 p += strlen_user(p);
239 } 239 }
240 __put_user((unsigned long) NULL, argv); 240 __put_user((unsigned long) NULL, argv);
241 current->mm->arg_end = current->mm->env_start = (unsigned long) p; 241 current->mm->arg_end = current->mm->env_start = (unsigned long) p;
242 while (envc-->0) { 242 while (envc-->0) {
243 __put_user((unsigned long)p,envp++); 243 __put_user((unsigned long)p, envp++);
244 p += strlen_user(p); 244 p += strlen_user(p);
245 } 245 }
246 __put_user((unsigned long) NULL, envp); 246 __put_user((unsigned long) NULL, envp);
@@ -581,7 +581,7 @@ static void irix_map_prda_page(void)
581 struct prda *pp; 581 struct prda *pp;
582 582
583 down_write(&current->mm->mmap_sem); 583 down_write(&current->mm->mmap_sem);
584 v = do_brk (PRDA_ADDRESS, PAGE_SIZE); 584 v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
585 up_write(&current->mm->mmap_sem); 585 up_write(&current->mm->mmap_sem);
586 586
587 if (v < 0) 587 if (v < 0)
@@ -815,7 +815,7 @@ out_free_interp:
815 kfree(elf_interpreter); 815 kfree(elf_interpreter);
816out_free_file: 816out_free_file:
817out_free_ph: 817out_free_ph:
818 kfree (elf_phdata); 818 kfree(elf_phdata);
819 goto out; 819 goto out;
820} 820}
821 821
@@ -831,7 +831,7 @@ static int load_irix_library(struct file *file)
831 int retval; 831 int retval;
832 unsigned int bss; 832 unsigned int bss;
833 int error; 833 int error;
834 int i,j, k; 834 int i, j, k;
835 835
836 error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex)); 836 error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex));
837 if (error != sizeof(elf_ex)) 837 if (error != sizeof(elf_ex))
@@ -1232,7 +1232,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1232 strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname)); 1232 strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname));
1233 1233
1234 /* Try to dump the FPU. */ 1234 /* Try to dump the FPU. */
1235 prstatus.pr_fpvalid = dump_fpu (regs, &fpu); 1235 prstatus.pr_fpvalid = dump_fpu(regs, &fpu);
1236 if (!prstatus.pr_fpvalid) { 1236 if (!prstatus.pr_fpvalid) {
1237 numnote--; 1237 numnote--;
1238 } else { 1238 } else {
diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c
index de8584f62311..cf2dcd3d6a93 100644
--- a/arch/mips/kernel/irixinv.c
+++ b/arch/mips/kernel/irixinv.c
@@ -14,7 +14,7 @@ int inventory_items = 0;
14 14
15static inventory_t inventory [MAX_INVENTORY]; 15static inventory_t inventory [MAX_INVENTORY];
16 16
17void add_to_inventory (int class, int type, int controller, int unit, int state) 17void add_to_inventory(int class, int type, int controller, int unit, int state)
18{ 18{
19 inventory_t *ni = &inventory [inventory_items]; 19 inventory_t *ni = &inventory [inventory_items];
20 20
@@ -30,7 +30,7 @@ void add_to_inventory (int class, int type, int controller, int unit, int state)
30 inventory_items++; 30 inventory_items++;
31} 31}
32 32
33int dump_inventory_to_user (void __user *userbuf, int size) 33int dump_inventory_to_user(void __user *userbuf, int size)
34{ 34{
35 inventory_t *inv = &inventory [0]; 35 inventory_t *inv = &inventory [0];
36 inventory_t __user *user = userbuf; 36 inventory_t __user *user = userbuf;
@@ -45,7 +45,7 @@ int dump_inventory_to_user (void __user *userbuf, int size)
45 return -EFAULT; 45 return -EFAULT;
46 user++; 46 user++;
47 } 47 }
48 return inventory_items * sizeof (inventory_t); 48 return inventory_items * sizeof(inventory_t);
49} 49}
50 50
51int __init init_inventory(void) 51int __init init_inventory(void)
@@ -55,24 +55,24 @@ int __init init_inventory(void)
55 * most likely this will not let just anyone run the X server 55 * most likely this will not let just anyone run the X server
56 * until we put the right values all over the place 56 * until we put the right values all over the place
57 */ 57 */
58 add_to_inventory (10, 3, 0, 0, 16400); 58 add_to_inventory(10, 3, 0, 0, 16400);
59 add_to_inventory (1, 1, 150, -1, 12); 59 add_to_inventory(1, 1, 150, -1, 12);
60 add_to_inventory (1, 3, 0, 0, 8976); 60 add_to_inventory(1, 3, 0, 0, 8976);
61 add_to_inventory (1, 2, 0, 0, 8976); 61 add_to_inventory(1, 2, 0, 0, 8976);
62 add_to_inventory (4, 8, 0, 0, 2); 62 add_to_inventory(4, 8, 0, 0, 2);
63 add_to_inventory (5, 5, 0, 0, 1); 63 add_to_inventory(5, 5, 0, 0, 1);
64 add_to_inventory (3, 3, 0, 0, 32768); 64 add_to_inventory(3, 3, 0, 0, 32768);
65 add_to_inventory (3, 4, 0, 0, 32768); 65 add_to_inventory(3, 4, 0, 0, 32768);
66 add_to_inventory (3, 8, 0, 0, 524288); 66 add_to_inventory(3, 8, 0, 0, 524288);
67 add_to_inventory (3, 9, 0, 0, 64); 67 add_to_inventory(3, 9, 0, 0, 64);
68 add_to_inventory (3, 1, 0, 0, 67108864); 68 add_to_inventory(3, 1, 0, 0, 67108864);
69 add_to_inventory (12, 3, 0, 0, 16); 69 add_to_inventory(12, 3, 0, 0, 16);
70 add_to_inventory (8, 7, 17, 0, 16777472); 70 add_to_inventory(8, 7, 17, 0, 16777472);
71 add_to_inventory (8, 0, 0, 0, 1); 71 add_to_inventory(8, 0, 0, 0, 1);
72 add_to_inventory (2, 1, 0, 13, 2); 72 add_to_inventory(2, 1, 0, 13, 2);
73 add_to_inventory (2, 2, 0, 2, 0); 73 add_to_inventory(2, 2, 0, 2, 0);
74 add_to_inventory (2, 2, 0, 1, 0); 74 add_to_inventory(2, 2, 0, 1, 0);
75 add_to_inventory (7, 14, 0, 0, 6); 75 add_to_inventory(7, 14, 0, 0, 6);
76 76
77 return 0; 77 return 0;
78} 78}
diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c
index 30f9eb09db3f..2bde200d5ad0 100644
--- a/arch/mips/kernel/irixioctl.c
+++ b/arch/mips/kernel/irixioctl.c
@@ -238,7 +238,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
238 current->comm, current->pid, cmd); 238 current->comm, current->pid, cmd);
239 do_exit(255); 239 do_exit(255);
240#else 240#else
241 error = sys_ioctl (fd, cmd, arg); 241 error = sys_ioctl(fd, cmd, arg);
242#endif 242#endif
243 } 243 }
244 244
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 28b2a8f00911..85c2e389edd6 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -163,9 +163,9 @@ static inline int handle_signal(unsigned long sig, siginfo_t *info,
163 ret = setup_irix_frame(ka, regs, sig, oldset); 163 ret = setup_irix_frame(ka, regs, sig, oldset);
164 164
165 spin_lock_irq(&current->sighand->siglock); 165 spin_lock_irq(&current->sighand->siglock);
166 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 166 sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
167 if (!(ka->sa.sa_flags & SA_NODEFER)) 167 if (!(ka->sa.sa_flags & SA_NODEFER))
168 sigaddset(&current->blocked,sig); 168 sigaddset(&current->blocked, sig);
169 recalc_sigpending(); 169 recalc_sigpending();
170 spin_unlock_irq(&current->sighand->siglock); 170 spin_unlock_irq(&current->sighand->siglock);
171 171
@@ -605,8 +605,8 @@ repeat:
605 current->state = TASK_INTERRUPTIBLE; 605 current->state = TASK_INTERRUPTIBLE;
606 read_lock(&tasklist_lock); 606 read_lock(&tasklist_lock);
607 tsk = current; 607 tsk = current;
608 list_for_each(_p,&tsk->children) { 608 list_for_each(_p, &tsk->children) {
609 p = list_entry(_p,struct task_struct,sibling); 609 p = list_entry(_p, struct task_struct, sibling);
610 if ((type == IRIX_P_PID) && p->pid != pid) 610 if ((type == IRIX_P_PID) && p->pid != pid)
611 continue; 611 continue;
612 if ((type == IRIX_P_PGID) && process_group(p) != pid) 612 if ((type == IRIX_P_PGID) && process_group(p) != pid)
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
new file mode 100644
index 000000000000..1b81b131f43c
--- /dev/null
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -0,0 +1,131 @@
1/*
2 * GT641xx IRQ routines.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/hardirq.h>
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/spinlock.h>
24#include <linux/types.h>
25
26#include <asm/gt64120.h>
27
28#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
29
30static DEFINE_SPINLOCK(gt641xx_irq_lock);
31
32static void ack_gt641xx_irq(unsigned int irq)
33{
34 unsigned long flags;
35 u32 cause;
36
37 spin_lock_irqsave(&gt641xx_irq_lock, flags);
38 cause = GT_READ(GT_INTRCAUSE_OFS);
39 cause &= ~GT641XX_IRQ_TO_BIT(irq);
40 GT_WRITE(GT_INTRCAUSE_OFS, cause);
41 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
42}
43
44static void mask_gt641xx_irq(unsigned int irq)
45{
46 unsigned long flags;
47 u32 mask;
48
49 spin_lock_irqsave(&gt641xx_irq_lock, flags);
50 mask = GT_READ(GT_INTRMASK_OFS);
51 mask &= ~GT641XX_IRQ_TO_BIT(irq);
52 GT_WRITE(GT_INTRMASK_OFS, mask);
53 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
54}
55
56static void mask_ack_gt641xx_irq(unsigned int irq)
57{
58 unsigned long flags;
59 u32 cause, mask;
60
61 spin_lock_irqsave(&gt641xx_irq_lock, flags);
62 mask = GT_READ(GT_INTRMASK_OFS);
63 mask &= ~GT641XX_IRQ_TO_BIT(irq);
64 GT_WRITE(GT_INTRMASK_OFS, mask);
65
66 cause = GT_READ(GT_INTRCAUSE_OFS);
67 cause &= ~GT641XX_IRQ_TO_BIT(irq);
68 GT_WRITE(GT_INTRCAUSE_OFS, cause);
69 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
70}
71
72static void unmask_gt641xx_irq(unsigned int irq)
73{
74 unsigned long flags;
75 u32 mask;
76
77 spin_lock_irqsave(&gt641xx_irq_lock, flags);
78 mask = GT_READ(GT_INTRMASK_OFS);
79 mask |= GT641XX_IRQ_TO_BIT(irq);
80 GT_WRITE(GT_INTRMASK_OFS, mask);
81 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
82}
83
84static struct irq_chip gt641xx_irq_chip = {
85 .name = "GT641xx",
86 .ack = ack_gt641xx_irq,
87 .mask = mask_gt641xx_irq,
88 .mask_ack = mask_ack_gt641xx_irq,
89 .unmask = unmask_gt641xx_irq,
90};
91
92void gt641xx_irq_dispatch(void)
93{
94 u32 cause, mask;
95 int i;
96
97 cause = GT_READ(GT_INTRCAUSE_OFS);
98 mask = GT_READ(GT_INTRMASK_OFS);
99 cause &= mask;
100
101 /*
102 * bit0 : logical or of all the interrupt bits.
103 * bit30: logical or of bits[29:26,20:1].
104 * bit31: logical or of bits[25:1].
105 */
106 for (i = 1; i < 30; i++) {
107 if (cause & (1U << i)) {
108 do_IRQ(GT641XX_IRQ_BASE + i);
109 return;
110 }
111 }
112
113 atomic_inc(&irq_err_count);
114}
115
116void __init gt641xx_irq_init(void)
117{
118 int i;
119
120 GT_WRITE(GT_INTRMASK_OFS, 0);
121 GT_WRITE(GT_INTRCAUSE_OFS, 0);
122
123 /*
124 * bit0 : logical or of all the interrupt bits.
125 * bit30: logical or of bits[29:26,20:1].
126 * bit31: logical or of bits[25:1].
127 */
128 for (i = 1; i < 30; i++)
129 set_irq_chip_and_handler(GT641XX_IRQ_BASE + i,
130 &gt641xx_irq_chip, handle_level_irq);
131}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 1ecdd50bfc60..4edc7e451d91 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -99,7 +99,7 @@ void ll_msc_irq(void)
99} 99}
100 100
101void 101void
102msc_bind_eic_interrupt (unsigned int irq, unsigned int set) 102msc_bind_eic_interrupt(unsigned int irq, unsigned int set)
103{ 103{
104 MSCIC_WRITE(MSC01_IC_RAMW, 104 MSCIC_WRITE(MSC01_IC_RAMW,
105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
@@ -130,7 +130,7 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
130{ 130{
131 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); 131 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
132 132
133 _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); 133 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
134 134
135 /* Reset interrupt controller - initialises all registers to 0 */ 135 /* Reset interrupt controller - initialises all registers to 0 */
136 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); 136 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a990aad2f049..d06e9c9af790 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -93,7 +93,7 @@ int show_interrupts(struct seq_file *p, void *v)
93 if (i == 0) { 93 if (i == 0) {
94 seq_printf(p, " "); 94 seq_printf(p, " ");
95 for_each_online_cpu(j) 95 for_each_online_cpu(j)
96 seq_printf(p, "CPU%d ",j); 96 seq_printf(p, "CPU%d ", j);
97 seq_putc(p, '\n'); 97 seq_putc(p, '\n');
98 } 98 }
99 99
@@ -102,7 +102,7 @@ int show_interrupts(struct seq_file *p, void *v)
102 action = irq_desc[i].action; 102 action = irq_desc[i].action;
103 if (!action) 103 if (!action)
104 goto skip; 104 goto skip;
105 seq_printf(p, "%3d: ",i); 105 seq_printf(p, "%3d: ", i);
106#ifndef CONFIG_SMP 106#ifndef CONFIG_SMP
107 seq_printf(p, "%10u ", kstat_irqs(i)); 107 seq_printf(p, "%10u ", kstat_irqs(i));
108#else 108#else
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index cb9a14a1ca5b..d2c2e00e5864 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -118,11 +118,11 @@ struct apsp_table syscall_command_table[] = {
118 118
119static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3) 119static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3)
120{ 120{
121 register long int _num __asm__ ("$2") = num; 121 register long int _num __asm__("$2") = num;
122 register long int _arg0 __asm__ ("$4") = arg0; 122 register long int _arg0 __asm__("$4") = arg0;
123 register long int _arg1 __asm__ ("$5") = arg1; 123 register long int _arg1 __asm__("$5") = arg1;
124 register long int _arg2 __asm__ ("$6") = arg2; 124 register long int _arg2 __asm__("$6") = arg2;
125 register long int _arg3 __asm__ ("$7") = arg3; 125 register long int _arg3 __asm__("$7") = arg3;
126 126
127 mm_segment_t old_fs; 127 mm_segment_t old_fs;
128 128
@@ -239,7 +239,7 @@ void sp_work_handle_request(void)
239 case MTSP_SYSCALL_GETTOD: 239 case MTSP_SYSCALL_GETTOD:
240 memset(&tz, 0, sizeof(tz)); 240 memset(&tz, 0, sizeof(tz));
241 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv, 241 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
242 (int)&tz, 0,0)) == 0) 242 (int)&tz, 0, 0)) == 0)
243 ret.retval = tv.tv_sec; 243 ret.retval = tv.tv_sec;
244 break; 244 break;
245 245
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 135d9a5fe337..d6e01215fb2b 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -58,10 +58,10 @@
58#define AA(__x) ((unsigned long)((int)__x)) 58#define AA(__x) ((unsigned long)((int)__x))
59 59
60#ifdef __MIPSEB__ 60#ifdef __MIPSEB__
61#define merge_64(r1,r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL)) 61#define merge_64(r1, r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL))
62#endif 62#endif
63#ifdef __MIPSEL__ 63#ifdef __MIPSEL__
64#define merge_64(r1,r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) 64#define merge_64(r1, r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL))
65#endif 65#endif
66 66
67/* 67/*
@@ -96,7 +96,7 @@ int cp_compat_stat(struct kstat *stat, struct compat_stat __user *statbuf)
96#endif 96#endif
97 tmp.st_blocks = stat->blocks; 97 tmp.st_blocks = stat->blocks;
98 tmp.st_blksize = stat->blksize; 98 tmp.st_blksize = stat->blksize;
99 return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; 99 return copy_to_user(statbuf, &tmp, sizeof(tmp)) ? -EFAULT : 0;
100} 100}
101 101
102asmlinkage unsigned long 102asmlinkage unsigned long
@@ -300,13 +300,13 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
300{ 300{
301 struct timespec t; 301 struct timespec t;
302 int ret; 302 int ret;
303 mm_segment_t old_fs = get_fs (); 303 mm_segment_t old_fs = get_fs();
304 304
305 set_fs (KERNEL_DS); 305 set_fs(KERNEL_DS);
306 ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t); 306 ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t);
307 set_fs (old_fs); 307 set_fs(old_fs);
308 if (put_user (t.tv_sec, &interval->tv_sec) || 308 if (put_user (t.tv_sec, &interval->tv_sec) ||
309 __put_user (t.tv_nsec, &interval->tv_nsec)) 309 __put_user(t.tv_nsec, &interval->tv_nsec))
310 return -EFAULT; 310 return -EFAULT;
311 return ret; 311 return ret;
312} 312}
@@ -314,7 +314,7 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
314#ifdef CONFIG_SYSVIPC 314#ifdef CONFIG_SYSVIPC
315 315
316asmlinkage long 316asmlinkage long
317sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 317sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
318{ 318{
319 int version, err; 319 int version, err;
320 320
@@ -373,7 +373,7 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
373#else 373#else
374 374
375asmlinkage long 375asmlinkage long
376sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 376sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
377{ 377{
378 return -ENOSYS; 378 return -ENOSYS;
379} 379}
@@ -505,16 +505,16 @@ asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32)
505 505
506 set_fs(KERNEL_DS); 506 set_fs(KERNEL_DS);
507 err = sys_ustat(dev, (struct ustat __user *)&tmp); 507 err = sys_ustat(dev, (struct ustat __user *)&tmp);
508 set_fs (old_fs); 508 set_fs(old_fs);
509 509
510 if (err) 510 if (err)
511 goto out; 511 goto out;
512 512
513 memset(&tmp32,0,sizeof(struct ustat32)); 513 memset(&tmp32, 0, sizeof(struct ustat32));
514 tmp32.f_tfree = tmp.f_tfree; 514 tmp32.f_tfree = tmp.f_tfree;
515 tmp32.f_tinode = tmp.f_tinode; 515 tmp32.f_tinode = tmp.f_tinode;
516 516
517 err = copy_to_user(ubuf32,&tmp32,sizeof(struct ustat32)) ? -EFAULT : 0; 517 err = copy_to_user(ubuf32, &tmp32, sizeof(struct ustat32)) ? -EFAULT : 0;
518 518
519out: 519out:
520 return err; 520 return err;
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index 56750b02ab40..3d6b1ec1f328 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -236,7 +236,7 @@ void mips_mt_set_cpuoptions(void)
236 if (oconfig7 != nconfig7) { 236 if (oconfig7 != nconfig7) {
237 __asm__ __volatile("sync"); 237 __asm__ __volatile("sync");
238 write_c0_config7(nconfig7); 238 write_c0_config7(nconfig7);
239 ehb (); 239 ehb();
240 printk("Config7: 0x%08x\n", read_c0_config7()); 240 printk("Config7: 0x%08x\n", read_c0_config7());
241 } 241 }
242 242
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index ec04f5a1a5ea..efd2d1314123 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -17,76 +17,6 @@
17 17
18unsigned int vced_count, vcei_count; 18unsigned int vced_count, vcei_count;
19 19
20static const char *cpu_name[] = {
21 [CPU_UNKNOWN] = "unknown",
22 [CPU_R2000] = "R2000",
23 [CPU_R3000] = "R3000",
24 [CPU_R3000A] = "R3000A",
25 [CPU_R3041] = "R3041",
26 [CPU_R3051] = "R3051",
27 [CPU_R3052] = "R3052",
28 [CPU_R3081] = "R3081",
29 [CPU_R3081E] = "R3081E",
30 [CPU_R4000PC] = "R4000PC",
31 [CPU_R4000SC] = "R4000SC",
32 [CPU_R4000MC] = "R4000MC",
33 [CPU_R4200] = "R4200",
34 [CPU_R4400PC] = "R4400PC",
35 [CPU_R4400SC] = "R4400SC",
36 [CPU_R4400MC] = "R4400MC",
37 [CPU_R4600] = "R4600",
38 [CPU_R6000] = "R6000",
39 [CPU_R6000A] = "R6000A",
40 [CPU_R8000] = "R8000",
41 [CPU_R10000] = "R10000",
42 [CPU_R12000] = "R12000",
43 [CPU_R14000] = "R14000",
44 [CPU_R4300] = "R4300",
45 [CPU_R4650] = "R4650",
46 [CPU_R4700] = "R4700",
47 [CPU_R5000] = "R5000",
48 [CPU_R5000A] = "R5000A",
49 [CPU_R4640] = "R4640",
50 [CPU_NEVADA] = "Nevada",
51 [CPU_RM7000] = "RM7000",
52 [CPU_RM9000] = "RM9000",
53 [CPU_R5432] = "R5432",
54 [CPU_4KC] = "MIPS 4Kc",
55 [CPU_5KC] = "MIPS 5Kc",
56 [CPU_R4310] = "R4310",
57 [CPU_SB1] = "SiByte SB1",
58 [CPU_SB1A] = "SiByte SB1A",
59 [CPU_TX3912] = "TX3912",
60 [CPU_TX3922] = "TX3922",
61 [CPU_TX3927] = "TX3927",
62 [CPU_AU1000] = "Au1000",
63 [CPU_AU1500] = "Au1500",
64 [CPU_AU1100] = "Au1100",
65 [CPU_AU1550] = "Au1550",
66 [CPU_AU1200] = "Au1200",
67 [CPU_4KEC] = "MIPS 4KEc",
68 [CPU_4KSC] = "MIPS 4KSc",
69 [CPU_VR41XX] = "NEC Vr41xx",
70 [CPU_R5500] = "R5500",
71 [CPU_TX49XX] = "TX49xx",
72 [CPU_20KC] = "MIPS 20Kc",
73 [CPU_24K] = "MIPS 24K",
74 [CPU_25KF] = "MIPS 25Kf",
75 [CPU_34K] = "MIPS 34K",
76 [CPU_74K] = "MIPS 74K",
77 [CPU_VR4111] = "NEC VR4111",
78 [CPU_VR4121] = "NEC VR4121",
79 [CPU_VR4122] = "NEC VR4122",
80 [CPU_VR4131] = "NEC VR4131",
81 [CPU_VR4133] = "NEC VR4133",
82 [CPU_VR4181] = "NEC VR4181",
83 [CPU_VR4181A] = "NEC VR4181A",
84 [CPU_SR71000] = "Sandcraft SR71000",
85 [CPU_PR4450] = "Philips PR4450",
86 [CPU_LOONGSON2] = "ICT Loongson-2",
87};
88
89
90static int show_cpuinfo(struct seq_file *m, void *v) 20static int show_cpuinfo(struct seq_file *m, void *v)
91{ 21{
92 unsigned long n = (unsigned long) v - 1; 22 unsigned long n = (unsigned long) v - 1;
@@ -108,8 +38,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
108 seq_printf(m, "processor\t\t: %ld\n", n); 38 seq_printf(m, "processor\t\t: %ld\n", n);
109 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", 39 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
110 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); 40 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
111 seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? 41 seq_printf(m, fmt, __cpu_name[smp_processor_id()],
112 cpu_data[n].cputype : CPU_UNKNOWN],
113 (version >> 4) & 0x0f, version & 0x0f, 42 (version >> 4) & 0x0f, version & 0x0f,
114 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 43 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
115 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", 44 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index e6ce943099a0..11cb264f59ce 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -11,6 +11,7 @@
11#include <linux/errno.h> 11#include <linux/errno.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/sched.h> 13#include <linux/sched.h>
14#include <linux/tick.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15#include <linux/mm.h> 16#include <linux/mm.h>
16#include <linux/stddef.h> 17#include <linux/stddef.h>
@@ -52,6 +53,7 @@ void __noreturn cpu_idle(void)
52{ 53{
53 /* endless idle loop with no priority at all */ 54 /* endless idle loop with no priority at all */
54 while (1) { 55 while (1) {
56 tick_nohz_stop_sched_tick();
55 while (!need_resched()) { 57 while (!need_resched()) {
56#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 58#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
57 extern void smtc_idle_loop_hook(void); 59 extern void smtc_idle_loop_hook(void);
@@ -61,6 +63,7 @@ void __noreturn cpu_idle(void)
61 if (cpu_wait) 63 if (cpu_wait)
62 (*cpu_wait)(); 64 (*cpu_wait)();
63 } 65 }
66 tick_nohz_restart_sched_tick();
64 preempt_enable_no_resched(); 67 preempt_enable_no_resched();
65 schedule(); 68 schedule();
66 preempt_disable(); 69 preempt_disable();
@@ -199,13 +202,13 @@ void elf_dump_regs(elf_greg_t *gp, struct pt_regs *regs)
199#endif 202#endif
200} 203}
201 204
202int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs) 205int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
203{ 206{
204 elf_dump_regs(*regs, task_pt_regs(tsk)); 207 elf_dump_regs(*regs, task_pt_regs(tsk));
205 return 1; 208 return 1;
206} 209}
207 210
208int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) 211int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
209{ 212{
210 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); 213 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu));
211 214
@@ -231,8 +234,8 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
231 regs.cp0_epc = (unsigned long) kernel_thread_helper; 234 regs.cp0_epc = (unsigned long) kernel_thread_helper;
232 regs.cp0_status = read_c0_status(); 235 regs.cp0_status = read_c0_status();
233#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 236#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
234 regs.cp0_status &= ~(ST0_KUP | ST0_IEC); 237 regs.cp0_status = (regs.cp0_status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
235 regs.cp0_status |= ST0_IEP; 238 ((regs.cp0_status & (ST0_KUC | ST0_IEC)) << 2);
236#else 239#else
237 regs.cp0_status |= ST0_EXL; 240 regs.cp0_status |= ST0_EXL;
238#endif 241#endif
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index bbd57b20b43e..58aa6fec1146 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -54,7 +54,7 @@ void ptrace_disable(struct task_struct *child)
54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. 54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
55 * Registers are sign extended to fill the available space. 55 * Registers are sign extended to fill the available space.
56 */ 56 */
57int ptrace_getregs (struct task_struct *child, __s64 __user *data) 57int ptrace_getregs(struct task_struct *child, __s64 __user *data)
58{ 58{
59 struct pt_regs *regs; 59 struct pt_regs *regs;
60 int i; 60 int i;
@@ -65,13 +65,13 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data)
65 regs = task_pt_regs(child); 65 regs = task_pt_regs(child);
66 66
67 for (i = 0; i < 32; i++) 67 for (i = 0; i < 32; i++)
68 __put_user (regs->regs[i], data + i); 68 __put_user(regs->regs[i], data + i);
69 __put_user (regs->lo, data + EF_LO - EF_R0); 69 __put_user(regs->lo, data + EF_LO - EF_R0);
70 __put_user (regs->hi, data + EF_HI - EF_R0); 70 __put_user(regs->hi, data + EF_HI - EF_R0);
71 __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 71 __put_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
72 __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); 72 __put_user(regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
73 __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0); 73 __put_user(regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
74 __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); 74 __put_user(regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
75 75
76 return 0; 76 return 0;
77} 77}
@@ -81,7 +81,7 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data)
81 * the 64-bit format. On a 32-bit kernel only the lower order half 81 * the 64-bit format. On a 32-bit kernel only the lower order half
82 * (according to endianness) will be used. 82 * (according to endianness) will be used.
83 */ 83 */
84int ptrace_setregs (struct task_struct *child, __s64 __user *data) 84int ptrace_setregs(struct task_struct *child, __s64 __user *data)
85{ 85{
86 struct pt_regs *regs; 86 struct pt_regs *regs;
87 int i; 87 int i;
@@ -92,17 +92,17 @@ int ptrace_setregs (struct task_struct *child, __s64 __user *data)
92 regs = task_pt_regs(child); 92 regs = task_pt_regs(child);
93 93
94 for (i = 0; i < 32; i++) 94 for (i = 0; i < 32; i++)
95 __get_user (regs->regs[i], data + i); 95 __get_user(regs->regs[i], data + i);
96 __get_user (regs->lo, data + EF_LO - EF_R0); 96 __get_user(regs->lo, data + EF_LO - EF_R0);
97 __get_user (regs->hi, data + EF_HI - EF_R0); 97 __get_user(regs->hi, data + EF_HI - EF_R0);
98 __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 98 __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
99 99
100 /* badvaddr, status, and cause may not be written. */ 100 /* badvaddr, status, and cause may not be written. */
101 101
102 return 0; 102 return 0;
103} 103}
104 104
105int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) 105int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
106{ 106{
107 int i; 107 int i;
108 unsigned int tmp; 108 unsigned int tmp;
@@ -113,13 +113,13 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
113 if (tsk_used_math(child)) { 113 if (tsk_used_math(child)) {
114 fpureg_t *fregs = get_fpu_regs(child); 114 fpureg_t *fregs = get_fpu_regs(child);
115 for (i = 0; i < 32; i++) 115 for (i = 0; i < 32; i++)
116 __put_user (fregs[i], i + (__u64 __user *) data); 116 __put_user(fregs[i], i + (__u64 __user *) data);
117 } else { 117 } else {
118 for (i = 0; i < 32; i++) 118 for (i = 0; i < 32; i++)
119 __put_user ((__u64) -1, i + (__u64 __user *) data); 119 __put_user((__u64) -1, i + (__u64 __user *) data);
120 } 120 }
121 121
122 __put_user (child->thread.fpu.fcr31, data + 64); 122 __put_user(child->thread.fpu.fcr31, data + 64);
123 123
124 preempt_disable(); 124 preempt_disable();
125 if (cpu_has_fpu) { 125 if (cpu_has_fpu) {
@@ -142,12 +142,12 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
142 tmp = 0; 142 tmp = 0;
143 } 143 }
144 preempt_enable(); 144 preempt_enable();
145 __put_user (tmp, data + 65); 145 __put_user(tmp, data + 65);
146 146
147 return 0; 147 return 0;
148} 148}
149 149
150int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) 150int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
151{ 151{
152 fpureg_t *fregs; 152 fpureg_t *fregs;
153 int i; 153 int i;
@@ -158,9 +158,9 @@ int ptrace_setfpregs (struct task_struct *child, __u32 __user *data)
158 fregs = get_fpu_regs(child); 158 fregs = get_fpu_regs(child);
159 159
160 for (i = 0; i < 32; i++) 160 for (i = 0; i < 32; i++)
161 __get_user (fregs[i], i + (__u64 __user *) data); 161 __get_user(fregs[i], i + (__u64 __user *) data);
162 162
163 __get_user (child->thread.fpu.fcr31, data + 64); 163 __get_user(child->thread.fpu.fcr31, data + 64);
164 164
165 /* FIR may not be written. */ 165 /* FIR may not be written. */
166 166
@@ -390,19 +390,19 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
390 } 390 }
391 391
392 case PTRACE_GETREGS: 392 case PTRACE_GETREGS:
393 ret = ptrace_getregs (child, (__u64 __user *) data); 393 ret = ptrace_getregs(child, (__u64 __user *) data);
394 break; 394 break;
395 395
396 case PTRACE_SETREGS: 396 case PTRACE_SETREGS:
397 ret = ptrace_setregs (child, (__u64 __user *) data); 397 ret = ptrace_setregs(child, (__u64 __user *) data);
398 break; 398 break;
399 399
400 case PTRACE_GETFPREGS: 400 case PTRACE_GETFPREGS:
401 ret = ptrace_getfpregs (child, (__u32 __user *) data); 401 ret = ptrace_getfpregs(child, (__u32 __user *) data);
402 break; 402 break;
403 403
404 case PTRACE_SETFPREGS: 404 case PTRACE_SETFPREGS:
405 ret = ptrace_setfpregs (child, (__u32 __user *) data); 405 ret = ptrace_setfpregs(child, (__u32 __user *) data);
406 break; 406 break;
407 407
408 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 408 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index d9a39c169450..f2bffed94fa3 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -36,11 +36,11 @@
36#include <asm/uaccess.h> 36#include <asm/uaccess.h>
37#include <asm/bootinfo.h> 37#include <asm/bootinfo.h>
38 38
39int ptrace_getregs (struct task_struct *child, __s64 __user *data); 39int ptrace_getregs(struct task_struct *child, __s64 __user *data);
40int ptrace_setregs (struct task_struct *child, __s64 __user *data); 40int ptrace_setregs(struct task_struct *child, __s64 __user *data);
41 41
42int ptrace_getfpregs (struct task_struct *child, __u32 __user *data); 42int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
43int ptrace_setfpregs (struct task_struct *child, __u32 __user *data); 43int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
44 44
45/* 45/*
46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not 46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
@@ -346,19 +346,19 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
346 } 346 }
347 347
348 case PTRACE_GETREGS: 348 case PTRACE_GETREGS:
349 ret = ptrace_getregs (child, (__u64 __user *) (__u64) data); 349 ret = ptrace_getregs(child, (__u64 __user *) (__u64) data);
350 break; 350 break;
351 351
352 case PTRACE_SETREGS: 352 case PTRACE_SETREGS:
353 ret = ptrace_setregs (child, (__u64 __user *) (__u64) data); 353 ret = ptrace_setregs(child, (__u64 __user *) (__u64) data);
354 break; 354 break;
355 355
356 case PTRACE_GETFPREGS: 356 case PTRACE_GETFPREGS:
357 ret = ptrace_getfpregs (child, (__u32 __user *) (__u64) data); 357 ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
358 break; 358 break;
359 359
360 case PTRACE_SETFPREGS: 360 case PTRACE_SETFPREGS:
361 ret = ptrace_setfpregs (child, (__u32 __user *) (__u64) data); 361 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
362 break; 362 break;
363 363
364 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 364 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 316685fca059..a06a27d6cfcd 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -51,10 +51,8 @@ EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS);
51 * These are initialized so they are in the .data section 51 * These are initialized so they are in the .data section
52 */ 52 */
53unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; 53unsigned long mips_machtype __read_mostly = MACH_UNKNOWN;
54unsigned long mips_machgroup __read_mostly = MACH_GROUP_UNKNOWN;
55 54
56EXPORT_SYMBOL(mips_machtype); 55EXPORT_SYMBOL(mips_machtype);
57EXPORT_SYMBOL(mips_machgroup);
58 56
59struct boot_mem_map boot_mem_map; 57struct boot_mem_map boot_mem_map;
60 58
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 2a08ce41bf2b..a4e106c56ab5 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -613,9 +613,9 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
613 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); 613 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset);
614 614
615 spin_lock_irq(&current->sighand->siglock); 615 spin_lock_irq(&current->sighand->siglock);
616 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 616 sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
617 if (!(ka->sa.sa_flags & SA_NODEFER)) 617 if (!(ka->sa.sa_flags & SA_NODEFER))
618 sigaddset(&current->blocked,sig); 618 sigaddset(&current->blocked, sig);
619 recalc_sigpending(); 619 recalc_sigpending();
620 spin_unlock_irq(&current->sighand->siglock); 620 spin_unlock_irq(&current->sighand->siglock);
621 621
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 64b612a0a622..572c610db1b1 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -261,11 +261,11 @@ static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t __user *ubuf)
261 default: 261 default:
262 __put_sigset_unknown_nsig(); 262 __put_sigset_unknown_nsig();
263 case 2: 263 case 2:
264 err |= __put_user (kbuf->sig[1] >> 32, &ubuf->sig[3]); 264 err |= __put_user(kbuf->sig[1] >> 32, &ubuf->sig[3]);
265 err |= __put_user (kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]); 265 err |= __put_user(kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]);
266 case 1: 266 case 1:
267 err |= __put_user (kbuf->sig[0] >> 32, &ubuf->sig[1]); 267 err |= __put_user(kbuf->sig[0] >> 32, &ubuf->sig[1]);
268 err |= __put_user (kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]); 268 err |= __put_user(kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]);
269 } 269 }
270 270
271 return err; 271 return err;
@@ -283,12 +283,12 @@ static inline int get_sigset(sigset_t *kbuf, const compat_sigset_t __user *ubuf)
283 default: 283 default:
284 __get_sigset_unknown_nsig(); 284 __get_sigset_unknown_nsig();
285 case 2: 285 case 2:
286 err |= __get_user (sig[3], &ubuf->sig[3]); 286 err |= __get_user(sig[3], &ubuf->sig[3]);
287 err |= __get_user (sig[2], &ubuf->sig[2]); 287 err |= __get_user(sig[2], &ubuf->sig[2]);
288 kbuf->sig[1] = sig[2] | (sig[3] << 32); 288 kbuf->sig[1] = sig[2] | (sig[3] << 32);
289 case 1: 289 case 1:
290 err |= __get_user (sig[1], &ubuf->sig[1]); 290 err |= __get_user(sig[1], &ubuf->sig[1]);
291 err |= __get_user (sig[0], &ubuf->sig[0]); 291 err |= __get_user(sig[0], &ubuf->sig[0]);
292 kbuf->sig[0] = sig[0] | (sig[1] << 32); 292 kbuf->sig[0] = sig[0] | (sig[1] << 32);
293 } 293 }
294 294
@@ -412,10 +412,10 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs)
412 return -EFAULT; 412 return -EFAULT;
413 } 413 }
414 414
415 set_fs (KERNEL_DS); 415 set_fs(KERNEL_DS);
416 ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL, 416 ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL,
417 uoss ? (stack_t __user *)&koss : NULL, usp); 417 uoss ? (stack_t __user *)&koss : NULL, usp);
418 set_fs (old_fs); 418 set_fs(old_fs);
419 419
420 if (!ret && uoss) { 420 if (!ret && uoss) {
421 if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss))) 421 if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss)))
@@ -559,9 +559,9 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
559 /* It is more difficult to avoid calling this function than to 559 /* It is more difficult to avoid calling this function than to
560 call it and ignore errors. */ 560 call it and ignore errors. */
561 old_fs = get_fs(); 561 old_fs = get_fs();
562 set_fs (KERNEL_DS); 562 set_fs(KERNEL_DS);
563 do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); 563 do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]);
564 set_fs (old_fs); 564 set_fs(old_fs);
565 565
566 /* 566 /*
567 * Don't let your children do this ... 567 * Don't let your children do this ...
@@ -746,11 +746,11 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t __user *set,
746 if (set && get_sigset(&new_set, set)) 746 if (set && get_sigset(&new_set, set))
747 return -EFAULT; 747 return -EFAULT;
748 748
749 set_fs (KERNEL_DS); 749 set_fs(KERNEL_DS);
750 ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL, 750 ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL,
751 oset ? (sigset_t __user *)&old_set : NULL, 751 oset ? (sigset_t __user *)&old_set : NULL,
752 sigsetsize); 752 sigsetsize);
753 set_fs (old_fs); 753 set_fs(old_fs);
754 754
755 if (!ret && oset && put_sigset(&old_set, oset)) 755 if (!ret && oset && put_sigset(&old_set, oset))
756 return -EFAULT; 756 return -EFAULT;
@@ -765,9 +765,9 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset,
765 sigset_t set; 765 sigset_t set;
766 mm_segment_t old_fs = get_fs(); 766 mm_segment_t old_fs = get_fs();
767 767
768 set_fs (KERNEL_DS); 768 set_fs(KERNEL_DS);
769 ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize); 769 ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize);
770 set_fs (old_fs); 770 set_fs(old_fs);
771 771
772 if (!ret && put_sigset(&set, uset)) 772 if (!ret && put_sigset(&set, uset))
773 return -EFAULT; 773 return -EFAULT;
@@ -781,12 +781,12 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *
781 int ret; 781 int ret;
782 mm_segment_t old_fs = get_fs(); 782 mm_segment_t old_fs = get_fs();
783 783
784 if (copy_from_user (&info, uinfo, 3*sizeof(int)) || 784 if (copy_from_user(&info, uinfo, 3*sizeof(int)) ||
785 copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) 785 copy_from_user(info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE))
786 return -EFAULT; 786 return -EFAULT;
787 set_fs (KERNEL_DS); 787 set_fs(KERNEL_DS);
788 ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info); 788 ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info);
789 set_fs (old_fs); 789 set_fs(old_fs);
790 return ret; 790 return ret;
791} 791}
792 792
@@ -801,10 +801,10 @@ sys32_waitid(int which, compat_pid_t pid,
801 mm_segment_t old_fs = get_fs(); 801 mm_segment_t old_fs = get_fs();
802 802
803 info.si_signo = 0; 803 info.si_signo = 0;
804 set_fs (KERNEL_DS); 804 set_fs(KERNEL_DS);
805 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options, 805 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options,
806 uru ? (struct rusage __user *) &ru : NULL); 806 uru ? (struct rusage __user *) &ru : NULL);
807 set_fs (old_fs); 807 set_fs(old_fs);
808 808
809 if (ret < 0 || info.si_signo == 0) 809 if (ret < 0 || info.si_signo == 0)
810 return ret; 810 return ret;
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index eb7e05926ebe..bb277e82d421 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -88,7 +88,7 @@ struct rt_sigframe_n32 {
88 88
89#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */ 89#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */
90 90
91extern void sigset_from_compat (sigset_t *set, compat_sigset_t *compat); 91extern void sigset_from_compat(sigset_t *set, compat_sigset_t *compat);
92 92
93asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) 93asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
94{ 94{
@@ -105,7 +105,7 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
105 unewset = (compat_sigset_t __user *) regs.regs[4]; 105 unewset = (compat_sigset_t __user *) regs.regs[4];
106 if (copy_from_user(&uset, unewset, sizeof(uset))) 106 if (copy_from_user(&uset, unewset, sizeof(uset)))
107 return -EFAULT; 107 return -EFAULT;
108 sigset_from_compat (&newset, &uset); 108 sigset_from_compat(&newset, &uset);
109 sigdelsetmask(&newset, ~_BLOCKABLE); 109 sigdelsetmask(&newset, ~_BLOCKABLE);
110 110
111 spin_lock_irq(&current->sighand->siglock); 111 spin_lock_irq(&current->sighand->siglock);
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 05dcce416325..94e210cc6cb6 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -353,7 +353,7 @@ void core_send_ipi(int cpu, unsigned int action)
353 unsigned long flags; 353 unsigned long flags;
354 int vpflags; 354 int vpflags;
355 355
356 local_irq_save (flags); 356 local_irq_save(flags);
357 357
358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ 358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
359 359
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 73b0dab02668..432f2e376aea 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -38,6 +38,7 @@
38#include <asm/system.h> 38#include <asm/system.h>
39#include <asm/mmu_context.h> 39#include <asm/mmu_context.h>
40#include <asm/smp.h> 40#include <asm/smp.h>
41#include <asm/time.h>
41 42
42#ifdef CONFIG_MIPS_MT_SMTC 43#ifdef CONFIG_MIPS_MT_SMTC
43#include <asm/mipsmtregs.h> 44#include <asm/mipsmtregs.h>
@@ -70,6 +71,7 @@ asmlinkage __cpuinit void start_secondary(void)
70 cpu_probe(); 71 cpu_probe();
71 cpu_report(); 72 cpu_report();
72 per_cpu_trap_init(); 73 per_cpu_trap_init();
74 mips_clockevent_init();
73 prom_init_secondary(); 75 prom_init_secondary();
74 76
75 /* 77 /*
@@ -95,6 +97,8 @@ struct call_data_struct *call_data;
95 97
96/* 98/*
97 * Run a function on all other CPUs. 99 * Run a function on all other CPUs.
100 *
101 * <mask> cpuset_t of all processors to run the function on.
98 * <func> The function to run. This must be fast and non-blocking. 102 * <func> The function to run. This must be fast and non-blocking.
99 * <info> An arbitrary pointer to pass to the function. 103 * <info> An arbitrary pointer to pass to the function.
100 * <retry> If true, keep retrying until ready. 104 * <retry> If true, keep retrying until ready.
@@ -119,18 +123,20 @@ struct call_data_struct *call_data;
119 * Spin waiting for call_lock 123 * Spin waiting for call_lock
120 * Deadlock Deadlock 124 * Deadlock Deadlock
121 */ 125 */
122int smp_call_function (void (*func) (void *info), void *info, int retry, 126int smp_call_function_mask(cpumask_t mask, void (*func) (void *info),
123 int wait) 127 void *info, int retry, int wait)
124{ 128{
125 struct call_data_struct data; 129 struct call_data_struct data;
126 int i, cpus = num_online_cpus() - 1;
127 int cpu = smp_processor_id(); 130 int cpu = smp_processor_id();
131 int cpus;
128 132
129 /* 133 /*
130 * Can die spectacularly if this CPU isn't yet marked online 134 * Can die spectacularly if this CPU isn't yet marked online
131 */ 135 */
132 BUG_ON(!cpu_online(cpu)); 136 BUG_ON(!cpu_online(cpu));
133 137
138 cpu_clear(cpu, mask);
139 cpus = cpus_weight(mask);
134 if (!cpus) 140 if (!cpus)
135 return 0; 141 return 0;
136 142
@@ -149,9 +155,7 @@ int smp_call_function (void (*func) (void *info), void *info, int retry,
149 smp_mb(); 155 smp_mb();
150 156
151 /* Send a message to all other CPUs and wait for them to respond */ 157 /* Send a message to all other CPUs and wait for them to respond */
152 for_each_online_cpu(i) 158 core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
153 if (i != cpu)
154 core_send_ipi(i, SMP_CALL_FUNCTION);
155 159
156 /* Wait for response */ 160 /* Wait for response */
157 /* FIXME: lock-up detection, backtrace on lock-up */ 161 /* FIXME: lock-up detection, backtrace on lock-up */
@@ -167,6 +171,11 @@ int smp_call_function (void (*func) (void *info), void *info, int retry,
167 return 0; 171 return 0;
168} 172}
169 173
174int smp_call_function(void (*func) (void *info), void *info, int retry,
175 int wait)
176{
177 return smp_call_function_mask(cpu_online_map, func, info, retry, wait);
178}
170 179
171void smp_call_function_interrupt(void) 180void smp_call_function_interrupt(void)
172{ 181{
@@ -197,8 +206,7 @@ void smp_call_function_interrupt(void)
197int smp_call_function_single(int cpu, void (*func) (void *info), void *info, 206int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
198 int retry, int wait) 207 int retry, int wait)
199{ 208{
200 struct call_data_struct data; 209 int ret, me;
201 int me;
202 210
203 /* 211 /*
204 * Can die spectacularly if this CPU isn't yet marked online 212 * Can die spectacularly if this CPU isn't yet marked online
@@ -217,33 +225,8 @@ int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
217 return 0; 225 return 0;
218 } 226 }
219 227
220 /* Can deadlock when called with interrupts disabled */ 228 ret = smp_call_function_mask(cpumask_of_cpu(cpu), func, info, retry,
221 WARN_ON(irqs_disabled()); 229 wait);
222
223 data.func = func;
224 data.info = info;
225 atomic_set(&data.started, 0);
226 data.wait = wait;
227 if (wait)
228 atomic_set(&data.finished, 0);
229
230 spin_lock(&smp_call_lock);
231 call_data = &data;
232 smp_mb();
233
234 /* Send a message to the other CPU */
235 core_send_ipi(cpu, SMP_CALL_FUNCTION);
236
237 /* Wait for response */
238 /* FIXME: lock-up detection, backtrace on lock-up */
239 while (atomic_read(&data.started) != 1)
240 barrier();
241
242 if (wait)
243 while (atomic_read(&data.finished) != 1)
244 barrier();
245 call_data = NULL;
246 spin_unlock(&smp_call_lock);
247 230
248 put_cpu(); 231 put_cpu();
249 return 0; 232 return 0;
@@ -390,12 +373,15 @@ void flush_tlb_mm(struct mm_struct *mm)
390 preempt_disable(); 373 preempt_disable();
391 374
392 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { 375 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
393 smp_on_other_tlbs(flush_tlb_mm_ipi, (void *)mm); 376 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
394 } else { 377 } else {
395 int i; 378 cpumask_t mask = cpu_online_map;
396 for (i = 0; i < num_online_cpus(); i++) 379 unsigned int cpu;
397 if (smp_processor_id() != i) 380
398 cpu_context(i, mm) = 0; 381 cpu_clear(smp_processor_id(), mask);
382 for_each_online_cpu(cpu)
383 if (cpu_context(cpu, mm))
384 cpu_context(cpu, mm) = 0;
399 } 385 }
400 local_flush_tlb_mm(mm); 386 local_flush_tlb_mm(mm);
401 387
@@ -410,7 +396,7 @@ struct flush_tlb_data {
410 396
411static void flush_tlb_range_ipi(void *info) 397static void flush_tlb_range_ipi(void *info)
412{ 398{
413 struct flush_tlb_data *fd = (struct flush_tlb_data *)info; 399 struct flush_tlb_data *fd = info;
414 400
415 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); 401 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
416} 402}
@@ -421,17 +407,21 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l
421 407
422 preempt_disable(); 408 preempt_disable();
423 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { 409 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
424 struct flush_tlb_data fd; 410 struct flush_tlb_data fd = {
411 .vma = vma,
412 .addr1 = start,
413 .addr2 = end,
414 };
425 415
426 fd.vma = vma; 416 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
427 fd.addr1 = start;
428 fd.addr2 = end;
429 smp_on_other_tlbs(flush_tlb_range_ipi, (void *)&fd);
430 } else { 417 } else {
431 int i; 418 cpumask_t mask = cpu_online_map;
432 for (i = 0; i < num_online_cpus(); i++) 419 unsigned int cpu;
433 if (smp_processor_id() != i) 420
434 cpu_context(i, mm) = 0; 421 cpu_clear(smp_processor_id(), mask);
422 for_each_online_cpu(cpu)
423 if (cpu_context(cpu, mm))
424 cpu_context(cpu, mm) = 0;
435 } 425 }
436 local_flush_tlb_range(vma, start, end); 426 local_flush_tlb_range(vma, start, end);
437 preempt_enable(); 427 preempt_enable();
@@ -439,23 +429,24 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l
439 429
440static void flush_tlb_kernel_range_ipi(void *info) 430static void flush_tlb_kernel_range_ipi(void *info)
441{ 431{
442 struct flush_tlb_data *fd = (struct flush_tlb_data *)info; 432 struct flush_tlb_data *fd = info;
443 433
444 local_flush_tlb_kernel_range(fd->addr1, fd->addr2); 434 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
445} 435}
446 436
447void flush_tlb_kernel_range(unsigned long start, unsigned long end) 437void flush_tlb_kernel_range(unsigned long start, unsigned long end)
448{ 438{
449 struct flush_tlb_data fd; 439 struct flush_tlb_data fd = {
440 .addr1 = start,
441 .addr2 = end,
442 };
450 443
451 fd.addr1 = start; 444 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1, 1);
452 fd.addr2 = end;
453 on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1);
454} 445}
455 446
456static void flush_tlb_page_ipi(void *info) 447static void flush_tlb_page_ipi(void *info)
457{ 448{
458 struct flush_tlb_data *fd = (struct flush_tlb_data *)info; 449 struct flush_tlb_data *fd = info;
459 450
460 local_flush_tlb_page(fd->vma, fd->addr1); 451 local_flush_tlb_page(fd->vma, fd->addr1);
461} 452}
@@ -464,16 +455,20 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
464{ 455{
465 preempt_disable(); 456 preempt_disable();
466 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { 457 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
467 struct flush_tlb_data fd; 458 struct flush_tlb_data fd = {
459 .vma = vma,
460 .addr1 = page,
461 };
468 462
469 fd.vma = vma; 463 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
470 fd.addr1 = page;
471 smp_on_other_tlbs(flush_tlb_page_ipi, (void *)&fd);
472 } else { 464 } else {
473 int i; 465 cpumask_t mask = cpu_online_map;
474 for (i = 0; i < num_online_cpus(); i++) 466 unsigned int cpu;
475 if (smp_processor_id() != i) 467
476 cpu_context(i, vma->vm_mm) = 0; 468 cpu_clear(smp_processor_id(), mask);
469 for_each_online_cpu(cpu)
470 if (cpu_context(cpu, vma->vm_mm))
471 cpu_context(cpu, vma->vm_mm) = 0;
477 } 472 }
478 local_flush_tlb_page(vma, page); 473 local_flush_tlb_page(vma, page);
479 preempt_enable(); 474 preempt_enable();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f09404377ef1..a8c1a698d588 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1,5 +1,6 @@
1/* Copyright (C) 2004 Mips Technologies, Inc */ 1/* Copyright (C) 2004 Mips Technologies, Inc */
2 2
3#include <linux/clockchips.h>
3#include <linux/kernel.h> 4#include <linux/kernel.h>
4#include <linux/sched.h> 5#include <linux/sched.h>
5#include <linux/cpumask.h> 6#include <linux/cpumask.h>
@@ -62,7 +63,7 @@ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
62 * Clock interrupt "latch" buffers, per "CPU" 63 * Clock interrupt "latch" buffers, per "CPU"
63 */ 64 */
64 65
65unsigned int ipi_timer_latch[NR_CPUS]; 66static atomic_t ipi_timer_latch[NR_CPUS];
66 67
67/* 68/*
68 * Number of InterProcessor Interupt (IPI) message buffers to allocate 69 * Number of InterProcessor Interupt (IPI) message buffers to allocate
@@ -179,7 +180,7 @@ void __init sanitize_tlb_entries(void)
179 180
180static void smtc_configure_tlb(void) 181static void smtc_configure_tlb(void)
181{ 182{
182 int i,tlbsiz,vpes; 183 int i, tlbsiz, vpes;
183 unsigned long mvpconf0; 184 unsigned long mvpconf0;
184 unsigned long config1val; 185 unsigned long config1val;
185 186
@@ -296,8 +297,10 @@ int __init mipsmt_build_cpu_map(int start_cpu_slot)
296 __cpu_number_map[i] = i; 297 __cpu_number_map[i] = i;
297 __cpu_logical_map[i] = i; 298 __cpu_logical_map[i] = i;
298 } 299 }
300#ifdef CONFIG_MIPS_MT_FPAFF
299 /* Initialize map of CPUs with FPUs */ 301 /* Initialize map of CPUs with FPUs */
300 cpus_clear(mt_fpu_cpumask); 302 cpus_clear(mt_fpu_cpumask);
303#endif
301 304
302 /* One of those TC's is the one booting, and not a secondary... */ 305 /* One of those TC's is the one booting, and not a secondary... */
303 printk("%i available secondary CPU TC(s)\n", i - 1); 306 printk("%i available secondary CPU TC(s)\n", i - 1);
@@ -359,7 +362,7 @@ void mipsmt_prepare_cpus(void)
359 IPIQ[i].head = IPIQ[i].tail = NULL; 362 IPIQ[i].head = IPIQ[i].tail = NULL;
360 spin_lock_init(&IPIQ[i].lock); 363 spin_lock_init(&IPIQ[i].lock);
361 IPIQ[i].depth = 0; 364 IPIQ[i].depth = 0;
362 ipi_timer_latch[i] = 0; 365 atomic_set(&ipi_timer_latch[i], 0);
363 } 366 }
364 367
365 /* cpu_data index starts at zero */ 368 /* cpu_data index starts at zero */
@@ -369,7 +372,7 @@ void mipsmt_prepare_cpus(void)
369 cpu++; 372 cpu++;
370 373
371 /* Report on boot-time options */ 374 /* Report on boot-time options */
372 mips_mt_set_cpuoptions (); 375 mips_mt_set_cpuoptions();
373 if (vpelimit > 0) 376 if (vpelimit > 0)
374 printk("Limit of %d VPEs set\n", vpelimit); 377 printk("Limit of %d VPEs set\n", vpelimit);
375 if (tclimit > 0) 378 if (tclimit > 0)
@@ -420,7 +423,7 @@ void mipsmt_prepare_cpus(void)
420 * code. Leave it alone! 423 * code. Leave it alone!
421 */ 424 */
422 if (tc != 0) { 425 if (tc != 0) {
423 smtc_tc_setup(vpe,tc, cpu); 426 smtc_tc_setup(vpe, tc, cpu);
424 cpu++; 427 cpu++;
425 } 428 }
426 printk(" %d", tc); 429 printk(" %d", tc);
@@ -428,7 +431,7 @@ void mipsmt_prepare_cpus(void)
428 } 431 }
429 if (slop) { 432 if (slop) {
430 if (tc != 0) { 433 if (tc != 0) {
431 smtc_tc_setup(vpe,tc, cpu); 434 smtc_tc_setup(vpe, tc, cpu);
432 cpu++; 435 cpu++;
433 } 436 }
434 printk(" %d", tc); 437 printk(" %d", tc);
@@ -482,10 +485,12 @@ void mipsmt_prepare_cpus(void)
482 485
483 /* Set up coprocessor affinity CPU mask(s) */ 486 /* Set up coprocessor affinity CPU mask(s) */
484 487
488#ifdef CONFIG_MIPS_MT_FPAFF
485 for (tc = 0; tc < ntc; tc++) { 489 for (tc = 0; tc < ntc; tc++) {
486 if (cpu_data[tc].options & MIPS_CPU_FPU) 490 if (cpu_data[tc].options & MIPS_CPU_FPU)
487 cpu_set(tc, mt_fpu_cpumask); 491 cpu_set(tc, mt_fpu_cpumask);
488 } 492 }
493#endif
489 494
490 /* set up ipi interrupts... */ 495 /* set up ipi interrupts... */
491 496
@@ -567,7 +572,7 @@ void smtc_init_secondary(void)
567 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 572 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
568 ((read_c0_tcbind() & TCBIND_CURVPE) 573 ((read_c0_tcbind() & TCBIND_CURVPE)
569 != cpu_data[smp_processor_id() - 1].vpe_id)){ 574 != cpu_data[smp_processor_id() - 1].vpe_id)){
570 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); 575 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
571 } 576 }
572 577
573 local_irq_enable(); 578 local_irq_enable();
@@ -606,6 +611,60 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new,
606 return setup_irq(irq, new); 611 return setup_irq(irq, new);
607} 612}
608 613
614#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
615/*
616 * Support for IRQ affinity to TCs
617 */
618
619void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
620{
621 /*
622 * If a "fast path" cache of quickly decodable affinity state
623 * is maintained, this is where it gets done, on a call up
624 * from the platform affinity code.
625 */
626}
627
628void smtc_forward_irq(unsigned int irq)
629{
630 int target;
631
632 /*
633 * OK wise guy, now figure out how to get the IRQ
634 * to be serviced on an authorized "CPU".
635 *
636 * Ideally, to handle the situation where an IRQ has multiple
637 * eligible CPUS, we would maintain state per IRQ that would
638 * allow a fair distribution of service requests. Since the
639 * expected use model is any-or-only-one, for simplicity
640 * and efficiency, we just pick the easiest one to find.
641 */
642
643 target = first_cpu(irq_desc[irq].affinity);
644
645 /*
646 * We depend on the platform code to have correctly processed
647 * IRQ affinity change requests to ensure that the IRQ affinity
648 * mask has been purged of bits corresponding to nonexistent and
649 * offline "CPUs", and to TCs bound to VPEs other than the VPE
650 * connected to the physical interrupt input for the interrupt
651 * in question. Otherwise we have a nasty problem with interrupt
652 * mask management. This is best handled in non-performance-critical
653 * platform IRQ affinity setting code, to minimize interrupt-time
654 * checks.
655 */
656
657 /* If no one is eligible, service locally */
658 if (target >= NR_CPUS) {
659 do_IRQ_no_affinity(irq);
660 return;
661 }
662
663 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
664}
665
666#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
667
609/* 668/*
610 * IPI model for SMTC is tricky, because interrupts aren't TC-specific. 669 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
611 * Within a VPE one TC can interrupt another by different approaches. 670 * Within a VPE one TC can interrupt another by different approaches.
@@ -648,7 +707,7 @@ static void smtc_ipi_qdump(void)
648 * be done with the atomic.h primitives). And since this is 707 * be done with the atomic.h primitives). And since this is
649 * MIPS MT, we can assume that we have LL/SC. 708 * MIPS MT, we can assume that we have LL/SC.
650 */ 709 */
651static __inline__ int atomic_postincrement(unsigned int *pv) 710static inline int atomic_postincrement(atomic_t *v)
652{ 711{
653 unsigned long result; 712 unsigned long result;
654 713
@@ -659,9 +718,9 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
659 " addu %1, %0, 1 \n" 718 " addu %1, %0, 1 \n"
660 " sc %1, %2 \n" 719 " sc %1, %2 \n"
661 " beqz %1, 1b \n" 720 " beqz %1, 1b \n"
662 " sync \n" 721 __WEAK_LLSC_MB
663 : "=&r" (result), "=&r" (temp), "=m" (*pv) 722 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
664 : "m" (*pv) 723 : "m" (v->counter)
665 : "memory"); 724 : "memory");
666 725
667 return result; 726 return result;
@@ -689,6 +748,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
689 pipi->arg = (void *)action; 748 pipi->arg = (void *)action;
690 pipi->dest = cpu; 749 pipi->dest = cpu;
691 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 750 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
751 if (type == SMTC_CLOCK_TICK)
752 atomic_inc(&ipi_timer_latch[cpu]);
692 /* If not on same VPE, enqueue and send cross-VPE interupt */ 753 /* If not on same VPE, enqueue and send cross-VPE interupt */
693 smtc_ipi_nq(&IPIQ[cpu], pipi); 754 smtc_ipi_nq(&IPIQ[cpu], pipi);
694 LOCK_CORE_PRA(); 755 LOCK_CORE_PRA();
@@ -730,6 +791,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
730 } 791 }
731 smtc_ipi_nq(&IPIQ[cpu], pipi); 792 smtc_ipi_nq(&IPIQ[cpu], pipi);
732 } else { 793 } else {
794 if (type == SMTC_CLOCK_TICK)
795 atomic_inc(&ipi_timer_latch[cpu]);
733 post_direct_ipi(cpu, pipi); 796 post_direct_ipi(cpu, pipi);
734 write_tc_c0_tchalt(0); 797 write_tc_c0_tchalt(0);
735 UNLOCK_CORE_PRA(); 798 UNLOCK_CORE_PRA();
@@ -747,6 +810,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
747 unsigned long tcrestart; 810 unsigned long tcrestart;
748 extern u32 kernelsp[NR_CPUS]; 811 extern u32 kernelsp[NR_CPUS];
749 extern void __smtc_ipi_vector(void); 812 extern void __smtc_ipi_vector(void);
813//printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
750 814
751 /* Extract Status, EPC from halted TC */ 815 /* Extract Status, EPC from halted TC */
752 tcstatus = read_tc_c0_tcstatus(); 816 tcstatus = read_tc_c0_tcstatus();
@@ -797,25 +861,31 @@ static void ipi_call_interrupt(void)
797 smp_call_function_interrupt(); 861 smp_call_function_interrupt();
798} 862}
799 863
864DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
865
800void ipi_decode(struct smtc_ipi *pipi) 866void ipi_decode(struct smtc_ipi *pipi)
801{ 867{
868 unsigned int cpu = smp_processor_id();
869 struct clock_event_device *cd;
802 void *arg_copy = pipi->arg; 870 void *arg_copy = pipi->arg;
803 int type_copy = pipi->type; 871 int type_copy = pipi->type;
804 int dest_copy = pipi->dest; 872 int ticks;
805 873
806 smtc_ipi_nq(&freeIPIq, pipi); 874 smtc_ipi_nq(&freeIPIq, pipi);
807 switch (type_copy) { 875 switch (type_copy) {
808 case SMTC_CLOCK_TICK: 876 case SMTC_CLOCK_TICK:
809 irq_enter(); 877 irq_enter();
810 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++; 878 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
811 /* Invoke Clock "Interrupt" */ 879 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
812 ipi_timer_latch[dest_copy] = 0; 880 ticks = atomic_read(&ipi_timer_latch[cpu]);
813#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 881 atomic_sub(ticks, &ipi_timer_latch[cpu]);
814 clock_hang_reported[dest_copy] = 0; 882 while (ticks) {
815#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ 883 cd->event_handler(cd);
816 local_timer_interrupt(0, NULL); 884 ticks--;
885 }
817 irq_exit(); 886 irq_exit();
818 break; 887 break;
888
819 case LINUX_SMP_IPI: 889 case LINUX_SMP_IPI:
820 switch ((int)arg_copy) { 890 switch ((int)arg_copy) {
821 case SMP_RESCHEDULE_YOURSELF: 891 case SMP_RESCHEDULE_YOURSELF:
@@ -830,6 +900,15 @@ void ipi_decode(struct smtc_ipi *pipi)
830 break; 900 break;
831 } 901 }
832 break; 902 break;
903#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
904 case IRQ_AFFINITY_IPI:
905 /*
906 * Accept a "forwarded" interrupt that was initially
907 * taken by a TC who doesn't have affinity for the IRQ.
908 */
909 do_IRQ_no_affinity((int)arg_copy);
910 break;
911#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
833 default: 912 default:
834 printk("Impossible SMTC IPI Type 0x%x\n", type_copy); 913 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
835 break; 914 break;
@@ -858,25 +937,6 @@ void deferred_smtc_ipi(void)
858} 937}
859 938
860/* 939/*
861 * Send clock tick to all TCs except the one executing the funtion
862 */
863
864void smtc_timer_broadcast(void)
865{
866 int cpu;
867 int myTC = cpu_data[smp_processor_id()].tc_id;
868 int myVPE = cpu_data[smp_processor_id()].vpe_id;
869
870 smtc_cpu_stats[smp_processor_id()].timerints++;
871
872 for_each_online_cpu(cpu) {
873 if (cpu_data[cpu].vpe_id == myVPE &&
874 cpu_data[cpu].tc_id != myTC)
875 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
876 }
877}
878
879/*
880 * Cross-VPE interrupts in the SMTC prototype use "software interrupts" 940 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
881 * set via cross-VPE MTTR manipulation of the Cause register. It would be 941 * set via cross-VPE MTTR manipulation of the Cause register. It would be
882 * in some regards preferable to have external logic for "doorbell" hardware 942 * in some regards preferable to have external logic for "doorbell" hardware
@@ -1117,11 +1177,11 @@ void smtc_idle_loop_hook(void)
1117 for (tc = 0; tc < NR_CPUS; tc++) { 1177 for (tc = 0; tc < NR_CPUS; tc++) {
1118 /* Don't check ourself - we'll dequeue IPIs just below */ 1178 /* Don't check ourself - we'll dequeue IPIs just below */
1119 if ((tc != smp_processor_id()) && 1179 if ((tc != smp_processor_id()) &&
1120 ipi_timer_latch[tc] > timerq_limit) { 1180 atomic_read(&ipi_timer_latch[tc]) > timerq_limit) {
1121 if (clock_hang_reported[tc] == 0) { 1181 if (clock_hang_reported[tc] == 0) {
1122 pdb_msg += sprintf(pdb_msg, 1182 pdb_msg += sprintf(pdb_msg,
1123 "TC %d looks hung with timer latch at %d\n", 1183 "TC %d looks hung with timer latch at %d\n",
1124 tc, ipi_timer_latch[tc]); 1184 tc, atomic_read(&ipi_timer_latch[tc]));
1125 clock_hang_reported[tc]++; 1185 clock_hang_reported[tc]++;
1126 } 1186 }
1127 } 1187 }
@@ -1162,7 +1222,7 @@ void smtc_soft_dump(void)
1162 smtc_ipi_qdump(); 1222 smtc_ipi_qdump();
1163 printk("Timer IPI Backlogs:\n"); 1223 printk("Timer IPI Backlogs:\n");
1164 for (i=0; i < NR_CPUS; i++) { 1224 for (i=0; i < NR_CPUS; i++) {
1165 printk("%d: %d\n", i, ipi_timer_latch[i]); 1225 printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i]));
1166 } 1226 }
1167 printk("%d Recoveries of \"stolen\" FPU\n", 1227 printk("%d Recoveries of \"stolen\" FPU\n",
1168 atomic_read(&smtc_fpu_recoveries)); 1228 atomic_read(&smtc_fpu_recoveries));
@@ -1204,7 +1264,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1204 if (cpu_has_vtag_icache) 1264 if (cpu_has_vtag_icache)
1205 flush_icache_all(); 1265 flush_icache_all();
1206 /* Traverse all online CPUs (hack requires contigous range) */ 1266 /* Traverse all online CPUs (hack requires contigous range) */
1207 for (i = 0; i < num_online_cpus(); i++) { 1267 for_each_online_cpu(i) {
1208 /* 1268 /*
1209 * We don't need to worry about our own CPU, nor those of 1269 * We don't need to worry about our own CPU, nor those of
1210 * CPUs who don't share our TLB. 1270 * CPUs who don't share our TLB.
@@ -1233,7 +1293,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1233 /* 1293 /*
1234 * SMTC shares the TLB within VPEs and possibly across all VPEs. 1294 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1235 */ 1295 */
1236 for (i = 0; i < num_online_cpus(); i++) { 1296 for_each_online_cpu(i) {
1237 if ((smtc_status & SMTC_TLB_SHARED) || 1297 if ((smtc_status & SMTC_TLB_SHARED) ||
1238 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 1298 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1239 cpu_context(i, mm) = asid_cache(i) = asid; 1299 cpu_context(i, mm) = asid_cache(i) = asid;
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 7c800ec3ff55..17c4374d2209 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -245,7 +245,7 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name)
245 245
246 if (!name) 246 if (!name)
247 return -EFAULT; 247 return -EFAULT;
248 if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname))) 248 if (!access_ok(VERIFY_WRITE, name, sizeof(struct oldold_utsname)))
249 return -EFAULT; 249 return -EFAULT;
250 250
251 error = __copy_to_user(&name->sysname, &utsname()->sysname, 251 error = __copy_to_user(&name->sysname, &utsname()->sysname,
@@ -314,8 +314,8 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
314 * 314 *
315 * This is really horribly ugly. 315 * This is really horribly ugly.
316 */ 316 */
317asmlinkage int sys_ipc (unsigned int call, int first, int second, 317asmlinkage int sys_ipc(unsigned int call, int first, int second,
318 unsigned long third, void __user *ptr, long fifth) 318 unsigned long third, void __user *ptr, long fifth)
319{ 319{
320 int version, ret; 320 int version, ret;
321 321
@@ -324,26 +324,26 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second,
324 324
325 switch (call) { 325 switch (call) {
326 case SEMOP: 326 case SEMOP:
327 return sys_semtimedop (first, (struct sembuf __user *)ptr, 327 return sys_semtimedop(first, (struct sembuf __user *)ptr,
328 second, NULL); 328 second, NULL);
329 case SEMTIMEDOP: 329 case SEMTIMEDOP:
330 return sys_semtimedop (first, (struct sembuf __user *)ptr, 330 return sys_semtimedop(first, (struct sembuf __user *)ptr,
331 second, 331 second,
332 (const struct timespec __user *)fifth); 332 (const struct timespec __user *)fifth);
333 case SEMGET: 333 case SEMGET:
334 return sys_semget (first, second, third); 334 return sys_semget(first, second, third);
335 case SEMCTL: { 335 case SEMCTL: {
336 union semun fourth; 336 union semun fourth;
337 if (!ptr) 337 if (!ptr)
338 return -EINVAL; 338 return -EINVAL;
339 if (get_user(fourth.__pad, (void __user *__user *) ptr)) 339 if (get_user(fourth.__pad, (void __user *__user *) ptr))
340 return -EFAULT; 340 return -EFAULT;
341 return sys_semctl (first, second, third, fourth); 341 return sys_semctl(first, second, third, fourth);
342 } 342 }
343 343
344 case MSGSND: 344 case MSGSND:
345 return sys_msgsnd (first, (struct msgbuf __user *) ptr, 345 return sys_msgsnd(first, (struct msgbuf __user *) ptr,
346 second, third); 346 second, third);
347 case MSGRCV: 347 case MSGRCV:
348 switch (version) { 348 switch (version) {
349 case 0: { 349 case 0: {
@@ -353,45 +353,45 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second,
353 353
354 if (copy_from_user(&tmp, 354 if (copy_from_user(&tmp,
355 (struct ipc_kludge __user *) ptr, 355 (struct ipc_kludge __user *) ptr,
356 sizeof (tmp))) 356 sizeof(tmp)))
357 return -EFAULT; 357 return -EFAULT;
358 return sys_msgrcv (first, tmp.msgp, second, 358 return sys_msgrcv(first, tmp.msgp, second,
359 tmp.msgtyp, third); 359 tmp.msgtyp, third);
360 } 360 }
361 default: 361 default:
362 return sys_msgrcv (first, 362 return sys_msgrcv(first,
363 (struct msgbuf __user *) ptr, 363 (struct msgbuf __user *) ptr,
364 second, fifth, third); 364 second, fifth, third);
365 } 365 }
366 case MSGGET: 366 case MSGGET:
367 return sys_msgget ((key_t) first, second); 367 return sys_msgget((key_t) first, second);
368 case MSGCTL: 368 case MSGCTL:
369 return sys_msgctl (first, second, 369 return sys_msgctl(first, second,
370 (struct msqid_ds __user *) ptr); 370 (struct msqid_ds __user *) ptr);
371 371
372 case SHMAT: 372 case SHMAT:
373 switch (version) { 373 switch (version) {
374 default: { 374 default: {
375 unsigned long raddr; 375 unsigned long raddr;
376 ret = do_shmat (first, (char __user *) ptr, second, 376 ret = do_shmat(first, (char __user *) ptr, second,
377 &raddr); 377 &raddr);
378 if (ret) 378 if (ret)
379 return ret; 379 return ret;
380 return put_user (raddr, (unsigned long __user *) third); 380 return put_user(raddr, (unsigned long __user *) third);
381 } 381 }
382 case 1: /* iBCS2 emulator entry point */ 382 case 1: /* iBCS2 emulator entry point */
383 if (!segment_eq(get_fs(), get_ds())) 383 if (!segment_eq(get_fs(), get_ds()))
384 return -EINVAL; 384 return -EINVAL;
385 return do_shmat (first, (char __user *) ptr, second, 385 return do_shmat(first, (char __user *) ptr, second,
386 (unsigned long *) third); 386 (unsigned long *) third);
387 } 387 }
388 case SHMDT: 388 case SHMDT:
389 return sys_shmdt ((char __user *)ptr); 389 return sys_shmdt((char __user *)ptr);
390 case SHMGET: 390 case SHMGET:
391 return sys_shmget (first, second, third); 391 return sys_shmget(first, second, third);
392 case SHMCTL: 392 case SHMCTL:
393 return sys_shmctl (first, second, 393 return sys_shmctl(first, second,
394 (struct shmid_ds __user *) ptr); 394 (struct shmid_ds __user *) ptr);
395 default: 395 default:
396 return -ENOSYS; 396 return -ENOSYS;
397 } 397 }
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index 93a148486f88..ee7790d9debe 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -486,10 +486,10 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
486 486
487 switch (arg1) { 487 switch (arg1) {
488 case SGI_INV_SIZEOF: 488 case SGI_INV_SIZEOF:
489 retval = sizeof (inventory_t); 489 retval = sizeof(inventory_t);
490 break; 490 break;
491 case SGI_INV_READ: 491 case SGI_INV_READ:
492 retval = dump_inventory_to_user (buffer, count); 492 retval = dump_inventory_to_user(buffer, count);
493 break; 493 break;
494 default: 494 default:
495 retval = -EINVAL; 495 retval = -EINVAL;
@@ -778,7 +778,7 @@ asmlinkage int irix_times(struct tms __user *tbuf)
778 int err = 0; 778 int err = 0;
779 779
780 if (tbuf) { 780 if (tbuf) {
781 if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) 781 if (!access_ok(VERIFY_WRITE, tbuf, sizeof *tbuf))
782 return -EFAULT; 782 return -EFAULT;
783 783
784 err = __put_user(current->utime, &tbuf->tms_utime); 784 err = __put_user(current->utime, &tbuf->tms_utime);
@@ -1042,9 +1042,9 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot,
1042 long max_size = offset + len; 1042 long max_size = offset + len;
1043 1043
1044 if (max_size > file->f_path.dentry->d_inode->i_size) { 1044 if (max_size > file->f_path.dentry->d_inode->i_size) {
1045 old_pos = sys_lseek (fd, max_size - 1, 0); 1045 old_pos = sys_lseek(fd, max_size - 1, 0);
1046 sys_write (fd, (void __user *) "", 1); 1046 sys_write(fd, (void __user *) "", 1);
1047 sys_lseek (fd, old_pos, 0); 1047 sys_lseek(fd, old_pos, 0);
1048 } 1048 }
1049 } 1049 }
1050 } 1050 }
@@ -1176,7 +1176,7 @@ static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf)
1176 ub.st_ctime1 = stat->atime.tv_nsec; 1176 ub.st_ctime1 = stat->atime.tv_nsec;
1177 ub.st_blksize = stat->blksize; 1177 ub.st_blksize = stat->blksize;
1178 ub.st_blocks = stat->blocks; 1178 ub.st_blocks = stat->blocks;
1179 strcpy (ub.st_fstype, "efs"); 1179 strcpy(ub.st_fstype, "efs");
1180 1180
1181 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; 1181 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0;
1182} 1182}
@@ -1208,7 +1208,7 @@ static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf)
1208 ks.st_nlink = (u32) stat->nlink; 1208 ks.st_nlink = (u32) stat->nlink;
1209 ks.st_uid = (s32) stat->uid; 1209 ks.st_uid = (s32) stat->uid;
1210 ks.st_gid = (s32) stat->gid; 1210 ks.st_gid = (s32) stat->gid;
1211 ks.st_rdev = sysv_encode_dev (stat->rdev); 1211 ks.st_rdev = sysv_encode_dev(stat->rdev);
1212 ks.st_pad2[0] = ks.st_pad2[1] = 0; 1212 ks.st_pad2[0] = ks.st_pad2[1] = 0;
1213 ks.st_size = (long long) stat->size; 1213 ks.st_size = (long long) stat->size;
1214 ks.st_pad3 = 0; 1214 ks.st_pad3 = 0;
@@ -1527,9 +1527,9 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1527 long max_size = off2 + len; 1527 long max_size = off2 + len;
1528 1528
1529 if (max_size > file->f_path.dentry->d_inode->i_size) { 1529 if (max_size > file->f_path.dentry->d_inode->i_size) {
1530 old_pos = sys_lseek (fd, max_size - 1, 0); 1530 old_pos = sys_lseek(fd, max_size - 1, 0);
1531 sys_write (fd, (void __user *) "", 1); 1531 sys_write(fd, (void __user *) "", 1);
1532 sys_lseek (fd, old_pos, 0); 1532 sys_lseek(fd, old_pos, 0);
1533 } 1533 }
1534 } 1534 }
1535 } 1535 }
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 9a5596bf8571..5892491b40eb 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,6 +11,7 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/clockchips.h>
14#include <linux/types.h> 15#include <linux/types.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/init.h> 17#include <linux/init.h>
@@ -24,6 +25,7 @@
24#include <linux/spinlock.h> 25#include <linux/spinlock.h>
25#include <linux/interrupt.h> 26#include <linux/interrupt.h>
26#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/kallsyms.h>
27 29
28#include <asm/bootinfo.h> 30#include <asm/bootinfo.h>
29#include <asm/cache.h> 31#include <asm/cache.h>
@@ -32,8 +34,11 @@
32#include <asm/cpu-features.h> 34#include <asm/cpu-features.h>
33#include <asm/div64.h> 35#include <asm/div64.h>
34#include <asm/sections.h> 36#include <asm/sections.h>
37#include <asm/smtc_ipi.h>
35#include <asm/time.h> 38#include <asm/time.h>
36 39
40#include <irq.h>
41
37/* 42/*
38 * The integer part of the number of usecs per jiffy is taken from tick, 43 * The integer part of the number of usecs per jiffy is taken from tick,
39 * but the fractional part is not recorded, so we calculate it using the 44 * but the fractional part is not recorded, so we calculate it using the
@@ -49,32 +54,27 @@
49 * forward reference 54 * forward reference
50 */ 55 */
51DEFINE_SPINLOCK(rtc_lock); 56DEFINE_SPINLOCK(rtc_lock);
57EXPORT_SYMBOL(rtc_lock);
52 58
53/* 59int __weak rtc_mips_set_time(unsigned long sec)
54 * By default we provide the null RTC ops
55 */
56static unsigned long null_rtc_get_time(void)
57{ 60{
58 return mktime(2000, 1, 1, 0, 0, 0); 61 return 0;
59} 62}
63EXPORT_SYMBOL(rtc_mips_set_time);
60 64
61static int null_rtc_set_time(unsigned long sec) 65int __weak rtc_mips_set_mmss(unsigned long nowtime)
62{ 66{
63 return 0; 67 return rtc_mips_set_time(nowtime);
64} 68}
65 69
66unsigned long (*rtc_mips_get_time)(void) = null_rtc_get_time; 70int update_persistent_clock(struct timespec now)
67int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time; 71{
68int (*rtc_mips_set_mmss)(unsigned long); 72 return rtc_mips_set_mmss(now.tv_sec);
69 73}
70 74
71/* how many counter cycles in a jiffy */ 75/* how many counter cycles in a jiffy */
72static unsigned long cycles_per_jiffy __read_mostly; 76static unsigned long cycles_per_jiffy __read_mostly;
73 77
74/* expirelo is the count value for next CPU timer interrupt */
75static unsigned int expirelo;
76
77
78/* 78/*
79 * Null timer ack for systems not needing one (e.g. i8254). 79 * Null timer ack for systems not needing one (e.g. i8254).
80 */ 80 */
@@ -93,18 +93,7 @@ static cycle_t null_hpt_read(void)
93 */ 93 */
94static void c0_timer_ack(void) 94static void c0_timer_ack(void)
95{ 95{
96 unsigned int count; 96 write_c0_compare(read_c0_compare());
97
98 /* Ack this timer interrupt and set the next one. */
99 expirelo += cycles_per_jiffy;
100 write_c0_compare(expirelo);
101
102 /* Check to see if we have missed any timer interrupts. */
103 while (((count = read_c0_count()) - expirelo) < 0x7fffffff) {
104 /* missed_timer_count++; */
105 expirelo = count + cycles_per_jiffy;
106 write_c0_compare(expirelo);
107 }
108} 97}
109 98
110/* 99/*
@@ -115,19 +104,9 @@ static cycle_t c0_hpt_read(void)
115 return read_c0_count(); 104 return read_c0_count();
116} 105}
117 106
118/* For use both as a high precision timer and an interrupt source. */
119static void __init c0_hpt_timer_init(void)
120{
121 expirelo = read_c0_count() + cycles_per_jiffy;
122 write_c0_compare(expirelo);
123}
124
125int (*mips_timer_state)(void); 107int (*mips_timer_state)(void);
126void (*mips_timer_ack)(void); 108void (*mips_timer_ack)(void);
127 109
128/* last time when xtime and rtc are sync'ed up */
129static long last_rtc_update;
130
131/* 110/*
132 * local_timer_interrupt() does profiling and process accounting 111 * local_timer_interrupt() does profiling and process accounting
133 * on a per-CPU basis. 112 * on a per-CPU basis.
@@ -144,60 +123,15 @@ void local_timer_interrupt(int irq, void *dev_id)
144 update_process_times(user_mode(get_irq_regs())); 123 update_process_times(user_mode(get_irq_regs()));
145} 124}
146 125
147/*
148 * High-level timer interrupt service routines. This function
149 * is set as irqaction->handler and is invoked through do_IRQ.
150 */
151irqreturn_t timer_interrupt(int irq, void *dev_id)
152{
153 write_seqlock(&xtime_lock);
154
155 mips_timer_ack();
156
157 /*
158 * call the generic timer interrupt handling
159 */
160 do_timer(1);
161
162 /*
163 * If we have an externally synchronized Linux clock, then update
164 * CMOS clock accordingly every ~11 minutes. rtc_mips_set_time() has to be
165 * called as close as possible to 500 ms before the new second starts.
166 */
167 if (ntp_synced() &&
168 xtime.tv_sec > last_rtc_update + 660 &&
169 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
170 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
171 if (rtc_mips_set_mmss(xtime.tv_sec) == 0) {
172 last_rtc_update = xtime.tv_sec;
173 } else {
174 /* do it again in 60 s */
175 last_rtc_update = xtime.tv_sec - 600;
176 }
177 }
178
179 write_sequnlock(&xtime_lock);
180
181 /*
182 * In UP mode, we call local_timer_interrupt() to do profiling
183 * and process accouting.
184 *
185 * In SMP mode, local_timer_interrupt() is invoked by appropriate
186 * low-level local timer interrupt handler.
187 */
188 local_timer_interrupt(irq, dev_id);
189
190 return IRQ_HANDLED;
191}
192
193int null_perf_irq(void) 126int null_perf_irq(void)
194{ 127{
195 return 0; 128 return 0;
196} 129}
197 130
131EXPORT_SYMBOL(null_perf_irq);
132
198int (*perf_irq)(void) = null_perf_irq; 133int (*perf_irq)(void) = null_perf_irq;
199 134
200EXPORT_SYMBOL(null_perf_irq);
201EXPORT_SYMBOL(perf_irq); 135EXPORT_SYMBOL(perf_irq);
202 136
203/* 137/*
@@ -215,7 +149,7 @@ EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
215 * Possibly handle a performance counter interrupt. 149 * Possibly handle a performance counter interrupt.
216 * Return true if the timer interrupt should not be checked 150 * Return true if the timer interrupt should not be checked
217 */ 151 */
218static inline int handle_perf_irq (int r2) 152static inline int handle_perf_irq(int r2)
219{ 153{
220 /* 154 /*
221 * The performance counter overflow interrupt may be shared with the 155 * The performance counter overflow interrupt may be shared with the
@@ -229,63 +163,23 @@ static inline int handle_perf_irq (int r2)
229 !r2; 163 !r2;
230} 164}
231 165
232asmlinkage void ll_timer_interrupt(int irq)
233{
234 int r2 = cpu_has_mips_r2;
235
236 irq_enter();
237 kstat_this_cpu.irqs[irq]++;
238
239 if (handle_perf_irq(r2))
240 goto out;
241
242 if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
243 goto out;
244
245 timer_interrupt(irq, NULL);
246
247out:
248 irq_exit();
249}
250
251asmlinkage void ll_local_timer_interrupt(int irq)
252{
253 irq_enter();
254 if (smp_processor_id() != 0)
255 kstat_this_cpu.irqs[irq]++;
256
257 /* we keep interrupt disabled all the time */
258 local_timer_interrupt(irq, NULL);
259
260 irq_exit();
261}
262
263/* 166/*
264 * time_init() - it does the following things. 167 * time_init() - it does the following things.
265 * 168 *
266 * 1) board_time_init() - 169 * 1) plat_time_init() -
267 * a) (optional) set up RTC routines, 170 * a) (optional) set up RTC routines,
268 * b) (optional) calibrate and set the mips_hpt_frequency 171 * b) (optional) calibrate and set the mips_hpt_frequency
269 * (only needed if you intended to use cpu counter as timer interrupt 172 * (only needed if you intended to use cpu counter as timer interrupt
270 * source) 173 * source)
271 * 2) setup xtime based on rtc_mips_get_time(). 174 * 2) calculate a couple of cached variables for later usage
272 * 3) calculate a couple of cached variables for later usage 175 * 3) plat_timer_setup() -
273 * 4) plat_timer_setup() -
274 * a) (optional) over-write any choices made above by time_init(). 176 * a) (optional) over-write any choices made above by time_init().
275 * b) machine specific code should setup the timer irqaction. 177 * b) machine specific code should setup the timer irqaction.
276 * c) enable the timer interrupt 178 * c) enable the timer interrupt
277 */ 179 */
278 180
279void (*board_time_init)(void);
280
281unsigned int mips_hpt_frequency; 181unsigned int mips_hpt_frequency;
282 182
283static struct irqaction timer_irqaction = {
284 .handler = timer_interrupt,
285 .flags = IRQF_DISABLED | IRQF_PERCPU,
286 .name = "timer",
287};
288
289static unsigned int __init calibrate_hpt(void) 183static unsigned int __init calibrate_hpt(void)
290{ 184{
291 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz; 185 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
@@ -334,6 +228,84 @@ struct clocksource clocksource_mips = {
334 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 228 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
335}; 229};
336 230
231static int mips_next_event(unsigned long delta,
232 struct clock_event_device *evt)
233{
234 unsigned int cnt;
235 int res;
236
237#ifdef CONFIG_MIPS_MT_SMTC
238 {
239 unsigned long flags, vpflags;
240 local_irq_save(flags);
241 vpflags = dvpe();
242#endif
243 cnt = read_c0_count();
244 cnt += delta;
245 write_c0_compare(cnt);
246 res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
247#ifdef CONFIG_MIPS_MT_SMTC
248 evpe(vpflags);
249 local_irq_restore(flags);
250 }
251#endif
252 return res;
253}
254
255static void mips_set_mode(enum clock_event_mode mode,
256 struct clock_event_device *evt)
257{
258 /* Nothing to do ... */
259}
260
261static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
262static int cp0_timer_irq_installed;
263
264static irqreturn_t timer_interrupt(int irq, void *dev_id)
265{
266 const int r2 = cpu_has_mips_r2;
267 struct clock_event_device *cd;
268 int cpu = smp_processor_id();
269
270 /*
271 * Suckage alert:
272 * Before R2 of the architecture there was no way to see if a
273 * performance counter interrupt was pending, so we have to run
274 * the performance counter interrupt handler anyway.
275 */
276 if (handle_perf_irq(r2))
277 goto out;
278
279 /*
280 * The same applies to performance counter interrupts. But with the
281 * above we now know that the reason we got here must be a timer
282 * interrupt. Being the paranoiacs we are we check anyway.
283 */
284 if (!r2 || (read_c0_cause() & (1 << 30))) {
285 c0_timer_ack();
286#ifdef CONFIG_MIPS_MT_SMTC
287 if (cpu_data[cpu].vpe_id)
288 goto out;
289 cpu = 0;
290#endif
291 cd = &per_cpu(mips_clockevent_device, cpu);
292 cd->event_handler(cd);
293 }
294
295out:
296 return IRQ_HANDLED;
297}
298
299static struct irqaction timer_irqaction = {
300 .handler = timer_interrupt,
301#ifdef CONFIG_MIPS_MT_SMTC
302 .flags = IRQF_DISABLED,
303#else
304 .flags = IRQF_DISABLED | IRQF_PERCPU,
305#endif
306 .name = "timer",
307};
308
337static void __init init_mips_clocksource(void) 309static void __init init_mips_clocksource(void)
338{ 310{
339 u64 temp; 311 u64 temp;
@@ -357,19 +329,127 @@ static void __init init_mips_clocksource(void)
357 clocksource_register(&clocksource_mips); 329 clocksource_register(&clocksource_mips);
358} 330}
359 331
360void __init time_init(void) 332void __init __weak plat_time_init(void)
333{
334}
335
336void __init __weak plat_timer_setup(struct irqaction *irq)
337{
338}
339
340#ifdef CONFIG_MIPS_MT_SMTC
341DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
342
343static void smtc_set_mode(enum clock_event_mode mode,
344 struct clock_event_device *evt)
345{
346}
347
348int dummycnt[NR_CPUS];
349
350static void mips_broadcast(cpumask_t mask)
351{
352 unsigned int cpu;
353
354 for_each_cpu_mask(cpu, mask)
355 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
356}
357
358static void setup_smtc_dummy_clockevent_device(void)
359{
360 //uint64_t mips_freq = mips_hpt_^frequency;
361 unsigned int cpu = smp_processor_id();
362 struct clock_event_device *cd;
363
364 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
365
366 cd->name = "SMTC";
367 cd->features = CLOCK_EVT_FEAT_DUMMY;
368
369 /* Calculate the min / max delta */
370 cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
371 cd->shift = 0; //32;
372 cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
373 cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
374
375 cd->rating = 200;
376 cd->irq = 17; //-1;
377// if (cpu)
378// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
379// else
380 cd->cpumask = cpumask_of_cpu(cpu);
381
382 cd->set_mode = smtc_set_mode;
383
384 cd->broadcast = mips_broadcast;
385
386 clockevents_register_device(cd);
387}
388#endif
389
390static void mips_event_handler(struct clock_event_device *dev)
361{ 391{
362 if (board_time_init) 392}
363 board_time_init();
364 393
365 if (!rtc_mips_set_mmss) 394void __cpuinit mips_clockevent_init(void)
366 rtc_mips_set_mmss = rtc_mips_set_time; 395{
396 uint64_t mips_freq = mips_hpt_frequency;
397 unsigned int cpu = smp_processor_id();
398 struct clock_event_device *cd;
399 unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
367 400
368 xtime.tv_sec = rtc_mips_get_time(); 401 if (!cpu_has_counter)
369 xtime.tv_nsec = 0; 402 return;
370 403
371 set_normalized_timespec(&wall_to_monotonic, 404#ifdef CONFIG_MIPS_MT_SMTC
372 -xtime.tv_sec, -xtime.tv_nsec); 405 setup_smtc_dummy_clockevent_device();
406
407 /*
408 * On SMTC we only register VPE0's compare interrupt as clockevent
409 * device.
410 */
411 if (cpu)
412 return;
413#endif
414
415 cd = &per_cpu(mips_clockevent_device, cpu);
416
417 cd->name = "MIPS";
418 cd->features = CLOCK_EVT_FEAT_ONESHOT;
419
420 /* Calculate the min / max delta */
421 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
422 cd->shift = 32;
423 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
424 cd->min_delta_ns = clockevent_delta2ns(0x30, cd);
425
426 cd->rating = 300;
427 cd->irq = irq;
428#ifdef CONFIG_MIPS_MT_SMTC
429 cd->cpumask = CPU_MASK_ALL;
430#else
431 cd->cpumask = cpumask_of_cpu(cpu);
432#endif
433 cd->set_next_event = mips_next_event;
434 cd->set_mode = mips_set_mode;
435 cd->event_handler = mips_event_handler;
436
437 clockevents_register_device(cd);
438
439 if (!cp0_timer_irq_installed) {
440#ifdef CONFIG_MIPS_MT_SMTC
441#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
442 setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
443#else
444 setup_irq(irq, &timer_irqaction);
445#endif /* CONFIG_MIPS_MT_SMTC */
446 cp0_timer_irq_installed = 1;
447 }
448}
449
450void __init time_init(void)
451{
452 plat_time_init();
373 453
374 /* Choose appropriate high precision timer routines. */ 454 /* Choose appropriate high precision timer routines. */
375 if (!cpu_has_counter && !clocksource_mips.read) 455 if (!cpu_has_counter && !clocksource_mips.read)
@@ -392,11 +472,6 @@ void __init time_init(void)
392 /* Calculate cache parameters. */ 472 /* Calculate cache parameters. */
393 cycles_per_jiffy = 473 cycles_per_jiffy =
394 (mips_hpt_frequency + HZ / 2) / HZ; 474 (mips_hpt_frequency + HZ / 2) / HZ;
395 /*
396 * This sets up the high precision
397 * timer for the first interrupt.
398 */
399 c0_hpt_timer_init();
400 } 475 }
401 } 476 }
402 if (!mips_hpt_frequency) 477 if (!mips_hpt_frequency)
@@ -406,6 +481,10 @@ void __init time_init(void)
406 printk("Using %u.%03u MHz high precision timer.\n", 481 printk("Using %u.%03u MHz high precision timer.\n",
407 ((mips_hpt_frequency + 500) / 1000) / 1000, 482 ((mips_hpt_frequency + 500) / 1000) / 1000,
408 ((mips_hpt_frequency + 500) / 1000) % 1000); 483 ((mips_hpt_frequency + 500) / 1000) % 1000);
484
485#ifdef CONFIG_IRQ_CPU
486 setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
487#endif
409 } 488 }
410 489
411 if (!mips_timer_ack) 490 if (!mips_timer_ack)
@@ -426,56 +505,5 @@ void __init time_init(void)
426 plat_timer_setup(&timer_irqaction); 505 plat_timer_setup(&timer_irqaction);
427 506
428 init_mips_clocksource(); 507 init_mips_clocksource();
508 mips_clockevent_init();
429} 509}
430
431#define FEBRUARY 2
432#define STARTOFTIME 1970
433#define SECDAY 86400L
434#define SECYR (SECDAY * 365)
435#define leapyear(y) ((!((y) % 4) && ((y) % 100)) || !((y) % 400))
436#define days_in_year(y) (leapyear(y) ? 366 : 365)
437#define days_in_month(m) (month_days[(m) - 1])
438
439static int month_days[12] = {
440 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
441};
442
443void to_tm(unsigned long tim, struct rtc_time *tm)
444{
445 long hms, day, gday;
446 int i;
447
448 gday = day = tim / SECDAY;
449 hms = tim % SECDAY;
450
451 /* Hours, minutes, seconds are easy */
452 tm->tm_hour = hms / 3600;
453 tm->tm_min = (hms % 3600) / 60;
454 tm->tm_sec = (hms % 3600) % 60;
455
456 /* Number of years in days */
457 for (i = STARTOFTIME; day >= days_in_year(i); i++)
458 day -= days_in_year(i);
459 tm->tm_year = i;
460
461 /* Number of months in days left */
462 if (leapyear(tm->tm_year))
463 days_in_month(FEBRUARY) = 29;
464 for (i = 1; day >= days_in_month(i); i++)
465 day -= days_in_month(i);
466 days_in_month(FEBRUARY) = 28;
467 tm->tm_mon = i - 1; /* tm_mon starts from 0 to 11 */
468
469 /* Days are what is left over (+1) from all that. */
470 tm->tm_mday = day + 1;
471
472 /*
473 * Determine the day of week
474 */
475 tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */
476}
477
478EXPORT_SYMBOL(rtc_lock);
479EXPORT_SYMBOL(to_tm);
480EXPORT_SYMBOL(rtc_mips_set_time);
481EXPORT_SYMBOL(rtc_mips_get_time);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 6379003f9d8d..632bce1bf420 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -295,7 +295,8 @@ void show_regs(struct pt_regs *regs)
295 if (1 <= cause && cause <= 5) 295 if (1 <= cause && cause <= 5)
296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
297 297
298 printk("PrId : %08x\n", read_c0_prid()); 298 printk("PrId : %08x (%s)\n", read_c0_prid(),
299 cpu_name_string());
299} 300}
300 301
301void show_registers(struct pt_regs *regs) 302void show_registers(struct pt_regs *regs)
@@ -627,7 +628,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
627 lose_fpu(1); 628 lose_fpu(1);
628 629
629 /* Run the emulator */ 630 /* Run the emulator */
630 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1); 631 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
631 632
632 /* 633 /*
633 * We can't allow the emulated instruction to leave any of 634 * We can't allow the emulated instruction to leave any of
@@ -954,7 +955,7 @@ asmlinkage void do_reserved(struct pt_regs *regs)
954 */ 955 */
955static inline void parity_protection_init(void) 956static inline void parity_protection_init(void)
956{ 957{
957 switch (current_cpu_data.cputype) { 958 switch (current_cpu_type()) {
958 case CPU_24K: 959 case CPU_24K:
959 case CPU_34K: 960 case CPU_34K:
960 case CPU_5KC: 961 case CPU_5KC:
@@ -1075,8 +1076,8 @@ void *set_except_vector(int n, void *addr)
1075 1076
1076 exception_handlers[n] = handler; 1077 exception_handlers[n] = handler;
1077 if (n == 0 && cpu_has_divec) { 1078 if (n == 0 && cpu_has_divec) {
1078 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1079 *(u32 *)(ebase + 0x200) = 0x08000000 |
1079 (0x03ffffff & (handler >> 2)); 1080 (0x03ffffff & (handler >> 2));
1080 flush_icache_range(ebase + 0x200, ebase + 0x204); 1081 flush_icache_range(ebase + 0x200, ebase + 0x204);
1081 } 1082 }
1082 return (void *)old_handler; 1083 return (void *)old_handler;
@@ -1165,11 +1166,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1165 1166
1166 if (cpu_has_veic) { 1167 if (cpu_has_veic) {
1167 if (board_bind_eic_interrupt) 1168 if (board_bind_eic_interrupt)
1168 board_bind_eic_interrupt (n, srs); 1169 board_bind_eic_interrupt(n, srs);
1169 } else if (cpu_has_vint) { 1170 } else if (cpu_has_vint) {
1170 /* SRSMap is only defined if shadow sets are implemented */ 1171 /* SRSMap is only defined if shadow sets are implemented */
1171 if (mips_srs_max() > 1) 1172 if (mips_srs_max() > 1)
1172 change_c0_srsmap (0xf << n*4, srs << n*4); 1173 change_c0_srsmap(0xf << n*4, srs << n*4);
1173 } 1174 }
1174 1175
1175 if (srs == 0) { 1176 if (srs == 0) {
@@ -1198,10 +1199,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1198 * Sigh... panicing won't help as the console 1199 * Sigh... panicing won't help as the console
1199 * is probably not configured :( 1200 * is probably not configured :(
1200 */ 1201 */
1201 panic ("VECTORSPACING too small"); 1202 panic("VECTORSPACING too small");
1202 } 1203 }
1203 1204
1204 memcpy (b, &except_vec_vi, handler_len); 1205 memcpy(b, &except_vec_vi, handler_len);
1205#ifdef CONFIG_MIPS_MT_SMTC 1206#ifdef CONFIG_MIPS_MT_SMTC
1206 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1207 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1207 1208
@@ -1370,9 +1371,9 @@ void __init per_cpu_trap_init(void)
1370#endif /* CONFIG_MIPS_MT_SMTC */ 1371#endif /* CONFIG_MIPS_MT_SMTC */
1371 1372
1372 if (cpu_has_veic || cpu_has_vint) { 1373 if (cpu_has_veic || cpu_has_vint) {
1373 write_c0_ebase (ebase); 1374 write_c0_ebase(ebase);
1374 /* Setting vector spacing enables EI/VI mode */ 1375 /* Setting vector spacing enables EI/VI mode */
1375 change_c0_intctl (0x3e0, VECTORSPACING); 1376 change_c0_intctl(0x3e0, VECTORSPACING);
1376 } 1377 }
1377 if (cpu_has_divec) { 1378 if (cpu_has_divec) {
1378 if (cpu_has_mipsmt) { 1379 if (cpu_has_mipsmt) {
@@ -1390,8 +1391,8 @@ void __init per_cpu_trap_init(void)
1390 * o read IntCtl.IPPCI to determine the performance counter interrupt 1391 * o read IntCtl.IPPCI to determine the performance counter interrupt
1391 */ 1392 */
1392 if (cpu_has_mips_r2) { 1393 if (cpu_has_mips_r2) {
1393 cp0_compare_irq = (read_c0_intctl () >> 29) & 7; 1394 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1394 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; 1395 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1395 if (cp0_perfcount_irq == cp0_compare_irq) 1396 if (cp0_perfcount_irq == cp0_compare_irq)
1396 cp0_perfcount_irq = -1; 1397 cp0_perfcount_irq = -1;
1397 } else { 1398 } else {
@@ -1429,14 +1430,17 @@ void __init per_cpu_trap_init(void)
1429} 1430}
1430 1431
1431/* Install CPU exception handler */ 1432/* Install CPU exception handler */
1432void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1433void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1433{ 1434{
1434 memcpy((void *)(ebase + offset), addr, size); 1435 memcpy((void *)(ebase + offset), addr, size);
1435 flush_icache_range(ebase + offset, ebase + offset + size); 1436 flush_icache_range(ebase + offset, ebase + offset + size);
1436} 1437}
1437 1438
1439static char panic_null_cerr[] __initdata =
1440 "Trying to set NULL cache error exception handler";
1441
1438/* Install uncached CPU exception handler */ 1442/* Install uncached CPU exception handler */
1439void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1443void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
1440{ 1444{
1441#ifdef CONFIG_32BIT 1445#ifdef CONFIG_32BIT
1442 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1446 unsigned long uncached_ebase = KSEG1ADDR(ebase);
@@ -1445,6 +1449,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
1445 unsigned long uncached_ebase = TO_UNCAC(ebase); 1449 unsigned long uncached_ebase = TO_UNCAC(ebase);
1446#endif 1450#endif
1447 1451
1452 if (!addr)
1453 panic(panic_null_cerr);
1454
1448 memcpy((void *)(uncached_ebase + offset), addr, size); 1455 memcpy((void *)(uncached_ebase + offset), addr, size);
1449} 1456}
1450 1457
@@ -1464,7 +1471,7 @@ void __init trap_init(void)
1464 unsigned long i; 1471 unsigned long i;
1465 1472
1466 if (cpu_has_veic || cpu_has_vint) 1473 if (cpu_has_veic || cpu_has_vint)
1467 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1474 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1468 else 1475 else
1469 ebase = CAC_BASE; 1476 ebase = CAC_BASE;
1470 1477
@@ -1490,7 +1497,7 @@ void __init trap_init(void)
1490 * destination. 1497 * destination.
1491 */ 1498 */
1492 if (cpu_has_ejtag && board_ejtag_handler_setup) 1499 if (cpu_has_ejtag && board_ejtag_handler_setup)
1493 board_ejtag_handler_setup (); 1500 board_ejtag_handler_setup();
1494 1501
1495 /* 1502 /*
1496 * Only some CPUs have the watch exceptions. 1503 * Only some CPUs have the watch exceptions.
@@ -1543,8 +1550,8 @@ void __init trap_init(void)
1543 set_except_vector(12, handle_ov); 1550 set_except_vector(12, handle_ov);
1544 set_except_vector(13, handle_tr); 1551 set_except_vector(13, handle_tr);
1545 1552
1546 if (current_cpu_data.cputype == CPU_R6000 || 1553 if (current_cpu_type() == CPU_R6000 ||
1547 current_cpu_data.cputype == CPU_R6000A) { 1554 current_cpu_type() == CPU_R6000A) {
1548 /* 1555 /*
1549 * The R6000 is the only R-series CPU that features a machine 1556 * The R6000 is the only R-series CPU that features a machine
1550 * check exception (similar to the R4000 cache error) and 1557 * check exception (similar to the R4000 cache error) and
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index d34b1fb3665d..c327b21bca81 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -481,7 +481,7 @@ fault:
481 if (fixup_exception(regs)) 481 if (fixup_exception(regs))
482 return; 482 return;
483 483
484 die_if_kernel ("Unhandled kernel unaligned access", regs); 484 die_if_kernel("Unhandled kernel unaligned access", regs);
485 send_sig(SIGSEGV, current, 1); 485 send_sig(SIGSEGV, current, 1);
486 486
487 return; 487 return;
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 087ab997487d..84f9a4cc6f2f 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -6,163 +6,202 @@
6OUTPUT_ARCH(mips) 6OUTPUT_ARCH(mips)
7ENTRY(kernel_entry) 7ENTRY(kernel_entry)
8jiffies = JIFFIES; 8jiffies = JIFFIES;
9
9SECTIONS 10SECTIONS
10{ 11{
11#ifdef CONFIG_BOOT_ELF64 12#ifdef CONFIG_BOOT_ELF64
12 /* Read-only sections, merged into text segment: */ 13 /* Read-only sections, merged into text segment: */
13 /* . = 0xc000000000000000; */ 14 /* . = 0xc000000000000000; */
14 15
15 /* This is the value for an Origin kernel, taken from an IRIX kernel. */ 16 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
16 /* . = 0xc00000000001c000; */ 17 /* . = 0xc00000000001c000; */
17 18
18 /* Set the vaddr for the text segment to a value 19 /* Set the vaddr for the text segment to a value
19 >= 0xa800 0000 0001 9000 if no symmon is going to configured 20 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
20 >= 0xa800 0000 0030 0000 otherwise */ 21 * >= 0xa800 0000 0030 0000 otherwise
22 */
21 23
22 /* . = 0xa800000000300000; */ 24 /* . = 0xa800000000300000; */
23 /* . = 0xa800000000300000; */ 25 /* . = 0xa800000000300000; */
24 . = 0xffffffff80300000; 26 . = 0xffffffff80300000;
25#endif 27#endif
26 . = LOADADDR; 28 . = LOADADDR;
27 /* read-only */ 29 /* read-only */
28 _text = .; /* Text and read-only data */ 30 _text = .; /* Text and read-only data */
29 .text : { 31 .text : {
30 TEXT_TEXT 32 TEXT_TEXT
31 SCHED_TEXT 33 SCHED_TEXT
32 LOCK_TEXT 34 LOCK_TEXT
33 *(.fixup) 35 *(.fixup)
34 *(.gnu.warning) 36 *(.gnu.warning)
35 } =0 37 } =0
36 38 _etext = .; /* End of text section */
37 _etext = .; /* End of text section */ 39
38 40 /* Exception table */
39 . = ALIGN(16); /* Exception table */ 41 . = ALIGN(16);
40 __start___ex_table = .; 42 __ex_table : {
41 __ex_table : { *(__ex_table) } 43 __start___ex_table = .;
42 __stop___ex_table = .; 44 *(__ex_table)
43 45 __stop___ex_table = .;
44 __start___dbe_table = .; /* Exception table for data bus errors */ 46 }
45 __dbe_table : { *(__dbe_table) } 47
46 __stop___dbe_table = .; 48 /* Exception table for data bus errors */
47 49 __dbe_table : {
48 NOTES 50 __start___dbe_table = .;
49 51 *(__dbe_table)
50 RODATA 52 __stop___dbe_table = .;
51 53 }
52 /* writeable */ 54 RODATA
53 .data : { /* Data */ 55
54 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 56 /* writeable */
55 /* 57 .data : { /* Data */
56 * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which 58 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
57 * limits the maximum alignment to at most 32kB and results in the following 59 /*
58 * warning: 60 * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which
59 * 61 * limits the maximum alignment to at most 32kB and results in the following
60 * CC arch/mips/kernel/init_task.o 62 * warning:
61 * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ 63 *
62 * is greater than maximum object file alignment. Using 32768 64 * CC arch/mips/kernel/init_task.o
63 */ 65 * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’
64 . = ALIGN(_PAGE_SIZE); 66 * is greater than maximum object file alignment. Using 32768
65 *(.data.init_task) 67 */
66 68 . = ALIGN(_PAGE_SIZE);
67 DATA_DATA 69 *(.data.init_task)
68 70
69 CONSTRUCTORS 71 DATA_DATA
70 } 72 CONSTRUCTORS
71 _gp = . + 0x8000; 73 }
72 .lit8 : { *(.lit8) } 74 _gp = . + 0x8000;
73 .lit4 : { *(.lit4) } 75 .lit8 : {
74 /* We want the small data sections together, so single-instruction offsets 76 *(.lit8)
75 can access them all, and initialized data all before uninitialized, so 77 }
76 we can shorten the on-disk segment size. */ 78 .lit4 : {
77 .sdata : { *(.sdata) } 79 *(.lit4)
78 80 }
79 . = ALIGN(_PAGE_SIZE); 81 /* We want the small data sections together, so single-instruction offsets
80 __nosave_begin = .; 82 can access them all, and initialized data all before uninitialized, so
81 .data_nosave : { *(.data.nosave) } 83 we can shorten the on-disk segment size. */
82 . = ALIGN(_PAGE_SIZE); 84 .sdata : {
83 __nosave_end = .; 85 *(.sdata)
84 86 }
85 . = ALIGN(32); 87
86 .data.cacheline_aligned : { *(.data.cacheline_aligned) } 88 . = ALIGN(_PAGE_SIZE);
87 89 .data_nosave : {
88 _edata = .; /* End of data section */ 90 __nosave_begin = .;
89 91 *(.data.nosave)
90 /* will be freed after init */ 92 }
91 . = ALIGN(_PAGE_SIZE); /* Init code and data */ 93 . = ALIGN(_PAGE_SIZE);
92 __init_begin = .; 94 __nosave_end = .;
93 .init.text : { 95
94 _sinittext = .; 96 . = ALIGN(32);
95 *(.init.text) 97 .data.cacheline_aligned : {
96 _einittext = .; 98 *(.data.cacheline_aligned)
97 } 99 }
98 .init.data : { *(.init.data) } 100 _edata = .; /* End of data section */
99 . = ALIGN(16); 101
100 __setup_start = .; 102 /* will be freed after init */
101 .init.setup : { *(.init.setup) } 103 . = ALIGN(_PAGE_SIZE); /* Init code and data */
102 __setup_end = .; 104 __init_begin = .;
103 105 .init.text : {
104 __initcall_start = .; 106 _sinittext = .;
105 .initcall.init : { 107 *(.init.text)
106 INITCALLS 108 _einittext = .;
107 } 109 }
108 __initcall_end = .; 110 .init.data : {
109 111 *(.init.data)
110 __con_initcall_start = .; 112 }
111 .con_initcall.init : { *(.con_initcall.init) } 113 . = ALIGN(16);
112 __con_initcall_end = .; 114 .init.setup : {
113 SECURITY_INIT 115 __setup_start = .;
114 /* .exit.text is discarded at runtime, not link time, to deal with 116 *(.init.setup)
115 references from .rodata */ 117 __setup_end = .;
116 .exit.text : { *(.exit.text) } 118 }
117 .exit.data : { *(.exit.data) } 119
120 .initcall.init : {
121 __initcall_start = .;
122 INITCALLS
123 __initcall_end = .;
124 }
125
126 .con_initcall.init : {
127 __con_initcall_start = .;
128 *(.con_initcall.init)
129 __con_initcall_end = .;
130 }
131 SECURITY_INIT
132
133 /* .exit.text is discarded at runtime, not link time, to deal with
134 * references from .rodata
135 */
136 .exit.text : {
137 *(.exit.text)
138 }
139 .exit.data : {
140 *(.exit.data)
141 }
118#if defined(CONFIG_BLK_DEV_INITRD) 142#if defined(CONFIG_BLK_DEV_INITRD)
119 . = ALIGN(_PAGE_SIZE); 143 . = ALIGN(_PAGE_SIZE);
120 __initramfs_start = .; 144 .init.ramfs : {
121 .init.ramfs : { *(.init.ramfs) } 145 __initramfs_start = .;
122 __initramfs_end = .; 146 *(.init.ramfs)
147 __initramfs_end = .;
148 }
123#endif 149#endif
124 PERCPU(_PAGE_SIZE) 150 PERCPU(_PAGE_SIZE)
125 . = ALIGN(_PAGE_SIZE); 151 . = ALIGN(_PAGE_SIZE);
126 __init_end = .; 152 __init_end = .;
127 /* freed after init ends here */ 153 /* freed after init ends here */
128 154
129 __bss_start = .; /* BSS */ 155 __bss_start = .; /* BSS */
130 .sbss : { 156 .sbss : {
131 *(.sbss) 157 *(.sbss)
132 *(.scommon) 158 *(.scommon)
133 } 159 }
134 .bss : { 160 .bss : {
135 *(.bss) 161 *(.bss)
136 *(COMMON) 162 *(COMMON)
137 } 163 }
138 __bss_stop = .; 164 __bss_stop = .;
139 165
140 _end = . ; 166 _end = . ;
141 167
142 /* Sections to be discarded */ 168 /* Sections to be discarded */
143 /DISCARD/ : { 169 /DISCARD/ : {
144 *(.exitcall.exit) 170 *(.exitcall.exit)
145 171
146 /* ABI crap starts here */ 172 /* ABI crap starts here */
147 *(.MIPS.options) 173 *(.MIPS.options)
148 *(.options) 174 *(.options)
149 *(.pdr) 175 *(.pdr)
150 *(.reginfo) 176 *(.reginfo)
151 } 177 }
152 178
153 /* These mark the ABI of the kernel for debuggers. */ 179 /* These mark the ABI of the kernel for debuggers. */
154 .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) } 180 .mdebug.abi32 : {
155 .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) } 181 KEEP(*(.mdebug.abi32))
156 182 }
157 /* This is the MIPS specific mdebug section. */ 183 .mdebug.abi64 : {
158 .mdebug : { *(.mdebug) } 184 KEEP(*(.mdebug.abi64))
159 185 }
160 STABS_DEBUG 186
161 187 /* This is the MIPS specific mdebug section. */
162 DWARF_DEBUG 188 .mdebug : {
163 189 *(.mdebug)
164 /* These must appear regardless of . */ 190 }
165 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } 191
166 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } 192 STABS_DEBUG
167 .note : { *(.note) } 193 DWARF_DEBUG
194
195 /* These must appear regardless of . */
196 .gptab.sdata : {
197 *(.gptab.data)
198 *(.gptab.sdata)
199 }
200 .gptab.sbss : {
201 *(.gptab.bss)
202 *(.gptab.sbss)
203 }
204 .note : {
205 *(.note)
206 }
168} 207}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 3c09b9785f4c..61b729fa0548 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -936,8 +936,18 @@ static int vpe_elfload(struct vpe * v)
936 936
937 } 937 }
938 } else { 938 } else {
939 for (i = 0; i < hdr->e_shnum; i++) { 939 struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
940 940
941 for (i = 0; i < hdr->e_phnum; i++) {
942 if (phdr->p_type != PT_LOAD)
943 continue;
944
945 memcpy((void *)phdr->p_vaddr, (char *)hdr + phdr->p_offset, phdr->p_filesz);
946 memset((void *)phdr->p_vaddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz);
947 phdr++;
948 }
949
950 for (i = 0; i < hdr->e_shnum; i++) {
941 /* Internal symbols and strings. */ 951 /* Internal symbols and strings. */
942 if (sechdrs[i].sh_type == SHT_SYMTAB) { 952 if (sechdrs[i].sh_type == SHT_SYMTAB) {
943 symindex = i; 953 symindex = i;
@@ -948,39 +958,6 @@ static int vpe_elfload(struct vpe * v)
948 magic symbols */ 958 magic symbols */
949 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 959 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
950 } 960 }
951
952 /* filter sections we dont want in the final image */
953 if (!(sechdrs[i].sh_flags & SHF_ALLOC) ||
954 (sechdrs[i].sh_type == SHT_MIPS_REGINFO)) {
955 printk( KERN_DEBUG " ignoring section, "
956 "name %s type %x address 0x%x \n",
957 secstrings + sechdrs[i].sh_name,
958 sechdrs[i].sh_type, sechdrs[i].sh_addr);
959 continue;
960 }
961
962 if (sechdrs[i].sh_addr < (unsigned int)v->load_addr) {
963 printk( KERN_WARNING "VPE loader: "
964 "fully linked image has invalid section, "
965 "name %s type %x address 0x%x, before load "
966 "address of 0x%x\n",
967 secstrings + sechdrs[i].sh_name,
968 sechdrs[i].sh_type, sechdrs[i].sh_addr,
969 (unsigned int)v->load_addr);
970 return -ENOEXEC;
971 }
972
973 printk(KERN_DEBUG " copying section sh_name %s, sh_addr 0x%x "
974 "size 0x%x0 from x%p\n",
975 secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr,
976 sechdrs[i].sh_size, hdr + sechdrs[i].sh_offset);
977
978 if (sechdrs[i].sh_type != SHT_NOBITS)
979 memcpy((void *)sechdrs[i].sh_addr,
980 (char *)hdr + sechdrs[i].sh_offset,
981 sechdrs[i].sh_size);
982 else
983 memset((void *)sechdrs[i].sh_addr, 0, sechdrs[i].sh_size);
984 } 961 }
985 } 962 }
986 963
@@ -1044,7 +1021,7 @@ static int getcwd(char *buff, int size)
1044 old_fs = get_fs(); 1021 old_fs = get_fs();
1045 set_fs(KERNEL_DS); 1022 set_fs(KERNEL_DS);
1046 1023
1047 ret = sys_getcwd(buff,size); 1024 ret = sys_getcwd(buff, size);
1048 1025
1049 set_fs(old_fs); 1026 set_fs(old_fs);
1050 1027
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
new file mode 100644
index 000000000000..1d2ee8a9be13
--- /dev/null
+++ b/arch/mips/lasat/Kconfig
@@ -0,0 +1,15 @@
1config PICVUE
2 tristate "PICVUE LCD display driver"
3 depends on LASAT
4
5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE
8
9config DS1603
10 bool "DS1603 RTC driver"
11 depends on LASAT
12
13config LASAT_SYSCTL
14 bool "LASAT sysctl interface"
15 depends on LASAT
diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
new file mode 100644
index 000000000000..33791609fe99
--- /dev/null
+++ b/arch/mips/lasat/Makefile
@@ -0,0 +1,16 @@
1#
2# Makefile for the LASAT specific kernel interface routines under Linux.
3#
4
5obj-y += reset.o setup.o prom.o lasat_board.o \
6 at93c.o interrupt.o serial.o
7
8obj-$(CONFIG_LASAT_SYSCTL) += sysctl.o
9obj-$(CONFIG_DS1603) += ds1603.o
10obj-$(CONFIG_PICVUE) += picvue.o
11obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o
12
13clean:
14 make -C image clean
15
16EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
new file mode 100644
index 000000000000..793e234719a6
--- /dev/null
+++ b/arch/mips/lasat/at93c.c
@@ -0,0 +1,149 @@
1/*
2 * Atmel AT93C46 serial eeprom driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <asm/lasat/lasat.h>
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "at93c.h"
14
15#define AT93C_ADDR_SHIFT 7
16#define AT93C_ADDR_MAX ((1 << AT93C_ADDR_SHIFT) - 1)
17#define AT93C_RCMD (0x6 << AT93C_ADDR_SHIFT)
18#define AT93C_WCMD (0x5 << AT93C_ADDR_SHIFT)
19#define AT93C_WENCMD 0x260
20#define AT93C_WDSCMD 0x200
21
22struct at93c_defs *at93c;
23
24static void at93c_reg_write(u32 val)
25{
26 *at93c->reg = val;
27}
28
29static u32 at93c_reg_read(void)
30{
31 u32 tmp = *at93c->reg;
32 return tmp;
33}
34
35static u32 at93c_datareg_read(void)
36{
37 u32 tmp = *at93c->rdata_reg;
38 return tmp;
39}
40
41static void at93c_cycle_clk(u32 data)
42{
43 at93c_reg_write(data | at93c->clk);
44 lasat_ndelay(250);
45 at93c_reg_write(data & ~at93c->clk);
46 lasat_ndelay(250);
47}
48
49static void at93c_write_databit(u8 bit)
50{
51 u32 data = at93c_reg_read();
52 if (bit)
53 data |= 1 << at93c->wdata_shift;
54 else
55 data &= ~(1 << at93c->wdata_shift);
56
57 at93c_reg_write(data);
58 lasat_ndelay(100);
59 at93c_cycle_clk(data);
60}
61
62static unsigned int at93c_read_databit(void)
63{
64 u32 data;
65
66 at93c_cycle_clk(at93c_reg_read());
67 data = (at93c_datareg_read() >> at93c->rdata_shift) & 1;
68 return data;
69}
70
71static u8 at93c_read_byte(void)
72{
73 int i;
74 u8 data = 0;
75
76 for (i = 0; i <= 7; i++) {
77 data <<= 1;
78 data |= at93c_read_databit();
79 }
80 return data;
81}
82
83static void at93c_write_bits(u32 data, int size)
84{
85 int i;
86 int shift = size - 1;
87 u32 mask = (1 << shift);
88
89 for (i = 0; i < size; i++) {
90 at93c_write_databit((data & mask) >> shift);
91 data <<= 1;
92 }
93}
94
95static void at93c_init_op(void)
96{
97 at93c_reg_write((at93c_reg_read() | at93c->cs) &
98 ~at93c->clk & ~(1 << at93c->rdata_shift));
99 lasat_ndelay(50);
100}
101
102static void at93c_end_op(void)
103{
104 at93c_reg_write(at93c_reg_read() & ~at93c->cs);
105 lasat_ndelay(250);
106}
107
108static void at93c_wait(void)
109{
110 at93c_init_op();
111 while (!at93c_read_databit())
112 ;
113 at93c_end_op();
114};
115
116static void at93c_disable_wp(void)
117{
118 at93c_init_op();
119 at93c_write_bits(AT93C_WENCMD, 10);
120 at93c_end_op();
121}
122
123static void at93c_enable_wp(void)
124{
125 at93c_init_op();
126 at93c_write_bits(AT93C_WDSCMD, 10);
127 at93c_end_op();
128}
129
130u8 at93c_read(u8 addr)
131{
132 u8 byte;
133 at93c_init_op();
134 at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_RCMD, 10);
135 byte = at93c_read_byte();
136 at93c_end_op();
137 return byte;
138}
139
140void at93c_write(u8 addr, u8 data)
141{
142 at93c_disable_wp();
143 at93c_init_op();
144 at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_WCMD, 10);
145 at93c_write_bits(data, 8);
146 at93c_end_op();
147 at93c_wait();
148 at93c_enable_wp();
149}
diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h
new file mode 100644
index 000000000000..cfe2f99b1d44
--- /dev/null
+++ b/arch/mips/lasat/at93c.h
@@ -0,0 +1,18 @@
1/*
2 * Atmel AT93C46 serial eeprom driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7
8extern struct at93c_defs {
9 volatile u32 *reg;
10 volatile u32 *rdata_reg;
11 int rdata_shift;
12 int wdata_shift;
13 u32 cs;
14 u32 clk;
15} *at93c;
16
17u8 at93c_read(u8 addr);
18void at93c_write(u8 addr, u8 data);
diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c
new file mode 100644
index 000000000000..52cb1436a12a
--- /dev/null
+++ b/arch/mips/lasat/ds1603.c
@@ -0,0 +1,183 @@
1/*
2 * Dallas Semiconductors 1603 RTC driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#include <linux/kernel.h>
8#include <asm/lasat/lasat.h>
9#include <linux/delay.h>
10#include <asm/lasat/ds1603.h>
11#include <asm/time.h>
12
13#include "ds1603.h"
14
15#define READ_TIME_CMD 0x81
16#define SET_TIME_CMD 0x80
17#define TRIMMER_SET_CMD 0xC0
18#define TRIMMER_VALUE_MASK 0x38
19#define TRIMMER_SHIFT 3
20
21struct ds_defs *ds1603;
22
23/* HW specific register functions */
24static void rtc_reg_write(unsigned long val)
25{
26 *ds1603->reg = val;
27}
28
29static unsigned long rtc_reg_read(void)
30{
31 unsigned long tmp = *ds1603->reg;
32 return tmp;
33}
34
35static unsigned long rtc_datareg_read(void)
36{
37 unsigned long tmp = *ds1603->data_reg;
38 return tmp;
39}
40
41static void rtc_nrst_high(void)
42{
43 rtc_reg_write(rtc_reg_read() | ds1603->rst);
44}
45
46static void rtc_nrst_low(void)
47{
48 rtc_reg_write(rtc_reg_read() & ~ds1603->rst);
49}
50
51static void rtc_cycle_clock(unsigned long data)
52{
53 data |= ds1603->clk;
54 rtc_reg_write(data);
55 lasat_ndelay(250);
56 if (ds1603->data_reversed)
57 data &= ~ds1603->data;
58 else
59 data |= ds1603->data;
60 data &= ~ds1603->clk;
61 rtc_reg_write(data);
62 lasat_ndelay(250 + ds1603->huge_delay);
63}
64
65static void rtc_write_databit(unsigned int bit)
66{
67 unsigned long data = rtc_reg_read();
68 if (ds1603->data_reversed)
69 bit = !bit;
70 if (bit)
71 data |= ds1603->data;
72 else
73 data &= ~ds1603->data;
74
75 rtc_reg_write(data);
76 lasat_ndelay(50 + ds1603->huge_delay);
77 rtc_cycle_clock(data);
78}
79
80static unsigned int rtc_read_databit(void)
81{
82 unsigned int data;
83
84 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
85 >> ds1603->data_read_shift;
86 rtc_cycle_clock(rtc_reg_read());
87 return data;
88}
89
90static void rtc_write_byte(unsigned int byte)
91{
92 int i;
93
94 for (i = 0; i <= 7; i++) {
95 rtc_write_databit(byte & 1L);
96 byte >>= 1;
97 }
98}
99
100static void rtc_write_word(unsigned long word)
101{
102 int i;
103
104 for (i = 0; i <= 31; i++) {
105 rtc_write_databit(word & 1L);
106 word >>= 1;
107 }
108}
109
110static unsigned long rtc_read_word(void)
111{
112 int i;
113 unsigned long word = 0;
114 unsigned long shift = 0;
115
116 for (i = 0; i <= 31; i++) {
117 word |= rtc_read_databit() << shift;
118 shift++;
119 }
120 return word;
121}
122
123static void rtc_init_op(void)
124{
125 rtc_nrst_high();
126
127 rtc_reg_write(rtc_reg_read() & ~ds1603->clk);
128
129 lasat_ndelay(50);
130}
131
132static void rtc_end_op(void)
133{
134 rtc_nrst_low();
135 lasat_ndelay(1000);
136}
137
138unsigned long read_persistent_clock(void)
139{
140 unsigned long word;
141 unsigned long flags;
142
143 spin_lock_irqsave(&rtc_lock, flags);
144 rtc_init_op();
145 rtc_write_byte(READ_TIME_CMD);
146 word = rtc_read_word();
147 rtc_end_op();
148 spin_unlock_irqrestore(&rtc_lock, flags);
149
150 return word;
151}
152
153int rtc_mips_set_mmss(unsigned long time)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&rtc_lock, flags);
158 rtc_init_op();
159 rtc_write_byte(SET_TIME_CMD);
160 rtc_write_word(time);
161 rtc_end_op();
162 spin_unlock_irqrestore(&rtc_lock, flags);
163
164 return 0;
165}
166
167void ds1603_set_trimmer(unsigned int trimval)
168{
169 rtc_init_op();
170 rtc_write_byte(((trimval << TRIMMER_SHIFT) & TRIMMER_VALUE_MASK)
171 | (TRIMMER_SET_CMD));
172 rtc_end_op();
173}
174
175void ds1603_disable(void)
176{
177 ds1603_set_trimmer(TRIMMER_DISABLE_RTC);
178}
179
180void ds1603_enable(void)
181{
182 ds1603_set_trimmer(TRIMMER_DEFAULT);
183}
diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h
new file mode 100644
index 000000000000..2da3704044fd
--- /dev/null
+++ b/arch/mips/lasat/ds1603.h
@@ -0,0 +1,31 @@
1/*
2 * Dallas Semiconductors 1603 RTC driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#ifndef __DS1603_H
8#define __DS1603_H
9
10struct ds_defs {
11 volatile u32 *reg;
12 volatile u32 *data_reg;
13 u32 rst;
14 u32 clk;
15 u32 data;
16 u32 data_read_shift;
17 char data_reversed;
18 u32 huge_delay;
19};
20
21extern struct ds_defs *ds1603;
22
23void ds1603_set_trimmer(unsigned int);
24void ds1603_enable(void);
25void ds1603_disable(void);
26void ds1603_init(struct ds_defs *);
27
28#define TRIMMER_DEFAULT 3
29#define TRIMMER_DISABLE_RTC 0
30
31#endif
diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
new file mode 100644
index 000000000000..5332449ec040
--- /dev/null
+++ b/arch/mips/lasat/image/Makefile
@@ -0,0 +1,54 @@
1#
2# MAKEFILE FOR THE MIPS LINUX BOOTLOADER AND ROM DEBUGGER
3#
4# i-data Networks
5#
6# Author: Thomas Horsten <thh@i-data.com>
7#
8
9ifndef Version
10 Version = "$(USER)-test"
11endif
12
13MKLASATIMG = mklasatimg
14MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200
15KERNEL_IMAGE = $(TOPDIR)/vmlinux
16KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ )
17KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ )
18
19LDSCRIPT= -L$(obj) -Tromscript.normal
20
21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
22 -D_kernel_entry=0x$(KERNEL_ENTRY) \
23 -D VERSION="\"$(Version)\"" \
24 -D TIMESTAMP=$(shell date +%s)
25
26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
28
29OBJECTS = head.o kImage.o
30
31rom.sw: $(obj)/rom.sw
32rom.bin: $(obj)/rom.bin
33
34$(obj)/rom.sw: $(obj)/rom.bin
35 $(MKLASATIMG) -o $@ -k $^ -m $(MKLASATIMG_ARCH)
36
37$(obj)/rom.bin: $(obj)/rom
38 $(OBJCOPY) -O binary -S $^ $@
39
40# Rule to make the bootloader
41$(obj)/rom: $(addprefix $(obj)/,$(OBJECTS))
42 $(LD) $(LDFLAGS) $(LDSCRIPT) -o $@ $^
43
44$(obj)/%.o: $(obj)/%.gz
45 $(LD) -r -o $@ -b binary $<
46
47$(obj)/%.gz: $(obj)/%.bin
48 gzip -cf -9 $< > $@
49
50$(obj)/kImage.bin: $(KERNEL_IMAGE)
51 $(OBJCOPY) -O binary -S $^ $@
52
53clean:
54 rm -f rom rom.bin rom.sw kImage.bin kImage.o
diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S
new file mode 100644
index 000000000000..efb95f2609c2
--- /dev/null
+++ b/arch/mips/lasat/image/head.S
@@ -0,0 +1,31 @@
1#include <asm/lasat/head.h>
2
3 .text
4 .section .text.start, "ax"
5 .set noreorder
6 .set mips3
7
8 /* Magic words identifying a software image */
9 .word LASAT_K_MAGIC0_VAL
10 .word LASAT_K_MAGIC1_VAL
11
12 /* Image header version */
13 .word 0x00000002
14
15 /* image start and size */
16 .word _image_start
17 .word _image_size
18
19 /* start of kernel and entrypoint in uncompressed image */
20 .word _kernel_start
21 .word _kernel_entry
22
23 /* Here we have room for future flags */
24
25 .org 0x40
26reldate:
27 .word TIMESTAMP
28
29 .org 0x50
30release:
31 .string VERSION
diff --git a/arch/mips/lasat/image/romscript.normal b/arch/mips/lasat/image/romscript.normal
new file mode 100644
index 000000000000..988f8ad189cb
--- /dev/null
+++ b/arch/mips/lasat/image/romscript.normal
@@ -0,0 +1,23 @@
1OUTPUT_ARCH(mips)
2
3SECTIONS
4{
5 .text :
6 {
7 *(.text.start)
8 }
9
10 /* Data in ROM */
11
12 .data ALIGN(0x10) :
13 {
14 *(.data)
15 }
16 _image_start = ADDR(.data);
17 _image_size = SIZEOF(.data);
18
19 .other :
20 {
21 *(.*)
22 }
23}
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
new file mode 100644
index 000000000000..5f35289bfff5
--- /dev/null
+++ b/arch/mips/lasat/interrupt.c
@@ -0,0 +1,130 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines for generic manipulation of the interrupts found on the
19 * Lasat boards.
20 */
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/sched.h>
24#include <linux/slab.h>
25#include <linux/interrupt.h>
26#include <linux/kernel_stat.h>
27
28#include <asm/bootinfo.h>
29#include <asm/lasat/lasatint.h>
30#include <asm/time.h>
31#include <asm/gdb-stub.h>
32
33static volatile int *lasat_int_status;
34static volatile int *lasat_int_mask;
35static volatile int lasat_int_mask_shift;
36
37void disable_lasat_irq(unsigned int irq_nr)
38{
39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
40}
41
42void enable_lasat_irq(unsigned int irq_nr)
43{
44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
45}
46
47static struct irq_chip lasat_irq_type = {
48 .name = "Lasat",
49 .ack = disable_lasat_irq,
50 .mask = disable_lasat_irq,
51 .mask_ack = disable_lasat_irq,
52 .unmask = enable_lasat_irq,
53};
54
55static inline int ls1bit32(unsigned int x)
56{
57 int b = 31, s;
58
59 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
60 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
61 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
62 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
63 s = 1; if (x << 1 == 0) s = 0; b -= s;
64
65 return b;
66}
67
68static unsigned long (*get_int_status)(void);
69
70static unsigned long get_int_status_100(void)
71{
72 return *lasat_int_status & *lasat_int_mask;
73}
74
75static unsigned long get_int_status_200(void)
76{
77 unsigned long int_status;
78
79 int_status = *lasat_int_status;
80 int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff;
81 return int_status;
82}
83
84asmlinkage void plat_irq_dispatch(void)
85{
86 unsigned long int_status;
87 unsigned int cause = read_c0_cause();
88 int irq;
89
90 if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
91 ll_timer_interrupt(7);
92 return;
93 }
94
95 int_status = get_int_status();
96
97 /* if int_status == 0, then the interrupt has already been cleared */
98 if (int_status) {
99 irq = ls1bit32(int_status);
100
101 do_IRQ(irq);
102 }
103}
104
105void __init arch_init_irq(void)
106{
107 int i;
108
109 switch (mips_machtype) {
110 case MACH_LASAT_100:
111 lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
112 lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
113 lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
114 get_int_status = get_int_status_100;
115 *lasat_int_mask = 0;
116 break;
117 case MACH_LASAT_200:
118 lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
119 lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
120 lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
121 get_int_status = get_int_status_200;
122 *lasat_int_mask &= 0xffff;
123 break;
124 default:
125 panic("arch_init_irq: mips_machtype incorrect");
126 }
127
128 for (i = 0; i <= LASATINT_END; i++)
129 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
130}
diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c
new file mode 100644
index 000000000000..ec2f658c3709
--- /dev/null
+++ b/arch/mips/lasat/lasat_board.c
@@ -0,0 +1,280 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines specific to the LASAT boards
19 */
20#include <linux/types.h>
21#include <linux/crc32.h>
22#include <asm/lasat/lasat.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/ctype.h>
26#include <asm/bootinfo.h>
27#include <asm/addrspace.h>
28#include "at93c.h"
29/* New model description table */
30#include "lasat_models.h"
31
32#define EEPROM_CRC(data, len) (~crc32(~0, data, len))
33
34struct lasat_info lasat_board_info;
35
36void update_bcastaddr(void);
37
38int EEPROMRead(unsigned int pos, unsigned char *data, int len)
39{
40 int i;
41
42 for (i = 0; i < len; i++)
43 *data++ = at93c_read(pos++);
44
45 return 0;
46}
47
48int EEPROMWrite(unsigned int pos, unsigned char *data, int len)
49{
50 int i;
51
52 for (i = 0; i < len; i++)
53 at93c_write(pos++, *data++);
54
55 return 0;
56}
57
58static void init_flash_sizes(void)
59{
60 unsigned long *lb = lasat_board_info.li_flashpart_base;
61 unsigned long *ls = lasat_board_info.li_flashpart_size;
62 int i;
63
64 ls[LASAT_MTD_BOOTLOADER] = 0x40000;
65 ls[LASAT_MTD_SERVICE] = 0xC0000;
66 ls[LASAT_MTD_NORMAL] = 0x100000;
67
68 if (mips_machtype == MACH_LASAT_100) {
69 lasat_board_info.li_flash_base = 0x1e000000;
70
71 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000;
72
73 if (lasat_board_info.li_flash_size > 0x200000) {
74 ls[LASAT_MTD_CONFIG] = 0x100000;
75 ls[LASAT_MTD_FS] = 0x500000;
76 }
77 } else {
78 lasat_board_info.li_flash_base = 0x10000000;
79
80 if (lasat_board_info.li_flash_size < 0x1000000) {
81 lb[LASAT_MTD_BOOTLOADER] = 0x10000000;
82 ls[LASAT_MTD_CONFIG] = 0x100000;
83 if (lasat_board_info.li_flash_size >= 0x400000)
84 ls[LASAT_MTD_FS] =
85 lasat_board_info.li_flash_size - 0x300000;
86 }
87 }
88
89 for (i = 1; i < LASAT_MTD_LAST; i++)
90 lb[i] = lb[i-1] + ls[i-1];
91}
92
93int lasat_init_board_info(void)
94{
95 int c;
96 unsigned long crc;
97 unsigned long cfg0, cfg1;
98 const struct product_info *ppi;
99 int i_n_base_models = N_BASE_MODELS;
100 const char * const * i_txt_base_models = txt_base_models;
101 int i_n_prids = N_PRIDS;
102
103 memset(&lasat_board_info, 0, sizeof(lasat_board_info));
104
105 /* First read the EEPROM info */
106 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
107 sizeof(struct lasat_eeprom_struct));
108
109 /* Check the CRC */
110 crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
111 sizeof(struct lasat_eeprom_struct) - 4);
112
113 if (crc != lasat_board_info.li_eeprom_info.crc32) {
114 printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM CRC does "
115 "not match calculated, attempting to soldier on...\n");
116 }
117
118 if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) {
119 printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM version "
120 "%d, wanted version %d, attempting to soldier on...\n",
121 (unsigned int)lasat_board_info.li_eeprom_info.version,
122 LASAT_EEPROM_VERSION);
123 }
124
125 cfg0 = lasat_board_info.li_eeprom_info.cfg[0];
126 cfg1 = lasat_board_info.li_eeprom_info.cfg[1];
127
128 if (LASAT_W0_DSCTYPE(cfg0) != 1) {
129 printk(KERN_WARNING "WARNING...\nWARNING...\n"
130 "Invalid configuration read from EEPROM, attempting to "
131 "soldier on...");
132 }
133 /* We have a valid configuration */
134
135 switch (LASAT_W0_SDRAMBANKSZ(cfg0)) {
136 case 0:
137 lasat_board_info.li_memsize = 0x0800000;
138 break;
139 case 1:
140 lasat_board_info.li_memsize = 0x1000000;
141 break;
142 case 2:
143 lasat_board_info.li_memsize = 0x2000000;
144 break;
145 case 3:
146 lasat_board_info.li_memsize = 0x4000000;
147 break;
148 case 4:
149 lasat_board_info.li_memsize = 0x8000000;
150 break;
151 default:
152 lasat_board_info.li_memsize = 0;
153 }
154
155 switch (LASAT_W0_SDRAMBANKS(cfg0)) {
156 case 0:
157 break;
158 case 1:
159 lasat_board_info.li_memsize *= 2;
160 break;
161 default:
162 break;
163 }
164
165 switch (LASAT_W0_BUSSPEED(cfg0)) {
166 case 0x0:
167 lasat_board_info.li_bus_hz = 60000000;
168 break;
169 case 0x1:
170 lasat_board_info.li_bus_hz = 66000000;
171 break;
172 case 0x2:
173 lasat_board_info.li_bus_hz = 66666667;
174 break;
175 case 0x3:
176 lasat_board_info.li_bus_hz = 80000000;
177 break;
178 case 0x4:
179 lasat_board_info.li_bus_hz = 83333333;
180 break;
181 case 0x5:
182 lasat_board_info.li_bus_hz = 100000000;
183 break;
184 }
185
186 switch (LASAT_W0_CPUCLK(cfg0)) {
187 case 0x0:
188 lasat_board_info.li_cpu_hz =
189 lasat_board_info.li_bus_hz;
190 break;
191 case 0x1:
192 lasat_board_info.li_cpu_hz =
193 lasat_board_info.li_bus_hz +
194 (lasat_board_info.li_bus_hz >> 1);
195 break;
196 case 0x2:
197 lasat_board_info.li_cpu_hz =
198 lasat_board_info.li_bus_hz +
199 lasat_board_info.li_bus_hz;
200 break;
201 case 0x3:
202 lasat_board_info.li_cpu_hz =
203 lasat_board_info.li_bus_hz +
204 lasat_board_info.li_bus_hz +
205 (lasat_board_info.li_bus_hz >> 1);
206 break;
207 case 0x4:
208 lasat_board_info.li_cpu_hz =
209 lasat_board_info.li_bus_hz +
210 lasat_board_info.li_bus_hz +
211 lasat_board_info.li_bus_hz;
212 break;
213 }
214
215 /* Flash size */
216 switch (LASAT_W1_FLASHSIZE(cfg1)) {
217 case 0:
218 lasat_board_info.li_flash_size = 0x200000;
219 break;
220 case 1:
221 lasat_board_info.li_flash_size = 0x400000;
222 break;
223 case 2:
224 lasat_board_info.li_flash_size = 0x800000;
225 break;
226 case 3:
227 lasat_board_info.li_flash_size = 0x1000000;
228 break;
229 case 4:
230 lasat_board_info.li_flash_size = 0x2000000;
231 break;
232 }
233
234 init_flash_sizes();
235
236 lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0);
237 lasat_board_info.li_prid = lasat_board_info.li_eeprom_info.prid;
238 if (lasat_board_info.li_prid == 0xffff || lasat_board_info.li_prid == 0)
239 lasat_board_info.li_prid = lasat_board_info.li_bmid;
240
241 /* Base model stuff */
242 if (lasat_board_info.li_bmid > i_n_base_models)
243 lasat_board_info.li_bmid = i_n_base_models;
244 strcpy(lasat_board_info.li_bmstr,
245 i_txt_base_models[lasat_board_info.li_bmid]);
246
247 /* Product ID dependent values */
248 c = lasat_board_info.li_prid;
249 if (c >= i_n_prids) {
250 strcpy(lasat_board_info.li_namestr, "Unknown Model");
251 strcpy(lasat_board_info.li_typestr, "Unknown Type");
252 } else {
253 ppi = &vendor_info_table[0].vi_product_info[c];
254 strcpy(lasat_board_info.li_namestr, ppi->pi_name);
255 if (ppi->pi_type)
256 strcpy(lasat_board_info.li_typestr, ppi->pi_type);
257 else
258 sprintf(lasat_board_info.li_typestr, "%d", 10 * c);
259 }
260
261#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL)
262 update_bcastaddr();
263#endif
264
265 return 0;
266}
267
268void lasat_write_eeprom_info(void)
269{
270 unsigned long crc;
271
272 /* Generate the CRC */
273 crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
274 sizeof(struct lasat_eeprom_struct) - 4);
275 lasat_board_info.li_eeprom_info.crc32 = crc;
276
277 /* Write the EEPROM info */
278 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
279 sizeof(struct lasat_eeprom_struct));
280}
diff --git a/arch/mips/lasat/lasat_models.h b/arch/mips/lasat/lasat_models.h
new file mode 100644
index 000000000000..e1cbd26ae1b3
--- /dev/null
+++ b/arch/mips/lasat/lasat_models.h
@@ -0,0 +1,67 @@
1/*
2 * Model description tables
3 */
4#include <linux/kernel.h>
5
6struct product_info {
7 const char *pi_name;
8 const char *pi_type;
9};
10
11struct vendor_info {
12 const char *vi_name;
13 const struct product_info *vi_product_info;
14};
15
16/*
17 * Base models
18 */
19static const char * const txt_base_models[] = {
20 "MQ 2", "MQ Pro", "SP 25", "SP 50", "SP 100", "SP 5000", "SP 7000",
21 "SP 1000", "Unknown"
22};
23#define N_BASE_MODELS (ARRAY_SIZE(txt_base_models) - 1)
24
25/*
26 * Eicon Networks
27 */
28static const char txt_en_mq[] = "Masquerade";
29static const char txt_en_sp[] = "Safepipe";
30
31static const struct product_info product_info_eicon[] = {
32 { txt_en_mq, "II" }, /* 0 */
33 { txt_en_mq, "Pro" }, /* 1 */
34 { txt_en_sp, "25" }, /* 2 */
35 { txt_en_sp, "50" }, /* 3 */
36 { txt_en_sp, "100" }, /* 4 */
37 { txt_en_sp, "5000" }, /* 5 */
38 { txt_en_sp, "7000" }, /* 6 */
39 { txt_en_sp, "30" }, /* 7 */
40 { txt_en_sp, "5100" }, /* 8 */
41 { txt_en_sp, "7100" }, /* 9 */
42 { txt_en_sp, "1110" }, /* 10 */
43 { txt_en_sp, "3020" }, /* 11 */
44 { txt_en_sp, "3030" }, /* 12 */
45 { txt_en_sp, "5020" }, /* 13 */
46 { txt_en_sp, "5030" }, /* 14 */
47 { txt_en_sp, "1120" }, /* 15 */
48 { txt_en_sp, "1130" }, /* 16 */
49 { txt_en_sp, "6010" }, /* 17 */
50 { txt_en_sp, "6110" }, /* 18 */
51 { txt_en_sp, "6210" }, /* 19 */
52 { txt_en_sp, "1020" }, /* 20 */
53 { txt_en_sp, "1040" }, /* 21 */
54 { txt_en_sp, "1050" }, /* 22 */
55 { txt_en_sp, "1060" }, /* 23 */
56};
57
58#define N_PRIDS ARRAY_SIZE(product_info_eicon)
59
60/*
61 * The vendor table
62 */
63static struct vendor_info const vendor_info_table[] = {
64 { "Eicon Networks", product_info_eicon },
65};
66
67#define N_VENDORS ARRAY_SIZE(vendor_info_table)
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
new file mode 100644
index 000000000000..6471d0663fd8
--- /dev/null
+++ b/arch/mips/lasat/picvue.c
@@ -0,0 +1,244 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <asm/bootinfo.h>
10#include <asm/lasat/lasat.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15
16#include "picvue.h"
17
18#define PVC_BUSY 0x80
19#define PVC_NLINES 2
20#define PVC_DISPMEM 80
21#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES
22
23struct pvc_defs *picvue;
24
25DECLARE_MUTEX(pvc_sem);
26
27static void pvc_reg_write(u32 val)
28{
29 *picvue->reg = val;
30}
31
32static u32 pvc_reg_read(void)
33{
34 u32 tmp = *picvue->reg;
35 return tmp;
36}
37
38static void pvc_write_byte(u32 data, u8 byte)
39{
40 data |= picvue->e;
41 pvc_reg_write(data);
42 data &= ~picvue->data_mask;
43 data |= byte << picvue->data_shift;
44 pvc_reg_write(data);
45 ndelay(220);
46 pvc_reg_write(data & ~picvue->e);
47 ndelay(220);
48}
49
50static u8 pvc_read_byte(u32 data)
51{
52 u8 byte;
53
54 data |= picvue->e;
55 pvc_reg_write(data);
56 ndelay(220);
57 byte = (pvc_reg_read() & picvue->data_mask) >> picvue->data_shift;
58 data &= ~picvue->e;
59 pvc_reg_write(data);
60 ndelay(220);
61 return byte;
62}
63
64static u8 pvc_read_data(void)
65{
66 u32 data = pvc_reg_read();
67 u8 byte;
68 data |= picvue->rw;
69 data &= ~picvue->rs;
70 pvc_reg_write(data);
71 ndelay(40);
72 byte = pvc_read_byte(data);
73 data |= picvue->rs;
74 pvc_reg_write(data);
75 return byte;
76}
77
78#define TIMEOUT 1000
79static int pvc_wait(void)
80{
81 int i = TIMEOUT;
82 int err = 0;
83
84 while ((pvc_read_data() & PVC_BUSY) && i)
85 i--;
86 if (i == 0)
87 err = -ETIME;
88
89 return err;
90}
91
92#define MODE_INST 0
93#define MODE_DATA 1
94static void pvc_write(u8 byte, int mode)
95{
96 u32 data = pvc_reg_read();
97 data &= ~picvue->rw;
98 if (mode == MODE_DATA)
99 data |= picvue->rs;
100 else
101 data &= ~picvue->rs;
102 pvc_reg_write(data);
103 ndelay(40);
104 pvc_write_byte(data, byte);
105 if (mode == MODE_DATA)
106 data &= ~picvue->rs;
107 else
108 data |= picvue->rs;
109 pvc_reg_write(data);
110 pvc_wait();
111}
112
113void pvc_write_string(const unsigned char *str, u8 addr, int line)
114{
115 int i = 0;
116
117 if (line > 0 && (PVC_NLINES > 1))
118 addr += 0x40 * line;
119 pvc_write(0x80 | addr, MODE_INST);
120
121 while (*str != 0 && i < PVC_LINELEN) {
122 pvc_write(*str++, MODE_DATA);
123 i++;
124 }
125}
126
127void pvc_write_string_centered(const unsigned char *str, int line)
128{
129 int len = strlen(str);
130 u8 addr;
131
132 if (len > PVC_VISIBLE_CHARS)
133 addr = 0;
134 else
135 addr = (PVC_VISIBLE_CHARS - strlen(str))/2;
136
137 pvc_write_string(str, addr, line);
138}
139
140void pvc_dump_string(const unsigned char *str)
141{
142 int len = strlen(str);
143
144 pvc_write_string(str, 0, 0);
145 if (len > PVC_VISIBLE_CHARS)
146 pvc_write_string(&str[PVC_VISIBLE_CHARS], 0, 1);
147}
148
149#define BM_SIZE 8
150#define MAX_PROGRAMMABLE_CHARS 8
151int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE])
152{
153 int i;
154 int addr;
155
156 if (charnum > MAX_PROGRAMMABLE_CHARS)
157 return -ENOENT;
158
159 addr = charnum * 8;
160 pvc_write(0x40 | addr, MODE_INST);
161
162 for (i = 0; i < BM_SIZE; i++)
163 pvc_write(bitmap[i], MODE_DATA);
164 return 0;
165}
166
167#define FUNC_SET_CMD 0x20
168#define EIGHT_BYTE (1 << 4)
169#define FOUR_BYTE 0
170#define TWO_LINES (1 << 3)
171#define ONE_LINE 0
172#define LARGE_FONT (1 << 2)
173#define SMALL_FONT 0
174
175static void pvc_funcset(u8 cmd)
176{
177 pvc_write(FUNC_SET_CMD | (cmd & (EIGHT_BYTE|TWO_LINES|LARGE_FONT)),
178 MODE_INST);
179}
180
181#define ENTRYMODE_CMD 0x4
182#define AUTO_INC (1 << 1)
183#define AUTO_DEC 0
184#define CURSOR_FOLLOWS_DISP (1 << 0)
185
186static void pvc_entrymode(u8 cmd)
187{
188 pvc_write(ENTRYMODE_CMD | (cmd & (AUTO_INC|CURSOR_FOLLOWS_DISP)),
189 MODE_INST);
190}
191
192#define DISP_CNT_CMD 0x08
193#define DISP_OFF 0
194#define DISP_ON (1 << 2)
195#define CUR_ON (1 << 1)
196#define CUR_BLINK (1 << 0)
197void pvc_dispcnt(u8 cmd)
198{
199 pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST);
200}
201
202#define MOVE_CMD 0x10
203#define DISPLAY (1 << 3)
204#define CURSOR 0
205#define RIGHT (1 << 2)
206#define LEFT 0
207void pvc_move(u8 cmd)
208{
209 pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST);
210}
211
212#define CLEAR_CMD 0x1
213void pvc_clear(void)
214{
215 pvc_write(CLEAR_CMD, MODE_INST);
216}
217
218#define HOME_CMD 0x2
219void pvc_home(void)
220{
221 pvc_write(HOME_CMD, MODE_INST);
222}
223
224int pvc_init(void)
225{
226 u8 cmd = EIGHT_BYTE;
227
228 if (PVC_NLINES == 2)
229 cmd |= (SMALL_FONT|TWO_LINES);
230 else
231 cmd |= (LARGE_FONT|ONE_LINE);
232 pvc_funcset(cmd);
233 pvc_dispcnt(DISP_ON);
234 pvc_entrymode(AUTO_INC);
235
236 pvc_clear();
237 pvc_write_string_centered("Display", 0);
238 pvc_write_string_centered("Initialized", 1);
239
240 return 0;
241}
242
243module_init(pvc_init);
244MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
new file mode 100644
index 000000000000..2a96bf971897
--- /dev/null
+++ b/arch/mips/lasat/picvue.h
@@ -0,0 +1,48 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <asm/semaphore.h>
8
9struct pvc_defs {
10 volatile u32 *reg;
11 u32 data_shift;
12 u32 data_mask;
13 u32 e;
14 u32 rw;
15 u32 rs;
16};
17
18extern struct pvc_defs *picvue;
19
20#define PVC_NLINES 2
21#define PVC_DISPMEM 80
22#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES
23#define PVC_VISIBLE_CHARS 16
24
25void pvc_write_string(const unsigned char *str, u8 addr, int line);
26void pvc_write_string_centered(const unsigned char *str, int line);
27void pvc_dump_string(const unsigned char *str);
28
29#define BM_SIZE 8
30#define MAX_PROGRAMMABLE_CHARS 8
31int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]);
32
33void pvc_dispcnt(u8 cmd);
34#define DISP_OFF 0
35#define DISP_ON (1 << 2)
36#define CUR_ON (1 << 1)
37#define CUR_BLINK (1 << 0)
38
39void pvc_move(u8 cmd);
40#define DISPLAY (1 << 3)
41#define CURSOR 0
42#define RIGHT (1 << 2)
43#define LEFT 0
44
45void pvc_clear(void);
46void pvc_home(void);
47
48extern struct semaphore pvc_sem;
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
new file mode 100644
index 000000000000..9947c1525822
--- /dev/null
+++ b/arch/mips/lasat/picvue_proc.c
@@ -0,0 +1,191 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/errno.h>
11
12#include <linux/proc_fs.h>
13#include <linux/interrupt.h>
14
15#include <linux/timer.h>
16
17#include "picvue.h"
18
19static char pvc_lines[PVC_NLINES][PVC_LINELEN+1];
20static int pvc_linedata[PVC_NLINES];
21static struct proc_dir_entry *pvc_display_dir;
22static char *pvc_linename[PVC_NLINES] = {"line1", "line2"};
23#define DISPLAY_DIR_NAME "display"
24static int scroll_dir, scroll_interval;
25
26static struct timer_list timer;
27
28static void pvc_display(unsigned long data)
29{
30 int i;
31
32 pvc_clear();
33 for (i = 0; i < PVC_NLINES; i++)
34 pvc_write_string(pvc_lines[i], 0, i);
35}
36
37static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
38
39static int pvc_proc_read_line(char *page, char **start,
40 off_t off, int count,
41 int *eof, void *data)
42{
43 char *origpage = page;
44 int lineno = *(int *)data;
45
46 if (lineno < 0 || lineno > PVC_NLINES) {
47 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
48 return 0;
49 }
50
51 down(&pvc_sem);
52 page += sprintf(page, "%s\n", pvc_lines[lineno]);
53 up(&pvc_sem);
54
55 return page - origpage;
56}
57
58static int pvc_proc_write_line(struct file *file, const char *buffer,
59 unsigned long count, void *data)
60{
61 int origcount = count;
62 int lineno = *(int *)data;
63
64 if (lineno < 0 || lineno > PVC_NLINES) {
65 printk(KERN_WARNING "proc_write_line: invalid lineno %d\n",
66 lineno);
67 return origcount;
68 }
69
70 if (count > PVC_LINELEN)
71 count = PVC_LINELEN;
72
73 if (buffer[count-1] == '\n')
74 count--;
75
76 down(&pvc_sem);
77 strncpy(pvc_lines[lineno], buffer, count);
78 pvc_lines[lineno][count] = '\0';
79 up(&pvc_sem);
80
81 tasklet_schedule(&pvc_display_tasklet);
82
83 return origcount;
84}
85
86static int pvc_proc_write_scroll(struct file *file, const char *buffer,
87 unsigned long count, void *data)
88{
89 int origcount = count;
90 int cmd = simple_strtol(buffer, NULL, 10);
91
92 down(&pvc_sem);
93 if (scroll_interval != 0)
94 del_timer(&timer);
95
96 if (cmd == 0) {
97 scroll_dir = 0;
98 scroll_interval = 0;
99 } else {
100 if (cmd < 0) {
101 scroll_dir = -1;
102 scroll_interval = -cmd;
103 } else {
104 scroll_dir = 1;
105 scroll_interval = cmd;
106 }
107 add_timer(&timer);
108 }
109 up(&pvc_sem);
110
111 return origcount;
112}
113
114static int pvc_proc_read_scroll(char *page, char **start,
115 off_t off, int count,
116 int *eof, void *data)
117{
118 char *origpage = page;
119
120 down(&pvc_sem);
121 page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
122 up(&pvc_sem);
123
124 return page - origpage;
125}
126
127
128void pvc_proc_timerfunc(unsigned long data)
129{
130 if (scroll_dir < 0)
131 pvc_move(DISPLAY|RIGHT);
132 else if (scroll_dir > 0)
133 pvc_move(DISPLAY|LEFT);
134
135 timer.expires = jiffies + scroll_interval;
136 add_timer(&timer);
137}
138
139static void pvc_proc_cleanup(void)
140{
141 int i;
142 for (i = 0; i < PVC_NLINES; i++)
143 remove_proc_entry(pvc_linename[i], pvc_display_dir);
144 remove_proc_entry("scroll", pvc_display_dir);
145 remove_proc_entry(DISPLAY_DIR_NAME, NULL);
146
147 del_timer(&timer);
148}
149
150static int __init pvc_proc_init(void)
151{
152 struct proc_dir_entry *proc_entry;
153 int i;
154
155 pvc_display_dir = proc_mkdir(DISPLAY_DIR_NAME, NULL);
156 if (pvc_display_dir == NULL)
157 goto error;
158
159 for (i = 0; i < PVC_NLINES; i++) {
160 strcpy(pvc_lines[i], "");
161 pvc_linedata[i] = i;
162 }
163 for (i = 0; i < PVC_NLINES; i++) {
164 proc_entry = create_proc_entry(pvc_linename[i], 0644,
165 pvc_display_dir);
166 if (proc_entry == NULL)
167 goto error;
168
169 proc_entry->read_proc = pvc_proc_read_line;
170 proc_entry->write_proc = pvc_proc_write_line;
171 proc_entry->data = &pvc_linedata[i];
172 }
173 proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir);
174 if (proc_entry == NULL)
175 goto error;
176
177 proc_entry->write_proc = pvc_proc_write_scroll;
178 proc_entry->read_proc = pvc_proc_read_scroll;
179
180 init_timer(&timer);
181 timer.function = pvc_proc_timerfunc;
182
183 return 0;
184error:
185 pvc_proc_cleanup();
186 return -ENOMEM;
187}
188
189module_init(pvc_proc_init);
190module_exit(pvc_proc_cleanup);
191MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
new file mode 100644
index 000000000000..209edcc26f07
--- /dev/null
+++ b/arch/mips/lasat/prom.c
@@ -0,0 +1,126 @@
1/*
2 * PROM interface routines.
3 */
4#include <linux/types.h>
5#include <linux/init.h>
6#include <linux/string.h>
7#include <linux/ctype.h>
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/bootmem.h>
11#include <linux/ioport.h>
12#include <asm/bootinfo.h>
13#include <asm/lasat/lasat.h>
14#include <asm/cpu.h>
15
16#include "at93c.h"
17#include <asm/lasat/eeprom.h>
18#include "prom.h"
19
20#define RESET_VECTOR 0xbfc00000
21#define PROM_JUMP_TABLE_ENTRY(n) (*((u32 *)(RESET_VECTOR + 0x20) + n))
22#define PROM_DISPLAY_ADDR PROM_JUMP_TABLE_ENTRY(0)
23#define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1)
24#define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2)
25
26static void null_prom_display(const char *string, int pos, int clear)
27{
28}
29
30static void null_prom_monitor(void)
31{
32}
33
34static void null_prom_putc(char c)
35{
36}
37
38/* these are functions provided by the bootloader */
39static void (*__prom_putc)(char c) = null_prom_putc;
40
41void prom_putchar(char c)
42{
43 __prom_putc(c);
44}
45
46void (*prom_display)(const char *string, int pos, int clear) =
47 null_prom_display;
48void (*prom_monitor)(void) = null_prom_monitor;
49
50unsigned int lasat_ndelay_divider;
51
52static void setup_prom_vectors(void)
53{
54 u32 version = *(u32 *)(RESET_VECTOR + 0x90);
55
56 if (version >= 307) {
57 prom_display = (void *)PROM_DISPLAY_ADDR;
58 __prom_putc = (void *)PROM_PUTC_ADDR;
59 prom_monitor = (void *)PROM_MONITOR_ADDR;
60 }
61 printk(KERN_DEBUG "prom vectors set up\n");
62}
63
64static struct at93c_defs at93c_defs[N_MACHTYPES] = {
65 {
66 .reg = (void *)AT93C_REG_100,
67 .rdata_reg = (void *)AT93C_RDATA_REG_100,
68 .rdata_shift = AT93C_RDATA_SHIFT_100,
69 .wdata_shift = AT93C_WDATA_SHIFT_100,
70 .cs = AT93C_CS_M_100,
71 .clk = AT93C_CLK_M_100
72 }, {
73 .reg = (void *)AT93C_REG_200,
74 .rdata_reg = (void *)AT93C_RDATA_REG_200,
75 .rdata_shift = AT93C_RDATA_SHIFT_200,
76 .wdata_shift = AT93C_WDATA_SHIFT_200,
77 .cs = AT93C_CS_M_200,
78 .clk = AT93C_CLK_M_200
79 },
80};
81
82void __init prom_init(void)
83{
84 int argc = fw_arg0;
85 char **argv = (char **) fw_arg1;
86
87 setup_prom_vectors();
88
89 if (current_cpu_data.cputype == CPU_R5000) {
90 printk(KERN_INFO "LASAT 200 board\n");
91 mips_machtype = MACH_LASAT_200;
92 lasat_ndelay_divider = LASAT_200_DIVIDER;
93 } else {
94 printk(KERN_INFO "LASAT 100 board\n");
95 mips_machtype = MACH_LASAT_100;
96 lasat_ndelay_divider = LASAT_100_DIVIDER;
97 }
98
99 at93c = &at93c_defs[mips_machtype];
100
101 lasat_init_board_info(); /* Read info from EEPROM */
102
103 /* Get the command line */
104 if (argc > 0) {
105 strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
106 arcs_cmdline[CL_SIZE-1] = '\0';
107 }
108
109 /* Set the I/O base address */
110 set_io_port_base(KSEG1);
111
112 /* Set memory regions */
113 ioport_resource.start = 0;
114 ioport_resource.end = 0xffffffff; /* Wrong, fixme. */
115
116 add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM);
117}
118
119void __init prom_free_prom_memory(void)
120{
121}
122
123const char *get_system_type(void)
124{
125 return lasat_board_info.li_bmstr;
126}
diff --git a/arch/mips/lasat/prom.h b/arch/mips/lasat/prom.h
new file mode 100644
index 000000000000..337acbc27442
--- /dev/null
+++ b/arch/mips/lasat/prom.h
@@ -0,0 +1,7 @@
1#ifndef __PROM_H
2#define __PROM_H
3
4extern void (*prom_display)(const char *string, int pos, int clear);
5extern void (*prom_monitor)(void);
6
7#endif /* __PROM_H */
diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c
new file mode 100644
index 000000000000..b1e7a89fb730
--- /dev/null
+++ b/arch/mips/lasat/reset.c
@@ -0,0 +1,61 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Reset the LASAT board.
19 */
20#include <linux/kernel.h>
21#include <linux/pm.h>
22
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <asm/lasat/lasat.h>
26
27#include "picvue.h"
28#include "prom.h"
29
30static void lasat_machine_restart(char *command);
31static void lasat_machine_halt(void);
32
33/* Used to set machine to boot in service mode via /proc interface */
34int lasat_boot_to_service;
35
36static void lasat_machine_restart(char *command)
37{
38 local_irq_disable();
39
40 if (lasat_boot_to_service) {
41 *(volatile unsigned int *)0xa0000024 = 0xdeadbeef;
42 *(volatile unsigned int *)0xa00000fc = 0xfedeabba;
43 }
44 *lasat_misc->reset_reg = 0xbedead;
45 for (;;) ;
46}
47
48static void lasat_machine_halt(void)
49{
50 local_irq_disable();
51
52 prom_monitor();
53 for (;;) ;
54}
55
56void lasat_reboot_setup(void)
57{
58 _machine_restart = lasat_machine_restart;
59 _machine_halt = lasat_machine_halt;
60 pm_power_off = lasat_machine_halt;
61}
diff --git a/arch/mips/lasat/serial.c b/arch/mips/lasat/serial.c
new file mode 100644
index 000000000000..205bd397d75b
--- /dev/null
+++ b/arch/mips/lasat/serial.c
@@ -0,0 +1,94 @@
1/*
2 * Registration of Lasat UART platform device.
3 *
4 * Copyright (C) 2007 Brian Murphy <brian@murphy.dk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <asm/bootinfo.h>
27#include <asm/lasat/lasat.h>
28#include <asm/lasat/serial.h>
29
30static struct resource lasat_serial_res[2] __initdata;
31
32static struct plat_serial8250_port lasat_serial8250_port[] = {
33 {
34 .iotype = UPIO_MEM,
35 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
36 UPF_SKIP_TEST,
37 },
38 {},
39};
40
41static __init int lasat_uart_add(void)
42{
43 struct platform_device *pdev;
44 int retval;
45
46 pdev = platform_device_alloc("serial8250", -1);
47 if (!pdev)
48 return -ENOMEM;
49
50 if (mips_machtype == MACH_LASAT_100) {
51 lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100);
52 lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_100 * 8 - 1;
53 lasat_serial_res[0].flags = IORESOURCE_MEM;
54 lasat_serial_res[1].start = LASATINT_UART_100;
55 lasat_serial_res[1].end = LASATINT_UART_100;
56 lasat_serial_res[1].flags = IORESOURCE_IRQ;
57
58 lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_100;
59 lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_100 * 16;
60 lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_100;
61 lasat_serial8250_port[0].irq = LASATINT_UART_100;
62 } else {
63 lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_200);
64 lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_200 * 8 - 1;
65 lasat_serial_res[0].flags = IORESOURCE_MEM;
66 lasat_serial_res[1].start = LASATINT_UART_200;
67 lasat_serial_res[1].end = LASATINT_UART_200;
68 lasat_serial_res[1].flags = IORESOURCE_IRQ;
69
70 lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_200;
71 lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_200 * 16;
72 lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_200;
73 lasat_serial8250_port[0].irq = LASATINT_UART_200;
74 }
75
76 pdev->id = PLAT8250_DEV_PLATFORM;
77 pdev->dev.platform_data = lasat_serial8250_port;
78
79 retval = platform_device_add_resources(pdev, lasat_serial_res, ARRAY_SIZE(lasat_serial_res));
80 if (retval)
81 goto err_free_device;
82
83 retval = platform_device_add(pdev);
84 if (retval)
85 goto err_free_device;
86
87 return 0;
88
89err_free_device:
90 platform_device_put(pdev);
91
92 return retval;
93}
94device_initcall(lasat_uart_add);
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
new file mode 100644
index 000000000000..54827d0174bf
--- /dev/null
+++ b/arch/mips/lasat/setup.c
@@ -0,0 +1,154 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
4 *
5 * Thomas Horsten <thh@lasat.com>
6 * Copyright (C) 2000 LASAT Networks A/S.
7 *
8 * Brian Murphy <brian@murphy.dk>
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * Lasat specific setup.
24 */
25#include <linux/init.h>
26#include <linux/sched.h>
27#include <linux/pci.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30
31#include <asm/time.h>
32#include <asm/cpu.h>
33#include <asm/bootinfo.h>
34#include <asm/irq.h>
35#include <asm/lasat/lasat.h>
36#include <asm/lasat/serial.h>
37
38#ifdef CONFIG_PICVUE
39#include <linux/notifier.h>
40#endif
41
42#include "ds1603.h"
43#include <asm/lasat/ds1603.h>
44#include <asm/lasat/picvue.h>
45#include <asm/lasat/eeprom.h>
46
47#include "prom.h"
48
49int lasat_command_line;
50void lasatint_init(void);
51
52extern void lasat_reboot_setup(void);
53extern void pcisetup(void);
54extern void edhac_init(void *, void *, void *);
55extern void addrflt_init(void);
56
57struct lasat_misc lasat_misc_info[N_MACHTYPES] = {
58 {
59 .reset_reg = (void *)KSEG1ADDR(0x1c840000),
60 .flash_wp_reg = (void *)KSEG1ADDR(0x1c800000), 2
61 }, {
62 .reset_reg = (void *)KSEG1ADDR(0x11080000),
63 .flash_wp_reg = (void *)KSEG1ADDR(0x11000000), 6
64 }
65};
66
67struct lasat_misc *lasat_misc;
68
69#ifdef CONFIG_DS1603
70static struct ds_defs ds_defs[N_MACHTYPES] = {
71 { (void *)DS1603_REG_100, (void *)DS1603_REG_100,
72 DS1603_RST_100, DS1603_CLK_100, DS1603_DATA_100,
73 DS1603_DATA_SHIFT_100, 0, 0 },
74 { (void *)DS1603_REG_200, (void *)DS1603_DATA_REG_200,
75 DS1603_RST_200, DS1603_CLK_200, DS1603_DATA_200,
76 DS1603_DATA_READ_SHIFT_200, 1, 2000 }
77};
78#endif
79
80#ifdef CONFIG_PICVUE
81#include "picvue.h"
82static struct pvc_defs pvc_defs[N_MACHTYPES] = {
83 { (void *)PVC_REG_100, PVC_DATA_SHIFT_100, PVC_DATA_M_100,
84 PVC_E_100, PVC_RW_100, PVC_RS_100 },
85 { (void *)PVC_REG_200, PVC_DATA_SHIFT_200, PVC_DATA_M_200,
86 PVC_E_200, PVC_RW_200, PVC_RS_200 }
87};
88#endif
89
90static int lasat_panic_display(struct notifier_block *this,
91 unsigned long event, void *ptr)
92{
93#ifdef CONFIG_PICVUE
94 unsigned char *string = ptr;
95 if (string == NULL)
96 string = "Kernel Panic";
97 pvc_dump_string(string);
98#endif
99 return NOTIFY_DONE;
100}
101
102static int lasat_panic_prom_monitor(struct notifier_block *this,
103 unsigned long event, void *ptr)
104{
105 prom_monitor();
106 return NOTIFY_DONE;
107}
108
109static struct notifier_block lasat_panic_block[] =
110{
111 {
112 .notifier_call = lasat_panic_display,
113 .priority = INT_MAX
114 }, {
115 .notifier_call = lasat_panic_prom_monitor,
116 .priority = INT_MIN
117 }
118};
119
120void plat_time_init(void)
121{
122 mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2;
123}
124
125void __init plat_timer_setup(struct irqaction *irq)
126{
127 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
128}
129
130void __init plat_mem_setup(void)
131{
132 int i;
133 lasat_misc = &lasat_misc_info[mips_machtype];
134#ifdef CONFIG_PICVUE
135 picvue = &pvc_defs[mips_machtype];
136#endif
137
138 /* Set up panic notifier */
139 for (i = 0; i < ARRAY_SIZE(lasat_panic_block); i++)
140 atomic_notifier_chain_register(&panic_notifier_list,
141 &lasat_panic_block[i]);
142
143 lasat_reboot_setup();
144
145#ifdef CONFIG_DS1603
146 ds1603 = &ds_defs[mips_machtype];
147#endif
148
149#ifdef DYNAMIC_SERIAL_INIT
150 serial_init();
151#endif
152
153 pr_info("Lasat specific initialization complete\n");
154}
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
new file mode 100644
index 000000000000..389336c4ecc5
--- /dev/null
+++ b/arch/mips/lasat/sysctl.c
@@ -0,0 +1,456 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines specific to the LASAT boards
19 */
20#include <linux/types.h>
21#include <asm/lasat/lasat.h>
22
23#include <linux/module.h>
24#include <linux/sysctl.h>
25#include <linux/stddef.h>
26#include <linux/init.h>
27#include <linux/fs.h>
28#include <linux/ctype.h>
29#include <linux/string.h>
30#include <linux/net.h>
31#include <linux/inet.h>
32#include <linux/mutex.h>
33#include <linux/uaccess.h>
34
35#include <asm/time.h>
36
37#include "sysctl.h"
38#include "ds1603.h"
39
40static DEFINE_MUTEX(lasat_info_mutex);
41
42/* Strategy function to write EEPROM after changing string entry */
43int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
44 void *oldval, size_t *oldlenp,
45 void *newval, size_t newlen)
46{
47 int r;
48
49 mutex_lock(&lasat_info_mutex);
50 r = sysctl_string(table, name,
51 nlen, oldval, oldlenp, newval, newlen);
52 if (r < 0) {
53 mutex_unlock(&lasat_info_mutex);
54 return r;
55 }
56 if (newval && newlen)
57 lasat_write_eeprom_info();
58 mutex_unlock(&lasat_info_mutex);
59
60 return 1;
61}
62
63
64/* And the same for proc */
65int proc_dolasatstring(ctl_table *table, int write, struct file *filp,
66 void *buffer, size_t *lenp, loff_t *ppos)
67{
68 int r;
69
70 mutex_lock(&lasat_info_mutex);
71 r = proc_dostring(table, write, filp, buffer, lenp, ppos);
72 if ((!write) || r) {
73 mutex_unlock(&lasat_info_mutex);
74 return r;
75 }
76 lasat_write_eeprom_info();
77 mutex_unlock(&lasat_info_mutex);
78
79 return 0;
80}
81
82/* proc function to write EEPROM after changing int entry */
83int proc_dolasatint(ctl_table *table, int write, struct file *filp,
84 void *buffer, size_t *lenp, loff_t *ppos)
85{
86 int r;
87
88 mutex_lock(&lasat_info_mutex);
89 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
90 if ((!write) || r) {
91 mutex_unlock(&lasat_info_mutex);
92 return r;
93 }
94 lasat_write_eeprom_info();
95 mutex_unlock(&lasat_info_mutex);
96
97 return 0;
98}
99
100static int rtctmp;
101
102#ifdef CONFIG_DS1603
103/* proc function to read/write RealTime Clock */
104int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
105 void *buffer, size_t *lenp, loff_t *ppos)
106{
107 int r;
108
109 mutex_lock(&lasat_info_mutex);
110 if (!write) {
111 rtctmp = read_persistent_clock();
112 /* check for time < 0 and set to 0 */
113 if (rtctmp < 0)
114 rtctmp = 0;
115 }
116 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
117 if ((!write) || r) {
118 mutex_unlock(&lasat_info_mutex);
119 return r;
120 }
121 rtc_mips_set_mmss(rtctmp);
122 mutex_unlock(&lasat_info_mutex);
123
124 return 0;
125}
126#endif
127
128/* Sysctl for setting the IP addresses */
129int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen,
130 void *oldval, size_t *oldlenp,
131 void *newval, size_t newlen)
132{
133 int r;
134
135 mutex_lock(&lasat_info_mutex);
136 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
137 if (r < 0) {
138 mutex_unlock(&lasat_info_mutex);
139 return r;
140 }
141 if (newval && newlen)
142 lasat_write_eeprom_info();
143 mutex_unlock(&lasat_info_mutex);
144
145 return 1;
146}
147
148#ifdef CONFIG_DS1603
149/* Same for RTC */
150int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen,
151 void *oldval, size_t *oldlenp,
152 void *newval, size_t newlen)
153{
154 int r;
155
156 mutex_lock(&lasat_info_mutex);
157 rtctmp = read_persistent_clock();
158 if (rtctmp < 0)
159 rtctmp = 0;
160 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
161 if (r < 0) {
162 mutex_unlock(&lasat_info_mutex);
163 return r;
164 }
165 if (newval && newlen)
166 rtc_mips_set_mmss(rtctmp);
167 mutex_unlock(&lasat_info_mutex);
168
169 return 1;
170}
171#endif
172
173#ifdef CONFIG_INET
174static char lasat_bcastaddr[16];
175
176void update_bcastaddr(void)
177{
178 unsigned int ip;
179
180 ip = (lasat_board_info.li_eeprom_info.ipaddr &
181 lasat_board_info.li_eeprom_info.netmask) |
182 ~lasat_board_info.li_eeprom_info.netmask;
183
184 sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
185 (ip) & 0xff,
186 (ip >> 8) & 0xff,
187 (ip >> 16) & 0xff,
188 (ip >> 24) & 0xff);
189}
190
191static char proc_lasat_ipbuf[32];
192
193/* Parsing of IP address */
194int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
195 void *buffer, size_t *lenp, loff_t *ppos)
196{
197 unsigned int ip;
198 char *p, c;
199 int len;
200
201 if (!table->data || !table->maxlen || !*lenp ||
202 (*ppos && !write)) {
203 *lenp = 0;
204 return 0;
205 }
206
207 mutex_lock(&lasat_info_mutex);
208 if (write) {
209 len = 0;
210 p = buffer;
211 while (len < *lenp) {
212 if (get_user(c, p++)) {
213 mutex_unlock(&lasat_info_mutex);
214 return -EFAULT;
215 }
216 if (c == 0 || c == '\n')
217 break;
218 len++;
219 }
220 if (len >= sizeof(proc_lasat_ipbuf)-1)
221 len = sizeof(proc_lasat_ipbuf) - 1;
222 if (copy_from_user(proc_lasat_ipbuf, buffer, len)) {
223 mutex_unlock(&lasat_info_mutex);
224 return -EFAULT;
225 }
226 proc_lasat_ipbuf[len] = 0;
227 *ppos += *lenp;
228 /* Now see if we can convert it to a valid IP */
229 ip = in_aton(proc_lasat_ipbuf);
230 *(unsigned int *)(table->data) = ip;
231 lasat_write_eeprom_info();
232 } else {
233 ip = *(unsigned int *)(table->data);
234 sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d",
235 (ip) & 0xff,
236 (ip >> 8) & 0xff,
237 (ip >> 16) & 0xff,
238 (ip >> 24) & 0xff);
239 len = strlen(proc_lasat_ipbuf);
240 if (len > *lenp)
241 len = *lenp;
242 if (len)
243 if (copy_to_user(buffer, proc_lasat_ipbuf, len)) {
244 mutex_unlock(&lasat_info_mutex);
245 return -EFAULT;
246 }
247 if (len < *lenp) {
248 if (put_user('\n', ((char *) buffer) + len)) {
249 mutex_unlock(&lasat_info_mutex);
250 return -EFAULT;
251 }
252 len++;
253 }
254 *lenp = len;
255 *ppos += len;
256 }
257 update_bcastaddr();
258 mutex_unlock(&lasat_info_mutex);
259
260 return 0;
261}
262#endif /* defined(CONFIG_INET) */
263
264static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
265 void *oldval, size_t *oldlenp,
266 void *newval, size_t newlen)
267{
268 int r;
269
270 mutex_lock(&lasat_info_mutex);
271 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
272 if (r < 0) {
273 mutex_unlock(&lasat_info_mutex);
274 return r;
275 }
276
277 if (newval && newlen) {
278 if (name && *name == LASAT_PRID)
279 lasat_board_info.li_eeprom_info.prid = *(int *)newval;
280
281 lasat_write_eeprom_info();
282 lasat_init_board_info();
283 }
284 mutex_unlock(&lasat_info_mutex);
285
286 return 0;
287}
288
289int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
290 void *buffer, size_t *lenp, loff_t *ppos)
291{
292 int r;
293
294 mutex_lock(&lasat_info_mutex);
295 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
296 if ((!write) || r) {
297 mutex_unlock(&lasat_info_mutex);
298 return r;
299 }
300 if (filp && filp->f_path.dentry) {
301 if (!strcmp(filp->f_path.dentry->d_name.name, "prid"))
302 lasat_board_info.li_eeprom_info.prid =
303 lasat_board_info.li_prid;
304 if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess"))
305 lasat_board_info.li_eeprom_info.debugaccess =
306 lasat_board_info.li_debugaccess;
307 }
308 lasat_write_eeprom_info();
309 mutex_unlock(&lasat_info_mutex);
310
311 return 0;
312}
313
314extern int lasat_boot_to_service;
315
316#ifdef CONFIG_SYSCTL
317
318static ctl_table lasat_table[] = {
319 {
320 .ctl_name = CTL_UNNUMBERED,
321 .procname = "cpu-hz",
322 .data = &lasat_board_info.li_cpu_hz,
323 .maxlen = sizeof(int),
324 .mode = 0444,
325 .proc_handler = &proc_dointvec,
326 .strategy = &sysctl_intvec
327 },
328 {
329 .ctl_name = CTL_UNNUMBERED,
330 .procname = "bus-hz",
331 .data = &lasat_board_info.li_bus_hz,
332 .maxlen = sizeof(int),
333 .mode = 0444,
334 .proc_handler = &proc_dointvec,
335 .strategy = &sysctl_intvec
336 },
337 {
338 .ctl_name = CTL_UNNUMBERED,
339 .procname = "bmid",
340 .data = &lasat_board_info.li_bmid,
341 .maxlen = sizeof(int),
342 .mode = 0444,
343 .proc_handler = &proc_dointvec,
344 .strategy = &sysctl_intvec
345 },
346 {
347 .ctl_name = CTL_UNNUMBERED,
348 .procname = "prid",
349 .data = &lasat_board_info.li_prid,
350 .maxlen = sizeof(int),
351 .mode = 0644,
352 .proc_handler = &proc_lasat_eeprom_value,
353 .strategy = &sysctl_lasat_eeprom_value
354 },
355#ifdef CONFIG_INET
356 {
357 .ctl_name = CTL_UNNUMBERED,
358 .procname = "ipaddr",
359 .data = &lasat_board_info.li_eeprom_info.ipaddr,
360 .maxlen = sizeof(int),
361 .mode = 0644,
362 .proc_handler = &proc_lasat_ip,
363 .strategy = &sysctl_lasat_intvec
364 },
365 {
366 .ctl_name = LASAT_NETMASK,
367 .procname = "netmask",
368 .data = &lasat_board_info.li_eeprom_info.netmask,
369 .maxlen = sizeof(int),
370 .mode = 0644,
371 .proc_handler = &proc_lasat_ip,
372 .strategy = &sysctl_lasat_intvec
373 },
374 {
375 .ctl_name = CTL_UNNUMBERED,
376 .procname = "bcastaddr",
377 .data = &lasat_bcastaddr,
378 .maxlen = sizeof(lasat_bcastaddr),
379 .mode = 0600,
380 .proc_handler = &proc_dostring,
381 .strategy = &sysctl_string
382 },
383#endif
384 {
385 .ctl_name = CTL_UNNUMBERED,
386 .procname = "passwd_hash",
387 .data = &lasat_board_info.li_eeprom_info.passwd_hash,
388 .maxlen =
389 sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
390 .mode = 0600,
391 .proc_handler = &proc_dolasatstring,
392 .strategy = &sysctl_lasatstring
393 },
394 {
395 .ctl_name = CTL_UNNUMBERED,
396 .procname = "boot-service",
397 .data = &lasat_boot_to_service,
398 .maxlen = sizeof(int),
399 .mode = 0644,
400 .proc_handler = &proc_dointvec,
401 .strategy = &sysctl_intvec
402 },
403#ifdef CONFIG_DS1603
404 {
405 .ctl_name = CTL_UNNUMBERED,
406 .procname = "rtc",
407 .data = &rtctmp,
408 .maxlen = sizeof(int),
409 .mode = 0644,
410 .proc_handler = &proc_dolasatrtc,
411 .strategy = &sysctl_lasat_rtc
412 },
413#endif
414 {
415 .ctl_name = CTL_UNNUMBERED,
416 .procname = "namestr",
417 .data = &lasat_board_info.li_namestr,
418 .maxlen = sizeof(lasat_board_info.li_namestr),
419 .mode = 0444,
420 .proc_handler = &proc_dostring,
421 .strategy = &sysctl_string
422 },
423 {
424 .ctl_name = CTL_UNNUMBERED,
425 .procname = "typestr",
426 .data = &lasat_board_info.li_typestr,
427 .maxlen = sizeof(lasat_board_info.li_typestr),
428 .mode = 0444,
429 .proc_handler = &proc_dostring,
430 .strategy = &sysctl_string
431 },
432 {}
433};
434
435static ctl_table lasat_root_table[] = {
436 {
437 .ctl_name = CTL_UNNUMBERED,
438 .procname = "lasat",
439 .mode = 0555,
440 .child = lasat_table
441 },
442 {}
443};
444
445static int __init lasat_register_sysctl(void)
446{
447 struct ctl_table_header *lasat_table_header;
448
449 lasat_table_header =
450 register_sysctl_table(lasat_root_table);
451
452 return 0;
453}
454
455__initcall(lasat_register_sysctl);
456#endif /* CONFIG_SYSCTL */
diff --git a/arch/mips/lasat/sysctl.h b/arch/mips/lasat/sysctl.h
new file mode 100644
index 000000000000..341b97933423
--- /dev/null
+++ b/arch/mips/lasat/sysctl.h
@@ -0,0 +1,24 @@
1/*
2 * LASAT sysctl values
3 */
4
5#ifndef _LASAT_SYSCTL_H
6#define _LASAT_SYSCTL_H
7
8/* /proc/sys/lasat */
9enum {
10 LASAT_CPU_HZ = 1,
11 LASAT_BUS_HZ,
12 LASAT_MODEL,
13 LASAT_PRID,
14 LASAT_IPADDR,
15 LASAT_NETMASK,
16 LASAT_BCAST,
17 LASAT_PASSWORD,
18 LASAT_SBOOT,
19 LASAT_RTC,
20 LASAT_NAMESTR,
21 LASAT_TYPESTR,
22};
23
24#endif /* _LASAT_SYSCTL_H */
diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile
index dcaf6f4c3a37..d34671d1b899 100644
--- a/arch/mips/lemote/lm2e/Makefile
+++ b/arch/mips/lemote/lm2e/Makefile
@@ -4,5 +4,4 @@
4 4
5obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o 5obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o
6 6
7EXTRA_AFLAGS := $(CFLAGS)
8EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c
index 3efb1cf111f2..824336812198 100644
--- a/arch/mips/lemote/lm2e/prom.c
+++ b/arch/mips/lemote/lm2e/prom.c
@@ -57,7 +57,6 @@ void __init prom_init(void)
57 arg = (int *)fw_arg1; 57 arg = (int *)fw_arg1;
58 env = (int *)fw_arg2; 58 env = (int *)fw_arg2;
59 59
60 mips_machgroup = MACH_GROUP_LEMOTE;
61 mips_machtype = MACH_LEMOTE_FULONG; 60 mips_machtype = MACH_LEMOTE_FULONG;
62 61
63 prom_init_cmdline(); 62 prom_init_cmdline();
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
index f34350a4f271..09314a20f9fb 100644
--- a/arch/mips/lemote/lm2e/setup.c
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -58,13 +58,13 @@ void __init plat_timer_setup(struct irqaction *irq)
58 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); 58 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
59} 59}
60 60
61static void __init loongson2e_time_init(void) 61void __init plat_time_init(void)
62{ 62{
63 /* setup mips r4k timer */ 63 /* setup mips r4k timer */
64 mips_hpt_frequency = cpu_clock_freq / 2; 64 mips_hpt_frequency = cpu_clock_freq / 2;
65} 65}
66 66
67static unsigned long __init mips_rtc_get_time(void) 67unsigned long read_persistent_clock(void)
68{ 68{
69 return mc146818_get_cmos_time(); 69 return mc146818_get_cmos_time();
70} 70}
@@ -89,9 +89,6 @@ void __init plat_mem_setup(void)
89 89
90 mips_reboot_setup(); 90 mips_reboot_setup();
91 91
92 board_time_init = loongson2e_time_init;
93 rtc_mips_get_time = mips_rtc_get_time;
94
95 __wbflush = wbflush_loongson2e; 92 __wbflush = wbflush_loongson2e;
96 93
97 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); 94 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c
index e2ff6072b5a3..b33d8569bcb0 100644
--- a/arch/mips/lib/ucmpdi2.c
+++ b/arch/mips/lib/ucmpdi2.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5word_type __ucmpdi2 (unsigned long long a, unsigned long long b) 5word_type __ucmpdi2(unsigned long long a, unsigned long long b)
6{ 6{
7 const DWunion au = {.ll = a}; 7 const DWunion au = {.ll = a};
8 const DWunion bu = {.ll = b}; 8 const DWunion bu = {.ll = b};
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 17419e11ecad..b08fc65c13a6 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -178,24 +178,24 @@ static int isBranchInstr(mips_instruction * i)
178#define FR_BIT 0 178#define FR_BIT 0
179#endif 179#endif
180 180
181#define SIFROMREG(si,x) ((si) = \ 181#define SIFROMREG(si, x) ((si) = \
182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
183 (int)ctx->fpr[x] : \ 183 (int)ctx->fpr[x] : \
184 (int)(ctx->fpr[x & ~1] >> 32 )) 184 (int)(ctx->fpr[x & ~1] >> 32 ))
185#define SITOREG(si,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ 185#define SITOREG(si, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
189 189
190#define DIFROMREG(di,x) ((di) = \ 190#define DIFROMREG(di, x) ((di) = \
191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)]) 191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)])
192#define DITOREG(di,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ 192#define DITOREG(di, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
193 = (di)) 193 = (di))
194 194
195#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x) 195#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
196#define SPTOREG(sp,x) SITOREG((sp).bits,x) 196#define SPTOREG(sp, x) SITOREG((sp).bits, x)
197#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x) 197#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
198#define DPTOREG(dp,x) DITOREG((dp).bits,x) 198#define DPTOREG(dp, x) DITOREG((dp).bits, x)
199 199
200/* 200/*
201 * Emulate the single floating point instruction pointed at by EPC. 201 * Emulate the single floating point instruction pointed at by EPC.
@@ -549,16 +549,16 @@ static const unsigned char cmptab[8] = {
549 */ 549 */
550 550
551#define DEF3OP(name, p, f1, f2, f3) \ 551#define DEF3OP(name, p, f1, f2, f3) \
552static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ 552static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
553 ieee754##p t) \ 553 ieee754##p t) \
554{ \ 554{ \
555 struct _ieee754_csr ieee754_csr_save; \ 555 struct _ieee754_csr ieee754_csr_save; \
556 s = f1 (s, t); \ 556 s = f1(s, t); \
557 ieee754_csr_save = ieee754_csr; \ 557 ieee754_csr_save = ieee754_csr; \
558 s = f2 (s, r); \ 558 s = f2(s, r); \
559 ieee754_csr_save.cx |= ieee754_csr.cx; \ 559 ieee754_csr_save.cx |= ieee754_csr.cx; \
560 ieee754_csr_save.sx |= ieee754_csr.sx; \ 560 ieee754_csr_save.sx |= ieee754_csr.sx; \
561 s = f3 (s); \ 561 s = f3(s); \
562 ieee754_csr.cx |= ieee754_csr_save.cx; \ 562 ieee754_csr.cx |= ieee754_csr_save.cx; \
563 ieee754_csr.sx |= ieee754_csr_save.sx; \ 563 ieee754_csr.sx |= ieee754_csr_save.sx; \
564 return s; \ 564 return s; \
@@ -584,12 +584,12 @@ static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
584 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 584 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
585} 585}
586 586
587DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,); 587DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
588DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,); 588DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
589DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 589DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
590DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 590DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
591DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,); 591DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
592DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,); 592DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
593DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 593DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
594DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 594DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
595 595
diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
index f2373902f524..48908a809c17 100644
--- a/arch/mips/math-emu/dp_mul.c
+++ b/arch/mips/math-emu/dp_mul.c
@@ -121,7 +121,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y)
121 */ 121 */
122 122
123 /* 32 * 32 => 64 */ 123 /* 32 * 32 => 64 */
124#define DPXMULT(x,y) ((u64)(x) * (u64)y) 124#define DPXMULT(x, y) ((u64)(x) * (u64)y)
125 125
126 { 126 {
127 unsigned lxm = xm; 127 unsigned lxm = xm;
diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c
index a93c45dbdefd..946aee331788 100644
--- a/arch/mips/math-emu/ieee754.c
+++ b/arch/mips/math-emu/ieee754.c
@@ -47,13 +47,13 @@
47 47
48 48
49#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) 49#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__)
50#define SPSTR(s,b,m) {m,b,s} 50#define SPSTR(s, b, m) {m, b, s}
51#define DPSTR(s,b,mh,ml) {ml,mh,b,s} 51#define DPSTR(s, b, mh, ml) {ml, mh, b, s}
52#endif 52#endif
53 53
54#ifdef __MIPSEB__ 54#ifdef __MIPSEB__
55#define SPSTR(s,b,m) {s,b,m} 55#define SPSTR(s, b, m) {s, b, m}
56#define DPSTR(s,b,mh,ml) {s,b,mh,ml} 56#define DPSTR(s, b, mh, ml) {s, b, mh, ml}
57#endif 57#endif
58 58
59const struct ieee754dp_konst __ieee754dp_spcvals[] = { 59const struct ieee754dp_konst __ieee754dp_spcvals[] = {
@@ -65,7 +65,7 @@ const struct ieee754dp_konst __ieee754dp_spcvals[] = {
65 DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */ 65 DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */
66 DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */ 66 DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */
67 DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */ 67 DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */
68 DPSTR(0,DP_EMAX+1+DP_EBIAS,0x7FFFF,0xFFFFFFFF), /* + indef quiet Nan */ 68 DPSTR(0, DP_EMAX+1+DP_EBIAS, 0x7FFFF, 0xFFFFFFFF), /* + indef quiet Nan */
69 DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */ 69 DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */
70 DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */ 70 DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */
71 DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */ 71 DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */
@@ -85,7 +85,7 @@ const struct ieee754sp_konst __ieee754sp_spcvals[] = {
85 SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */ 85 SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */
86 SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */ 86 SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */
87 SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */ 87 SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */
88 SPSTR(0,SP_EMAX+1+SP_EBIAS,0x3FFFFF), /* + indef quiet Nan */ 88 SPSTR(0, SP_EMAX+1+SP_EBIAS, 0x3FFFFF), /* + indef quiet Nan */
89 SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */ 89 SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */
90 SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */ 90 SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */
91 SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */ 91 SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */
diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h
index a37370dae232..8977eb585a37 100644
--- a/arch/mips/math-emu/ieee754dp.h
+++ b/arch/mips/math-emu/ieee754dp.h
@@ -43,8 +43,8 @@
43/* convert denormal to normalized with extended exponent */ 43/* convert denormal to normalized with extended exponent */
44#define DPDNORMx(m,e) \ 44#define DPDNORMx(m,e) \
45 while( (m >> DP_MBITS) == 0) { m <<= 1; e--; } 45 while( (m >> DP_MBITS) == 0) { m <<= 1; e--; }
46#define DPDNORMX DPDNORMx(xm,xe) 46#define DPDNORMX DPDNORMx(xm, xe)
47#define DPDNORMY DPDNORMx(ym,ye) 47#define DPDNORMY DPDNORMx(ym, ye)
48 48
49static __inline ieee754dp builddp(int s, int bx, u64 m) 49static __inline ieee754dp builddp(int s, int bx, u64 m)
50{ 50{
@@ -71,13 +71,13 @@ extern ieee754dp ieee754dp_bestnan(ieee754dp, ieee754dp);
71extern ieee754dp ieee754dp_format(int, int, u64); 71extern ieee754dp ieee754dp_format(int, int, u64);
72 72
73 73
74#define DPNORMRET2(s,e,m,name,a0,a1) \ 74#define DPNORMRET2(s, e, m, name, a0, a1) \
75{ \ 75{ \
76 ieee754dp V = ieee754dp_format(s,e,m); \ 76 ieee754dp V = ieee754dp_format(s, e, m); \
77 if(TSTX()) \ 77 if(TSTX()) \
78 return ieee754dp_xcpt(V,name,a0,a1); \ 78 return ieee754dp_xcpt(V, name, a0, a1); \
79 else \ 79 else \
80 return V; \ 80 return V; \
81} 81}
82 82
83#define DPNORMRET1(s,e,m,name,a0) DPNORMRET2(s,e,m,name,a0,a0) 83#define DPNORMRET1(s, e, m, name, a0) DPNORMRET2(s, e, m, name, a0, a0)
diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index 4a5a81d6b893..1a846c5425cd 100644
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -55,16 +55,16 @@
55#define DPBEXP(dp) (dp.parts.bexp) 55#define DPBEXP(dp) (dp.parts.bexp)
56#define DPMANT(dp) (dp.parts.mant) 56#define DPMANT(dp) (dp.parts.mant)
57 57
58#define CLPAIR(x,y) ((x)*6+(y)) 58#define CLPAIR(x, y) ((x)*6+(y))
59 59
60#define CLEARCX \ 60#define CLEARCX \
61 (ieee754_csr.cx = 0) 61 (ieee754_csr.cx = 0)
62 62
63#define SETCX(x) \ 63#define SETCX(x) \
64 (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x)) 64 (ieee754_csr.cx |= (x), ieee754_csr.sx |= (x))
65 65
66#define SETANDTESTCX(x) \ 66#define SETANDTESTCX(x) \
67 (SETCX(x),ieee754_csr.mx & (x)) 67 (SETCX(x), ieee754_csr.mx & (x))
68 68
69#define TSTX() \ 69#define TSTX() \
70 (ieee754_csr.cx & ieee754_csr.mx) 70 (ieee754_csr.cx & ieee754_csr.mx)
@@ -76,7 +76,7 @@
76#define COMPYSP \ 76#define COMPYSP \
77 unsigned ym; int ye; int ys; int yc 77 unsigned ym; int ye; int ys; int yc
78 78
79#define EXPLODESP(v,vc,vs,ve,vm) \ 79#define EXPLODESP(v, vc, vs, ve, vm) \
80{\ 80{\
81 vs = SPSIGN(v);\ 81 vs = SPSIGN(v);\
82 ve = SPBEXP(v);\ 82 ve = SPBEXP(v);\
@@ -100,8 +100,8 @@
100 vc = IEEE754_CLASS_NORM;\ 100 vc = IEEE754_CLASS_NORM;\
101 }\ 101 }\
102} 102}
103#define EXPLODEXSP EXPLODESP(x,xc,xs,xe,xm) 103#define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm)
104#define EXPLODEYSP EXPLODESP(y,yc,ys,ye,ym) 104#define EXPLODEYSP EXPLODESP(y, yc, ys, ye, ym)
105 105
106 106
107#define COMPXDP \ 107#define COMPXDP \
@@ -110,7 +110,7 @@ u64 xm; int xe; int xs; int xc
110#define COMPYDP \ 110#define COMPYDP \
111u64 ym; int ye; int ys; int yc 111u64 ym; int ye; int ys; int yc
112 112
113#define EXPLODEDP(v,vc,vs,ve,vm) \ 113#define EXPLODEDP(v, vc, vs, ve, vm) \
114{\ 114{\
115 vm = DPMANT(v);\ 115 vm = DPMANT(v);\
116 vs = DPSIGN(v);\ 116 vs = DPSIGN(v);\
@@ -134,10 +134,10 @@ u64 ym; int ye; int ys; int yc
134 vc = IEEE754_CLASS_NORM;\ 134 vc = IEEE754_CLASS_NORM;\
135 }\ 135 }\
136} 136}
137#define EXPLODEXDP EXPLODEDP(x,xc,xs,xe,xm) 137#define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm)
138#define EXPLODEYDP EXPLODEDP(y,yc,ys,ye,ym) 138#define EXPLODEYDP EXPLODEDP(y, yc, ys, ye, ym)
139 139
140#define FLUSHDP(v,vc,vs,ve,vm) \ 140#define FLUSHDP(v, vc, vs, ve, vm) \
141 if(vc==IEEE754_CLASS_DNORM) {\ 141 if(vc==IEEE754_CLASS_DNORM) {\
142 if(ieee754_csr.nod) {\ 142 if(ieee754_csr.nod) {\
143 SETCX(IEEE754_INEXACT);\ 143 SETCX(IEEE754_INEXACT);\
@@ -148,7 +148,7 @@ u64 ym; int ye; int ys; int yc
148 }\ 148 }\
149 } 149 }
150 150
151#define FLUSHSP(v,vc,vs,ve,vm) \ 151#define FLUSHSP(v, vc, vs, ve, vm) \
152 if(vc==IEEE754_CLASS_DNORM) {\ 152 if(vc==IEEE754_CLASS_DNORM) {\
153 if(ieee754_csr.nod) {\ 153 if(ieee754_csr.nod) {\
154 SETCX(IEEE754_INEXACT);\ 154 SETCX(IEEE754_INEXACT);\
@@ -159,7 +159,7 @@ u64 ym; int ye; int ys; int yc
159 }\ 159 }\
160 } 160 }
161 161
162#define FLUSHXDP FLUSHDP(x,xc,xs,xe,xm) 162#define FLUSHXDP FLUSHDP(x, xc, xs, xe, xm)
163#define FLUSHYDP FLUSHDP(y,yc,ys,ye,ym) 163#define FLUSHYDP FLUSHDP(y, yc, ys, ye, ym)
164#define FLUSHXSP FLUSHSP(x,xc,xs,xe,xm) 164#define FLUSHXSP FLUSHSP(x, xc, xs, xe, xm)
165#define FLUSHYSP FLUSHSP(y,yc,ys,ye,ym) 165#define FLUSHYSP FLUSHSP(y, yc, ys, ye, ym)
diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
index ae82f51297e5..9917c1e4d947 100644
--- a/arch/mips/math-emu/ieee754sp.h
+++ b/arch/mips/math-emu/ieee754sp.h
@@ -48,8 +48,8 @@
48/* convert denormal to normalized with extended exponent */ 48/* convert denormal to normalized with extended exponent */
49#define SPDNORMx(m,e) \ 49#define SPDNORMx(m,e) \
50 while( (m >> SP_MBITS) == 0) { m <<= 1; e--; } 50 while( (m >> SP_MBITS) == 0) { m <<= 1; e--; }
51#define SPDNORMX SPDNORMx(xm,xe) 51#define SPDNORMX SPDNORMx(xm, xe)
52#define SPDNORMY SPDNORMx(ym,ye) 52#define SPDNORMY SPDNORMx(ym, ye)
53 53
54static __inline ieee754sp buildsp(int s, int bx, unsigned m) 54static __inline ieee754sp buildsp(int s, int bx, unsigned m)
55{ 55{
@@ -77,13 +77,13 @@ extern ieee754sp ieee754sp_bestnan(ieee754sp, ieee754sp);
77extern ieee754sp ieee754sp_format(int, int, unsigned); 77extern ieee754sp ieee754sp_format(int, int, unsigned);
78 78
79 79
80#define SPNORMRET2(s,e,m,name,a0,a1) \ 80#define SPNORMRET2(s, e, m, name, a0, a1) \
81{ \ 81{ \
82 ieee754sp V = ieee754sp_format(s,e,m); \ 82 ieee754sp V = ieee754sp_format(s, e, m); \
83 if(TSTX()) \ 83 if(TSTX()) \
84 return ieee754sp_xcpt(V,name,a0,a1); \ 84 return ieee754sp_xcpt(V, name, a0, a1); \
85 else \ 85 else \
86 return V; \ 86 return V; \
87} 87}
88 88
89#define SPNORMRET1(s,e,m,name,a0) SPNORMRET2(s,e,m,name,a0,a0) 89#define SPNORMRET1(s, e, m, name, a0) SPNORMRET2(s, e, m, name, a0, a0)
diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c
index fb65280f1780..00c98cff62dc 100644
--- a/arch/mips/mips-boards/atlas/atlas_gdb.c
+++ b/arch/mips/mips-boards/atlas/atlas_gdb.c
@@ -22,7 +22,7 @@
22#include <asm/mips-boards/saa9730_uart.h> 22#include <asm/mips-boards/saa9730_uart.h>
23 23
24#define INB(a) inb((unsigned long)a) 24#define INB(a) inb((unsigned long)a)
25#define OUTB(x,a) outb(x,(unsigned long)a) 25#define OUTB(x, a) outb(x, (unsigned long)a)
26 26
27/* 27/*
28 * This is the interface to the remote debugger stub 28 * This is the interface to the remote debugger stub
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 3c692abc2553..6fb29c3ff62d 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -112,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(void)
112 112
113static inline int clz(unsigned long x) 113static inline int clz(unsigned long x)
114{ 114{
115 __asm__ ( 115 __asm__(
116 " .set push \n" 116 " .set push \n"
117 " .set mips32 \n" 117 " .set mips32 \n"
118 " clz %0, %1 \n" 118 " clz %0, %1 \n"
@@ -194,7 +194,7 @@ asmlinkage void plat_irq_dispatch(void)
194 spurious_interrupt(); 194 spurious_interrupt();
195} 195}
196 196
197static inline void init_atlas_irqs (int base) 197static inline void init_atlas_irqs(int base)
198{ 198{
199 int i; 199 int i;
200 200
@@ -249,21 +249,21 @@ void __init arch_init_irq(void)
249 case MIPS_REVISION_CORID_CORE_24K: 249 case MIPS_REVISION_CORID_CORE_24K:
250 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 250 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
251 if (cpu_has_veic) 251 if (cpu_has_veic)
252 init_msc_irqs (MSC01E_INT_BASE, MSC01E_INT_BASE, 252 init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE,
253 msc_eicirqmap, msc_nr_eicirqs); 253 msc_eicirqmap, msc_nr_eicirqs);
254 else 254 else
255 init_msc_irqs (MSC01E_INT_BASE, MSC01C_INT_BASE, 255 init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE,
256 msc_irqmap, msc_nr_irqs); 256 msc_irqmap, msc_nr_irqs);
257 } 257 }
258 258
259 if (cpu_has_veic) { 259 if (cpu_has_veic) {
260 set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); 260 set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
261 setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); 261 setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
262 } else if (cpu_has_vint) { 262 } else if (cpu_has_vint) {
263 set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); 263 set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
264#ifdef CONFIG_MIPS_MT_SMTC 264#ifdef CONFIG_MIPS_MT_SMTC
265 setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, 265 setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
266 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); 266 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
267#else /* Not SMTC */ 267#else /* Not SMTC */
268 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); 268 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
269#endif /* CONFIG_MIPS_MT_SMTC */ 269#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index c68358a476dd..e405d112a067 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -35,8 +35,6 @@
35#include <asm/traps.h> 35#include <asm/traps.h>
36 36
37extern void mips_reboot_setup(void); 37extern void mips_reboot_setup(void);
38extern void mips_time_init(void);
39extern unsigned long mips_rtc_get_time(void);
40 38
41#ifdef CONFIG_KGDB 39#ifdef CONFIG_KGDB
42extern void kgdb_config(void); 40extern void kgdb_config(void);
@@ -57,15 +55,12 @@ void __init plat_mem_setup(void)
57 55
58 ioport_resource.end = 0x7fffffff; 56 ioport_resource.end = 0x7fffffff;
59 57
60 serial_init (); 58 serial_init();
61 59
62#ifdef CONFIG_KGDB 60#ifdef CONFIG_KGDB
63 kgdb_config(); 61 kgdb_config();
64#endif 62#endif
65 mips_reboot_setup(); 63 mips_reboot_setup();
66
67 board_time_init = mips_time_init;
68 rtc_mips_get_time = mips_rtc_get_time;
69} 64}
70 65
71static void __init serial_init(void) 66static void __init serial_init(void)
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index e2c7147fedf7..30f1f54cb68b 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -166,15 +166,15 @@ static void __init console_config(void)
166 bits = '8'; 166 bits = '8';
167 if (flow == '\0') 167 if (flow == '\0')
168 flow = 'r'; 168 flow = 'r';
169 sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 169 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
170 strcat (prom_getcmdline(), console_string); 170 strcat(prom_getcmdline(), console_string);
171 pr_info("Config serial console:%s\n", console_string); 171 pr_info("Config serial console:%s\n", console_string);
172 } 172 }
173} 173}
174#endif 174#endif
175 175
176#ifdef CONFIG_KGDB 176#ifdef CONFIG_KGDB
177void __init kgdb_config (void) 177void __init kgdb_config(void)
178{ 178{
179 extern int (*generic_putDebugChar)(char); 179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void); 180 extern char (*generic_getDebugChar)(void);
@@ -218,7 +218,7 @@ void __init kgdb_config (void)
218 { 218 {
219 char *s; 219 char *s;
220 for (s = "Please connect GDB to this port\r\n"; *s; ) 220 for (s = "Please connect GDB to this port\r\n"; *s; )
221 generic_putDebugChar (*s++); 221 generic_putDebugChar(*s++);
222 } 222 }
223 223
224 /* Breakpoint is invoked after interrupts are initialised */ 224 /* Breakpoint is invoked after interrupts are initialised */
@@ -226,7 +226,7 @@ void __init kgdb_config (void)
226} 226}
227#endif 227#endif
228 228
229void __init mips_nmi_setup (void) 229void __init mips_nmi_setup(void)
230{ 230{
231 void *base; 231 void *base;
232 extern char except_vec_nmi; 232 extern char except_vec_nmi;
@@ -238,7 +238,7 @@ void __init mips_nmi_setup (void)
238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
239} 239}
240 240
241void __init mips_ejtag_setup (void) 241void __init mips_ejtag_setup(void)
242{ 242{
243 void *base; 243 void *base;
244 extern char except_vec_ejtag_debug; 244 extern char except_vec_ejtag_debug;
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index ae39953da2c4..dc272c188233 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
125 return &mdesc[0]; 125 return &mdesc[0];
126} 126}
127 127
128static int __init prom_memtype_classify (unsigned int type) 128static int __init prom_memtype_classify(unsigned int type)
129{ 129{
130 switch (type) { 130 switch (type) {
131 case yamon_free: 131 case yamon_free:
@@ -158,7 +158,7 @@ void __init prom_meminit(void)
158 long type; 158 long type;
159 unsigned long base, size; 159 unsigned long base, size;
160 160
161 type = prom_memtype_classify (p->type); 161 type = prom_memtype_classify(p->type);
162 base = p->base; 162 base = p->base;
163 size = p->size; 163 size = p->size;
164 164
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index c9852206890a..b9743190609a 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -239,5 +239,5 @@ void __init mips_pcibios_init(void)
239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
240 ioport_resource.end = controller->io_resource->end; 240 ioport_resource.end = controller->io_resource->end;
241 241
242 register_pci_controller (controller); 242 register_pci_controller(controller);
243} 243}
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index d7bff9ca5356..1d00b778ff1e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -31,6 +31,7 @@
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h> 32#include <asm/mipsmtregs.h>
33#include <asm/hardirq.h> 33#include <asm/hardirq.h>
34#include <asm/i8253.h>
34#include <asm/irq.h> 35#include <asm/irq.h>
35#include <asm/div64.h> 36#include <asm/div64.h>
36#include <asm/cpu.h> 37#include <asm/cpu.h>
@@ -55,7 +56,6 @@ unsigned long cpu_khz;
55 56
56static int mips_cpu_timer_irq; 57static int mips_cpu_timer_irq;
57extern int cp0_perfcount_irq; 58extern int cp0_perfcount_irq;
58extern void smtc_timer_broadcast(void);
59 59
60static void mips_timer_dispatch(void) 60static void mips_timer_dispatch(void)
61{ 61{
@@ -68,108 +68,6 @@ static void mips_perf_dispatch(void)
68} 68}
69 69
70/* 70/*
71 * Redeclare until I get around mopping the timer code insanity on MIPS.
72 */
73extern int null_perf_irq(void);
74
75extern int (*perf_irq)(void);
76
77/*
78 * Possibly handle a performance counter interrupt.
79 * Return true if the timer interrupt should not be checked
80 */
81static inline int handle_perf_irq (int r2)
82{
83 /*
84 * The performance counter overflow interrupt may be shared with the
85 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
86 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
87 * and we can't reliably determine if a counter interrupt has also
88 * happened (!r2) then don't check for a timer interrupt.
89 */
90 return (cp0_perfcount_irq < 0) &&
91 perf_irq() == IRQ_HANDLED &&
92 !r2;
93}
94
95irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
96{
97 int cpu = smp_processor_id();
98
99#ifdef CONFIG_MIPS_MT_SMTC
100 /*
101 * In an SMTC system, one Count/Compare set exists per VPE.
102 * Which TC within a VPE gets the interrupt is essentially
103 * random - we only know that it shouldn't be one with
104 * IXMT set. Whichever TC gets the interrupt needs to
105 * send special interprocessor interrupts to the other
106 * TCs to make sure that they schedule, etc.
107 *
108 * That code is specific to the SMTC kernel, not to
109 * the a particular platform, so it's invoked from
110 * the general MIPS timer_interrupt routine.
111 */
112
113 /*
114 * We could be here due to timer interrupt,
115 * perf counter overflow, or both.
116 */
117 (void) handle_perf_irq(1);
118
119 if (read_c0_cause() & (1 << 30)) {
120 /*
121 * There are things we only want to do once per tick
122 * in an "MP" system. One TC of each VPE will take
123 * the actual timer interrupt. The others will get
124 * timer broadcast IPIs. We use whoever it is that takes
125 * the tick on VPE 0 to run the full timer_interrupt().
126 */
127 if (cpu_data[cpu].vpe_id == 0) {
128 timer_interrupt(irq, NULL);
129 } else {
130 write_c0_compare(read_c0_count() +
131 (mips_hpt_frequency/HZ));
132 local_timer_interrupt(irq, dev_id);
133 }
134 smtc_timer_broadcast();
135 }
136#else /* CONFIG_MIPS_MT_SMTC */
137 int r2 = cpu_has_mips_r2;
138
139 if (handle_perf_irq(r2))
140 goto out;
141
142 if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
143 goto out;
144
145 if (cpu == 0) {
146 /*
147 * CPU 0 handles the global timer interrupt job and process
148 * accounting resets count/compare registers to trigger next
149 * timer int.
150 */
151 timer_interrupt(irq, NULL);
152 } else {
153 /* Everyone else needs to reset the timer int here as
154 ll_local_timer_interrupt doesn't */
155 /*
156 * FIXME: need to cope with counter underflow.
157 * More support needs to be added to kernel/time for
158 * counter/timer interrupts on multiple CPU's
159 */
160 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
161
162 /*
163 * Other CPUs should do profiling and process accounting
164 */
165 local_timer_interrupt(irq, dev_id);
166 }
167out:
168#endif /* CONFIG_MIPS_MT_SMTC */
169 return IRQ_HANDLED;
170}
171
172/*
173 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 71 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
174 */ 72 */
175static unsigned int __init estimate_cpu_frequency(void) 73static unsigned int __init estimate_cpu_frequency(void)
@@ -224,19 +122,19 @@ static unsigned int __init estimate_cpu_frequency(void)
224 return count; 122 return count;
225} 123}
226 124
227unsigned long __init mips_rtc_get_time(void) 125unsigned long read_persistent_clock(void)
228{ 126{
229 return mc146818_get_cmos_time(); 127 return mc146818_get_cmos_time();
230} 128}
231 129
232void __init mips_time_init(void) 130void __init plat_time_init(void)
233{ 131{
234 unsigned int est_freq; 132 unsigned int est_freq;
235 133
236 /* Set Data mode - binary. */ 134 /* Set Data mode - binary. */
237 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
238 136
239 est_freq = estimate_cpu_frequency (); 137 est_freq = estimate_cpu_frequency();
240 138
241 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
242 (est_freq%1000000)*100/1000000); 140 (est_freq%1000000)*100/1000000);
@@ -244,38 +142,37 @@ void __init mips_time_init(void)
244 cpu_khz = est_freq / 1000; 142 cpu_khz = est_freq / 1000;
245 143
246 mips_scroll_message(); 144 mips_scroll_message();
145#ifdef CONFIG_I8253 /* Only Malta has a PIT */
146 setup_pit_timer();
147#endif
247} 148}
248 149
249irqreturn_t mips_perf_interrupt(int irq, void *dev_id) 150//static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
250{ 151//{
251 return perf_irq(); 152// return perf_irq();
252} 153//}
253 154
254static struct irqaction perf_irqaction = { 155//static struct irqaction perf_irqaction = {
255 .handler = mips_perf_interrupt, 156// .handler = mips_perf_interrupt,
256 .flags = IRQF_DISABLED | IRQF_PERCPU, 157// .flags = IRQF_DISABLED | IRQF_PERCPU,
257 .name = "performance", 158// .name = "performance",
258}; 159//};
259 160
260void __init plat_perf_setup(struct irqaction *irq) 161void __init plat_perf_setup(void)
261{ 162{
163// struct irqaction *irq = &perf_irqaction;
164
262 cp0_perfcount_irq = -1; 165 cp0_perfcount_irq = -1;
263 166
264#ifdef MSC01E_INT_BASE 167#ifdef MSC01E_INT_BASE
265 if (cpu_has_veic) { 168 if (cpu_has_veic) {
266 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); 169 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
267 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 170 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
268 } else 171 } else
269#endif 172#endif
270 if (cp0_perfcount_irq >= 0) { 173 if (cp0_perfcount_irq >= 0) {
271 if (cpu_has_vint) 174 if (cpu_has_vint)
272 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); 175 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
273#ifdef CONFIG_MIPS_MT_SMTC
274 setup_irq_smtc(cp0_perfcount_irq, irq,
275 0x100 << cp0_perfcount_irq);
276#else
277 setup_irq(cp0_perfcount_irq, irq);
278#endif /* CONFIG_MIPS_MT_SMTC */
279#ifdef CONFIG_SMP 176#ifdef CONFIG_SMP
280 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); 177 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
281#endif 178#endif
@@ -286,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq)
286{ 183{
287#ifdef MSC01E_INT_BASE 184#ifdef MSC01E_INT_BASE
288 if (cpu_has_veic) { 185 if (cpu_has_veic) {
289 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); 186 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
290 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 187 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
291 } 188 }
292 else 189 else
@@ -297,8 +194,6 @@ void __init plat_timer_setup(struct irqaction *irq)
297 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 194 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
298 } 195 }
299 196
300 /* we are using the cpu counter for timer interrupts */
301 irq->handler = mips_timer_interrupt; /* we use our own handler */
302#ifdef CONFIG_MIPS_MT_SMTC 197#ifdef CONFIG_MIPS_MT_SMTC
303 setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); 198 setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
304#else 199#else
@@ -308,5 +203,5 @@ void __init plat_timer_setup(struct irqaction *irq)
308 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 203 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
309#endif 204#endif
310 205
311 plat_perf_setup(&perf_irqaction); 206 plat_perf_setup();
312} 207}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index b73f21823c5e..f010261b75d8 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -124,7 +124,7 @@ static void corehi_irqdispatch(void)
124{ 124{
125 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 125 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
126 unsigned int pcimstat, intisr, inten, intpol; 126 unsigned int pcimstat, intisr, inten, intpol;
127 unsigned int intrcause,datalo,datahi; 127 unsigned int intrcause, datalo, datahi;
128 struct pt_regs *regs = get_irq_regs(); 128 struct pt_regs *regs = get_irq_regs();
129 129
130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
@@ -178,7 +178,7 @@ static void corehi_irqdispatch(void)
178 178
179static inline int clz(unsigned long x) 179static inline int clz(unsigned long x)
180{ 180{
181 __asm__ ( 181 __asm__(
182 " .set push \n" 182 " .set push \n"
183 " .set mips32 \n" 183 " .set mips32 \n"
184 " clz %0, %1 \n" 184 " clz %0, %1 \n"
@@ -303,32 +303,32 @@ void __init arch_init_irq(void)
303 case MIPS_REVISION_SCON_SOCIT: 303 case MIPS_REVISION_SCON_SOCIT:
304 case MIPS_REVISION_SCON_ROCIT: 304 case MIPS_REVISION_SCON_ROCIT:
305 if (cpu_has_veic) 305 if (cpu_has_veic)
306 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 306 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
307 else 307 else
308 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 308 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
309 break; 309 break;
310 310
311 case MIPS_REVISION_SCON_SOCITSC: 311 case MIPS_REVISION_SCON_SOCITSC:
312 case MIPS_REVISION_SCON_SOCITSCP: 312 case MIPS_REVISION_SCON_SOCITSCP:
313 if (cpu_has_veic) 313 if (cpu_has_veic)
314 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 314 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
315 else 315 else
316 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 316 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
317 } 317 }
318 318
319 if (cpu_has_veic) { 319 if (cpu_has_veic) {
320 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); 320 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
321 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); 321 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
322 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 322 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
323 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 323 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
324 } 324 }
325 else if (cpu_has_vint) { 325 else if (cpu_has_vint) {
326 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 326 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); 327 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 328#ifdef CONFIG_MIPS_MT_SMTC
329 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 329 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
330 (0x100 << MIPSCPU_INT_I8259A)); 330 (0x100 << MIPSCPU_INT_I8259A));
331 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 331 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
333 /* 333 /*
334 * Temporary hack to ensure that the subsidiary device 334 * Temporary hack to ensure that the subsidiary device
@@ -343,12 +343,12 @@ void __init arch_init_irq(void)
343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
344 } 344 }
345#else /* Not SMTC */ 345#else /* Not SMTC */
346 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 346 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
347 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 347 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
348#endif /* CONFIG_MIPS_MT_SMTC */ 348#endif /* CONFIG_MIPS_MT_SMTC */
349 } 349 }
350 else { 350 else {
351 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 351 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
352 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 352 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
353 } 353 }
354} 354}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 8f1b78dfd89f..9a2636e56243 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -36,7 +36,6 @@
36#endif 36#endif
37 37
38extern void mips_reboot_setup(void); 38extern void mips_reboot_setup(void);
39extern void mips_time_init(void);
40extern unsigned long mips_rtc_get_time(void); 39extern unsigned long mips_rtc_get_time(void);
41 40
42#ifdef CONFIG_KGDB 41#ifdef CONFIG_KGDB
@@ -100,7 +99,7 @@ void __init plat_mem_setup(void)
100 enable_dma(4); 99 enable_dma(4);
101 100
102#ifdef CONFIG_KGDB 101#ifdef CONFIG_KGDB
103 kgdb_config (); 102 kgdb_config();
104#endif 103#endif
105 104
106 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
@@ -109,7 +108,7 @@ void __init plat_mem_setup(void)
109 argptr = prom_getcmdline(); 108 argptr = prom_getcmdline();
110 if (strstr(argptr, "debug")) { 109 if (strstr(argptr, "debug")) {
111 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
112 printk ("Enabled Bonito debug mode\n"); 111 printk("Enabled Bonito debug mode\n");
113 } 112 }
114 else 113 else
115 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
@@ -160,14 +159,14 @@ void __init plat_mem_setup(void)
160 if (pciclock != 33 && !strstr (argptr, "idebus=")) { 159 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
161 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); 160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
162 argptr += strlen(argptr); 161 argptr += strlen(argptr);
163 sprintf (argptr, " idebus=%d", pciclock); 162 sprintf(argptr, " idebus=%d", pciclock);
164 if (pciclock < 20 || pciclock > 66) 163 if (pciclock < 20 || pciclock > 66)
165 printk ("WARNING: IDE timing calculations will be incorrect\n"); 164 printk("WARNING: IDE timing calculations will be incorrect\n");
166 } 165 }
167 } 166 }
168#endif 167#endif
169#ifdef CONFIG_BLK_DEV_FD 168#ifdef CONFIG_BLK_DEV_FD
170 fd_activate (); 169 fd_activate();
171#endif 170#endif
172#ifdef CONFIG_VT 171#ifdef CONFIG_VT
173#if defined(CONFIG_VGA_CONSOLE) 172#if defined(CONFIG_VGA_CONSOLE)
@@ -177,7 +176,7 @@ void __init plat_mem_setup(void)
177 0, /* orig-video-page */ 176 0, /* orig-video-page */
178 0, /* orig-video-mode */ 177 0, /* orig-video-mode */
179 80, /* orig-video-cols */ 178 80, /* orig-video-cols */
180 0,0,0, /* ega_ax, ega_bx, ega_cx */ 179 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
181 25, /* orig-video-lines */ 180 25, /* orig-video-lines */
182 VIDEO_TYPE_VGAC, /* orig-video-isVGA */ 181 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
183 16 /* orig-video-points */ 182 16 /* orig-video-points */
@@ -185,7 +184,4 @@ void __init plat_mem_setup(void)
185#endif 184#endif
186#endif 185#endif
187 mips_reboot_setup(); 186 mips_reboot_setup();
188
189 board_time_init = mips_time_init;
190 rtc_mips_get_time = mips_rtc_get_time;
191} 187}
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index ae05d058cb37..5c980f4a48fe 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -88,3 +88,53 @@ void __cpuinit prom_smp_finish(void)
88void prom_cpus_done(void) 88void prom_cpus_done(void)
89{ 89{
90} 90}
91
92#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
93/*
94 * IRQ affinity hook
95 */
96
97
98void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity)
99{
100 cpumask_t tmask = affinity;
101 int cpu = 0;
102 void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff);
103
104 /*
105 * On the legacy Malta development board, all I/O interrupts
106 * are routed through the 8259 and combined in a single signal
107 * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
108 * that signal is brought to IP2 of both VPEs. To avoid racing
109 * concurrent interrupt service events, IP2 is enabled only on
110 * one VPE, by convention VPE0. So long as no bits are ever
111 * cleared in the affinity mask, there will never be any
112 * interrupt forwarding. But as soon as a program or operator
113 * sets affinity for one of the related IRQs, we need to make
114 * sure that we don't ever try to forward across the VPE boundry,
115 * at least not until we engineer a system where the interrupt
116 * _ack() or _end() function can somehow know that it corresponds
117 * to an interrupt taken on another VPE, and perform the appropriate
118 * restoration of Status.IM state using MFTR/MTTR instead of the
119 * normal local behavior. We also ensure that no attempt will
120 * be made to forward to an offline "CPU".
121 */
122
123 for_each_cpu_mask(cpu, affinity) {
124 if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
125 cpu_clear(cpu, tmask);
126 }
127 irq_desc[irq].affinity = tmask;
128
129 if (cpus_empty(tmask))
130 /*
131 * We could restore a default mask here, but the
132 * runtime code can anyway deal with the null set
133 */
134 printk(KERN_WARNING
135 "IRQ affinity leaves no legal CPU for IRQ %d\n", irq);
136
137 /* Do any generic SMTC IRQ affinity setup */
138 smtc_set_irq_affinity(irq, tmask);
139}
140#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9ca0f82f1360..ec6dd194c14a 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -31,7 +31,7 @@
31 31
32static inline int clz(unsigned long x) 32static inline int clz(unsigned long x)
33{ 33{
34 __asm__ ( 34 __asm__(
35 " .set push \n" 35 " .set push \n"
36 " .set mips32 \n" 36 " .set mips32 \n"
37 " clz %0, %1 \n" 37 " clz %0, %1 \n"
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 5f70eaf01fab..1fb61b852304 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -35,7 +35,6 @@
35#include <asm/time.h> 35#include <asm/time.h>
36 36
37extern void mips_reboot_setup(void); 37extern void mips_reboot_setup(void);
38extern void mips_time_init(void);
39 38
40static void __init serial_init(void); 39static void __init serial_init(void);
41 40
@@ -50,9 +49,7 @@ void __init plat_mem_setup(void)
50{ 49{
51 ioport_resource.end = 0x7fffffff; 50 ioport_resource.end = 0x7fffffff;
52 51
53 serial_init (); 52 serial_init();
54
55 board_time_init = mips_time_init;
56 53
57 mips_reboot_setup(); 54 mips_reboot_setup();
58} 55}
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
index 5cbc3509ab52..46067ad542dc 100644
--- a/arch/mips/mipssim/sim_int.c
+++ b/arch/mips/mipssim/sim_int.c
@@ -25,7 +25,7 @@
25 25
26static inline int clz(unsigned long x) 26static inline int clz(unsigned long x)
27{ 27{
28 __asm__ ( 28 __asm__(
29 " .set push \n" 29 " .set push \n"
30 " .set mips32 \n" 30 " .set mips32 \n"
31 " clz %0, %1 \n" 31 " clz %0, %1 \n"
diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c
index 2312483eb838..953d836a7713 100644
--- a/arch/mips/mipssim/sim_mem.c
+++ b/arch/mips/mipssim/sim_mem.c
@@ -69,7 +69,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
69 return &mdesc[0]; 69 return &mdesc[0];
70} 70}
71 71
72static int __init prom_memtype_classify (unsigned int type) 72static int __init prom_memtype_classify(unsigned int type)
73{ 73{
74 switch (type) { 74 switch (type) {
75 case simmem_free: 75 case simmem_free:
@@ -90,7 +90,7 @@ void __init prom_meminit(void)
90 long type; 90 long type;
91 unsigned long base, size; 91 unsigned long base, size;
92 92
93 type = prom_memtype_classify (p->type); 93 type = prom_memtype_classify(p->type);
94 base = p->base; 94 base = p->base;
95 size = p->size; 95 size = p->size;
96 96
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index d012719c4d24..452c129d02c1 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -36,7 +36,6 @@
36#include <asm/mips-boards/simint.h> 36#include <asm/mips-boards/simint.h>
37 37
38 38
39extern void sim_time_init(void);
40static void __init serial_init(void); 39static void __init serial_init(void);
41unsigned int _isbonito = 0; 40unsigned int _isbonito = 0;
42 41
@@ -54,7 +53,6 @@ void __init plat_mem_setup(void)
54 53
55 serial_init(); 54 serial_init();
56 55
57 board_time_init = sim_time_init;
58 pr_info("Linux started...\n"); 56 pr_info("Linux started...\n");
59 57
60#ifdef CONFIG_MIPS_MT_SMP 58#ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index a0f5a5dca1b2..e7fa0d1078a3 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -23,77 +23,6 @@
23 23
24unsigned long cpu_khz; 24unsigned long cpu_khz;
25 25
26irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
27{
28#ifdef CONFIG_SMP
29 int cpu = smp_processor_id();
30
31 /*
32 * CPU 0 handles the global timer interrupt job
33 * resets count/compare registers to trigger next timer int.
34 */
35#ifndef CONFIG_MIPS_MT_SMTC
36 if (cpu == 0) {
37 timer_interrupt(irq, dev_id);
38 } else {
39 /* Everyone else needs to reset the timer int here as
40 ll_local_timer_interrupt doesn't */
41 /*
42 * FIXME: need to cope with counter underflow.
43 * More support needs to be added to kernel/time for
44 * counter/timer interrupts on multiple CPU's
45 */
46 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
47 }
48#else /* SMTC */
49 /*
50 * In SMTC system, one Count/Compare set exists per VPE.
51 * Which TC within a VPE gets the interrupt is essentially
52 * random - we only know that it shouldn't be one with
53 * IXMT set. Whichever TC gets the interrupt needs to
54 * send special interprocessor interrupts to the other
55 * TCs to make sure that they schedule, etc.
56 *
57 * That code is specific to the SMTC kernel, not to
58 * the simulation platform, so it's invoked from
59 * the general MIPS timer_interrupt routine.
60 *
61 * We have a problem in that the interrupt vector code
62 * had to turn off the timer IM bit to avoid redundant
63 * entries, but we may never get to mips_cpu_irq_end
64 * to turn it back on again if the scheduler gets
65 * involved. So we clear the pending timer here,
66 * and re-enable the mask...
67 */
68
69 int vpflags = dvpe();
70 write_c0_compare (read_c0_count() - 1);
71 clear_c0_cause(0x100 << cp0_compare_irq);
72 set_c0_status(0x100 << cp0_compare_irq);
73 irq_enable_hazard();
74 evpe(vpflags);
75
76 if (cpu_data[cpu].vpe_id == 0)
77 timer_interrupt(irq, dev_id);
78 else
79 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
80 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
81
82#endif /* CONFIG_MIPS_MT_SMTC */
83
84 /*
85 * every CPU should do profiling and process accounting
86 */
87 local_timer_interrupt (irq, dev_id);
88
89 return IRQ_HANDLED;
90#else
91 return timer_interrupt (irq, dev_id);
92#endif
93}
94
95
96
97/* 26/*
98 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 27 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
99 */ 28 */
@@ -146,7 +75,7 @@ static unsigned int __init estimate_cpu_frequency(void)
146 return count; 75 return count;
147} 76}
148 77
149void __init sim_time_init(void) 78void __init plat_time_init(void)
150{ 79{
151 unsigned int est_freq, flags; 80 unsigned int est_freq, flags;
152 81
@@ -155,7 +84,7 @@ void __init sim_time_init(void)
155 /* Set Data mode - binary. */ 84 /* Set Data mode - binary. */
156 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 85 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
157 86
158 est_freq = estimate_cpu_frequency (); 87 est_freq = estimate_cpu_frequency();
159 88
160 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, 89 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
161 (est_freq % 1000000) * 100 / 1000000); 90 (est_freq % 1000000) * 100 / 1000000);
@@ -185,7 +114,6 @@ void __init plat_timer_setup(struct irqaction *irq)
185 } 114 }
186 115
187 /* we are using the cpu counter for timer interrupts */ 116 /* we are using the cpu counter for timer interrupts */
188 irq->handler = sim_timer_interrupt;
189 setup_irq(mips_cpu_timer_irq, irq); 117 setup_irq(mips_cpu_timer_irq, irq);
190 118
191#ifdef CONFIG_SMP 119#ifdef CONFIG_SMP
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 43e4810dcaa8..32fd5db95774 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
22obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o 22obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o
23obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 23obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
24obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 24obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
25obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ 25obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \
26 tlb-r4k.o 26 tlb-r4k.o
27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o 27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o
28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 59868a1edf66..c55312f6fd3a 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -121,7 +121,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end)
121 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); 121 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
122 122
123 for (i = 0; i < size; i += 0x080) { 123 for (i = 0; i < size; i += 0x080) {
124 asm ( "sb\t$0, 0x000(%0)\n\t" 124 asm( "sb\t$0, 0x000(%0)\n\t"
125 "sb\t$0, 0x004(%0)\n\t" 125 "sb\t$0, 0x004(%0)\n\t"
126 "sb\t$0, 0x008(%0)\n\t" 126 "sb\t$0, 0x008(%0)\n\t"
127 "sb\t$0, 0x00c(%0)\n\t" 127 "sb\t$0, 0x00c(%0)\n\t"
@@ -178,7 +178,7 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
178 write_c0_status((ST0_ISC|flags)&~ST0_IEC); 178 write_c0_status((ST0_ISC|flags)&~ST0_IEC);
179 179
180 for (i = 0; i < size; i += 0x080) { 180 for (i = 0; i < size; i += 0x080) {
181 asm ( "sb\t$0, 0x000(%0)\n\t" 181 asm( "sb\t$0, 0x000(%0)\n\t"
182 "sb\t$0, 0x004(%0)\n\t" 182 "sb\t$0, 0x004(%0)\n\t"
183 "sb\t$0, 0x008(%0)\n\t" 183 "sb\t$0, 0x008(%0)\n\t"
184 "sb\t$0, 0x00c(%0)\n\t" 184 "sb\t$0, 0x00c(%0)\n\t"
@@ -217,8 +217,8 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
217 write_c0_status(flags); 217 write_c0_status(flags);
218} 218}
219 219
220static inline unsigned long get_phys_page (unsigned long addr, 220static inline unsigned long get_phys_page(unsigned long addr,
221 struct mm_struct *mm) 221 struct mm_struct *mm)
222{ 222{
223 pgd_t *pgd; 223 pgd_t *pgd;
224 pud_t *pud; 224 pud_t *pud;
@@ -281,13 +281,13 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
281 write_c0_status(flags&~ST0_IEC); 281 write_c0_status(flags&~ST0_IEC);
282 282
283 /* Fill the TLB to avoid an exception with caches isolated. */ 283 /* Fill the TLB to avoid an exception with caches isolated. */
284 asm ( "lw\t$0, 0x000(%0)\n\t" 284 asm( "lw\t$0, 0x000(%0)\n\t"
285 "lw\t$0, 0x004(%0)\n\t" 285 "lw\t$0, 0x004(%0)\n\t"
286 : : "r" (addr) ); 286 : : "r" (addr) );
287 287
288 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); 288 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
289 289
290 asm ( "sb\t$0, 0x000(%0)\n\t" 290 asm( "sb\t$0, 0x000(%0)\n\t"
291 "sb\t$0, 0x004(%0)\n\t" 291 "sb\t$0, 0x004(%0)\n\t"
292 : : "r" (addr) ); 292 : : "r" (addr) );
293 293
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bad571971bf6..971f6c047b8a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -8,7 +8,9 @@
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/highmem.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/linkage.h>
12#include <linux/sched.h> 14#include <linux/sched.h>
13#include <linux/mm.h> 15#include <linux/mm.h>
14#include <linux/bitops.h> 16#include <linux/bitops.h>
@@ -162,12 +164,12 @@ static inline void tx49_blast_icache32(void)
162 /* I'm in even chunk. blast odd chunks */ 164 /* I'm in even chunk. blast odd chunks */
163 for (ws = 0; ws < ws_end; ws += ws_inc) 165 for (ws = 0; ws < ws_end; ws += ws_inc)
164 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 166 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
165 cache32_unroll32(addr|ws,Index_Invalidate_I); 167 cache32_unroll32(addr|ws, Index_Invalidate_I);
166 CACHE32_UNROLL32_ALIGN; 168 CACHE32_UNROLL32_ALIGN;
167 /* I'm in odd chunk. blast even chunks */ 169 /* I'm in odd chunk. blast even chunks */
168 for (ws = 0; ws < ws_end; ws += ws_inc) 170 for (ws = 0; ws < ws_end; ws += ws_inc)
169 for (addr = start; addr < end; addr += 0x400 * 2) 171 for (addr = start; addr < end; addr += 0x400 * 2)
170 cache32_unroll32(addr|ws,Index_Invalidate_I); 172 cache32_unroll32(addr|ws, Index_Invalidate_I);
171} 173}
172 174
173static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 175static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
@@ -193,12 +195,12 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
193 /* I'm in even chunk. blast odd chunks */ 195 /* I'm in even chunk. blast odd chunks */
194 for (ws = 0; ws < ws_end; ws += ws_inc) 196 for (ws = 0; ws < ws_end; ws += ws_inc)
195 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 197 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
196 cache32_unroll32(addr|ws,Index_Invalidate_I); 198 cache32_unroll32(addr|ws, Index_Invalidate_I);
197 CACHE32_UNROLL32_ALIGN; 199 CACHE32_UNROLL32_ALIGN;
198 /* I'm in odd chunk. blast even chunks */ 200 /* I'm in odd chunk. blast even chunks */
199 for (ws = 0; ws < ws_end; ws += ws_inc) 201 for (ws = 0; ws < ws_end; ws += ws_inc)
200 for (addr = start; addr < end; addr += 0x400 * 2) 202 for (addr = start; addr < end; addr += 0x400 * 2)
201 cache32_unroll32(addr|ws,Index_Invalidate_I); 203 cache32_unroll32(addr|ws, Index_Invalidate_I);
202} 204}
203 205
204static void (* r4k_blast_icache_page)(unsigned long addr); 206static void (* r4k_blast_icache_page)(unsigned long addr);
@@ -317,23 +319,6 @@ static void __init r4k_blast_scache_setup(void)
317 r4k_blast_scache = blast_scache128; 319 r4k_blast_scache = blast_scache128;
318} 320}
319 321
320/*
321 * This is former mm's flush_cache_all() which really should be
322 * flush_cache_vunmap these days ...
323 */
324static inline void local_r4k_flush_cache_all(void * args)
325{
326 r4k_blast_dcache();
327}
328
329static void r4k_flush_cache_all(void)
330{
331 if (!cpu_has_dc_aliases)
332 return;
333
334 r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
335}
336
337static inline void local_r4k___flush_cache_all(void * args) 322static inline void local_r4k___flush_cache_all(void * args)
338{ 323{
339#if defined(CONFIG_CPU_LOONGSON2) 324#if defined(CONFIG_CPU_LOONGSON2)
@@ -343,7 +328,7 @@ static inline void local_r4k___flush_cache_all(void * args)
343 r4k_blast_dcache(); 328 r4k_blast_dcache();
344 r4k_blast_icache(); 329 r4k_blast_icache();
345 330
346 switch (current_cpu_data.cputype) { 331 switch (current_cpu_type()) {
347 case CPU_R4000SC: 332 case CPU_R4000SC:
348 case CPU_R4000MC: 333 case CPU_R4000MC:
349 case CPU_R4400SC: 334 case CPU_R4400SC:
@@ -392,10 +377,10 @@ static inline void local_r4k_flush_cache_mm(void * args)
392 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 377 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
393 * caches, so we can bail out early. 378 * caches, so we can bail out early.
394 */ 379 */
395 if (current_cpu_data.cputype == CPU_R4000SC || 380 if (current_cpu_type() == CPU_R4000SC ||
396 current_cpu_data.cputype == CPU_R4000MC || 381 current_cpu_type() == CPU_R4000MC ||
397 current_cpu_data.cputype == CPU_R4400SC || 382 current_cpu_type() == CPU_R4400SC ||
398 current_cpu_data.cputype == CPU_R4400MC) { 383 current_cpu_type() == CPU_R4400MC) {
399 r4k_blast_scache(); 384 r4k_blast_scache();
400 return; 385 return;
401 } 386 }
@@ -422,13 +407,14 @@ static inline void local_r4k_flush_cache_page(void *args)
422 struct flush_cache_page_args *fcp_args = args; 407 struct flush_cache_page_args *fcp_args = args;
423 struct vm_area_struct *vma = fcp_args->vma; 408 struct vm_area_struct *vma = fcp_args->vma;
424 unsigned long addr = fcp_args->addr; 409 unsigned long addr = fcp_args->addr;
425 unsigned long paddr = fcp_args->pfn << PAGE_SHIFT; 410 struct page *page = pfn_to_page(fcp_args->pfn);
426 int exec = vma->vm_flags & VM_EXEC; 411 int exec = vma->vm_flags & VM_EXEC;
427 struct mm_struct *mm = vma->vm_mm; 412 struct mm_struct *mm = vma->vm_mm;
428 pgd_t *pgdp; 413 pgd_t *pgdp;
429 pud_t *pudp; 414 pud_t *pudp;
430 pmd_t *pmdp; 415 pmd_t *pmdp;
431 pte_t *ptep; 416 pte_t *ptep;
417 void *vaddr;
432 418
433 /* 419 /*
434 * If ownes no valid ASID yet, cannot possibly have gotten 420 * If ownes no valid ASID yet, cannot possibly have gotten
@@ -450,43 +436,40 @@ static inline void local_r4k_flush_cache_page(void *args)
450 if (!(pte_val(*ptep) & _PAGE_PRESENT)) 436 if (!(pte_val(*ptep) & _PAGE_PRESENT))
451 return; 437 return;
452 438
453 /* 439 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
454 * Doing flushes for another ASID than the current one is 440 vaddr = NULL;
455 * too difficult since stupid R4k caches do a TLB translation 441 else {
456 * for every cache flush operation. So we do indexed flushes 442 /*
457 * in that case, which doesn't overly flush the cache too much. 443 * Use kmap_coherent or kmap_atomic to do flushes for
458 */ 444 * another ASID than the current one.
459 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { 445 */
460 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 446 if (cpu_has_dc_aliases)
461 r4k_blast_dcache_page(addr); 447 vaddr = kmap_coherent(page, addr);
462 if (exec && !cpu_icache_snoops_remote_store) 448 else
463 r4k_blast_scache_page(addr); 449 vaddr = kmap_atomic(page, KM_USER0);
464 } 450 addr = (unsigned long)vaddr;
465 if (exec)
466 r4k_blast_icache_page(addr);
467
468 return;
469 } 451 }
470 452
471 /*
472 * Do indexed flush, too much work to get the (possible) TLB refills
473 * to work correctly.
474 */
475 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 453 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
476 r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ? 454 r4k_blast_dcache_page(addr);
477 paddr : addr); 455 if (exec && !cpu_icache_snoops_remote_store)
478 if (exec && !cpu_icache_snoops_remote_store) { 456 r4k_blast_scache_page(addr);
479 r4k_blast_scache_page_indexed(paddr);
480 }
481 } 457 }
482 if (exec) { 458 if (exec) {
483 if (cpu_has_vtag_icache && mm == current->active_mm) { 459 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
484 int cpu = smp_processor_id(); 460 int cpu = smp_processor_id();
485 461
486 if (cpu_context(cpu, mm) != 0) 462 if (cpu_context(cpu, mm) != 0)
487 drop_mmu_context(mm, cpu); 463 drop_mmu_context(mm, cpu);
488 } else 464 } else
489 r4k_blast_icache_page_indexed(addr); 465 r4k_blast_icache_page(addr);
466 }
467
468 if (vaddr) {
469 if (cpu_has_dc_aliases)
470 kunmap_coherent();
471 else
472 kunmap_atomic(vaddr, KM_USER0);
490 } 473 }
491} 474}
492 475
@@ -948,12 +931,16 @@ static void __init probe_pcache(void)
948 switch (c->cputype) { 931 switch (c->cputype) {
949 case CPU_20KC: 932 case CPU_20KC:
950 case CPU_25KF: 933 case CPU_25KF:
934 case CPU_SB1:
935 case CPU_SB1A:
951 c->dcache.flags |= MIPS_CACHE_PINDEX; 936 c->dcache.flags |= MIPS_CACHE_PINDEX;
937 break;
938
952 case CPU_R10000: 939 case CPU_R10000:
953 case CPU_R12000: 940 case CPU_R12000:
954 case CPU_R14000: 941 case CPU_R14000:
955 case CPU_SB1:
956 break; 942 break;
943
957 case CPU_24K: 944 case CPU_24K:
958 case CPU_34K: 945 case CPU_34K:
959 case CPU_74K: 946 case CPU_74K:
@@ -1210,7 +1197,7 @@ static void __init coherency_setup(void)
1210 * this bit and; some wire it to zero, others like Toshiba had the 1197 * this bit and; some wire it to zero, others like Toshiba had the
1211 * silly idea of putting something else there ... 1198 * silly idea of putting something else there ...
1212 */ 1199 */
1213 switch (current_cpu_data.cputype) { 1200 switch (current_cpu_type()) {
1214 case CPU_R4000PC: 1201 case CPU_R4000PC:
1215 case CPU_R4000SC: 1202 case CPU_R4000SC:
1216 case CPU_R4000MC: 1203 case CPU_R4000MC:
@@ -1235,11 +1222,20 @@ void __init r4k_cache_init(void)
1235{ 1222{
1236 extern void build_clear_page(void); 1223 extern void build_clear_page(void);
1237 extern void build_copy_page(void); 1224 extern void build_copy_page(void);
1238 extern char except_vec2_generic; 1225 extern char __weak except_vec2_generic;
1226 extern char __weak except_vec2_sb1;
1239 struct cpuinfo_mips *c = &current_cpu_data; 1227 struct cpuinfo_mips *c = &current_cpu_data;
1240 1228
1241 /* Default cache error handler for R4000 and R5000 family */ 1229 switch (c->cputype) {
1242 set_uncached_handler (0x100, &except_vec2_generic, 0x80); 1230 case CPU_SB1:
1231 case CPU_SB1A:
1232 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1233 break;
1234
1235 default:
1236 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1237 break;
1238 }
1243 1239
1244 probe_pcache(); 1240 probe_pcache();
1245 setup_scache(); 1241 setup_scache();
@@ -1265,7 +1261,7 @@ void __init r4k_cache_init(void)
1265 PAGE_SIZE - 1); 1261 PAGE_SIZE - 1);
1266 else 1262 else
1267 shm_align_mask = PAGE_SIZE-1; 1263 shm_align_mask = PAGE_SIZE-1;
1268 flush_cache_all = r4k_flush_cache_all; 1264 flush_cache_all = cache_noop;
1269 __flush_cache_all = r4k___flush_cache_all; 1265 __flush_cache_all = r4k___flush_cache_all;
1270 flush_cache_mm = r4k_flush_cache_mm; 1266 flush_cache_mm = r4k_flush_cache_mm;
1271 flush_cache_page = r4k_flush_cache_page; 1267 flush_cache_page = r4k_flush_cache_page;
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
deleted file mode 100644
index 85ce2842d0da..000000000000
--- a/arch/mips/mm/c-sb1.c
+++ /dev/null
@@ -1,535 +0,0 @@
1/*
2 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
3 * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
4 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
5 * Copyright (C) 2004 Maciej W. Rozycki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include <linux/init.h>
22#include <linux/hardirq.h>
23
24#include <asm/asm.h>
25#include <asm/bootinfo.h>
26#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/mipsregs.h>
29#include <asm/mmu_context.h>
30#include <asm/uaccess.h>
31
32extern void sb1_dma_init(void);
33
34/* These are probed at ld_mmu time */
35static unsigned long icache_size;
36static unsigned long dcache_size;
37
38static unsigned short icache_line_size;
39static unsigned short dcache_line_size;
40
41static unsigned int icache_index_mask;
42static unsigned int dcache_index_mask;
43
44static unsigned short icache_assoc;
45static unsigned short dcache_assoc;
46
47static unsigned short icache_sets;
48static unsigned short dcache_sets;
49
50static unsigned int icache_range_cutoff;
51static unsigned int dcache_range_cutoff;
52
53static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
54 int retry, int wait)
55{
56 preempt_disable();
57 smp_call_function(func, info, retry, wait);
58 func(info);
59 preempt_enable();
60}
61
62/*
63 * The dcache is fully coherent to the system, with one
64 * big caveat: the instruction stream. In other words,
65 * if we miss in the icache, and have dirty data in the
66 * L1 dcache, then we'll go out to memory (or the L2) and
67 * get the not-as-recent data.
68 *
69 * So the only time we have to flush the dcache is when
70 * we're flushing the icache. Since the L2 is fully
71 * coherent to everything, including I/O, we never have
72 * to flush it
73 */
74
75#define cache_set_op(op, addr) \
76 __asm__ __volatile__( \
77 " .set noreorder \n" \
78 " .set mips64\n\t \n" \
79 " cache %0, (0<<13)(%1) \n" \
80 " cache %0, (1<<13)(%1) \n" \
81 " cache %0, (2<<13)(%1) \n" \
82 " cache %0, (3<<13)(%1) \n" \
83 " .set mips0 \n" \
84 " .set reorder" \
85 : \
86 : "i" (op), "r" (addr))
87
88#define sync() \
89 __asm__ __volatile( \
90 " .set mips64\n\t \n" \
91 " sync \n" \
92 " .set mips0")
93
94#define mispredict() \
95 __asm__ __volatile__( \
96 " bnezl $0, 1f \n" /* Force mispredict */ \
97 "1: \n");
98
99/*
100 * Writeback and invalidate the entire dcache
101 */
102static inline void __sb1_writeback_inv_dcache_all(void)
103{
104 unsigned long addr = 0;
105
106 while (addr < dcache_line_size * dcache_sets) {
107 cache_set_op(Index_Writeback_Inv_D, addr);
108 addr += dcache_line_size;
109 }
110}
111
112/*
113 * Writeback and invalidate a range of the dcache. The addresses are
114 * virtual, and since we're using index ops and bit 12 is part of both
115 * the virtual frame and physical index, we have to clear both sets
116 * (bit 12 set and cleared).
117 */
118static inline void __sb1_writeback_inv_dcache_range(unsigned long start,
119 unsigned long end)
120{
121 unsigned long index;
122
123 start &= ~(dcache_line_size - 1);
124 end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
125
126 while (start != end) {
127 index = start & dcache_index_mask;
128 cache_set_op(Index_Writeback_Inv_D, index);
129 cache_set_op(Index_Writeback_Inv_D, index ^ (1<<12));
130 start += dcache_line_size;
131 }
132 sync();
133}
134
135/*
136 * Writeback and invalidate a range of the dcache. With physical
137 * addresseses, we don't have to worry about possible bit 12 aliasing.
138 * XXXKW is it worth turning on KX and using hit ops with xkphys?
139 */
140static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start,
141 unsigned long end)
142{
143 start &= ~(dcache_line_size - 1);
144 end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
145
146 while (start != end) {
147 cache_set_op(Index_Writeback_Inv_D, start & dcache_index_mask);
148 start += dcache_line_size;
149 }
150 sync();
151}
152
153
154/*
155 * Invalidate the entire icache
156 */
157static inline void __sb1_flush_icache_all(void)
158{
159 unsigned long addr = 0;
160
161 while (addr < icache_line_size * icache_sets) {
162 cache_set_op(Index_Invalidate_I, addr);
163 addr += icache_line_size;
164 }
165}
166
167/*
168 * Invalidate a range of the icache. The addresses are virtual, and
169 * the cache is virtually indexed and tagged. However, we don't
170 * necessarily have the right ASID context, so use index ops instead
171 * of hit ops.
172 */
173static inline void __sb1_flush_icache_range(unsigned long start,
174 unsigned long end)
175{
176 start &= ~(icache_line_size - 1);
177 end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
178
179 while (start != end) {
180 cache_set_op(Index_Invalidate_I, start & icache_index_mask);
181 start += icache_line_size;
182 }
183 mispredict();
184 sync();
185}
186
187/*
188 * Flush the icache for a given physical page. Need to writeback the
189 * dcache first, then invalidate the icache. If the page isn't
190 * executable, nothing is required.
191 */
192static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
193{
194 int cpu = smp_processor_id();
195
196#ifndef CONFIG_SMP
197 if (!(vma->vm_flags & VM_EXEC))
198 return;
199#endif
200
201 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
202
203 /*
204 * Bumping the ASID is probably cheaper than the flush ...
205 */
206 if (vma->vm_mm == current->active_mm) {
207 if (cpu_context(cpu, vma->vm_mm) != 0)
208 drop_mmu_context(vma->vm_mm, cpu);
209 } else
210 __sb1_flush_icache_range(addr, addr + PAGE_SIZE);
211}
212
213#ifdef CONFIG_SMP
214struct flush_cache_page_args {
215 struct vm_area_struct *vma;
216 unsigned long addr;
217 unsigned long pfn;
218};
219
220static void sb1_flush_cache_page_ipi(void *info)
221{
222 struct flush_cache_page_args *args = info;
223
224 local_sb1_flush_cache_page(args->vma, args->addr, args->pfn);
225}
226
227/* Dirty dcache could be on another CPU, so do the IPIs */
228static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
229{
230 struct flush_cache_page_args args;
231
232 if (!(vma->vm_flags & VM_EXEC))
233 return;
234
235 addr &= PAGE_MASK;
236 args.vma = vma;
237 args.addr = addr;
238 args.pfn = pfn;
239 sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
240}
241#else
242void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
243 __attribute__((alias("local_sb1_flush_cache_page")));
244#endif
245
246#ifdef CONFIG_SMP
247static void sb1_flush_cache_data_page_ipi(void *info)
248{
249 unsigned long start = (unsigned long)info;
250
251 __sb1_writeback_inv_dcache_range(start, start + PAGE_SIZE);
252}
253
254static void sb1_flush_cache_data_page(unsigned long addr)
255{
256 if (in_atomic())
257 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
258 else
259 on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1);
260}
261#else
262
263static void local_sb1_flush_cache_data_page(unsigned long addr)
264{
265 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
266}
267
268void sb1_flush_cache_data_page(unsigned long)
269 __attribute__((alias("local_sb1_flush_cache_data_page")));
270#endif
271
272/*
273 * Invalidate all caches on this CPU
274 */
275static void __used local_sb1___flush_cache_all(void)
276{
277 __sb1_writeback_inv_dcache_all();
278 __sb1_flush_icache_all();
279}
280
281#ifdef CONFIG_SMP
282void sb1___flush_cache_all_ipi(void *ignored)
283 __attribute__((alias("local_sb1___flush_cache_all")));
284
285static void sb1___flush_cache_all(void)
286{
287 sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
288}
289#else
290void sb1___flush_cache_all(void)
291 __attribute__((alias("local_sb1___flush_cache_all")));
292#endif
293
294/*
295 * When flushing a range in the icache, we have to first writeback
296 * the dcache for the same range, so new ifetches will see any
297 * data that was dirty in the dcache.
298 *
299 * The start/end arguments are Kseg addresses (possibly mapped Kseg).
300 */
301
302static void local_sb1_flush_icache_range(unsigned long start,
303 unsigned long end)
304{
305 /* Just wb-inv the whole dcache if the range is big enough */
306 if ((end - start) > dcache_range_cutoff)
307 __sb1_writeback_inv_dcache_all();
308 else
309 __sb1_writeback_inv_dcache_range(start, end);
310
311 /* Just flush the whole icache if the range is big enough */
312 if ((end - start) > icache_range_cutoff)
313 __sb1_flush_icache_all();
314 else
315 __sb1_flush_icache_range(start, end);
316}
317
318#ifdef CONFIG_SMP
319struct flush_icache_range_args {
320 unsigned long start;
321 unsigned long end;
322};
323
324static void sb1_flush_icache_range_ipi(void *info)
325{
326 struct flush_icache_range_args *args = info;
327
328 local_sb1_flush_icache_range(args->start, args->end);
329}
330
331void sb1_flush_icache_range(unsigned long start, unsigned long end)
332{
333 struct flush_icache_range_args args;
334
335 args.start = start;
336 args.end = end;
337 sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
338}
339#else
340void sb1_flush_icache_range(unsigned long start, unsigned long end)
341 __attribute__((alias("local_sb1_flush_icache_range")));
342#endif
343
344/*
345 * A signal trampoline must fit into a single cacheline.
346 */
347static void local_sb1_flush_cache_sigtramp(unsigned long addr)
348{
349 cache_set_op(Index_Writeback_Inv_D, addr & dcache_index_mask);
350 cache_set_op(Index_Writeback_Inv_D, (addr ^ (1<<12)) & dcache_index_mask);
351 cache_set_op(Index_Invalidate_I, addr & icache_index_mask);
352 mispredict();
353}
354
355#ifdef CONFIG_SMP
356static void sb1_flush_cache_sigtramp_ipi(void *info)
357{
358 unsigned long iaddr = (unsigned long) info;
359 local_sb1_flush_cache_sigtramp(iaddr);
360}
361
362static void sb1_flush_cache_sigtramp(unsigned long addr)
363{
364 sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
365}
366#else
367void sb1_flush_cache_sigtramp(unsigned long addr)
368 __attribute__((alias("local_sb1_flush_cache_sigtramp")));
369#endif
370
371
372/*
373 * Anything that just flushes dcache state can be ignored, as we're always
374 * coherent in dcache space. This is just a dummy function that all the
375 * nop'ed routines point to
376 */
377static void sb1_nop(void)
378{
379}
380
381/*
382 * Cache set values (from the mips64 spec)
383 * 0 - 64
384 * 1 - 128
385 * 2 - 256
386 * 3 - 512
387 * 4 - 1024
388 * 5 - 2048
389 * 6 - 4096
390 * 7 - Reserved
391 */
392
393static unsigned int decode_cache_sets(unsigned int config_field)
394{
395 if (config_field == 7) {
396 /* JDCXXX - Find a graceful way to abort. */
397 return 0;
398 }
399 return (1<<(config_field + 6));
400}
401
402/*
403 * Cache line size values (from the mips64 spec)
404 * 0 - No cache present.
405 * 1 - 4 bytes
406 * 2 - 8 bytes
407 * 3 - 16 bytes
408 * 4 - 32 bytes
409 * 5 - 64 bytes
410 * 6 - 128 bytes
411 * 7 - Reserved
412 */
413
414static unsigned int decode_cache_line_size(unsigned int config_field)
415{
416 if (config_field == 0) {
417 return 0;
418 } else if (config_field == 7) {
419 /* JDCXXX - Find a graceful way to abort. */
420 return 0;
421 }
422 return (1<<(config_field + 1));
423}
424
425/*
426 * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs)
427 *
428 * 24:22 Icache sets per way
429 * 21:19 Icache line size
430 * 18:16 Icache Associativity
431 * 15:13 Dcache sets per way
432 * 12:10 Dcache line size
433 * 9:7 Dcache Associativity
434 */
435
436static char *way_string[] = {
437 "direct mapped", "2-way", "3-way", "4-way",
438 "5-way", "6-way", "7-way", "8-way",
439};
440
441static __init void probe_cache_sizes(void)
442{
443 u32 config1;
444
445 config1 = read_c0_config1();
446 icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7);
447 dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7);
448 icache_sets = decode_cache_sets((config1 >> 22) & 0x7);
449 dcache_sets = decode_cache_sets((config1 >> 13) & 0x7);
450 icache_assoc = ((config1 >> 16) & 0x7) + 1;
451 dcache_assoc = ((config1 >> 7) & 0x7) + 1;
452 icache_size = icache_line_size * icache_sets * icache_assoc;
453 dcache_size = dcache_line_size * dcache_sets * dcache_assoc;
454 /* Need to remove non-index bits for index ops */
455 icache_index_mask = (icache_sets - 1) * icache_line_size;
456 dcache_index_mask = (dcache_sets - 1) * dcache_line_size;
457 /*
458 * These are for choosing range (index ops) versus all.
459 * icache flushes all ways for each set, so drop icache_assoc.
460 * dcache flushes all ways and each setting of bit 12 for each
461 * index, so drop dcache_assoc and halve the dcache_sets.
462 */
463 icache_range_cutoff = icache_sets * icache_line_size;
464 dcache_range_cutoff = (dcache_sets / 2) * icache_line_size;
465
466 printk("Primary instruction cache %ldkB, %s, linesize %d bytes.\n",
467 icache_size >> 10, way_string[icache_assoc - 1],
468 icache_line_size);
469 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
470 dcache_size >> 10, way_string[dcache_assoc - 1],
471 dcache_line_size);
472}
473
474/*
475 * This is called from cache.c. We have to set up all the
476 * memory management function pointers, as well as initialize
477 * the caches and tlbs
478 */
479void __init sb1_cache_init(void)
480{
481 extern char except_vec2_sb1;
482
483 /* Special cache error handler for SB1 */
484 set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
485
486 probe_cache_sizes();
487
488#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
489 sb1_dma_init();
490#endif
491
492 /*
493 * None of these are needed for the SB1 - the Dcache is
494 * physically indexed and tagged, so no virtual aliasing can
495 * occur
496 */
497 flush_cache_range = (void *) sb1_nop;
498 flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop;
499 flush_cache_all = sb1_nop;
500
501 /* These routines are for Icache coherence with the Dcache */
502 flush_icache_range = sb1_flush_icache_range;
503 flush_icache_all = __sb1_flush_icache_all; /* local only */
504
505 /* This implies an Icache flush too, so can't be nop'ed */
506 flush_cache_page = sb1_flush_cache_page;
507
508 flush_cache_sigtramp = sb1_flush_cache_sigtramp;
509 local_flush_data_cache_page = (void *) sb1_nop;
510 flush_data_cache_page = sb1_flush_cache_data_page;
511
512 /* Full flush */
513 __flush_cache_all = sb1___flush_cache_all;
514
515 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
516
517 /*
518 * This is the only way to force the update of K0 to complete
519 * before subsequent instruction fetch.
520 */
521 __asm__ __volatile__(
522 ".set push \n"
523 " .set noat \n"
524 " .set noreorder \n"
525 " .set mips3 \n"
526 " " STR(PTR_LA) " $1, 1f \n"
527 " " STR(MTC0) " $1, $14 \n"
528 " eret \n"
529 "1: .set pop"
530 :
531 :
532 : "memory");
533
534 local_sb1___flush_cache_all();
535}
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 560a6de96556..9ea121e8cdce 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -69,7 +69,7 @@ static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
69/* TX39H2,TX39H3 */ 69/* TX39H2,TX39H3 */
70static inline void tx39_blast_dcache_page(unsigned long addr) 70static inline void tx39_blast_dcache_page(unsigned long addr)
71{ 71{
72 if (current_cpu_data.cputype != CPU_TX3912) 72 if (current_cpu_type() != CPU_TX3912)
73 blast_dcache16_page(addr); 73 blast_dcache16_page(addr);
74} 74}
75 75
@@ -307,7 +307,7 @@ static __init void tx39_probe_cache(void)
307 TX39_CONF_DCS_SHIFT)); 307 TX39_CONF_DCS_SHIFT));
308 308
309 current_cpu_data.icache.linesz = 16; 309 current_cpu_data.icache.linesz = 16;
310 switch (current_cpu_data.cputype) { 310 switch (current_cpu_type()) {
311 case CPU_TX3912: 311 case CPU_TX3912:
312 current_cpu_data.icache.ways = 1; 312 current_cpu_data.icache.ways = 1;
313 current_cpu_data.dcache.ways = 1; 313 current_cpu_data.dcache.ways = 1;
@@ -341,7 +341,7 @@ void __init tx39_cache_init(void)
341 341
342 tx39_probe_cache(); 342 tx39_probe_cache();
343 343
344 switch (current_cpu_data.cputype) { 344 switch (current_cpu_type()) {
345 case CPU_TX3912: 345 case CPU_TX3912:
346 /* TX39/H core (writethru direct-map cache) */ 346 /* TX39/H core (writethru direct-map cache) */
347 flush_cache_all = tx39h_flush_icache_all; 347 flush_cache_all = tx39h_flush_icache_all;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 81f925a9a731..43dde874f414 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -3,13 +3,14 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 MIPS Technologies, Inc. 7 * Copyright (C) 2007 MIPS Technologies, Inc.
8 */ 8 */
9#include <linux/fs.h> 9#include <linux/fs.h>
10#include <linux/fcntl.h> 10#include <linux/fcntl.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/linkage.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/sched.h> 15#include <linux/sched.h>
15#include <linux/mm.h> 16#include <linux/mm.h>
@@ -157,12 +158,6 @@ void __init cpu_cache_init(void)
157 tx39_cache_init(); 158 tx39_cache_init();
158 return; 159 return;
159 } 160 }
160 if (cpu_has_sb1_cache) {
161 extern void __weak sb1_cache_init(void);
162
163 sb1_cache_init();
164 return;
165 }
166 161
167 panic(cache_panic); 162 panic(cache_panic);
168} 163}
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 4c72e650f9b6..e7f539e3284b 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -271,14 +271,22 @@ asmlinkage void sb1_cache_error(void)
271 271
272/* Parity lookup table. */ 272/* Parity lookup table. */
273static const uint8_t parity[256] = { 273static const uint8_t parity[256] = {
274 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 274 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
275 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 275 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
276 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 276 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
277 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 277 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
278 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 278 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
279 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 279 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
280 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 280 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
281 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 281 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
282 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
283 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
284 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
285 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
286 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
287 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
288 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
289 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
282}; 290};
283 291
284/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ 292/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f60b3dc0fc62..98b5e5bac02e 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -35,8 +35,8 @@ static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)
35static inline int cpu_is_noncoherent_r10000(struct device *dev) 35static inline int cpu_is_noncoherent_r10000(struct device *dev)
36{ 36{
37 return !plat_device_is_coherent(dev) && 37 return !plat_device_is_coherent(dev) &&
38 (current_cpu_data.cputype == CPU_R10000 || 38 (current_cpu_type() == CPU_R10000 ||
39 current_cpu_data.cputype == CPU_R12000); 39 current_cpu_type() == CPU_R12000);
40} 40}
41 41
42void *dma_alloc_noncoherent(struct device *dev, size_t size, 42void *dma_alloc_noncoherent(struct device *dev, size_t size,
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index e47e9e9486bf..4f770ac885ce 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -347,13 +347,14 @@ void __init build_clear_page(void)
347{ 347{
348 unsigned int loop_start; 348 unsigned int loop_start;
349 unsigned long off; 349 unsigned long off;
350 int i;
350 351
351 epc = (unsigned int *) &clear_page_array; 352 epc = (unsigned int *) &clear_page_array;
352 instruction_pending = 0; 353 instruction_pending = 0;
353 store_offset = 0; 354 store_offset = 0;
354 355
355 if (cpu_has_prefetch) { 356 if (cpu_has_prefetch) {
356 switch (current_cpu_data.cputype) { 357 switch (current_cpu_type()) {
357 case CPU_TX49XX: 358 case CPU_TX49XX:
358 /* TX49 supports only Pref_Load */ 359 /* TX49 supports only Pref_Load */
359 pref_offset_clear = 0; 360 pref_offset_clear = 0;
@@ -434,12 +435,22 @@ dest = label();
434 build_jr_ra(); 435 build_jr_ra();
435 436
436 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); 437 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
438
439 pr_info("Synthesized clear page handler (%u instructions).\n",
440 (unsigned int)(epc - clear_page_array));
441
442 pr_debug("\t.set push\n");
443 pr_debug("\t.set noreorder\n");
444 for (i = 0; i < (epc - clear_page_array); i++)
445 pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
446 pr_debug("\t.set pop\n");
437} 447}
438 448
439void __init build_copy_page(void) 449void __init build_copy_page(void)
440{ 450{
441 unsigned int loop_start; 451 unsigned int loop_start;
442 unsigned long off; 452 unsigned long off;
453 int i;
443 454
444 epc = (unsigned int *) &copy_page_array; 455 epc = (unsigned int *) &copy_page_array;
445 store_offset = load_offset = 0; 456 store_offset = load_offset = 0;
@@ -515,4 +526,13 @@ dest = label();
515 build_jr_ra(); 526 build_jr_ra();
516 527
517 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); 528 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
529
530 pr_info("Synthesized copy page handler (%u instructions).\n",
531 (unsigned int)(epc - copy_page_array));
532
533 pr_debug("\t.set push\n");
534 pr_debug("\t.set noreorder\n");
535 for (i = 0; i < (epc - copy_page_array); i++)
536 pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
537 pr_debug("\t.set pop\n");
518} 538}
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index adb37d0a30ea..a3e98c243a89 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -188,9 +188,9 @@ static inline void copy_page_cpu(void *to, void *from)
188 : "+r" (src), "+r" (dst) 188 : "+r" (src), "+r" (dst)
189 : "r" (end) 189 : "r" (end)
190#ifdef CONFIG_64BIT 190#ifdef CONFIG_64BIT
191 : "$8","$9","$10","$11","memory"); 191 : "$8", "$9", "$10", "$11", "memory");
192#else 192#else
193 : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); 193 : "$2", "$3", "$6", "$7", "$8", "$9", "$10", "$11", "memory");
194#endif 194#endif
195} 195}
196 196
@@ -292,3 +292,11 @@ void copy_page(void *to, void *from)
292 292
293EXPORT_SYMBOL(clear_page); 293EXPORT_SYMBOL(clear_page);
294EXPORT_SYMBOL(copy_page); 294EXPORT_SYMBOL(copy_page);
295
296void __init build_clear_page(void)
297{
298}
299
300void __init build_copy_page(void)
301{
302}
diff --git a/arch/mips/mm/pgtable.c b/arch/mips/mm/pgtable.c
index c93aa6cbcaca..57df1c38e303 100644
--- a/arch/mips/mm/pgtable.c
+++ b/arch/mips/mm/pgtable.c
@@ -29,9 +29,9 @@ void show_mem(void)
29 shared += page_count(page) - 1; 29 shared += page_count(page) - 1;
30 } 30 }
31 printk("%d pages of RAM\n", total); 31 printk("%d pages of RAM\n", total);
32 printk("%d pages of HIGHMEM\n",highmem); 32 printk("%d pages of HIGHMEM\n", highmem);
33 printk("%d reserved pages\n",reserved); 33 printk("%d reserved pages\n", reserved);
34 printk("%d pages shared\n",shared); 34 printk("%d pages shared\n", shared);
35 printk("%d pages swap cached\n",cached); 35 printk("%d pages swap cached\n", cached);
36#endif 36#endif
37} 37}
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 42b50964c644..c13170bc675c 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -102,7 +102,7 @@ static inline int __init mips_sc_probe(void)
102 102
103int __init mips_sc_init(void) 103int __init mips_sc_init(void)
104{ 104{
105 int found = mips_sc_probe (); 105 int found = mips_sc_probe();
106 if (found) { 106 if (found) {
107 mips_sc_enable(); 107 mips_sc_enable();
108 bcops = &mips_sc_ops; 108 bcops = &mips_sc_ops;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index dcd6913dc1ff..74ae0348cc92 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -491,7 +491,7 @@ void __init tlb_init(void)
491 int wired = current_cpu_data.tlbsize - ntlb; 491 int wired = current_cpu_data.tlbsize - ntlb;
492 write_c0_wired(wired); 492 write_c0_wired(wired);
493 write_c0_index(wired-1); 493 write_c0_index(wired-1);
494 printk ("Restricting TLB to %d entries\n", ntlb); 494 printk("Restricting TLB to %d entries\n", ntlb);
495 } else 495 } else
496 printk("Ignoring invalid argument ntlb=%d\n", ntlb); 496 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
497 } 497 }
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 266a47d65eed..bd8409d8ff62 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -56,7 +56,7 @@ void local_flush_tlb_mm(struct mm_struct *mm)
56 int cpu = smp_processor_id(); 56 int cpu = smp_processor_id();
57 57
58 if (cpu_context(cpu, mm) != 0) 58 if (cpu_context(cpu, mm) != 0)
59 drop_mmu_context(mm,cpu); 59 drop_mmu_context(mm, cpu);
60} 60}
61 61
62void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 62void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6c425b052442..01b0961acfb6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -35,24 +35,24 @@
35#include <asm/smp.h> 35#include <asm/smp.h>
36#include <asm/war.h> 36#include <asm/war.h>
37 37
38static __init int __maybe_unused r45k_bvahwbug(void) 38static inline int r45k_bvahwbug(void)
39{ 39{
40 /* XXX: We should probe for the presence of this bug, but we don't. */ 40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0; 41 return 0;
42} 42}
43 43
44static __init int __maybe_unused r4k_250MHZhwbug(void) 44static inline int r4k_250MHZhwbug(void)
45{ 45{
46 /* XXX: We should probe for the presence of this bug, but we don't. */ 46 /* XXX: We should probe for the presence of this bug, but we don't. */
47 return 0; 47 return 0;
48} 48}
49 49
50static __init int __maybe_unused bcm1250_m3_war(void) 50static inline int __maybe_unused bcm1250_m3_war(void)
51{ 51{
52 return BCM1250_M3_WAR; 52 return BCM1250_M3_WAR;
53} 53}
54 54
55static __init int __maybe_unused r10000_llsc_war(void) 55static inline int __maybe_unused r10000_llsc_war(void)
56{ 56{
57 return R10000_LLSC_WAR; 57 return R10000_LLSC_WAR;
58} 58}
@@ -66,7 +66,7 @@ static __init int __maybe_unused r10000_llsc_war(void)
66 * why; it's not an issue caused by the core RTL. 66 * why; it's not an issue caused by the core RTL.
67 * 67 *
68 */ 68 */
69static __init int __attribute__((unused)) m4kc_tlbp_war(void) 69static int __init m4kc_tlbp_war(void)
70{ 70{
71 return (current_cpu_data.processor_id & 0xffff00) == 71 return (current_cpu_data.processor_id & 0xffff00) ==
72 (PRID_COMP_MIPS | PRID_IMP_4KC); 72 (PRID_COMP_MIPS | PRID_IMP_4KC);
@@ -140,60 +140,60 @@ struct insn {
140 | (e) << RE_SH \ 140 | (e) << RE_SH \
141 | (f) << FUNC_SH) 141 | (f) << FUNC_SH)
142 142
143static __initdata struct insn insn_table[] = { 143static struct insn insn_table[] __initdata = {
144 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
145 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 145 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
146 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 146 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
147 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 147 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
148 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 148 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
149 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 149 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
150 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 150 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
151 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 151 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
152 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 152 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
153 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 153 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
154 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 154 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
155 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 155 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
156 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 156 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
157 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, 157 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
158 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, 158 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
159 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 159 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
160 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 160 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
161 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 161 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
162 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 162 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
163 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, 163 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
164 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 164 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
165 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 165 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
166 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 166 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
167 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 167 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
168 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 168 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
169 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 169 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
170 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 170 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
171 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 171 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
172 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 172 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
173 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 173 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
174 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, 174 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
175 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, 175 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
176 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 176 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
177 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 177 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
178 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 178 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
179 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 179 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
180 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 180 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
181 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 181 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
182 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 182 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
183 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 183 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
184 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 184 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
185 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 185 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
186 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 186 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
187 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 187 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
188 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 188 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
189 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 189 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
190 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 190 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
191 { insn_invalid, 0, 0 } 191 { insn_invalid, 0, 0 }
192}; 192};
193 193
194#undef M 194#undef M
195 195
196static __init u32 build_rs(u32 arg) 196static u32 __init build_rs(u32 arg)
197{ 197{
198 if (arg & ~RS_MASK) 198 if (arg & ~RS_MASK)
199 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 199 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -201,7 +201,7 @@ static __init u32 build_rs(u32 arg)
201 return (arg & RS_MASK) << RS_SH; 201 return (arg & RS_MASK) << RS_SH;
202} 202}
203 203
204static __init u32 build_rt(u32 arg) 204static u32 __init build_rt(u32 arg)
205{ 205{
206 if (arg & ~RT_MASK) 206 if (arg & ~RT_MASK)
207 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 207 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -209,7 +209,7 @@ static __init u32 build_rt(u32 arg)
209 return (arg & RT_MASK) << RT_SH; 209 return (arg & RT_MASK) << RT_SH;
210} 210}
211 211
212static __init u32 build_rd(u32 arg) 212static u32 __init build_rd(u32 arg)
213{ 213{
214 if (arg & ~RD_MASK) 214 if (arg & ~RD_MASK)
215 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 215 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -217,7 +217,7 @@ static __init u32 build_rd(u32 arg)
217 return (arg & RD_MASK) << RD_SH; 217 return (arg & RD_MASK) << RD_SH;
218} 218}
219 219
220static __init u32 build_re(u32 arg) 220static u32 __init build_re(u32 arg)
221{ 221{
222 if (arg & ~RE_MASK) 222 if (arg & ~RE_MASK)
223 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 223 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -225,7 +225,7 @@ static __init u32 build_re(u32 arg)
225 return (arg & RE_MASK) << RE_SH; 225 return (arg & RE_MASK) << RE_SH;
226} 226}
227 227
228static __init u32 build_simm(s32 arg) 228static u32 __init build_simm(s32 arg)
229{ 229{
230 if (arg > 0x7fff || arg < -0x8000) 230 if (arg > 0x7fff || arg < -0x8000)
231 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 231 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -233,7 +233,7 @@ static __init u32 build_simm(s32 arg)
233 return arg & 0xffff; 233 return arg & 0xffff;
234} 234}
235 235
236static __init u32 build_uimm(u32 arg) 236static u32 __init build_uimm(u32 arg)
237{ 237{
238 if (arg & ~IMM_MASK) 238 if (arg & ~IMM_MASK)
239 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 239 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -241,7 +241,7 @@ static __init u32 build_uimm(u32 arg)
241 return arg & IMM_MASK; 241 return arg & IMM_MASK;
242} 242}
243 243
244static __init u32 build_bimm(s32 arg) 244static u32 __init build_bimm(s32 arg)
245{ 245{
246 if (arg > 0x1ffff || arg < -0x20000) 246 if (arg > 0x1ffff || arg < -0x20000)
247 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 247 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -252,7 +252,7 @@ static __init u32 build_bimm(s32 arg)
252 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 252 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
253} 253}
254 254
255static __init u32 build_jimm(u32 arg) 255static u32 __init build_jimm(u32 arg)
256{ 256{
257 if (arg & ~((JIMM_MASK) << 2)) 257 if (arg & ~((JIMM_MASK) << 2))
258 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 258 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -260,7 +260,7 @@ static __init u32 build_jimm(u32 arg)
260 return (arg >> 2) & JIMM_MASK; 260 return (arg >> 2) & JIMM_MASK;
261} 261}
262 262
263static __init u32 build_func(u32 arg) 263static u32 __init build_func(u32 arg)
264{ 264{
265 if (arg & ~FUNC_MASK) 265 if (arg & ~FUNC_MASK)
266 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 266 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -268,7 +268,7 @@ static __init u32 build_func(u32 arg)
268 return arg & FUNC_MASK; 268 return arg & FUNC_MASK;
269} 269}
270 270
271static __init u32 build_set(u32 arg) 271static u32 __init build_set(u32 arg)
272{ 272{
273 if (arg & ~SET_MASK) 273 if (arg & ~SET_MASK)
274 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 274 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -315,69 +315,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...)
315} 315}
316 316
317#define I_u1u2u3(op) \ 317#define I_u1u2u3(op) \
318 static inline void __init i##op(u32 **buf, unsigned int a, \ 318 static inline void i##op(u32 **buf, unsigned int a, \
319 unsigned int b, unsigned int c) \ 319 unsigned int b, unsigned int c) \
320 { \ 320 { \
321 build_insn(buf, insn##op, a, b, c); \ 321 build_insn(buf, insn##op, a, b, c); \
322 } 322 }
323 323
324#define I_u2u1u3(op) \ 324#define I_u2u1u3(op) \
325 static inline void __init i##op(u32 **buf, unsigned int a, \ 325 static inline void i##op(u32 **buf, unsigned int a, \
326 unsigned int b, unsigned int c) \ 326 unsigned int b, unsigned int c) \
327 { \ 327 { \
328 build_insn(buf, insn##op, b, a, c); \ 328 build_insn(buf, insn##op, b, a, c); \
329 } 329 }
330 330
331#define I_u3u1u2(op) \ 331#define I_u3u1u2(op) \
332 static inline void __init i##op(u32 **buf, unsigned int a, \ 332 static inline void i##op(u32 **buf, unsigned int a, \
333 unsigned int b, unsigned int c) \ 333 unsigned int b, unsigned int c) \
334 { \ 334 { \
335 build_insn(buf, insn##op, b, c, a); \ 335 build_insn(buf, insn##op, b, c, a); \
336 } 336 }
337 337
338#define I_u1u2s3(op) \ 338#define I_u1u2s3(op) \
339 static inline void __init i##op(u32 **buf, unsigned int a, \ 339 static inline void i##op(u32 **buf, unsigned int a, \
340 unsigned int b, signed int c) \ 340 unsigned int b, signed int c) \
341 { \ 341 { \
342 build_insn(buf, insn##op, a, b, c); \ 342 build_insn(buf, insn##op, a, b, c); \
343 } 343 }
344 344
345#define I_u2s3u1(op) \ 345#define I_u2s3u1(op) \
346 static inline void __init i##op(u32 **buf, unsigned int a, \ 346 static inline void i##op(u32 **buf, unsigned int a, \
347 signed int b, unsigned int c) \ 347 signed int b, unsigned int c) \
348 { \ 348 { \
349 build_insn(buf, insn##op, c, a, b); \ 349 build_insn(buf, insn##op, c, a, b); \
350 } 350 }
351 351
352#define I_u2u1s3(op) \ 352#define I_u2u1s3(op) \
353 static inline void __init i##op(u32 **buf, unsigned int a, \ 353 static inline void i##op(u32 **buf, unsigned int a, \
354 unsigned int b, signed int c) \ 354 unsigned int b, signed int c) \
355 { \ 355 { \
356 build_insn(buf, insn##op, b, a, c); \ 356 build_insn(buf, insn##op, b, a, c); \
357 } 357 }
358 358
359#define I_u1u2(op) \ 359#define I_u1u2(op) \
360 static inline void __init i##op(u32 **buf, unsigned int a, \ 360 static inline void i##op(u32 **buf, unsigned int a, \
361 unsigned int b) \ 361 unsigned int b) \
362 { \ 362 { \
363 build_insn(buf, insn##op, a, b); \ 363 build_insn(buf, insn##op, a, b); \
364 } 364 }
365 365
366#define I_u1s2(op) \ 366#define I_u1s2(op) \
367 static inline void __init i##op(u32 **buf, unsigned int a, \ 367 static inline void i##op(u32 **buf, unsigned int a, \
368 signed int b) \ 368 signed int b) \
369 { \ 369 { \
370 build_insn(buf, insn##op, a, b); \ 370 build_insn(buf, insn##op, a, b); \
371 } 371 }
372 372
373#define I_u1(op) \ 373#define I_u1(op) \
374 static inline void __init i##op(u32 **buf, unsigned int a) \ 374 static inline void i##op(u32 **buf, unsigned int a) \
375 { \ 375 { \
376 build_insn(buf, insn##op, a); \ 376 build_insn(buf, insn##op, a); \
377 } 377 }
378 378
379#define I_0(op) \ 379#define I_0(op) \
380 static inline void __init i##op(u32 **buf) \ 380 static inline void i##op(u32 **buf) \
381 { \ 381 { \
382 build_insn(buf, insn##op); \ 382 build_insn(buf, insn##op); \
383 } 383 }
@@ -457,7 +457,7 @@ struct label {
457 enum label_id lab; 457 enum label_id lab;
458}; 458};
459 459
460static __init void build_label(struct label **lab, u32 *addr, 460static void __init build_label(struct label **lab, u32 *addr,
461 enum label_id l) 461 enum label_id l)
462{ 462{
463 (*lab)->addr = addr; 463 (*lab)->addr = addr;
@@ -526,34 +526,34 @@ L_LA(_r3000_write_probe_fail)
526#define i_ehb(buf) i_sll(buf, 0, 0, 3) 526#define i_ehb(buf) i_sll(buf, 0, 0, 3)
527 527
528#ifdef CONFIG_64BIT 528#ifdef CONFIG_64BIT
529static __init int __maybe_unused in_compat_space_p(long addr) 529static int __init __maybe_unused in_compat_space_p(long addr)
530{ 530{
531 /* Is this address in 32bit compat space? */ 531 /* Is this address in 32bit compat space? */
532 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 532 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
533} 533}
534 534
535static __init int __maybe_unused rel_highest(long val) 535static int __init __maybe_unused rel_highest(long val)
536{ 536{
537 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 537 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
538} 538}
539 539
540static __init int __maybe_unused rel_higher(long val) 540static int __init __maybe_unused rel_higher(long val)
541{ 541{
542 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 542 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
543} 543}
544#endif 544#endif
545 545
546static __init int rel_hi(long val) 546static int __init rel_hi(long val)
547{ 547{
548 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 548 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
549} 549}
550 550
551static __init int rel_lo(long val) 551static int __init rel_lo(long val)
552{ 552{
553 return ((val & 0xffff) ^ 0x8000) - 0x8000; 553 return ((val & 0xffff) ^ 0x8000) - 0x8000;
554} 554}
555 555
556static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 556static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr)
557{ 557{
558#ifdef CONFIG_64BIT 558#ifdef CONFIG_64BIT
559 if (!in_compat_space_p(addr)) { 559 if (!in_compat_space_p(addr)) {
@@ -571,7 +571,7 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
571 i_lui(buf, rs, rel_hi(addr)); 571 i_lui(buf, rs, rel_hi(addr));
572} 572}
573 573
574static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, 574static void __init __maybe_unused i_LA(u32 **buf, unsigned int rs,
575 long addr) 575 long addr)
576{ 576{
577 i_LA_mostly(buf, rs, addr); 577 i_LA_mostly(buf, rs, addr);
@@ -589,7 +589,7 @@ struct reloc {
589 enum label_id lab; 589 enum label_id lab;
590}; 590};
591 591
592static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 592static void __init r_mips_pc16(struct reloc **rel, u32 *addr,
593 enum label_id l) 593 enum label_id l)
594{ 594{
595 (*rel)->addr = addr; 595 (*rel)->addr = addr;
@@ -614,7 +614,7 @@ static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
614 } 614 }
615} 615}
616 616
617static __init void resolve_relocs(struct reloc *rel, struct label *lab) 617static void __init resolve_relocs(struct reloc *rel, struct label *lab)
618{ 618{
619 struct label *l; 619 struct label *l;
620 620
@@ -624,7 +624,7 @@ static __init void resolve_relocs(struct reloc *rel, struct label *lab)
624 __resolve_relocs(rel, l); 624 __resolve_relocs(rel, l);
625} 625}
626 626
627static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 627static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end,
628 long off) 628 long off)
629{ 629{
630 for (; rel->lab != label_invalid; rel++) 630 for (; rel->lab != label_invalid; rel++)
@@ -632,7 +632,7 @@ static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
632 rel->addr += off; 632 rel->addr += off;
633} 633}
634 634
635static __init void move_labels(struct label *lab, u32 *first, u32 *end, 635static void __init move_labels(struct label *lab, u32 *first, u32 *end,
636 long off) 636 long off)
637{ 637{
638 for (; lab->lab != label_invalid; lab++) 638 for (; lab->lab != label_invalid; lab++)
@@ -640,7 +640,7 @@ static __init void move_labels(struct label *lab, u32 *first, u32 *end,
640 lab->addr += off; 640 lab->addr += off;
641} 641}
642 642
643static __init void copy_handler(struct reloc *rel, struct label *lab, 643static void __init copy_handler(struct reloc *rel, struct label *lab,
644 u32 *first, u32 *end, u32 *target) 644 u32 *first, u32 *end, u32 *target)
645{ 645{
646 long off = (long)(target - first); 646 long off = (long)(target - first);
@@ -651,7 +651,7 @@ static __init void copy_handler(struct reloc *rel, struct label *lab,
651 move_labels(lab, first, end, off); 651 move_labels(lab, first, end, off);
652} 652}
653 653
654static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, 654static int __init __maybe_unused insn_has_bdelay(struct reloc *rel,
655 u32 *addr) 655 u32 *addr)
656{ 656{
657 for (; rel->lab != label_invalid; rel++) { 657 for (; rel->lab != label_invalid; rel++) {
@@ -743,11 +743,11 @@ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
743 * We deliberately chose a buffer size of 128, so we won't scribble 743 * We deliberately chose a buffer size of 128, so we won't scribble
744 * over anything important on overflow before we panic. 744 * over anything important on overflow before we panic.
745 */ 745 */
746static __initdata u32 tlb_handler[128]; 746static u32 tlb_handler[128] __initdata;
747 747
748/* simply assume worst case size for labels and relocs */ 748/* simply assume worst case size for labels and relocs */
749static __initdata struct label labels[128]; 749static struct label labels[128] __initdata;
750static __initdata struct reloc relocs[128]; 750static struct reloc relocs[128] __initdata;
751 751
752/* 752/*
753 * The R3000 TLB handler is simple. 753 * The R3000 TLB handler is simple.
@@ -801,7 +801,7 @@ static void __init build_r3000_tlb_refill_handler(void)
801 * other one.To keep things simple, we first assume linear space, 801 * other one.To keep things simple, we first assume linear space,
802 * then we relocate it to the final handler layout as needed. 802 * then we relocate it to the final handler layout as needed.
803 */ 803 */
804static __initdata u32 final_handler[64]; 804static u32 final_handler[64] __initdata;
805 805
806/* 806/*
807 * Hazards 807 * Hazards
@@ -825,9 +825,9 @@ static __initdata u32 final_handler[64];
825 * 825 *
826 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 826 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
827 */ 827 */
828static __init void __maybe_unused build_tlb_probe_entry(u32 **p) 828static void __init __maybe_unused build_tlb_probe_entry(u32 **p)
829{ 829{
830 switch (current_cpu_data.cputype) { 830 switch (current_cpu_type()) {
831 /* Found by experiment: R4600 v2.0 needs this, too. */ 831 /* Found by experiment: R4600 v2.0 needs this, too. */
832 case CPU_R4600: 832 case CPU_R4600:
833 case CPU_R5000: 833 case CPU_R5000:
@@ -849,7 +849,7 @@ static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
849 */ 849 */
850enum tlb_write_entry { tlb_random, tlb_indexed }; 850enum tlb_write_entry { tlb_random, tlb_indexed };
851 851
852static __init void build_tlb_write_entry(u32 **p, struct label **l, 852static void __init build_tlb_write_entry(u32 **p, struct label **l,
853 struct reloc **r, 853 struct reloc **r,
854 enum tlb_write_entry wmode) 854 enum tlb_write_entry wmode)
855{ 855{
@@ -860,7 +860,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
860 case tlb_indexed: tlbw = i_tlbwi; break; 860 case tlb_indexed: tlbw = i_tlbwi; break;
861 } 861 }
862 862
863 switch (current_cpu_data.cputype) { 863 switch (current_cpu_type()) {
864 case CPU_R4000PC: 864 case CPU_R4000PC:
865 case CPU_R4000SC: 865 case CPU_R4000SC:
866 case CPU_R4000MC: 866 case CPU_R4000MC:
@@ -908,6 +908,8 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
908 case CPU_4KSC: 908 case CPU_4KSC:
909 case CPU_20KC: 909 case CPU_20KC:
910 case CPU_25KF: 910 case CPU_25KF:
911 case CPU_BCM3302:
912 case CPU_BCM4710:
911 case CPU_LOONGSON2: 913 case CPU_LOONGSON2:
912 if (m4kc_tlbp_war()) 914 if (m4kc_tlbp_war())
913 i_nop(p); 915 i_nop(p);
@@ -991,7 +993,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
991 * TMP and PTR are scratch. 993 * TMP and PTR are scratch.
992 * TMP will be clobbered, PTR will hold the pmd entry. 994 * TMP will be clobbered, PTR will hold the pmd entry.
993 */ 995 */
994static __init void 996static void __init
995build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 997build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
996 unsigned int tmp, unsigned int ptr) 998 unsigned int tmp, unsigned int ptr)
997{ 999{
@@ -1052,7 +1054,7 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
1052 * BVADDR is the faulting address, PTR is scratch. 1054 * BVADDR is the faulting address, PTR is scratch.
1053 * PTR will hold the pgd for vmalloc. 1055 * PTR will hold the pgd for vmalloc.
1054 */ 1056 */
1055static __init void 1057static void __init
1056build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 1058build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1057 unsigned int bvaddr, unsigned int ptr) 1059 unsigned int bvaddr, unsigned int ptr)
1058{ 1060{
@@ -1116,7 +1118,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1116 * TMP and PTR are scratch. 1118 * TMP and PTR are scratch.
1117 * TMP will be clobbered, PTR will hold the pgd entry. 1119 * TMP will be clobbered, PTR will hold the pgd entry.
1118 */ 1120 */
1119static __init void __maybe_unused 1121static void __init __maybe_unused
1120build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1122build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1121{ 1123{
1122 long pgdc = (long)pgd_current; 1124 long pgdc = (long)pgd_current;
@@ -1151,12 +1153,12 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1151 1153
1152#endif /* !CONFIG_64BIT */ 1154#endif /* !CONFIG_64BIT */
1153 1155
1154static __init void build_adjust_context(u32 **p, unsigned int ctx) 1156static void __init build_adjust_context(u32 **p, unsigned int ctx)
1155{ 1157{
1156 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 1158 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1157 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1159 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1158 1160
1159 switch (current_cpu_data.cputype) { 1161 switch (current_cpu_type()) {
1160 case CPU_VR41XX: 1162 case CPU_VR41XX:
1161 case CPU_VR4111: 1163 case CPU_VR4111:
1162 case CPU_VR4121: 1164 case CPU_VR4121:
@@ -1177,7 +1179,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx)
1177 i_andi(p, ctx, ctx, mask); 1179 i_andi(p, ctx, ctx, mask);
1178} 1180}
1179 1181
1180static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1182static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1181{ 1183{
1182 /* 1184 /*
1183 * Bug workaround for the Nevada. It seems as if under certain 1185 * Bug workaround for the Nevada. It seems as if under certain
@@ -1186,7 +1188,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1186 * in a different cacheline or a load instruction, probably any 1188 * in a different cacheline or a load instruction, probably any
1187 * memory reference, is between them. 1189 * memory reference, is between them.
1188 */ 1190 */
1189 switch (current_cpu_data.cputype) { 1191 switch (current_cpu_type()) {
1190 case CPU_NEVADA: 1192 case CPU_NEVADA:
1191 i_LW(p, ptr, 0, ptr); 1193 i_LW(p, ptr, 0, ptr);
1192 GET_CONTEXT(p, tmp); /* get context reg */ 1194 GET_CONTEXT(p, tmp); /* get context reg */
@@ -1202,7 +1204,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1202 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1204 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1203} 1205}
1204 1206
1205static __init void build_update_entries(u32 **p, unsigned int tmp, 1207static void __init build_update_entries(u32 **p, unsigned int tmp,
1206 unsigned int ptep) 1208 unsigned int ptep)
1207{ 1209{
1208 /* 1210 /*
@@ -1870,7 +1872,7 @@ void __init build_tlb_refill_handler(void)
1870 */ 1872 */
1871 static int run_once = 0; 1873 static int run_once = 0;
1872 1874
1873 switch (current_cpu_data.cputype) { 1875 switch (current_cpu_type()) {
1874 case CPU_R2000: 1876 case CPU_R2000:
1875 case CPU_R3000: 1877 case CPU_R3000:
1876 case CPU_R3000A: 1878 case CPU_R3000A:
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 4e0a90b3916b..aa52aa146cea 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -74,7 +74,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
74 struct op_mips_model *lmodel = NULL; 74 struct op_mips_model *lmodel = NULL;
75 int res; 75 int res;
76 76
77 switch (current_cpu_data.cputype) { 77 switch (current_cpu_type()) {
78 case CPU_5KC: 78 case CPU_5KC:
79 case CPU_20KC: 79 case CPU_20KC:
80 case CPU_24K: 80 case CPU_24K:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1ea5c9c1010b..423bc2c473df 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -118,7 +118,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
118 118
119/* Program all of the registers in preparation for enabling profiling. */ 119/* Program all of the registers in preparation for enabling profiling. */
120 120
121static void mipsxx_cpu_setup (void *args) 121static void mipsxx_cpu_setup(void *args)
122{ 122{
123 unsigned int counters = op_model_mipsxx_ops.num_counters; 123 unsigned int counters = op_model_mipsxx_ops.num_counters;
124 124
@@ -222,7 +222,7 @@ static inline int n_counters(void)
222{ 222{
223 int counters; 223 int counters;
224 224
225 switch (current_cpu_data.cputype) { 225 switch (current_cpu_type()) {
226 case CPU_R10000: 226 case CPU_R10000:
227 counters = 2; 227 counters = 2;
228 break; 228 break;
@@ -274,7 +274,7 @@ static int __init mipsxx_init(void)
274#endif 274#endif
275 275
276 op_model_mipsxx_ops.num_counters = counters; 276 op_model_mipsxx_ops.num_counters = counters;
277 switch (current_cpu_data.cputype) { 277 switch (current_cpu_type()) {
278 case CPU_20KC: 278 case CPU_20KC:
279 op_model_mipsxx_ops.cpu_type = "mips/20K"; 279 op_model_mipsxx_ops.cpu_type = "mips/20K";
280 break; 280 break;
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index d29040a56aea..a45d3202894f 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -60,7 +60,7 @@ static void rm9000_reg_setup(struct op_counter_config *ctr)
60 60
61/* Program all of the registers in preparation for enabling profiling. */ 61/* Program all of the registers in preparation for enabling profiling. */
62 62
63static void rm9000_cpu_setup (void *args) 63static void rm9000_cpu_setup(void *args)
64{ 64{
65 uint64_t perfcount; 65 uint64_t perfcount;
66 66
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 4ee6800e67e6..ed0c07622baa 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -10,6 +10,7 @@ obj-y += pci.o
10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o 11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
12obj-$(CONFIG_MIPS_MSC) += ops-msc.o 12obj-$(CONFIG_MIPS_MSC) += ops-msc.o
13obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
13obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o 14obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
14obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
15obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 16obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
19# These are still pretty much in the old state, watch, go blind. 20# These are still pretty much in the old state, watch, go blind.
20# 21#
21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o 22obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
23obj-$(CONFIG_LASAT) += pci-lasat.o
22obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 24obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
23obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 25obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
24obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 26obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index 45224fd2c7ba..506e883a8c71 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -77,12 +77,12 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
77 * code, but it is better than nothing... 77 * code, but it is better than nothing...
78 */ 78 */
79 79
80static void atlas_saa9730_base_fixup (struct pci_dev *pdev) 80static void atlas_saa9730_base_fixup(struct pci_dev *pdev)
81{ 81{
82 extern void *saa9730_base; 82 extern void *saa9730_base;
83 if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19) 83 if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19)
84 (void) pci_read_config_dword (pdev, 0x14, (u32 *)&saa9730_base); 84 (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base);
85 printk ("saa9730_base = %x\n", saa9730_base); 85 printk("saa9730_base = %x\n", saa9730_base);
86} 86}
87 87
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, 88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730,
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 76b4f0ffb1e5..f7df1142912b 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -18,6 +18,24 @@
18#include <asm/gt64120.h> 18#include <asm/gt64120.h>
19 19
20#include <cobalt.h> 20#include <cobalt.h>
21#include <irq.h>
22
23/*
24 * PCI slot numbers
25 */
26#define COBALT_PCICONF_CPU 0x06
27#define COBALT_PCICONF_ETH0 0x07
28#define COBALT_PCICONF_RAQSCSI 0x08
29#define COBALT_PCICONF_VIA 0x09
30#define COBALT_PCICONF_PCISLOT 0x0A
31#define COBALT_PCICONF_ETH1 0x0C
32
33/*
34 * The Cobalt board ID information. The boards have an ID number wired
35 * into the VIA that is available in the high nibble of register 94.
36 */
37#define VIA_COBALT_BRD_ID_REG 0x94
38#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
21 39
22static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 40static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
23{ 41{
@@ -132,29 +150,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
132 150
133static char irq_tab_qube1[] __initdata = { 151static char irq_tab_qube1[] __initdata = {
134 [COBALT_PCICONF_CPU] = 0, 152 [COBALT_PCICONF_CPU] = 0,
135 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, 153 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
136 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 154 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
137 [COBALT_PCICONF_VIA] = 0, 155 [COBALT_PCICONF_VIA] = 0,
138 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 156 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
139 [COBALT_PCICONF_ETH1] = 0 157 [COBALT_PCICONF_ETH1] = 0
140}; 158};
141 159
142static char irq_tab_cobalt[] __initdata = { 160static char irq_tab_cobalt[] __initdata = {
143 [COBALT_PCICONF_CPU] = 0, 161 [COBALT_PCICONF_CPU] = 0,
144 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 162 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
145 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 163 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
146 [COBALT_PCICONF_VIA] = 0, 164 [COBALT_PCICONF_VIA] = 0,
147 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 165 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
148 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 166 [COBALT_PCICONF_ETH1] = ETH1_IRQ
149}; 167};
150 168
151static char irq_tab_raq2[] __initdata = { 169static char irq_tab_raq2[] __initdata = {
152 [COBALT_PCICONF_CPU] = 0, 170 [COBALT_PCICONF_CPU] = 0,
153 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 171 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
154 [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, 172 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
155 [COBALT_PCICONF_VIA] = 0, 173 [COBALT_PCICONF_VIA] = 0,
156 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 174 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
157 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 175 [COBALT_PCICONF_ETH1] = ETH1_IRQ
158}; 176};
159 177
160int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 178int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 7932dfe5eb9b..6b29904acf45 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -112,7 +112,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
112 first_cfg = 0; 112 first_cfg = 0;
113 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); 113 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
114 if (!pci_cfg_vm) 114 if (!pci_cfg_vm)
115 panic (KERN_ERR "PCI unable to get vm area\n"); 115 panic(KERN_ERR "PCI unable to get vm area\n");
116 pci_cfg_wired_entry = read_c0_wired(); 116 pci_cfg_wired_entry = read_c0_wired();
117 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); 117 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
118 last_entryLo0 = last_entryLo1 = 0xffffffff; 118 last_entryLo0 = last_entryLo1 = 0xffffffff;
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
new file mode 100644
index 000000000000..b7f0fb0210f4
--- /dev/null
+++ b/arch/mips/pci/ops-nile4.c
@@ -0,0 +1,147 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/pci.h>
4#include <asm/bootinfo.h>
5
6#include <asm/lasat/lasat.h>
7#include <asm/gt64120.h>
8#include <asm/nile4.h>
9
10#define PCI_ACCESS_READ 0
11#define PCI_ACCESS_WRITE 1
12
13#define LO(reg) (reg / 4)
14#define HI(reg) (reg / 4 + 1)
15
16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
17
18static DEFINE_SPINLOCK(nile4_pci_lock);
19
20static int nile4_pcibios_config_access(unsigned char access_type,
21 struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
22{
23 unsigned char busnum = bus->number;
24 u32 adr, mask, err;
25
26 if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
27 /* The addressing scheme chosen leaves room for just
28 * 8 devices on the first busnum (besides the PCI
29 * controller itself) */
30 return PCIBIOS_DEVICE_NOT_FOUND;
31
32 if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
33 /* Access controller registers directly */
34 if (access_type == PCI_ACCESS_WRITE) {
35 vrc_pciregs[(0x200 + where) >> 2] = *val;
36 } else {
37 *val = vrc_pciregs[(0x200 + where) >> 2];
38 }
39 return PCIBIOS_SUCCESSFUL;
40 }
41
42 /* Temporarily map PCI Window 1 to config space */
43 mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
44 vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
45
46 /* Clear PCI Error register. This also clears the Error Type
47 * bits in the Control register */
48 vrc_pciregs[LO(NILE4_PCIERR)] = 0;
49 vrc_pciregs[HI(NILE4_PCIERR)] = 0;
50
51 /* Setup address */
52 if (busnum == 0)
53 adr =
54 KSEG1ADDR(PCI_WINDOW1) +
55 ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
56 | (where & ~3));
57 else
58 adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
59 (where & ~3);
60
61 if (access_type == PCI_ACCESS_WRITE)
62 *(u32 *) adr = *val;
63 else
64 *val = *(u32 *) adr;
65
66 /* Check for master or target abort */
67 err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
68
69 /* Restore PCI Window 1 */
70 vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
71
72 if (err)
73 return PCIBIOS_DEVICE_NOT_FOUND;
74
75 return PCIBIOS_SUCCESSFUL;
76}
77
78static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 *val)
80{
81 unsigned long flags;
82 u32 data = 0;
83 int err;
84
85 if ((size == 2) && (where & 1))
86 return PCIBIOS_BAD_REGISTER_NUMBER;
87 else if ((size == 4) && (where & 3))
88 return PCIBIOS_BAD_REGISTER_NUMBER;
89
90 spin_lock_irqsave(&nile4_pci_lock, flags);
91 err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
92 &data);
93 spin_unlock_irqrestore(&nile4_pci_lock, flags);
94
95 if (err)
96 return err;
97
98 if (size == 1)
99 *val = (data >> ((where & 3) << 3)) & 0xff;
100 else if (size == 2)
101 *val = (data >> ((where & 3) << 3)) & 0xffff;
102 else
103 *val = data;
104
105 return PCIBIOS_SUCCESSFUL;
106}
107
108static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
109 int where, int size, u32 val)
110{
111 unsigned long flags;
112 u32 data = 0;
113 int err;
114
115 if ((size == 2) && (where & 1))
116 return PCIBIOS_BAD_REGISTER_NUMBER;
117 else if ((size == 4) && (where & 3))
118 return PCIBIOS_BAD_REGISTER_NUMBER;
119
120 spin_lock_irqsave(&nile4_pci_lock, flags);
121 err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
122 &data);
123 spin_unlock_irqrestore(&nile4_pci_lock, flags);
124
125 if (err)
126 return err;
127
128 if (size == 1)
129 data = (data & ~(0xff << ((where & 3) << 3))) |
130 (val << ((where & 3) << 3));
131 else if (size == 2)
132 data = (data & ~(0xffff << ((where & 3) << 3))) |
133 (val << ((where & 3) << 3));
134 else
135 data = val;
136
137 if (nile4_pcibios_config_access
138 (PCI_ACCESS_WRITE, bus, devfn, where, &data))
139 return -1;
140
141 return PCIBIOS_SUCCESSFUL;
142}
143
144struct pci_ops nile4_pci_ops = {
145 .read = nile4_pcibios_read,
146 .write = nile4_pcibios_write,
147};
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index fa2d2c60f797..97ed25b92edf 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
70 70
71 switch (size) { 71 switch (size) {
72 case 1: 72 case 1:
73 outb (val, PCIMT_CONFIG_DATA + (reg & 3)); 73 outb(val, PCIMT_CONFIG_DATA + (reg & 3));
74 break; 74 break;
75 case 2: 75 case 2:
76 outw (val, PCIMT_CONFIG_DATA + (reg & 2)); 76 outw(val, PCIMT_CONFIG_DATA + (reg & 2));
77 break; 77 break;
78 case 4: 78 case 4:
79 outl (val, PCIMT_CONFIG_DATA); 79 outl(val, PCIMT_CONFIG_DATA);
80 break; 80 break;
81 } 81 }
82 82
@@ -93,7 +93,7 @@ static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int r
93 if ((devfn > 255) || (reg > 255) || (busno > 255)) 93 if ((devfn > 255) || (reg > 255) || (busno > 255))
94 return PCIBIOS_BAD_REGISTER_NUMBER; 94 return PCIBIOS_BAD_REGISTER_NUMBER;
95 95
96 outl ((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); 96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8);
97 return PCIBIOS_SUCCESSFUL; 97 return PCIBIOS_SUCCESSFUL;
98} 98}
99 99
@@ -108,12 +108,12 @@ static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg,
108 * we don't do it, we will get a data bus error 108 * we don't do it, we will get a data bus error
109 */ 109 */
110 if (bus->number == 0) { 110 if (bus->number == 0) {
111 pcit_set_config_address (0, 0, 0x68); 111 pcit_set_config_address(0, 0, 0x68);
112 outl (inl (0xcfc) | 0xc0000000, 0xcfc); 112 outl(inl(0xcfc) | 0xc0000000, 0xcfc);
113 if ((res = pcit_set_config_address(0, devfn, 0))) 113 if ((res = pcit_set_config_address(0, devfn, 0)))
114 return res; 114 return res;
115 outl (0xffffffff, 0xcfc); 115 outl(0xffffffff, 0xcfc);
116 pcit_set_config_address (0, 0, 0x68); 116 pcit_set_config_address(0, 0, 0x68);
117 if (inl(0xcfc) & 0x100000) 117 if (inl(0xcfc) & 0x100000)
118 return PCIBIOS_DEVICE_NOT_FOUND; 118 return PCIBIOS_DEVICE_NOT_FOUND;
119 } 119 }
@@ -144,13 +144,13 @@ static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg,
144 144
145 switch (size) { 145 switch (size) {
146 case 1: 146 case 1:
147 outb (val, PCIMT_CONFIG_DATA + (reg & 3)); 147 outb(val, PCIMT_CONFIG_DATA + (reg & 3));
148 break; 148 break;
149 case 2: 149 case 2:
150 outw (val, PCIMT_CONFIG_DATA + (reg & 2)); 150 outw(val, PCIMT_CONFIG_DATA + (reg & 2));
151 break; 151 break;
152 case 4: 152 case 4:
153 outl (val, PCIMT_CONFIG_DATA); 153 outl(val, PCIMT_CONFIG_DATA);
154 break; 154 break;
155 } 155 }
156 156
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 2b4e30c7d105..5443ea3596f8 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -49,8 +49,8 @@
49 * Macros for calculating offsets into config space given a device 49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg 50 * structure or dev/fun/reg
51 */ 51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 52#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 53#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
@@ -255,7 +255,7 @@ static int __init bcm1480_pcibios_init(void)
255 register_pci_controller(&bcm1480_controller); 255 register_pci_controller(&bcm1480_controller);
256 256
257#ifdef CONFIG_VGA_CONSOLE 257#ifdef CONFIG_VGA_CONSOLE
258 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); 258 take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
259#endif 259#endif
260 return 0; 260 return 0;
261} 261}
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index ba2e34b09231..a63e3bd6b0ac 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -48,8 +48,8 @@
48 * Macros for calculating offsets into config space given a device 48 * Macros for calculating offsets into config space given a device
49 * structure or dev/fun/reg 49 * structure or dev/fun/reg
50 */ 50 */
51#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 51#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
52#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 52#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
53 53
54static void *ht_cfg_space; 54static void *ht_cfg_space;
55 55
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
new file mode 100644
index 000000000000..5abd5c7119be
--- /dev/null
+++ b/arch/mips/pci/pci-lasat.c
@@ -0,0 +1,91 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2001, 04 Keith M Wesolowski
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/types.h>
12#include <asm/bootinfo.h>
13
14extern struct pci_ops nile4_pci_ops;
15extern struct pci_ops gt64xxx_pci0_ops;
16static struct resource lasat_pci_mem_resource = {
17 .name = "LASAT PCI MEM",
18 .start = 0x18000000,
19 .end = 0x19ffffff,
20 .flags = IORESOURCE_MEM,
21};
22
23static struct resource lasat_pci_io_resource = {
24 .name = "LASAT PCI IO",
25 .start = 0x1a000000,
26 .end = 0x1bffffff,
27 .flags = IORESOURCE_IO,
28};
29
30static struct pci_controller lasat_pci_controller = {
31 .mem_resource = &lasat_pci_mem_resource,
32 .io_resource = &lasat_pci_io_resource,
33};
34
35static int __init lasat_pci_setup(void)
36{
37 printk(KERN_DEBUG "PCI: starting\n");
38
39 switch (mips_machtype) {
40 case MACH_LASAT_100:
41 lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
42 break;
43 case MACH_LASAT_200:
44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
45 break;
46 default:
47 panic("pcibios_init: mips_machtype incorrect");
48 }
49
50 register_pci_controller(&lasat_pci_controller);
51
52 return 0;
53}
54
55arch_initcall(lasat_pci_setup);
56
57#define LASATINT_ETH1 0
58#define LASATINT_ETH0 1
59#define LASATINT_HDC 2
60#define LASATINT_COMP 3
61#define LASATINT_HDLC 4
62#define LASATINT_PCIA 5
63#define LASATINT_PCIB 6
64#define LASATINT_PCIC 7
65#define LASATINT_PCID 8
66
67int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
68{
69 switch (slot) {
70 case 1:
71 case 2:
72 case 3:
73 return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
74 case 4:
75 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
76 case 5:
77 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
78 case 6:
79 return LASATINT_HDC; /* IDE controller */
80 default:
81 return 0xff; /* Illegal */
82 }
83
84 return -1;
85}
86
87/* Do platform specific device initialization at pci_enable_device() time */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index c1ac6493155e..42e4d2c800fa 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -49,8 +49,8 @@
49 * Macros for calculating offsets into config space given a device 49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg 50 * structure or dev/fun/reg
51 */ 51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where)) 52#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 53#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 9885fa403603..240df9e33813 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -228,7 +228,7 @@ static int __init vr41xx_pciu_init(void)
228 else 228 else
229 pciu_write(PCIEXACCREG, 0); 229 pciu_write(PCIEXACCREG, 0);
230 230
231 if (current_cpu_data.cputype == CPU_VR4122) 231 if (current_cpu_type() == CPU_VR4122)
232 pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy)); 232 pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
233 233
234 pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer)); 234 pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
index 92311e95b700..18b125e3b65d 100644
--- a/arch/mips/philips/pnx8550/common/proc.c
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -27,20 +27,20 @@
27#include <uart.h> 27#include <uart.h>
28 28
29 29
30static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) 30static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
31{ 31{
32 int len = 0; 32 int len = 0;
33 int configPR = read_c0_config7(); 33 int configPR = read_c0_config7();
34 34
35 if (offset==0) { 35 if (offset==0) {
36 len += sprintf(&page[len],"Timer: count, compare, tc, status\n"); 36 len += sprintf(&page[len], "Timer: count, compare, tc, status\n");
37 len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n", 37 len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n",
38 read_c0_count(), read_c0_compare(), 38 read_c0_count(), read_c0_compare(),
39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); 39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
40 len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n", 40 len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n",
41 read_c0_count2(), read_c0_compare2(), 41 read_c0_count2(), read_c0_compare2(),
42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); 42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
43 len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n", 43 len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n",
44 read_c0_count3(), read_c0_compare3(), 44 read_c0_count3(), read_c0_compare3(),
45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); 45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
46 } 46 }
@@ -48,23 +48,23 @@ static int pnx8550_timers_read (char* page, char** start, off_t offset, int coun
48 return len; 48 return len;
49} 49}
50 50
51static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) 51static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
52{ 52{
53 int len = 0; 53 int len = 0;
54 54
55 if (offset==0) { 55 if (offset==0) {
56 len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1()); 56 len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1());
57 len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2()); 57 len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2());
58 len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3()); 58 len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3());
59 len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7()); 59 len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7());
60 len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status()); 60 len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status());
61 len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause()); 61 len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause());
62 len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count()); 62 len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count());
63 len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2()); 63 len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2());
64 len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3()); 64 len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3());
65 len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare()); 65 len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare());
66 len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2()); 66 len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2());
67 len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3()); 67 len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3());
68 } 68 }
69 69
70 return len; 70 return len;
diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c
index 5bd737477685..2ce298f4d19a 100644
--- a/arch/mips/philips/pnx8550/common/setup.c
+++ b/arch/mips/philips/pnx8550/common/setup.c
@@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void);
47extern void pnx8550_machine_power_off(void); 47extern void pnx8550_machine_power_off(void);
48extern struct resource ioport_resource; 48extern struct resource ioport_resource;
49extern struct resource iomem_resource; 49extern struct resource iomem_resource;
50extern void pnx8550_time_init(void);
51extern void rs_kgdb_hook(int tty_no); 50extern void rs_kgdb_hook(int tty_no);
52extern char *prom_getcmdline(void); 51extern char *prom_getcmdline(void);
53 52
@@ -104,8 +103,6 @@ void __init plat_mem_setup(void)
104 _machine_halt = pnx8550_machine_halt; 103 _machine_halt = pnx8550_machine_halt;
105 pm_power_off = pnx8550_machine_power_off; 104 pm_power_off = pnx8550_machine_power_off;
106 105
107 board_time_init = pnx8550_time_init;
108
109 /* Clear the Global 2 Register, PCI Inta Output Enable Registers 106 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
110 Bit 1:Enable DAC Powerdown 107 Bit 1:Enable DAC Powerdown
111 -> 0:DACs are enabled and are working normally 108 -> 0:DACs are enabled and are working normally
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 68def3880a1c..e818fd0f1584 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright 2001, 2002, 2003 MontaVista Software Inc. 2 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
4 * 5 *
5 * Common time service routines for MIPS machines. See 6 * Common time service routines for MIPS machines. See
6 * Documents/MIPS/README.txt. 7 * Documents/MIPS/README.txt.
@@ -46,16 +47,16 @@ static void timer_ack(void)
46} 47}
47 48
48/* 49/*
49 * pnx8550_time_init() - it does the following things: 50 * plat_time_init() - it does the following things:
50 * 51 *
51 * 1) board_time_init() - 52 * 1) plat_time_init() -
52 * a) (optional) set up RTC routines, 53 * a) (optional) set up RTC routines,
53 * b) (optional) calibrate and set the mips_hpt_frequency 54 * b) (optional) calibrate and set the mips_hpt_frequency
54 * (only needed if you intended to use cpu counter as timer interrupt 55 * (only needed if you intended to use cpu counter as timer interrupt
55 * source) 56 * source)
56 */ 57 */
57 58
58void pnx8550_time_init(void) 59__init void plat_time_init(void)
59{ 60{
60 unsigned int n; 61 unsigned int n;
61 unsigned int m; 62 unsigned int m;
diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c
index 85f449174bc3..cfd90fa3d799 100644
--- a/arch/mips/philips/pnx8550/jbs/init.c
+++ b/arch/mips/philips/pnx8550/jbs/init.c
@@ -48,7 +48,6 @@ void __init prom_init(void)
48 48
49 unsigned long memsize; 49 unsigned long memsize;
50 50
51 mips_machgroup = MACH_GROUP_PHILIPS;
52 mips_machtype = MACH_PHILIPS_JBS; 51 mips_machtype = MACH_PHILIPS_JBS;
53 52
54 //memsize = 0x02800000; /* Trimedia uses memory above */ 53 //memsize = 0x02800000; /* Trimedia uses memory above */
diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c
index ea5b4e0fb47d..fdb33ed089b9 100644
--- a/arch/mips/philips/pnx8550/stb810/prom_init.c
+++ b/arch/mips/philips/pnx8550/stb810/prom_init.c
@@ -41,7 +41,6 @@ void __init prom_init(void)
41 41
42 prom_init_cmdline(); 42 prom_init_cmdline();
43 43
44 mips_machgroup = MACH_GROUP_PHILIPS;
45 mips_machtype = MACH_PHILIPS_STB810; 44 mips_machtype = MACH_PHILIPS_STB810;
46 45
47 memsize = 0x08000000; /* Trimedia uses memory above */ 46 memsize = 0x08000000; /* Trimedia uses memory above */
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index 6fa85728158b..ab96a2d7f4c4 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -163,7 +163,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
163 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq); 163 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
164 *CIC_EXT_CFG_REG = cic_ext; 164 *CIC_EXT_CFG_REG = cic_ext;
165 165
166 return request_irq(hirq->irq, hwbutton_handler, SA_INTERRUPT, 166 return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED,
167 hirq->name, (void *)hirq); 167 hirq->name, (void *)hirq);
168} 168}
169 169
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index e25bac537d77..15e7b8000b4c 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -117,7 +117,7 @@ void __init msp_serial_setup(void)
117 117
118 /* Initialize first serial port */ 118 /* Initialize first serial port */
119 up.mapbase = MSP_UART0_BASE; 119 up.mapbase = MSP_UART0_BASE;
120 up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); 120 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
121 up.irq = MSP_INT_UART0; 121 up.irq = MSP_INT_UART0;
122 up.uartclk = uartclk; 122 up.uartclk = uartclk;
123 up.regshift = 2; 123 up.regshift = 2;
@@ -145,9 +145,9 @@ void __init msp_serial_setup(void)
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) { 145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA 146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA ) 147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk,19200); 148 initDebugPort(uartclk, 19200);
149 else 149 else
150 initDebugPort(uartclk,57600); 150 initDebugPort(uartclk, 57600);
151 } 151 }
152#endif 152#endif
153 break; 153 break;
@@ -157,7 +157,7 @@ void __init msp_serial_setup(void)
157 } 157 }
158 158
159 up.mapbase = MSP_UART1_BASE; 159 up.mapbase = MSP_UART1_BASE;
160 up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); 160 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
161 up.irq = MSP_INT_UART1; 161 up.irq = MSP_INT_UART1;
162 up.line = 1; 162 up.line = 1;
163 up.private_data = (void*)UART1_STATUS_REG; 163 up.private_data = (void*)UART1_STATUS_REG;
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index 8f69b789be90..c93675615f5d 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -25,7 +25,6 @@
25#define MSP_BOARD_RESET_GPIO 9 25#define MSP_BOARD_RESET_GPIO 9
26#endif 26#endif
27 27
28extern void msp_timer_init(void);
29extern void msp_serial_setup(void); 28extern void msp_serial_setup(void);
30extern void pmctwiled_setup(void); 29extern void pmctwiled_setup(void);
31 30
@@ -149,8 +148,6 @@ void __init plat_mem_setup(void)
149 _machine_restart = msp_restart; 148 _machine_restart = msp_restart;
150 _machine_halt = msp_halt; 149 _machine_halt = msp_halt;
151 pm_power_off = msp_power_off; 150 pm_power_off = msp_power_off;
152
153 board_time_init = msp_timer_init;
154} 151}
155 152
156void __init prom_init(void) 153void __init prom_init(void)
@@ -176,16 +173,13 @@ void __init prom_init(void)
176 case FAMILY_FPGA: 173 case FAMILY_FPGA:
177 if (FPGA_IS_MSP4200(revision)) { 174 if (FPGA_IS_MSP4200(revision)) {
178 /* Old-style revision ID */ 175 /* Old-style revision ID */
179 mips_machgroup = MACH_GROUP_MSP;
180 mips_machtype = MACH_MSP4200_FPGA; 176 mips_machtype = MACH_MSP4200_FPGA;
181 } else { 177 } else {
182 mips_machgroup = MACH_GROUP_MSP;
183 mips_machtype = MACH_MSP_OTHER; 178 mips_machtype = MACH_MSP_OTHER;
184 } 179 }
185 break; 180 break;
186 181
187 case FAMILY_MSP4200: 182 case FAMILY_MSP4200:
188 mips_machgroup = MACH_GROUP_MSP;
189#if defined(CONFIG_PMC_MSP4200_EVAL) 183#if defined(CONFIG_PMC_MSP4200_EVAL)
190 mips_machtype = MACH_MSP4200_EVAL; 184 mips_machtype = MACH_MSP4200_EVAL;
191#elif defined(CONFIG_PMC_MSP4200_GW) 185#elif defined(CONFIG_PMC_MSP4200_GW)
@@ -196,12 +190,10 @@ void __init prom_init(void)
196 break; 190 break;
197 191
198 case FAMILY_MSP4200_FPGA: 192 case FAMILY_MSP4200_FPGA:
199 mips_machgroup = MACH_GROUP_MSP;
200 mips_machtype = MACH_MSP4200_FPGA; 193 mips_machtype = MACH_MSP4200_FPGA;
201 break; 194 break;
202 195
203 case FAMILY_MSP7100: 196 case FAMILY_MSP7100:
204 mips_machgroup = MACH_GROUP_MSP;
205#if defined(CONFIG_PMC_MSP7120_EVAL) 197#if defined(CONFIG_PMC_MSP7120_EVAL)
206 mips_machtype = MACH_MSP7120_EVAL; 198 mips_machtype = MACH_MSP7120_EVAL;
207#elif defined(CONFIG_PMC_MSP7120_GW) 199#elif defined(CONFIG_PMC_MSP7120_GW)
@@ -212,22 +204,14 @@ void __init prom_init(void)
212 break; 204 break;
213 205
214 case FAMILY_MSP7100_FPGA: 206 case FAMILY_MSP7100_FPGA:
215 mips_machgroup = MACH_GROUP_MSP;
216 mips_machtype = MACH_MSP7120_FPGA; 207 mips_machtype = MACH_MSP7120_FPGA;
217 break; 208 break;
218 209
219 default: 210 default:
220 /* we don't recognize the machine */ 211 /* we don't recognize the machine */
221 mips_machgroup = MACH_GROUP_UNKNOWN;
222 mips_machtype = MACH_UNKNOWN; 212 mips_machtype = MACH_UNKNOWN;
223 break;
224 }
225
226 /* make sure we have the right initialization routine - sanity */
227 if (mips_machgroup != MACH_GROUP_MSP) {
228 ppfinit("Unknown machine group in a "
229 "MSP initialization routine\n");
230 panic("***Bogosity factor five***, exiting\n"); 213 panic("***Bogosity factor five***, exiting\n");
214 break;
231 } 215 }
232 216
233 prom_init_cmdline(); 217 prom_init_cmdline();
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
index 2a2beac5a4f8..f221d4763625 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_time.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -36,7 +36,7 @@
36#include <msp_int.h> 36#include <msp_int.h>
37#include <msp_regs.h> 37#include <msp_regs.h>
38 38
39void __init msp_timer_init(void) 39void __init plat_time_init(void)
40{ 40{
41 char *endp, *s; 41 char *endp, *s;
42 unsigned long cpu_rate = 0; 42 unsigned long cpu_rate = 0;
@@ -81,7 +81,6 @@ void __init msp_timer_init(void)
81 mips_hpt_frequency = cpu_rate/2; 81 mips_hpt_frequency = cpu_rate/2;
82} 82}
83 83
84
85void __init plat_timer_setup(struct irqaction *irq) 84void __init plat_timer_setup(struct irqaction *irq)
86{ 85{
87#ifdef CONFIG_IRQ_MSP_CIC 86#ifdef CONFIG_IRQ_MSP_CIC
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
index 21f9c70b6923..f7ca4f582331 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -58,7 +58,7 @@ static struct platform_device msp_usbhost_device = {
58 .dma_mask = &msp_usbhost_dma_mask, 58 .dma_mask = &msp_usbhost_dma_mask,
59 .coherent_dma_mask = DMA_32BIT_MASK, 59 .coherent_dma_mask = DMA_32BIT_MASK,
60 }, 60 },
61 .num_resources = ARRAY_SIZE (msp_usbhost_resources), 61 .num_resources = ARRAY_SIZE(msp_usbhost_resources),
62 .resource = msp_usbhost_resources, 62 .resource = msp_usbhost_resources,
63}; 63};
64#endif /* CONFIG_USB_EHCI_HCD */ 64#endif /* CONFIG_USB_EHCI_HCD */
@@ -86,7 +86,7 @@ static struct platform_device msp_usbdev_device = {
86 .dma_mask = &msp_usbdev_dma_mask, 86 .dma_mask = &msp_usbdev_dma_mask,
87 .coherent_dma_mask = DMA_32BIT_MASK, 87 .coherent_dma_mask = DMA_32BIT_MASK,
88 }, 88 },
89 .num_resources = ARRAY_SIZE (msp_usbdev_resources), 89 .num_resources = ARRAY_SIZE(msp_usbdev_resources),
90 .resource = msp_usbdev_resources, 90 .resource = msp_usbdev_resources,
91}; 91};
92#endif /* CONFIG_USB_GADGET */ 92#endif /* CONFIG_USB_GADGET */
@@ -129,7 +129,7 @@ static int __init msp_usb_setup(void)
129 ppfinit("platform add USB HOST done %s.\n", 129 ppfinit("platform add USB HOST done %s.\n",
130 msp_devs[0]->name); 130 msp_devs[0]->name);
131 131
132 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); 132 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
133#endif /* CONFIG_USB_EHCI_HCD */ 133#endif /* CONFIG_USB_EHCI_HCD */
134 } 134 }
135#if defined(CONFIG_USB_GADGET) 135#if defined(CONFIG_USB_GADGET)
@@ -139,7 +139,7 @@ static int __init msp_usb_setup(void)
139 ppfinit("platform add USB DEVICE done %s.\n", 139 ppfinit("platform add USB DEVICE done %s.\n",
140 msp_devs[0]->name); 140 msp_devs[0]->name);
141 141
142 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); 142 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
143 } 143 }
144#endif /* CONFIG_USB_GADGET */ 144#endif /* CONFIG_USB_GADGET */
145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ 145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
index 1f7c999eb7c6..6380662bbf3c 100644
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -115,7 +115,7 @@ static int titan_ht_config_read_word(struct pci_dev *device,
115 115
116u32 longswap(unsigned long l) 116u32 longswap(unsigned long l)
117{ 117{
118 unsigned char b1,b2,b3,b4; 118 unsigned char b1, b2, b3, b4;
119 119
120 b1 = l&255; 120 b1 = l&255;
121 b2 = (l>>8)&255; 121 b2 = (l>>8)&255;
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
index 0cd78f0f5f2d..9b9936de6589 100644
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ b/arch/mips/pmc-sierra/yosemite/prom.c
@@ -126,7 +126,6 @@ void __init prom_init(void)
126 env++; 126 env++;
127 } 127 }
128 128
129 mips_machgroup = MACH_GROUP_TITAN;
130 mips_machtype = MACH_TITAN_YOSEMITE; 129 mips_machtype = MACH_TITAN_YOSEMITE;
131 130
132 prom_grab_secondary(); 131 prom_grab_secondary();
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
index 58862c8d1d00..015fcc363dc0 100644
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ b/arch/mips/pmc-sierra/yosemite/setup.c
@@ -70,7 +70,7 @@ void __init bus_error_init(void)
70} 70}
71 71
72 72
73unsigned long m48t37y_get_time(void) 73unsigned long read_persistent_clock(void)
74{ 74{
75 unsigned int year, month, day, hour, min, sec; 75 unsigned int year, month, day, hour, min, sec;
76 unsigned long flags; 76 unsigned long flags;
@@ -95,13 +95,17 @@ unsigned long m48t37y_get_time(void)
95 return mktime(year, month, day, hour, min, sec); 95 return mktime(year, month, day, hour, min, sec);
96} 96}
97 97
98int m48t37y_set_time(unsigned long sec) 98int rtc_mips_set_time(unsigned long tim)
99{ 99{
100 struct rtc_time tm; 100 struct rtc_time tm;
101 unsigned long flags; 101 unsigned long flags;
102 102
103 /* convert to a more useful format -- note months count from 0 */ 103 /*
104 to_tm(sec, &tm); 104 * Convert to a more useful format -- note months count from 0
105 * and years from 1900
106 */
107 rtc_time_to_tm(tim, &tm);
108 tm.tm_year += 1900;
105 tm.tm_mon += 1; 109 tm.tm_mon += 1;
106 110
107 spin_lock_irqsave(&rtc_lock, flags); 111 spin_lock_irqsave(&rtc_lock, flags);
@@ -138,7 +142,7 @@ void __init plat_timer_setup(struct irqaction *irq)
138 setup_irq(7, irq); 142 setup_irq(7, irq);
139} 143}
140 144
141void yosemite_time_init(void) 145void __init plat_time_init(void)
142{ 146{
143 mips_hpt_frequency = cpu_clock_freq / 2; 147 mips_hpt_frequency = cpu_clock_freq / 2;
144mips_hpt_frequency = 33000000 * 3 * 5; 148mips_hpt_frequency = 33000000 * 3 * 5;
@@ -198,17 +202,6 @@ static void __init py_rtc_setup(void)
198 m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE); 202 m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
199 if (!m48t37_base) 203 if (!m48t37_base)
200 printk(KERN_ERR "Mapping the RTC failed\n"); 204 printk(KERN_ERR "Mapping the RTC failed\n");
201
202 rtc_mips_get_time = m48t37y_get_time;
203 rtc_mips_set_time = m48t37y_set_time;
204
205 write_seqlock(&xtime_lock);
206 xtime.tv_sec = m48t37y_get_time();
207 xtime.tv_nsec = 0;
208
209 set_normalized_timespec(&wall_to_monotonic,
210 -xtime.tv_sec, -xtime.tv_nsec);
211 write_sequnlock(&xtime_lock);
212} 205}
213 206
214/* Not only time init but that's what the hook it's called through is named */ 207/* Not only time init but that's what the hook it's called through is named */
@@ -221,7 +214,6 @@ static void __init py_late_time_init(void)
221 214
222void __init plat_mem_setup(void) 215void __init plat_mem_setup(void)
223{ 216{
224 board_time_init = yosemite_time_init;
225 late_time_init = py_late_time_init; 217 late_time_init = py_late_time_init;
226 218
227 /* Add memory regions */ 219 /* Add memory regions */
diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c
index fb2a8673a6bf..c2239b417587 100644
--- a/arch/mips/qemu/q-firmware.c
+++ b/arch/mips/qemu/q-firmware.c
@@ -10,7 +10,7 @@ void __init prom_init(void)
10 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260); 10 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260);
11 if (*cmdline == 0x12345678) { 11 if (*cmdline == 0x12345678) {
12 if (*(char *)(cmdline + 1)) 12 if (*(char *)(cmdline + 1))
13 strcpy (arcs_cmdline, (char *)(cmdline + 1)); 13 strcpy(arcs_cmdline, (char *)(cmdline + 1));
14 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM); 14 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM);
15 } else { 15 } else {
16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); 16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
index 89891e984b3b..4681757460a1 100644
--- a/arch/mips/qemu/q-irq.c
+++ b/arch/mips/qemu/q-irq.c
@@ -2,6 +2,7 @@
2#include <linux/linkage.h> 2#include <linux/linkage.h>
3 3
4#include <asm/i8259.h> 4#include <asm/i8259.h>
5#include <asm/irq_cpu.h>
5#include <asm/mipsregs.h> 6#include <asm/mipsregs.h>
6#include <asm/qemu.h> 7#include <asm/qemu.h>
7#include <asm/system.h> 8#include <asm/system.h>
@@ -12,7 +13,7 @@ asmlinkage void plat_irq_dispatch(void)
12 unsigned int pending = read_c0_status() & read_c0_cause(); 13 unsigned int pending = read_c0_status() & read_c0_cause();
13 14
14 if (pending & 0x8000) { 15 if (pending & 0x8000) {
15 ll_timer_interrupt(Q_COUNT_COMPARE_IRQ); 16 do_IRQ(Q_COUNT_COMPARE_IRQ);
16 return; 17 return;
17 } 18 }
18 if (pending & 0x0400) { 19 if (pending & 0x0400) {
@@ -29,6 +30,7 @@ void __init arch_init_irq(void)
29{ 30{
30 mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ 31 mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */
31 32
33 mips_cpu_irq_init();
32 init_i8259_irqs(); 34 init_i8259_irqs();
33 set_c0_status(0x8400); 35 set_c0_status(0x8400);
34} 36}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
index 841394336f00..23d34c1917c0 100644
--- a/arch/mips/qemu/q-setup.c
+++ b/arch/mips/qemu/q-setup.c
@@ -1,4 +1,6 @@
1#include <linux/init.h> 1#include <linux/init.h>
2
3#include <asm/i8253.h>
2#include <asm/io.h> 4#include <asm/io.h>
3#include <asm/time.h> 5#include <asm/time.h>
4 6
@@ -11,13 +13,9 @@ const char *get_system_type(void)
11 return "Qemu"; 13 return "Qemu";
12} 14}
13 15
14void __init plat_timer_setup(struct irqaction *irq) 16void __init plat_time_init(void)
15{ 17{
16 /* set the clock to 100 Hz */ 18 setup_pit_timer();
17 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
18 outb_p(LATCH & 0xff , 0x40); /* LSB */
19 outb(LATCH >> 8 , 0x40); /* MSB */
20 setup_irq(0, irq);
21} 19}
22 20
23void __init plat_mem_setup(void) 21void __init plat_mem_setup(void)
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 6b6e97b90c6e..26854fb11e7c 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -55,7 +55,7 @@ static char __init *decode_eisa_sig(unsigned long addr)
55 int i; 55 int i;
56 56
57 for (i = 0; i < 4; i++) { 57 for (i = 0; i < 4; i++) {
58 sig[i] = inb (addr + i); 58 sig[i] = inb(addr + i);
59 59
60 if (!i && (sig[0] & 0x80)) 60 if (!i && (sig[0] & 0x80))
61 return NULL; 61 return NULL;
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 18348321795d..f6d9bf4b26e7 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -20,10 +20,10 @@
20#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/addrspace.h> 21#include <asm/addrspace.h>
22#include <asm/irq_cpu.h> 22#include <asm/irq_cpu.h>
23
24#include <asm/sgi/ioc.h> 23#include <asm/sgi/ioc.h>
25#include <asm/sgi/hpc3.h> 24#include <asm/sgi/hpc3.h>
26#include <asm/sgi/ip22.h> 25#include <asm/sgi/ip22.h>
26#include <asm/time.h>
27 27
28/* #define DEBUG_SGINT */ 28/* #define DEBUG_SGINT */
29 29
@@ -204,7 +204,6 @@ static struct irqaction map1_cascade = {
204#define SGI_INTERRUPTS SGINT_LOCAL3 204#define SGI_INTERRUPTS SGINT_LOCAL3
205#endif 205#endif
206 206
207extern void indy_r4k_timer_interrupt(void);
208extern void indy_8254timer_irq(void); 207extern void indy_8254timer_irq(void);
209 208
210/* 209/*
@@ -243,7 +242,7 @@ asmlinkage void plat_irq_dispatch(void)
243 * First we check for r4k counter/timer IRQ. 242 * First we check for r4k counter/timer IRQ.
244 */ 243 */
245 if (pending & CAUSEF_IP7) 244 if (pending & CAUSEF_IP7)
246 indy_r4k_timer_interrupt(); 245 do_IRQ(SGI_TIMER_IRQ);
247 else if (pending & CAUSEF_IP2) 246 else if (pending & CAUSEF_IP2)
248 indy_local0_irqdispatch(); 247 indy_local0_irqdispatch();
249 else if (pending & CAUSEF_IP3) 248 else if (pending & CAUSEF_IP3)
@@ -345,6 +344,6 @@ void __init arch_init_irq(void)
345 344
346#ifdef CONFIG_EISA 345#ifdef CONFIG_EISA
347 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ 346 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
348 ip22_eisa_init (); 347 ip22_eisa_init();
349#endif 348#endif
350} 349}
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index e7ce7982db72..174f09e42f6b 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -51,7 +51,6 @@ void ip22_do_break(void)
51EXPORT_SYMBOL(ip22_do_break); 51EXPORT_SYMBOL(ip22_do_break);
52 52
53extern void ip22_be_init(void) __init; 53extern void ip22_be_init(void) __init;
54extern void ip22_time_init(void) __init;
55 54
56void __init plat_mem_setup(void) 55void __init plat_mem_setup(void)
57{ 56{
@@ -59,7 +58,6 @@ void __init plat_mem_setup(void)
59 char *cserial; 58 char *cserial;
60 59
61 board_be_init = ip22_be_init; 60 board_be_init = ip22_be_init;
62 ip22_time_init();
63 61
64 /* Init the INDY HPC I/O controller. Need to call this before 62 /* Init the INDY HPC I/O controller. Need to call this before
65 * fucking with the memory controller because it needs to know the 63 * fucking with the memory controller because it needs to know the
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index de3d01823ad5..9b9bffd2e8fb 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/cpu.h> 21#include <asm/cpu.h>
22#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
23#include <asm/i8253.h>
23#include <asm/io.h> 24#include <asm/io.h>
24#include <asm/irq.h> 25#include <asm/irq.h>
25#include <asm/time.h> 26#include <asm/time.h>
@@ -29,10 +30,10 @@
29#include <asm/sgi/ip22.h> 30#include <asm/sgi/ip22.h>
30 31
31/* 32/*
32 * note that mktime uses month from 1 to 12 while to_tm 33 * Note that mktime uses month from 1 to 12 while rtc_time_to_tm
33 * uses 0 to 11. 34 * uses 0 to 11.
34 */ 35 */
35static unsigned long indy_rtc_get_time(void) 36unsigned long read_persistent_clock(void)
36{ 37{
37 unsigned int yrs, mon, day, hrs, min, sec; 38 unsigned int yrs, mon, day, hrs, min, sec;
38 unsigned int save_control; 39 unsigned int save_control;
@@ -60,16 +61,16 @@ static unsigned long indy_rtc_get_time(void)
60 return mktime(yrs + 1900, mon, day, hrs, min, sec); 61 return mktime(yrs + 1900, mon, day, hrs, min, sec);
61} 62}
62 63
63static int indy_rtc_set_time(unsigned long tim) 64int rtc_mips_set_time(unsigned long tim)
64{ 65{
65 struct rtc_time tm; 66 struct rtc_time tm;
66 unsigned int save_control; 67 unsigned int save_control;
67 unsigned long flags; 68 unsigned long flags;
68 69
69 to_tm(tim, &tm); 70 rtc_time_to_tm(tim, &tm);
70 71
71 tm.tm_mon += 1; /* tm_mon starts at zero */ 72 tm.tm_mon += 1; /* tm_mon starts at zero */
72 tm.tm_year -= 1940; 73 tm.tm_year -= 40;
73 if (tm.tm_year >= 100) 74 if (tm.tm_year >= 100)
74 tm.tm_year -= 100; 75 tm.tm_year -= 100;
75 76
@@ -128,7 +129,7 @@ static unsigned long dosample(void)
128/* 129/*
129 * Here we need to calibrate the cycle counter to at least be close. 130 * Here we need to calibrate the cycle counter to at least be close.
130 */ 131 */
131static __init void indy_time_init(void) 132__init void plat_time_init(void)
132{ 133{
133 unsigned long r4k_ticks[3]; 134 unsigned long r4k_ticks[3];
134 unsigned long r4k_tick; 135 unsigned long r4k_tick;
@@ -172,6 +173,9 @@ static __init void indy_time_init(void)
172 (int) (r4k_tick % (500000 / HZ))); 173 (int) (r4k_tick % (500000 / HZ)));
173 174
174 mips_hpt_frequency = r4k_tick * HZ; 175 mips_hpt_frequency = r4k_tick * HZ;
176
177 if (ip22_is_fullhouse())
178 setup_pit_timer();
175} 179}
176 180
177/* Generic SGI handler for (spurious) 8254 interrupts */ 181/* Generic SGI handler for (spurious) 8254 interrupts */
@@ -189,16 +193,6 @@ void indy_8254timer_irq(void)
189 irq_exit(); 193 irq_exit();
190} 194}
191 195
192void indy_r4k_timer_interrupt(void)
193{
194 int irq = SGI_TIMER_IRQ;
195
196 irq_enter();
197 kstat_this_cpu.irqs[irq]++;
198 timer_interrupt(irq, NULL);
199 irq_exit();
200}
201
202void __init plat_timer_setup(struct irqaction *irq) 196void __init plat_timer_setup(struct irqaction *irq)
203{ 197{
204 /* over-write the handler, we use our own way */ 198 /* over-write the handler, we use our own way */
@@ -207,12 +201,3 @@ void __init plat_timer_setup(struct irqaction *irq)
207 /* setup irqaction */ 201 /* setup irqaction */
208 setup_irq(SGI_TIMER_IRQ, irq); 202 setup_irq(SGI_TIMER_IRQ, irq);
209} 203}
210
211void __init ip22_time_init(void)
212{
213 /* setup hookup functions */
214 rtc_mips_get_time = indy_rtc_get_time;
215 rtc_mips_set_time = indy_rtc_set_time;
216
217 board_time_init = indy_time_init;
218}
diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c
index 123141ab21a2..7d05e68fdc77 100644
--- a/arch/mips/sgi-ip27/ip27-berr.c
+++ b/arch/mips/sgi-ip27/ip27-berr.c
@@ -21,8 +21,6 @@
21#include <asm/traps.h> 21#include <asm/traps.h>
22#include <asm/uaccess.h> 22#include <asm/uaccess.h>
23 23
24extern void dump_tlb_all(void);
25
26static void dump_hub_information(unsigned long errst0, unsigned long errst1) 24static void dump_hub_information(unsigned long errst0, unsigned long errst1)
27{ 25{
28 static char *err_type[2][8] = { 26 static char *err_type[2][8] = {
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 74158d349630..681b593071cb 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -47,6 +47,9 @@ cnodeid_t cpuid_to_compact_node[MAXCPUS];
47 47
48EXPORT_SYMBOL(nasid_to_compact_node); 48EXPORT_SYMBOL(nasid_to_compact_node);
49 49
50struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
51EXPORT_SYMBOL_GPL(sn_cpu_info);
52
50extern void pcibr_setup(cnodeid_t); 53extern void pcibr_setup(cnodeid_t);
51 54
52extern void xtalk_probe_node(cnodeid_t nid); 55extern void xtalk_probe_node(cnodeid_t nid);
@@ -191,7 +194,6 @@ static inline void ioc3_eth_init(void)
191 ioc3->eier = 0; 194 ioc3->eier = 0;
192} 195}
193 196
194extern void ip27_time_init(void);
195extern void ip27_reboot_setup(void); 197extern void ip27_reboot_setup(void);
196 198
197void __init plat_mem_setup(void) 199void __init plat_mem_setup(void)
@@ -238,6 +240,4 @@ void __init plat_mem_setup(void)
238 per_cpu_init(); 240 per_cpu_init();
239 241
240 set_io_port_base(IO_BASE); 242 set_io_port_base(IO_BASE);
241
242 board_time_init = ip27_time_init;
243} 243}
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index fbb27728a76a..a70656d42191 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -33,7 +33,7 @@ static void alloc_cpupda(cpuid_t cpu, int cpunum)
33 nasid_t nasid = COMPACT_TO_NASID_NODEID(node); 33 nasid_t nasid = COMPACT_TO_NASID_NODEID(node);
34 34
35 cputonasid(cpunum) = nasid; 35 cputonasid(cpunum) = nasid;
36 cpu_data[cpunum].p_nodeid = node; 36 sn_cpu_info[cpunum].p_nodeid = node;
37 cputoslice(cpunum) = get_cpu_slice(cpu); 37 cputoslice(cpunum) = get_cpu_slice(cpu);
38} 38}
39 39
@@ -176,7 +176,7 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
176 unsigned long gp = (unsigned long)task_thread_info(idle); 176 unsigned long gp = (unsigned long)task_thread_info(idle);
177 unsigned long sp = __KSTK_TOS(idle); 177 unsigned long sp = __KSTK_TOS(idle);
178 178
179 LAUNCH_SLAVE(cputonasid(cpu),cputoslice(cpu), 179 LAUNCH_SLAVE(cputonasid(cpu), cputoslice(cpu),
180 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap), 180 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap),
181 0, (void *) sp, (void *) gp); 181 0, (void *) sp, (void *) gp);
182} 182}
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 8c3c78c63ccd..b7b3479b6bce 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -40,7 +40,6 @@
40#define TICK_SIZE (tick_nsec / 1000) 40#define TICK_SIZE (tick_nsec / 1000)
41 41
42static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */ 42static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */
43static long last_rtc_update; /* Last time the rtc clock got updated */
44 43
45#if 0 44#if 0
46static int set_rtc_mmss(unsigned long nowtime) 45static int set_rtc_mmss(unsigned long nowtime)
@@ -113,23 +112,6 @@ again:
113 112
114 update_process_times(user_mode(get_irq_regs())); 113 update_process_times(user_mode(get_irq_regs()));
115 114
116 /*
117 * If we have an externally synchronized Linux clock, then update
118 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
119 * called as close as possible to when a second starts.
120 */
121 if (ntp_synced() &&
122 xtime.tv_sec > last_rtc_update + 660 &&
123 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
124 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
125 if (rtc_mips_set_time(xtime.tv_sec) == 0) {
126 last_rtc_update = xtime.tv_sec;
127 } else {
128 last_rtc_update = xtime.tv_sec - 600;
129 /* do it again in 60 s */
130 }
131 }
132
133 write_sequnlock(&xtime_lock); 115 write_sequnlock(&xtime_lock);
134 irq_exit(); 116 irq_exit();
135} 117}
@@ -141,7 +123,7 @@ again:
141#include <asm/sn/sn0/hubio.h> 123#include <asm/sn/sn0/hubio.h>
142#include <asm/pci/bridge.h> 124#include <asm/pci/bridge.h>
143 125
144static __init unsigned long get_m48t35_time(void) 126unsigned long read_persistent_clock(void)
145{ 127{
146 unsigned int year, month, date, hour, min, sec; 128 unsigned int year, month, date, hour, min, sec;
147 struct m48t35_rtc *rtc; 129 struct m48t35_rtc *rtc;
@@ -218,17 +200,23 @@ void __init plat_timer_setup(struct irqaction *irq)
218 setup_irq(irqno, &rt_irqaction); 200 setup_irq(irqno, &rt_irqaction);
219} 201}
220 202
221static cycle_t ip27_hpt_read(void) 203static cycle_t hub_rt_read(void)
222{ 204{
223 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); 205 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
224} 206}
225 207
226void __init ip27_time_init(void) 208struct clocksource ht_rt_clocksource = {
209 .name = "HUB",
210 .rating = 200,
211 .read = hub_rt_read,
212 .mask = CLOCKSOURCE_MASK(52),
213 .shift = 32,
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
215};
216
217void __init plat_time_init(void)
227{ 218{
228 clocksource_mips.read = ip27_hpt_read; 219 clocksource_register(&ht_rt_clocksource);
229 mips_hpt_frequency = CYCLES_PER_SEC;
230 xtime.tv_sec = get_m48t35_time();
231 xtime.tv_nsec = 0;
232} 220}
233 221
234void __init cpu_time_init(void) 222void __init cpu_time_init(void)
diff --git a/arch/mips/sgi-ip32/crime.c b/arch/mips/sgi-ip32/crime.c
index bff508704d03..563c614ad021 100644
--- a/arch/mips/sgi-ip32/crime.c
+++ b/arch/mips/sgi-ip32/crime.c
@@ -35,8 +35,8 @@ void __init crime_init(void)
35 id = crime->id; 35 id = crime->id;
36 rev = id & CRIME_ID_REV; 36 rev = id & CRIME_ID_REV;
37 id = (id & CRIME_ID_IDBITS) >> 4; 37 id = (id & CRIME_ID_IDBITS) >> 4;
38 printk (KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n", 38 printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
39 id, rev, field, (unsigned long) CRIME_BASE); 39 id, rev, field, (unsigned long) CRIME_BASE);
40} 40}
41 41
42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id) 42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
@@ -96,7 +96,7 @@ irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK; 96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
97 97
98 addr <<= 2; 98 addr <<= 2;
99 printk ("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat); 99 printk("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat);
100 crime->cpu_error_stat = 0; 100 crime->cpu_error_stat = 0;
101 101
102 return IRQ_HANDLED; 102 return IRQ_HANDLED;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index fb9da9acf53f..7f4b793c3df3 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -117,10 +117,18 @@ static void inline flush_mace_bus(void)
117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
119 119
120struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, 120struct irqaction memerr_irq = {
121 CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; 121 .handler = crime_memerr_intr,
122struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED, 122 .flags = IRQF_DISABLED,
123 CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; 123 .mask = CPU_MASK_NONE,
124 .name = "CRIME memory error",
125};
126struct irqaction cpuerr_irq = {
127 .handler = crime_cpuerr_intr,
128 .flags = IRQF_DISABLED,
129 .mask = CPU_MASK_NONE,
130 .name = "CRIME CPU error",
131};
124 132
125/* 133/*
126 * For interrupts wired from a single device to the CPU. Only the clock 134 * For interrupts wired from a single device to the CPU. Only the clock
@@ -140,7 +148,7 @@ static void disable_cpu_irq(unsigned int irq)
140static void end_cpu_irq(unsigned int irq) 148static void end_cpu_irq(unsigned int irq)
141{ 149{
142 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 150 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
143 enable_cpu_irq (irq); 151 enable_cpu_irq(irq);
144} 152}
145 153
146static struct irq_chip ip32_cpu_interrupt = { 154static struct irq_chip ip32_cpu_interrupt = {
@@ -281,11 +289,11 @@ static struct irq_chip ip32_macepci_interrupt = {
281 289
282static unsigned long maceisa_mask; 290static unsigned long maceisa_mask;
283 291
284static void enable_maceisa_irq (unsigned int irq) 292static void enable_maceisa_irq(unsigned int irq)
285{ 293{
286 unsigned int crime_int = 0; 294 unsigned int crime_int = 0;
287 295
288 DBG ("maceisa enable: %u\n", irq); 296 DBG("maceisa enable: %u\n", irq);
289 297
290 switch (irq) { 298 switch (irq) {
291 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 299 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
@@ -298,7 +306,7 @@ static void enable_maceisa_irq (unsigned int irq)
298 crime_int = MACE_SUPERIO_INT; 306 crime_int = MACE_SUPERIO_INT;
299 break; 307 break;
300 } 308 }
301 DBG ("crime_int %08x enabled\n", crime_int); 309 DBG("crime_int %08x enabled\n", crime_int);
302 crime_mask |= crime_int; 310 crime_mask |= crime_int;
303 crime->imask = crime_mask; 311 crime->imask = crime_mask;
304 maceisa_mask |= 1 << (irq - 33); 312 maceisa_mask |= 1 << (irq - 33);
@@ -389,15 +397,15 @@ static struct irq_chip ip32_mace_interrupt = {
389 397
390static void ip32_unknown_interrupt(void) 398static void ip32_unknown_interrupt(void)
391{ 399{
392 printk ("Unknown interrupt occurred!\n"); 400 printk("Unknown interrupt occurred!\n");
393 printk ("cp0_status: %08x\n", read_c0_status()); 401 printk("cp0_status: %08x\n", read_c0_status());
394 printk ("cp0_cause: %08x\n", read_c0_cause()); 402 printk("cp0_cause: %08x\n", read_c0_cause());
395 printk ("CRIME intr mask: %016lx\n", crime->imask); 403 printk("CRIME intr mask: %016lx\n", crime->imask);
396 printk ("CRIME intr status: %016lx\n", crime->istat); 404 printk("CRIME intr status: %016lx\n", crime->istat);
397 printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); 405 printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
398 printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 406 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
399 printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 407 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
400 printk ("MACE PCI control register: %08x\n", mace->pci.control); 408 printk("MACE PCI control register: %08x\n", mace->pci.control);
401 409
402 printk("Register dump:\n"); 410 printk("Register dump:\n");
403 show_regs(get_irq_regs()); 411 show_regs(get_irq_regs());
@@ -449,7 +457,7 @@ static void ip32_irq4(void)
449 457
450static void ip32_irq5(void) 458static void ip32_irq5(void)
451{ 459{
452 ll_timer_interrupt(IP32_R4K_TIMER_IRQ); 460 do_IRQ(IP32_R4K_TIMER_IRQ);
453} 461}
454 462
455asmlinkage void plat_irq_dispatch(void) 463asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
index 849d392a0013..ca93ecf825ae 100644
--- a/arch/mips/sgi-ip32/ip32-memory.c
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -19,7 +19,7 @@
19 19
20extern void crime_init(void); 20extern void crime_init(void);
21 21
22void __init prom_meminit (void) 22void __init prom_meminit(void)
23{ 23{
24 u64 base, size; 24 u64 base, size;
25 int bank; 25 int bank;
@@ -38,7 +38,7 @@ void __init prom_meminit (void)
38 38
39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", 39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
40 bank, base, size >> 20); 40 bank, base, size >> 20);
41 add_memory_region (base, size, BOOT_MEM_RAM); 41 add_memory_region(base, size, BOOT_MEM_RAM);
42 } 42 }
43} 43}
44 44
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index bbba066cb405..4125a5ba119e 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -62,10 +62,15 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
62} 62}
63#endif 63#endif
64 64
65unsigned long read_persistent_clock(void)
66{
67 return mc146818_get_cmos_time();
68}
69
65/* An arbitrary time; this can be decreased if reliability looks good */ 70/* An arbitrary time; this can be decreased if reliability looks good */
66#define WAIT_MS 10 71#define WAIT_MS 10
67 72
68void __init ip32_time_init(void) 73void __init plat_time_init(void)
69{ 74{
70 printk(KERN_INFO "Calibrating system timer... "); 75 printk(KERN_INFO "Calibrating system timer... ");
71 write_c0_count(0); 76 write_c0_count(0);
@@ -85,11 +90,6 @@ void __init plat_mem_setup(void)
85{ 90{
86 board_be_init = ip32_be_init; 91 board_be_init = ip32_be_init;
87 92
88 rtc_mips_get_time = mc146818_get_cmos_time;
89 rtc_mips_set_mmss = mc146818_set_rtc_mmss;
90
91 board_time_init = ip32_time_init;
92
93#ifdef CONFIG_SGI_O2MACE_ETH 93#ifdef CONFIG_SGI_O2MACE_ETH
94 { 94 {
95 char *mac = ArcGetEnvironmentVariable("eaddr"); 95 char *mac = ArcGetEnvironmentVariable("eaddr");
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index fdd7bd98fb44..e8fb880272bd 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -1,6 +1,7 @@
1config SIBYTE_SB1250 1config SIBYTE_SB1250
2 bool 2 bool
3 select HW_HAS_PCI 3 select HW_HAS_PCI
4 select IRQ_CPU
4 select SIBYTE_ENABLE_LDT_IF_PCI 5 select SIBYTE_ENABLE_LDT_IF_PCI
5 select SIBYTE_HAS_ZBUS_PROFILING 6 select SIBYTE_HAS_ZBUS_PROFILING
6 select SIBYTE_SB1xxx_SOC 7 select SIBYTE_SB1xxx_SOC
@@ -8,6 +9,7 @@ config SIBYTE_SB1250
8 9
9config SIBYTE_BCM1120 10config SIBYTE_BCM1120
10 bool 11 bool
12 select IRQ_CPU
11 select SIBYTE_BCM112X 13 select SIBYTE_BCM112X
12 select SIBYTE_HAS_ZBUS_PROFILING 14 select SIBYTE_HAS_ZBUS_PROFILING
13 select SIBYTE_SB1xxx_SOC 15 select SIBYTE_SB1xxx_SOC
@@ -15,6 +17,7 @@ config SIBYTE_BCM1120
15config SIBYTE_BCM1125 17config SIBYTE_BCM1125
16 bool 18 bool
17 select HW_HAS_PCI 19 select HW_HAS_PCI
20 select IRQ_CPU
18 select SIBYTE_BCM112X 21 select SIBYTE_BCM112X
19 select SIBYTE_HAS_ZBUS_PROFILING 22 select SIBYTE_HAS_ZBUS_PROFILING
20 select SIBYTE_SB1xxx_SOC 23 select SIBYTE_SB1xxx_SOC
@@ -22,6 +25,7 @@ config SIBYTE_BCM1125
22config SIBYTE_BCM1125H 25config SIBYTE_BCM1125H
23 bool 26 bool
24 select HW_HAS_PCI 27 select HW_HAS_PCI
28 select IRQ_CPU
25 select SIBYTE_BCM112X 29 select SIBYTE_BCM112X
26 select SIBYTE_ENABLE_LDT_IF_PCI 30 select SIBYTE_ENABLE_LDT_IF_PCI
27 select SIBYTE_HAS_ZBUS_PROFILING 31 select SIBYTE_HAS_ZBUS_PROFILING
@@ -29,12 +33,14 @@ config SIBYTE_BCM1125H
29 33
30config SIBYTE_BCM112X 34config SIBYTE_BCM112X
31 bool 35 bool
36 select IRQ_CPU
32 select SIBYTE_SB1xxx_SOC 37 select SIBYTE_SB1xxx_SOC
33 select SIBYTE_HAS_ZBUS_PROFILING 38 select SIBYTE_HAS_ZBUS_PROFILING
34 39
35config SIBYTE_BCM1x80 40config SIBYTE_BCM1x80
36 bool 41 bool
37 select HW_HAS_PCI 42 select HW_HAS_PCI
43 select IRQ_CPU
38 select SIBYTE_HAS_ZBUS_PROFILING 44 select SIBYTE_HAS_ZBUS_PROFILING
39 select SIBYTE_SB1xxx_SOC 45 select SIBYTE_SB1xxx_SOC
40 select SYS_SUPPORTS_SMP 46 select SYS_SUPPORTS_SMP
@@ -42,6 +48,7 @@ config SIBYTE_BCM1x80
42config SIBYTE_BCM1x55 48config SIBYTE_BCM1x55
43 bool 49 bool
44 select HW_HAS_PCI 50 select HW_HAS_PCI
51 select IRQ_CPU
45 select SIBYTE_SB1xxx_SOC 52 select SIBYTE_SB1xxx_SOC
46 select SIBYTE_HAS_ZBUS_PROFILING 53 select SIBYTE_HAS_ZBUS_PROFILING
47 select SYS_SUPPORTS_SMP 54 select SYS_SUPPORTS_SMP
@@ -49,6 +56,7 @@ config SIBYTE_BCM1x55
49config SIBYTE_SB1xxx_SOC 56config SIBYTE_SB1xxx_SOC
50 bool 57 bool
51 select DMA_COHERENT 58 select DMA_COHERENT
59 select IRQ_CPU
52 select SIBYTE_CFE 60 select SIBYTE_CFE
53 select SWAP_IO_SPACE 61 select SWAP_IO_SPACE
54 select SYS_SUPPORTS_32BIT_KERNEL 62 select SYS_SUPPORTS_32BIT_KERNEL
@@ -124,6 +132,7 @@ config SB1_CERR_STALL
124config SIBYTE_CFE 132config SIBYTE_CFE
125 bool "Booting from CFE" 133 bool "Booting from CFE"
126 depends on SIBYTE_SB1xxx_SOC 134 depends on SIBYTE_SB1xxx_SOC
135 select CFE
127 select SYS_HAS_EARLY_PRINTK 136 select SYS_HAS_EARLY_PRINTK
128 help 137 help
129 Make use of the CFE API for enumerating available memory, 138 Make use of the CFE API for enumerating available memory,
@@ -165,10 +174,6 @@ config SIBYTE_BW_TRACE
165 buffer activity. Raw buffer data is dumped to console, and 174 buffer activity. Raw buffer data is dumped to console, and
166 must be processed off-line. 175 must be processed off-line.
167 176
168config SIBYTE_SB1250_PROF
169 bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
170 depends on SIBYTE_SB1xxx_SOC
171
172config SIBYTE_TBPROF 177config SIBYTE_TBPROF
173 tristate "Support for ZBbus profiling" 178 tristate "Support for ZBbus profiling"
174 depends on SIBYTE_HAS_ZBUS_PROFILING 179 depends on SIBYTE_HAS_ZBUS_PROFILING
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index e729b5f30264..7aa79bf63c4a 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -289,7 +289,7 @@ int bcm1480_steal_irq(int irq)
289 if (irq >= BCM1480_NR_IRQS) 289 if (irq >= BCM1480_NR_IRQS)
290 return -EINVAL; 290 return -EINVAL;
291 291
292 spin_lock_irqsave(&desc->lock,flags); 292 spin_lock_irqsave(&desc->lock, flags);
293 /* Don't allow sharing at all for these */ 293 /* Don't allow sharing at all for these */
294 if (desc->action != NULL) 294 if (desc->action != NULL)
295 retval = -EBUSY; 295 retval = -EBUSY;
@@ -297,7 +297,7 @@ int bcm1480_steal_irq(int irq)
297 desc->action = &bcm1480_dummy_action; 297 desc->action = &bcm1480_dummy_action;
298 desc->depth = 0; 298 desc->depth = 0;
299 } 299 }
300 spin_unlock_irqrestore(&desc->lock,flags); 300 spin_unlock_irqrestore(&desc->lock, flags);
301 return 0; 301 return 0;
302} 302}
303 303
@@ -431,8 +431,8 @@ void __init arch_init_irq(void)
431 431
432#include <linux/delay.h> 432#include <linux/delay.h>
433 433
434#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 434#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
435#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 435#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
436 436
437static void bcm1480_kgdb_interrupt(void) 437static void bcm1480_kgdb_interrupt(void)
438{ 438{
@@ -450,7 +450,6 @@ static void bcm1480_kgdb_interrupt(void)
450 450
451#endif /* CONFIG_KGDB */ 451#endif /* CONFIG_KGDB */
452 452
453extern void bcm1480_timer_interrupt(void);
454extern void bcm1480_mailbox_interrupt(void); 453extern void bcm1480_mailbox_interrupt(void);
455 454
456asmlinkage void plat_irq_dispatch(void) 455asmlinkage void plat_irq_dispatch(void)
@@ -470,8 +469,16 @@ asmlinkage void plat_irq_dispatch(void)
470 else 469 else
471#endif 470#endif
472 471
473 if (pending & CAUSEF_IP4) 472 if (pending & CAUSEF_IP4) {
474 bcm1480_timer_interrupt(); 473 int cpu = smp_processor_id();
474 int irq = K_BCM1480_INT_TIMER_0 + cpu;
475
476 /* Reset the timer */
477 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
478 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
479
480 do_IRQ(irq);
481 }
475 482
476#ifdef CONFIG_SMP 483#ifdef CONFIG_SMP
477 else if (pending & CAUSEF_IP3) 484 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
index 7e1aa348b8e0..05ed92c92b69 100644
--- a/arch/mips/sibyte/bcm1480/setup.c
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -43,16 +43,49 @@ static unsigned int part_type;
43static char *soc_str; 43static char *soc_str;
44static char *pass_str; 44static char *pass_str;
45 45
46static inline int setup_bcm1x80_bcm1x55(void); 46static int __init setup_bcm1x80_bcm1x55(void)
47{
48 int ret = 0;
49
50 switch (soc_pass) {
51 case K_SYS_REVISION_BCM1480_S0:
52 periph_rev = 1;
53 pass_str = "S0 (pass1)";
54 break;
55 case K_SYS_REVISION_BCM1480_A1:
56 periph_rev = 1;
57 pass_str = "A1 (pass1)";
58 break;
59 case K_SYS_REVISION_BCM1480_A2:
60 periph_rev = 1;
61 pass_str = "A2 (pass1)";
62 break;
63 case K_SYS_REVISION_BCM1480_A3:
64 periph_rev = 1;
65 pass_str = "A3 (pass1)";
66 break;
67 case K_SYS_REVISION_BCM1480_B0:
68 periph_rev = 1;
69 pass_str = "B0 (pass2)";
70 break;
71 default:
72 printk("Unknown %s rev %x\n", soc_str, soc_pass);
73 periph_rev = 1;
74 pass_str = "Unknown Revision";
75 break;
76 }
77
78 return ret;
79}
47 80
48/* Setup code likely to be common to all SiByte platforms */ 81/* Setup code likely to be common to all SiByte platforms */
49 82
50static inline int sys_rev_decode(void) 83static int __init sys_rev_decode(void)
51{ 84{
52 int ret = 0; 85 int ret = 0;
53 86
54 switch (soc_type) { 87 switch (soc_type) {
55 case K_SYS_SOC_TYPE_BCM1x80: 88 case K_SYS_SOC_TYPE_BCM1x80:
56 if (part_type == K_SYS_PART_BCM1480) 89 if (part_type == K_SYS_PART_BCM1480)
57 soc_str = "BCM1480"; 90 soc_str = "BCM1480";
58 else if (part_type == K_SYS_PART_BCM1280) 91 else if (part_type == K_SYS_PART_BCM1280)
@@ -62,7 +95,7 @@ static inline int sys_rev_decode(void)
62 ret = setup_bcm1x80_bcm1x55(); 95 ret = setup_bcm1x80_bcm1x55();
63 break; 96 break;
64 97
65 case K_SYS_SOC_TYPE_BCM1x55: 98 case K_SYS_SOC_TYPE_BCM1x55:
66 if (part_type == K_SYS_PART_BCM1455) 99 if (part_type == K_SYS_PART_BCM1455)
67 soc_str = "BCM1455"; 100 soc_str = "BCM1455";
68 else if (part_type == K_SYS_PART_BCM1255) 101 else if (part_type == K_SYS_PART_BCM1255)
@@ -72,49 +105,16 @@ static inline int sys_rev_decode(void)
72 ret = setup_bcm1x80_bcm1x55(); 105 ret = setup_bcm1x80_bcm1x55();
73 break; 106 break;
74 107
75 default: 108 default:
76 printk("Unknown part type %x\n", part_type); 109 printk("Unknown part type %x\n", part_type);
77 ret = 1; 110 ret = 1;
78 break; 111 break;
79 } 112 }
80 return ret;
81}
82 113
83static inline int setup_bcm1x80_bcm1x55(void)
84{
85 int ret = 0;
86
87 switch (soc_pass) {
88 case K_SYS_REVISION_BCM1480_S0:
89 periph_rev = 1;
90 pass_str = "S0 (pass1)";
91 break;
92 case K_SYS_REVISION_BCM1480_A1:
93 periph_rev = 1;
94 pass_str = "A1 (pass1)";
95 break;
96 case K_SYS_REVISION_BCM1480_A2:
97 periph_rev = 1;
98 pass_str = "A2 (pass1)";
99 break;
100 case K_SYS_REVISION_BCM1480_A3:
101 periph_rev = 1;
102 pass_str = "A3 (pass1)";
103 break;
104 case K_SYS_REVISION_BCM1480_B0:
105 periph_rev = 1;
106 pass_str = "B0 (pass2)";
107 break;
108 default:
109 printk("Unknown %s rev %x\n", soc_str, soc_pass);
110 periph_rev = 1;
111 pass_str = "Unknown Revision";
112 break;
113 }
114 return ret; 114 return ret;
115} 115}
116 116
117void bcm1480_setup(void) 117void __init bcm1480_setup(void)
118{ 118{
119 uint64_t sys_rev; 119 uint64_t sys_rev;
120 int plldiv; 120 int plldiv;
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 6f3f71bf4244..40d7126cd5bf 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -25,6 +25,7 @@
25 * code to do general bookkeeping (e.g. update jiffies, run 25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.) 26 * bottom halves, etc.)
27 */ 27 */
28#include <linux/clockchips.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <linux/sched.h> 30#include <linux/sched.h>
30#include <linux/spinlock.h> 31#include <linux/spinlock.h>
@@ -55,15 +56,12 @@
55 56
56extern int bcm1480_steal_irq(int irq); 57extern int bcm1480_steal_irq(int irq);
57 58
58void bcm1480_time_init(void) 59void __init plat_time_init(void)
59{ 60{
60 int cpu = smp_processor_id(); 61 unsigned int cpu = smp_processor_id();
61 int irq = K_BCM1480_INT_TIMER_0+cpu; 62 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
62 63
63 /* Only have 4 general purpose timers */ 64 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
64 if (cpu > 3) {
65 BUG();
66 }
67 65
68 bcm1480_mask_irq(cpu, irq); 66 bcm1480_mask_irq(cpu, irq);
69 67
@@ -71,27 +69,83 @@ void bcm1480_time_init(void)
71 __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) 69 __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H)
72 + (irq<<3))); 70 + (irq<<3)));
73 71
74 /* the general purpose timer ticks at 1 Mhz independent of the rest of the system */ 72 bcm1480_unmask_irq(cpu, irq);
75 /* Disable the timer and set up the count */ 73 bcm1480_steal_irq(irq);
76 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 74}
77 __raw_writeq( 75
78 BCM1480_HPT_VALUE/HZ 76/*
79 , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 77 * The general purpose timer ticks at 1 Mhz independent if
78 * the rest of the system
79 */
80static void sibyte_set_mode(enum clock_event_mode mode,
81 struct clock_event_device *evt)
82{
83 unsigned int cpu = smp_processor_id();
84 void __iomem *timer_cfg, *timer_init;
85
86 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
87 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
88
89 switch (mode) {
90 case CLOCK_EVT_MODE_PERIODIC:
91 __raw_writeq(0, timer_cfg);
92 __raw_writeq(BCM1480_HPT_VALUE / HZ - 1, timer_init);
93 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
94 timer_cfg);
95 break;
96
97 case CLOCK_EVT_MODE_ONESHOT:
98 /* Stop the timer until we actually program a shot */
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 __raw_writeq(0, timer_cfg);
101 break;
102
103 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
104 ;
105 }
106}
107
108struct clock_event_device sibyte_hpt_clockevent = {
109 .name = "bcm1480-counter",
110 .features = CLOCK_EVT_FEAT_PERIODIC,
111 .set_mode = sibyte_set_mode,
112 .shift = 32,
113 .irq = 0,
114};
115
116static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
117{
118 struct clock_event_device *cd = &sibyte_hpt_clockevent;
119 unsigned int cpu = smp_processor_id();
80 120
81 /* Set the timer running */ 121 /* Reset the timer */
82 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 122 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
83 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 123 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
124 cd->event_handler(cd);
84 125
85 bcm1480_unmask_irq(cpu, irq); 126 return IRQ_HANDLED;
86 bcm1480_steal_irq(irq); 127}
87 /* 128
88 * This interrupt is "special" in that it doesn't use the request_irq 129static struct irqaction sibyte_counter_irqaction = {
89 * way to hook the irq line. The timer interrupt is initialized early 130 .handler = sibyte_counter_handler,
90 * enough to make this a major pain, and it's also firing enough to 131 .flags = IRQF_DISABLED | IRQF_PERCPU,
91 * warrant a bit of special case code. bcm1480_timer_interrupt is 132 .name = "timer",
92 * called directly from irq_handler.S when IP[4] is set during an 133};
93 * interrupt 134
94 */ 135/*
136 * This interrupt is "special" in that it doesn't use the request_irq
137 * way to hook the irq line. The timer interrupt is initialized early
138 * enough to make this a major pain, and it's also firing enough to
139 * warrant a bit of special case code. bcm1480_timer_interrupt is
140 * called directly from irq_handler.S when IP[4] is set during an
141 * interrupt
142 */
143static void __init sb1480_clockevent_init(void)
144{
145 unsigned int cpu = smp_processor_id();
146 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
147
148 setup_irq(irq, &sibyte_counter_irqaction);
95} 149}
96 150
97void bcm1480_timer_interrupt(void) 151void bcm1480_timer_interrupt(void)
@@ -103,18 +157,7 @@ void bcm1480_timer_interrupt(void)
103 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 157 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
104 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 158 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
105 159
106 if (cpu == 0) { 160 ll_timer_interrupt(irq);
107 /*
108 * CPU 0 handles the global timer interrupt job
109 */
110 ll_timer_interrupt(irq);
111 }
112 else {
113 /*
114 * other CPUs should just do profiling and process accounting
115 */
116 ll_local_timer_interrupt(irq);
117 }
118} 161}
119 162
120static cycle_t bcm1480_hpt_read(void) 163static cycle_t bcm1480_hpt_read(void)
@@ -129,4 +172,5 @@ void __init bcm1480_hpt_setup(void)
129{ 172{
130 clocksource_mips.read = bcm1480_hpt_read; 173 clocksource_mips.read = bcm1480_hpt_read;
131 mips_hpt_frequency = BCM1480_HPT_VALUE; 174 mips_hpt_frequency = BCM1480_HPT_VALUE;
175 sb1480_clockevent_init();
132} 176}
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
index 059d84a1d8a8..a1214937b705 100644
--- a/arch/mips/sibyte/cfe/Makefile
+++ b/arch/mips/sibyte/cfe/Makefile
@@ -1,3 +1,3 @@
1lib-y = cfe_api.o setup.o 1lib-y = setup.o
2lib-$(CONFIG_SMP) += smp.o 2lib-$(CONFIG_SMP) += smp.o
3lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o 3lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
index 4cec9d798d2f..81e3d54376e9 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/cfe/console.c
@@ -4,8 +4,8 @@
4 4
5#include <asm/sibyte/board.h> 5#include <asm/sibyte/board.h>
6 6
7#include "cfe_api.h" 7#include <asm/fw/cfe/cfe_api.h>
8#include "cfe_error.h" 8#include <asm/fw/cfe/cfe_error.h>
9 9
10extern int cfe_cons_handle; 10extern int cfe_cons_handle;
11 11
@@ -14,7 +14,7 @@ static void cfe_console_write(struct console *cons, const char *str,
14{ 14{
15 int i, last, written; 15 int i, last, written;
16 16
17 for (i=0,last=0; i<count; i++) { 17 for (i=0, last=0; i<count; i++) {
18 if (!str[i]) 18 if (!str[i])
19 /* XXXKW can/should this ever happen? */ 19 /* XXXKW can/should this ever happen? */
20 return; 20 return;
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index 51898dd1304a..dbd6e6fdd3f9 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -29,8 +29,8 @@
29#include <asm/reboot.h> 29#include <asm/reboot.h>
30#include <asm/sibyte/board.h> 30#include <asm/sibyte/board.h>
31 31
32#include "cfe_api.h" 32#include <asm/fw/cfe/cfe_api.h>
33#include "cfe_error.h" 33#include <asm/fw/cfe/cfe_error.h>
34 34
35/* Max ram addressable in 32-bit segments */ 35/* Max ram addressable in 32-bit segments */
36#ifdef CONFIG_64BIT 36#ifdef CONFIG_64BIT
@@ -309,7 +309,7 @@ void __init prom_init(void)
309 } 309 }
310 310
311#ifdef CONFIG_KGDB 311#ifdef CONFIG_KGDB
312 if ((arg = strstr(arcs_cmdline,"kgdb=duart")) != NULL) 312 if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
313 kgdb_port = (arg[10] == '0') ? 0 : 1; 313 kgdb_port = (arg[10] == '0') ? 0 : 1;
314 else 314 else
315 kgdb_port = 1; 315 kgdb_port = 1;
@@ -339,7 +339,6 @@ void __init prom_init(void)
339 /* Not sure this is needed, but it's the safe way. */ 339 /* Not sure this is needed, but it's the safe way. */
340 arcs_cmdline[CL_SIZE-1] = 0; 340 arcs_cmdline[CL_SIZE-1] = 0;
341 341
342 mips_machgroup = MACH_GROUP_SIBYTE;
343 prom_meminit(); 342 prom_meminit();
344} 343}
345 344
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
index 5de4cff9d14a..534a62912f21 100644
--- a/arch/mips/sibyte/cfe/smp.c
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -21,8 +21,8 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <asm/processor.h> 22#include <asm/processor.h>
23 23
24#include "cfe_api.h" 24#include <asm/fw/cfe/cfe_api.h>
25#include "cfe_error.h" 25#include <asm/fw/cfe/cfe_error.h>
26 26
27/* 27/*
28 * Use CFE to find out how many CPUs are available, setting up 28 * Use CFE to find out how many CPUs are available, setting up
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index f8ae30066a05..48a91b9e5870 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -2,5 +2,4 @@ obj-y :=
2 2
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o 3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
4 4
5EXTRA_AFLAGS := $(CFLAGS)
6EXTRA_CFLAGS += -Werror 5EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 4fcdaa8ba514..63b444eaf01e 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -276,8 +276,8 @@ static int sbprof_zbprof_start(struct file *filp)
276 sbp.next_tb_sample = 0; 276 sbp.next_tb_sample = 0;
277 filp->f_pos = 0; 277 filp->f_pos = 0;
278 278
279 err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, 279 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
280 DEVNAME " trace freeze", &sbp); 280 DEVNAME " trace freeze", &sbp);
281 if (err) 281 if (err)
282 return -EBUSY; 282 return -EBUSY;
283 283
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index ad593a6c20be..7659174819c6 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -28,6 +28,7 @@
28#include <asm/errno.h> 28#include <asm/errno.h>
29#include <asm/signal.h> 29#include <asm/signal.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/time.h>
31#include <asm/io.h> 32#include <asm/io.h>
32 33
33#include <asm/sibyte/sb1250_regs.h> 34#include <asm/sibyte/sb1250_regs.h>
@@ -258,7 +259,7 @@ int sb1250_steal_irq(int irq)
258 if (irq >= SB1250_NR_IRQS) 259 if (irq >= SB1250_NR_IRQS)
259 return -EINVAL; 260 return -EINVAL;
260 261
261 spin_lock_irqsave(&desc->lock,flags); 262 spin_lock_irqsave(&desc->lock, flags);
262 /* Don't allow sharing at all for these */ 263 /* Don't allow sharing at all for these */
263 if (desc->action != NULL) 264 if (desc->action != NULL)
264 retval = -EBUSY; 265 retval = -EBUSY;
@@ -266,7 +267,7 @@ int sb1250_steal_irq(int irq)
266 desc->action = &sb1250_dummy_action; 267 desc->action = &sb1250_dummy_action;
267 desc->depth = 0; 268 desc->depth = 0;
268 } 269 }
269 spin_unlock_irqrestore(&desc->lock,flags); 270 spin_unlock_irqrestore(&desc->lock, flags);
270 return 0; 271 return 0;
271} 272}
272 273
@@ -380,8 +381,8 @@ void __init arch_init_irq(void)
380 381
381#include <linux/delay.h> 382#include <linux/delay.h>
382 383
383#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 384#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
384#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 385#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
385 386
386static void sb1250_kgdb_interrupt(void) 387static void sb1250_kgdb_interrupt(void)
387{ 388{
@@ -399,18 +400,45 @@ static void sb1250_kgdb_interrupt(void)
399 400
400#endif /* CONFIG_KGDB */ 401#endif /* CONFIG_KGDB */
401 402
402extern void sb1250_timer_interrupt(void); 403static inline void sb1250_timer_interrupt(void)
404{
405 int cpu = smp_processor_id();
406 int irq = K_INT_TIMER_0 + cpu;
407
408 irq_enter();
409 kstat_this_cpu.irqs[irq]++;
410
411 write_seqlock(&xtime_lock);
412
413 /* ACK interrupt */
414 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
415 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
416
417 /*
418 * call the generic timer interrupt handling
419 */
420 do_timer(1);
421
422 write_sequnlock(&xtime_lock);
423
424 /*
425 * In UP mode, we call local_timer_interrupt() to do profiling
426 * and process accouting.
427 *
428 * In SMP mode, local_timer_interrupt() is invoked by appropriate
429 * low-level local timer interrupt handler.
430 */
431 local_timer_interrupt(irq);
432
433 irq_exit();
434}
435
403extern void sb1250_mailbox_interrupt(void); 436extern void sb1250_mailbox_interrupt(void);
404 437
405asmlinkage void plat_irq_dispatch(void) 438asmlinkage void plat_irq_dispatch(void)
406{ 439{
407 unsigned int pending; 440 unsigned int pending;
408 441
409#ifdef CONFIG_SIBYTE_SB1250_PROF
410 /* Set compare to count to silence count/compare timer interrupts */
411 write_c0_compare(read_c0_count());
412#endif
413
414 /* 442 /*
415 * What a pain. We have to be really careful saving the upper 32 bits 443 * What a pain. We have to be really careful saving the upper 32 bits
416 * of any * register across function calls if we don't want them 444 * of any * register across function calls if we don't want them
@@ -423,13 +451,9 @@ asmlinkage void plat_irq_dispatch(void)
423 451
424 pending = read_c0_cause() & read_c0_status() & ST0_IM; 452 pending = read_c0_cause() & read_c0_status() & ST0_IM;
425 453
426#ifdef CONFIG_SIBYTE_SB1250_PROF 454 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
427 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 455 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
428 sbprof_cpu_intr(); 456 else if (pending & CAUSEF_IP4)
429 else
430#endif
431
432 if (pending & CAUSEF_IP4)
433 sb1250_timer_interrupt(); 457 sb1250_timer_interrupt();
434 458
435#ifdef CONFIG_SMP 459#ifdef CONFIG_SMP
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
index 257c4e674353..cf8f6b3de86c 100644
--- a/arch/mips/sibyte/sb1250/prom.c
+++ b/arch/mips/sibyte/sb1250/prom.c
@@ -66,7 +66,7 @@ static void prom_linux_exit(void)
66{ 66{
67#ifdef CONFIG_SMP 67#ifdef CONFIG_SMP
68 if (smp_processor_id()) { 68 if (smp_processor_id()) {
69 smp_call_function(prom_cpu0_exit,NULL,1,1); 69 smp_call_function(prom_cpu0_exit, NULL, 1, 1);
70 } 70 }
71#endif 71#endif
72 while(1); 72 while(1);
@@ -83,7 +83,6 @@ void __init prom_init(void)
83 83
84 strcpy(arcs_cmdline, "root=/dev/ram0 "); 84 strcpy(arcs_cmdline, "root=/dev/ram0 ");
85 85
86 mips_machgroup = MACH_GROUP_SIBYTE;
87 prom_meminit(); 86 prom_meminit();
88} 87}
89 88
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 2d5c6d8b41f2..0444da1e23c2 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -40,43 +40,6 @@ static char *soc_str;
40static char *pass_str; 40static char *pass_str;
41static unsigned int war_pass; /* XXXKW don't overload PASS defines? */ 41static unsigned int war_pass; /* XXXKW don't overload PASS defines? */
42 42
43static inline int setup_bcm1250(void);
44static inline int setup_bcm112x(void);
45
46/* Setup code likely to be common to all SiByte platforms */
47
48static int __init sys_rev_decode(void)
49{
50 int ret = 0;
51
52 war_pass = soc_pass;
53 switch (soc_type) {
54 case K_SYS_SOC_TYPE_BCM1250:
55 case K_SYS_SOC_TYPE_BCM1250_ALT:
56 case K_SYS_SOC_TYPE_BCM1250_ALT2:
57 soc_str = "BCM1250";
58 ret = setup_bcm1250();
59 break;
60 case K_SYS_SOC_TYPE_BCM1120:
61 soc_str = "BCM1120";
62 ret = setup_bcm112x();
63 break;
64 case K_SYS_SOC_TYPE_BCM1125:
65 soc_str = "BCM1125";
66 ret = setup_bcm112x();
67 break;
68 case K_SYS_SOC_TYPE_BCM1125H:
69 soc_str = "BCM1125H";
70 ret = setup_bcm112x();
71 break;
72 default:
73 printk("Unknown SOC type %x\n", soc_type);
74 ret = 1;
75 break;
76 }
77 return ret;
78}
79
80static int __init setup_bcm1250(void) 43static int __init setup_bcm1250(void)
81{ 44{
82 int ret = 0; 45 int ret = 0;
@@ -120,6 +83,7 @@ static int __init setup_bcm1250(void)
120 } 83 }
121 break; 84 break;
122 } 85 }
86
123 return ret; 87 return ret;
124} 88}
125 89
@@ -158,6 +122,42 @@ static int __init setup_bcm112x(void)
158 printk("Unknown %s rev %x\n", soc_str, soc_pass); 122 printk("Unknown %s rev %x\n", soc_str, soc_pass);
159 ret = 1; 123 ret = 1;
160 } 124 }
125
126 return ret;
127}
128
129/* Setup code likely to be common to all SiByte platforms */
130
131static int __init sys_rev_decode(void)
132{
133 int ret = 0;
134
135 war_pass = soc_pass;
136 switch (soc_type) {
137 case K_SYS_SOC_TYPE_BCM1250:
138 case K_SYS_SOC_TYPE_BCM1250_ALT:
139 case K_SYS_SOC_TYPE_BCM1250_ALT2:
140 soc_str = "BCM1250";
141 ret = setup_bcm1250();
142 break;
143 case K_SYS_SOC_TYPE_BCM1120:
144 soc_str = "BCM1120";
145 ret = setup_bcm112x();
146 break;
147 case K_SYS_SOC_TYPE_BCM1125:
148 soc_str = "BCM1125";
149 ret = setup_bcm112x();
150 break;
151 case K_SYS_SOC_TYPE_BCM1125H:
152 soc_str = "BCM1125H";
153 ret = setup_bcm112x();
154 break;
155 default:
156 printk("Unknown SOC type %x\n", soc_type);
157 ret = 1;
158 break;
159 }
160
161 return ret; 161 return ret;
162} 162}
163 163
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 2efffe15ff23..38199ad8fc54 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -25,6 +25,7 @@
25 * code to do general bookkeeping (e.g. update jiffies, run 25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.) 26 * bottom halves, etc.)
27 */ 27 */
28#include <linux/clockchips.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <linux/sched.h> 30#include <linux/sched.h>
30#include <linux/spinlock.h> 31#include <linux/spinlock.h>
@@ -71,16 +72,158 @@ void __init sb1250_hpt_setup(void)
71 } 72 }
72} 73}
73 74
75/*
76 * The general purpose timer ticks at 1 Mhz independent if
77 * the rest of the system
78 */
79static void sibyte_set_mode(enum clock_event_mode mode,
80 struct clock_event_device *evt)
81{
82 unsigned int cpu = smp_processor_id();
83 void __iomem *timer_cfg, *timer_init;
84
85 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
86 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
74 87
75void sb1250_time_init(void) 88 switch(mode) {
89 case CLOCK_EVT_MODE_PERIODIC:
90 __raw_writeq(0, timer_cfg);
91 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
92 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
93 timer_cfg);
94 break;
95
96 case CLOCK_EVT_MODE_ONESHOT:
97 /* Stop the timer until we actually program a shot */
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 __raw_writeq(0, timer_cfg);
100 break;
101
102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
103 ;
104 }
105}
106
107static int
108sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
76{ 109{
77 int cpu = smp_processor_id(); 110 unsigned int cpu = smp_processor_id();
78 int irq = K_INT_TIMER_0+cpu; 111 void __iomem *timer_cfg, *timer_init;
79 112
80 /* Only have 4 general purpose timers, and we use last one as hpt */ 113 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
81 if (cpu > 2) { 114 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
82 BUG(); 115
116 __raw_writeq(0, timer_cfg);
117 __raw_writeq(delta, timer_init);
118 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
119
120 return 0;
121}
122
123struct clock_event_device sibyte_hpt_clockevent = {
124 .name = "sb1250-counter",
125 .features = CLOCK_EVT_FEAT_PERIODIC,
126 .set_mode = sibyte_set_mode,
127 .set_next_event = sibyte_next_event,
128 .shift = 32,
129 .irq = 0,
130};
131
132static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
133{
134 struct clock_event_device *cd = &sibyte_hpt_clockevent;
135
136 cd->event_handler(cd);
137
138 return IRQ_HANDLED;
139}
140
141static struct irqaction sibyte_irqaction = {
142 .handler = sibyte_counter_handler,
143 .flags = IRQF_DISABLED | IRQF_PERCPU,
144 .name = "timer",
145};
146
147/*
148 * The general purpose timer ticks at 1 Mhz independent if
149 * the rest of the system
150 */
151static void sibyte_set_mode(enum clock_event_mode mode,
152 struct clock_event_device *evt)
153{
154 unsigned int cpu = smp_processor_id();
155 void __iomem *timer_cfg, *timer_init;
156
157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
159
160 switch (mode) {
161 case CLOCK_EVT_MODE_PERIODIC:
162 __raw_writeq(0, timer_cfg);
163 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
164 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
165 timer_cfg);
166 break;
167
168 case CLOCK_EVT_MODE_ONESHOT:
169 /* Stop the timer until we actually program a shot */
170 case CLOCK_EVT_MODE_SHUTDOWN:
171 __raw_writeq(0, timer_cfg);
172 break;
173
174 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
175 ;
83 } 176 }
177}
178
179static int
180sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
181{
182 unsigned int cpu = smp_processor_id();
183 void __iomem *timer_cfg, *timer_init;
184
185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
187
188 __raw_writeq(0, timer_cfg);
189 __raw_writeq(delta, timer_init);
190 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
191
192 return 0;
193}
194
195struct clock_event_device sibyte_hpt_clockevent = {
196 .name = "sb1250-counter",
197 .features = CLOCK_EVT_FEAT_PERIODIC,
198 .set_mode = sibyte_set_mode,
199 .set_next_event = sibyte_next_event,
200 .shift = 32,
201 .irq = 0,
202};
203
204static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
205{
206 struct clock_event_device *cd = &sibyte_hpt_clockevent;
207
208 cd->event_handler(cd);
209
210 return IRQ_HANDLED;
211}
212
213static struct irqaction sibyte_irqaction = {
214 .handler = sibyte_counter_handler,
215 .flags = IRQF_DISABLED | IRQF_PERCPU,
216 .name = "timer",
217};
218
219static void __init sb1250_clockevent_init(void)
220{
221 struct clock_event_device *cd = &sibyte_hpt_clockevent;
222 unsigned int cpu = smp_processor_id();
223 int irq = K_INT_TIMER_0 + cpu;
224
225 /* Only have 4 general purpose timers, and we use last one as hpt */
226 BUG_ON(cpu > 2);
84 227
85 sb1250_mask_irq(cpu, irq); 228 sb1250_mask_irq(cpu, irq);
86 229
@@ -88,24 +231,11 @@ void sb1250_time_init(void)
88 __raw_writeq(IMR_IP4_VAL, 231 __raw_writeq(IMR_IP4_VAL,
89 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + 232 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
90 (irq << 3))); 233 (irq << 3)));
91 234 cd->cpumask = cpumask_of_cpu(0);
92 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
93 /* Disable the timer and set up the count */
94 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
95#ifdef CONFIG_SIMULATION
96 __raw_writeq((50000 / HZ) - 1,
97 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
98#else
99 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
100 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
101#endif
102
103 /* Set the timer running */
104 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
105 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
106 235
107 sb1250_unmask_irq(cpu, irq); 236 sb1250_unmask_irq(cpu, irq);
108 sb1250_steal_irq(irq); 237 sb1250_steal_irq(irq);
238
109 /* 239 /*
110 * This interrupt is "special" in that it doesn't use the request_irq 240 * This interrupt is "special" in that it doesn't use the request_irq
111 * way to hook the irq line. The timer interrupt is initialized early 241 * way to hook the irq line. The timer interrupt is initialized early
@@ -114,29 +244,15 @@ void sb1250_time_init(void)
114 * called directly from irq_handler.S when IP[4] is set during an 244 * called directly from irq_handler.S when IP[4] is set during an
115 * interrupt 245 * interrupt
116 */ 246 */
247 setup_irq(irq, &sibyte_irqaction);
248
249 clockevents_register_device(cd);
117} 250}
118 251
119void sb1250_timer_interrupt(void) 252void __init plat_time_init(void)
120{ 253{
121 int cpu = smp_processor_id(); 254 sb1250_clocksource_init();
122 int irq = K_INT_TIMER_0 + cpu; 255 sb1250_clockevent_init();
123
124 /* ACK interrupt */
125 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
126 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
127
128 if (cpu == 0) {
129 /*
130 * CPU 0 handles the global timer interrupt job
131 */
132 ll_timer_interrupt(irq);
133 }
134 else {
135 /*
136 * other CPUs should just do profiling and process accounting
137 */
138 ll_local_timer_interrupt(irq);
139 }
140} 256}
141 257
142/* 258/*
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
index 75ce14c8eb69..b97ae3048482 100644
--- a/arch/mips/sibyte/swarm/dbg_io.c
+++ b/arch/mips/sibyte/swarm/dbg_io.c
@@ -37,8 +37,8 @@ static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
37/* -------------------- END OF CONFIG --------------------- */ 37/* -------------------- END OF CONFIG --------------------- */
38extern int kgdb_port; 38extern int kgdb_port;
39 39
40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
42 42
43void putDebugChar(unsigned char c); 43void putDebugChar(unsigned char c);
44unsigned char getDebugChar(void); 44unsigned char getDebugChar(void);
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
index c13914bdda59..26fbff4c15b1 100644
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -146,7 +146,8 @@ int m41t81_set_time(unsigned long t)
146 struct rtc_time tm; 146 struct rtc_time tm;
147 unsigned long flags; 147 unsigned long flags;
148 148
149 to_tm(t, &tm); 149 /* Note we don't care about the century */
150 rtc_time_to_tm(t, &tm);
150 151
151 /* 152 /*
152 * Note the write order matters as it ensures the correctness. 153 * Note the write order matters as it ensures the correctness.
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
index f4a178836415..ff3e5dabb348 100644
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -115,7 +115,8 @@ int xicor_set_time(unsigned long t)
115 int tmp; 115 int tmp;
116 unsigned long flags; 116 unsigned long flags;
117 117
118 to_tm(t, &tm); 118 rtc_time_to_tm(t, &tm);
119 tm.tm_year += 1900;
119 120
120 spin_lock_irqsave(&rtc_lock, flags); 121 spin_lock_irqsave(&rtc_lock, flags);
121 /* unlock writes to the CCR */ 122 /* unlock writes to the CCR */
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 83572d8f3e14..8b3ef0e4cd55 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -69,7 +69,7 @@ const char *get_system_type(void)
69 return "SiByte " SIBYTE_BOARD_NAME; 69 return "SiByte " SIBYTE_BOARD_NAME;
70} 70}
71 71
72void __init swarm_time_init(void) 72void __init plat_time_init(void)
73{ 73{
74#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 74#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
75 /* Setup HPT */ 75 /* Setup HPT */
@@ -104,6 +104,44 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
104 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); 104 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
105} 105}
106 106
107enum swarm_rtc_type {
108 RTC_NONE,
109 RTC_XICOR,
110 RTC_M4LT81
111};
112
113enum swarm_rtc_type swarm_rtc_type;
114
115unsigned long read_persistent_clock(void)
116{
117 switch (swarm_rtc_type) {
118 case RTC_XICOR:
119 return xicor_get_time();
120
121 case RTC_M4LT81:
122 return m41t81_get_time();
123
124 case RTC_NONE:
125 default:
126 return mktime(2000, 1, 1, 0, 0, 0);
127 }
128}
129
130int rtc_mips_set_time(unsigned long sec)
131{
132 switch (swarm_rtc_type) {
133 case RTC_XICOR:
134 return xicor_set_time(sec);
135
136 case RTC_M4LT81:
137 return m41t81_set_time(sec);
138
139 case RTC_NONE:
140 default:
141 return -1;
142 }
143}
144
107void __init plat_mem_setup(void) 145void __init plat_mem_setup(void)
108{ 146{
109#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 147#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
@@ -116,20 +154,12 @@ void __init plat_mem_setup(void)
116 154
117 panic_timeout = 5; /* For debug. */ 155 panic_timeout = 5; /* For debug. */
118 156
119 board_time_init = swarm_time_init;
120 board_be_handler = swarm_be_handler; 157 board_be_handler = swarm_be_handler;
121 158
122 if (xicor_probe()) { 159 if (xicor_probe())
123 printk("swarm setup: Xicor 1241 RTC detected.\n"); 160 swarm_rtc_type = RTC_XICOR;
124 rtc_mips_get_time = xicor_get_time; 161 if (m41t81_probe())
125 rtc_mips_set_time = xicor_set_time; 162 swarm_rtc_type = RTC_M4LT81;
126 }
127
128 if (m41t81_probe()) {
129 printk("swarm setup: M41T81 RTC detected.\n");
130 rtc_mips_get_time = m41t81_get_time;
131 rtc_mips_set_time = m41t81_set_time;
132 }
133 163
134 printk("This kernel optimized for " 164 printk("This kernel optimized for "
135#ifdef CONFIG_SIMULATION 165#ifdef CONFIG_SIMULATION
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index acc9ba76c1a9..b74607599971 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -127,7 +127,7 @@ static u32 a20r_ack_hwint(void)
127{ 127{
128 u32 status = read_c0_status(); 128 u32 status = read_c0_status();
129 129
130 write_c0_status (status | 0x00010000); 130 write_c0_status(status | 0x00010000);
131 asm volatile( 131 asm volatile(
132 " .set push \n" 132 " .set push \n"
133 " .set noat \n" 133 " .set noat \n"
@@ -195,7 +195,7 @@ static void a20r_hwint(void)
195 u32 cause, status; 195 u32 cause, status;
196 int irq; 196 int irq;
197 197
198 clear_c0_status (IE_IRQ0); 198 clear_c0_status(IE_IRQ0);
199 status = a20r_ack_hwint(); 199 status = a20r_ack_hwint();
200 cause = read_c0_cause(); 200 cause = read_c0_cause();
201 201
@@ -213,7 +213,7 @@ void __init sni_a20r_irq_init(void)
213 set_irq_chip(i, &a20r_irq_type); 213 set_irq_chip(i, &a20r_irq_type);
214 sni_hwint = a20r_hwint; 214 sni_hwint = a20r_hwint;
215 change_c0_status(ST0_IM, IE_IRQ0); 215 change_c0_status(ST0_IM, IE_IRQ0);
216 setup_irq (SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); 216 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
217} 217}
218 218
219void sni_a20r_init(void) 219void sni_a20r_init(void)
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 44b1ae62aa4a..39bb15f1f2a6 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -284,9 +284,9 @@ static void sni_pcimt_hwint(void)
284 u32 pending = read_c0_cause() & read_c0_status(); 284 u32 pending = read_c0_cause() & read_c0_status();
285 285
286 if (pending & C_IRQ5) 286 if (pending & C_IRQ5)
287 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 287 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
288 else if (pending & C_IRQ4) 288 else if (pending & C_IRQ4)
289 do_IRQ (MIPS_CPU_IRQ_BASE + 6); 289 do_IRQ(MIPS_CPU_IRQ_BASE + 6);
290 else if (pending & C_IRQ3) 290 else if (pending & C_IRQ3)
291 pcimt_hwint3(); 291 pcimt_hwint3();
292 else if (pending & C_IRQ1) 292 else if (pending & C_IRQ1)
@@ -313,7 +313,6 @@ void __init sni_pcimt_init(void)
313{ 313{
314 sni_pcimt_detect(); 314 sni_pcimt_detect();
315 sni_pcimt_sc_init(); 315 sni_pcimt_sc_init();
316 board_time_init = sni_cpu_time_init;
317 ioport_resource.end = sni_io_resource.end; 316 ioport_resource.end = sni_io_resource.end;
318#ifdef CONFIG_PCI 317#ifdef CONFIG_PCI
319 PCIBIOS_MIN_IO = 0x9000; 318 PCIBIOS_MIN_IO = 0x9000;
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 2480c478dcbd..416f397c768b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -188,8 +188,8 @@ static void pcit_hwint1(void)
188 irq = ffs((pending >> 16) & 0x7f); 188 irq = ffs((pending >> 16) & 0x7f);
189 189
190 if (likely(irq > 0)) 190 if (likely(irq > 0))
191 do_IRQ (irq + SNI_PCIT_INT_START - 1); 191 do_IRQ(irq + SNI_PCIT_INT_START - 1);
192 set_c0_status (IE_IRQ1); 192 set_c0_status(IE_IRQ1);
193} 193}
194 194
195static void pcit_hwint0(void) 195static void pcit_hwint0(void)
@@ -201,8 +201,8 @@ static void pcit_hwint0(void)
201 irq = ffs((pending >> 16) & 0x3f); 201 irq = ffs((pending >> 16) & 0x3f);
202 202
203 if (likely(irq > 0)) 203 if (likely(irq > 0))
204 do_IRQ (irq + SNI_PCIT_INT_START - 1); 204 do_IRQ(irq + SNI_PCIT_INT_START - 1);
205 set_c0_status (IE_IRQ0); 205 set_c0_status(IE_IRQ0);
206} 206}
207 207
208static void sni_pcit_hwint(void) 208static void sni_pcit_hwint(void)
@@ -212,11 +212,11 @@ static void sni_pcit_hwint(void)
212 if (pending & C_IRQ1) 212 if (pending & C_IRQ1)
213 pcit_hwint1(); 213 pcit_hwint1();
214 else if (pending & C_IRQ2) 214 else if (pending & C_IRQ2)
215 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 215 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
216 else if (pending & C_IRQ3) 216 else if (pending & C_IRQ3)
217 do_IRQ (MIPS_CPU_IRQ_BASE + 5); 217 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
218 else if (pending & C_IRQ5) 218 else if (pending & C_IRQ5)
219 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 219 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
220} 220}
221 221
222static void sni_pcit_hwint_cplus(void) 222static void sni_pcit_hwint_cplus(void)
@@ -226,13 +226,13 @@ static void sni_pcit_hwint_cplus(void)
226 if (pending & C_IRQ0) 226 if (pending & C_IRQ0)
227 pcit_hwint0(); 227 pcit_hwint0();
228 else if (pending & C_IRQ1) 228 else if (pending & C_IRQ1)
229 do_IRQ (MIPS_CPU_IRQ_BASE + 3); 229 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
230 else if (pending & C_IRQ2) 230 else if (pending & C_IRQ2)
231 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 231 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
232 else if (pending & C_IRQ3) 232 else if (pending & C_IRQ3)
233 do_IRQ (MIPS_CPU_IRQ_BASE + 5); 233 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
234 else if (pending & C_IRQ5) 234 else if (pending & C_IRQ5)
235 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 235 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
236} 236}
237 237
238void __init sni_pcit_irq_init(void) 238void __init sni_pcit_irq_init(void)
@@ -245,7 +245,7 @@ void __init sni_pcit_irq_init(void)
245 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 245 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
246 sni_hwint = sni_pcit_hwint; 246 sni_hwint = sni_pcit_hwint;
247 change_c0_status(ST0_IM, IE_IRQ1); 247 change_c0_status(ST0_IM, IE_IRQ1);
248 setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); 248 setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
249} 249}
250 250
251void __init sni_pcit_cplus_irq_init(void) 251void __init sni_pcit_cplus_irq_init(void)
@@ -258,12 +258,11 @@ void __init sni_pcit_cplus_irq_init(void)
258 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; 258 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
259 sni_hwint = sni_pcit_hwint_cplus; 259 sni_hwint = sni_pcit_hwint_cplus;
260 change_c0_status(ST0_IM, IE_IRQ0); 260 change_c0_status(ST0_IM, IE_IRQ0);
261 setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); 261 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
262} 262}
263 263
264void __init sni_pcit_init(void) 264void __init sni_pcit_init(void)
265{ 265{
266 board_time_init = sni_cpu_time_init;
267 ioport_resource.end = sni_io_resource.end; 266 ioport_resource.end = sni_io_resource.end;
268#ifdef CONFIG_PCI 267#ifdef CONFIG_PCI
269 PCIBIOS_MIN_IO = 0x9000; 268 PCIBIOS_MIN_IO = 0x9000;
diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c
index 38b6a97a31b5..79f8d70f48c9 100644
--- a/arch/mips/sni/reset.c
+++ b/arch/mips/sni/reset.c
@@ -35,7 +35,7 @@ void sni_machine_restart(char *command)
35 kb_wait(); 35 kb_wait();
36 for (j = 0; j < 100000 ; j++) 36 for (j = 0; j < 100000 ; j++)
37 /* nothing */; 37 /* nothing */;
38 outb_p(0xfe,0x64); /* pulse reset low */ 38 outb_p(0xfe, 0x64); /* pulse reset low */
39 } 39 }
40 } 40 }
41} 41}
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 28a11d8605ce..67b061eef6cd 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -162,16 +162,16 @@ static void sni_rm200_hwint(void)
162 int irq; 162 int irq;
163 163
164 if (pending & C_IRQ5) 164 if (pending & C_IRQ5)
165 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 165 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
166 else if (pending & C_IRQ0) { 166 else if (pending & C_IRQ0) {
167 clear_c0_status (IE_IRQ0); 167 clear_c0_status(IE_IRQ0);
168 mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f; 168 mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f;
169 stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14; 169 stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14;
170 irq = ffs(stat & mask & 0x1f); 170 irq = ffs(stat & mask & 0x1f);
171 171
172 if (likely(irq > 0)) 172 if (likely(irq > 0))
173 do_IRQ (irq + SNI_RM200_INT_START - 1); 173 do_IRQ(irq + SNI_RM200_INT_START - 1);
174 set_c0_status (IE_IRQ0); 174 set_c0_status(IE_IRQ0);
175 } 175 }
176} 176}
177 177
@@ -187,12 +187,11 @@ void __init sni_rm200_irq_init(void)
187 set_irq_chip(i, &rm200_irq_type); 187 set_irq_chip(i, &rm200_irq_type);
188 sni_hwint = sni_rm200_hwint; 188 sni_hwint = sni_rm200_hwint;
189 change_c0_status(ST0_IM, IE_IRQ0); 189 change_c0_status(ST0_IM, IE_IRQ0);
190 setup_irq (SNI_RM200_INT_START + 0, &sni_isa_irq); 190 setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq);
191} 191}
192 192
193void __init sni_rm200_init(void) 193void __init sni_rm200_init(void)
194{ 194{
195 set_io_port_base(SNI_PORT_BASE + 0x02000000); 195 set_io_port_base(SNI_PORT_BASE + 0x02000000);
196 ioport_resource.end += 0x02000000; 196 ioport_resource.end += 0x02000000;
197 board_time_init = sni_cpu_time_init;
198} 197}
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 6edbb3051c82..e8b26bdee24c 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -15,7 +15,7 @@
15#include <linux/screen_info.h> 15#include <linux/screen_info.h>
16 16
17#ifdef CONFIG_ARC 17#ifdef CONFIG_ARC
18#include <asm/arc/types.h> 18#include <asm/fw/arc/types.h>
19#include <asm/sgialib.h> 19#include <asm/sgialib.h>
20#endif 20#endif
21 21
@@ -106,11 +106,11 @@ static void __devinit quirk_cirrus_ram_size(struct pci_dev *dev)
106 * need to do it here, otherwise we get screen corruption 106 * need to do it here, otherwise we get screen corruption
107 * on older Cirrus chips 107 * on older Cirrus chips
108 */ 108 */
109 pci_read_config_word (dev, PCI_COMMAND, &cmd); 109 pci_read_config_word(dev, PCI_COMMAND, &cmd);
110 if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) 110 if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))
111 == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) { 111 == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
112 vga_wseq (NULL, CL_SEQR6, 0x12); /* unlock all extension registers */ 112 vga_wseq(NULL, CL_SEQR6, 0x12); /* unlock all extension registers */
113 vga_wseq (NULL, CL_SEQRF, 0x18); 113 vga_wseq(NULL, CL_SEQRF, 0x18);
114 } 114 }
115} 115}
116 116
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
index db544a6e23f3..eff4b89d7b75 100644
--- a/arch/mips/sni/sniprom.c
+++ b/arch/mips/sni/sniprom.c
@@ -45,7 +45,7 @@ void prom_putchar(char c)
45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); 45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); 46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
47 47
48char *prom_getenv (char *s) 48char *prom_getenv(char *s)
49{ 49{
50 return __prom_getenv(s); 50 return __prom_getenv(s);
51} 51}
@@ -131,9 +131,9 @@ static void __init sni_console_setup(void)
131 int port; 131 int port;
132 static char options[8]; 132 static char options[8];
133 133
134 cdev = prom_getenv ("console_dev"); 134 cdev = prom_getenv("console_dev");
135 if (strncmp (cdev, "tty", 3) == 0) { 135 if (strncmp (cdev, "tty", 3) == 0) {
136 ctype = prom_getenv ("console"); 136 ctype = prom_getenv("console");
137 switch (*ctype) { 137 switch (*ctype) {
138 default: 138 default:
139 case 'l': 139 case 'l':
@@ -233,7 +233,7 @@ void __init prom_init(void)
233 systype = "RM300-Exx"; 233 systype = "RM300-Exx";
234 break; 234 break;
235 } 235 }
236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type,systype); 236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, systype);
237 237
238#ifdef DEBUG 238#ifdef DEBUG
239 sni_idprom_dump(); 239 sni_idprom_dump();
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 20028fc7757e..b80877349d38 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -2,8 +2,10 @@
2#include <linux/interrupt.h> 2#include <linux/interrupt.h>
3#include <linux/time.h> 3#include <linux/time.h>
4 4
5#include <asm/i8253.h>
5#include <asm/sni.h> 6#include <asm/sni.h>
6#include <asm/time.h> 7#include <asm/time.h>
8#include <asm-generic/rtc.h>
7 9
8#define SNI_CLOCK_TICK_RATE 3686400 10#define SNI_CLOCK_TICK_RATE 3686400
9#define SNI_COUNTER2_DIV 64 11#define SNI_COUNTER2_DIV 64
@@ -42,23 +44,23 @@ static __init unsigned long dosample(void)
42 volatile u8 msb, lsb; 44 volatile u8 msb, lsb;
43 45
44 /* Start the counter. */ 46 /* Start the counter. */
45 outb_p (0x34, 0x43); 47 outb_p(0x34, 0x43);
46 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); 48 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
47 outb (SNI_8254_TCSAMP_COUNTER >> 8, 0x40); 49 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
48 50
49 /* Get initial counter invariant */ 51 /* Get initial counter invariant */
50 ct0 = read_c0_count(); 52 ct0 = read_c0_count();
51 53
52 /* Latch and spin until top byte of counter0 is zero */ 54 /* Latch and spin until top byte of counter0 is zero */
53 do { 55 do {
54 outb (0x00, 0x43); 56 outb(0x00, 0x43);
55 lsb = inb (0x40); 57 lsb = inb(0x40);
56 msb = inb (0x40); 58 msb = inb(0x40);
57 ct1 = read_c0_count(); 59 ct1 = read_c0_count();
58 } while (msb); 60 } while (msb);
59 61
60 /* Stop the counter. */ 62 /* Stop the counter. */
61 outb (0x38, 0x43); 63 outb(0x38, 0x43);
62 /* 64 /*
63 * Return the difference, this is how far the r4k counter increments 65 * Return the difference, this is how far the r4k counter increments
64 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 66 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
@@ -71,7 +73,7 @@ static __init unsigned long dosample(void)
71/* 73/*
72 * Here we need to calibrate the cycle counter to at least be close. 74 * Here we need to calibrate the cycle counter to at least be close.
73 */ 75 */
74__init void sni_cpu_time_init(void) 76void __init plat_time_init(void)
75{ 77{
76 unsigned long r4k_ticks[3]; 78 unsigned long r4k_ticks[3];
77 unsigned long r4k_tick; 79 unsigned long r4k_tick;
@@ -115,6 +117,8 @@ __init void sni_cpu_time_init(void)
115 (int) (r4k_tick % (500000 / HZ))); 117 (int) (r4k_tick % (500000 / HZ)));
116 118
117 mips_hpt_frequency = r4k_tick * HZ; 119 mips_hpt_frequency = r4k_tick * HZ;
120
121 setup_pit_timer();
118} 122}
119 123
120/* 124/*
@@ -133,7 +137,7 @@ void __init plat_timer_setup(struct irqaction *irq)
133 case SNI_BRD_10NEW: 137 case SNI_BRD_10NEW:
134 case SNI_BRD_TOWER_OASIC: 138 case SNI_BRD_TOWER_OASIC:
135 case SNI_BRD_MINITOWER: 139 case SNI_BRD_MINITOWER:
136 sni_a20r_timer_setup (irq); 140 sni_a20r_timer_setup(irq);
137 break; 141 break;
138 142
139 case SNI_BRD_PCI_TOWER: 143 case SNI_BRD_PCI_TOWER:
@@ -142,7 +146,12 @@ void __init plat_timer_setup(struct irqaction *irq)
142 case SNI_BRD_PCI_DESKTOP: 146 case SNI_BRD_PCI_DESKTOP:
143 case SNI_BRD_PCI_TOWER_CPLUS: 147 case SNI_BRD_PCI_TOWER_CPLUS:
144 case SNI_BRD_PCI_MTOWER_CPLUS: 148 case SNI_BRD_PCI_MTOWER_CPLUS:
145 sni_cpu_timer_setup (irq); 149 sni_cpu_timer_setup(irq);
146 break; 150 break;
147 } 151 }
148} 152}
153
154unsigned long read_persistent_clock(void)
155{
156 return -1;
157}
diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c
index 09bdf2baa835..d8423e001b2d 100644
--- a/arch/mips/tx4927/common/tx4927_dbgio.c
+++ b/arch/mips/tx4927/common/tx4927_dbgio.c
@@ -31,7 +31,6 @@
31 31
32#include <asm/mipsregs.h> 32#include <asm/mipsregs.h>
33#include <asm/system.h> 33#include <asm/system.h>
34#include <asm/tx4927/tx4927_mips.h>
35 34
36u8 getDebugChar(void) 35u8 getDebugChar(void)
37{ 36{
diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c
index 7d4cbf512d8a..6eed53d8f386 100644
--- a/arch/mips/tx4927/common/tx4927_prom.c
+++ b/arch/mips/tx4927/common/tx4927_prom.c
@@ -38,7 +38,7 @@
38#include <asm/bootinfo.h> 38#include <asm/bootinfo.h>
39#include <asm/tx4927/tx4927.h> 39#include <asm/tx4927/tx4927.h>
40 40
41static unsigned int __init tx4927_process_sdccr(u64 * addr) 41static unsigned int __init tx4927_process_sdccr(unsigned long addr)
42{ 42{
43 u64 val; 43 u64 val;
44 unsigned int sdccr_ce; 44 unsigned int sdccr_ce;
@@ -52,7 +52,7 @@ static unsigned int __init tx4927_process_sdccr(u64 * addr)
52 unsigned int mw = 0; 52 unsigned int mw = 0;
53 unsigned int msize = 0; 53 unsigned int msize = 0;
54 54
55 val = (*((vu64 *) (addr))); 55 val = __raw_readq((void __iomem *)addr);
56 56
57 /* MVMCP -- need #defs for these bits masks */ 57 /* MVMCP -- need #defs for these bits masks */
58 sdccr_ce = ((val & (1 << 10)) >> 10); 58 sdccr_ce = ((val & (1 << 10)) >> 10);
@@ -136,10 +136,10 @@ unsigned int __init tx4927_get_mem_size(void)
136 unsigned int total; 136 unsigned int total;
137 137
138 /* MVMCP -- need #defs for these registers */ 138 /* MVMCP -- need #defs for these registers */
139 c0 = tx4927_process_sdccr((u64 *) 0xff1f8000); 139 c0 = tx4927_process_sdccr(0xff1f8000);
140 c1 = tx4927_process_sdccr((u64 *) 0xff1f8008); 140 c1 = tx4927_process_sdccr(0xff1f8008);
141 c2 = tx4927_process_sdccr((u64 *) 0xff1f8010); 141 c2 = tx4927_process_sdccr(0xff1f8010);
142 c3 = tx4927_process_sdccr((u64 *) 0xff1f8018); 142 c3 = tx4927_process_sdccr(0xff1f8018);
143 total = c0 + c1 + c2 + c3; 143 total = c0 + c1 + c2 + c3;
144 144
145 return (total); 145 return (total);
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index c8e49feb345b..8ce0989671d8 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -49,14 +49,11 @@
49 49
50#undef DEBUG 50#undef DEBUG
51 51
52void __init tx4927_time_init(void);
53void dump_cp0(char *key); 52void dump_cp0(char *key);
54 53
55 54
56void __init plat_mem_setup(void) 55void __init plat_mem_setup(void)
57{ 56{
58 board_time_init = tx4927_time_init;
59
60#ifdef CONFIG_TOSHIBA_RBTX4927 57#ifdef CONFIG_TOSHIBA_RBTX4927
61 { 58 {
62 extern void toshiba_rbtx4927_setup(void); 59 extern void toshiba_rbtx4927_setup(void);
@@ -65,20 +62,16 @@ void __init plat_mem_setup(void)
65#endif 62#endif
66} 63}
67 64
68void __init tx4927_time_init(void) 65void __init plat_time_init(void)
69{ 66{
70
71#ifdef CONFIG_TOSHIBA_RBTX4927 67#ifdef CONFIG_TOSHIBA_RBTX4927
72 { 68 {
73 extern void toshiba_rbtx4927_time_init(void); 69 extern void toshiba_rbtx4927_time_init(void);
74 toshiba_rbtx4927_time_init(); 70 toshiba_rbtx4927_time_init();
75 } 71 }
76#endif 72#endif
77
78 return;
79} 73}
80 74
81
82void __init plat_timer_setup(struct irqaction *irq) 75void __init plat_timer_setup(struct irqaction *irq)
83{ 76{
84 setup_irq(TX4927_IRQ_CPU_TIMER, irq); 77 setup_irq(TX4927_IRQ_CPU_TIMER, irq);
@@ -124,10 +117,10 @@ dump_cp0(char *key)
124 return; 117 return;
125} 118}
126 119
127void print_pic(char *key, u32 reg, char *name) 120void print_pic(char *key, unsigned long reg, char *name)
128{ 121{
129 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, 122 printk(KERN_INFO "%s pic:0x%08lx:%s=0x%08x\n", key, reg, name,
130 TX4927_RD(reg)); 123 __raw_readl((void __iomem *)reg));
131 return; 124 return;
132} 125}
133 126
@@ -166,9 +159,10 @@ void dump_pic(char *key)
166} 159}
167 160
168 161
169void print_addr(char *hdr, char *key, u32 addr) 162void print_addr(char *hdr, char *key, unsigned long addr)
170{ 163{
171 printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr)); 164 printk(KERN_INFO "%s %s:0x%08lx=0x%08x\n", hdr, key, addr,
165 __raw_readl((void __iomem *)addr));
172 return; 166 return;
173} 167}
174 168
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 9607ad5e734a..3f808b629242 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -176,7 +176,7 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
176 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 176 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
177 } 177 }
178#else 178#else
179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) 179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...)
180#endif 180#endif
181 181
182 182
@@ -204,8 +204,8 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
204 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 204 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
205 .unmask = toshiba_rbtx4927_irq_ioc_enable, 205 .unmask = toshiba_rbtx4927_irq_ioc_enable,
206}; 206};
207#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 207#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
208#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 208#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
209 209
210 210
211u32 bit2num(u32 num) 211u32 bit2num(u32 num)
@@ -224,7 +224,7 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
224{ 224{
225 u32 level3; 225 u32 level3;
226 226
227 level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 227 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
228 if (level3) { 228 if (level3) {
229 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); 229 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
230 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { 230 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
@@ -243,10 +243,12 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
243 return (sw_irq); 243 return (sw_irq);
244} 244}
245 245
246//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 246static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
247#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL } 247 .handler = no_action,
248static struct irqaction toshiba_rbtx4927_irq_ioc_action = 248 .flags = IRQF_SHARED,
249TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); 249 .mask = CPU_MASK_NONE,
250 .name = TOSHIBA_RBTX4927_IOC_NAME
251};
250 252
251 253
252/**********************************************************************************/ 254/**********************************************************************************/
@@ -286,9 +288,9 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
286 panic("\n"); 288 panic("\n");
287 } 289 }
288 290
289 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 291 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
290 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 292 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
291 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 293 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
292} 294}
293 295
294 296
@@ -306,9 +308,10 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
306 panic("\n"); 308 panic("\n");
307 } 309 }
308 310
309 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 311 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
310 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 312 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
311 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 313 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
314 mmiowb();
312} 315}
313 316
314 317
@@ -385,12 +388,12 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
385 level1_m = level0_m; 388 level1_m = level0_m;
386 level1_s = level0_s & 0x87; 389 level1_s = level0_s & 0x87;
387 390
388 level2 = TX4927_RD(0xff1ff6a0); 391 level2 = __raw_readl((void __iomem *)0xff1ff6a0UL);
389 level2_p = (((level2 & 0x10000)) ? 0 : 1); 392 level2_p = (((level2 & 0x10000)) ? 0 : 1);
390 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); 393 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
391 394
392 level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; 395 level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
393 level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 396 level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
394 397
395 level4_m = inb(0x21); 398 level4_m = inb(0x21);
396 outb(0x0A, 0x20); 399 outb(0x0A, 0x20);
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
index 9a3a5babd1fb..f3f86857beae 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
@@ -66,8 +66,6 @@ void __init prom_init(void)
66 66
67 prom_init_cmdline(); 67 prom_init_cmdline();
68 68
69 mips_machgroup = MACH_GROUP_TOSHIBA;
70
71 if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { 69 if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) {
72 mips_machtype = MACH_TOSHIBA_RBTX4927; 70 mips_machtype = MACH_TOSHIBA_RBTX4927;
73 toshiba_name = "TX4927"; 71 toshiba_name = "TX4927";
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 3e84237abe63..acaf613358c7 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -122,7 +122,7 @@ static const u32 toshiba_rbtx4927_setup_debug_flag =
122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
123 } 123 }
124#else 124#else
125#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) 125#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
126#endif 126#endif
127 127
128/* These functions are used for rebooting or halting the machine*/ 128/* These functions are used for rebooting or halting the machine*/
@@ -497,7 +497,7 @@ void __init tx4927_pci_setup(void)
497 "Internal"); 497 "Internal");
498 called = 1; 498 called = 1;
499 } 499 }
500 printk("%s PCIC --%s PCICLK:",toshiba_name, 500 printk("%s PCIC --%s PCICLK:", toshiba_name,
501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); 501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { 502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
503 int pciclk = 0; 503 int pciclk = 0;
@@ -679,25 +679,30 @@ void __init tx4927_pci_setup(void)
679 679
680#endif /* CONFIG_PCI */ 680#endif /* CONFIG_PCI */
681 681
682static void __noreturn wait_forever(void)
683{
684 while (1)
685 if (cpu_wait)
686 (*cpu_wait)();
687}
688
682void toshiba_rbtx4927_restart(char *command) 689void toshiba_rbtx4927_restart(char *command)
683{ 690{
684 printk(KERN_NOTICE "System Rebooting...\n"); 691 printk(KERN_NOTICE "System Rebooting...\n");
685 692
686 /* enable the s/w reset register */ 693 /* enable the s/w reset register */
687 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); 694 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
688 695
689 /* wait for enable to be seen */ 696 /* wait for enable to be seen */
690 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & 697 while ((readb(RBTX4927_SW_RESET_ENABLE) &
691 RBTX4927_SW_RESET_ENABLE_SET) == 0x00); 698 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
692 699
693 /* do a s/w reset */ 700 /* do a s/w reset */
694 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); 701 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
695 702
696 /* do something passive while waiting for reset */ 703 /* do something passive while waiting for reset */
697 local_irq_disable(); 704 local_irq_disable();
698 while (1) 705 wait_forever();
699 asm_wait();
700
701 /* no return */ 706 /* no return */
702} 707}
703 708
@@ -706,9 +711,7 @@ void toshiba_rbtx4927_halt(void)
706{ 711{
707 printk(KERN_NOTICE "System Halted\n"); 712 printk(KERN_NOTICE "System Halted\n");
708 local_irq_disable(); 713 local_irq_disable();
709 while (1) { 714 wait_forever();
710 asm_wait();
711 }
712 /* no return */ 715 /* no return */
713} 716}
714 717
@@ -720,7 +723,7 @@ void toshiba_rbtx4927_power_off(void)
720 723
721void __init toshiba_rbtx4927_setup(void) 724void __init toshiba_rbtx4927_setup(void)
722{ 725{
723 vu32 cp0_config; 726 u32 cp0_config;
724 char *argptr; 727 char *argptr;
725 728
726 printk("CPU is %s\n", toshiba_name); 729 printk("CPU is %s\n", toshiba_name);
@@ -747,15 +750,6 @@ void __init toshiba_rbtx4927_setup(void)
747 } 750 }
748#endif 751#endif
749 752
750 /* setup serial stuff */
751 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
752 ":Setting up tx4927 sio.\n");
753 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
754 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
755
756 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
757 "+\n");
758
759 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); 753 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
760 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, 754 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
761 ":mips_io_port_base=0x%08lx\n", 755 ":mips_io_port_base=0x%08lx\n",
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index 142abf453e40..ab4082267553 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -34,25 +34,16 @@
34#include <asm/tx4938/rbtx4938.h> 34#include <asm/tx4938/rbtx4938.h>
35 35
36extern void toshiba_rbtx4938_setup(void); 36extern void toshiba_rbtx4938_setup(void);
37extern void rbtx4938_time_init(void);
38 37
39void __init tx4938_setup(void); 38void __init tx4938_setup(void);
40void __init tx4938_time_init(void);
41void dump_cp0(char *key); 39void dump_cp0(char *key);
42 40
43void __init 41void __init
44plat_mem_setup(void) 42plat_mem_setup(void)
45{ 43{
46 board_time_init = tx4938_time_init;
47 toshiba_rbtx4938_setup(); 44 toshiba_rbtx4938_setup();
48} 45}
49 46
50void __init
51tx4938_time_init(void)
52{
53 rbtx4938_time_init();
54}
55
56void __init plat_timer_setup(struct irqaction *irq) 47void __init plat_timer_setup(struct irqaction *irq)
57{ 48{
58 setup_irq(TX4938_IRQ_CPU_TIMER, irq); 49 setup_irq(TX4938_IRQ_CPU_TIMER, irq);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
index 7dc6a0aae21c..69f21c1b7942 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
@@ -47,7 +47,6 @@ void __init prom_init(void)
47#ifndef CONFIG_TX4938_NAND_BOOT 47#ifndef CONFIG_TX4938_NAND_BOOT
48 prom_init_cmdline(); 48 prom_init_cmdline();
49#endif 49#endif
50 mips_machgroup = MACH_GROUP_TOSHIBA;
51 mips_machtype = MACH_TOSHIBA_RBTX4938; 50 mips_machtype = MACH_TOSHIBA_RBTX4938;
52 51
53 msize = tx4938_get_mem_size(); 52 msize = tx4938_get_mem_size();
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index f236b1ff8923..ceecaf498957 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -39,7 +39,6 @@
39#include <asm/tx4938/spi.h> 39#include <asm/tx4938/spi.h>
40#include <asm/gpio.h> 40#include <asm/gpio.h>
41 41
42extern void rbtx4938_time_init(void) __init;
43extern char * __init prom_getcmdline(void); 42extern char * __init prom_getcmdline(void);
44static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); 43static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
45 44
@@ -458,9 +457,9 @@ extern struct pci_controller tx4938_pci_controller[];
458static int __init tx4938_pcibios_init(void) 457static int __init tx4938_pcibios_init(void)
459{ 458{
460 unsigned long mem_base[2]; 459 unsigned long mem_base[2];
461 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ 460 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
462 unsigned long io_base[2]; 461 unsigned long io_base[2];
463 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ 462 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
464 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ 463 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
465 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); 464 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
466 465
@@ -856,7 +855,7 @@ void tx4938_report_pcic_status(void)
856/* We use onchip r4k counter or TMR timer as our system wide timer 855/* We use onchip r4k counter or TMR timer as our system wide timer
857 * interrupt running at 100HZ. */ 856 * interrupt running at 100HZ. */
858 857
859void __init rbtx4938_time_init(void) 858void __init plat_time_init(void)
860{ 859{
861 mips_hpt_frequency = txx9_cpu_clock / 2; 860 mips_hpt_frequency = txx9_cpu_clock / 2;
862} 861}
diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c
index ff272b2e8395..d77c330a0d59 100644
--- a/arch/mips/vr41xx/common/bcu.c
+++ b/arch/mips/vr41xx/common/bcu.c
@@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency);
70 70
71static inline uint16_t read_clkspeed(void) 71static inline uint16_t read_clkspeed(void)
72{ 72{
73 switch (current_cpu_data.cputype) { 73 switch (current_cpu_type()) {
74 case CPU_VR4111: 74 case CPU_VR4111:
75 case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1); 75 case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1);
76 case CPU_VR4122: 76 case CPU_VR4122:
@@ -88,7 +88,7 @@ static inline unsigned long calculate_pclock(uint16_t clkspeed)
88{ 88{
89 unsigned long pclock = 0; 89 unsigned long pclock = 0;
90 90
91 switch (current_cpu_data.cputype) { 91 switch (current_cpu_type()) {
92 case CPU_VR4111: 92 case CPU_VR4111:
93 case CPU_VR4121: 93 case CPU_VR4121:
94 pclock = 18432000 * 64; 94 pclock = 18432000 * 64;
@@ -138,7 +138,7 @@ static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long p
138{ 138{
139 unsigned long vtclock = 0; 139 unsigned long vtclock = 0;
140 140
141 switch (current_cpu_data.cputype) { 141 switch (current_cpu_type()) {
142 case CPU_VR4111: 142 case CPU_VR4111:
143 /* The NEC VR4111 doesn't have the VTClock. */ 143 /* The NEC VR4111 doesn't have the VTClock. */
144 break; 144 break;
@@ -180,7 +180,7 @@ static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pc
180{ 180{
181 unsigned long tclock = 0; 181 unsigned long tclock = 0;
182 182
183 switch (current_cpu_data.cputype) { 183 switch (current_cpu_type()) {
184 case CPU_VR4111: 184 case CPU_VR4111:
185 if (!(clkspeed & DIV2B)) 185 if (!(clkspeed & DIV2B))
186 tclock = pclock / 2; 186 tclock = pclock / 2;
diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c
index 657c5133c933..ad0e8e3409d9 100644
--- a/arch/mips/vr41xx/common/cmu.c
+++ b/arch/mips/vr41xx/common/cmu.c
@@ -95,8 +95,8 @@ void vr41xx_supply_clock(vr41xx_clock_t clock)
95 cmuclkmsk |= MSKFIR | MSKFFIR; 95 cmuclkmsk |= MSKFIR | MSKFFIR;
96 break; 96 break;
97 case DSIU_CLOCK: 97 case DSIU_CLOCK:
98 if (current_cpu_data.cputype == CPU_VR4111 || 98 if (current_cpu_type() == CPU_VR4111 ||
99 current_cpu_data.cputype == CPU_VR4121) 99 current_cpu_type() == CPU_VR4121)
100 cmuclkmsk |= MSKDSIU; 100 cmuclkmsk |= MSKDSIU;
101 else 101 else
102 cmuclkmsk |= MSKSIU | MSKDSIU; 102 cmuclkmsk |= MSKSIU | MSKDSIU;
@@ -146,8 +146,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock)
146 cmuclkmsk &= ~MSKPIU; 146 cmuclkmsk &= ~MSKPIU;
147 break; 147 break;
148 case SIU_CLOCK: 148 case SIU_CLOCK:
149 if (current_cpu_data.cputype == CPU_VR4111 || 149 if (current_cpu_type() == CPU_VR4111 ||
150 current_cpu_data.cputype == CPU_VR4121) { 150 current_cpu_type() == CPU_VR4121) {
151 cmuclkmsk &= ~(MSKSIU | MSKSSIU); 151 cmuclkmsk &= ~(MSKSIU | MSKSSIU);
152 } else { 152 } else {
153 if (cmuclkmsk & MSKDSIU) 153 if (cmuclkmsk & MSKDSIU)
@@ -166,8 +166,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock)
166 cmuclkmsk &= ~(MSKFIR | MSKFFIR); 166 cmuclkmsk &= ~(MSKFIR | MSKFFIR);
167 break; 167 break;
168 case DSIU_CLOCK: 168 case DSIU_CLOCK:
169 if (current_cpu_data.cputype == CPU_VR4111 || 169 if (current_cpu_type() == CPU_VR4111 ||
170 current_cpu_data.cputype == CPU_VR4121) { 170 current_cpu_type() == CPU_VR4121) {
171 cmuclkmsk &= ~MSKDSIU; 171 cmuclkmsk &= ~MSKDSIU;
172 } else { 172 } else {
173 if (cmuclkmsk & MSKSSIU) 173 if (cmuclkmsk & MSKSSIU)
@@ -216,7 +216,7 @@ static int __init vr41xx_cmu_init(void)
216{ 216{
217 unsigned long start, size; 217 unsigned long start, size;
218 218
219 switch (current_cpu_data.cputype) { 219 switch (current_cpu_type()) {
220 case CPU_VR4111: 220 case CPU_VR4111:
221 case CPU_VR4121: 221 case CPU_VR4121:
222 start = CMU_TYPE1_BASE; 222 start = CMU_TYPE1_BASE;
@@ -246,7 +246,7 @@ static int __init vr41xx_cmu_init(void)
246 } 246 }
247 247
248 cmuclkmsk = cmu_read(CMUCLKMSK); 248 cmuclkmsk = cmu_read(CMUCLKMSK);
249 if (current_cpu_data.cputype == CPU_VR4133) 249 if (current_cpu_type() == CPU_VR4133)
250 cmuclkmsk2 = cmu_read(CMUCLKMSK2); 250 cmuclkmsk2 = cmu_read(CMUCLKMSK2);
251 251
252 spin_lock_init(&cmu_lock); 252 spin_lock_init(&cmu_lock);
diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c
index d21f6f2d22a3..2b272f1496fe 100644
--- a/arch/mips/vr41xx/common/giu.c
+++ b/arch/mips/vr41xx/common/giu.c
@@ -81,7 +81,7 @@ static int __init vr41xx_giu_add(void)
81 if (!pdev) 81 if (!pdev)
82 return -ENOMEM; 82 return -ENOMEM;
83 83
84 switch (current_cpu_data.cputype) { 84 switch (current_cpu_type()) {
85 case CPU_VR4111: 85 case CPU_VR4111:
86 case CPU_VR4121: 86 case CPU_VR4121:
87 pdev->id = GPIO_50PINS_PULLUPDOWN; 87 pdev->id = GPIO_50PINS_PULLUPDOWN;
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index adabc6bad440..1899601e5862 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -157,8 +157,8 @@ void vr41xx_enable_piuint(uint16_t mask)
157 struct irq_desc *desc = irq_desc + PIU_IRQ; 157 struct irq_desc *desc = irq_desc + PIU_IRQ;
158 unsigned long flags; 158 unsigned long flags;
159 159
160 if (current_cpu_data.cputype == CPU_VR4111 || 160 if (current_cpu_type() == CPU_VR4111 ||
161 current_cpu_data.cputype == CPU_VR4121) { 161 current_cpu_type() == CPU_VR4121) {
162 spin_lock_irqsave(&desc->lock, flags); 162 spin_lock_irqsave(&desc->lock, flags);
163 icu1_set(MPIUINTREG, mask); 163 icu1_set(MPIUINTREG, mask);
164 spin_unlock_irqrestore(&desc->lock, flags); 164 spin_unlock_irqrestore(&desc->lock, flags);
@@ -172,8 +172,8 @@ void vr41xx_disable_piuint(uint16_t mask)
172 struct irq_desc *desc = irq_desc + PIU_IRQ; 172 struct irq_desc *desc = irq_desc + PIU_IRQ;
173 unsigned long flags; 173 unsigned long flags;
174 174
175 if (current_cpu_data.cputype == CPU_VR4111 || 175 if (current_cpu_type() == CPU_VR4111 ||
176 current_cpu_data.cputype == CPU_VR4121) { 176 current_cpu_type() == CPU_VR4121) {
177 spin_lock_irqsave(&desc->lock, flags); 177 spin_lock_irqsave(&desc->lock, flags);
178 icu1_clear(MPIUINTREG, mask); 178 icu1_clear(MPIUINTREG, mask);
179 spin_unlock_irqrestore(&desc->lock, flags); 179 spin_unlock_irqrestore(&desc->lock, flags);
@@ -187,8 +187,8 @@ void vr41xx_enable_aiuint(uint16_t mask)
187 struct irq_desc *desc = irq_desc + AIU_IRQ; 187 struct irq_desc *desc = irq_desc + AIU_IRQ;
188 unsigned long flags; 188 unsigned long flags;
189 189
190 if (current_cpu_data.cputype == CPU_VR4111 || 190 if (current_cpu_type() == CPU_VR4111 ||
191 current_cpu_data.cputype == CPU_VR4121) { 191 current_cpu_type() == CPU_VR4121) {
192 spin_lock_irqsave(&desc->lock, flags); 192 spin_lock_irqsave(&desc->lock, flags);
193 icu1_set(MAIUINTREG, mask); 193 icu1_set(MAIUINTREG, mask);
194 spin_unlock_irqrestore(&desc->lock, flags); 194 spin_unlock_irqrestore(&desc->lock, flags);
@@ -202,8 +202,8 @@ void vr41xx_disable_aiuint(uint16_t mask)
202 struct irq_desc *desc = irq_desc + AIU_IRQ; 202 struct irq_desc *desc = irq_desc + AIU_IRQ;
203 unsigned long flags; 203 unsigned long flags;
204 204
205 if (current_cpu_data.cputype == CPU_VR4111 || 205 if (current_cpu_type() == CPU_VR4111 ||
206 current_cpu_data.cputype == CPU_VR4121) { 206 current_cpu_type() == CPU_VR4121) {
207 spin_lock_irqsave(&desc->lock, flags); 207 spin_lock_irqsave(&desc->lock, flags);
208 icu1_clear(MAIUINTREG, mask); 208 icu1_clear(MAIUINTREG, mask);
209 spin_unlock_irqrestore(&desc->lock, flags); 209 spin_unlock_irqrestore(&desc->lock, flags);
@@ -217,8 +217,8 @@ void vr41xx_enable_kiuint(uint16_t mask)
217 struct irq_desc *desc = irq_desc + KIU_IRQ; 217 struct irq_desc *desc = irq_desc + KIU_IRQ;
218 unsigned long flags; 218 unsigned long flags;
219 219
220 if (current_cpu_data.cputype == CPU_VR4111 || 220 if (current_cpu_type() == CPU_VR4111 ||
221 current_cpu_data.cputype == CPU_VR4121) { 221 current_cpu_type() == CPU_VR4121) {
222 spin_lock_irqsave(&desc->lock, flags); 222 spin_lock_irqsave(&desc->lock, flags);
223 icu1_set(MKIUINTREG, mask); 223 icu1_set(MKIUINTREG, mask);
224 spin_unlock_irqrestore(&desc->lock, flags); 224 spin_unlock_irqrestore(&desc->lock, flags);
@@ -232,8 +232,8 @@ void vr41xx_disable_kiuint(uint16_t mask)
232 struct irq_desc *desc = irq_desc + KIU_IRQ; 232 struct irq_desc *desc = irq_desc + KIU_IRQ;
233 unsigned long flags; 233 unsigned long flags;
234 234
235 if (current_cpu_data.cputype == CPU_VR4111 || 235 if (current_cpu_type() == CPU_VR4111 ||
236 current_cpu_data.cputype == CPU_VR4121) { 236 current_cpu_type() == CPU_VR4121) {
237 spin_lock_irqsave(&desc->lock, flags); 237 spin_lock_irqsave(&desc->lock, flags);
238 icu1_clear(MKIUINTREG, mask); 238 icu1_clear(MKIUINTREG, mask);
239 spin_unlock_irqrestore(&desc->lock, flags); 239 spin_unlock_irqrestore(&desc->lock, flags);
@@ -319,9 +319,9 @@ void vr41xx_enable_pciint(void)
319 struct irq_desc *desc = irq_desc + PCI_IRQ; 319 struct irq_desc *desc = irq_desc + PCI_IRQ;
320 unsigned long flags; 320 unsigned long flags;
321 321
322 if (current_cpu_data.cputype == CPU_VR4122 || 322 if (current_cpu_type() == CPU_VR4122 ||
323 current_cpu_data.cputype == CPU_VR4131 || 323 current_cpu_type() == CPU_VR4131 ||
324 current_cpu_data.cputype == CPU_VR4133) { 324 current_cpu_type() == CPU_VR4133) {
325 spin_lock_irqsave(&desc->lock, flags); 325 spin_lock_irqsave(&desc->lock, flags);
326 icu2_write(MPCIINTREG, PCIINT0); 326 icu2_write(MPCIINTREG, PCIINT0);
327 spin_unlock_irqrestore(&desc->lock, flags); 327 spin_unlock_irqrestore(&desc->lock, flags);
@@ -335,9 +335,9 @@ void vr41xx_disable_pciint(void)
335 struct irq_desc *desc = irq_desc + PCI_IRQ; 335 struct irq_desc *desc = irq_desc + PCI_IRQ;
336 unsigned long flags; 336 unsigned long flags;
337 337
338 if (current_cpu_data.cputype == CPU_VR4122 || 338 if (current_cpu_type() == CPU_VR4122 ||
339 current_cpu_data.cputype == CPU_VR4131 || 339 current_cpu_type() == CPU_VR4131 ||
340 current_cpu_data.cputype == CPU_VR4133) { 340 current_cpu_type() == CPU_VR4133) {
341 spin_lock_irqsave(&desc->lock, flags); 341 spin_lock_irqsave(&desc->lock, flags);
342 icu2_write(MPCIINTREG, 0); 342 icu2_write(MPCIINTREG, 0);
343 spin_unlock_irqrestore(&desc->lock, flags); 343 spin_unlock_irqrestore(&desc->lock, flags);
@@ -351,9 +351,9 @@ void vr41xx_enable_scuint(void)
351 struct irq_desc *desc = irq_desc + SCU_IRQ; 351 struct irq_desc *desc = irq_desc + SCU_IRQ;
352 unsigned long flags; 352 unsigned long flags;
353 353
354 if (current_cpu_data.cputype == CPU_VR4122 || 354 if (current_cpu_type() == CPU_VR4122 ||
355 current_cpu_data.cputype == CPU_VR4131 || 355 current_cpu_type() == CPU_VR4131 ||
356 current_cpu_data.cputype == CPU_VR4133) { 356 current_cpu_type() == CPU_VR4133) {
357 spin_lock_irqsave(&desc->lock, flags); 357 spin_lock_irqsave(&desc->lock, flags);
358 icu2_write(MSCUINTREG, SCUINT0); 358 icu2_write(MSCUINTREG, SCUINT0);
359 spin_unlock_irqrestore(&desc->lock, flags); 359 spin_unlock_irqrestore(&desc->lock, flags);
@@ -367,9 +367,9 @@ void vr41xx_disable_scuint(void)
367 struct irq_desc *desc = irq_desc + SCU_IRQ; 367 struct irq_desc *desc = irq_desc + SCU_IRQ;
368 unsigned long flags; 368 unsigned long flags;
369 369
370 if (current_cpu_data.cputype == CPU_VR4122 || 370 if (current_cpu_type() == CPU_VR4122 ||
371 current_cpu_data.cputype == CPU_VR4131 || 371 current_cpu_type() == CPU_VR4131 ||
372 current_cpu_data.cputype == CPU_VR4133) { 372 current_cpu_type() == CPU_VR4133) {
373 spin_lock_irqsave(&desc->lock, flags); 373 spin_lock_irqsave(&desc->lock, flags);
374 icu2_write(MSCUINTREG, 0); 374 icu2_write(MSCUINTREG, 0);
375 spin_unlock_irqrestore(&desc->lock, flags); 375 spin_unlock_irqrestore(&desc->lock, flags);
@@ -383,9 +383,9 @@ void vr41xx_enable_csiint(uint16_t mask)
383 struct irq_desc *desc = irq_desc + CSI_IRQ; 383 struct irq_desc *desc = irq_desc + CSI_IRQ;
384 unsigned long flags; 384 unsigned long flags;
385 385
386 if (current_cpu_data.cputype == CPU_VR4122 || 386 if (current_cpu_type() == CPU_VR4122 ||
387 current_cpu_data.cputype == CPU_VR4131 || 387 current_cpu_type() == CPU_VR4131 ||
388 current_cpu_data.cputype == CPU_VR4133) { 388 current_cpu_type() == CPU_VR4133) {
389 spin_lock_irqsave(&desc->lock, flags); 389 spin_lock_irqsave(&desc->lock, flags);
390 icu2_set(MCSIINTREG, mask); 390 icu2_set(MCSIINTREG, mask);
391 spin_unlock_irqrestore(&desc->lock, flags); 391 spin_unlock_irqrestore(&desc->lock, flags);
@@ -399,9 +399,9 @@ void vr41xx_disable_csiint(uint16_t mask)
399 struct irq_desc *desc = irq_desc + CSI_IRQ; 399 struct irq_desc *desc = irq_desc + CSI_IRQ;
400 unsigned long flags; 400 unsigned long flags;
401 401
402 if (current_cpu_data.cputype == CPU_VR4122 || 402 if (current_cpu_type() == CPU_VR4122 ||
403 current_cpu_data.cputype == CPU_VR4131 || 403 current_cpu_type() == CPU_VR4131 ||
404 current_cpu_data.cputype == CPU_VR4133) { 404 current_cpu_type() == CPU_VR4133) {
405 spin_lock_irqsave(&desc->lock, flags); 405 spin_lock_irqsave(&desc->lock, flags);
406 icu2_clear(MCSIINTREG, mask); 406 icu2_clear(MCSIINTREG, mask);
407 spin_unlock_irqrestore(&desc->lock, flags); 407 spin_unlock_irqrestore(&desc->lock, flags);
@@ -415,9 +415,9 @@ void vr41xx_enable_bcuint(void)
415 struct irq_desc *desc = irq_desc + BCU_IRQ; 415 struct irq_desc *desc = irq_desc + BCU_IRQ;
416 unsigned long flags; 416 unsigned long flags;
417 417
418 if (current_cpu_data.cputype == CPU_VR4122 || 418 if (current_cpu_type() == CPU_VR4122 ||
419 current_cpu_data.cputype == CPU_VR4131 || 419 current_cpu_type() == CPU_VR4131 ||
420 current_cpu_data.cputype == CPU_VR4133) { 420 current_cpu_type() == CPU_VR4133) {
421 spin_lock_irqsave(&desc->lock, flags); 421 spin_lock_irqsave(&desc->lock, flags);
422 icu2_write(MBCUINTREG, BCUINTR); 422 icu2_write(MBCUINTREG, BCUINTR);
423 spin_unlock_irqrestore(&desc->lock, flags); 423 spin_unlock_irqrestore(&desc->lock, flags);
@@ -431,9 +431,9 @@ void vr41xx_disable_bcuint(void)
431 struct irq_desc *desc = irq_desc + BCU_IRQ; 431 struct irq_desc *desc = irq_desc + BCU_IRQ;
432 unsigned long flags; 432 unsigned long flags;
433 433
434 if (current_cpu_data.cputype == CPU_VR4122 || 434 if (current_cpu_type() == CPU_VR4122 ||
435 current_cpu_data.cputype == CPU_VR4131 || 435 current_cpu_type() == CPU_VR4131 ||
436 current_cpu_data.cputype == CPU_VR4133) { 436 current_cpu_type() == CPU_VR4133) {
437 spin_lock_irqsave(&desc->lock, flags); 437 spin_lock_irqsave(&desc->lock, flags);
438 icu2_write(MBCUINTREG, 0); 438 icu2_write(MBCUINTREG, 0);
439 spin_unlock_irqrestore(&desc->lock, flags); 439 spin_unlock_irqrestore(&desc->lock, flags);
@@ -608,7 +608,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
608{ 608{
609 int retval = -EINVAL; 609 int retval = -EINVAL;
610 610
611 if (current_cpu_data.cputype != CPU_VR4133) 611 if (current_cpu_type() != CPU_VR4133)
612 return -EINVAL; 612 return -EINVAL;
613 613
614 if (intassign > INTASSIGN_MAX) 614 if (intassign > INTASSIGN_MAX)
@@ -665,7 +665,7 @@ static int __init vr41xx_icu_init(void)
665 unsigned long icu1_start, icu2_start; 665 unsigned long icu1_start, icu2_start;
666 int i; 666 int i;
667 667
668 switch (current_cpu_data.cputype) { 668 switch (current_cpu_type()) {
669 case CPU_VR4111: 669 case CPU_VR4111:
670 case CPU_VR4121: 670 case CPU_VR4121:
671 icu1_start = ICU1_TYPE1_BASE; 671 icu1_start = ICU1_TYPE1_BASE;
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index 4f97e0ba9e24..407cec203b29 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -36,7 +36,7 @@ static void __init iomem_resource_init(void)
36 iomem_resource.end = IO_MEM_RESOURCE_END; 36 iomem_resource.end = IO_MEM_RESOURCE_END;
37} 37}
38 38
39static void __init setup_timer_frequency(void) 39void __init plat_time_init(void)
40{ 40{
41 unsigned long tclock; 41 unsigned long tclock;
42 42
@@ -53,16 +53,10 @@ void __init plat_timer_setup(struct irqaction *irq)
53 setup_irq(TIMER_IRQ, irq); 53 setup_irq(TIMER_IRQ, irq);
54} 54}
55 55
56static void __init timer_init(void)
57{
58 board_time_init = setup_timer_frequency;
59}
60
61void __init plat_mem_setup(void) 56void __init plat_mem_setup(void)
62{ 57{
63 vr41xx_calculate_clock_frequency(); 58 vr41xx_calculate_clock_frequency();
64 59
65 timer_init();
66 iomem_resource_init(); 60 iomem_resource_init();
67} 61}
68 62
diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c
index 5e469796413f..028aaf75eb21 100644
--- a/arch/mips/vr41xx/common/pmu.c
+++ b/arch/mips/vr41xx/common/pmu.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * pmu.c, Power Management Unit routines for NEC VR4100 series. 2 * pmu.c, Power Management Unit routines for NEC VR4100 series.
3 * 3 *
4 * Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> 4 * Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -22,11 +22,13 @@
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/pm.h> 24#include <linux/pm.h>
25#include <linux/smp.h> 25#include <linux/sched.h>
26#include <linux/types.h> 26#include <linux/types.h>
27 27
28#include <asm/cacheflush.h>
28#include <asm/cpu.h> 29#include <asm/cpu.h>
29#include <asm/io.h> 30#include <asm/io.h>
31#include <asm/processor.h>
30#include <asm/reboot.h> 32#include <asm/reboot.h>
31#include <asm/system.h> 33#include <asm/system.h>
32 34
@@ -44,11 +46,23 @@ static void __iomem *pmu_base;
44#define pmu_read(offset) readw(pmu_base + (offset)) 46#define pmu_read(offset) readw(pmu_base + (offset))
45#define pmu_write(offset, value) writew((value), pmu_base + (offset)) 47#define pmu_write(offset, value) writew((value), pmu_base + (offset))
46 48
49static void vr41xx_cpu_wait(void)
50{
51 local_irq_disable();
52 if (!need_resched())
53 /*
54 * "standby" sets IE bit of the CP0_STATUS to 1.
55 */
56 __asm__("standby;\n");
57 else
58 local_irq_enable();
59}
60
47static inline void software_reset(void) 61static inline void software_reset(void)
48{ 62{
49 uint16_t pmucnt2; 63 uint16_t pmucnt2;
50 64
51 switch (current_cpu_data.cputype) { 65 switch (current_cpu_type()) {
52 case CPU_VR4122: 66 case CPU_VR4122:
53 case CPU_VR4131: 67 case CPU_VR4131:
54 case CPU_VR4133: 68 case CPU_VR4133:
@@ -57,6 +71,11 @@ static inline void software_reset(void)
57 pmu_write(PMUCNT2REG, pmucnt2); 71 pmu_write(PMUCNT2REG, pmucnt2);
58 break; 72 break;
59 default: 73 default:
74 set_c0_status(ST0_BEV | ST0_ERL);
75 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
76 flush_cache_all();
77 write_c0_wired(0);
78 __asm__("jr %0"::"r"(0xbfc00000));
60 break; 79 break;
61 } 80 }
62} 81}
@@ -65,7 +84,6 @@ static void vr41xx_restart(char *command)
65{ 84{
66 local_irq_disable(); 85 local_irq_disable();
67 software_reset(); 86 software_reset();
68 printk(KERN_NOTICE "\nYou can reset your system\n");
69 while (1) ; 87 while (1) ;
70} 88}
71 89
@@ -73,21 +91,14 @@ static void vr41xx_halt(void)
73{ 91{
74 local_irq_disable(); 92 local_irq_disable();
75 printk(KERN_NOTICE "\nYou can turn off the power supply\n"); 93 printk(KERN_NOTICE "\nYou can turn off the power supply\n");
76 while (1) ; 94 __asm__("hibernate;\n");
77}
78
79static void vr41xx_power_off(void)
80{
81 local_irq_disable();
82 printk(KERN_NOTICE "\nYou can turn off the power supply\n");
83 while (1) ;
84} 95}
85 96
86static int __init vr41xx_pmu_init(void) 97static int __init vr41xx_pmu_init(void)
87{ 98{
88 unsigned long start, size; 99 unsigned long start, size;
89 100
90 switch (current_cpu_data.cputype) { 101 switch (current_cpu_type()) {
91 case CPU_VR4111: 102 case CPU_VR4111:
92 case CPU_VR4121: 103 case CPU_VR4121:
93 start = PMU_TYPE1_BASE; 104 start = PMU_TYPE1_BASE;
@@ -113,9 +124,10 @@ static int __init vr41xx_pmu_init(void)
113 return -EBUSY; 124 return -EBUSY;
114 } 125 }
115 126
127 cpu_wait = vr41xx_cpu_wait;
116 _machine_restart = vr41xx_restart; 128 _machine_restart = vr41xx_restart;
117 _machine_halt = vr41xx_halt; 129 _machine_halt = vr41xx_halt;
118 pm_power_off = vr41xx_power_off; 130 pm_power_off = vr41xx_halt;
119 131
120 return 0; 132 return 0;
121} 133}
diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c
index cce605b3d688..9f26c14edcac 100644
--- a/arch/mips/vr41xx/common/rtc.c
+++ b/arch/mips/vr41xx/common/rtc.c
@@ -82,7 +82,7 @@ static int __init vr41xx_rtc_add(void)
82 if (!pdev) 82 if (!pdev)
83 return -ENOMEM; 83 return -ENOMEM;
84 84
85 switch (current_cpu_data.cputype) { 85 switch (current_cpu_type()) {
86 case CPU_VR4111: 86 case CPU_VR4111:
87 case CPU_VR4121: 87 case CPU_VR4121:
88 res = rtc_type1_resource; 88 res = rtc_type1_resource;
diff --git a/arch/mips/vr41xx/common/siu.c b/arch/mips/vr41xx/common/siu.c
index a1e774142163..b735f45b25f0 100644
--- a/arch/mips/vr41xx/common/siu.c
+++ b/arch/mips/vr41xx/common/siu.c
@@ -83,7 +83,7 @@ static int __init vr41xx_siu_add(void)
83 if (!pdev) 83 if (!pdev)
84 return -ENOMEM; 84 return -ENOMEM;
85 85
86 switch (current_cpu_data.cputype) { 86 switch (current_cpu_type()) {
87 case CPU_VR4111: 87 case CPU_VR4111:
88 case CPU_VR4121: 88 case CPU_VR4121:
89 pdev->dev.platform_data = siu_type1_ports; 89 pdev->dev.platform_data = siu_type1_ports;
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c
index ae1af6b21c45..7c5e18ee2231 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/init.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c
@@ -36,7 +36,7 @@ void disable_pcnet(void)
36 */ 36 */
37 37
38 writel((2 << 16) | 38 writel((2 << 16) |
39 (PCI_DEVFN(1,0) << 8) | 39 (PCI_DEVFN(1, 0) << 8) |
40 (0 & 0xfc) | 40 (0 & 0xfc) |
41 1UL, 41 1UL,
42 PCICONFAREG); 42 PCICONFAREG);
@@ -44,7 +44,7 @@ void disable_pcnet(void)
44 data = readl(PCICONFDREG); 44 data = readl(PCICONFDREG);
45 45
46 writel((2 << 16) | 46 writel((2 << 16) |
47 (PCI_DEVFN(1,0) << 8) | 47 (PCI_DEVFN(1, 0) << 8) |
48 (4 & 0xfc) | 48 (4 & 0xfc) |
49 1UL, 49 1UL,
50 PCICONFAREG); 50 PCICONFAREG);
@@ -52,7 +52,7 @@ void disable_pcnet(void)
52 data = readl(PCICONFDREG); 52 data = readl(PCICONFDREG);
53 53
54 writel((2 << 16) | 54 writel((2 << 16) |
55 (PCI_DEVFN(1,0) << 8) | 55 (PCI_DEVFN(1, 0) << 8) |
56 (4 & 0xfc) | 56 (4 & 0xfc) |
57 1UL, 57 1UL,
58 PCICONFAREG); 58 PCICONFAREG);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
index f45caccedc07..1341f3287d04 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
@@ -38,7 +38,7 @@
38 outb_p((dev_no), DATA_PORT(port)); \ 38 outb_p((dev_no), DATA_PORT(port)); \
39 } while(0) 39 } while(0)
40 40
41#define WRITE_CONFIG_DATA(port,index,data) \ 41#define WRITE_CONFIG_DATA(port, index, data) \
42 do { \ 42 do { \
43 outb_p((index), INDEX_PORT(port)); \ 43 outb_p((index), INDEX_PORT(port)); \
44 outb_p((data), DATA_PORT(port)); \ 44 outb_p((data), DATA_PORT(port)); \
@@ -206,8 +206,8 @@ static inline u16 ali_config_readw(u8 reg, int devfn)
206int vr4133_rockhopper = 0; 206int vr4133_rockhopper = 0;
207void __init ali_m5229_preinit(void) 207void __init ali_m5229_preinit(void)
208{ 208{
209 if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL && 209 if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
210 ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) { 210 ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
211 printk(KERN_INFO "Found an NEC Rockhopper \n"); 211 printk(KERN_INFO "Found an NEC Rockhopper \n");
212 vr4133_rockhopper = 1; 212 vr4133_rockhopper = 1;
213 /* 213 /*
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
index b20b93b2b95e..58e47686b499 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
@@ -64,7 +64,6 @@ static void __init nec_cmbvr4133_setup(void)
64#endif 64#endif
65 set_io_port_base(KSEG1ADDR(0x16000000)); 65 set_io_port_base(KSEG1ADDR(0x16000000));
66 66
67 mips_machgroup = MACH_GROUP_NEC_VR41XX;
68 mips_machtype = MACH_NEC_CMBVR4133; 67 mips_machtype = MACH_NEC_CMBVR4133;
69 68
70#ifdef CONFIG_PCI 69#ifdef CONFIG_PCI
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 0b3ff9c48409..0bb7a93b7a5e 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -123,10 +123,10 @@
123/* 123/*
124 * 64-bit address conversions 124 * 64-bit address conversions
125 */ 125 */
126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
129#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
130 ((cm)<<59) | (a)) 130 ((cm)<<59) | (a))
131 131
132/* 132/*
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index 838eb3144d81..12e17581b823 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -21,11 +21,11 @@
21 21
22#ifndef CAT 22#ifndef CAT
23#ifdef __STDC__ 23#ifdef __STDC__
24#define __CAT(str1,str2) str1##str2 24#define __CAT(str1, str2) str1##str2
25#else 25#else
26#define __CAT(str1,str2) str1/**/str2 26#define __CAT(str1, str2) str1/**/str2
27#endif 27#endif
28#define CAT(str1,str2) __CAT(str1,str2) 28#define CAT(str1, str2) __CAT(str1, str2)
29#endif 29#endif
30 30
31/* 31/*
@@ -51,9 +51,9 @@
51#define LEAF(symbol) \ 51#define LEAF(symbol) \
52 .globl symbol; \ 52 .globl symbol; \
53 .align 2; \ 53 .align 2; \
54 .type symbol,@function; \ 54 .type symbol, @function; \
55 .ent symbol,0; \ 55 .ent symbol, 0; \
56symbol: .frame sp,0,ra 56symbol: .frame sp, 0, ra
57 57
58/* 58/*
59 * NESTED - declare nested routine entry point 59 * NESTED - declare nested routine entry point
@@ -61,8 +61,8 @@ symbol: .frame sp,0,ra
61#define NESTED(symbol, framesize, rpc) \ 61#define NESTED(symbol, framesize, rpc) \
62 .globl symbol; \ 62 .globl symbol; \
63 .align 2; \ 63 .align 2; \
64 .type symbol,@function; \ 64 .type symbol, @function; \
65 .ent symbol,0; \ 65 .ent symbol, 0; \
66symbol: .frame sp, framesize, rpc 66symbol: .frame sp, framesize, rpc
67 67
68/* 68/*
@@ -70,7 +70,7 @@ symbol: .frame sp, framesize, rpc
70 */ 70 */
71#define END(function) \ 71#define END(function) \
72 .end function; \ 72 .end function; \
73 .size function,.-function 73 .size function, .-function
74 74
75/* 75/*
76 * EXPORT - export definition of symbol 76 * EXPORT - export definition of symbol
@@ -84,7 +84,7 @@ symbol:
84 */ 84 */
85#define FEXPORT(symbol) \ 85#define FEXPORT(symbol) \
86 .globl symbol; \ 86 .globl symbol; \
87 .type symbol,@function; \ 87 .type symbol, @function; \
88symbol: 88symbol:
89 89
90/* 90/*
@@ -97,7 +97,7 @@ symbol = value
97#define PANIC(msg) \ 97#define PANIC(msg) \
98 .set push; \ 98 .set push; \
99 .set reorder; \ 99 .set reorder; \
100 PTR_LA a0,8f; \ 100 PTR_LA a0, 8f; \
101 jal panic; \ 101 jal panic; \
1029: b 9b; \ 1029: b 9b; \
103 .set pop; \ 103 .set pop; \
@@ -110,7 +110,7 @@ symbol = value
110#define PRINT(string) \ 110#define PRINT(string) \
111 .set push; \ 111 .set push; \
112 .set reorder; \ 112 .set reorder; \
113 PTR_LA a0,8f; \ 113 PTR_LA a0, 8f; \
114 jal printk; \ 114 jal printk; \
115 .set pop; \ 115 .set pop; \
116 TEXT(string) 116 TEXT(string)
@@ -146,19 +146,19 @@ symbol = value
146#define PREF(hint,addr) \ 146#define PREF(hint,addr) \
147 .set push; \ 147 .set push; \
148 .set mips4; \ 148 .set mips4; \
149 pref hint,addr; \ 149 pref hint, addr; \
150 .set pop 150 .set pop
151 151
152#define PREFX(hint,addr) \ 152#define PREFX(hint,addr) \
153 .set push; \ 153 .set push; \
154 .set mips4; \ 154 .set mips4; \
155 prefx hint,addr; \ 155 prefx hint, addr; \
156 .set pop 156 .set pop
157 157
158#else /* !CONFIG_CPU_HAS_PREFETCH */ 158#else /* !CONFIG_CPU_HAS_PREFETCH */
159 159
160#define PREF(hint,addr) 160#define PREF(hint, addr)
161#define PREFX(hint,addr) 161#define PREFX(hint, addr)
162 162
163#endif /* !CONFIG_CPU_HAS_PREFETCH */ 163#endif /* !CONFIG_CPU_HAS_PREFETCH */
164 164
@@ -166,43 +166,43 @@ symbol = value
166 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. 166 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
167 */ 167 */
168#if (_MIPS_ISA == _MIPS_ISA_MIPS1) 168#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
169#define MOVN(rd,rs,rt) \ 169#define MOVN(rd, rs, rt) \
170 .set push; \ 170 .set push; \
171 .set reorder; \ 171 .set reorder; \
172 beqz rt,9f; \ 172 beqz rt, 9f; \
173 move rd,rs; \ 173 move rd, rs; \
174 .set pop; \ 174 .set pop; \
1759: 1759:
176#define MOVZ(rd,rs,rt) \ 176#define MOVZ(rd, rs, rt) \
177 .set push; \ 177 .set push; \
178 .set reorder; \ 178 .set reorder; \
179 bnez rt,9f; \ 179 bnez rt, 9f; \
180 move rd,rs; \ 180 move rd, rs; \
181 .set pop; \ 181 .set pop; \
1829: 1829:
183#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ 183#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
184#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) 184#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
185#define MOVN(rd,rs,rt) \ 185#define MOVN(rd, rs, rt) \
186 .set push; \ 186 .set push; \
187 .set noreorder; \ 187 .set noreorder; \
188 bnezl rt,9f; \ 188 bnezl rt, 9f; \
189 move rd,rs; \ 189 move rd, rs; \
190 .set pop; \ 190 .set pop; \
1919: 1919:
192#define MOVZ(rd,rs,rt) \ 192#define MOVZ(rd, rs, rt) \
193 .set push; \ 193 .set push; \
194 .set noreorder; \ 194 .set noreorder; \
195 beqzl rt,9f; \ 195 beqzl rt, 9f; \
196 move rd,rs; \ 196 move rd, rs; \
197 .set pop; \ 197 .set pop; \
1989: 1989:
199#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ 199#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
200#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ 200#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
201 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) 201 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
202#define MOVN(rd,rs,rt) \ 202#define MOVN(rd, rs, rt) \
203 movn rd,rs,rt 203 movn rd, rs, rt
204#define MOVZ(rd,rs,rt) \ 204#define MOVZ(rd, rs, rt) \
205 movz rd,rs,rt 205 movz rd, rs, rt
206#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ 206#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
207 207
208/* 208/*
@@ -396,6 +396,6 @@ symbol = value
396#define MTC0 dmtc0 396#define MTC0 dmtc0
397#endif 397#endif
398 398
399#define SSNOP sll zero,zero,1 399#define SSNOP sll zero, zero, 1
400 400
401#endif /* __ASM_ASM_H */ 401#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index c5f20df780e9..7a881755800f 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -56,27 +56,27 @@
56 * Temporary until all gas have MT ASE support 56 * Temporary until all gas have MT ASE support
57 */ 57 */
58 .macro DMT reg=0 58 .macro DMT reg=0
59 .word (0x41600bc1 | (\reg << 16)) 59 .word 0x41600bc1 | (\reg << 16)
60 .endm 60 .endm
61 61
62 .macro EMT reg=0 62 .macro EMT reg=0
63 .word (0x41600be1 | (\reg << 16)) 63 .word 0x41600be1 | (\reg << 16)
64 .endm 64 .endm
65 65
66 .macro DVPE reg=0 66 .macro DVPE reg=0
67 .word (0x41600001 | (\reg << 16)) 67 .word 0x41600001 | (\reg << 16)
68 .endm 68 .endm
69 69
70 .macro EVPE reg=0 70 .macro EVPE reg=0
71 .word (0x41600021 | (\reg << 16)) 71 .word 0x41600021 | (\reg << 16)
72 .endm 72 .endm
73 73
74 .macro MFTR rt=0, rd=0, u=0, sel=0 74 .macro MFTR rt=0, rd=0, u=0, sel=0
75 .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 75 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
76 .endm 76 .endm
77 77
78 .macro MTTR rt=0, rd=0, u=0, sel=0 78 .macro MTTR rt=0, rd=0, u=0, sel=0
79 .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 79 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
80 .endm 80 .endm
81 81
82#endif /* _ASM_ASMMACRO_H */ 82#endif /* _ASM_ASMMACRO_H */
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 7d8003769a44..a798d6299a79 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -39,7 +39,7 @@ typedef struct { volatile int counter; } atomic_t;
39 * 39 *
40 * Atomically sets the value of @v to @i. 40 * Atomically sets the value of @v to @i.
41 */ 41 */
42#define atomic_set(v,i) ((v)->counter = (i)) 42#define atomic_set(v, i) ((v)->counter = (i))
43 43
44/* 44/*
45 * atomic_add - add integer to atomic variable 45 * atomic_add - add integer to atomic variable
@@ -335,8 +335,8 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
335} 335}
336#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 336#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
337 337
338#define atomic_dec_return(v) atomic_sub_return(1,(v)) 338#define atomic_dec_return(v) atomic_sub_return(1, (v))
339#define atomic_inc_return(v) atomic_add_return(1,(v)) 339#define atomic_inc_return(v) atomic_add_return(1, (v))
340 340
341/* 341/*
342 * atomic_sub_and_test - subtract value from variable and test result 342 * atomic_sub_and_test - subtract value from variable and test result
@@ -347,7 +347,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
347 * true if the result is zero, or false for all 347 * true if the result is zero, or false for all
348 * other cases. 348 * other cases.
349 */ 349 */
350#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) 350#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
351 351
352/* 352/*
353 * atomic_inc_and_test - increment and test 353 * atomic_inc_and_test - increment and test
@@ -381,7 +381,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
381 * 381 *
382 * Atomically increments @v by 1. 382 * Atomically increments @v by 1.
383 */ 383 */
384#define atomic_inc(v) atomic_add(1,(v)) 384#define atomic_inc(v) atomic_add(1, (v))
385 385
386/* 386/*
387 * atomic_dec - decrement and test 387 * atomic_dec - decrement and test
@@ -389,7 +389,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
389 * 389 *
390 * Atomically decrements @v by 1. 390 * Atomically decrements @v by 1.
391 */ 391 */
392#define atomic_dec(v) atomic_sub(1,(v)) 392#define atomic_dec(v) atomic_sub(1, (v))
393 393
394/* 394/*
395 * atomic_add_negative - add and test if negative 395 * atomic_add_negative - add and test if negative
@@ -400,7 +400,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
400 * if the result is negative, or false when 400 * if the result is negative, or false when
401 * result is greater than or equal to zero. 401 * result is greater than or equal to zero.
402 */ 402 */
403#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) 403#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
404 404
405#ifdef CONFIG_64BIT 405#ifdef CONFIG_64BIT
406 406
@@ -420,7 +420,7 @@ typedef struct { volatile long counter; } atomic64_t;
420 * @v: pointer of type atomic64_t 420 * @v: pointer of type atomic64_t
421 * @i: required value 421 * @i: required value
422 */ 422 */
423#define atomic64_set(v,i) ((v)->counter = (i)) 423#define atomic64_set(v, i) ((v)->counter = (i))
424 424
425/* 425/*
426 * atomic64_add - add integer to atomic variable 426 * atomic64_add - add integer to atomic variable
@@ -718,8 +718,8 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
718 718
719#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) 719#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
720 720
721#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) 721#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
722#define atomic64_inc_return(v) atomic64_add_return(1,(v)) 722#define atomic64_inc_return(v) atomic64_add_return(1, (v))
723 723
724/* 724/*
725 * atomic64_sub_and_test - subtract value from variable and test result 725 * atomic64_sub_and_test - subtract value from variable and test result
@@ -730,7 +730,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
730 * true if the result is zero, or false for all 730 * true if the result is zero, or false for all
731 * other cases. 731 * other cases.
732 */ 732 */
733#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) 733#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
734 734
735/* 735/*
736 * atomic64_inc_and_test - increment and test 736 * atomic64_inc_and_test - increment and test
@@ -764,7 +764,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
764 * 764 *
765 * Atomically increments @v by 1. 765 * Atomically increments @v by 1.
766 */ 766 */
767#define atomic64_inc(v) atomic64_add(1,(v)) 767#define atomic64_inc(v) atomic64_add(1, (v))
768 768
769/* 769/*
770 * atomic64_dec - decrement and test 770 * atomic64_dec - decrement and test
@@ -772,7 +772,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
772 * 772 *
773 * Atomically decrements @v by 1. 773 * Atomically decrements @v by 1.
774 */ 774 */
775#define atomic64_dec(v) atomic64_sub(1,(v)) 775#define atomic64_dec(v) atomic64_sub(1, (v))
776 776
777/* 777/*
778 * atomic64_add_negative - add and test if negative 778 * atomic64_add_negative - add and test if negative
@@ -783,7 +783,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
783 * if the result is negative, or false when 783 * if the result is negative, or false when
784 * result is greater than or equal to zero. 784 * result is greater than or equal to zero.
785 */ 785 */
786#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) 786#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
787 787
788#endif /* CONFIG_64BIT */ 788#endif /* CONFIG_64BIT */
789 789
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 148bc79557f1..899357a72ac4 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -19,14 +19,14 @@
19#include <asm/sgidefs.h> 19#include <asm/sgidefs.h>
20#include <asm/war.h> 20#include <asm/war.h>
21 21
22#if (_MIPS_SZLONG == 32) 22#if _MIPS_SZLONG == 32
23#define SZLONG_LOG 5 23#define SZLONG_LOG 5
24#define SZLONG_MASK 31UL 24#define SZLONG_MASK 31UL
25#define __LL "ll " 25#define __LL "ll "
26#define __SC "sc " 26#define __SC "sc "
27#define __INS "ins " 27#define __INS "ins "
28#define __EXT "ext " 28#define __EXT "ext "
29#elif (_MIPS_SZLONG == 64) 29#elif _MIPS_SZLONG == 64
30#define SZLONG_LOG 6 30#define SZLONG_LOG 6
31#define SZLONG_MASK 63UL 31#define SZLONG_MASK 63UL
32#define __LL "lld " 32#define __LL "lld "
@@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x)
461 int lz; 461 int lz;
462 462
463 if (sizeof(x) == 4) { 463 if (sizeof(x) == 4) {
464 __asm__ ( 464 __asm__(
465 " .set push \n" 465 " .set push \n"
466 " .set mips32 \n" 466 " .set mips32 \n"
467 " clz %0, %1 \n" 467 " clz %0, %1 \n"
@@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x)
474 474
475 BUG_ON(sizeof(x) != 8); 475 BUG_ON(sizeof(x) != 8);
476 476
477 __asm__ ( 477 __asm__(
478 " .set push \n" 478 " .set push \n"
479 " .set mips64 \n" 479 " .set mips64 \n"
480 " dclz %0, %1 \n" 480 " dclz %0, %1 \n"
@@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word)
508 */ 508 */
509static inline int fls(int word) 509static inline int fls(int word)
510{ 510{
511 __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); 511 __asm__("clz %0, %1" : "=r" (word) : "r" (word));
512 512
513 return 32 - word; 513 return 32 - word;
514} 514}
@@ -516,7 +516,7 @@ static inline int fls(int word)
516#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) 516#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
517static inline int fls64(__u64 word) 517static inline int fls64(__u64 word)
518{ 518{
519 __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); 519 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
520 520
521 return 64 - word; 521 return 64 - word;
522} 522}
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index c0f052b37b9e..b2dd9b33de8f 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -15,21 +15,19 @@
15#include <asm/setup.h> 15#include <asm/setup.h>
16 16
17/* 17/*
18 * The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining 18 * The MACH_ IDs are sort of equivalent to PCI product IDs. As such the
19 * MACH_ values equivalent to product IDs. As such the numbers do not 19 * numbers do not necessarily reflect technical relations or similarities
20 * necessarily reflect technical relations or similarities between systems. 20 * between systems.
21 */ 21 */
22 22
23/* 23/*
24 * Valid machtype values for group unknown 24 * Valid machtype values for group unknown
25 */ 25 */
26#define MACH_GROUP_UNKNOWN 0 /* whatever... */
27#define MACH_UNKNOWN 0 /* whatever... */ 26#define MACH_UNKNOWN 0 /* whatever... */
28 27
29/* 28/*
30 * Valid machtype values for group JAZZ 29 * Valid machtype values for group JAZZ
31 */ 30 */
32#define MACH_GROUP_JAZZ 1 /* Jazz */
33#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ 31#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */
34#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ 32#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */
35#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ 33#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */
@@ -37,7 +35,6 @@
37/* 35/*
38 * Valid machtype for group DEC 36 * Valid machtype for group DEC
39 */ 37 */
40#define MACH_GROUP_DEC 2 /* Digital Equipment */
41#define MACH_DSUNKNOWN 0 38#define MACH_DSUNKNOWN 0
42#define MACH_DS23100 1 /* DECstation 2100 or 3100 */ 39#define MACH_DS23100 1 /* DECstation 2100 or 3100 */
43#define MACH_DS5100 2 /* DECsystem 5100 */ 40#define MACH_DS5100 2 /* DECsystem 5100 */
@@ -53,26 +50,22 @@
53/* 50/*
54 * Valid machtype for group ARC 51 * Valid machtype for group ARC
55 */ 52 */
56#define MACH_GROUP_ARC 3 /* Deskstation */
57#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ 53#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */
58#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ 54#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */
59 55
60/* 56/*
61 * Valid machtype for group SNI_RM 57 * Valid machtype for group SNI_RM
62 */ 58 */
63#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */
64#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ 59#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */
65 60
66/* 61/*
67 * Valid machtype for group ACN 62 * Valid machtype for group ACN
68 */ 63 */
69#define MACH_GROUP_ACN 5
70#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ 64#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */
71 65
72/* 66/*
73 * Valid machtype for group SGI 67 * Valid machtype for group SGI
74 */ 68 */
75#define MACH_GROUP_SGI 6 /* Silicon Graphics */
76#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ 69#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */
77#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ 70#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */
78#define MACH_SGI_IP28 2 /* Indigo2 Impact */ 71#define MACH_SGI_IP28 2 /* Indigo2 Impact */
@@ -82,26 +75,22 @@
82/* 75/*
83 * Valid machtype for group COBALT 76 * Valid machtype for group COBALT
84 */ 77 */
85#define MACH_GROUP_COBALT 7 /* Cobalt servers */
86#define MACH_COBALT_27 0 /* Proto "27" hardware */ 78#define MACH_COBALT_27 0 /* Proto "27" hardware */
87 79
88/* 80/*
89 * Valid machtype for group BAGET 81 * Valid machtype for group BAGET
90 */ 82 */
91#define MACH_GROUP_BAGET 9 /* Baget */
92#define MACH_BAGET201 0 /* BT23-201 */ 83#define MACH_BAGET201 0 /* BT23-201 */
93#define MACH_BAGET202 1 /* BT23-202 */ 84#define MACH_BAGET202 1 /* BT23-202 */
94 85
95/* 86/*
96 * Cosine boards. 87 * Cosine boards.
97 */ 88 */
98#define MACH_GROUP_COSINE 10 /* CoSine Orion */
99#define MACH_COSINE_ORION 0 89#define MACH_COSINE_ORION 0
100 90
101/* 91/*
102 * Valid machtype for group MOMENCO 92 * Valid machtype for group MOMENCO
103 */ 93 */
104#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */
105#define MACH_MOMENCO_OCELOT 0 94#define MACH_MOMENCO_OCELOT 0
106#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ 95#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
107#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ 96#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */
@@ -111,7 +100,6 @@
111/* 100/*
112 * Valid machtype for group PHILIPS 101 * Valid machtype for group PHILIPS
113 */ 102 */
114#define MACH_GROUP_PHILIPS 14
115#define MACH_PHILIPS_NINO 0 /* Nino */ 103#define MACH_PHILIPS_NINO 0 /* Nino */
116#define MACH_PHILIPS_VELO 1 /* Velo */ 104#define MACH_PHILIPS_VELO 1 /* Velo */
117#define MACH_PHILIPS_JBS 2 /* JBS */ 105#define MACH_PHILIPS_JBS 2 /* JBS */
@@ -120,13 +108,11 @@
120/* 108/*
121 * Valid machtype for group SIBYTE 109 * Valid machtype for group SIBYTE
122 */ 110 */
123#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */
124#define MACH_SWARM 0 111#define MACH_SWARM 0
125 112
126/* 113/*
127 * Valid machtypes for group Toshiba 114 * Valid machtypes for group Toshiba
128 */ 115 */
129#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */
130#define MACH_PALLAS 0 116#define MACH_PALLAS 0
131#define MACH_TOPAS 1 117#define MACH_TOPAS 1
132#define MACH_JMR 2 118#define MACH_JMR 2
@@ -138,7 +124,6 @@
138/* 124/*
139 * Valid machtype for group Alchemy 125 * Valid machtype for group Alchemy
140 */ 126 */
141#define MACH_GROUP_ALCHEMY 18 /* AMD Alchemy */
142#define MACH_PB1000 0 /* Au1000-based eval board */ 127#define MACH_PB1000 0 /* Au1000-based eval board */
143#define MACH_PB1100 1 /* Au1100-based eval board */ 128#define MACH_PB1100 1 /* Au1100-based eval board */
144#define MACH_PB1500 2 /* Au1500-based eval board */ 129#define MACH_PB1500 2 /* Au1500-based eval board */
@@ -160,7 +145,6 @@
160 * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by 145 * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by
161 * technical properties, so no new additions to this group. 146 * technical properties, so no new additions to this group.
162 */ 147 */
163#define MACH_GROUP_NEC_VR41XX 19
164#define MACH_NEC_OSPREY 0 /* Osprey eval board */ 148#define MACH_NEC_OSPREY 0 /* Osprey eval board */
165#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ 149#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */
166#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ 150#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */
@@ -171,32 +155,33 @@
171#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ 155#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
172#define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */ 156#define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */
173 157
174#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
175#define MACH_HP_LASERJET 1 158#define MACH_HP_LASERJET 1
176 159
177/* 160/*
161 * Valid machtype for group LASAT
162 */
163#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
164#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
165
166/*
178 * Valid machtype for group TITAN 167 * Valid machtype for group TITAN
179 */ 168 */
180#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
181#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ 169#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
182#define MACH_TITAN_EXCITE 2 /* Basler eXcite */ 170#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
183 171
184/* 172/*
185 * Valid machtype for group NEC EMMA2RH 173 * Valid machtype for group NEC EMMA2RH
186 */ 174 */
187#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
188#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ 175#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
189 176
190/* 177/*
191 * Valid machtype for group LEMOTE 178 * Valid machtype for group LEMOTE
192 */ 179 */
193#define MACH_GROUP_LEMOTE 27
194#define MACH_LEMOTE_FULONG 0 180#define MACH_LEMOTE_FULONG 0
195 181
196/* 182/*
197 * Valid machtype for group PMC-MSP 183 * Valid machtype for group PMC-MSP
198 */ 184 */
199#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */
200#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ 185#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
201#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ 186#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
202#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ 187#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
@@ -205,15 +190,19 @@
205#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ 190#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
206#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ 191#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
207 192
208#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */
209#define MACH_WRPPMC 1 193#define MACH_WRPPMC 1
210 194
195/*
196 * Valid machtype for group Broadcom
197 */
198#define MACH_GROUP_BRCM 23 /* Broadcom */
199#define MACH_BCM47XX 1 /* Broadcom BCM47XX */
200
211#define CL_SIZE COMMAND_LINE_SIZE 201#define CL_SIZE COMMAND_LINE_SIZE
212 202
213const char *get_system_type(void); 203const char *get_system_type(void);
214 204
215extern unsigned long mips_machtype; 205extern unsigned long mips_machtype;
216extern unsigned long mips_machgroup;
217 206
218#define BOOT_MEM_MAP_MAX 32 207#define BOOT_MEM_MAP_MAX 32
219#define BOOT_MEM_RAM 1 208#define BOOT_MEM_RAM 1
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index eee83cbdf2b0..fe7dc2d59b69 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
65 65
66#endif /* __GNUC__ */ 66#endif /* __GNUC__ */
67 67
68#if defined (__MIPSEB__) 68#if defined(__MIPSEB__)
69# include <linux/byteorder/big_endian.h> 69# include <linux/byteorder/big_endian.h>
70#elif defined (__MIPSEL__) 70#elif defined(__MIPSEL__)
71# include <linux/byteorder/little_endian.h> 71# include <linux/byteorder/little_endian.h>
72#else 72#else
73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" 73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h
index c5b4708e003b..a5ec0e5dc5b8 100644
--- a/include/asm-mips/cmpxchg.h
+++ b/include/asm-mips/cmpxchg.h
@@ -72,7 +72,7 @@
72 */ 72 */
73extern void __cmpxchg_called_with_bad_pointer(void); 73extern void __cmpxchg_called_with_bad_pointer(void);
74 74
75#define __cmpxchg(ptr,old,new,barrier) \ 75#define __cmpxchg(ptr, old, new, barrier) \
76({ \ 76({ \
77 __typeof__(ptr) __ptr = (ptr); \ 77 __typeof__(ptr) __ptr = (ptr); \
78 __typeof__(*(ptr)) __old = (old); \ 78 __typeof__(*(ptr)) __old = (old); \
@@ -102,6 +102,6 @@ extern void __cmpxchg_called_with_bad_pointer(void);
102}) 102})
103 103
104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) 104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,) 105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, )
106 106
107#endif /* __ASM_CMPXCHG_H */ 107#endif /* __ASM_CMPXCHG_H */
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index d95a83e3e1d7..f6bd308f047f 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -9,11 +9,14 @@
9#ifndef __ASM_CPU_FEATURES_H 9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H 10#define __ASM_CPU_FEATURES_H
11 11
12
13#include <asm/cpu.h> 12#include <asm/cpu.h>
14#include <asm/cpu-info.h> 13#include <asm/cpu-info.h>
15#include <cpu-feature-overrides.h> 14#include <cpu-feature-overrides.h>
16 15
16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
17/* 20/*
18 * SMP assumption: Options of CPU 0 are a superset of all processors. 21 * SMP assumption: Options of CPU 0 are a superset of all processors.
19 * This is true for all known MIPS systems. 22 * This is true for all known MIPS systems.
@@ -35,9 +38,6 @@
35#ifndef cpu_has_tx39_cache 38#ifndef cpu_has_tx39_cache
36#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
37#endif 40#endif
38#ifndef cpu_has_sb1_cache
39#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
40#endif
41#ifndef cpu_has_fpu 41#ifndef cpu_has_fpu
42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 22fe8453fcc7..94f1c8172360 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -14,10 +14,6 @@
14 14
15#include <asm/cache.h> 15#include <asm/cache.h>
16 16
17#ifdef CONFIG_SGI_IP27
18#include <asm/sn/types.h>
19#endif
20
21/* 17/*
22 * Descriptor for a cache 18 * Descriptor for a cache
23 */ 19 */
@@ -43,20 +39,6 @@ struct cache_desc {
43struct cpuinfo_mips { 39struct cpuinfo_mips {
44 unsigned long udelay_val; 40 unsigned long udelay_val;
45 unsigned long asid_cache; 41 unsigned long asid_cache;
46#if defined(CONFIG_SGI_IP27)
47// cpuid_t p_cpuid; /* PROM assigned cpuid */
48 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
49 nasid_t p_nasid; /* my node ID in numa-as-id-space */
50 unsigned char p_slice; /* Physical position on node board */
51#endif
52#if 0
53 unsigned long loops_per_sec;
54 unsigned long ipi_count;
55 unsigned long irq_attempt[NR_IRQS];
56 unsigned long smp_local_irq_count;
57 unsigned long prof_multiplier;
58 unsigned long prof_counter;
59#endif
60 42
61 /* 43 /*
62 * Capability and feature descriptor structure for MIPS CPU 44 * Capability and feature descriptor structure for MIPS CPU
@@ -92,4 +74,7 @@ extern struct cpuinfo_mips cpu_data[];
92extern void cpu_probe(void); 74extern void cpu_probe(void);
93extern void cpu_report(void); 75extern void cpu_report(void);
94 76
77extern const char *__cpu_name[];
78#define cpu_name_string() __cpu_name[smp_processor_id()]
79
95#endif /* __ASM_CPU_INFO_H */ 80#endif /* __ASM_CPU_INFO_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 3857358fb6de..54fc18a4e5a8 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -106,6 +106,13 @@
106#define PRID_IMP_SR71000 0x0400 106#define PRID_IMP_SR71000 0x0400
107 107
108/* 108/*
109 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
110 */
111
112#define PRID_IMP_BCM4710 0x4000
113#define PRID_IMP_BCM3302 0x9000
114
115/*
109 * Definitions for 7:0 on legacy processors 116 * Definitions for 7:0 on legacy processors
110 */ 117 */
111 118
@@ -150,75 +157,55 @@
150 157
151#define FPIR_IMP_NONE 0x0000 158#define FPIR_IMP_NONE 0x0000
152 159
153#define CPU_UNKNOWN 0 160enum cpu_type_enum {
154#define CPU_R2000 1 161 CPU_UNKNOWN,
155#define CPU_R3000 2 162
156#define CPU_R3000A 3 163 /*
157#define CPU_R3041 4 164 * R2000 class processors
158#define CPU_R3051 5 165 */
159#define CPU_R3052 6 166 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
160#define CPU_R3081 7 167 CPU_R3081, CPU_R3081E,
161#define CPU_R3081E 8 168
162#define CPU_R4000PC 9 169 /*
163#define CPU_R4000SC 10 170 * R6000 class processors
164#define CPU_R4000MC 11 171 */
165#define CPU_R4200 12 172 CPU_R6000, CPU_R6000A,
166#define CPU_R4400PC 13 173
167#define CPU_R4400SC 14 174 /*
168#define CPU_R4400MC 15 175 * R4000 class processors
169#define CPU_R4600 16 176 */
170#define CPU_R6000 17 177 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
171#define CPU_R6000A 18 178 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
172#define CPU_R8000 19 179 CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
173#define CPU_R10000 20 180 CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
174#define CPU_R12000 21 181 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
175#define CPU_R4300 22 182 CPU_SR71000, CPU_RM9000, CPU_TX49XX,
176#define CPU_R4650 23 183
177#define CPU_R4700 24 184 /*
178#define CPU_R5000 25 185 * R8000 class processors
179#define CPU_R5000A 26 186 */
180#define CPU_R4640 27 187 CPU_R8000,
181#define CPU_NEVADA 28 188
182#define CPU_RM7000 29 189 /*
183#define CPU_R5432 30 190 * TX3900 class processors
184#define CPU_4KC 31 191 */
185#define CPU_5KC 32 192 CPU_TX3912, CPU_TX3922, CPU_TX3927,
186#define CPU_R4310 33 193
187#define CPU_SB1 34 194 /*
188#define CPU_TX3912 35 195 * MIPS32 class processors
189#define CPU_TX3922 36 196 */
190#define CPU_TX3927 37 197 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
191#define CPU_AU1000 38 198 CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450,
192#define CPU_4KEC 39 199 CPU_BCM3302, CPU_BCM4710,
193#define CPU_4KSC 40 200
194#define CPU_VR41XX 41 201 /*
195#define CPU_R5500 42 202 * MIPS64 class processors
196#define CPU_TX49XX 43 203 */
197#define CPU_AU1500 44 204 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
198#define CPU_20KC 45 205
199#define CPU_VR4111 46 206 CPU_LAST
200#define CPU_VR4121 47 207};
201#define CPU_VR4122 48 208
202#define CPU_VR4131 49
203#define CPU_VR4181 50
204#define CPU_VR4181A 51
205#define CPU_AU1100 52
206#define CPU_SR71000 53
207#define CPU_RM9000 54
208#define CPU_25KF 55
209#define CPU_VR4133 56
210#define CPU_AU1550 57
211#define CPU_24K 58
212#define CPU_AU1200 59
213#define CPU_34K 60
214#define CPU_PR4450 61
215#define CPU_SB1A 62
216#define CPU_74K 63
217#define CPU_R14000 64
218#define CPU_LOONGSON1 65
219#define CPU_LOONGSON2 66
220
221#define CPU_LAST 66
222 209
223/* 210/*
224 * ISA Level encodings 211 * ISA Level encodings
@@ -247,24 +234,23 @@
247#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 234#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
248#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 235#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
249#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 236#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
250#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ 237#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
251#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ 238#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
252#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ 239#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
253#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ 240#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
254#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ 241#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
255#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ 242#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
256#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ 243#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
257#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ 244#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
258#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ 245#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
259#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ 246#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
260#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ 247#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
261#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ 248#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
262#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ 249#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
263#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ 250#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
264#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 251#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
265#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 252#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
266#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 253#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
267#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
268 254
269/* 255/*
270 * CPU ASE encodings 256 * CPU ASE encodings
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index 223d156efb9f..fab32131e9b4 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -81,7 +81,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
81 81
82#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val 82#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
83 83
84#define udelay(usecs) __udelay((usecs),__udelay_val) 84#define udelay(usecs) __udelay((usecs), __udelay_val)
85 85
86/* make sure "usecs *= ..." in udelay do not overflow. */ 86/* make sure "usecs *= ..." in udelay do not overflow. */
87#if HZ >= 1000 87#if HZ >= 1000
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index e7d95d48177d..766f91ad5cd3 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -319,7 +319,7 @@ do { \
319struct task_struct; 319struct task_struct;
320 320
321extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); 321extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
322extern int dump_task_regs (struct task_struct *, elf_gregset_t *); 322extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
323extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 323extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
324 324
325#define ELF_CORE_COPY_REGS(elf_regs, regs) \ 325#define ELF_CORE_COPY_REGS(elf_regs, regs) \
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index 02c8a13fc894..f27b96cfac2e 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -60,8 +60,8 @@ enum fixed_addresses {
60 __end_of_fixed_addresses 60 __end_of_fixed_addresses
61}; 61};
62 62
63extern void __set_fixmap (enum fixed_addresses idx, 63extern void __set_fixmap(enum fixed_addresses idx,
64 unsigned long phys, pgprot_t flags); 64 unsigned long phys, pgprot_t flags);
65 65
66#define set_fixmap(idx, phys) \ 66#define set_fixmap(idx, phys) \
67 __set_fixmap(idx, phys, PAGE_KERNEL) 67 __set_fixmap(idx, phys, PAGE_KERNEL)
diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h
index aa1ef8b352cc..a62d0990c8ae 100644
--- a/include/asm-mips/floppy.h
+++ b/include/asm-mips/floppy.h
@@ -10,9 +10,11 @@
10#ifndef _ASM_FLOPPY_H 10#ifndef _ASM_FLOPPY_H
11#define _ASM_FLOPPY_H 11#define _ASM_FLOPPY_H
12 12
13#include <linux/dma-mapping.h>
14
13static inline void fd_cacheflush(char * addr, long size) 15static inline void fd_cacheflush(char * addr, long size)
14{ 16{
15 dma_cache_wback_inv((unsigned long)addr,size); 17 dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL);
16} 18}
17 19
18#define MAX_BUFFER_SECTORS 24 20#define MAX_BUFFER_SECTORS 24
@@ -47,7 +49,7 @@ static inline void fd_cacheflush(char * addr, long size)
47 * Actually this needs to be a bit more complicated since the so much different 49 * Actually this needs to be a bit more complicated since the so much different
48 * hardware available with MIPS CPUs ... 50 * hardware available with MIPS CPUs ...
49 */ 51 */
50#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) 52#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
51 53
52#define EXTRA_FLOPPY_PARAMS 54#define EXTRA_FLOPPY_PARAMS
53 55
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index b623882bce19..3e7e30d4f418 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -75,7 +75,7 @@
75} 75}
76 76
77static inline int 77static inline int
78futex_atomic_op_inuser (int encoded_op, int __user *uaddr) 78futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
79{ 79{
80 int op = (encoded_op >> 28) & 7; 80 int op = (encoded_op >> 28) & 7;
81 int cmp = (encoded_op >> 24) & 15; 81 int cmp = (encoded_op >> 24) & 15;
diff --git a/include/asm-mips/arc/hinv.h b/include/asm-mips/fw/arc/hinv.h
index ee792bf04002..e6ff4add04e2 100644
--- a/include/asm-mips/arc/hinv.h
+++ b/include/asm-mips/fw/arc/hinv.h
@@ -4,7 +4,8 @@
4#ifndef _ASM_ARC_HINV_H 4#ifndef _ASM_ARC_HINV_H
5#define _ASM_ARC_HINV_H 5#define _ASM_ARC_HINV_H
6 6
7#include <asm/arc/types.h> 7#include <asm/sgidefs.h>
8#include <asm/fw/arc/types.h>
8 9
9/* configuration query defines */ 10/* configuration query defines */
10typedef enum configclass { 11typedef enum configclass {
@@ -110,7 +111,7 @@ union key_u {
110 ULONG FullKey; 111 ULONG FullKey;
111}; 112};
112 113
113#if _MIPS_SIM == _ABI64 114#if _MIPS_SIM == _MIPS_SIM_ABI64
114#define SGI_ARCS_VERS 64 /* sgi 64-bit version */ 115#define SGI_ARCS_VERS 64 /* sgi 64-bit version */
115#define SGI_ARCS_REV 0 /* rev .00 */ 116#define SGI_ARCS_REV 0 /* rev .00 */
116#else 117#else
diff --git a/include/asm-mips/arc/types.h b/include/asm-mips/fw/arc/types.h
index b9adcd6f0860..b9adcd6f0860 100644
--- a/include/asm-mips/arc/types.h
+++ b/include/asm-mips/fw/arc/types.h
diff --git a/arch/mips/sibyte/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h
index d8230cc53b81..41cf050b6810 100644
--- a/arch/mips/sibyte/cfe/cfe_api.h
+++ b/include/asm-mips/fw/cfe/cfe_api.h
@@ -136,25 +136,25 @@ int64_t cfe_getticks(void);
136 */ 136 */
137#ifdef CFE_API_IMPL_NAMESPACE 137#ifdef CFE_API_IMPL_NAMESPACE
138#define cfe_close(a) __cfe_close(a) 138#define cfe_close(a) __cfe_close(a)
139#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e) 139#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e)
140#define cfe_cpu_stop(a) __cfe_cpu_stop(a) 140#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
141#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f) 141#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f)
142#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e) 142#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e)
143#define cfe_exit(a,b) __cfe_exit(a,b) 143#define cfe_exit(a, b) __cfe_exit(a, b)
144#define cfe_flushcache(a) __cfe_cacheflush(a) 144#define cfe_flushcache(a) __cfe_cacheflush(a)
145#define cfe_getdevinfo(a) __cfe_getdevinfo(a) 145#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
146#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c) 146#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c)
147#define cfe_getfwinfo(a) __cfe_getfwinfo(a) 147#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
148#define cfe_getstdhandle(a) __cfe_getstdhandle(a) 148#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
149#define cfe_init(a,b) __cfe_init(a,b) 149#define cfe_init(a, b) __cfe_init(a, b)
150#define cfe_inpstat(a) __cfe_inpstat(a) 150#define cfe_inpstat(a) __cfe_inpstat(a)
151#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f) 151#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f)
152#define cfe_open(a) __cfe_open(a) 152#define cfe_open(a) __cfe_open(a)
153#define cfe_read(a,b,c) __cfe_read(a,b,c) 153#define cfe_read(a, b, c) __cfe_read(a, b, c)
154#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d) 154#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d)
155#define cfe_setenv(a,b) __cfe_setenv(a,b) 155#define cfe_setenv(a, b) __cfe_setenv(a, b)
156#define cfe_write(a,b,c) __cfe_write(a,b,c) 156#define cfe_write(a, b, c) __cfe_write(a, b, c)
157#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d) 157#define cfe_writeblk(a, b, c, d __cfe_writeblk(a, b, c, d)
158#endif /* CFE_API_IMPL_NAMESPACE */ 158#endif /* CFE_API_IMPL_NAMESPACE */
159 159
160int cfe_close(int handle); 160int cfe_close(int handle);
diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h
index 975f00002cbe..975f00002cbe 100644
--- a/arch/mips/sibyte/cfe/cfe_error.h
+++ b/include/asm-mips/fw/cfe/cfe_error.h
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 6a5fa32f615b..2de638f84c86 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -10,11 +10,12 @@
10#ifndef _ASM_HAZARDS_H 10#ifndef _ASM_HAZARDS_H
11#define _ASM_HAZARDS_H 11#define _ASM_HAZARDS_H
12 12
13
14#ifdef __ASSEMBLY__ 13#ifdef __ASSEMBLY__
15#define ASMMACRO(name, code...) .macro name; code; .endm 14#define ASMMACRO(name, code...) .macro name; code; .endm
16#else 15#else
17 16
17#include <asm/cpu-features.h>
18
18#define ASMMACRO(name, code...) \ 19#define ASMMACRO(name, code...) \
19__asm__(".macro " #name "; " #code "; .endm"); \ 20__asm__(".macro " #name "; " #code "; .endm"); \
20 \ 21 \
@@ -86,6 +87,57 @@ do { \
86 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
87} while (0) 88} while (0)
88 89
90#elif defined(CONFIG_CPU_MIPSR1)
91
92/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to
94 * run fine on R2 processors.
95 */
96ASMMACRO(mtc0_tlbw_hazard,
97 _ssnop; _ssnop; _ehb
98 )
99ASMMACRO(tlbw_use_hazard,
100 _ssnop; _ssnop; _ssnop; _ehb
101 )
102ASMMACRO(tlb_probe_hazard,
103 _ssnop; _ssnop; _ssnop; _ehb
104 )
105ASMMACRO(irq_enable_hazard,
106 _ssnop; _ssnop; _ssnop; _ehb
107 )
108ASMMACRO(irq_disable_hazard,
109 _ssnop; _ssnop; _ssnop; _ehb
110 )
111ASMMACRO(back_to_back_c0_hazard,
112 _ssnop; _ssnop; _ssnop; _ehb
113 )
114/*
115 * gcc has a tradition of misscompiling the previous construct using the
116 * address of a label as argument to inline assembler. Gas otoh has the
117 * annoying difference between la and dla which are only usable for 32-bit
118 * rsp. 64-bit code, so can't be used without conditional compilation.
119 * The alterantive is switching the assembler to 64-bit code which happens
120 * to work right even for 32-bit code ...
121 */
122#define __instruction_hazard() \
123do { \
124 unsigned long tmp; \
125 \
126 __asm__ __volatile__( \
127 " .set mips64r2 \n" \
128 " dla %0, 1f \n" \
129 " jr.hb %0 \n" \
130 " .set mips0 \n" \
131 "1: \n" \
132 : "=r" (tmp)); \
133} while (0)
134
135#define instruction_hazard() \
136do { \
137 if (cpu_has_mips_r2) \
138 __instruction_hazard(); \
139} while (0)
140
89#elif defined(CONFIG_CPU_R10000) 141#elif defined(CONFIG_CPU_R10000)
90 142
91/* 143/*
@@ -193,7 +245,7 @@ ASMMACRO(enable_fpu_hazard,
193 .set mips64; 245 .set mips64;
194 .set noreorder; 246 .set noreorder;
195 _ssnop; 247 _ssnop;
196 bnezl $0,.+4; 248 bnezl $0, .+4;
197 _ssnop; 249 _ssnop;
198 .set pop 250 .set pop
199) 251)
diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h
index 458d9fdc76bf..aca05a43a97b 100644
--- a/include/asm-mips/hw_irq.h
+++ b/include/asm-mips/hw_irq.h
@@ -8,15 +8,8 @@
8#ifndef __ASM_HW_IRQ_H 8#ifndef __ASM_HW_IRQ_H
9#define __ASM_HW_IRQ_H 9#define __ASM_HW_IRQ_H
10 10
11#include <linux/profile.h>
12#include <asm/atomic.h> 11#include <asm/atomic.h>
13 12
14extern void disable_8259A_irq(unsigned int irq);
15extern void enable_8259A_irq(unsigned int irq);
16extern int i8259A_irq_pending(unsigned int irq);
17extern void make_8259A_irq(unsigned int irq);
18extern void init_8259A(int aeoi);
19
20extern atomic_t irq_err_count; 13extern atomic_t irq_err_count;
21 14
22/* 15/*
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
new file mode 100644
index 000000000000..8f689d7df6b1
--- /dev/null
+++ b/include/asm-mips/i8253.h
@@ -0,0 +1,30 @@
1/*
2 * Machine specific IO port address definition for generic.
3 * Written by Osamu Tomita <tomita@cinet.co.jp>
4 */
5#ifndef _MACH_IO_PORTS_H
6#define _MACH_IO_PORTS_H
7
8/* i8253A PIT registers */
9#define PIT_MODE 0x43
10#define PIT_CH0 0x40
11#define PIT_CH2 0x42
12
13/* i8259A PIC registers */
14#define PIC_MASTER_CMD 0x20
15#define PIC_MASTER_IMR 0x21
16#define PIC_MASTER_ISR PIC_MASTER_CMD
17#define PIC_MASTER_POLL PIC_MASTER_ISR
18#define PIC_MASTER_OCW3 PIC_MASTER_ISR
19#define PIC_SLAVE_CMD 0xa0
20#define PIC_SLAVE_IMR 0xa1
21
22/* i8259A PIC related value */
23#define PIC_CASCADE_IR 2
24#define MASTER_ICW4_DEFAULT 0x01
25#define SLAVE_ICW4_DEFAULT 0x01
26#define PIC_ICW4_AEOI 2
27
28extern void setup_pit_timer(void);
29
30#endif /* !_MACH_IO_PORTS_H */
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
index e88a01607fea..8572a2d90484 100644
--- a/include/asm-mips/i8259.h
+++ b/include/asm-mips/i8259.h
@@ -37,9 +37,8 @@
37 37
38extern spinlock_t i8259A_lock; 38extern spinlock_t i8259A_lock;
39 39
40extern void init_8259A(int auto_eoi); 40extern int i8259A_irq_pending(unsigned int irq);
41extern void enable_8259A_irq(unsigned int irq); 41extern void make_8259A_irq(unsigned int irq);
42extern void disable_8259A_irq(unsigned int irq);
43 42
44extern void init_i8259_irqs(void); 43extern void init_i8259_irqs(void);
45 44
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
index 92d90f75a636..cc88aed23f0f 100644
--- a/include/asm-mips/inventory.h
+++ b/include/asm-mips/inventory.h
@@ -17,8 +17,8 @@ typedef struct inventory_s {
17 17
18extern int inventory_items; 18extern int inventory_items;
19 19
20extern void add_to_inventory (int class, int type, int controller, int unit, int state); 20extern void add_to_inventory(int class, int type, int controller, int unit, int state);
21extern int dump_inventory_to_user (void __user *userbuf, int size); 21extern int dump_inventory_to_user(void __user *userbuf, int size);
22extern int __init init_inventory(void); 22extern int __init init_inventory(void);
23 23
24#endif /* __ASM_INVENTORY_H */ 24#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 7ba92890ea13..2cd8323c8586 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -40,11 +40,11 @@
40 * hardware. An example use would be for flash memory that's used for 40 * hardware. An example use would be for flash memory that's used for
41 * execute in place. 41 * execute in place.
42 */ 42 */
43# define __raw_ioswabb(a,x) (x) 43# define __raw_ioswabb(a, x) (x)
44# define __raw_ioswabw(a,x) (x) 44# define __raw_ioswabw(a, x) (x)
45# define __raw_ioswabl(a,x) (x) 45# define __raw_ioswabl(a, x) (x)
46# define __raw_ioswabq(a,x) (x) 46# define __raw_ioswabq(a, x) (x)
47# define ____raw_ioswabq(a,x) (x) 47# define ____raw_ioswabq(a, x) (x)
48 48
49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
50 50
@@ -561,9 +561,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
561extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 561extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
562extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 562extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
563 563
564#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) 564#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
565#define dma_cache_wback(start, size) _dma_cache_wback(start,size) 565#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
566#define dma_cache_inv(start, size) _dma_cache_inv(start,size) 566#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
567 567
568#else /* Sane hardware */ 568#else /* Sane hardware */
569 569
@@ -587,7 +587,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
587#define __CSR_32_ADJUST 0 587#define __CSR_32_ADJUST 0
588#endif 588#endif
589 589
590#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 590#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
591#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 591#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
592 592
593/* 593/*
diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h
index 2036fcb9f117..85067e248a83 100644
--- a/include/asm-mips/ioctl.h
+++ b/include/asm-mips/ioctl.h
@@ -54,7 +54,7 @@
54#define _IOC_IN 0x80000000 54#define _IOC_IN 0x80000000
55#define _IOC_INOUT (IOC_IN|IOC_OUT) 55#define _IOC_INOUT (IOC_IN|IOC_OUT)
56 56
57#define _IOC(dir,type,nr,size) \ 57#define _IOC(dir, type, nr, size) \
58 (((dir) << _IOC_DIRSHIFT) | \ 58 (((dir) << _IOC_DIRSHIFT) | \
59 ((type) << _IOC_TYPESHIFT) | \ 59 ((type) << _IOC_TYPESHIFT) | \
60 ((nr) << _IOC_NRSHIFT) | \ 60 ((nr) << _IOC_NRSHIFT) | \
@@ -68,13 +68,13 @@ extern unsigned int __invalid_size_argument_for_IOC;
68 sizeof(t) : __invalid_size_argument_for_IOC) 68 sizeof(t) : __invalid_size_argument_for_IOC)
69 69
70/* used to create numbers */ 70/* used to create numbers */
71#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) 71#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
72#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) 72#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
73#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) 73#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
74#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) 74#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
75#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) 75#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
76#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) 76#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
77#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) 77#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
78 78
79 79
80/* used to decode them.. */ 80/* used to decode them.. */
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
index 5097cbf183a9..3f04a995ec54 100644
--- a/include/asm-mips/ioctls.h
+++ b/include/asm-mips/ioctls.h
@@ -77,12 +77,12 @@
77#define TIOCSBRK 0x5427 /* BSD compatibility */ 77#define TIOCSBRK 0x5427 /* BSD compatibility */
78#define TIOCCBRK 0x5428 /* BSD compatibility */ 78#define TIOCCBRK 0x5428 /* BSD compatibility */
79#define TIOCGSID 0x7416 /* Return the session ID of FD */ 79#define TIOCGSID 0x7416 /* Return the session ID of FD */
80#define TCGETS2 _IOR('T',0x2A, struct termios2) 80#define TCGETS2 _IOR('T', 0x2A, struct termios2)
81#define TCSETS2 _IOW('T',0x2B, struct termios2) 81#define TCSETS2 _IOW('T', 0x2B, struct termios2)
82#define TCSETSW2 _IOW('T',0x2C, struct termios2) 82#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
83#define TCSETSF2 _IOW('T',0x2D, struct termios2) 83#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
84#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 84#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
85#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 85#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */
86 86
87/* I hope the range from 0x5480 on is free ... */ 87/* I hope the range from 0x5480 on is free ... */
88#define TIOCSCTTY 0x5480 /* become controlling tty */ 88#define TIOCSCTTY 0x5480 /* become controlling tty */
diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h
deleted file mode 100644
index 1b631b8da6f8..000000000000
--- a/include/asm-mips/ip32/machine.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * machine.h -- Machine/group probing for ip32
3 *
4 * Copyright (C) 2001 Keith M Wesolowski
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10#ifndef _ASM_IP32_MACHINE_H
11#define _ASM_IP32_MACHINE_H
12
13
14#ifdef CONFIG_SGI_IP32
15
16#define SGI_MACH_O2 0x3201
17
18#endif /* CONFIG_SGI_IP32 */
19
20#endif /* _ASM_SGI_MACHINE_H */
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 2cb52cf8bd4e..a58f0eecc68f 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -46,6 +46,38 @@ static inline void smtc_im_ack_irq(unsigned int irq)
46 46
47#endif /* CONFIG_MIPS_MT_SMTC */ 47#endif /* CONFIG_MIPS_MT_SMTC */
48 48
49#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
50#include <linux/cpumask.h>
51
52extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity);
53extern void smtc_forward_irq(unsigned int irq);
54
55/*
56 * IRQ affinity hook invoked at the beginning of interrupt dispatch
57 * if option is enabled.
58 *
59 * Up through Linux 2.6.22 (at least) cpumask operations are very
60 * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
61 * used a "fast path" per-IRQ-descriptor cache of affinity information
62 * to reduce latency. As there is a project afoot to optimize the
63 * cpumask implementations, this version is optimistically assuming
64 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
65 */
66#define IRQ_AFFINITY_HOOK(irq) \
67do { \
68 if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \
69 smtc_forward_irq(irq); \
70 irq_exit(); \
71 return; \
72 } \
73} while (0)
74
75#else /* Not doing SMTC affinity */
76
77#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
78
79#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
80
49#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP 81#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
50 82
51/* 83/*
@@ -56,13 +88,27 @@ static inline void smtc_im_ack_irq(unsigned int irq)
56 */ 88 */
57#define __DO_IRQ_SMTC_HOOK(irq) \ 89#define __DO_IRQ_SMTC_HOOK(irq) \
58do { \ 90do { \
91 IRQ_AFFINITY_HOOK(irq); \
59 if (irq_hwmask[irq] & 0x0000ff00) \ 92 if (irq_hwmask[irq] & 0x0000ff00) \
60 write_c0_tccontext(read_c0_tccontext() & \ 93 write_c0_tccontext(read_c0_tccontext() & \
61 ~(irq_hwmask[irq] & 0x0000ff00)); \ 94 ~(irq_hwmask[irq] & 0x0000ff00)); \
95} while (0)
96
97#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
98do { \
99 if (irq_hwmask[irq] & 0x0000ff00) \
100 write_c0_tccontext(read_c0_tccontext() & \
101 ~(irq_hwmask[irq] & 0x0000ff00)); \
62} while (0) 102} while (0)
103
63#else 104#else
64 105
65#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) 106#define __DO_IRQ_SMTC_HOOK(irq) \
107do { \
108 IRQ_AFFINITY_HOOK(irq); \
109} while (0)
110#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
111
66#endif 112#endif
67 113
68/* 114/*
@@ -81,6 +127,23 @@ do { \
81 irq_exit(); \ 127 irq_exit(); \
82} while (0) 128} while (0)
83 129
130#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
131/*
132 * To avoid inefficient and in some cases pathological re-checking of
133 * IRQ affinity, we have this variant that skips the affinity check.
134 */
135
136
137#define do_IRQ_no_affinity(irq) \
138do { \
139 irq_enter(); \
140 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
141 generic_handle_irq(irq); \
142 irq_exit(); \
143} while (0)
144
145#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
146
84extern void arch_init_irq(void); 147extern void arch_init_irq(void);
85extern void spurious_interrupt(void); 148extern void spurious_interrupt(void);
86 149
diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h
new file mode 100644
index 000000000000..f9a7c3ac2e66
--- /dev/null
+++ b/include/asm-mips/irq_gt641xx.h
@@ -0,0 +1,60 @@
1/*
2 * Galileo/Marvell GT641xx IRQ definitions.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#ifndef _ASM_IRQ_GT641XX_H
21#define _ASM_IRQ_GT641XX_H
22
23#ifndef GT641XX_IRQ_BASE
24#define GT641XX_IRQ_BASE 8
25#endif
26
27#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
28#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
29#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
30#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
31#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
32#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
33#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
34#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
35#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
36#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
37#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
38#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
39#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
40#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
41#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
42#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
43#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
44#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
45#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
46#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
47#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
48#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
49#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
50#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
51#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
52#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
53#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
54#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
55#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
56
57extern void gt641xx_irq_dispatch(void);
58extern void gt641xx_irq_init(void);
59
60#endif /* _ASM_IRQ_GT641XX_H */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
index e459fa05db83..881e8866501d 100644
--- a/include/asm-mips/irqflags.h
+++ b/include/asm-mips/irqflags.h
@@ -16,7 +16,7 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <asm/hazards.h> 17#include <asm/hazards.h>
18 18
19__asm__ ( 19__asm__(
20 " .macro raw_local_irq_enable \n" 20 " .macro raw_local_irq_enable \n"
21 " .set push \n" 21 " .set push \n"
22 " .set reorder \n" 22 " .set reorder \n"
@@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void)
65 * 65 *
66 * Workaround: mask EXL bit of the result or place a nop before mfc0. 66 * Workaround: mask EXL bit of the result or place a nop before mfc0.
67 */ 67 */
68__asm__ ( 68__asm__(
69 " .macro raw_local_irq_disable\n" 69 " .macro raw_local_irq_disable\n"
70 " .set push \n" 70 " .set push \n"
71 " .set noat \n" 71 " .set noat \n"
@@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void)
96 : "memory"); 96 : "memory");
97} 97}
98 98
99__asm__ ( 99__asm__(
100 " .macro raw_local_save_flags flags \n" 100 " .macro raw_local_save_flags flags \n"
101 " .set push \n" 101 " .set push \n"
102 " .set reorder \n" 102 " .set reorder \n"
@@ -113,7 +113,7 @@ __asm__ __volatile__( \
113 "raw_local_save_flags %0" \ 113 "raw_local_save_flags %0" \
114 : "=r" (x)) 114 : "=r" (x))
115 115
116__asm__ ( 116__asm__(
117 " .macro raw_local_irq_save result \n" 117 " .macro raw_local_irq_save result \n"
118 " .set push \n" 118 " .set push \n"
119 " .set reorder \n" 119 " .set reorder \n"
@@ -145,7 +145,7 @@ __asm__ __volatile__( \
145 : /* no inputs */ \ 145 : /* no inputs */ \
146 : "memory") 146 : "memory")
147 147
148__asm__ ( 148__asm__(
149 " .macro raw_local_irq_restore flags \n" 149 " .macro raw_local_irq_restore flags \n"
150 " .set push \n" 150 " .set push \n"
151 " .set noreorder \n" 151 " .set noreorder \n"
diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h
index 81cbf004fd13..83f449dec95e 100644
--- a/include/asm-mips/jazz.h
+++ b/include/asm-mips/jazz.h
@@ -185,37 +185,25 @@ typedef struct {
185#define JAZZ_IO_IRQ_ENABLE 0xe0010002 185#define JAZZ_IO_IRQ_ENABLE 0xe0010002
186 186
187/* 187/*
188 * JAZZ interrupt enable bits
189 */
190#define JAZZ_IE_PARALLEL (1 << 0)
191#define JAZZ_IE_FLOPPY (1 << 1)
192#define JAZZ_IE_SOUND (1 << 2)
193#define JAZZ_IE_VIDEO (1 << 3)
194#define JAZZ_IE_ETHERNET (1 << 4)
195#define JAZZ_IE_SCSI (1 << 5)
196#define JAZZ_IE_KEYBOARD (1 << 6)
197#define JAZZ_IE_MOUSE (1 << 7)
198#define JAZZ_IE_SERIAL1 (1 << 8)
199#define JAZZ_IE_SERIAL2 (1 << 9)
200
201/*
202 * JAZZ Interrupt Level definitions 188 * JAZZ Interrupt Level definitions
203 * 189 *
204 * This is somewhat broken. For reasons which nobody can remember anymore 190 * This is somewhat broken. For reasons which nobody can remember anymore
205 * we remap the Jazz interrupts to the usual ISA style interrupt numbers. 191 * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
206 */ 192 */
207#define JAZZ_PARALLEL_IRQ 16 193#define JAZZ_IRQ_START 24
208#define JAZZ_FLOPPY_IRQ 17 194#define JAZZ_IRQ_END (24 + 9)
209#define JAZZ_SOUND_IRQ 18 195#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0)
210#define JAZZ_VIDEO_IRQ 19 196#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1)
211#define JAZZ_ETHERNET_IRQ 20 197#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2)
212#define JAZZ_SCSI_IRQ 21 198#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3)
213#define JAZZ_KEYBOARD_IRQ 22 199#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4)
214#define JAZZ_MOUSE_IRQ 23 200#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5)
215#define JAZZ_SERIAL1_IRQ 24 201#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6)
216#define JAZZ_SERIAL2_IRQ 25 202#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7)
217 203#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8)
218#define JAZZ_TIMER_IRQ 31 204#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9)
205
206#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
219 207
220 208
221/* 209/*
diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h
index 0a205b77e505..8bb37bba68f0 100644
--- a/include/asm-mips/jazzdma.h
+++ b/include/asm-mips/jazzdma.h
@@ -7,7 +7,6 @@
7/* 7/*
8 * Prototypes and macros 8 * Prototypes and macros
9 */ 9 */
10extern void vdma_init(void);
11extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); 10extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
12extern int vdma_free(unsigned long laddr); 11extern int vdma_free(unsigned long laddr);
13extern int vdma_remap(unsigned long laddr, unsigned long paddr, 12extern int vdma_remap(unsigned long laddr, unsigned long paddr,
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 4be2f25f70dd..211bcf47fffb 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -53,23 +53,23 @@ struct tx3927_dma_reg {
53#include <asm/byteorder.h> 53#include <asm/byteorder.h>
54 54
55#ifdef __BIG_ENDIAN 55#ifdef __BIG_ENDIAN
56#define endian_def_s2(e1,e2) \ 56#define endian_def_s2(e1, e2) \
57 volatile unsigned short e1,e2 57 volatile unsigned short e1, e2
58#define endian_def_sb2(e1,e2,e3) \ 58#define endian_def_sb2(e1, e2, e3) \
59 volatile unsigned short e1;volatile unsigned char e2,e3 59 volatile unsigned short e1;volatile unsigned char e2, e3
60#define endian_def_b2s(e1,e2,e3) \ 60#define endian_def_b2s(e1, e2, e3) \
61 volatile unsigned char e1,e2;volatile unsigned short e3 61 volatile unsigned char e1, e2;volatile unsigned short e3
62#define endian_def_b4(e1,e2,e3,e4) \ 62#define endian_def_b4(e1, e2, e3, e4) \
63 volatile unsigned char e1,e2,e3,e4 63 volatile unsigned char e1, e2, e3, e4
64#else 64#else
65#define endian_def_s2(e1,e2) \ 65#define endian_def_s2(e1, e2) \
66 volatile unsigned short e2,e1 66 volatile unsigned short e2, e1
67#define endian_def_sb2(e1,e2,e3) \ 67#define endian_def_sb2(e1, e2, e3) \
68 volatile unsigned char e3,e2;volatile unsigned short e1 68 volatile unsigned char e3, e2;volatile unsigned short e1
69#define endian_def_b2s(e1,e2,e3) \ 69#define endian_def_b2s(e1, e2, e3) \
70 volatile unsigned short e3;volatile unsigned char e2,e1 70 volatile unsigned short e3;volatile unsigned char e2, e1
71#define endian_def_b4(e1,e2,e3,e4) \ 71#define endian_def_b4(e1, e2, e3, e4) \
72 volatile unsigned char e4,e3,e2,e1 72 volatile unsigned char e4, e3, e2, e1
73#endif 73#endif
74 74
75struct tx3927_pcic_reg { 75struct tx3927_pcic_reg {
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
new file mode 100644
index 000000000000..edcd7544b358
--- /dev/null
+++ b/include/asm-mips/lasat/ds1603.h
@@ -0,0 +1,18 @@
1#include <asm/addrspace.h>
2
3/* Lasat 100 */
4#define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
5#define DS1603_RST_100 (1 << 2)
6#define DS1603_CLK_100 (1 << 0)
7#define DS1603_DATA_SHIFT_100 1
8#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100)
9
10/* Lasat 200 */
11#define DS1603_REG_200 (KSEG1ADDR(0x11000000))
12#define DS1603_RST_200 (1 << 3)
13#define DS1603_CLK_200 (1 << 4)
14#define DS1603_DATA_200 (1 << 5)
15
16#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000)
17#define DS1603_DATA_READ_SHIFT_200 9
18#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
new file mode 100644
index 000000000000..3dac203697fa
--- /dev/null
+++ b/include/asm-mips/lasat/eeprom.h
@@ -0,0 +1,17 @@
1#include <asm/addrspace.h>
2
3/* lasat 100 */
4#define AT93C_REG_100 KSEG1ADDR(0x1c810000)
5#define AT93C_RDATA_REG_100 AT93C_REG_100
6#define AT93C_RDATA_SHIFT_100 4
7#define AT93C_WDATA_SHIFT_100 4
8#define AT93C_CS_M_100 (1 << 5)
9#define AT93C_CLK_M_100 (1 << 3)
10
11/* lasat 200 */
12#define AT93C_REG_200 KSEG1ADDR(0x11000000)
13#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000)
14#define AT93C_RDATA_SHIFT_200 8
15#define AT93C_WDATA_SHIFT_200 2
16#define AT93C_CS_M_200 (1 << 0)
17#define AT93C_CLK_M_200 (1 << 1)
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
new file mode 100644
index 000000000000..f5589f31a197
--- /dev/null
+++ b/include/asm-mips/lasat/head.h
@@ -0,0 +1,22 @@
1/*
2 * Image header stuff
3 */
4#ifndef _HEAD_H
5#define _HEAD_H
6
7#define LASAT_K_MAGIC0_VAL 0xfedeabba
8#define LASAT_K_MAGIC1_VAL 0x00bedead
9
10#ifndef _LANGUAGE_ASSEMBLY
11#include <linux/types.h>
12struct bootloader_header {
13 u32 magic[2];
14 u32 version;
15 u32 image_start;
16 u32 image_size;
17 u32 kernel_start;
18 u32 kernel_entry;
19};
20#endif
21
22#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
new file mode 100644
index 000000000000..ea04d9262edc
--- /dev/null
+++ b/include/asm-mips/lasat/lasat.h
@@ -0,0 +1,256 @@
1/*
2 * lasat.h
3 *
4 * Thomas Horsten <thh@lasat.com>
5 * Copyright (C) 2000 LASAT Networks A/S.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Configuration for LASAT boards, loads the appropriate include files.
21 */
22#ifndef _LASAT_H
23#define _LASAT_H
24
25#ifndef _LANGUAGE_ASSEMBLY
26
27extern struct lasat_misc {
28 volatile u32 *reset_reg;
29 volatile u32 *flash_wp_reg;
30 u32 flash_wp_bit;
31} *lasat_misc;
32
33enum lasat_mtdparts {
34 LASAT_MTD_BOOTLOADER,
35 LASAT_MTD_SERVICE,
36 LASAT_MTD_NORMAL,
37 LASAT_MTD_CONFIG,
38 LASAT_MTD_FS,
39 LASAT_MTD_LAST
40};
41
42/*
43 * The format of the data record in the EEPROM.
44 * See Documentation/LASAT/eeprom.txt for a detailed description
45 * of the fields in this struct, and the LASAT Hardware Configuration
46 * field specification for a detailed description of the config
47 * field.
48 */
49#include <linux/types.h>
50
51#define LASAT_EEPROM_VERSION 7
52struct lasat_eeprom_struct {
53 unsigned int version;
54 unsigned int cfg[3];
55 unsigned char hwaddr[6];
56 unsigned char print_partno[12];
57 unsigned char term0;
58 unsigned char print_serial[14];
59 unsigned char term1;
60 unsigned char prod_partno[12];
61 unsigned char term2;
62 unsigned char prod_serial[14];
63 unsigned char term3;
64 unsigned char passwd_hash[16];
65 unsigned char pwdnull;
66 unsigned char vendid;
67 unsigned char ts_ref;
68 unsigned char ts_signoff;
69 unsigned char reserved[11];
70 unsigned char debugaccess;
71 unsigned short prid;
72 unsigned int serviceflag;
73 unsigned int ipaddr;
74 unsigned int netmask;
75 unsigned int crc32;
76};
77
78struct lasat_eeprom_struct_pre7 {
79 unsigned int version;
80 unsigned int flags[3];
81 unsigned char hwaddr0[6];
82 unsigned char hwaddr1[6];
83 unsigned char print_partno[9];
84 unsigned char term0;
85 unsigned char print_serial[14];
86 unsigned char term1;
87 unsigned char prod_partno[9];
88 unsigned char term2;
89 unsigned char prod_serial[14];
90 unsigned char term3;
91 unsigned char passwd_hash[24];
92 unsigned char pwdnull;
93 unsigned char vendor;
94 unsigned char ts_ref;
95 unsigned char ts_signoff;
96 unsigned char reserved[6];
97 unsigned int writecount;
98 unsigned int ipaddr;
99 unsigned int netmask;
100 unsigned int crc32;
101};
102
103/* Configuration descriptor encoding - see the doc for details */
104
105#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf)
106#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf)
107#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf)
108#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf)
109#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf)
110#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf)
111#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf)
112#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf)
113
114#define LASAT_W1_EDHAC(v) (((v)) & 0xf)
115#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1)
116#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1)
117#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1)
118#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1)
119#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1)
120#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1)
121#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1)
122#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf)
123#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf)
124#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf)
125#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf)
126#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf)
127
128/* Routines specific to LASAT boards */
129
130#define LASAT_BMID_MASQUERADE2 0
131#define LASAT_BMID_MASQUERADEPRO 1
132#define LASAT_BMID_SAFEPIPE25 2
133#define LASAT_BMID_SAFEPIPE50 3
134#define LASAT_BMID_SAFEPIPE100 4
135#define LASAT_BMID_SAFEPIPE5000 5
136#define LASAT_BMID_SAFEPIPE7000 6
137#define LASAT_BMID_SAFEPIPE1000 7
138#if 0
139#define LASAT_BMID_SAFEPIPE30 7
140#define LASAT_BMID_SAFEPIPE5100 8
141#define LASAT_BMID_SAFEPIPE7100 9
142#endif
143#define LASAT_BMID_UNKNOWN 0xf
144#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */
145
146#define LASAT_HAS_EDHAC (1 << 0)
147#define LASAT_EDHAC_FAST (1 << 1)
148#define LASAT_HAS_EADI (1 << 2)
149#define LASAT_HAS_HIFN (1 << 3)
150#define LASAT_HAS_ISDN (1 << 4)
151#define LASAT_HAS_LEASEDLINE_IF (1 << 5)
152#define LASAT_HAS_HDC (1 << 6)
153
154#define LASAT_PRID_MASQUERADE2 0
155#define LASAT_PRID_MASQUERADEPRO 1
156#define LASAT_PRID_SAFEPIPE25 2
157#define LASAT_PRID_SAFEPIPE50 3
158#define LASAT_PRID_SAFEPIPE100 4
159#define LASAT_PRID_SAFEPIPE5000 5
160#define LASAT_PRID_SAFEPIPE7000 6
161#define LASAT_PRID_SAFEPIPE30 7
162#define LASAT_PRID_SAFEPIPE5100 8
163#define LASAT_PRID_SAFEPIPE7100 9
164
165#define LASAT_PRID_SAFEPIPE1110 10
166#define LASAT_PRID_SAFEPIPE3020 11
167#define LASAT_PRID_SAFEPIPE3030 12
168#define LASAT_PRID_SAFEPIPE5020 13
169#define LASAT_PRID_SAFEPIPE5030 14
170#define LASAT_PRID_SAFEPIPE1120 15
171#define LASAT_PRID_SAFEPIPE1130 16
172#define LASAT_PRID_SAFEPIPE6010 17
173#define LASAT_PRID_SAFEPIPE6110 18
174#define LASAT_PRID_SAFEPIPE6210 19
175#define LASAT_PRID_SAFEPIPE1020 20
176#define LASAT_PRID_SAFEPIPE1040 21
177#define LASAT_PRID_SAFEPIPE1060 22
178
179struct lasat_info {
180 unsigned int li_cpu_hz;
181 unsigned int li_bus_hz;
182 unsigned int li_bmid;
183 unsigned int li_memsize;
184 unsigned int li_flash_size;
185 unsigned int li_prid;
186 unsigned char li_bmstr[16];
187 unsigned char li_namestr[32];
188 unsigned char li_typestr[16];
189 /* Info on the Flash layout */
190 unsigned int li_flash_base;
191 unsigned long li_flashpart_base[LASAT_MTD_LAST];
192 unsigned long li_flashpart_size[LASAT_MTD_LAST];
193 struct lasat_eeprom_struct li_eeprom_info;
194 unsigned int li_eeprom_upgrade_version;
195 unsigned int li_debugaccess;
196};
197
198extern struct lasat_info lasat_board_info;
199
200static inline unsigned long lasat_flash_partition_start(int partno)
201{
202 if (partno < 0 || partno >= LASAT_MTD_LAST)
203 return 0;
204
205 return lasat_board_info.li_flashpart_base[partno];
206}
207
208static inline unsigned long lasat_flash_partition_size(int partno)
209{
210 if (partno < 0 || partno >= LASAT_MTD_LAST)
211 return 0;
212
213 return lasat_board_info.li_flashpart_size[partno];
214}
215
216/* Called from setup() to initialize the global board_info struct */
217extern int lasat_init_board_info(void);
218
219/* Write the modified EEPROM info struct */
220extern void lasat_write_eeprom_info(void);
221
222#define N_MACHTYPES 2
223/* for calibration of delays */
224
225/* the lasat_ndelay function is necessary because it is used at an
226 * early stage of the boot process where ndelay is not calibrated.
227 * It is used for the bit-banging rtc and eeprom drivers */
228
229#include <linux/delay.h>
230
231/* calculating with the slowest board with 100 MHz clock */
232#define LASAT_100_DIVIDER 20
233/* All 200's run at 250 MHz clock */
234#define LASAT_200_DIVIDER 8
235
236extern unsigned int lasat_ndelay_divider;
237
238static inline void lasat_ndelay(unsigned int ns)
239{
240 __delay(ns / lasat_ndelay_divider);
241}
242
243#endif /* !defined (_LANGUAGE_ASSEMBLY) */
244
245#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
246#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
247
248/* Lasat 100 boards */
249#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
250
251/* Lasat 200 boards */
252#define Vrc5074_PHYS_BASE 0x1fa00000
253#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
254#define PCI_WINDOW1 0x1a000000
255
256#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
new file mode 100644
index 000000000000..065474feeccc
--- /dev/null
+++ b/include/asm-mips/lasat/lasatint.h
@@ -0,0 +1,12 @@
1#define LASATINT_END 16
2
3/* lasat 100 */
4#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
5#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
6#define LASATINT_MASK_SHIFT_100 0
7
8/* lasat 200 */
9#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
10#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
11#define LASATINT_MASK_SHIFT_200 16
12
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
new file mode 100644
index 000000000000..42a492edc40e
--- /dev/null
+++ b/include/asm-mips/lasat/picvue.h
@@ -0,0 +1,15 @@
1/* Lasat 100 */
2#define PVC_REG_100 KSEG1ADDR(0x1c820000)
3#define PVC_DATA_SHIFT_100 0
4#define PVC_DATA_M_100 0xFF
5#define PVC_E_100 (1 << 8)
6#define PVC_RW_100 (1 << 9)
7#define PVC_RS_100 (1 << 10)
8
9/* Lasat 200 */
10#define PVC_REG_200 KSEG1ADDR(0x11000000)
11#define PVC_DATA_SHIFT_200 24
12#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200)
13#define PVC_E_200 (1 << 16)
14#define PVC_RW_200 (1 << 17)
15#define PVC_RS_200 (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
new file mode 100644
index 000000000000..bafe68b10614
--- /dev/null
+++ b/include/asm-mips/lasat/serial.h
@@ -0,0 +1,13 @@
1#include <asm/lasat/lasat.h>
2
3/* Lasat 100 boards serial configuration */
4#define LASAT_BASE_BAUD_100 (7372800 / 16)
5#define LASAT_UART_REGS_BASE_100 0x1c8b0000
6#define LASAT_UART_REGS_SHIFT_100 2
7#define LASATINT_UART_100 8
8
9/* * LASAT 200 boards serial configuration */
10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
12#define LASAT_UART_REGS_SHIFT_200 3
13#define LASATINT_UART_200 13
diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h
index b6185d3cfe68..e9a940d1b0c6 100644
--- a/include/asm-mips/linkage.h
+++ b/include/asm-mips/linkage.h
@@ -5,4 +5,6 @@
5#include <asm/asm.h> 5#include <asm/asm.h>
6#endif 6#endif
7 7
8#define __weak __attribute__((weak))
9
8#endif 10#endif
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
index f9a5ce5c9af1..f96fd59e0845 100644
--- a/include/asm-mips/local.h
+++ b/include/asm-mips/local.h
@@ -15,10 +15,10 @@ typedef struct
15#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } 15#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) }
16 16
17#define local_read(l) atomic_long_read(&(l)->a) 17#define local_read(l) atomic_long_read(&(l)->a)
18#define local_set(l,i) atomic_long_set(&(l)->a, (i)) 18#define local_set(l, i) atomic_long_set(&(l)->a, (i))
19 19
20#define local_add(i,l) atomic_long_add((i),(&(l)->a)) 20#define local_add(i, l) atomic_long_add((i), (&(l)->a))
21#define local_sub(i,l) atomic_long_sub((i),(&(l)->a)) 21#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))
22#define local_inc(l) atomic_long_inc(&(l)->a) 22#define local_inc(l) atomic_long_inc(&(l)->a)
23#define local_dec(l) atomic_long_dec(&(l)->a) 23#define local_dec(l) atomic_long_dec(&(l)->a)
24 24
@@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
117 117
118#define local_cmpxchg(l, o, n) \ 118#define local_cmpxchg(l, o, n) \
119 ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) 119 ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
120#define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n))) 120#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
121 121
122/** 122/**
123 * local_add_unless - add unless the number is a given value 123 * local_add_unless - add unless the number is a given value
@@ -138,8 +138,8 @@ static __inline__ long local_sub_return(long i, local_t * l)
138}) 138})
139#define local_inc_not_zero(l) local_add_unless((l), 1, 0) 139#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
140 140
141#define local_dec_return(l) local_sub_return(1,(l)) 141#define local_dec_return(l) local_sub_return(1, (l))
142#define local_inc_return(l) local_add_return(1,(l)) 142#define local_inc_return(l) local_add_return(1, (l))
143 143
144/* 144/*
145 * local_sub_and_test - subtract value from variable and test result 145 * local_sub_and_test - subtract value from variable and test result
@@ -150,7 +150,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
150 * true if the result is zero, or false for all 150 * true if the result is zero, or false for all
151 * other cases. 151 * other cases.
152 */ 152 */
153#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0) 153#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
154 154
155/* 155/*
156 * local_inc_and_test - increment and test 156 * local_inc_and_test - increment and test
@@ -181,7 +181,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
181 * if the result is negative, or false when 181 * if the result is negative, or false when
182 * result is greater than or equal to zero. 182 * result is greater than or equal to zero.
183 */ 183 */
184#define local_add_negative(i,l) (local_add_return(i, (l)) < 0) 184#define local_add_negative(i, l) (local_add_return(i, (l)) < 0)
185 185
186/* Use these for per-cpu local_t variables: on some archs they are 186/* Use these for per-cpu local_t variables: on some archs they are
187 * much more efficient than these naive implementations. Note they take 187 * much more efficient than these naive implementations. Note they take
@@ -190,8 +190,8 @@ static __inline__ long local_sub_return(long i, local_t * l)
190 190
191#define __local_inc(l) ((l)->a.counter++) 191#define __local_inc(l) ((l)->a.counter++)
192#define __local_dec(l) ((l)->a.counter++) 192#define __local_dec(l) ((l)->a.counter++)
193#define __local_add(i,l) ((l)->a.counter+=(i)) 193#define __local_add(i, l) ((l)->a.counter+=(i))
194#define __local_sub(i,l) ((l)->a.counter-=(i)) 194#define __local_sub(i, l) ((l)->a.counter-=(i))
195 195
196/* Need to disable preemption for the cpu local counters otherwise we could 196/* Need to disable preemption for the cpu local counters otherwise we could
197 still access a variable of a previous CPU in a non atomic way. */ 197 still access a variable of a previous CPU in a non atomic way. */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 58fca8a5a9a6..10f613f23c33 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
951/* Programmable Counters 0 and 1 */ 951/* Programmable Counters 0 and 1 */
952#define SYS_BASE 0xB1900000 952#define SYS_BASE 0xB1900000
953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
954 #define SYS_CNTRL_E1S (1<<23) 954# define SYS_CNTRL_E1S (1<<23)
955 #define SYS_CNTRL_T1S (1<<20) 955# define SYS_CNTRL_T1S (1<<20)
956 #define SYS_CNTRL_M21 (1<<19) 956# define SYS_CNTRL_M21 (1<<19)
957 #define SYS_CNTRL_M11 (1<<18) 957# define SYS_CNTRL_M11 (1<<18)
958 #define SYS_CNTRL_M01 (1<<17) 958# define SYS_CNTRL_M01 (1<<17)
959 #define SYS_CNTRL_C1S (1<<16) 959# define SYS_CNTRL_C1S (1<<16)
960 #define SYS_CNTRL_BP (1<<14) 960# define SYS_CNTRL_BP (1<<14)
961 #define SYS_CNTRL_EN1 (1<<13) 961# define SYS_CNTRL_EN1 (1<<13)
962 #define SYS_CNTRL_BT1 (1<<12) 962# define SYS_CNTRL_BT1 (1<<12)
963 #define SYS_CNTRL_EN0 (1<<11) 963# define SYS_CNTRL_EN0 (1<<11)
964 #define SYS_CNTRL_BT0 (1<<10) 964# define SYS_CNTRL_BT0 (1<<10)
965 #define SYS_CNTRL_E0 (1<<8) 965# define SYS_CNTRL_E0 (1<<8)
966 #define SYS_CNTRL_E0S (1<<7) 966# define SYS_CNTRL_E0S (1<<7)
967 #define SYS_CNTRL_32S (1<<5) 967# define SYS_CNTRL_32S (1<<5)
968 #define SYS_CNTRL_T0S (1<<4) 968# define SYS_CNTRL_T0S (1<<4)
969 #define SYS_CNTRL_M20 (1<<3) 969# define SYS_CNTRL_M20 (1<<3)
970 #define SYS_CNTRL_M10 (1<<2) 970# define SYS_CNTRL_M10 (1<<2)
971 #define SYS_CNTRL_M00 (1<<1) 971# define SYS_CNTRL_M00 (1<<1)
972 #define SYS_CNTRL_C0S (1<<0) 972# define SYS_CNTRL_C0S (1<<0)
973 973
974/* Programmable Counter 0 Registers */ 974/* Programmable Counter 0 Registers */
975#define SYS_TOYTRIM (SYS_BASE + 0) 975#define SYS_TOYTRIM (SYS_BASE + 0)
@@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
989 989
990/* I2S Controller */ 990/* I2S Controller */
991#define I2S_DATA 0xB1000000 991#define I2S_DATA 0xB1000000
992 #define I2S_DATA_MASK (0xffffff) 992# define I2S_DATA_MASK (0xffffff)
993#define I2S_CONFIG 0xB1000004 993#define I2S_CONFIG 0xB1000004
994 #define I2S_CONFIG_XU (1<<25) 994# define I2S_CONFIG_XU (1<<25)
995 #define I2S_CONFIG_XO (1<<24) 995# define I2S_CONFIG_XO (1<<24)
996 #define I2S_CONFIG_RU (1<<23) 996# define I2S_CONFIG_RU (1<<23)
997 #define I2S_CONFIG_RO (1<<22) 997# define I2S_CONFIG_RO (1<<22)
998 #define I2S_CONFIG_TR (1<<21) 998# define I2S_CONFIG_TR (1<<21)
999 #define I2S_CONFIG_TE (1<<20) 999# define I2S_CONFIG_TE (1<<20)
1000 #define I2S_CONFIG_TF (1<<19) 1000# define I2S_CONFIG_TF (1<<19)
1001 #define I2S_CONFIG_RR (1<<18) 1001# define I2S_CONFIG_RR (1<<18)
1002 #define I2S_CONFIG_RE (1<<17) 1002# define I2S_CONFIG_RE (1<<17)
1003 #define I2S_CONFIG_RF (1<<16) 1003# define I2S_CONFIG_RF (1<<16)
1004 #define I2S_CONFIG_PD (1<<11) 1004# define I2S_CONFIG_PD (1<<11)
1005 #define I2S_CONFIG_LB (1<<10) 1005# define I2S_CONFIG_LB (1<<10)
1006 #define I2S_CONFIG_IC (1<<9) 1006# define I2S_CONFIG_IC (1<<9)
1007 #define I2S_CONFIG_FM_BIT 7 1007# define I2S_CONFIG_FM_BIT 7
1008 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1008# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1009 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1009# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1010 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1010# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1011 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1011# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1012 #define I2S_CONFIG_TN (1<<6) 1012# define I2S_CONFIG_TN (1<<6)
1013 #define I2S_CONFIG_RN (1<<5) 1013# define I2S_CONFIG_RN (1<<5)
1014 #define I2S_CONFIG_SZ_BIT 0 1014# define I2S_CONFIG_SZ_BIT 0
1015 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1015# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1016 1016
1017#define I2S_CONTROL 0xB1000008 1017#define I2S_CONTROL 0xB1000008
1018 #define I2S_CONTROL_D (1<<1) 1018# define I2S_CONTROL_D (1<<1)
1019 #define I2S_CONTROL_CE (1<<0) 1019# define I2S_CONTROL_CE (1<<0)
1020 1020
1021/* USB Host Controller */ 1021/* USB Host Controller */
1022#ifndef USB_OHCI_LEN 1022#ifndef USB_OHCI_LEN
@@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1034#define USBD_EP5RD 0xB0200014 1034#define USBD_EP5RD 0xB0200014
1035#define USBD_INTEN 0xB0200018 1035#define USBD_INTEN 0xB0200018
1036#define USBD_INTSTAT 0xB020001C 1036#define USBD_INTSTAT 0xB020001C
1037 #define USBDEV_INT_SOF (1<<12) 1037# define USBDEV_INT_SOF (1<<12)
1038 #define USBDEV_INT_HF_BIT 6 1038# define USBDEV_INT_HF_BIT 6
1039 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1039# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1040 #define USBDEV_INT_CMPLT_BIT 0 1040# define USBDEV_INT_CMPLT_BIT 0
1041 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1041# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1042#define USBD_CONFIG 0xB0200020 1042#define USBD_CONFIG 0xB0200020
1043#define USBD_EP0CS 0xB0200024 1043#define USBD_EP0CS 0xB0200024
1044#define USBD_EP2CS 0xB0200028 1044#define USBD_EP2CS 0xB0200028
1045#define USBD_EP3CS 0xB020002C 1045#define USBD_EP3CS 0xB020002C
1046#define USBD_EP4CS 0xB0200030 1046#define USBD_EP4CS 0xB0200030
1047#define USBD_EP5CS 0xB0200034 1047#define USBD_EP5CS 0xB0200034
1048 #define USBDEV_CS_SU (1<<14) 1048# define USBDEV_CS_SU (1<<14)
1049 #define USBDEV_CS_NAK (1<<13) 1049# define USBDEV_CS_NAK (1<<13)
1050 #define USBDEV_CS_ACK (1<<12) 1050# define USBDEV_CS_ACK (1<<12)
1051 #define USBDEV_CS_BUSY (1<<11) 1051# define USBDEV_CS_BUSY (1<<11)
1052 #define USBDEV_CS_TSIZE_BIT 1 1052# define USBDEV_CS_TSIZE_BIT 1
1053 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1053# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1054 #define USBDEV_CS_STALL (1<<0) 1054# define USBDEV_CS_STALL (1<<0)
1055#define USBD_EP0RDSTAT 0xB0200040 1055#define USBD_EP0RDSTAT 0xB0200040
1056#define USBD_EP0WRSTAT 0xB0200044 1056#define USBD_EP0WRSTAT 0xB0200044
1057#define USBD_EP2WRSTAT 0xB0200048 1057#define USBD_EP2WRSTAT 0xB0200048
1058#define USBD_EP3WRSTAT 0xB020004C 1058#define USBD_EP3WRSTAT 0xB020004C
1059#define USBD_EP4RDSTAT 0xB0200050 1059#define USBD_EP4RDSTAT 0xB0200050
1060#define USBD_EP5RDSTAT 0xB0200054 1060#define USBD_EP5RDSTAT 0xB0200054
1061 #define USBDEV_FSTAT_FLUSH (1<<6) 1061# define USBDEV_FSTAT_FLUSH (1<<6)
1062 #define USBDEV_FSTAT_UF (1<<5) 1062# define USBDEV_FSTAT_UF (1<<5)
1063 #define USBDEV_FSTAT_OF (1<<4) 1063# define USBDEV_FSTAT_OF (1<<4)
1064 #define USBDEV_FSTAT_FCNT_BIT 0 1064# define USBDEV_FSTAT_FCNT_BIT 0
1065 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1065# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1066#define USBD_ENABLE 0xB0200058 1066#define USBD_ENABLE 0xB0200058
1067 #define USBDEV_ENABLE (1<<1) 1067# define USBDEV_ENABLE (1<<1)
1068 #define USBDEV_CE (1<<0) 1068# define USBDEV_CE (1<<0)
1069 1069
1070#endif /* !CONFIG_SOC_AU1200 */ 1070#endif /* !CONFIG_SOC_AU1200 */
1071 1071
@@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1073 1073
1074/* 4 byte offsets from AU1000_ETH_BASE */ 1074/* 4 byte offsets from AU1000_ETH_BASE */
1075#define MAC_CONTROL 0x0 1075#define MAC_CONTROL 0x0
1076 #define MAC_RX_ENABLE (1<<2) 1076# define MAC_RX_ENABLE (1<<2)
1077 #define MAC_TX_ENABLE (1<<3) 1077# define MAC_TX_ENABLE (1<<3)
1078 #define MAC_DEF_CHECK (1<<5) 1078# define MAC_DEF_CHECK (1<<5)
1079 #define MAC_SET_BL(X) (((X)&0x3)<<6) 1079# define MAC_SET_BL(X) (((X)&0x3)<<6)
1080 #define MAC_AUTO_PAD (1<<8) 1080# define MAC_AUTO_PAD (1<<8)
1081 #define MAC_DISABLE_RETRY (1<<10) 1081# define MAC_DISABLE_RETRY (1<<10)
1082 #define MAC_DISABLE_BCAST (1<<11) 1082# define MAC_DISABLE_BCAST (1<<11)
1083 #define MAC_LATE_COL (1<<12) 1083# define MAC_LATE_COL (1<<12)
1084 #define MAC_HASH_MODE (1<<13) 1084# define MAC_HASH_MODE (1<<13)
1085 #define MAC_HASH_ONLY (1<<15) 1085# define MAC_HASH_ONLY (1<<15)
1086 #define MAC_PASS_ALL (1<<16) 1086# define MAC_PASS_ALL (1<<16)
1087 #define MAC_INVERSE_FILTER (1<<17) 1087# define MAC_INVERSE_FILTER (1<<17)
1088 #define MAC_PROMISCUOUS (1<<18) 1088# define MAC_PROMISCUOUS (1<<18)
1089 #define MAC_PASS_ALL_MULTI (1<<19) 1089# define MAC_PASS_ALL_MULTI (1<<19)
1090 #define MAC_FULL_DUPLEX (1<<20) 1090# define MAC_FULL_DUPLEX (1<<20)
1091 #define MAC_NORMAL_MODE 0 1091# define MAC_NORMAL_MODE 0
1092 #define MAC_INT_LOOPBACK (1<<21) 1092# define MAC_INT_LOOPBACK (1<<21)
1093 #define MAC_EXT_LOOPBACK (1<<22) 1093# define MAC_EXT_LOOPBACK (1<<22)
1094 #define MAC_DISABLE_RX_OWN (1<<23) 1094# define MAC_DISABLE_RX_OWN (1<<23)
1095 #define MAC_BIG_ENDIAN (1<<30) 1095# define MAC_BIG_ENDIAN (1<<30)
1096 #define MAC_RX_ALL (1<<31) 1096# define MAC_RX_ALL (1<<31)
1097#define MAC_ADDRESS_HIGH 0x4 1097#define MAC_ADDRESS_HIGH 0x4
1098#define MAC_ADDRESS_LOW 0x8 1098#define MAC_ADDRESS_LOW 0x8
1099#define MAC_MCAST_HIGH 0xC 1099#define MAC_MCAST_HIGH 0xC
1100#define MAC_MCAST_LOW 0x10 1100#define MAC_MCAST_LOW 0x10
1101#define MAC_MII_CNTRL 0x14 1101#define MAC_MII_CNTRL 0x14
1102 #define MAC_MII_BUSY (1<<0) 1102# define MAC_MII_BUSY (1<<0)
1103 #define MAC_MII_READ 0 1103# define MAC_MII_READ 0
1104 #define MAC_MII_WRITE (1<<1) 1104# define MAC_MII_WRITE (1<<1)
1105 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 1105# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1106 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 1106# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1107#define MAC_MII_DATA 0x18 1107#define MAC_MII_DATA 0x18
1108#define MAC_FLOW_CNTRL 0x1C 1108#define MAC_FLOW_CNTRL 0x1C
1109 #define MAC_FLOW_CNTRL_BUSY (1<<0) 1109# define MAC_FLOW_CNTRL_BUSY (1<<0)
1110 #define MAC_FLOW_CNTRL_ENABLE (1<<1) 1110# define MAC_FLOW_CNTRL_ENABLE (1<<1)
1111 #define MAC_PASS_CONTROL (1<<2) 1111# define MAC_PASS_CONTROL (1<<2)
1112 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 1112# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1113#define MAC_VLAN1_TAG 0x20 1113#define MAC_VLAN1_TAG 0x20
1114#define MAC_VLAN2_TAG 0x24 1114#define MAC_VLAN2_TAG 0x24
1115 1115
1116/* Ethernet Controller Enable */ 1116/* Ethernet Controller Enable */
1117 1117
1118 #define MAC_EN_CLOCK_ENABLE (1<<0) 1118# define MAC_EN_CLOCK_ENABLE (1<<0)
1119 #define MAC_EN_RESET0 (1<<1) 1119# define MAC_EN_RESET0 (1<<1)
1120 #define MAC_EN_TOSS (0<<2) 1120# define MAC_EN_TOSS (0<<2)
1121 #define MAC_EN_CACHEABLE (1<<3) 1121# define MAC_EN_CACHEABLE (1<<3)
1122 #define MAC_EN_RESET1 (1<<4) 1122# define MAC_EN_RESET1 (1<<4)
1123 #define MAC_EN_RESET2 (1<<5) 1123# define MAC_EN_RESET2 (1<<5)
1124 #define MAC_DMA_RESET (1<<6) 1124# define MAC_DMA_RESET (1<<6)
1125 1125
1126/* Ethernet Controller DMA Channels */ 1126/* Ethernet Controller DMA Channels */
1127 1127
@@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1129#define MAC1_TX_DMA_ADDR 0xB4004200 1129#define MAC1_TX_DMA_ADDR 0xB4004200
1130/* offsets from MAC_TX_RING_ADDR address */ 1130/* offsets from MAC_TX_RING_ADDR address */
1131#define MAC_TX_BUFF0_STATUS 0x0 1131#define MAC_TX_BUFF0_STATUS 0x0
1132 #define TX_FRAME_ABORTED (1<<0) 1132# define TX_FRAME_ABORTED (1<<0)
1133 #define TX_JAB_TIMEOUT (1<<1) 1133# define TX_JAB_TIMEOUT (1<<1)
1134 #define TX_NO_CARRIER (1<<2) 1134# define TX_NO_CARRIER (1<<2)
1135 #define TX_LOSS_CARRIER (1<<3) 1135# define TX_LOSS_CARRIER (1<<3)
1136 #define TX_EXC_DEF (1<<4) 1136# define TX_EXC_DEF (1<<4)
1137 #define TX_LATE_COLL_ABORT (1<<5) 1137# define TX_LATE_COLL_ABORT (1<<5)
1138 #define TX_EXC_COLL (1<<6) 1138# define TX_EXC_COLL (1<<6)
1139 #define TX_UNDERRUN (1<<7) 1139# define TX_UNDERRUN (1<<7)
1140 #define TX_DEFERRED (1<<8) 1140# define TX_DEFERRED (1<<8)
1141 #define TX_LATE_COLL (1<<9) 1141# define TX_LATE_COLL (1<<9)
1142 #define TX_COLL_CNT_MASK (0xF<<10) 1142# define TX_COLL_CNT_MASK (0xF<<10)
1143 #define TX_PKT_RETRY (1<<31) 1143# define TX_PKT_RETRY (1<<31)
1144#define MAC_TX_BUFF0_ADDR 0x4 1144#define MAC_TX_BUFF0_ADDR 0x4
1145 #define TX_DMA_ENABLE (1<<0) 1145# define TX_DMA_ENABLE (1<<0)
1146 #define TX_T_DONE (1<<1) 1146# define TX_T_DONE (1<<1)
1147 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1147# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1148#define MAC_TX_BUFF0_LEN 0x8 1148#define MAC_TX_BUFF0_LEN 0x8
1149#define MAC_TX_BUFF1_STATUS 0x10 1149#define MAC_TX_BUFF1_STATUS 0x10
1150#define MAC_TX_BUFF1_ADDR 0x14 1150#define MAC_TX_BUFF1_ADDR 0x14
@@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1160#define MAC1_RX_DMA_ADDR 0xB4004300 1160#define MAC1_RX_DMA_ADDR 0xB4004300
1161/* offsets from MAC_RX_RING_ADDR */ 1161/* offsets from MAC_RX_RING_ADDR */
1162#define MAC_RX_BUFF0_STATUS 0x0 1162#define MAC_RX_BUFF0_STATUS 0x0
1163 #define RX_FRAME_LEN_MASK 0x3fff 1163# define RX_FRAME_LEN_MASK 0x3fff
1164 #define RX_WDOG_TIMER (1<<14) 1164# define RX_WDOG_TIMER (1<<14)
1165 #define RX_RUNT (1<<15) 1165# define RX_RUNT (1<<15)
1166 #define RX_OVERLEN (1<<16) 1166# define RX_OVERLEN (1<<16)
1167 #define RX_COLL (1<<17) 1167# define RX_COLL (1<<17)
1168 #define RX_ETHER (1<<18) 1168# define RX_ETHER (1<<18)
1169 #define RX_MII_ERROR (1<<19) 1169# define RX_MII_ERROR (1<<19)
1170 #define RX_DRIBBLING (1<<20) 1170# define RX_DRIBBLING (1<<20)
1171 #define RX_CRC_ERROR (1<<21) 1171# define RX_CRC_ERROR (1<<21)
1172 #define RX_VLAN1 (1<<22) 1172# define RX_VLAN1 (1<<22)
1173 #define RX_VLAN2 (1<<23) 1173# define RX_VLAN2 (1<<23)
1174 #define RX_LEN_ERROR (1<<24) 1174# define RX_LEN_ERROR (1<<24)
1175 #define RX_CNTRL_FRAME (1<<25) 1175# define RX_CNTRL_FRAME (1<<25)
1176 #define RX_U_CNTRL_FRAME (1<<26) 1176# define RX_U_CNTRL_FRAME (1<<26)
1177 #define RX_MCAST_FRAME (1<<27) 1177# define RX_MCAST_FRAME (1<<27)
1178 #define RX_BCAST_FRAME (1<<28) 1178# define RX_BCAST_FRAME (1<<28)
1179 #define RX_FILTER_FAIL (1<<29) 1179# define RX_FILTER_FAIL (1<<29)
1180 #define RX_PACKET_FILTER (1<<30) 1180# define RX_PACKET_FILTER (1<<30)
1181 #define RX_MISSED_FRAME (1<<31) 1181# define RX_MISSED_FRAME (1<<31)
1182 1182
1183 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1183# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1186#define MAC_RX_BUFF0_ADDR 0x4 1186#define MAC_RX_BUFF0_ADDR 0x4
1187 #define RX_DMA_ENABLE (1<<0) 1187# define RX_DMA_ENABLE (1<<0)
1188 #define RX_T_DONE (1<<1) 1188# define RX_T_DONE (1<<1)
1189 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1189# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1190 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 1190# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1191#define MAC_RX_BUFF1_STATUS 0x10 1191#define MAC_RX_BUFF1_STATUS 0x10
1192#define MAC_RX_BUFF1_ADDR 0x14 1192#define MAC_RX_BUFF1_ADDR 0x14
1193#define MAC_RX_BUFF2_STATUS 0x20 1193#define MAC_RX_BUFF2_STATUS 0x20
@@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1298 1298
1299/* SSIO */ 1299/* SSIO */
1300#define SSI0_STATUS 0xB1600000 1300#define SSI0_STATUS 0xB1600000
1301 #define SSI_STATUS_BF (1<<4) 1301# define SSI_STATUS_BF (1<<4)
1302 #define SSI_STATUS_OF (1<<3) 1302# define SSI_STATUS_OF (1<<3)
1303 #define SSI_STATUS_UF (1<<2) 1303# define SSI_STATUS_UF (1<<2)
1304 #define SSI_STATUS_D (1<<1) 1304# define SSI_STATUS_D (1<<1)
1305 #define SSI_STATUS_B (1<<0) 1305# define SSI_STATUS_B (1<<0)
1306#define SSI0_INT 0xB1600004 1306#define SSI0_INT 0xB1600004
1307 #define SSI_INT_OI (1<<3) 1307# define SSI_INT_OI (1<<3)
1308 #define SSI_INT_UI (1<<2) 1308# define SSI_INT_UI (1<<2)
1309 #define SSI_INT_DI (1<<1) 1309# define SSI_INT_DI (1<<1)
1310#define SSI0_INT_ENABLE 0xB1600008 1310#define SSI0_INT_ENABLE 0xB1600008
1311 #define SSI_INTE_OIE (1<<3) 1311# define SSI_INTE_OIE (1<<3)
1312 #define SSI_INTE_UIE (1<<2) 1312# define SSI_INTE_UIE (1<<2)
1313 #define SSI_INTE_DIE (1<<1) 1313# define SSI_INTE_DIE (1<<1)
1314#define SSI0_CONFIG 0xB1600020 1314#define SSI0_CONFIG 0xB1600020
1315 #define SSI_CONFIG_AO (1<<24) 1315# define SSI_CONFIG_AO (1<<24)
1316 #define SSI_CONFIG_DO (1<<23) 1316# define SSI_CONFIG_DO (1<<23)
1317 #define SSI_CONFIG_ALEN_BIT 20 1317# define SSI_CONFIG_ALEN_BIT 20
1318 #define SSI_CONFIG_ALEN_MASK (0x7<<20) 1318# define SSI_CONFIG_ALEN_MASK (0x7<<20)
1319 #define SSI_CONFIG_DLEN_BIT 16 1319# define SSI_CONFIG_DLEN_BIT 16
1320 #define SSI_CONFIG_DLEN_MASK (0x7<<16) 1320# define SSI_CONFIG_DLEN_MASK (0x7<<16)
1321 #define SSI_CONFIG_DD (1<<11) 1321# define SSI_CONFIG_DD (1<<11)
1322 #define SSI_CONFIG_AD (1<<10) 1322# define SSI_CONFIG_AD (1<<10)
1323 #define SSI_CONFIG_BM_BIT 8 1323# define SSI_CONFIG_BM_BIT 8
1324 #define SSI_CONFIG_BM_MASK (0x3<<8) 1324# define SSI_CONFIG_BM_MASK (0x3<<8)
1325 #define SSI_CONFIG_CE (1<<7) 1325# define SSI_CONFIG_CE (1<<7)
1326 #define SSI_CONFIG_DP (1<<6) 1326# define SSI_CONFIG_DP (1<<6)
1327 #define SSI_CONFIG_DL (1<<5) 1327# define SSI_CONFIG_DL (1<<5)
1328 #define SSI_CONFIG_EP (1<<4) 1328# define SSI_CONFIG_EP (1<<4)
1329#define SSI0_ADATA 0xB1600024 1329#define SSI0_ADATA 0xB1600024
1330 #define SSI_AD_D (1<<24) 1330# define SSI_AD_D (1<<24)
1331 #define SSI_AD_ADDR_BIT 16 1331# define SSI_AD_ADDR_BIT 16
1332 #define SSI_AD_ADDR_MASK (0xff<<16) 1332# define SSI_AD_ADDR_MASK (0xff<<16)
1333 #define SSI_AD_DATA_BIT 0 1333# define SSI_AD_DATA_BIT 0
1334 #define SSI_AD_DATA_MASK (0xfff<<0) 1334# define SSI_AD_DATA_MASK (0xfff<<0)
1335#define SSI0_CLKDIV 0xB1600028 1335#define SSI0_CLKDIV 0xB1600028
1336#define SSI0_CONTROL 0xB1600100 1336#define SSI0_CONTROL 0xB1600100
1337 #define SSI_CONTROL_CD (1<<1) 1337# define SSI_CONTROL_CD (1<<1)
1338 #define SSI_CONTROL_E (1<<0) 1338# define SSI_CONTROL_E (1<<0)
1339 1339
1340/* SSI1 */ 1340/* SSI1 */
1341#define SSI1_STATUS 0xB1680000 1341#define SSI1_STATUS 0xB1680000
@@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1402#define IR_INT_CLEAR (IRDA_BASE+0x18) 1402#define IR_INT_CLEAR (IRDA_BASE+0x18)
1403#define IR_CONFIG_1 (IRDA_BASE+0x20) 1403#define IR_CONFIG_1 (IRDA_BASE+0x20)
1404 #define IR_RX_INVERT_LED (1<<0) 1404# define IR_RX_INVERT_LED (1<<0)
1405 #define IR_TX_INVERT_LED (1<<1) 1405# define IR_TX_INVERT_LED (1<<1)
1406 #define IR_ST (1<<2) 1406# define IR_ST (1<<2)
1407 #define IR_SF (1<<3) 1407# define IR_SF (1<<3)
1408 #define IR_SIR (1<<4) 1408# define IR_SIR (1<<4)
1409 #define IR_MIR (1<<5) 1409# define IR_MIR (1<<5)
1410 #define IR_FIR (1<<6) 1410# define IR_FIR (1<<6)
1411 #define IR_16CRC (1<<7) 1411# define IR_16CRC (1<<7)
1412 #define IR_TD (1<<8) 1412# define IR_TD (1<<8)
1413 #define IR_RX_ALL (1<<9) 1413# define IR_RX_ALL (1<<9)
1414 #define IR_DMA_ENABLE (1<<10) 1414# define IR_DMA_ENABLE (1<<10)
1415 #define IR_RX_ENABLE (1<<11) 1415# define IR_RX_ENABLE (1<<11)
1416 #define IR_TX_ENABLE (1<<12) 1416# define IR_TX_ENABLE (1<<12)
1417 #define IR_LOOPBACK (1<<14) 1417# define IR_LOOPBACK (1<<14)
1418 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1418# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1420#define IR_SIR_FLAGS (IRDA_BASE+0x24) 1420#define IR_SIR_FLAGS (IRDA_BASE+0x24)
1421#define IR_ENABLE (IRDA_BASE+0x28) 1421#define IR_ENABLE (IRDA_BASE+0x28)
1422 #define IR_RX_STATUS (1<<9) 1422# define IR_RX_STATUS (1<<9)
1423 #define IR_TX_STATUS (1<<10) 1423# define IR_TX_STATUS (1<<10)
1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1428#define IR_CONFIG_2 (IRDA_BASE+0x3C) 1428#define IR_CONFIG_2 (IRDA_BASE+0x3C)
1429 #define IR_MODE_INV (1<<0) 1429# define IR_MODE_INV (1<<0)
1430 #define IR_ONE_PIN (1<<1) 1430# define IR_ONE_PIN (1<<1)
1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1432 1432
1433/* GPIO */ 1433/* GPIO */
1434#define SYS_PINFUNC 0xB190002C 1434#define SYS_PINFUNC 0xB190002C
1435 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 1435# define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1436 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 1436# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1437 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 1437# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1438 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 1438# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1439 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 1439# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1440 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 1440# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1441 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 1441# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1442 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 1442# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1443 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 1443# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1444 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 1444# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1445 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 1445# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1446 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 1446# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1447 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 1447# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1448 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 1448# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1449 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 1449# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1450 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 1450# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1451 1451
1452/* Au1100 Only */ 1452/* Au1100 Only */
1453 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ 1453# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1454 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ 1454# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1455 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ 1455# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1456 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ 1456# define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1457 1457
1458/* Au1550 Only. Redefines lots of pins */ 1458/* Au1550 Only. Redefines lots of pins */
1459 #define SYS_PF_PSC2_MASK (7 << 17) 1459# define SYS_PF_PSC2_MASK (7 << 17)
1460 #define SYS_PF_PSC2_AC97 (0) 1460# define SYS_PF_PSC2_AC97 (0)
1461 #define SYS_PF_PSC2_SPI (0) 1461# define SYS_PF_PSC2_SPI (0)
1462 #define SYS_PF_PSC2_I2S (1 << 17) 1462# define SYS_PF_PSC2_I2S (1 << 17)
1463 #define SYS_PF_PSC2_SMBUS (3 << 17) 1463# define SYS_PF_PSC2_SMBUS (3 << 17)
1464 #define SYS_PF_PSC2_GPIO (7 << 17) 1464# define SYS_PF_PSC2_GPIO (7 << 17)
1465 #define SYS_PF_PSC3_MASK (7 << 20) 1465# define SYS_PF_PSC3_MASK (7 << 20)
1466 #define SYS_PF_PSC3_AC97 (0) 1466# define SYS_PF_PSC3_AC97 (0)
1467 #define SYS_PF_PSC3_SPI (0) 1467# define SYS_PF_PSC3_SPI (0)
1468 #define SYS_PF_PSC3_I2S (1 << 20) 1468# define SYS_PF_PSC3_I2S (1 << 20)
1469 #define SYS_PF_PSC3_SMBUS (3 << 20) 1469# define SYS_PF_PSC3_SMBUS (3 << 20)
1470 #define SYS_PF_PSC3_GPIO (7 << 20) 1470# define SYS_PF_PSC3_GPIO (7 << 20)
1471 #define SYS_PF_PSC1_S1 (1 << 1) 1471# define SYS_PF_PSC1_S1 (1 << 1)
1472 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1472# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1473 1473
1474/* Au1200 Only */ 1474/* Au1200 Only */
1475#ifdef CONFIG_SOC_AU1200 1475#ifdef CONFIG_SOC_AU1200
@@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1530 1530
1531/* Clock Controller */ 1531/* Clock Controller */
1532#define SYS_FREQCTRL0 0xB1900020 1532#define SYS_FREQCTRL0 0xB1900020
1533 #define SYS_FC_FRDIV2_BIT 22 1533# define SYS_FC_FRDIV2_BIT 22
1534 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1534# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1535 #define SYS_FC_FE2 (1<<21) 1535# define SYS_FC_FE2 (1<<21)
1536 #define SYS_FC_FS2 (1<<20) 1536# define SYS_FC_FS2 (1<<20)
1537 #define SYS_FC_FRDIV1_BIT 12 1537# define SYS_FC_FRDIV1_BIT 12
1538 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1538# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1539 #define SYS_FC_FE1 (1<<11) 1539# define SYS_FC_FE1 (1<<11)
1540 #define SYS_FC_FS1 (1<<10) 1540# define SYS_FC_FS1 (1<<10)
1541 #define SYS_FC_FRDIV0_BIT 2 1541# define SYS_FC_FRDIV0_BIT 2
1542 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1542# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1543 #define SYS_FC_FE0 (1<<1) 1543# define SYS_FC_FE0 (1<<1)
1544 #define SYS_FC_FS0 (1<<0) 1544# define SYS_FC_FS0 (1<<0)
1545#define SYS_FREQCTRL1 0xB1900024 1545#define SYS_FREQCTRL1 0xB1900024
1546 #define SYS_FC_FRDIV5_BIT 22 1546# define SYS_FC_FRDIV5_BIT 22
1547 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1547# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1548 #define SYS_FC_FE5 (1<<21) 1548# define SYS_FC_FE5 (1<<21)
1549 #define SYS_FC_FS5 (1<<20) 1549# define SYS_FC_FS5 (1<<20)
1550 #define SYS_FC_FRDIV4_BIT 12 1550# define SYS_FC_FRDIV4_BIT 12
1551 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1551# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1552 #define SYS_FC_FE4 (1<<11) 1552# define SYS_FC_FE4 (1<<11)
1553 #define SYS_FC_FS4 (1<<10) 1553# define SYS_FC_FS4 (1<<10)
1554 #define SYS_FC_FRDIV3_BIT 2 1554# define SYS_FC_FRDIV3_BIT 2
1555 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1555# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1556 #define SYS_FC_FE3 (1<<1) 1556# define SYS_FC_FE3 (1<<1)
1557 #define SYS_FC_FS3 (1<<0) 1557# define SYS_FC_FS3 (1<<0)
1558#define SYS_CLKSRC 0xB1900028 1558#define SYS_CLKSRC 0xB1900028
1559 #define SYS_CS_ME1_BIT 27 1559# define SYS_CS_ME1_BIT 27
1560 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) 1560# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1561 #define SYS_CS_DE1 (1<<26) 1561# define SYS_CS_DE1 (1<<26)
1562 #define SYS_CS_CE1 (1<<25) 1562# define SYS_CS_CE1 (1<<25)
1563 #define SYS_CS_ME0_BIT 22 1563# define SYS_CS_ME0_BIT 22
1564 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) 1564# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1565 #define SYS_CS_DE0 (1<<21) 1565# define SYS_CS_DE0 (1<<21)
1566 #define SYS_CS_CE0 (1<<20) 1566# define SYS_CS_CE0 (1<<20)
1567 #define SYS_CS_MI2_BIT 17 1567# define SYS_CS_MI2_BIT 17
1568 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1568# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1569 #define SYS_CS_DI2 (1<<16) 1569# define SYS_CS_DI2 (1<<16)
1570 #define SYS_CS_CI2 (1<<15) 1570# define SYS_CS_CI2 (1<<15)
1571#ifdef CONFIG_SOC_AU1100 1571#ifdef CONFIG_SOC_AU1100
1572 #define SYS_CS_ML_BIT 7 1572# define SYS_CS_ML_BIT 7
1573 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) 1573# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1574 #define SYS_CS_DL (1<<6) 1574# define SYS_CS_DL (1<<6)
1575 #define SYS_CS_CL (1<<5) 1575# define SYS_CS_CL (1<<5)
1576#else 1576#else
1577 #define SYS_CS_MUH_BIT 12 1577# define SYS_CS_MUH_BIT 12
1578 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1578# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1579 #define SYS_CS_DUH (1<<11) 1579# define SYS_CS_DUH (1<<11)
1580 #define SYS_CS_CUH (1<<10) 1580# define SYS_CS_CUH (1<<10)
1581 #define SYS_CS_MUD_BIT 7 1581# define SYS_CS_MUD_BIT 7
1582 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1582# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1583 #define SYS_CS_DUD (1<<6) 1583# define SYS_CS_DUD (1<<6)
1584 #define SYS_CS_CUD (1<<5) 1584# define SYS_CS_CUD (1<<5)
1585#endif 1585#endif
1586 #define SYS_CS_MIR_BIT 2 1586# define SYS_CS_MIR_BIT 2
1587 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1587# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1588 #define SYS_CS_DIR (1<<1) 1588# define SYS_CS_DIR (1<<1)
1589 #define SYS_CS_CIR (1<<0) 1589# define SYS_CS_CIR (1<<0)
1590 1590
1591 #define SYS_CS_MUX_AUX 0x1 1591# define SYS_CS_MUX_AUX 0x1
1592 #define SYS_CS_MUX_FQ0 0x2 1592# define SYS_CS_MUX_FQ0 0x2
1593 #define SYS_CS_MUX_FQ1 0x3 1593# define SYS_CS_MUX_FQ1 0x3
1594 #define SYS_CS_MUX_FQ2 0x4 1594# define SYS_CS_MUX_FQ2 0x4
1595 #define SYS_CS_MUX_FQ3 0x5 1595# define SYS_CS_MUX_FQ3 0x5
1596 #define SYS_CS_MUX_FQ4 0x6 1596# define SYS_CS_MUX_FQ4 0x6
1597 #define SYS_CS_MUX_FQ5 0x7 1597# define SYS_CS_MUX_FQ5 0x7
1598#define SYS_CPUPLL 0xB1900060 1598#define SYS_CPUPLL 0xB1900060
1599#define SYS_AUXPLL 0xB1900064 1599#define SYS_AUXPLL 0xB1900064
1600 1600
1601/* AC97 Controller */ 1601/* AC97 Controller */
1602#define AC97C_CONFIG 0xB0000000 1602#define AC97C_CONFIG 0xB0000000
1603 #define AC97C_RECV_SLOTS_BIT 13 1603# define AC97C_RECV_SLOTS_BIT 13
1604 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1604# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1605 #define AC97C_XMIT_SLOTS_BIT 3 1605# define AC97C_XMIT_SLOTS_BIT 3
1606 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1606# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1607 #define AC97C_SG (1<<2) 1607# define AC97C_SG (1<<2)
1608 #define AC97C_SYNC (1<<1) 1608# define AC97C_SYNC (1<<1)
1609 #define AC97C_RESET (1<<0) 1609# define AC97C_RESET (1<<0)
1610#define AC97C_STATUS 0xB0000004 1610#define AC97C_STATUS 0xB0000004
1611 #define AC97C_XU (1<<11) 1611# define AC97C_XU (1<<11)
1612 #define AC97C_XO (1<<10) 1612# define AC97C_XO (1<<10)
1613 #define AC97C_RU (1<<9) 1613# define AC97C_RU (1<<9)
1614 #define AC97C_RO (1<<8) 1614# define AC97C_RO (1<<8)
1615 #define AC97C_READY (1<<7) 1615# define AC97C_READY (1<<7)
1616 #define AC97C_CP (1<<6) 1616# define AC97C_CP (1<<6)
1617 #define AC97C_TR (1<<5) 1617# define AC97C_TR (1<<5)
1618 #define AC97C_TE (1<<4) 1618# define AC97C_TE (1<<4)
1619 #define AC97C_TF (1<<3) 1619# define AC97C_TF (1<<3)
1620 #define AC97C_RR (1<<2) 1620# define AC97C_RR (1<<2)
1621 #define AC97C_RE (1<<1) 1621# define AC97C_RE (1<<1)
1622 #define AC97C_RF (1<<0) 1622# define AC97C_RF (1<<0)
1623#define AC97C_DATA 0xB0000008 1623#define AC97C_DATA 0xB0000008
1624#define AC97C_CMD 0xB000000C 1624#define AC97C_CMD 0xB000000C
1625 #define AC97C_WD_BIT 16 1625# define AC97C_WD_BIT 16
1626 #define AC97C_READ (1<<7) 1626# define AC97C_READ (1<<7)
1627 #define AC97C_INDEX_MASK 0x7f 1627# define AC97C_INDEX_MASK 0x7f
1628#define AC97C_CNTRL 0xB0000010 1628#define AC97C_CNTRL 0xB0000010
1629 #define AC97C_RS (1<<1) 1629# define AC97C_RS (1<<1)
1630 #define AC97C_CE (1<<0) 1630# define AC97C_CE (1<<0)
1631 1631
1632 1632
1633/* Secure Digital (SD) Controller */ 1633/* Secure Digital (SD) Controller */
@@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1636#define SD1_XMIT_FIFO 0xB0680000 1636#define SD1_XMIT_FIFO 0xB0680000
1637#define SD1_RECV_FIFO 0xB0680004 1637#define SD1_RECV_FIFO 0xB0680004
1638 1638
1639#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1639#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1640/* Au1500 PCI Controller */ 1640/* Au1500 PCI Controller */
1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1644 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1644# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index eeb0c3115b6a..93d507cea518 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -199,7 +199,7 @@ typedef volatile struct au1xxx_ddma_desc {
199#define DSCR_CMD0_ALWAYS 31 199#define DSCR_CMD0_ALWAYS 31
200#define DSCR_NDEV_IDS 32 200#define DSCR_NDEV_IDS 32
201/* THis macro is used to find/create custom device types */ 201/* THis macro is used to find/create custom device types */
202#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) 202#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
203#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) 203#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
204 204
205 205
@@ -373,14 +373,14 @@ void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
373 Some compatibilty macros -- 373 Some compatibilty macros --
374 Needed to make changes to API without breaking existing drivers 374 Needed to make changes to API without breaking existing drivers
375*/ 375*/
376#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) 376#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
377#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) 377#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
378#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) 378#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
379 379
380 380
381#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) 381#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
382#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) 382#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
383#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) 383#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
384 384
385/* 385/*
386 * Flags for the put_source/put_dest functions. 386 * Flags for the put_source/put_dest functions.
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index 4663e8b415c9..aef0edbfe4c6 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -136,7 +136,7 @@ void auide_outl(u32 addr, unsigned long port);
136void auide_outsw(unsigned long port, void *addr, u32 count); 136void auide_outsw(unsigned long port, void *addr, u32 count);
137void auide_outsl(unsigned long port, void *addr, u32 count); 137void auide_outsl(unsigned long port, void *addr, u32 count);
138static void auide_tune_drive(ide_drive_t *drive, byte pio); 138static void auide_tune_drive(ide_drive_t *drive, byte pio);
139static int auide_tune_chipset (ide_drive_t *drive, u8 speed); 139static int auide_tune_chipset(ide_drive_t *drive, u8 speed);
140static int auide_ddma_init( _auide_hwif *auide ); 140static int auide_ddma_init( _auide_hwif *auide );
141static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); 141static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
142int __init auide_probe(void); 142int __init auide_probe(void);
diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h
new file mode 100644
index 000000000000..dd57d03d68ba
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
9#define __ASM_MIPS_MACH_AU1X00_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h
new file mode 100644
index 000000000000..d008f47a28bd
--- /dev/null
+++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#ifndef __ASM_BCM47XX_H
20#define __ASM_BCM47XX_H
21
22/* SSB bus */
23extern struct ssb_bus ssb_bcm47xx;
24
25#endif /* __ASM_BCM47XX_H */
diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h
new file mode 100644
index 000000000000..cfc8f4d618ce
--- /dev/null
+++ b/include/asm-mips/mach-bcm47xx/gpio.h
@@ -0,0 +1,59 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#ifndef __BCM47XX_GPIO_H
10#define __BCM47XX_GPIO_H
11
12#define BCM47XX_EXTIF_GPIO_LINES 5
13#define BCM47XX_CHIPCO_GPIO_LINES 16
14
15extern int bcm47xx_gpio_to_irq(unsigned gpio);
16extern int bcm47xx_gpio_get_value(unsigned gpio);
17extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
18extern int bcm47xx_gpio_direction_input(unsigned gpio);
19extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
20
21static inline int gpio_request(unsigned gpio, const char *label)
22{
23 return 0;
24}
25
26static inline void gpio_free(unsigned gpio)
27{
28}
29
30static inline int gpio_to_irq(unsigned gpio)
31{
32 return bcm47xx_gpio_to_irq(gpio);
33}
34
35static inline int gpio_get_value(unsigned gpio)
36{
37 return bcm47xx_gpio_get_value(gpio);
38}
39
40static inline void gpio_set_value(unsigned gpio, int value)
41{
42 bcm47xx_gpio_set_value(gpio, value);
43}
44
45static inline int gpio_direction_input(unsigned gpio)
46{
47 return bcm47xx_gpio_direction_input(gpio);
48}
49
50static inline int gpio_direction_output(unsigned gpio, int value)
51{
52 return bcm47xx_gpio_direction_output(gpio, value);
53}
54
55
56/* cansleep wrappers */
57#include <asm-generic/gpio.h>
58
59#endif /* __BCM47XX_GPIO_H */
diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h
new file mode 100644
index 000000000000..4a2b7986b582
--- /dev/null
+++ b/include/asm-mips/mach-bcm47xx/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H
9#define __ASM_MIPS_MACH_BCM947XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 9c9d2b998ca4..a79e7caf3a86 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -12,71 +12,16 @@
12#ifndef __ASM_COBALT_H 12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H 13#define __ASM_COBALT_H
14 14
15#include <irq.h>
16
17/*
18 * i8259 legacy interrupts used on Cobalt:
19 *
20 * 8 - RTC
21 * 9 - PCI
22 * 14 - IDE0
23 * 15 - IDE1
24 */
25#define COBALT_QUBE_SLOT_IRQ 9
26
27/*
28 * CPU IRQs are 16 ... 23
29 */
30#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
31
32#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
33#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
34#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
35#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
36#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
37#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
38#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
39#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
40
41/* 15/*
42 * PCI configuration space manifest constants. These are wired into 16 * The Cobalt board ID information.
43 * the board layout according to the PCI spec to enable the software
44 * to probe the hardware configuration space in a well defined manner.
45 *
46 * The PCI_DEVSHFT() macro transforms these values into numbers
47 * suitable for passing as the dev parameter to the various
48 * pcibios_read/write_config routines.
49 */ 17 */
50#define COBALT_PCICONF_CPU 0x06 18extern int cobalt_board_id;
51#define COBALT_PCICONF_ETH0 0x07
52#define COBALT_PCICONF_RAQSCSI 0x08
53#define COBALT_PCICONF_VIA 0x09
54#define COBALT_PCICONF_PCISLOT 0x0A
55#define COBALT_PCICONF_ETH1 0x0C
56
57 19
58/*
59 * The Cobalt board id information. The boards have an ID number wired
60 * into the VIA that is available in the high nibble of register 94.
61 * This register is available in the VIA configuration space through the
62 * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
63 */
64#define VIA_COBALT_BRD_ID_REG 0x94
65#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4)
66#define COBALT_BRD_ID_QUBE1 0x3 20#define COBALT_BRD_ID_QUBE1 0x3
67#define COBALT_BRD_ID_RAQ1 0x4 21#define COBALT_BRD_ID_RAQ1 0x4
68#define COBALT_BRD_ID_QUBE2 0x5 22#define COBALT_BRD_ID_QUBE2 0x5
69#define COBALT_BRD_ID_RAQ2 0x6 23#define COBALT_BRD_ID_RAQ2 0x6
70 24
71extern int cobalt_board_id;
72
73#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
74# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
75# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
76# define COBALT_LED_WEB (1 << 2) /* RaQ */
77# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */
78# define COBALT_LED_RESET 0x0f
79
80#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) 25#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
81# define COBALT_KEY_CLEAR (1 << 1) 26# define COBALT_KEY_CLEAR (1 << 1)
82# define COBALT_KEY_LEFT (1 << 2) 27# define COBALT_KEY_LEFT (1 << 2)
@@ -87,6 +32,4 @@ extern int cobalt_board_id;
87# define COBALT_KEY_SELECT (1 << 7) 32# define COBALT_KEY_SELECT (1 << 7)
88# define COBALT_KEY_MASK 0xfe 33# define COBALT_KEY_MASK 0xfe
89 34
90#define COBALT_UART ((volatile unsigned char *) CKSEG1ADDR(0x1c800000))
91
92#endif /* __ASM_COBALT_H */ 35#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
index d38f069d9e95..b3314cf53194 100644
--- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
@@ -14,7 +14,6 @@
14#define cpu_has_3k_cache 0 14#define cpu_has_3k_cache 0
15#define cpu_has_4k_cache 1 15#define cpu_has_4k_cache 1
16#define cpu_has_tx39_cache 0 16#define cpu_has_tx39_cache 0
17#define cpu_has_sb1_cache 0
18#define cpu_has_fpu 1 17#define cpu_has_fpu 1
19#define cpu_has_32fpr 1 18#define cpu_has_32fpr 1
20#define cpu_has_counter 1 19#define cpu_has_counter 1
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
new file mode 100644
index 000000000000..179d0e850b59
--- /dev/null
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -0,0 +1,58 @@
1/*
2 * Cobalt IRQ definitions.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
11 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
12 */
13#ifndef _ASM_COBALT_IRQ_H
14#define _ASM_COBALT_IRQ_H
15
16/*
17 * i8259 interrupts used on Cobalt:
18 *
19 * 8 - RTC
20 * 9 - PCI slot
21 * 14 - IDE0
22 * 15 - IDE1(no connector on board)
23 */
24#define I8259A_IRQ_BASE 0
25
26#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
27
28/*
29 * CPU interrupts used on Cobalt:
30 *
31 * 0 - Software interrupt 0 (unused)
32 * 1 - Software interrupt 0 (unused)
33 * 2 - cascade GT64111
34 * 3 - ethernet or SCSI host controller
35 * 4 - ethernet
36 * 5 - 16550 UART
37 * 6 - cascade i8259
38 * 7 - CP0 counter (unused)
39 */
40#define MIPS_CPU_IRQ_BASE 16
41
42#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
50
51
52#define GT641XX_IRQ_BASE 24
53
54#include <asm/irq_gt641xx.h>
55
56#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
57
58#endif /* _ASM_COBALT_IRQ_H */
diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h
new file mode 100644
index 000000000000..97884fd18ac0
--- /dev/null
+++ b/include/asm-mips/mach-cobalt/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
9#define __ASM_MIPS_MACH_COBALT_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h
new file mode 100644
index 000000000000..ca5e2ef909ad
--- /dev/null
+++ b/include/asm-mips/mach-dec/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_DEC_WAR_H
9#define __ASM_MIPS_MACH_DEC_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_DEC_WAR_H */
diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h
new file mode 100644
index 000000000000..b660a4c30e6a
--- /dev/null
+++ b/include/asm-mips/mach-emma2rh/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H
9#define __ASM_MIPS_MACH_EMMA2RH_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h
index 07f4322c235d..107104c3cd12 100644
--- a/include/asm-mips/mach-excite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h
@@ -34,6 +34,11 @@
34#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 35#define cpu_has_64bits 1
36 36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
37#define cpu_has_inclusive_pcaches 0 42#define cpu_has_inclusive_pcaches 0
38 43
39#define cpu_dcache_line_size() 32 44#define cpu_dcache_line_size() 32
diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h
new file mode 100644
index 000000000000..1f82180c1598
--- /dev/null
+++ b/include/asm-mips/mach-excite/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
9#define __ASM_MIPS_MACH_EXCITE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h
index 6e1b0c075de7..f49dc990214b 100644
--- a/include/asm-mips/mach-generic/mangle-port.h
+++ b/include/asm-mips/mach-generic/mangle-port.h
@@ -27,25 +27,25 @@
27 */ 27 */
28#if defined(CONFIG_SWAP_IO_SPACE) 28#if defined(CONFIG_SWAP_IO_SPACE)
29 29
30# define ioswabb(a,x) (x) 30# define ioswabb(a, x) (x)
31# define __mem_ioswabb(a,x) (x) 31# define __mem_ioswabb(a, x) (x)
32# define ioswabw(a,x) le16_to_cpu(x) 32# define ioswabw(a, x) le16_to_cpu(x)
33# define __mem_ioswabw(a,x) (x) 33# define __mem_ioswabw(a, x) (x)
34# define ioswabl(a,x) le32_to_cpu(x) 34# define ioswabl(a, x) le32_to_cpu(x)
35# define __mem_ioswabl(a,x) (x) 35# define __mem_ioswabl(a, x) (x)
36# define ioswabq(a,x) le64_to_cpu(x) 36# define ioswabq(a, x) le64_to_cpu(x)
37# define __mem_ioswabq(a,x) (x) 37# define __mem_ioswabq(a, x) (x)
38 38
39#else 39#else
40 40
41# define ioswabb(a,x) (x) 41# define ioswabb(a, x) (x)
42# define __mem_ioswabb(a,x) (x) 42# define __mem_ioswabb(a, x) (x)
43# define ioswabw(a,x) (x) 43# define ioswabw(a, x) (x)
44# define __mem_ioswabw(a,x) cpu_to_le16(x) 44# define __mem_ioswabw(a, x) cpu_to_le16(x)
45# define ioswabl(a,x) (x) 45# define ioswabl(a, x) (x)
46# define __mem_ioswabl(a,x) cpu_to_le32(x) 46# define __mem_ioswabl(a, x) cpu_to_le32(x)
47# define ioswabq(a,x) (x) 47# define ioswabq(a, x) (x)
48# define __mem_ioswabq(a,x) cpu_to_le32(x) 48# define __mem_ioswabq(a, x) cpu_to_le32(x)
49 49
50#endif 50#endif
51 51
diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h
new file mode 100644
index 000000000000..a44fa9656a82
--- /dev/null
+++ b/include/asm-mips/mach-ip22/war.h
@@ -0,0 +1,29 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_IP22_WAR_H
9#define __ASM_MIPS_MACH_IP22_WAR_H
10
11/*
12 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
13 */
14
15#define R4600_V1_INDEX_ICACHEOP_WAR 1
16#define R4600_V1_HIT_CACHEOP_WAR 1
17#define R4600_V2_HIT_CACHEOP_WAR 1
18#define R5432_CP0_INTERRUPT_WAR 0
19#define BCM1250_M3_WAR 0
20#define SIBYTE_1956_WAR 0
21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0
28
29#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h
index 25f0c3f39adf..cf4384bfa846 100644
--- a/include/asm-mips/mach-ip27/irq.h
+++ b/include/asm-mips/mach-ip27/irq.h
@@ -17,4 +17,6 @@
17 */ 17 */
18#define NR_IRQS 256 18#define NR_IRQS 256
19 19
20#include_next <irq.h>
21
20#endif /* __ASM_MACH_IP27_IRQ_H */ 22#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h
index d615312a451a..f6e4912ea062 100644
--- a/include/asm-mips/mach-ip27/mangle-port.h
+++ b/include/asm-mips/mach-ip27/mangle-port.h
@@ -13,13 +13,13 @@
13#define __swizzle_addr_l(port) (port) 13#define __swizzle_addr_l(port) (port)
14#define __swizzle_addr_q(port) (port) 14#define __swizzle_addr_q(port) (port)
15 15
16# define ioswabb(a,x) (x) 16# define ioswabb(a, x) (x)
17# define __mem_ioswabb(a,x) (x) 17# define __mem_ioswabb(a, x) (x)
18# define ioswabw(a,x) (x) 18# define ioswabw(a, x) (x)
19# define __mem_ioswabw(a,x) cpu_to_le16(x) 19# define __mem_ioswabw(a, x) cpu_to_le16(x)
20# define ioswabl(a,x) (x) 20# define ioswabl(a, x) (x)
21# define __mem_ioswabl(a,x) cpu_to_le32(x) 21# define __mem_ioswabl(a, x) cpu_to_le32(x)
22# define ioswabq(a,x) (x) 22# define ioswabq(a, x) (x)
23# define __mem_ioswabq(a,x) cpu_to_le32(x) 23# define __mem_ioswabq(a, x) cpu_to_le32(x)
24 24
25#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ 25#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index 61d9be3f3175..372291f53fb9 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -2,9 +2,27 @@
2#define _ASM_MACH_TOPOLOGY_H 1 2#define _ASM_MACH_TOPOLOGY_H 1
3 3
4#include <asm/sn/hub.h> 4#include <asm/sn/hub.h>
5#include <asm/sn/types.h>
5#include <asm/mmzone.h> 6#include <asm/mmzone.h>
6 7
7#define cpu_to_node(cpu) (cpu_data[(cpu)].p_nodeid) 8struct cpuinfo_ip27 {
9// cpuid_t p_cpuid; /* PROM assigned cpuid */
10 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
11 nasid_t p_nasid; /* my node ID in numa-as-id-space */
12 unsigned char p_slice; /* Physical position on node board */
13#if 0
14 unsigned long loops_per_sec;
15 unsigned long ipi_count;
16 unsigned long irq_attempt[NR_IRQS];
17 unsigned long smp_local_irq_count;
18 unsigned long prof_multiplier;
19 unsigned long prof_counter;
20#endif
21};
22
23extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
24
25#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
8#define parent_node(node) (node) 26#define parent_node(node) (node)
9#define node_to_cpumask(node) (hub_data(node)->h_cpus) 27#define node_to_cpumask(node) (hub_data(node)->h_cpus)
10#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) 28#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h
new file mode 100644
index 000000000000..e2ddcc9b1fff
--- /dev/null
+++ b/include/asm-mips/mach-ip27/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_IP27_WAR_H
9#define __ASM_MIPS_MACH_IP27_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
index f6198a21fba1..b1e0be60f720 100644
--- a/include/asm-mips/mach-ip32/kmalloc.h
+++ b/include/asm-mips/mach-ip32/kmalloc.h
@@ -2,7 +2,7 @@
2#define __ASM_MACH_IP32_KMALLOC_H 2#define __ASM_MACH_IP32_KMALLOC_H
3 3
4 4
5#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000) 5#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
6#define ARCH_KMALLOC_MINALIGN 32 6#define ARCH_KMALLOC_MINALIGN 32
7#else 7#else
8#define ARCH_KMALLOC_MINALIGN 128 8#define ARCH_KMALLOC_MINALIGN 128
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h
index 81320eb55324..f1d0f1756a9f 100644
--- a/include/asm-mips/mach-ip32/mangle-port.h
+++ b/include/asm-mips/mach-ip32/mangle-port.h
@@ -14,13 +14,13 @@
14#define __swizzle_addr_l(port) (port) 14#define __swizzle_addr_l(port) (port)
15#define __swizzle_addr_q(port) (port) 15#define __swizzle_addr_q(port) (port)
16 16
17# define ioswabb(a,x) (x) 17# define ioswabb(a, x) (x)
18# define __mem_ioswabb(a,x) (x) 18# define __mem_ioswabb(a, x) (x)
19# define ioswabw(a,x) (x) 19# define ioswabw(a, x) (x)
20# define __mem_ioswabw(a,x) cpu_to_le16(x) 20# define __mem_ioswabw(a, x) cpu_to_le16(x)
21# define ioswabl(a,x) (x) 21# define ioswabl(a, x) (x)
22# define __mem_ioswabl(a,x) cpu_to_le32(x) 22# define __mem_ioswabl(a, x) cpu_to_le32(x)
23# define ioswabq(a,x) (x) 23# define ioswabq(a, x) (x)
24# define __mem_ioswabq(a,x) cpu_to_le32(x) 24# define __mem_ioswabq(a, x) cpu_to_le32(x)
25 25
26#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ 26#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h
new file mode 100644
index 000000000000..d194056dcd7a
--- /dev/null
+++ b/include/asm-mips/mach-ip32/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_IP32_WAR_H
9#define __ASM_MIPS_MACH_IP32_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h
index f44fdba1998b..987f727afe25 100644
--- a/include/asm-mips/mach-jazz/mc146818rtc.h
+++ b/include/asm-mips/mach-jazz/mc146818rtc.h
@@ -4,12 +4,15 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle 6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 * Copyright (C) 2007 Thomas Bogendoerfer
7 * 8 *
8 * RTC routines for Jazz style attached Dallas chip. 9 * RTC routines for Jazz style attached Dallas chip.
9 */ 10 */
10#ifndef __ASM_MACH_JAZZ_MC146818RTC_H 11#ifndef __ASM_MACH_JAZZ_MC146818RTC_H
11#define __ASM_MACH_JAZZ_MC146818RTC_H 12#define __ASM_MACH_JAZZ_MC146818RTC_H
12 13
14#include <linux/delay.h>
15
13#include <asm/io.h> 16#include <asm/io.h>
14#include <asm/jazz.h> 17#include <asm/jazz.h>
15 18
@@ -19,16 +22,17 @@
19static inline unsigned char CMOS_READ(unsigned long addr) 22static inline unsigned char CMOS_READ(unsigned long addr)
20{ 23{
21 outb_p(addr, RTC_PORT(0)); 24 outb_p(addr, RTC_PORT(0));
22 25 return *(volatile char *)JAZZ_RTC_BASE;
23 return *(char *)JAZZ_RTC_BASE;
24} 26}
25 27
26static inline void CMOS_WRITE(unsigned char data, unsigned long addr) 28static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
27{ 29{
28 outb_p(addr, RTC_PORT(0)); 30 outb_p(addr, RTC_PORT(0));
29 *(char *)JAZZ_RTC_BASE = data; 31 *(volatile char *)JAZZ_RTC_BASE = data;
30} 32}
31 33
32#define RTC_ALWAYS_BCD 0 34#define RTC_ALWAYS_BCD 0
33 35
36#define mc146818_decode_year(year) ((year) + 1980)
37
34#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ 38#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */
diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h
new file mode 100644
index 000000000000..6158ee861bfd
--- /dev/null
+++ b/include/asm-mips/mach-jazz/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H
9#define __ASM_MIPS_MACH_JAZZ_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h
index 501a202631b5..11bffcd1043b 100644
--- a/include/asm-mips/mach-jmr3927/mangle-port.h
+++ b/include/asm-mips/mach-jmr3927/mangle-port.h
@@ -6,13 +6,13 @@ extern unsigned long __swizzle_addr_b(unsigned long port);
6#define __swizzle_addr_l(port) (port) 6#define __swizzle_addr_l(port) (port)
7#define __swizzle_addr_q(port) (port) 7#define __swizzle_addr_q(port) (port)
8 8
9#define ioswabb(a,x) (x) 9#define ioswabb(a, x) (x)
10#define __mem_ioswabb(a,x) (x) 10#define __mem_ioswabb(a, x) (x)
11#define ioswabw(a,x) le16_to_cpu(x) 11#define ioswabw(a, x) le16_to_cpu(x)
12#define __mem_ioswabw(a,x) (x) 12#define __mem_ioswabw(a, x) (x)
13#define ioswabl(a,x) le32_to_cpu(x) 13#define ioswabl(a, x) le32_to_cpu(x)
14#define __mem_ioswabl(a,x) (x) 14#define __mem_ioswabl(a, x) (x)
15#define ioswabq(a,x) le64_to_cpu(x) 15#define ioswabq(a, x) le64_to_cpu(x)
16#define __mem_ioswabq(a,x) (x) 16#define __mem_ioswabq(a, x) (x)
17 17
18#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ 18#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h
new file mode 100644
index 000000000000..1ff55fb3fbcb
--- /dev/null
+++ b/include/asm-mips/mach-jmr3927/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H
9#define __ASM_MIPS_MACH_JMR3927_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
new file mode 100644
index 000000000000..1a9ad45cc135
--- /dev/null
+++ b/include/asm-mips/mach-lasat/mach-gt64120.h
@@ -0,0 +1,27 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
9#define _ASM_GT64120_LASAT_GT64120_DEP_H
10
11/*
12 * GT64120 config space base address on Lasat 100
13 */
14#define GT64120_BASE (KSEG1ADDR(0x14000000))
15
16/*
17 * PCI Bus allocation
18 *
19 * (Guessing ...)
20 */
21#define GT_PCI_MEM_BASE 0x12000000UL
22#define GT_PCI_MEM_SIZE 0x02000000UL
23#define GT_PCI_IO_BASE 0x10000000UL
24#define GT_PCI_IO_SIZE 0x02000000UL
25#define GT_ISA_IO_BASE PCI_IO_BASE
26
27#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h
new file mode 100644
index 000000000000..bb1e0325c9be
--- /dev/null
+++ b/include/asm-mips/mach-lasat/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_LASAT_WAR_H
9#define __ASM_MIPS_MACH_LASAT_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h
new file mode 100644
index 000000000000..05f89e0f2a11
--- /dev/null
+++ b/include/asm-mips/mach-lemote/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H
9#define __ASM_MIPS_MACH_LEMOTE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */
diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h
index 511f7cf3a6be..0f863148f3b6 100644
--- a/include/asm-mips/mach-mips/mach-gt64120.h
+++ b/include/asm-mips/mach-mips/mach-gt64120.h
@@ -16,13 +16,4 @@ extern unsigned long _pcictrl_gt64120;
16 */ 16 */
17#define GT64120_BASE _pcictrl_gt64120 17#define GT64120_BASE _pcictrl_gt64120
18 18
19/*
20 * PCI Bus allocation
21 */
22#define GT_PCI_MEM_BASE 0x12000000UL
23#define GT_PCI_MEM_SIZE 0x02000000UL
24#define GT_PCI_IO_BASE 0x10000000UL
25#define GT_PCI_IO_SIZE 0x02000000UL
26#define GT_ISA_IO_BASE PCI_IO_BASE
27
28#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ 19#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h
new file mode 100644
index 000000000000..7c6931d5f45f
--- /dev/null
+++ b/include/asm-mips/mach-mips/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h
new file mode 100644
index 000000000000..c8a74a3515e0
--- /dev/null
+++ b/include/asm-mips/mach-mipssim/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
9#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
index 50c1e413a688..b52e0e7ee3fb 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -32,38 +32,38 @@
32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
33 33
34#define PB1000_PCR 0xBE000000 34#define PB1000_PCR 0xBE000000
35 #define PCR_SLOT_0_VPP0 (1<<0) 35# define PCR_SLOT_0_VPP0 (1<<0)
36 #define PCR_SLOT_0_VPP1 (1<<1) 36# define PCR_SLOT_0_VPP1 (1<<1)
37 #define PCR_SLOT_0_VCC0 (1<<2) 37# define PCR_SLOT_0_VCC0 (1<<2)
38 #define PCR_SLOT_0_VCC1 (1<<3) 38# define PCR_SLOT_0_VCC1 (1<<3)
39 #define PCR_SLOT_0_RST (1<<4) 39# define PCR_SLOT_0_RST (1<<4)
40 40
41 #define PCR_SLOT_1_VPP0 (1<<8) 41# define PCR_SLOT_1_VPP0 (1<<8)
42 #define PCR_SLOT_1_VPP1 (1<<9) 42# define PCR_SLOT_1_VPP1 (1<<9)
43 #define PCR_SLOT_1_VCC0 (1<<10) 43# define PCR_SLOT_1_VCC0 (1<<10)
44 #define PCR_SLOT_1_VCC1 (1<<11) 44# define PCR_SLOT_1_VCC1 (1<<11)
45 #define PCR_SLOT_1_RST (1<<12) 45# define PCR_SLOT_1_RST (1<<12)
46 46
47#define PB1000_MDR 0xBE000004 47#define PB1000_MDR 0xBE000004
48 #define MDR_PI (1<<5) /* pcmcia int latch */ 48# define MDR_PI (1<<5) /* pcmcia int latch */
49 #define MDR_EPI (1<<14) /* enable pcmcia int */ 49# define MDR_EPI (1<<14) /* enable pcmcia int */
50 #define MDR_CPI (1<<15) /* clear pcmcia int */ 50# define MDR_CPI (1<<15) /* clear pcmcia int */
51 51
52#define PB1000_ACR1 0xBE000008 52#define PB1000_ACR1 0xBE000008
53 #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ 53# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
54 #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ 54# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
55 #define ACR1_SLOT_0_READY (1<<2) /* ready */ 55# define ACR1_SLOT_0_READY (1<<2) /* ready */
56 #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ 56# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
57 #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ 57# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
58 #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ 58# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
59 #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ 59# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
60 #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ 60# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
61 #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ 61# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
62 #define ACR1_SLOT_1_READY (1<<10) /* ready */ 62# define ACR1_SLOT_1_READY (1<<10) /* ready */
63 #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ 63# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
64 #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ 64# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
65 #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ 65# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
66 #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ 66# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
67 67
68#define CPLD_AUX0 0xBE00000C 68#define CPLD_AUX0 0xBE00000C
69#define CPLD_AUX1 0xBE000010 69#define CPLD_AUX1 0xBE000010
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 4c5a1cd01841..63aa3926b297 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -29,44 +29,44 @@
29 29
30#define PB1100_IDENT 0xAE000000 30#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004 31#define BOARD_STATUS_REG 0xAE000004
32 #define PB1100_ROM_SEL (1<<15) 32# define PB1100_ROM_SEL (1<<15)
33 #define PB1100_ROM_SIZ (1<<14) 33# define PB1100_ROM_SIZ (1<<14)
34 #define PB1100_SWAP_BOOT (1<<13) 34# define PB1100_SWAP_BOOT (1<<13)
35 #define PB1100_FLASH_WP (1<<12) 35# define PB1100_FLASH_WP (1<<12)
36 #define PB1100_ROM_H_STS (1<<11) 36# define PB1100_ROM_H_STS (1<<11)
37 #define PB1100_ROM_L_STS (1<<10) 37# define PB1100_ROM_L_STS (1<<10)
38 #define PB1100_FLASH_H_STS (1<<9) 38# define PB1100_FLASH_H_STS (1<<9)
39 #define PB1100_FLASH_L_STS (1<<8) 39# define PB1100_FLASH_L_STS (1<<8)
40 #define PB1100_SRAM_SIZ (1<<7) 40# define PB1100_SRAM_SIZ (1<<7)
41 #define PB1100_TSC_BUSY (1<<6) 41# define PB1100_TSC_BUSY (1<<6)
42 #define PB1100_PCMCIA_VS_MASK (3<<4) 42# define PB1100_PCMCIA_VS_MASK (3<<4)
43 #define PB1100_RS232_CD (1<<3) 43# define PB1100_RS232_CD (1<<3)
44 #define PB1100_RS232_CTS (1<<2) 44# define PB1100_RS232_CTS (1<<2)
45 #define PB1100_RS232_DSR (1<<1) 45# define PB1100_RS232_DSR (1<<1)
46 #define PB1100_RS232_RI (1<<0) 46# define PB1100_RS232_RI (1<<0)
47 47
48#define PB1100_IRDA_RS232 0xAE00000C 48#define PB1100_IRDA_RS232 0xAE00000C
49 #define PB1100_IRDA_FULL (0<<14) /* full power */ 49# define PB1100_IRDA_FULL (0<<14) /* full power */
50 #define PB1100_IRDA_SHUTDOWN (1<<14) 50# define PB1100_IRDA_SHUTDOWN (1<<14)
51 #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ 51# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
52 #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ 52# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
53 #define PB1100_IRDA_FIR (1<<13) 53# define PB1100_IRDA_FIR (1<<13)
54 54
55#define PCMCIA_BOARD_REG 0xAE000010 55#define PCMCIA_BOARD_REG 0xAE000010
56 #define PB1100_SD_WP1_RO (1<<15) /* read only */ 56# define PB1100_SD_WP1_RO (1<<15) /* read only */
57 #define PB1100_SD_WP0_RO (1<<14) /* read only */ 57# define PB1100_SD_WP0_RO (1<<14) /* read only */
58 #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ 58# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
59 #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ 59# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
60 #define PB1100_SEL_SD_CONN1 (1<<9) 60# define PB1100_SEL_SD_CONN1 (1<<9)
61 #define PB1100_SEL_SD_CONN0 (1<<8) 61# define PB1100_SEL_SD_CONN0 (1<<8)
62 #define PC_DEASSERT_RST (1<<7) 62# define PC_DEASSERT_RST (1<<7)
63 #define PC_DRV_EN (1<<4) 63# define PC_DRV_EN (1<<4)
64 64
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ 65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66 66
67#define PB1100_RST_VDDI 0xAE00001C 67#define PB1100_RST_VDDI 0xAE00001C
68 #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ 68# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
69 #define PB1100_VDDI_MASK (0x1F) 69# define PB1100_VDDI_MASK (0x1F)
70 70
71#define PB1100_LEDS 0xAE000018 71#define PB1100_LEDS 0xAE000018
72 72
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
index 57102fa9da51..bdde00c9199b 100644
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -44,7 +44,7 @@ cache_begin: li t0, (1<<28)
44 mfc0 t0, CP0_CONFIG, 7 44 mfc0 t0, CP0_CONFIG, 7
45 HAZARD_CP0 45 HAZARD_CP0
46 46
47 and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */ 47 and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
48 mtc0 t0, CP0_CONFIG, 7 48 mtc0 t0, CP0_CONFIG, 7
49 HAZARD_CP0 49 HAZARD_CP0
50 50
@@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated:
200 200
201 icache_invd_loop: 201 icache_invd_loop:
202 /* 9 == register t1 */ 202 /* 9 == register t1 */
203 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ 203 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ 204 (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
205 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ 205 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ 206 (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
207 207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ 208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ 209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
@@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated:
235 235
236 dcache_wbinvd_loop: 236 dcache_wbinvd_loop:
237 /* 9 == register t1 */ 237 /* 9 == register t1 */
238 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ 239 (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
240 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ 241 (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
242 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ 243 (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
244 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ 245 (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
246 246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ 247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ 248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
index 814a7a15ab49..ad7608d44874 100644
--- a/include/asm-mips/mach-pnx8550/uart.h
+++ b/include/asm-mips/mach-pnx8550/uart.h
@@ -15,7 +15,7 @@
15 15
16/* early macros needed for prom/kgdb */ 16/* early macros needed for prom/kgdb */
17 17
18#define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000) 18#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
19#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) 19#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
20#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) 20#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
21#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) 21#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h
new file mode 100644
index 000000000000..d0458dd082f9
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
9#define __ASM_MIPS_MACH_PNX8550_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h
new file mode 100644
index 000000000000..0eaf0c548a47
--- /dev/null
+++ b/include/asm-mips/mach-qemu/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_QEMU_WAR_H
9#define __ASM_MIPS_MACH_QEMU_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */
diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h
new file mode 100644
index 000000000000..948d3129a114
--- /dev/null
+++ b/include/asm-mips/mach-rm/war.h
@@ -0,0 +1,29 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_RM_WAR_H
9#define __ASM_MIPS_MACH_RM_WAR_H
10
11/*
12 * The RM200C seems to have been shipped only with V2.0 R4600s
13 */
14
15#define R4600_V1_INDEX_ICACHEOP_WAR 0
16#define R4600_V1_HIT_CACHEOP_WAR 0
17#define R4600_V2_HIT_CACHEOP_WAR 1
18#define R5432_CP0_INTERRUPT_WAR 0
19#define BCM1250_M3_WAR 0
20#define SIBYTE_1956_WAR 0
21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0
28
29#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
index 63d5bf649af1..1c1f92415b9a 100644
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -9,7 +9,7 @@
9#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
10 10
11/* 11/*
12 * Sibyte are MIPS64 processors weired to a specific configuration 12 * Sibyte are MIPS64 processors wired to a specific configuration
13 */ 13 */
14#define cpu_has_watch 1 14#define cpu_has_watch 1
15#define cpu_has_mips16 0 15#define cpu_has_mips16 0
@@ -33,6 +33,11 @@
33#define cpu_has_nofpuex 0 33#define cpu_has_nofpuex 0
34#define cpu_has_64bits 1 34#define cpu_has_64bits 1
35 35
36#define cpu_has_mips32r1 1
37#define cpu_has_mips32r2 0
38#define cpu_has_mips64r1 1
39#define cpu_has_mips64r2 0
40
36#define cpu_has_inclusive_pcaches 0 41#define cpu_has_inclusive_pcaches 0
37 42
38#define cpu_dcache_line_size() 32 43#define cpu_dcache_line_size() 32
diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h
new file mode 100644
index 000000000000..7950ef4f032c
--- /dev/null
+++ b/include/asm-mips/mach-sibyte/war.h
@@ -0,0 +1,37 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
9#define __ASM_MIPS_MACH_SIBYTE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15
16#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
17 defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
18
19#define BCM1250_M3_WAR 1
20#define SIBYTE_1956_WAR 1
21
22#else
23
24#define BCM1250_M3_WAR 0
25#define SIBYTE_1956_WAR 0
26
27#endif
28
29#define MIPS4K_ICACHE_REFILL_WAR 0
30#define MIPS_CACHE_SYNC_WAR 0
31#define TX49XX_ICACHE_INDEX_INV_WAR 0
32#define RM9000_CDEX_SMP_WAR 0
33#define ICACHE_REFILLS_WORKAROUND_WAR 0
34#define R10000_LLSC_WAR 0
35#define MIPS34K_MISSED_ITLB_WAR 0
36
37#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h
new file mode 100644
index 000000000000..39b5d1177c57
--- /dev/null
+++ b/include/asm-mips/mach-tx49xx/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
9#define __ASM_MIPS_MACH_TX49XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 1
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h
new file mode 100644
index 000000000000..56a38926412a
--- /dev/null
+++ b/include/asm-mips/mach-vr41xx/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H
9#define __ASM_MIPS_MACH_VR41XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h
index ba9205a04582..00d8bf6164a9 100644
--- a/include/asm-mips/mach-wrppmc/mach-gt64120.h
+++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h
@@ -43,7 +43,6 @@
43#define GT_PCI_MEM_SIZE 0x02000000UL 43#define GT_PCI_MEM_SIZE 0x02000000UL
44#define GT_PCI_IO_BASE 0x11000000UL 44#define GT_PCI_IO_BASE 0x11000000UL
45#define GT_PCI_IO_SIZE 0x02000000UL 45#define GT_PCI_IO_SIZE 0x02000000UL
46#define GT_ISA_IO_BASE PCI_IO_BASE
47 46
48/* 47/*
49 * PCI interrupts will come in on either the INTA or INTD interrups lines, 48 * PCI interrupts will come in on either the INTA or INTD interrups lines,
diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h
new file mode 100644
index 000000000000..ac48629bb1ce
--- /dev/null
+++ b/include/asm-mips/mach-wrppmc/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
9#define __ASM_MIPS_MACH_WRPPMC_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h
new file mode 100644
index 000000000000..e5c6d53efc86
--- /dev/null
+++ b/include/asm-mips/mach-yosemite/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
9#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h
index 41ac8d363c67..cdc379a0a94e 100644
--- a/include/asm-mips/mc146818-time.h
+++ b/include/asm-mips/mc146818-time.h
@@ -63,8 +63,8 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
63 BIN_TO_BCD(real_seconds); 63 BIN_TO_BCD(real_seconds);
64 BIN_TO_BCD(real_minutes); 64 BIN_TO_BCD(real_minutes);
65 } 65 }
66 CMOS_WRITE(real_seconds,RTC_SECONDS); 66 CMOS_WRITE(real_seconds, RTC_SECONDS);
67 CMOS_WRITE(real_minutes,RTC_MINUTES); 67 CMOS_WRITE(real_minutes, RTC_MINUTES);
68 } else { 68 } else {
69 printk(KERN_WARNING 69 printk(KERN_WARNING
70 "set_rtc_mmss: can't update from %d to %d\n", 70 "set_rtc_mmss: can't update from %d to %d\n",
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
index dc3fc32eedd8..a0f04bb99c99 100644
--- a/include/asm-mips/mips-boards/bonito64.h
+++ b/include/asm-mips/mips-boards/bonito64.h
@@ -387,7 +387,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
387#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 387#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
388#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 388#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
389#define BONITO_PCIMAP_PCIMAP_2 0x00040000 389#define BONITO_PCIMAP_PCIMAP_2 0x00040000
390#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) 390#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
391 391
392#define BONITO_PCIMAP_WINSIZE (1<<26) 392#define BONITO_PCIMAP_WINSIZE (1<<26)
393#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) 393#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
@@ -412,19 +412,19 @@ extern unsigned long _pcictrl_bonito_pcicfg;
412 412
413#define BONITO_PCIMEMBASECFG_ASHIFT 23 413#define BONITO_PCIMEMBASECFG_ASHIFT 23
414#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff 414#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
415#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) 415#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
416#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) 416#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
417 417
418#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) 418#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
419 419
420 420
421#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 421#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
422#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 422#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
423#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 423#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
424 424
425#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ 425#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \
426 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ 426 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
427 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ 427 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
428 ) 428 )
429 429
430/* PCICmd */ 430/* PCICmd */
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
index eec91001bb65..93bf4e51b8a4 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/include/asm-mips/mips-boards/malta.h
@@ -72,7 +72,7 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
72 72
73#define SMSC_CONFIG_ACTIVATE_ENABLE 1 73#define SMSC_CONFIG_ACTIVATE_ENABLE 1
74 74
75#define SMSC_WRITE(x,a) outb(x,a) 75#define SMSC_WRITE(x, a) outb(x, a)
76 76
77#define MALTA_JMPRS_REG 0x1f000210 77#define MALTA_JMPRS_REG 0x1f000210
78 78
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
index 294bca12cd3f..5a2f8a3a6a1f 100644
--- a/include/asm-mips/mipsmtregs.h
+++ b/include/asm-mips/mipsmtregs.h
@@ -41,27 +41,27 @@
41 * Macros for use in assembly language code 41 * Macros for use in assembly language code
42 */ 42 */
43 43
44#define CP0_MVPCONTROL $0,1 44#define CP0_MVPCONTROL $0, 1
45#define CP0_MVPCONF0 $0,2 45#define CP0_MVPCONF0 $0, 2
46#define CP0_MVPCONF1 $0,3 46#define CP0_MVPCONF1 $0, 3
47#define CP0_VPECONTROL $1,1 47#define CP0_VPECONTROL $1, 1
48#define CP0_VPECONF0 $1,2 48#define CP0_VPECONF0 $1, 2
49#define CP0_VPECONF1 $1,3 49#define CP0_VPECONF1 $1, 3
50#define CP0_YQMASK $1,4 50#define CP0_YQMASK $1, 4
51#define CP0_VPESCHEDULE $1,5 51#define CP0_VPESCHEDULE $1, 5
52#define CP0_VPESCHEFBK $1,6 52#define CP0_VPESCHEFBK $1, 6
53#define CP0_TCSTATUS $2,1 53#define CP0_TCSTATUS $2, 1
54#define CP0_TCBIND $2,2 54#define CP0_TCBIND $2, 2
55#define CP0_TCRESTART $2,3 55#define CP0_TCRESTART $2, 3
56#define CP0_TCHALT $2,4 56#define CP0_TCHALT $2, 4
57#define CP0_TCCONTEXT $2,5 57#define CP0_TCCONTEXT $2, 5
58#define CP0_TCSCHEDULE $2,6 58#define CP0_TCSCHEDULE $2, 6
59#define CP0_TCSCHEFBK $2,7 59#define CP0_TCSCHEFBK $2, 7
60#define CP0_SRSCONF0 $6,1 60#define CP0_SRSCONF0 $6, 1
61#define CP0_SRSCONF1 $6,2 61#define CP0_SRSCONF1 $6, 2
62#define CP0_SRSCONF2 $6,3 62#define CP0_SRSCONF2 $6, 3
63#define CP0_SRSCONF3 $6,4 63#define CP0_SRSCONF3 $6, 4
64#define CP0_SRSCONF4 $6,5 64#define CP0_SRSCONF4 $6, 5
65 65
66#endif 66#endif
67 67
@@ -291,7 +291,7 @@ static inline void ehb(void)
291 __res; \ 291 __res; \
292}) 292})
293 293
294#define mftr(rt,u,sel) \ 294#define mftr(rt, u, sel) \
295({ \ 295({ \
296 unsigned long __res; \ 296 unsigned long __res; \
297 \ 297 \
@@ -315,7 +315,7 @@ do { \
315 : : "r" (v)); \ 315 : : "r" (v)); \
316} while (0) 316} while (0)
317 317
318#define mttc0(rd,sel,v) \ 318#define mttc0(rd, sel, v) \
319({ \ 319({ \
320 __asm__ __volatile__( \ 320 __asm__ __volatile__( \
321 " .set push \n" \ 321 " .set push \n" \
@@ -330,7 +330,7 @@ do { \
330}) 330})
331 331
332 332
333#define mttr(rd,u,sel,v) \ 333#define mttr(rd, u, sel, v) \
334({ \ 334({ \
335 __asm__ __volatile__( \ 335 __asm__ __volatile__( \
336 "mttr %0," #rd ", " #u ", " #sel \ 336 "mttr %0," #rd ", " #u ", " #sel \
@@ -362,7 +362,7 @@ do { \
362#define write_vpe_c0_config1(val) mttc0(16, 1, val) 362#define write_vpe_c0_config1(val) mttc0(16, 1, val)
363#define read_vpe_c0_config7() mftc0(16, 7) 363#define read_vpe_c0_config7() mftc0(16, 7)
364#define write_vpe_c0_config7(val) mttc0(16, 7, val) 364#define write_vpe_c0_config7(val) mttc0(16, 7, val)
365#define read_vpe_c0_ebase() mftc0(15,1) 365#define read_vpe_c0_ebase() mftc0(15, 1)
366#define write_vpe_c0_ebase(val) mttc0(15, 1, val) 366#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
367#define write_vpe_c0_compare(val) mttc0(11, 0, val) 367#define write_vpe_c0_compare(val) mttc0(11, 0, val)
368#define read_vpe_c0_badvaddr() mftc0(8, 0) 368#define read_vpe_c0_badvaddr() mftc0(8, 0)
@@ -372,15 +372,15 @@ do { \
372 372
373/* TC */ 373/* TC */
374#define read_tc_c0_tcstatus() mftc0(2, 1) 374#define read_tc_c0_tcstatus() mftc0(2, 1)
375#define write_tc_c0_tcstatus(val) mttc0(2,1,val) 375#define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
376#define read_tc_c0_tcbind() mftc0(2, 2) 376#define read_tc_c0_tcbind() mftc0(2, 2)
377#define write_tc_c0_tcbind(val) mttc0(2,2,val) 377#define write_tc_c0_tcbind(val) mttc0(2, 2, val)
378#define read_tc_c0_tcrestart() mftc0(2, 3) 378#define read_tc_c0_tcrestart() mftc0(2, 3)
379#define write_tc_c0_tcrestart(val) mttc0(2,3,val) 379#define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
380#define read_tc_c0_tchalt() mftc0(2, 4) 380#define read_tc_c0_tchalt() mftc0(2, 4)
381#define write_tc_c0_tchalt(val) mttc0(2,4,val) 381#define write_tc_c0_tchalt(val) mttc0(2, 4, val)
382#define read_tc_c0_tccontext() mftc0(2, 5) 382#define read_tc_c0_tccontext() mftc0(2, 5)
383#define write_tc_c0_tccontext(val) mttc0(2,5,val) 383#define write_tc_c0_tccontext(val) mttc0(2, 5, val)
384 384
385/* GPR */ 385/* GPR */
386#define read_tc_gpr_sp() mftgpr(29) 386#define read_tc_gpr_sp() mftgpr(29)
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 18f47f1e8cd5..aa17f658f73c 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -981,7 +981,7 @@ do { \
981#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 981#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
982 982
983/* MIPSR2 */ 983/* MIPSR2 */
984#define read_c0_hwrena() __read_32bit_c0_register($7,0) 984#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
985#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 985#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
986 986
987#define read_c0_intctl() __read_32bit_c0_register($12, 1) 987#define read_c0_intctl() __read_32bit_c0_register($12, 1)
@@ -993,7 +993,7 @@ do { \
993#define read_c0_srsmap() __read_32bit_c0_register($12, 3) 993#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
994#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 994#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
995 995
996#define read_c0_ebase() __read_32bit_c0_register($15,1) 996#define read_c0_ebase() __read_32bit_c0_register($15, 1)
997#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 997#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
998 998
999/* 999/*
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 65024ffd7879..0c4f245eaeb2 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -107,7 +107,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
107 107
108#else /* CONFIG_MIPS_MT_SMTC */ 108#else /* CONFIG_MIPS_MT_SMTC */
109 109
110#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu)) 110#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
111 111
112#endif /* CONFIG_MIPS_MT_SMTC */ 112#endif /* CONFIG_MIPS_MT_SMTC */
113 113
@@ -120,7 +120,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
120{ 120{
121 int i; 121 int i;
122 122
123 for (i = 0; i < num_online_cpus(); i++) 123 for_each_online_cpu(i)
124 cpu_context(i, mm) = 0; 124 cpu_context(i, mm) = 0;
125 125
126 return 0; 126 return 0;
@@ -191,7 +191,7 @@ static inline void destroy_context(struct mm_struct *mm)
191{ 191{
192} 192}
193 193
194#define deactivate_mm(tsk,mm) do { } while (0) 194#define deactivate_mm(tsk, mm) do { } while (0)
195 195
196/* 196/*
197 * After we have set current->mm to a new value, this activates 197 * After we have set current->mm to a new value, this activates
@@ -284,7 +284,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
284 int i; 284 int i;
285 285
286 /* SMTC shares the TLB (and ASIDs) across VPEs */ 286 /* SMTC shares the TLB (and ASIDs) across VPEs */
287 for (i = 0; i < num_online_cpus(); i++) { 287 for_each_online_cpu(i) {
288 if((smtc_status & SMTC_TLB_SHARED) 288 if((smtc_status & SMTC_TLB_SHARED)
289 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 289 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
290 cpu_context(i, mm) = 0; 290 cpu_context(i, mm) = 0;
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
new file mode 100644
index 000000000000..c3ca959aa4d9
--- /dev/null
+++ b/include/asm-mips/nile4.h
@@ -0,0 +1,310 @@
1/*
2 * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 *
7 * This file is based on the following documentation:
8 *
9 * NEC Vrc 5074 System Controller Data Sheet, June 1998
10 */
11
12#ifndef _ASM_NILE4_H
13#define _ASM_NILE4_H
14
15#define NILE4_BASE 0xbfa00000
16#define NILE4_SIZE 0x00200000 /* 2 MB */
17
18
19 /*
20 * Physical Device Address Registers (PDARs)
21 */
22
23#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
24#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
25#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
26#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
27#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
28#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
29#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
30#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
31#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
32#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
33#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
34#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */
35 /* [R/W] */
36#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
37
38
39 /*
40 * CPU Interface Registers
41 */
42
43#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */
44#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */
45#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
46#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
47 /* Enable [R/W] */
48#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
49#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
50
51
52 /*
53 * Memory-Interface Registers
54 */
55
56#define NILE4_MEMCTRL 0x00C0 /* Memory Control */
57#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
58#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
59
60
61 /*
62 * PCI-Bus Registers
63 */
64
65#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
66#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
67#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
68#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
69#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
70
71
72 /*
73 * Local-Bus Registers
74 */
75
76#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
77#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
78#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
79#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
80#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
81#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
82#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
83#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
84#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
85 /* Enables [R/W] */
86#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
87#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
88
89
90 /*
91 * DMA Registers
92 */
93
94#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
95#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
96#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
97#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
98#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
99#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
100
101
102 /*
103 * Timer Registers
104 */
105
106#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
107#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
108#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
109#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
110#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
111#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
112#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
113#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
114
115
116 /*
117 * PCI Configuration Space Registers
118 */
119
120#define NILE4_PCI_BASE 0x0200
121
122#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
123#define NILE4_DID 0x0202 /* PCI Device ID [R] */
124#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
125#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
126#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
127#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
128#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
129#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
130#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
131#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */
132#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
133#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
134#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
135#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
136 /* (unimplemented) */
137#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
138#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
139#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
140 /* (unimplemented) */
141#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
142#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
143#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
144#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
145#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
146#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
147#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
148#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
149#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
150#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
151#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
152#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
153
154
155 /*
156 * Serial-Port Registers
157 */
158
159#define NILE4_UART_BASE 0x0300
160
161#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */
162#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */
163#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */
164#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */
165#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */
166#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */
167#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */
168#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */
169#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */
170#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */
171#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */
172#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */
173
174#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */
175
176
177 /*
178 * Interrupt Lines
179 */
180
181#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */
182#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */
183#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
184#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */
185#define NILE4_INT_UART 4 /* UART Interrupt */
186#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */
187#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */
188#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */
189#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
190#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
191#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
192#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
193#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
194#define NILE4_INT_RESV 13 /* Reserved */
195#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
196#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
197
198
199 /*
200 * Nile 4 Register Access
201 */
202
203static inline void nile4_sync(void)
204{
205 volatile u32 *p = (volatile u32 *)0xbfc00000;
206 (void)(*p);
207}
208
209static inline void nile4_out32(u32 offset, u32 val)
210{
211 *(volatile u32 *)(NILE4_BASE+offset) = val;
212 nile4_sync();
213}
214
215static inline u32 nile4_in32(u32 offset)
216{
217 u32 val = *(volatile u32 *)(NILE4_BASE+offset);
218 nile4_sync();
219 return val;
220}
221
222static inline void nile4_out16(u32 offset, u16 val)
223{
224 *(volatile u16 *)(NILE4_BASE+offset) = val;
225 nile4_sync();
226}
227
228static inline u16 nile4_in16(u32 offset)
229{
230 u16 val = *(volatile u16 *)(NILE4_BASE+offset);
231 nile4_sync();
232 return val;
233}
234
235static inline void nile4_out8(u32 offset, u8 val)
236{
237 *(volatile u8 *)(NILE4_BASE+offset) = val;
238 nile4_sync();
239}
240
241static inline u8 nile4_in8(u32 offset)
242{
243 u8 val = *(volatile u8 *)(NILE4_BASE+offset);
244 nile4_sync();
245 return val;
246}
247
248
249 /*
250 * Physical Device Address Registers
251 */
252
253extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
254 int on_memory_bus, int visible);
255
256
257 /*
258 * PCI Master Registers
259 */
260
261#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
262#define NILE4_PCICMD_IO 1 /* PCI I/O Space */
263#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
264#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
265
266
267 /*
268 * PCI Address Spaces
269 *
270 * Note that these are multiplexed using PCIINIT[01]!
271 */
272
273#define NILE4_PCI_IO_BASE 0xa6000000
274#define NILE4_PCI_MEM_BASE 0xa8000000
275#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
276#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
277
278
279extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
280
281
282 /*
283 * Interrupt Programming
284 */
285
286#define NUM_I8259_INTERRUPTS 16
287#define NUM_NILE4_INTERRUPTS 16
288
289#define IRQ_I8259_CASCADE NILE4_INT_INTE
290#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
291#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
292#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
293
294extern void nile4_map_irq(int nile4_irq, int cpu_irq);
295extern void nile4_map_irq_all(int cpu_irq);
296extern void nile4_enable_irq(unsigned int nile4_irq);
297extern void nile4_disable_irq(unsigned int nile4_irq);
298extern void nile4_disable_irq_all(void);
299extern u16 nile4_get_irq_stat(int cpu_irq);
300extern void nile4_enable_irq_output(int cpu_irq);
301extern void nile4_disable_irq_output(int cpu_irq);
302extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
303extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
304extern void nile4_clear_irq(int nile4_irq);
305extern void nile4_clear_irq_mask(u32 mask);
306extern u8 nile4_i8259_iack(void);
307extern void nile4_dump_irq_status(void); /* Debug */
308
309#endif
310
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 8c08fa904b2c..c2394f8b0fe1 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -25,13 +25,13 @@
25extern asmlinkage void handle_ibe(void); 25extern asmlinkage void handle_ibe(void);
26extern asmlinkage void handle_dbe(void); 26extern asmlinkage void handle_dbe(void);
27 27
28#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) 28#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr)))
29#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) 29#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr)))
30 30
31struct __large_pstruct { unsigned long buf[100]; }; 31struct __large_pstruct { unsigned long buf[100]; };
32#define __mp(x) (*(struct __large_pstruct *)(x)) 32#define __mp(x) (*(struct __large_pstruct *)(x))
33 33
34#define __get_dbe(x,ptr,size) \ 34#define __get_dbe(x, ptr, size) \
35({ \ 35({ \
36 long __gu_err; \ 36 long __gu_err; \
37 __typeof__(*(ptr)) __gu_val; \ 37 __typeof__(*(ptr)) __gu_val; \
@@ -70,7 +70,7 @@ struct __large_pstruct { unsigned long buf[100]; };
70 70
71extern void __get_dbe_unknown(void); 71extern void __get_dbe_unknown(void);
72 72
73#define __put_dbe(x,ptr,size) \ 73#define __put_dbe(x, ptr, size) \
74({ \ 74({ \
75 long __pu_err; \ 75 long __pu_err; \
76 __typeof__(*(ptr)) __pu_val; \ 76 __typeof__(*(ptr)) __pu_val; \
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index e3301e54d559..d2ea983bec06 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -153,7 +153,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
153 ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) 153 ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
154#endif 154#endif
155#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) 155#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
156#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) 156#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0))
157 157
158#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 158#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
159 159
diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h
index a742e04e82de..f52656826cce 100644
--- a/include/asm-mips/parport.h
+++ b/include/asm-mips/parport.h
@@ -6,10 +6,10 @@
6#ifndef _ASM_PARPORT_H 6#ifndef _ASM_PARPORT_H
7#define _ASM_PARPORT_H 7#define _ASM_PARPORT_H
8 8
9static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); 9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) 10static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
11{ 11{
12 return parport_pc_find_isa_ports (autoirq, autodma); 12 return parport_pc_find_isa_ports(autoirq, autodma);
13} 13}
14 14
15#endif /* _ASM_PARPORT_H */ 15#endif /* _ASM_PARPORT_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 4fcc185cb2d1..301ff2f28012 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -150,8 +150,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res)
150 return root; 150 return root;
151} 151}
152 152
153#ifdef CONFIG_PCI_DOMAINS
154
155#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 153#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
156 154
157static inline int pci_proc_domain(struct pci_bus *bus) 155static inline int pci_proc_domain(struct pci_bus *bus)
@@ -160,8 +158,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
160 return hose->need_domain_info; 158 return hose->need_domain_info;
161} 159}
162 160
163#endif /* CONFIG_PCI_DOMAINS */
164
165#endif /* __KERNEL__ */ 161#endif /* __KERNEL__ */
166 162
167/* implement the pci_ DMA API in terms of the generic device dma_ one */ 163/* implement the pci_ DMA API in terms of the generic device dma_ one */
diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h
index 0c45e7598f3f..b84feebf2cef 100644
--- a/include/asm-mips/pci/bridge.h
+++ b/include/asm-mips/pci/bridge.h
@@ -360,7 +360,7 @@ typedef struct bridge_err_cmdword_s {
360#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ 360#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */
361#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ 361#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\
362 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) 362 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
363#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ 363#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\
364 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ 364 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
365 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) 365 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
366 366
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index 9fb57c035213..81b72122207a 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -95,7 +95,7 @@ static inline void pte_free(struct page *pte)
95 __free_pages(pte, PTE_ORDER); 95 __free_pages(pte, PTE_ORDER);
96} 96}
97 97
98#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) 98#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte))
99 99
100#ifdef CONFIG_32BIT 100#ifdef CONFIG_32BIT
101 101
@@ -104,7 +104,7 @@ static inline void pte_free(struct page *pte)
104 * inside the pgd, so has no extra memory associated with it. 104 * inside the pgd, so has no extra memory associated with it.
105 */ 105 */
106#define pmd_free(x) do { } while (0) 106#define pmd_free(x) do { } while (0)
107#define __pmd_free_tlb(tlb,x) do { } while (0) 107#define __pmd_free_tlb(tlb, x) do { } while (0)
108 108
109#endif 109#endif
110 110
@@ -125,7 +125,7 @@ static inline void pmd_free(pmd_t *pmd)
125 free_pages((unsigned long)pmd, PMD_ORDER); 125 free_pages((unsigned long)pmd, PMD_ORDER);
126} 126}
127 127
128#define __pmd_free_tlb(tlb,x) pmd_free(x) 128#define __pmd_free_tlb(tlb, x) pmd_free(x)
129 129
130#endif 130#endif
131 131
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 59c865deb0c7..a0947092d0e0 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -140,7 +140,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
140#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 140#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
141 141
142/* to find an entry in a page-table-directory */ 142/* to find an entry in a page-table-directory */
143#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 143#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
144 144
145/* Find an entry in the third-level page table.. */ 145/* Find an entry in the third-level page table.. */
146#define __pte_offset(address) \ 146#define __pte_offset(address) \
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 49f5a1a2dfcd..943515f0ef87 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -104,7 +104,7 @@
104#define VMALLOC_START MAP_BASE 104#define VMALLOC_START MAP_BASE
105#define VMALLOC_END \ 105#define VMALLOC_END \
106 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) 106 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
107#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) && \ 107#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
108 VMALLOC_START != CKSSEG 108 VMALLOC_START != CKSSEG
109/* Load modules into 32bit-compatible segment. */ 109/* Load modules into 32bit-compatible segment. */
110#define MODULE_START CKSSEG 110#define MODULE_START CKSSEG
@@ -193,7 +193,7 @@ static inline void pud_clear(pud_t *pudp)
193#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 193#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
194 194
195/* to find an entry in a page-table-directory */ 195/* to find an entry in a page-table-directory */
196#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 196#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
197 197
198static inline unsigned long pud_page_vaddr(pud_t pud) 198static inline unsigned long pud_page_vaddr(pud_t pud)
199{ 199{
@@ -237,7 +237,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
237 237
238#define __swp_type(x) (((x).val >> 32) & 0xff) 238#define __swp_type(x) (((x).val >> 32) & 0xff)
239#define __swp_offset(x) ((x).val >> 40) 239#define __swp_offset(x) ((x).val >> 40)
240#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 240#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
241#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 241#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
242#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 242#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
243 243
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index d2ee28156743..17a7703a2969 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -103,7 +103,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
103 } 103 }
104 } 104 }
105} 105}
106#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 106#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
107 107
108static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 108static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
109{ 109{
@@ -140,7 +140,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
140 } 140 }
141#endif 141#endif
142} 142}
143#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 143#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
144 144
145static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 145static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
146{ 146{
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
index 4aaaff670361..8121a9a75bfd 100644
--- a/include/asm-mips/prctl.h
+++ b/include/asm-mips/prctl.h
@@ -36,6 +36,6 @@ struct prda {
36 36
37#define t_sys prda_sys 37#define t_sys prda_sys
38 38
39ptrdiff_t prctl (int op, int v1, int v2); 39ptrdiff_t prctl(int op, int v1, int v2);
40 40
41#endif 41#endif
diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h
index 531caf44560c..487ced4a40de 100644
--- a/include/asm-mips/qemu.h
+++ b/include/asm-mips/qemu.h
@@ -12,7 +12,7 @@
12 * Interrupt numbers 12 * Interrupt numbers
13 */ 13 */
14#define Q_PIC_IRQ_BASE 0 14#define Q_PIC_IRQ_BASE 0
15#define Q_COUNT_COMPARE_IRQ 16 15#define Q_COUNT_COMPARE_IRQ 23
16 16
17/* 17/*
18 * Qemu clock rate. Unlike on real MIPS this has no relation to the 18 * Qemu clock rate. Unlike on real MIPS this has no relation to the
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 3c8e3c8d1a9a..2b8466ffd3ca 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -354,7 +354,7 @@ static inline void blast_##pfx##cache##lsize(void) \
354 \ 354 \
355 for (ws = 0; ws < ws_end; ws += ws_inc) \ 355 for (ws = 0; ws < ws_end; ws += ws_inc) \
356 for (addr = start; addr < end; addr += lsize * 32) \ 356 for (addr = start; addr < end; addr += lsize * 32) \
357 cache##lsize##_unroll32(addr|ws,indexop); \ 357 cache##lsize##_unroll32(addr|ws, indexop); \
358 \ 358 \
359 __##pfx##flush_epilogue \ 359 __##pfx##flush_epilogue \
360} \ 360} \
@@ -367,7 +367,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
367 __##pfx##flush_prologue \ 367 __##pfx##flush_prologue \
368 \ 368 \
369 do { \ 369 do { \
370 cache##lsize##_unroll32(start,hitop); \ 370 cache##lsize##_unroll32(start, hitop); \
371 start += lsize * 32; \ 371 start += lsize * 32; \
372 } while (start < end); \ 372 } while (start < end); \
373 \ 373 \
@@ -388,7 +388,7 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
388 \ 388 \
389 for (ws = 0; ws < ws_end; ws += ws_inc) \ 389 for (ws = 0; ws < ws_end; ws += ws_inc) \
390 for (addr = start; addr < end; addr += lsize * 32) \ 390 for (addr = start; addr < end; addr += lsize * 32) \
391 cache##lsize##_unroll32(addr|ws,indexop); \ 391 cache##lsize##_unroll32(addr|ws, indexop); \
392 \ 392 \
393 __##pfx##flush_epilogue \ 393 __##pfx##flush_epilogue \
394} 394}
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index 3d6aa7c7ea81..080daa77f867 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -46,23 +46,23 @@ struct semaphore {
46} 46}
47 47
48#define __DECLARE_SEMAPHORE_GENERIC(name, count) \ 48#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
49 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) 49 struct semaphore name = __SEMAPHORE_INITIALIZER(name, count)
50 50
51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) 51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) 52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
53 53
54static inline void sema_init (struct semaphore *sem, int val) 54static inline void sema_init(struct semaphore *sem, int val)
55{ 55{
56 atomic_set(&sem->count, val); 56 atomic_set(&sem->count, val);
57 init_waitqueue_head(&sem->wait); 57 init_waitqueue_head(&sem->wait);
58} 58}
59 59
60static inline void init_MUTEX (struct semaphore *sem) 60static inline void init_MUTEX(struct semaphore *sem)
61{ 61{
62 sema_init(sem, 1); 62 sema_init(sem, 1);
63} 63}
64 64
65static inline void init_MUTEX_LOCKED (struct semaphore *sem) 65static inline void init_MUTEX_LOCKED(struct semaphore *sem)
66{ 66{
67 sema_init(sem, 0); 67 sema_init(sem, 0);
68} 68}
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
index 439bce7daa3a..721327f88601 100644
--- a/include/asm-mips/sgiarcs.h
+++ b/include/asm-mips/sgiarcs.h
@@ -13,7 +13,7 @@
13#define _ASM_SGIARCS_H 13#define _ASM_SGIARCS_H
14 14
15#include <asm/types.h> 15#include <asm/types.h>
16#include <asm/arc/types.h> 16#include <asm/fw/arc/types.h>
17 17
18/* Various ARCS error codes. */ 18/* Various ARCS error codes. */
19#define PROM_ESUCCESS 0x00 19#define PROM_ESUCCESS 0x00
@@ -369,8 +369,8 @@ struct linux_smonblock {
369#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) 369#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
370 370
371#define __arc_clobbers \ 371#define __arc_clobbers \
372 "$2","$3" /* ... */, "$8","$9","$10","$11", \ 372 "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \
373 "$12","$13","$14","$15","$16","$24","$25","$31" 373 "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31"
374 374
375#define ARC_CALL0(dest) \ 375#define ARC_CALL0(dest) \
376({ long __res; \ 376({ long __res; \
@@ -382,11 +382,11 @@ struct linux_smonblock {
382 "move\t%0, $2" \ 382 "move\t%0, $2" \
383 : "=r" (__res), "=r" (__vec) \ 383 : "=r" (__res), "=r" (__vec) \
384 : "1" (__vec) \ 384 : "1" (__vec) \
385 : __arc_clobbers, "$4","$5","$6","$7"); \ 385 : __arc_clobbers, "$4", "$5", "$6", "$7"); \
386 (unsigned long) __res; \ 386 (unsigned long) __res; \
387}) 387})
388 388
389#define ARC_CALL1(dest,a1) \ 389#define ARC_CALL1(dest, a1) \
390({ long __res; \ 390({ long __res; \
391 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 391 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
392 long __vec = (long) romvec->dest; \ 392 long __vec = (long) romvec->dest; \
@@ -397,11 +397,11 @@ struct linux_smonblock {
397 "move\t%0, $2" \ 397 "move\t%0, $2" \
398 : "=r" (__res), "=r" (__vec) \ 398 : "=r" (__res), "=r" (__vec) \
399 : "1" (__vec), "r" (__a1) \ 399 : "1" (__vec), "r" (__a1) \
400 : __arc_clobbers, "$5","$6","$7"); \ 400 : __arc_clobbers, "$5", "$6", "$7"); \
401 (unsigned long) __res; \ 401 (unsigned long) __res; \
402}) 402})
403 403
404#define ARC_CALL2(dest,a1,a2) \ 404#define ARC_CALL2(dest, a1, a2) \
405({ long __res; \ 405({ long __res; \
406 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 406 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
407 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 407 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -413,11 +413,11 @@ struct linux_smonblock {
413 "move\t%0, $2" \ 413 "move\t%0, $2" \
414 : "=r" (__res), "=r" (__vec) \ 414 : "=r" (__res), "=r" (__vec) \
415 : "1" (__vec), "r" (__a1), "r" (__a2) \ 415 : "1" (__vec), "r" (__a1), "r" (__a2) \
416 : __arc_clobbers, "$6","$7"); \ 416 : __arc_clobbers, "$6", "$7"); \
417 __res; \ 417 __res; \
418}) 418})
419 419
420#define ARC_CALL3(dest,a1,a2,a3) \ 420#define ARC_CALL3(dest, a1, a2, a3) \
421({ long __res; \ 421({ long __res; \
422 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 422 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
423 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 423 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -434,7 +434,7 @@ struct linux_smonblock {
434 __res; \ 434 __res; \
435}) 435})
436 436
437#define ARC_CALL4(dest,a1,a2,a3,a4) \ 437#define ARC_CALL4(dest, a1, a2, a3, a4) \
438({ long __res; \ 438({ long __res; \
439 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 439 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
440 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 440 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -453,7 +453,7 @@ struct linux_smonblock {
453 __res; \ 453 __res; \
454}) 454})
455 455
456#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ 456#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \
457({ long __res; \ 457({ long __res; \
458 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 458 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
459 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 459 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -468,8 +468,8 @@ struct linux_smonblock {
468 "daddu\t$29, 32\n\t" \ 468 "daddu\t$29, 32\n\t" \
469 "move\t%0, $2" \ 469 "move\t%0, $2" \
470 : "=r" (__res), "=r" (__vec) \ 470 : "=r" (__res), "=r" (__vec) \
471 : "1" (__vec), \ 471 : "1" (__vec), \
472 "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ 472 "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \
473 "r" (__a5) \ 473 "r" (__a5) \
474 : __arc_clobbers); \ 474 : __arc_clobbers); \
475 __res; \ 475 __res; \
@@ -488,7 +488,7 @@ struct linux_smonblock {
488 __res; \ 488 __res; \
489}) 489})
490 490
491#define ARC_CALL1(dest,a1) \ 491#define ARC_CALL1(dest, a1) \
492({ long __res; \ 492({ long __res; \
493 long __a1 = (long) (a1); \ 493 long __a1 = (long) (a1); \
494 long (*__vec)(long) = (void *) romvec->dest; \ 494 long (*__vec)(long) = (void *) romvec->dest; \
@@ -497,7 +497,7 @@ struct linux_smonblock {
497 __res; \ 497 __res; \
498}) 498})
499 499
500#define ARC_CALL2(dest,a1,a2) \ 500#define ARC_CALL2(dest, a1, a2) \
501({ long __res; \ 501({ long __res; \
502 long __a1 = (long) (a1); \ 502 long __a1 = (long) (a1); \
503 long __a2 = (long) (a2); \ 503 long __a2 = (long) (a2); \
@@ -507,7 +507,7 @@ struct linux_smonblock {
507 __res; \ 507 __res; \
508}) 508})
509 509
510#define ARC_CALL3(dest,a1,a2,a3) \ 510#define ARC_CALL3(dest, a1, a2, a3) \
511({ long __res; \ 511({ long __res; \
512 long __a1 = (long) (a1); \ 512 long __a1 = (long) (a1); \
513 long __a2 = (long) (a2); \ 513 long __a2 = (long) (a2); \
@@ -518,7 +518,7 @@ struct linux_smonblock {
518 __res; \ 518 __res; \
519}) 519})
520 520
521#define ARC_CALL4(dest,a1,a2,a3,a4) \ 521#define ARC_CALL4(dest, a1, a2, a3, a4) \
522({ long __res; \ 522({ long __res; \
523 long __a1 = (long) (a1); \ 523 long __a1 = (long) (a1); \
524 long __a2 = (long) (a2); \ 524 long __a2 = (long) (a2); \
@@ -530,7 +530,7 @@ struct linux_smonblock {
530 __res; \ 530 __res; \
531}) 531})
532 532
533#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ 533#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \
534({ long __res; \ 534({ long __res; \
535 long __a1 = (long) (a1); \ 535 long __a1 = (long) (a1); \
536 long __a2 = (long) (a2); \ 536 long __a2 = (long) (a2); \
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
index c0d5206020fd..6109557c14e9 100644
--- a/include/asm-mips/sibyte/bcm1480_int.h
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -157,7 +157,7 @@
157 * Mask values for each interrupt 157 * Mask values for each interrupt
158 */ 158 */
159 159
160#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F)) 160#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F))
161#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) 161#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
162#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) 162#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
163 163
@@ -196,7 +196,7 @@
196#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) 196#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
197#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) 197#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
198#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) 198#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
199#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0) 199#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
200#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) 200#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
201#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) 201#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
202#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) 202#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
@@ -269,9 +269,9 @@
269 */ 269 */
270 270
271#define S_BCM1480_INT_HT_INTMSG 0 271#define S_BCM1480_INT_HT_INTMSG 0
272#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) 272#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
273#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) 273#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
274#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) 274#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
275 275
276#define K_BCM1480_INT_HT_INTMSG_FIXED 0 276#define K_BCM1480_INT_HT_INTMSG_FIXED 0
277#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 277#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
@@ -291,14 +291,14 @@
291#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE 291#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
292 292
293#define S_BCM1480_INT_HT_INTDEST 5 293#define S_BCM1480_INT_HT_INTDEST 5
294#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) 294#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
295#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) 295#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
296#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) 296#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
297 297
298#define S_BCM1480_INT_HT_VECTOR 13 298#define S_BCM1480_INT_HT_VECTOR 13
299#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) 299#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
300#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) 300#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
301#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) 301#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
302 302
303/* 303/*
304 * Vector prefix (Table 4-7) 304 * Vector prefix (Table 4-7)
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h
index 886b099565e6..fd75817f7ac4 100644
--- a/include/asm-mips/sibyte/bcm1480_l2c.h
+++ b/include/asm-mips/sibyte/bcm1480_l2c.h
@@ -40,22 +40,22 @@
40 */ 40 */
41 41
42#define S_BCM1480_L2C_MGMT_INDEX 5 42#define S_BCM1480_L2C_MGMT_INDEX 5
43#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) 43#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
44#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) 44#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
45#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) 45#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
46 46
47#define S_BCM1480_L2C_MGMT_WAY 17 47#define S_BCM1480_L2C_MGMT_WAY 17
48#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) 48#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
49#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) 49#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
50#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) 50#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
51 51
52#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) 52#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20)
53#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) 53#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21)
54 54
55#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 55#define S_BCM1480_L2C_MGMT_ECC_DIAG 22
56#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) 56#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
57#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) 57#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
58#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) 58#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
59 59
60#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 60#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000
61 61
@@ -68,36 +68,36 @@
68 */ 68 */
69 69
70#define S_BCM1480_L2C_TAG_MBZ 0 70#define S_BCM1480_L2C_TAG_MBZ 0
71#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) 71#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
72 72
73#define S_BCM1480_L2C_TAG_INDEX 5 73#define S_BCM1480_L2C_TAG_INDEX 5
74#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) 74#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
75#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) 75#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
76#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) 76#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
77 77
78/* Note that index bit 16 is also tag bit 40 */ 78/* Note that index bit 16 is also tag bit 40 */
79#define S_BCM1480_L2C_TAG_TAG 17 79#define S_BCM1480_L2C_TAG_TAG 17
80#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) 80#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
81#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) 81#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
82#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) 82#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
83 83
84#define S_BCM1480_L2C_TAG_ECC 40 84#define S_BCM1480_L2C_TAG_ECC 40
85#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) 85#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
86#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) 86#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
87#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) 87#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
88 88
89#define S_BCM1480_L2C_TAG_WAY 46 89#define S_BCM1480_L2C_TAG_WAY 46
90#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) 90#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
91#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) 91#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
92#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) 92#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
93 93
94#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) 94#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49)
95#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) 95#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50)
96 96
97#define S_BCM1480_L2C_DATA_ECC 51 97#define S_BCM1480_L2C_DATA_ECC 51
98#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) 98#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
99#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) 99#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
100#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) 100#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
101 101
102 102
103/* 103/*
@@ -105,24 +105,24 @@
105 */ 105 */
106 106
107#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 107#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0
108#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) 108#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
109#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) 109#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
110 110
111#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 111#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8
112#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) 112#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
113#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) 113#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
114 114
115#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 115#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16
116#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) 116#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
117#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) 117#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
118 118
119#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 119#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24
120#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) 120#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
121#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) 121#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
122 122
123#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 123#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26
124#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) 124#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
125#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) 125#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
126 126
127#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 127#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30
128#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) 128#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
@@ -136,24 +136,24 @@
136 */ 136 */
137 137
138#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 138#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0
139#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) 139#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
140#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) 140#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
141 141
142#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 142#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8
143#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) 143#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
144#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) 144#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
145 145
146#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 146#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16
147#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) 147#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
148#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) 148#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
149 149
150#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 150#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24
151#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) 151#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
152#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) 152#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
153 153
154#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 154#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32
155#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) 155#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
156#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) 156#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
157 157
158 158
159/* 159/*
@@ -161,16 +161,16 @@
161 */ 161 */
162 162
163#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 163#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0
164#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) 164#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
165#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) 165#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
166 166
167#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 167#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8
168#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) 168#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
169#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) 169#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
170 170
171#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 171#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16
172#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) 172#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
173#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) 173#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
174 174
175 175
176#endif /* _BCM1480_L2C_H */ 176#endif /* _BCM1480_L2C_H */
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
index a6a437451da4..f26a41a82b59 100644
--- a/include/asm-mips/sibyte/bcm1480_mc.h
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -40,27 +40,27 @@
40 */ 40 */
41 41
42#define S_BCM1480_MC_INTLV0 0 42#define S_BCM1480_MC_INTLV0 0
43#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 43#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
44#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 44#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
45#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 45#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
46#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) 46#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0)
47 47
48#define S_BCM1480_MC_INTLV1 8 48#define S_BCM1480_MC_INTLV1 8
49#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 49#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
50#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 50#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
51#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 51#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
52#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) 52#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0)
53 53
54#define S_BCM1480_MC_INTLV2 16 54#define S_BCM1480_MC_INTLV2 16
55#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) 55#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
56#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) 56#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
57#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) 57#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
58#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) 58#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0)
59 59
60#define S_BCM1480_MC_CS_MODE 32 60#define S_BCM1480_MC_CS_MODE 32
61#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) 61#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
62#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) 62#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
63#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) 63#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
64#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) 64#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0)
65 65
66#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ 66#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \
@@ -81,131 +81,131 @@
81 */ 81 */
82 82
83#define S_BCM1480_MC_CS0_START 0 83#define S_BCM1480_MC_CS0_START 0
84#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) 84#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
85#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) 85#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
86#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) 86#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
87 87
88#define S_BCM1480_MC_CS1_START 16 88#define S_BCM1480_MC_CS1_START 16
89#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) 89#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
90#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) 90#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
91#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) 91#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
92 92
93#define S_BCM1480_MC_CS2_START 32 93#define S_BCM1480_MC_CS2_START 32
94#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) 94#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
95#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) 95#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
96#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) 96#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
97 97
98#define S_BCM1480_MC_CS3_START 48 98#define S_BCM1480_MC_CS3_START 48
99#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) 99#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
100#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) 100#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
101#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) 101#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
102 102
103/* 103/*
104 * Chip Select End Address Register (Table 83) 104 * Chip Select End Address Register (Table 83)
105 */ 105 */
106 106
107#define S_BCM1480_MC_CS0_END 0 107#define S_BCM1480_MC_CS0_END 0
108#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) 108#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
109#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) 109#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
110#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) 110#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
111 111
112#define S_BCM1480_MC_CS1_END 16 112#define S_BCM1480_MC_CS1_END 16
113#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) 113#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
114#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) 114#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
115#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) 115#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
116 116
117#define S_BCM1480_MC_CS2_END 32 117#define S_BCM1480_MC_CS2_END 32
118#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) 118#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
119#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) 119#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
120#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) 120#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
121 121
122#define S_BCM1480_MC_CS3_END 48 122#define S_BCM1480_MC_CS3_END 48
123#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) 123#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
124#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) 124#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
125#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) 125#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
126 126
127/* 127/*
128 * Row Address Bit Select Register 0 (Table 84) 128 * Row Address Bit Select Register 0 (Table 84)
129 */ 129 */
130 130
131#define S_BCM1480_MC_ROW00 0 131#define S_BCM1480_MC_ROW00 0
132#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) 132#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
133#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) 133#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
134#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) 134#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
135 135
136#define S_BCM1480_MC_ROW01 8 136#define S_BCM1480_MC_ROW01 8
137#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) 137#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
138#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) 138#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
139#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) 139#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
140 140
141#define S_BCM1480_MC_ROW02 16 141#define S_BCM1480_MC_ROW02 16
142#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) 142#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
143#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) 143#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
144#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) 144#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
145 145
146#define S_BCM1480_MC_ROW03 24 146#define S_BCM1480_MC_ROW03 24
147#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) 147#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
148#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) 148#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
149#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) 149#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
150 150
151#define S_BCM1480_MC_ROW04 32 151#define S_BCM1480_MC_ROW04 32
152#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) 152#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
153#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) 153#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
154#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) 154#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
155 155
156#define S_BCM1480_MC_ROW05 40 156#define S_BCM1480_MC_ROW05 40
157#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) 157#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
158#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) 158#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
159#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) 159#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
160 160
161#define S_BCM1480_MC_ROW06 48 161#define S_BCM1480_MC_ROW06 48
162#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) 162#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
163#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) 163#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
164#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) 164#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
165 165
166#define S_BCM1480_MC_ROW07 56 166#define S_BCM1480_MC_ROW07 56
167#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) 167#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
168#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) 168#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
169#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) 169#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
170 170
171/* 171/*
172 * Row Address Bit Select Register 1 (Table 85) 172 * Row Address Bit Select Register 1 (Table 85)
173 */ 173 */
174 174
175#define S_BCM1480_MC_ROW08 0 175#define S_BCM1480_MC_ROW08 0
176#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) 176#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
177#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) 177#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
178#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) 178#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
179 179
180#define S_BCM1480_MC_ROW09 8 180#define S_BCM1480_MC_ROW09 8
181#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) 181#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
182#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) 182#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
183#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) 183#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
184 184
185#define S_BCM1480_MC_ROW10 16 185#define S_BCM1480_MC_ROW10 16
186#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) 186#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
187#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) 187#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
188#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) 188#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
189 189
190#define S_BCM1480_MC_ROW11 24 190#define S_BCM1480_MC_ROW11 24
191#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) 191#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
192#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) 192#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
193#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) 193#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
194 194
195#define S_BCM1480_MC_ROW12 32 195#define S_BCM1480_MC_ROW12 32
196#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) 196#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
197#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) 197#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
198#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) 198#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
199 199
200#define S_BCM1480_MC_ROW13 40 200#define S_BCM1480_MC_ROW13 40
201#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) 201#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
202#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) 202#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
203#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) 203#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
204 204
205#define S_BCM1480_MC_ROW14 48 205#define S_BCM1480_MC_ROW14 48
206#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) 206#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
207#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) 207#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
208#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) 208#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
209 209
210#define K_BCM1480_MC_ROWX_BIT_SPACING 8 210#define K_BCM1480_MC_ROWX_BIT_SPACING 8
211 211
@@ -214,80 +214,80 @@
214 */ 214 */
215 215
216#define S_BCM1480_MC_COL00 0 216#define S_BCM1480_MC_COL00 0
217#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) 217#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
218#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) 218#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
219#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) 219#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
220 220
221#define S_BCM1480_MC_COL01 8 221#define S_BCM1480_MC_COL01 8
222#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) 222#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
223#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) 223#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
224#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) 224#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
225 225
226#define S_BCM1480_MC_COL02 16 226#define S_BCM1480_MC_COL02 16
227#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) 227#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
228#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) 228#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
229#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) 229#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
230 230
231#define S_BCM1480_MC_COL03 24 231#define S_BCM1480_MC_COL03 24
232#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) 232#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
233#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) 233#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
234#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) 234#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
235 235
236#define S_BCM1480_MC_COL04 32 236#define S_BCM1480_MC_COL04 32
237#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) 237#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
238#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) 238#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
239#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) 239#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
240 240
241#define S_BCM1480_MC_COL05 40 241#define S_BCM1480_MC_COL05 40
242#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) 242#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
243#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) 243#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
244#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) 244#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
245 245
246#define S_BCM1480_MC_COL06 48 246#define S_BCM1480_MC_COL06 48
247#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) 247#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
248#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) 248#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
249#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) 249#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
250 250
251#define S_BCM1480_MC_COL07 56 251#define S_BCM1480_MC_COL07 56
252#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) 252#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
253#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) 253#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
254#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) 254#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
255 255
256/* 256/*
257 * Column Address Bit Select Register 1 (Table 87) 257 * Column Address Bit Select Register 1 (Table 87)
258 */ 258 */
259 259
260#define S_BCM1480_MC_COL08 0 260#define S_BCM1480_MC_COL08 0
261#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) 261#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
262#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) 262#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
263#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) 263#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
264 264
265#define S_BCM1480_MC_COL09 8 265#define S_BCM1480_MC_COL09 8
266#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) 266#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
267#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) 267#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
268#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) 268#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
269 269
270#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ 270#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */
271 271
272#define S_BCM1480_MC_COL11 24 272#define S_BCM1480_MC_COL11 24
273#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) 273#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
274#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) 274#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
275#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) 275#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
276 276
277#define S_BCM1480_MC_COL12 32 277#define S_BCM1480_MC_COL12 32
278#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) 278#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
279#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) 279#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
280#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) 280#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
281 281
282#define S_BCM1480_MC_COL13 40 282#define S_BCM1480_MC_COL13 40
283#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) 283#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
284#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) 284#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
285#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) 285#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
286 286
287#define S_BCM1480_MC_COL14 48 287#define S_BCM1480_MC_COL14 48
288#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) 288#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
289#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) 289#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
290#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) 290#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
291 291
292#define K_BCM1480_MC_COLX_BIT_SPACING 8 292#define K_BCM1480_MC_COLX_BIT_SPACING 8
293 293
@@ -296,38 +296,38 @@
296 */ 296 */
297 297
298#define S_BCM1480_MC_CS01_BANK0 0 298#define S_BCM1480_MC_CS01_BANK0 0
299#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) 299#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
300#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) 300#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
301#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) 301#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
302 302
303#define S_BCM1480_MC_CS01_BANK1 8 303#define S_BCM1480_MC_CS01_BANK1 8
304#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) 304#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
305#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) 305#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
306#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) 306#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
307 307
308#define S_BCM1480_MC_CS01_BANK2 16 308#define S_BCM1480_MC_CS01_BANK2 16
309#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) 309#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
310#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) 310#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
311#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) 311#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
312 312
313/* 313/*
314 * CS2 and CS3 Bank Address Bit Select Register (Table 89) 314 * CS2 and CS3 Bank Address Bit Select Register (Table 89)
315 */ 315 */
316 316
317#define S_BCM1480_MC_CS23_BANK0 0 317#define S_BCM1480_MC_CS23_BANK0 0
318#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) 318#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
319#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) 319#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
320#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) 320#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
321 321
322#define S_BCM1480_MC_CS23_BANK1 8 322#define S_BCM1480_MC_CS23_BANK1 8
323#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) 323#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
324#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) 324#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
325#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) 325#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
326 326
327#define S_BCM1480_MC_CS23_BANK2 16 327#define S_BCM1480_MC_CS23_BANK2 16
328#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) 328#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
329#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) 329#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
330#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) 330#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
331 331
332#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 332#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8
333 333
@@ -336,9 +336,9 @@
336 */ 336 */
337 337
338#define S_BCM1480_MC_COMMAND 0 338#define S_BCM1480_MC_COMMAND 0
339#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) 339#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
340#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) 340#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
341#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) 341#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
342 342
343#define K_BCM1480_MC_COMMAND_EMRS 0 343#define K_BCM1480_MC_COMMAND_EMRS 0
344#define K_BCM1480_MC_COMMAND_MRS 1 344#define K_BCM1480_MC_COMMAND_MRS 1
@@ -382,9 +382,9 @@
382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) 382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) 383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
384 384
385#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) 385#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) 386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) 387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
388 388
389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) 389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
390 390
@@ -393,21 +393,21 @@
393 */ 393 */
394 394
395#define S_BCM1480_MC_EMODE 0 395#define S_BCM1480_MC_EMODE 0
396#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) 396#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
397#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) 397#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
398#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) 398#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
399#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) 399#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0)
400 400
401#define S_BCM1480_MC_MODE 16 401#define S_BCM1480_MC_MODE 16
402#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) 402#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
403#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) 403#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
404#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) 404#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
405#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) 405#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0)
406 406
407#define S_BCM1480_MC_DRAM_TYPE 32 407#define S_BCM1480_MC_DRAM_TYPE 32
408#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) 408#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
409#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) 409#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
410#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) 410#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
411 411
412#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 412#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0
413#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 413#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1
@@ -431,9 +431,9 @@
431#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) 431#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39)
432 432
433#define S_BCM1480_MC_PG_POLICY 40 433#define S_BCM1480_MC_PG_POLICY 40
434#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) 434#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
435#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) 435#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
436#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) 436#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
437 437
438#define K_BCM1480_MC_PG_POLICY_CLOSED 0 438#define K_BCM1480_MC_PG_POLICY_CLOSED 0
439#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 439#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
@@ -454,16 +454,16 @@
454 */ 454 */
455 455
456#define S_BCM1480_MC_CLK_RATIO 0 456#define S_BCM1480_MC_CLK_RATIO 0
457#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) 457#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
458#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) 458#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
459#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) 459#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
460 460
461#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) 461#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10)
462 462
463#define S_BCM1480_MC_REF_RATE 8 463#define S_BCM1480_MC_REF_RATE 8
464#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) 464#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
465#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) 465#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
466#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) 466#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
467 467
468#define K_BCM1480_MC_REF_RATE_100MHz 0x31 468#define K_BCM1480_MC_REF_RATE_100MHz 0x31
469#define K_BCM1480_MC_REF_RATE_200MHz 0x62 469#define K_BCM1480_MC_REF_RATE_200MHz 0x62
@@ -519,20 +519,20 @@
519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) 519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
520 520
521#define S_BCM1480_MC_ODT0 0 521#define S_BCM1480_MC_ODT0 0
522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) 522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) 523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
524 524
525#define S_BCM1480_MC_ODT2 8 525#define S_BCM1480_MC_ODT2 8
526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) 526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) 527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
528 528
529#define S_BCM1480_MC_ODT4 16 529#define S_BCM1480_MC_ODT4 16
530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) 530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) 531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
532 532
533#define S_BCM1480_MC_ODT6 24 533#define S_BCM1480_MC_ODT6 24
534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) 534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) 535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
536#endif 536#endif
537 537
538/* 538/*
@@ -540,70 +540,70 @@
540 */ 540 */
541 541
542#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 542#define S_BCM1480_MC_ADDR_COARSE_ADJ 0
543#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) 543#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
544#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) 544#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
545#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) 545#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
546#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) 546#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
547 547
548#if SIBYTE_HDR_FEATURE(1480, PASS2) 548#if SIBYTE_HDR_FEATURE(1480, PASS2)
549#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 549#define S_BCM1480_MC_ADDR_FREQ_RANGE 8
550#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) 550#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
551#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) 551#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
552#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) 552#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
553#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) 553#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
554#endif 554#endif
555 555
556#define S_BCM1480_MC_ADDR_FINE_ADJ 8 556#define S_BCM1480_MC_ADDR_FINE_ADJ 8
557#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) 557#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
558#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) 558#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
559#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) 559#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
560#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) 560#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
561 561
562#define S_BCM1480_MC_DQI_COARSE_ADJ 16 562#define S_BCM1480_MC_DQI_COARSE_ADJ 16
563#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) 563#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
564#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) 564#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
565#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) 565#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
566#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) 566#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
567 567
568#if SIBYTE_HDR_FEATURE(1480, PASS2) 568#if SIBYTE_HDR_FEATURE(1480, PASS2)
569#define S_BCM1480_MC_DQI_FREQ_RANGE 24 569#define S_BCM1480_MC_DQI_FREQ_RANGE 24
570#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) 570#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
571#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) 571#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
572#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) 572#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
573#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) 573#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
574#endif 574#endif
575 575
576#define S_BCM1480_MC_DQI_FINE_ADJ 24 576#define S_BCM1480_MC_DQI_FINE_ADJ 24
577#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) 577#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
578#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) 578#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
579#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) 579#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
580#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) 580#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8)
581 581
582#define S_BCM1480_MC_DQO_COARSE_ADJ 32 582#define S_BCM1480_MC_DQO_COARSE_ADJ 32
583#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) 583#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
584#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) 584#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
585#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) 585#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
586#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) 586#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
587 587
588#if SIBYTE_HDR_FEATURE(1480, PASS2) 588#if SIBYTE_HDR_FEATURE(1480, PASS2)
589#define S_BCM1480_MC_DQO_FREQ_RANGE 40 589#define S_BCM1480_MC_DQO_FREQ_RANGE 40
590#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) 590#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
591#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) 591#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
592#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) 592#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
593#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) 593#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
594#endif 594#endif
595 595
596#define S_BCM1480_MC_DQO_FINE_ADJ 40 596#define S_BCM1480_MC_DQO_FINE_ADJ 40
597#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) 597#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
598#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) 598#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
599#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) 599#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
600#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) 600#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8)
601 601
602#if SIBYTE_HDR_FEATURE(1480, PASS2) 602#if SIBYTE_HDR_FEATURE(1480, PASS2)
603#define S_BCM1480_MC_DLL_PDSEL 44 603#define S_BCM1480_MC_DLL_PDSEL 44
604#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) 604#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
605#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) 605#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
606#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) 606#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
607#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) 607#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0)
608 608
609#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) 609#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46)
@@ -611,38 +611,38 @@
611#endif 611#endif
612 612
613#define S_BCM1480_MC_DLL_DEFAULT 48 613#define S_BCM1480_MC_DLL_DEFAULT 48
614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) 614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) 615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) 616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) 617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
618 618
619#if SIBYTE_HDR_FEATURE(1480, PASS2) 619#if SIBYTE_HDR_FEATURE(1480, PASS2)
620#define S_BCM1480_MC_DLL_REGCTRL 54 620#define S_BCM1480_MC_DLL_REGCTRL 54
621#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) 621#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
622#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) 622#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
623#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) 623#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
624#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) 624#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0)
625#endif 625#endif
626 626
627#if SIBYTE_HDR_FEATURE(1480, PASS2) 627#if SIBYTE_HDR_FEATURE(1480, PASS2)
628#define S_BCM1480_MC_DLL_FREQ_RANGE 56 628#define S_BCM1480_MC_DLL_FREQ_RANGE 56
629#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) 629#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
630#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) 630#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
631#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) 631#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
632#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) 632#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
633#endif 633#endif
634 634
635#define S_BCM1480_MC_DLL_STEP_SIZE 56 635#define S_BCM1480_MC_DLL_STEP_SIZE 56
636#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) 636#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
637#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) 637#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
638#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) 638#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
639#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) 639#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8)
640 640
641#if SIBYTE_HDR_FEATURE(1480, PASS2) 641#if SIBYTE_HDR_FEATURE(1480, PASS2)
642#define S_BCM1480_MC_DLL_BGCTRL 60 642#define S_BCM1480_MC_DLL_BGCTRL 60
643#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) 643#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
644#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) 644#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
645#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) 645#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
646#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) 646#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0)
647#endif 647#endif
648 648
@@ -653,37 +653,37 @@
653 */ 653 */
654 654
655#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 655#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0
656#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) 656#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
657#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) 657#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
658#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) 658#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
659 659
660#define S_BCM1480_MC_RTT_BYP_PULLUP 6 660#define S_BCM1480_MC_RTT_BYP_PULLUP 6
661#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) 661#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
662#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) 662#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
663#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) 663#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
664 664
665#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) 665#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8)
666#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) 666#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9)
667 667
668#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 668#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10
669#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 669#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
670#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 670#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
671#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 671#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
672 672
673#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 673#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15
674#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 674#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
675#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 675#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
676#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) 676#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
677 677
678#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 678#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20
679#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 679#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
680#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 680#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
681#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 681#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
682 682
683#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 683#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25
684#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 684#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
685#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 685#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
686#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) 686#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
687 687
688#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) 688#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30)
689#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) 689#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31)
@@ -703,111 +703,111 @@
703 */ 703 */
704 704
705#define S_BCM1480_MC_DATA_INVERT 0 705#define S_BCM1480_MC_DATA_INVERT 0
706#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) 706#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
707 707
708/* 708/*
709 * ECC Test ECC Register (Table 96) 709 * ECC Test ECC Register (Table 96)
710 */ 710 */
711 711
712#define S_BCM1480_MC_ECC_INVERT 0 712#define S_BCM1480_MC_ECC_INVERT 0
713#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) 713#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
714 714
715/* 715/*
716 * SDRAM Timing Register (Table 97) 716 * SDRAM Timing Register (Table 97)
717 */ 717 */
718 718
719#define S_BCM1480_MC_tRCD 0 719#define S_BCM1480_MC_tRCD 0
720#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) 720#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
721#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) 721#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
722#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) 722#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
723#define K_BCM1480_MC_tRCD_DEFAULT 3 723#define K_BCM1480_MC_tRCD_DEFAULT 3
724#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) 724#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
725 725
726#define S_BCM1480_MC_tCL 4 726#define S_BCM1480_MC_tCL 4
727#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) 727#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
728#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) 728#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
729#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) 729#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
730#define K_BCM1480_MC_tCL_DEFAULT 2 730#define K_BCM1480_MC_tCL_DEFAULT 2
731#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) 731#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
732 732
733#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) 733#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8)
734 734
735#define S_BCM1480_MC_tWR 9 735#define S_BCM1480_MC_tWR 9
736#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) 736#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
737#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) 737#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
738#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) 738#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
739#define K_BCM1480_MC_tWR_DEFAULT 2 739#define K_BCM1480_MC_tWR_DEFAULT 2
740#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) 740#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
741 741
742#define S_BCM1480_MC_tCwD 12 742#define S_BCM1480_MC_tCwD 12
743#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) 743#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
744#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) 744#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
745#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) 745#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
746#define K_BCM1480_MC_tCwD_DEFAULT 1 746#define K_BCM1480_MC_tCwD_DEFAULT 1
747#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) 747#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
748 748
749#define S_BCM1480_MC_tRP 16 749#define S_BCM1480_MC_tRP 16
750#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) 750#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
751#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) 751#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
752#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) 752#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
753#define K_BCM1480_MC_tRP_DEFAULT 4 753#define K_BCM1480_MC_tRP_DEFAULT 4
754#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) 754#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
755 755
756#define S_BCM1480_MC_tRRD 20 756#define S_BCM1480_MC_tRRD 20
757#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) 757#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
758#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) 758#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
759#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) 759#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
760#define K_BCM1480_MC_tRRD_DEFAULT 2 760#define K_BCM1480_MC_tRRD_DEFAULT 2
761#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) 761#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
762 762
763#define S_BCM1480_MC_tRCw 24 763#define S_BCM1480_MC_tRCw 24
764#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) 764#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
765#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) 765#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
766#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) 766#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
767#define K_BCM1480_MC_tRCw_DEFAULT 10 767#define K_BCM1480_MC_tRCw_DEFAULT 10
768#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) 768#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
769 769
770#define S_BCM1480_MC_tRCr 32 770#define S_BCM1480_MC_tRCr 32
771#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) 771#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
772#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) 772#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
773#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) 773#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
774#define K_BCM1480_MC_tRCr_DEFAULT 9 774#define K_BCM1480_MC_tRCr_DEFAULT 9
775#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) 775#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
776 776
777#if SIBYTE_HDR_FEATURE(1480, PASS2) 777#if SIBYTE_HDR_FEATURE(1480, PASS2)
778#define S_BCM1480_MC_tFAW 40 778#define S_BCM1480_MC_tFAW 40
779#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) 779#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
780#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) 780#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
781#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) 781#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
782#define K_BCM1480_MC_tFAW_DEFAULT 0 782#define K_BCM1480_MC_tFAW_DEFAULT 0
783#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) 783#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
784#endif 784#endif
785 785
786#define S_BCM1480_MC_tRFC 48 786#define S_BCM1480_MC_tRFC 48
787#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) 787#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
788#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) 788#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
789#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) 789#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
790#define K_BCM1480_MC_tRFC_DEFAULT 12 790#define K_BCM1480_MC_tRFC_DEFAULT 12
791#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) 791#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
792 792
793#define S_BCM1480_MC_tFIFO 56 793#define S_BCM1480_MC_tFIFO 56
794#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) 794#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
795#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) 795#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
796#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) 796#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
797#define K_BCM1480_MC_tFIFO_DEFAULT 0 797#define K_BCM1480_MC_tFIFO_DEFAULT 0
798#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) 798#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
799 799
800#define S_BCM1480_MC_tW2R 58 800#define S_BCM1480_MC_tW2R 58
801#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) 801#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
802#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) 802#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
803#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) 803#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
804#define K_BCM1480_MC_tW2R_DEFAULT 1 804#define K_BCM1480_MC_tW2R_DEFAULT 1
805#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) 805#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
806 806
807#define S_BCM1480_MC_tR2W 60 807#define S_BCM1480_MC_tR2W 60
808#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) 808#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
809#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) 809#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
810#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) 810#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
811#define K_BCM1480_MC_tR2W_DEFAULT 0 811#define K_BCM1480_MC_tR2W_DEFAULT 0
812#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) 812#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
813 813
@@ -835,30 +835,30 @@
835#if SIBYTE_HDR_FEATURE(1480, PASS2) 835#if SIBYTE_HDR_FEATURE(1480, PASS2)
836 836
837#define S_BCM1480_MC_tAL 0 837#define S_BCM1480_MC_tAL 0
838#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) 838#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
839#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) 839#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
840#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) 840#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
841#define K_BCM1480_MC_tAL_DEFAULT 0 841#define K_BCM1480_MC_tAL_DEFAULT 0
842#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) 842#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
843 843
844#define S_BCM1480_MC_tRTP 4 844#define S_BCM1480_MC_tRTP 4
845#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) 845#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
846#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) 846#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
847#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) 847#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
848#define K_BCM1480_MC_tRTP_DEFAULT 2 848#define K_BCM1480_MC_tRTP_DEFAULT 2
849#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) 849#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
850 850
851#define S_BCM1480_MC_tW2W 8 851#define S_BCM1480_MC_tW2W 8
852#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) 852#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
853#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) 853#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
854#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) 854#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
855#define K_BCM1480_MC_tW2W_DEFAULT 0 855#define K_BCM1480_MC_tW2W_DEFAULT 0
856#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) 856#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
857 857
858#define S_BCM1480_MC_tRAP 12 858#define S_BCM1480_MC_tRAP 12
859#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) 859#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
860#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) 860#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
861#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) 861#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
862#define K_BCM1480_MC_tRAP_DEFAULT 0 862#define K_BCM1480_MC_tRAP_DEFAULT 0
863#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) 863#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
864 864
@@ -875,30 +875,30 @@
875 */ 875 */
876 876
877#define S_BCM1480_MC_BLK_SET_MARK 8 877#define S_BCM1480_MC_BLK_SET_MARK 8
878#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) 878#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
879#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) 879#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
880#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) 880#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
881 881
882#define S_BCM1480_MC_BLK_CLR_MARK 12 882#define S_BCM1480_MC_BLK_CLR_MARK 12
883#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) 883#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
884#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) 884#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
885#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) 885#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
886 886
887#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) 887#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16)
888 888
889#define S_BCM1480_MC_MAX_AGE 20 889#define S_BCM1480_MC_MAX_AGE 20
890#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) 890#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
891#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) 891#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
892#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) 892#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
893 893
894#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) 894#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29)
895#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) 895#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30)
896#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) 896#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32)
897 897
898#define S_BCM1480_MC_SLEW 33 898#define S_BCM1480_MC_SLEW 33
899#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) 899#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
900#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) 900#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
901#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) 901#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
902 902
903#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) 903#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35)
904 904
@@ -907,19 +907,19 @@
907 */ 907 */
908 908
909#define S_BCM1480_MC_INTLV0 0 909#define S_BCM1480_MC_INTLV0 0
910#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 910#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
911#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 911#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
912#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 912#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
913 913
914#define S_BCM1480_MC_INTLV1 8 914#define S_BCM1480_MC_INTLV1 8
915#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 915#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
916#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 916#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
917#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 917#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
918 918
919#define S_BCM1480_MC_INTLV_MODE 16 919#define S_BCM1480_MC_INTLV_MODE 16
920#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) 920#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
921#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) 921#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
922#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) 922#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
923 923
924#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 924#define K_BCM1480_MC_INTLV_MODE_NONE 0x0
925#define K_BCM1480_MC_INTLV_MODE_01 0x1 925#define K_BCM1480_MC_INTLV_MODE_01 0x1
@@ -938,9 +938,9 @@
938 */ 938 */
939 939
940#define S_BCM1480_MC_ECC_ERR_ADDR 0 940#define S_BCM1480_MC_ECC_ERR_ADDR 0
941#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) 941#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
942#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) 942#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
943#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) 943#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
944 944
945#if SIBYTE_HDR_FEATURE(1480, PASS2) 945#if SIBYTE_HDR_FEATURE(1480, PASS2)
946#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) 946#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60)
@@ -955,27 +955,27 @@
955 */ 955 */
956 956
957#define S_BCM1480_MC_ECC_CORR_ADDR 0 957#define S_BCM1480_MC_ECC_CORR_ADDR 0
958#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) 958#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
959#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) 959#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
960#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) 960#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
961 961
962/* 962/*
963 * Global ECC Correction Register (Table 103) 963 * Global ECC Correction Register (Table 103)
964 */ 964 */
965 965
966#define S_BCM1480_MC_ECC_CORRECT 0 966#define S_BCM1480_MC_ECC_CORRECT 0
967#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) 967#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
968#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) 968#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
969#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) 969#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
970 970
971/* 971/*
972 * Global ECC Performance Counters Control Register (Table 104) 972 * Global ECC Performance Counters Control Register (Table 104)
973 */ 973 */
974 974
975#define S_BCM1480_MC_CHANNEL_SELECT 0 975#define S_BCM1480_MC_CHANNEL_SELECT 0
976#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) 976#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
977#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) 977#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
978#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) 978#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
979#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 979#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1
980#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 980#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2
981#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 981#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
index c34d36b6b8c2..b4077bb72611 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -87,7 +87,7 @@
87#define BCM1480_MC_REGISTER_SPACING 0x1000 87#define BCM1480_MC_REGISTER_SPACING 0x1000
88 88
89#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) 89#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
90#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) 90#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg))
91 91
92#define R_BCM1480_MC_CONFIG 0x0000000100 92#define R_BCM1480_MC_CONFIG 0x0000000100
93#define R_BCM1480_MC_CS_START 0x0000000120 93#define R_BCM1480_MC_CS_START 0x0000000120
@@ -327,7 +327,7 @@
327#define BCM1480_SCD_NUM_WDOGS 4 327#define BCM1480_SCD_NUM_WDOGS 4
328 328
329#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) 329#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
330#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) 330#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
331 331
332#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 332#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050
333#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 333#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058
@@ -372,7 +372,7 @@
372#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 372#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13
373 373
374#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) 374#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
375#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) 375#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
376 376
377/* Most IMR registers are 128 bits, implemented as non-contiguous 377/* Most IMR registers are 128 bits, implemented as non-contiguous
378 64-bit registers high (_H) and low (_L) */ 378 64-bit registers high (_H) and low (_L) */
@@ -413,7 +413,7 @@
413 413
414#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ 414#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
415 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) 415 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
416#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) 416#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
417 417
418#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ 418#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
419#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ 419#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
@@ -427,7 +427,7 @@
427#define R_BCM1480_IMR_MAILBOX_SET 0x08 427#define R_BCM1480_IMR_MAILBOX_SET 0x08
428#define R_BCM1480_IMR_MAILBOX_CLR 0x10 428#define R_BCM1480_IMR_MAILBOX_CLR 0x10
429#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 429#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
430#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ 430#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
431 (A_BCM1480_IMR_CPU0_BASE + \ 431 (A_BCM1480_IMR_CPU0_BASE + \
432 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ 432 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
433 (cpu * BCM1480_IMR_REGISTER_SPACING) + \ 433 (cpu * BCM1480_IMR_REGISTER_SPACING) + \
@@ -550,7 +550,7 @@
550#define BCM1480_HR_REGISTER_SPACING 0x80000 550#define BCM1480_HR_REGISTER_SPACING 0x80000
551 551
552#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) 552#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
553#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) 553#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg))
554 554
555#define R_BCM1480_HR_CFG 0x0000000000 555#define R_BCM1480_HR_CFG 0x0000000000
556 556
@@ -599,9 +599,9 @@
599#define BCM1480_PM_NUM_CHANNELS 32 599#define BCM1480_PM_NUM_CHANNELS 32
600 600
601#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 601#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
602#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) 602#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
603#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 603#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
604#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) 604#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
605 605
606#define BCM1480_PM_INT_PACKING 8 606#define BCM1480_PM_INT_PACKING 8
607#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 607#define BCM1480_PM_INT_FUNCTION_SPACING 0x40
@@ -721,7 +721,7 @@
721#define BCM1480_HSP_REGISTER_SPACING 0x80000 721#define BCM1480_HSP_REGISTER_SPACING 0x80000
722 722
723#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) 723#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
724#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) 724#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg))
725 725
726#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 726#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000
727#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 727#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
index 6111d6dcf117..25ef24cbb92a 100644
--- a/include/asm-mips/sibyte/bcm1480_scd.h
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -99,22 +99,22 @@
99#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) 99#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5)
100 100
101#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) 101#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6)
102#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) 102#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
103#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) 103#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
104#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) 104#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
105 105
106#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) 106#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11)
107#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) 107#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
108#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) 108#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
109#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) 109#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
110 110
111#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 111#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
112#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) 112#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17)
113 113
114#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) 114#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18)
115#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) 115#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
116#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) 116#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
117#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) 117#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
118#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 118#define K_BCM1480_SYS_BOOT_MODE_ROM32 0
119#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 119#define K_BCM1480_SYS_BOOT_MODE_ROM8 1
120#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 120#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
@@ -129,16 +129,16 @@
129#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) 129#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25)
130 130
131#define S_BCM1480_SYS_CONFIG 26 131#define S_BCM1480_SYS_CONFIG 26
132#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) 132#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
133#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) 133#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
134#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) 134#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
135 135
136#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) 136#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15)
137 137
138#define S_BCM1480_SYS_NODEID 47 138#define S_BCM1480_SYS_NODEID 47
139#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) 139#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
140#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) 140#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
141#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) 141#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
142 142
143#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) 143#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51)
144#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) 144#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52)
@@ -196,9 +196,9 @@
196#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 196#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
197 197
198#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 198#define S_BCM1480_SCD_WDOG_RESET_TYPE 2
199#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) 199#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
200#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) 200#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
201#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) 201#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
202 202
203#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 203#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
204#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 204#define K_BCM1480_SCD_WDOG_RESET_SOFT 1
@@ -244,24 +244,24 @@
244 */ 244 */
245 245
246#define S_SPC_CFG_SRC4 32 246#define S_SPC_CFG_SRC4 32
247#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) 247#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
248#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) 248#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
249#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) 249#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
250 250
251#define S_SPC_CFG_SRC5 40 251#define S_SPC_CFG_SRC5 40
252#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) 252#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
253#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) 253#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
254#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) 254#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
255 255
256#define S_SPC_CFG_SRC6 48 256#define S_SPC_CFG_SRC6 48
257#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) 257#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
258#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) 258#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
259#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) 259#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
260 260
261#define S_SPC_CFG_SRC7 56 261#define S_SPC_CFG_SRC7 56
262#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) 262#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
263#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) 263#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
264#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) 264#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
265 265
266/* 266/*
267 * System Performance Counter Control Register (Table 32) 267 * System Performance Counter Control Register (Table 32)
@@ -281,9 +281,9 @@
281 */ 281 */
282 282
283#define S_BCM1480_SPC_CNT_COUNT 0 283#define S_BCM1480_SPC_CNT_COUNT 0
284#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) 284#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
285#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) 285#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
286#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) 286#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
287 287
288#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) 288#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40)
289 289
@@ -322,13 +322,13 @@
322 * slightly different. 322 * slightly different.
323 */ 323 */
324 324
325#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) 325#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0)
326#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 326#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
327 327
328#define S_BCM1480_ATRAP_CFG_CNT 0 328#define S_BCM1480_ATRAP_CFG_CNT 0
329#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) 329#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
330#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) 330#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
331#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) 331#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
332 332
333#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 333#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
334#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 334#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
@@ -337,9 +337,9 @@
337#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 337#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
338 338
339#define S_BCM1480_ATRAP_CFG_AGENTID 8 339#define S_BCM1480_ATRAP_CFG_AGENTID 8
340#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) 340#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
341#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) 341#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
342#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) 342#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
343 343
344 344
345#define K_BCM1480_BUS_AGENT_CPU0 0 345#define K_BCM1480_BUS_AGENT_CPU0 0
@@ -354,9 +354,9 @@
354#define K_BCM1480_BUS_AGENT_PM 10 354#define K_BCM1480_BUS_AGENT_PM 10
355 355
356#define S_BCM1480_ATRAP_CFG_CATTR 12 356#define S_BCM1480_ATRAP_CFG_CATTR 12
357#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) 357#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
358#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) 358#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
359#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) 359#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
360 360
361#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 361#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0
362#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 362#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1
@@ -382,9 +382,9 @@
382#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) 382#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25)
383 383
384#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 384#define S_BCM1480_SCD_TRSEQ_SWFUNC 26
385#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) 385#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
386#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) 386#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
387#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) 387#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
388 388
389/* 389/*
390 * Trace Control Register (Table 49) 390 * Trace Control Register (Table 49)
@@ -395,9 +395,9 @@
395 */ 395 */
396 396
397#define S_BCM1480_SCD_TRACE_CFG_MODE 16 397#define S_BCM1480_SCD_TRACE_CFG_MODE 16
398#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) 398#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
399#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) 399#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
400#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) 400#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
401 401
402#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 402#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0
403#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 403#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index 73bce901a378..da198a1c8c81 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -41,7 +41,7 @@
41#ifdef __ASSEMBLY__ 41#ifdef __ASSEMBLY__
42 42
43#ifdef LEDS_PHYS 43#ifdef LEDS_PHYS
44#define setleds(t0,t1,c0,c1,c2,c3) \ 44#define setleds(t0, t1, c0, c1, c2, c3) \
45 li t0, (LEDS_PHYS|0xa0000000); \ 45 li t0, (LEDS_PHYS|0xa0000000); \
46 li t1, c0; \ 46 li t1, c0; \
47 sb t1, 0x18(t0); \ 47 sb t1, 0x18(t0); \
@@ -52,7 +52,7 @@
52 li t1, c3; \ 52 li t1, c3; \
53 sb t1, 0x00(t0) 53 sb t1, 0x00(t0)
54#else 54#else
55#define setleds(t0,t1,c0,c1,c2,c3) 55#define setleds(t0, t1, c0, c1, c2, c3)
56#endif /* LEDS_PHYS */ 56#endif /* LEDS_PHYS */
57 57
58#else 58#else
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index a885491217c1..09365f9111fa 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -232,18 +232,18 @@
232 * Make a mask for 'v' bits at position 'n' 232 * Make a mask for 'v' bits at position 'n'
233 */ 233 */
234 234
235#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) 235#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
236#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) 236#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
237 237
238/* 238/*
239 * Make a value at 'v' at bit position 'n' 239 * Make a value at 'v' at bit position 'n'
240 */ 240 */
241 241
242#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n)) 242#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
243#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n)) 243#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
244 244
245#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) 245#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
246#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) 246#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
247 247
248/* 248/*
249 * Macros to read/write on-chip registers 249 * Macros to read/write on-chip registers
@@ -252,7 +252,7 @@
252 252
253 253
254#if defined(__mips64) && !defined(__ASSEMBLY__) 254#if defined(__mips64) && !defined(__ASSEMBLY__)
255#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) 255#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
256#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) 256#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
257#endif /* __ASSEMBLY__ */ 257#endif /* __ASSEMBLY__ */
258 258
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index e6145f524fbd..bad56171d747 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -57,9 +57,9 @@
57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
58 58
59#define S_DMA_DESC_TYPE _SB_MAKE64(1) 59#define S_DMA_DESC_TYPE _SB_MAKE64(1)
60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) 60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
63 63
64#define K_DMA_DESC_TYPE_RING_AL 0 64#define K_DMA_DESC_TYPE_RING_AL 0
65#define K_DMA_DESC_TYPE_CHAIN_AL 1 65#define K_DMA_DESC_TYPE_CHAIN_AL 1
@@ -76,24 +76,24 @@
76#define M_DMA_TDX_EN _SB_MAKEMASK1(7) 76#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
77 77
78#define S_DMA_INT_PKTCNT _SB_MAKE64(8) 78#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
79#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) 79#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
80#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) 80#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
81#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) 81#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
82 82
83#define S_DMA_RINGSZ _SB_MAKE64(16) 83#define S_DMA_RINGSZ _SB_MAKE64(16)
84#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) 84#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ)
85#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) 85#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ)
86#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) 86#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
87 87
88#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) 88#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
89#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) 89#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
90#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) 90#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
91#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) 91#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
92 92
93#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) 93#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
94#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) 94#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
95#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) 95#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
96#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) 96#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
97 97
98/* 98/*
99 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) 99 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
@@ -116,37 +116,37 @@
116#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 116#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
117#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 117#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
118 118
119#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 119#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15)
120 120
121#define S_DMA_HDR_SIZE _SB_MAKE64(21) 121#define S_DMA_HDR_SIZE _SB_MAKE64(21)
122#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) 122#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
123#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) 123#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
124#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) 124#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
125 125
126#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) 126#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32)
127 127
128#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) 128#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
129#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) 129#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
130#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) 130#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
131#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) 131#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
132 132
133#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) 133#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
134#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) 134#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
135#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) 135#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
136#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) 136#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
137 137
138/* 138/*
139 * Ethernet and Serial DMA Descriptor base address (Table 7-6) 139 * Ethernet and Serial DMA Descriptor base address (Table 7-6)
140 */ 140 */
141 141
142#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) 142#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0)
143 143
144 144
145/* 145/*
146 * ASIC Mode Base Address (Table 7-7) 146 * ASIC Mode Base Address (Table 7-7)
147 */ 147 */
148 148
149#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) 149#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0)
150 150
151/* 151/*
152 * DMA Descriptor Count Registers (Table 7-8) 152 * DMA Descriptor Count Registers (Table 7-8)
@@ -160,9 +160,9 @@
160 */ 160 */
161 161
162#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) 162#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
163#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) 163#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
164#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 164#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
165#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 165#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
166 166
167#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 167#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
168#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 168#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
@@ -173,12 +173,12 @@
173 */ 173 */
174#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 174#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
175#define S_DMA_OODLOST_RX _SB_MAKE64(0) 175#define S_DMA_OODLOST_RX _SB_MAKE64(0)
176#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 176#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
177#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 177#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
178 178
179#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 179#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
180#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 180#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
181#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 181#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
182#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 182#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
183 183
184/* ********************************************************************* 184/* *********************************************************************
@@ -190,39 +190,39 @@
190 */ 190 */
191 191
192#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) 192#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
193#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) 193#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
194#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) 194#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
195#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) 195#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
196 196
197/* Note: Don't shift the address over, just mask it with the mask below */ 197/* Note: Don't shift the address over, just mask it with the mask below */
198#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) 198#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
199#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) 199#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
200 200
201#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 201#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
202 202
203#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 203#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
204#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 204#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
205#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 205#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
206#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 206#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
207 207
208#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 208#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
209#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 209#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
210#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 210#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
211#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 211#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
212 212
213#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 213#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
214#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 214#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
215#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 215#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
216#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 216#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
217#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 217#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
218 218
219#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 219#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
220#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 220#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
221 221
222#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) 222#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
223#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) 223#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
224#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) 224#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
225#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) 225#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
226 226
227/* 227/*
228 * Descriptor doubleword "B" (Table 7-13) 228 * Descriptor doubleword "B" (Table 7-13)
@@ -230,49 +230,49 @@
230 230
231 231
232#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) 232#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
233#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) 233#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
234#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 234#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
235#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 235#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
236 236
237#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 237#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 238#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
239#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 239#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
240#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 240#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
241#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 241#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
242#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 242#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
243 243
244#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 244#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
245 245
246/* Note: Don't shift the address over, just mask it with the mask below */ 246/* Note: Don't shift the address over, just mask it with the mask below */
247#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) 247#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
248#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) 248#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
249 249
250#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) 250#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
251#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) 251#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
252#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) 252#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
253#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) 253#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
254 254
255#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 255#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
256 256
257#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 257#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
258#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 258#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
259#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 259#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
260#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 260#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
261#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 261#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
262#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 262#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
263 263
264#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 264#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
265#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 265#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
266#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) 266#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
267#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) 267#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
268 268
269/* 269/*
270 * from pass2 some bits in dscr_b are also used for rx status 270 * from pass2 some bits in dscr_b are also used for rx status
271 */ 271 */
272#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) 272#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
273#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) 273#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
274#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) 274#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
275#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) 275#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
276 276
277/* 277/*
278 * Ethernet Descriptor Status Bits (Table 7-15) 278 * Ethernet Descriptor Status Bits (Table 7-15)
@@ -293,14 +293,14 @@
293#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 293#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
294 294
295#define S_DMA_ETHRX_RXCH 53 295#define S_DMA_ETHRX_RXCH 53
296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
297#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) 297#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
298#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) 298#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
299 299
300#define S_DMA_ETHRX_PKTTYPE 55 300#define S_DMA_ETHRX_PKTTYPE 55
301#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) 301#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
302#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) 302#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
303#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) 303#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
304 304
305#define K_DMA_ETHRX_PKTTYPE_IPV4 0 305#define K_DMA_ETHRX_PKTTYPE_IPV4 0
306#define K_DMA_ETHRX_PKTTYPE_ARPV4 1 306#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
@@ -385,21 +385,21 @@
385 * Register: DM_DSCR_BASE_3 385 * Register: DM_DSCR_BASE_3
386 */ 386 */
387 387
388#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) 388#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0)
389 389
390/* Note: Just mask the base address and then OR it in. */ 390/* Note: Just mask the base address and then OR it in. */
391#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) 391#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
392#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) 392#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
393 393
394#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) 394#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
395#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) 395#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
396#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) 396#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
397#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) 397#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
398 398
399#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) 399#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
400#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) 400#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
401#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) 401#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
402#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) 402#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
403 403
404#define K_DM_DSCR_BASE_PRIORITY_1 0 404#define K_DM_DSCR_BASE_PRIORITY_1 0
405#define K_DM_DSCR_BASE_PRIORITY_2 1 405#define K_DM_DSCR_BASE_PRIORITY_2 1
@@ -429,12 +429,12 @@
429 */ 429 */
430 430
431#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) 431#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
432#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) 432#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
433 433
434#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) 434#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
435#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) 435#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
436#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) 436#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
437#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ 437#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
438 M_DM_CUR_DSCR_DSCR_COUNT) 438 M_DM_CUR_DSCR_DSCR_COUNT)
439 439
440 440
@@ -447,15 +447,15 @@
447 * Register: DM_PARTIAL_3 447 * Register: DM_PARTIAL_3
448 */ 448 */
449#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) 449#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
450#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) 450#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
451#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) 451#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
452#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ 452#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
453 M_DM_PARTIAL_CRC_PARTIAL) 453 M_DM_PARTIAL_CRC_PARTIAL)
454 454
455#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) 455#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
456#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) 456#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
457#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) 457#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
458#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ 458#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
459 M_DM_PARTIAL_TCPCS_PARTIAL) 459 M_DM_PARTIAL_TCPCS_PARTIAL)
460 460
461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
@@ -469,15 +469,15 @@
469 * Register: CRC_DEF_1 469 * Register: CRC_DEF_1
470 */ 470 */
471#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) 471#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
472#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) 472#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
473#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) 473#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
474#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ 474#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
475 M_CRC_DEF_CRC_INIT) 475 M_CRC_DEF_CRC_INIT)
476 476
477#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) 477#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
478#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) 478#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
481 M_CRC_DEF_CRC_POLY) 481 M_CRC_DEF_CRC_POLY)
482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
483 483
@@ -489,21 +489,21 @@
489 * Register: CTCP_DEF_1 489 * Register: CTCP_DEF_1
490 */ 490 */
491#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) 491#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
492#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) 492#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
493#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) 493#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
494#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ 494#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
495 M_CTCP_DEF_CRC_TXOR) 495 M_CTCP_DEF_CRC_TXOR)
496 496
497#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) 497#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
498#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) 498#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
499#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) 499#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
500#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ 500#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
501 M_CTCP_DEF_TCPCS_INIT) 501 M_CTCP_DEF_TCPCS_INIT)
502 502
503#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) 503#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
504#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) 504#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
505#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) 505#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
506#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ 506#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
507 M_CTCP_DEF_CRC_WIDTH) 507 M_CTCP_DEF_CRC_WIDTH)
508 508
509#define K_CTCP_DEF_CRC_WIDTH_4 0 509#define K_CTCP_DEF_CRC_WIDTH_4 0
@@ -519,7 +519,7 @@
519 */ 519 */
520 520
521#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) 521#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
522#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) 522#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
523 523
524#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) 524#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
525#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) 525#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
@@ -529,30 +529,30 @@
529#endif /* up to 1250 PASS1 */ 529#endif /* up to 1250 PASS1 */
530 530
531#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) 531#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
532#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) 532#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
533#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) 533#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
534#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) 534#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
535 535
536#define K_DM_DSCRA_DIR_DEST_INCR 0 536#define K_DM_DSCRA_DIR_DEST_INCR 0
537#define K_DM_DSCRA_DIR_DEST_DECR 1 537#define K_DM_DSCRA_DIR_DEST_DECR 1
538#define K_DM_DSCRA_DIR_DEST_CONST 2 538#define K_DM_DSCRA_DIR_DEST_CONST 2
539 539
540#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) 540#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
541#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) 541#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
542#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) 542#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
543 543
544#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) 544#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
545#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) 545#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
546#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) 546#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
547#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) 547#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
548 548
549#define K_DM_DSCRA_DIR_SRC_INCR 0 549#define K_DM_DSCRA_DIR_SRC_INCR 0
550#define K_DM_DSCRA_DIR_SRC_DECR 1 550#define K_DM_DSCRA_DIR_SRC_DECR 1
551#define K_DM_DSCRA_DIR_SRC_CONST 2 551#define K_DM_DSCRA_DIR_SRC_CONST 2
552 552
553#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) 553#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
554#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) 554#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
555#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) 555#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
556 556
557 557
558#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) 558#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
@@ -576,19 +576,19 @@
576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
577#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 577#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
578 578
579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61)
580 580
581/* 581/*
582 * Data Mover Descriptor Doubleword "B" (Table 7-25) 582 * Data Mover Descriptor Doubleword "B" (Table 7-25)
583 */ 583 */
584 584
585#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) 585#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
586#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) 586#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
587 587
588#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) 588#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
589#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) 589#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
590#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) 590#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
591#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) 591#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
592 592
593 593
594#endif 594#endif
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index 1b5cbc5c6454..94e9c7c8e783 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -11,7 +11,7 @@
11 * 11 *
12 ********************************************************************* 12 *********************************************************************
13 * 13 *
14 * Copyright 2000,2001,2002,2003 14 * Copyright 2000, 2001, 2002, 2003
15 * Broadcom Corporation. All rights reserved. 15 * Broadcom Corporation. All rights reserved.
16 * 16 *
17 * This program is free software; you can redistribute it and/or 17 * This program is free software; you can redistribute it and/or
@@ -47,7 +47,7 @@
47#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 47#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
48 48
49#define S_IO_WIDTH_SEL 2 49#define S_IO_WIDTH_SEL 2
50#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) 50#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
51#define K_IO_WIDTH_SEL_1 0 51#define K_IO_WIDTH_SEL_1 0
52#define K_IO_WIDTH_SEL_2 1 52#define K_IO_WIDTH_SEL_2 1
53#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 53#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
@@ -55,8 +55,8 @@
55#define K_IO_WIDTH_SEL_1L 2 55#define K_IO_WIDTH_SEL_1L 2
56#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 56#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
57#define K_IO_WIDTH_SEL_4 3 57#define K_IO_WIDTH_SEL_4 3
58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) 58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) 59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
60 60
61#define S_IO_PARITY_ENA 4 61#define S_IO_PARITY_ENA 4
62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
@@ -71,18 +71,18 @@
71#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 71#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
72 72
73#define S_IO_TIMEOUT 8 73#define S_IO_TIMEOUT 8
74#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) 74#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT)
75#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) 75#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT)
76#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) 76#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
77 77
78/* 78/*
79 * Generic Bus Region Size register (Table 11-5) 79 * Generic Bus Region Size register (Table 11-5)
80 */ 80 */
81 81
82#define S_IO_MULT_SIZE 0 82#define S_IO_MULT_SIZE 0
83#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) 83#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE)
84#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) 84#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
85#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) 85#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
86 86
87#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 87#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
88 88
@@ -91,9 +91,9 @@
91 */ 91 */
92 92
93#define S_IO_START_ADDR 0 93#define S_IO_START_ADDR 0
94#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) 94#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR)
95#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) 95#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR)
96#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) 96#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
97 97
98#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 98#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
99 99
@@ -105,9 +105,9 @@
105 */ 105 */
106 106
107#define S_IO_ALE_WIDTH 0 107#define S_IO_ALE_WIDTH 0
108#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) 108#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
109#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) 109#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
110#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) 110#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
111 111
112#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 112#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
113 || SIBYTE_HDR_FEATURE_CHIP(1480) 113 || SIBYTE_HDR_FEATURE_CHIP(1480)
@@ -115,27 +115,27 @@
115#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 115#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
116 116
117#define S_IO_ALE_TO_CS 4 117#define S_IO_ALE_TO_CS 4
118#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) 118#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
119#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) 119#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
120#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) 120#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
121 121
122#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 122#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
123 || SIBYTE_HDR_FEATURE_CHIP(1480) 123 || SIBYTE_HDR_FEATURE_CHIP(1480)
124#define S_IO_BURST_WIDTH _SB_MAKE64(6) 124#define S_IO_BURST_WIDTH _SB_MAKE64(6)
125#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) 125#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
126#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) 126#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
127#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) 127#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
128#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 128#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
129 129
130#define S_IO_CS_WIDTH 8 130#define S_IO_CS_WIDTH 8
131#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) 131#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH)
132#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) 132#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
133#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) 133#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
134 134
135#define S_IO_RDY_SMPLE 13 135#define S_IO_RDY_SMPLE 13
136#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) 136#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
137#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) 137#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
138#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) 138#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
139 139
140 140
141/* 141/*
@@ -143,9 +143,9 @@
143 */ 143 */
144 144
145#define S_IO_ALE_TO_WRITE 0 145#define S_IO_ALE_TO_WRITE 0
146#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) 146#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
147#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) 147#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
148#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) 148#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
149 149
150#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 150#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
151 || SIBYTE_HDR_FEATURE_CHIP(1480) 151 || SIBYTE_HDR_FEATURE_CHIP(1480)
@@ -153,30 +153,30 @@
153#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 153#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
154 154
155#define S_IO_WRITE_WIDTH 4 155#define S_IO_WRITE_WIDTH 4
156#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) 156#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
157#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) 157#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
158#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) 158#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
159 159
160#define S_IO_IDLE_CYCLE 8 160#define S_IO_IDLE_CYCLE 8
161#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) 161#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
162#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) 162#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
163#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) 163#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
164 164
165#define S_IO_OE_TO_CS 12 165#define S_IO_OE_TO_CS 12
166#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) 166#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS)
167#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) 167#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
168#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) 168#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
169 169
170#define S_IO_CS_TO_OE 14 170#define S_IO_CS_TO_OE 14
171#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) 171#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE)
172#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) 172#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
173#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) 173#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
174 174
175/* 175/*
176 * Generic Bus Interrupt Status Register (Table 11-9) 176 * Generic Bus Interrupt Status Register (Table 11-9)
177 */ 177 */
178 178
179#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) 179#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8)
180#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 180#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
181#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 181#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
182#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 182#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
@@ -200,116 +200,116 @@
200 */ 200 */
201 201
202#define S_IO_SLEW0 0 202#define S_IO_SLEW0 0
203#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) 203#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0)
204#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) 204#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0)
205#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) 205#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
206 206
207#define S_IO_DRV_A 2 207#define S_IO_DRV_A 2
208#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) 208#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A)
209#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) 209#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A)
210#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) 210#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
211 211
212#define S_IO_DRV_B 6 212#define S_IO_DRV_B 6
213#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) 213#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B)
214#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) 214#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B)
215#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) 215#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
216 216
217#define S_IO_DRV_C 10 217#define S_IO_DRV_C 10
218#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) 218#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C)
219#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) 219#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C)
220#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) 220#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
221 221
222#define S_IO_DRV_D 14 222#define S_IO_DRV_D 14
223#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) 223#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D)
224#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) 224#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D)
225#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) 225#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
226 226
227/* 227/*
228 * Generic Bus Output Drive Control Register 1 (Table 14-19) 228 * Generic Bus Output Drive Control Register 1 (Table 14-19)
229 */ 229 */
230 230
231#define S_IO_DRV_E 2 231#define S_IO_DRV_E 2
232#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) 232#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E)
233#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) 233#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E)
234#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) 234#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
235 235
236#define S_IO_DRV_F 6 236#define S_IO_DRV_F 6
237#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) 237#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F)
238#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) 238#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F)
239#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) 239#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
240 240
241#define S_IO_SLEW1 8 241#define S_IO_SLEW1 8
242#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) 242#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1)
243#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) 243#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1)
244#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) 244#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
245 245
246#define S_IO_DRV_G 10 246#define S_IO_DRV_G 10
247#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) 247#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G)
248#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) 248#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G)
249#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) 249#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
250 250
251#define S_IO_SLEW2 12 251#define S_IO_SLEW2 12
252#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) 252#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2)
253#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) 253#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2)
254#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) 254#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
255 255
256#define S_IO_DRV_H 14 256#define S_IO_DRV_H 14
257#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) 257#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H)
258#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) 258#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H)
259#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) 259#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
260 260
261/* 261/*
262 * Generic Bus Output Drive Control Register 2 (Table 14-20) 262 * Generic Bus Output Drive Control Register 2 (Table 14-20)
263 */ 263 */
264 264
265#define S_IO_DRV_J 2 265#define S_IO_DRV_J 2
266#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) 266#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J)
267#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) 267#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J)
268#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) 268#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
269 269
270#define S_IO_DRV_K 6 270#define S_IO_DRV_K 6
271#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) 271#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K)
272#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) 272#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K)
273#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) 273#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
274 274
275#define S_IO_DRV_L 10 275#define S_IO_DRV_L 10
276#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) 276#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L)
277#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) 277#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L)
278#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) 278#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
279 279
280#define S_IO_DRV_M 14 280#define S_IO_DRV_M 14
281#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) 281#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M)
282#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) 282#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M)
283#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) 283#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
284 284
285/* 285/*
286 * Generic Bus Output Drive Control Register 3 (Table 14-21) 286 * Generic Bus Output Drive Control Register 3 (Table 14-21)
287 */ 287 */
288 288
289#define S_IO_SLEW3 0 289#define S_IO_SLEW3 0
290#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) 290#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3)
291#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) 291#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3)
292#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) 292#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
293 293
294#define S_IO_DRV_N 2 294#define S_IO_DRV_N 2
295#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) 295#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N)
296#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) 296#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N)
297#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) 297#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
298 298
299#define S_IO_DRV_P 6 299#define S_IO_DRV_P 6
300#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) 300#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P)
301#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) 301#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P)
302#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) 302#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
303 303
304#define S_IO_DRV_Q 10 304#define S_IO_DRV_Q 10
305#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) 305#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q)
306#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) 306#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q)
307#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) 307#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
308 308
309#define S_IO_DRV_R 14 309#define S_IO_DRV_R 14
310#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) 310#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R)
311#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) 311#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R)
312#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) 312#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
313 313
314 314
315/* 315/*
@@ -329,9 +329,9 @@
329 329
330#if SIBYTE_HDR_FEATURE_CHIP(1480) 330#if SIBYTE_HDR_FEATURE_CHIP(1480)
331#define S_PCMCIA_MODE 16 331#define S_PCMCIA_MODE 16
332#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) 332#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE)
333#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) 333#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE)
334#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) 334#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
335 335
336#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ 336#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
337#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ 337#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
@@ -369,49 +369,49 @@
369#define K_GPIO_INTR_SPLIT 3 369#define K_GPIO_INTR_SPLIT 3
370 370
371#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 371#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
372#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) 372#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
373#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) 373#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
374#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) 374#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
375 375
376#define S_GPIO_INTR_TYPE0 0 376#define S_GPIO_INTR_TYPE0 0
377#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) 377#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
378#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) 378#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
379#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) 379#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
380 380
381#define S_GPIO_INTR_TYPE2 2 381#define S_GPIO_INTR_TYPE2 2
382#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) 382#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
383#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) 383#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
384#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) 384#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
385 385
386#define S_GPIO_INTR_TYPE4 4 386#define S_GPIO_INTR_TYPE4 4
387#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) 387#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
388#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) 388#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
389#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) 389#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
390 390
391#define S_GPIO_INTR_TYPE6 6 391#define S_GPIO_INTR_TYPE6 6
392#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) 392#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
393#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) 393#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
394#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) 394#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
395 395
396#define S_GPIO_INTR_TYPE8 8 396#define S_GPIO_INTR_TYPE8 8
397#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) 397#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
398#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) 398#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
399#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) 399#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
400 400
401#define S_GPIO_INTR_TYPE10 10 401#define S_GPIO_INTR_TYPE10 10
402#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) 402#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
403#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) 403#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
404#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) 404#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
405 405
406#define S_GPIO_INTR_TYPE12 12 406#define S_GPIO_INTR_TYPE12 12
407#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) 407#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
408#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) 408#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
409#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) 409#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
410 410
411#define S_GPIO_INTR_TYPE14 14 411#define S_GPIO_INTR_TYPE14 14
412#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) 412#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
413#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) 413#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
414#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) 414#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
415 415
416#if SIBYTE_HDR_FEATURE_CHIP(1480) 416#if SIBYTE_HDR_FEATURE_CHIP(1480)
417 417
@@ -425,49 +425,49 @@
425#define K_GPIO_INTR_UNPRED2 3 425#define K_GPIO_INTR_UNPRED2 3
426 426
427#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) 427#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
428#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) 428#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
429#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) 429#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
430#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) 430#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
431 431
432#define S_GPIO_INTR_ATYPE0 0 432#define S_GPIO_INTR_ATYPE0 0
433#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) 433#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
434#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) 434#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
435#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) 435#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
436 436
437#define S_GPIO_INTR_ATYPE2 2 437#define S_GPIO_INTR_ATYPE2 2
438#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) 438#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
439#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) 439#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
440#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) 440#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
441 441
442#define S_GPIO_INTR_ATYPE4 4 442#define S_GPIO_INTR_ATYPE4 4
443#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) 443#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
444#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) 444#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
445#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) 445#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
446 446
447#define S_GPIO_INTR_ATYPE6 6 447#define S_GPIO_INTR_ATYPE6 6
448#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) 448#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
449#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) 449#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
450#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) 450#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
451 451
452#define S_GPIO_INTR_ATYPE8 8 452#define S_GPIO_INTR_ATYPE8 8
453#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) 453#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
454#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) 454#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
455#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) 455#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
456 456
457#define S_GPIO_INTR_ATYPE10 10 457#define S_GPIO_INTR_ATYPE10 10
458#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) 458#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
459#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) 459#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
460#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) 460#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
461 461
462#define S_GPIO_INTR_ATYPE12 12 462#define S_GPIO_INTR_ATYPE12 12
463#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) 463#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
464#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) 464#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
465#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) 465#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
466 466
467#define S_GPIO_INTR_ATYPE14 14 467#define S_GPIO_INTR_ATYPE14 14
468#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) 468#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
469#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) 469#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
470#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) 470#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
471#endif 471#endif
472 472
473 473
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index 94e8299b0a2a..f2850b4bcfd4 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000, 2001, 2002, 2003
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -150,7 +150,7 @@
150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) 150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) 151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) 152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
153#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0) 153#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0)
154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
155#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) 155#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
156#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) 156#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
@@ -208,9 +208,9 @@
208 */ 208 */
209 209
210#define S_INT_LDT_INTMSG 0 210#define S_INT_LDT_INTMSG 0
211#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG) 211#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
212#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG) 212#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
213#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG) 213#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
214 214
215#define K_INT_LDT_INTMSG_FIXED 0 215#define K_INT_LDT_INTMSG_FIXED 0
216#define K_INT_LDT_INTMSG_ARBITRATED 1 216#define K_INT_LDT_INTMSG_ARBITRATED 1
@@ -228,14 +228,14 @@
228#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) 228#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
229 229
230#define S_INT_LDT_INTDEST 5 230#define S_INT_LDT_INTDEST 5
231#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST) 231#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
232#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST) 232#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
233#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST) 233#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
234 234
235#define S_INT_LDT_VECTOR 13 235#define S_INT_LDT_VECTOR 13
236#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR) 236#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
237#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR) 237#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
238#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR) 238#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
239 239
240/* 240/*
241 * Vector format (Table 4-6) 241 * Vector format (Table 4-6)
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 842f205094af..6554dcf05cfe 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -40,27 +40,27 @@
40 */ 40 */
41 41
42#define S_L2C_TAG_MBZ 0 42#define S_L2C_TAG_MBZ 0
43#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ) 43#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
44 44
45#define S_L2C_TAG_INDEX 5 45#define S_L2C_TAG_INDEX 5
46#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX) 46#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
47#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX) 47#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
48#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX) 48#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
49 49
50#define S_L2C_TAG_TAG 17 50#define S_L2C_TAG_TAG 17
51#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG) 51#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG)
52#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG) 52#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
53#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG) 53#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
54 54
55#define S_L2C_TAG_ECC 40 55#define S_L2C_TAG_ECC 40
56#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC) 56#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC)
57#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC) 57#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
58#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC) 58#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
59 59
60#define S_L2C_TAG_WAY 46 60#define S_L2C_TAG_WAY 46
61#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY) 61#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY)
62#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY) 62#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
63#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY) 63#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
64 64
65#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) 65#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
66#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) 66#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
@@ -70,32 +70,32 @@
70 */ 70 */
71 71
72#define S_L2C_MGMT_INDEX 5 72#define S_L2C_MGMT_INDEX 5
73#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX) 73#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
74#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX) 74#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
75#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX) 75#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
76 76
77#define S_L2C_MGMT_QUADRANT 15 77#define S_L2C_MGMT_QUADRANT 15
78#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT) 78#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
79#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT) 79#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
80#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT) 80#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
81 81
82#define S_L2C_MGMT_HALF 16 82#define S_L2C_MGMT_HALF 16
83#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF) 83#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
84 84
85#define S_L2C_MGMT_WAY 17 85#define S_L2C_MGMT_WAY 17
86#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY) 86#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
87#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) 87#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
88#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) 88#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
89 89
90#define S_L2C_MGMT_ECC_DIAG 21 90#define S_L2C_MGMT_ECC_DIAG 21
91#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) 91#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
92#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) 92#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
93#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) 93#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
94 94
95#define S_L2C_MGMT_TAG 23 95#define S_L2C_MGMT_TAG 23
96#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) 96#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
97#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) 97#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
98#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) 98#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
99 99
100#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) 100#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
101#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) 101#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
@@ -111,9 +111,9 @@
111 * L2 Read Misc. register (A_L2_READ_MISC) 111 * L2 Read Misc. register (A_L2_READ_MISC)
112 */ 112 */
113#define S_L2C_MISC_NO_WAY 10 113#define S_L2C_MISC_NO_WAY 10
114#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY) 114#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
115#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY) 115#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
116#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY) 116#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
117 117
118#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) 118#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
119#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) 119#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index 7092535d1108..081e8b1c4ad0 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000, 2001, 2002, 2003
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -81,14 +81,14 @@
81 */ 81 */
82 82
83#define S_LDT_DEVICEID_VENDOR 0 83#define S_LDT_DEVICEID_VENDOR 0
84#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR) 84#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
85#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR) 85#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
86#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR) 86#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
87 87
88#define S_LDT_DEVICEID_DEVICEID 16 88#define S_LDT_DEVICEID_DEVICEID 16
89#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID) 89#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
90#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID) 90#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
91#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID) 91#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
92 92
93 93
94/* 94/*
@@ -111,14 +111,14 @@
111 */ 111 */
112 112
113#define S_LDT_CLASSREV_REV 0 113#define S_LDT_CLASSREV_REV 0
114#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV) 114#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
115#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV) 115#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
116#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV) 116#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
117 117
118#define S_LDT_CLASSREV_CLASS 8 118#define S_LDT_CLASSREV_CLASS 8
119#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS) 119#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
120#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS) 120#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
121#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS) 121#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
122 122
123#define K_LDT_REV 0x01 123#define K_LDT_REV 0x01
124#define K_LDT_CLASS 0x060000 124#define K_LDT_CLASS 0x060000
@@ -128,26 +128,26 @@
128 */ 128 */
129 129
130#define S_LDT_DEVHDR_CLINESZ 0 130#define S_LDT_DEVHDR_CLINESZ 0
131#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ) 131#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
132#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ) 132#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
133#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ) 133#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
134 134
135#define S_LDT_DEVHDR_LATTMR 8 135#define S_LDT_DEVHDR_LATTMR 8
136#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR) 136#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
137#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR) 137#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
138#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR) 138#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
139 139
140#define S_LDT_DEVHDR_HDRTYPE 16 140#define S_LDT_DEVHDR_HDRTYPE 16
141#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE) 141#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
142#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE) 142#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
143#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE) 143#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
144 144
145#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 145#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
146 146
147#define S_LDT_DEVHDR_BIST 24 147#define S_LDT_DEVHDR_BIST 24
148#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST) 148#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
149#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST) 149#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
150#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST) 150#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
151 151
152 152
153 153
@@ -170,9 +170,9 @@
170#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) 170#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
171 171
172#define S_LDT_STATUS_DEVSELTIMING 25 172#define S_LDT_STATUS_DEVSELTIMING 25
173#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING) 173#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
174#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING) 174#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
175#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING) 175#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
176 176
177#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) 177#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
178#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) 178#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
@@ -208,9 +208,9 @@
208#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) 208#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
209 209
210#define S_LDT_CMD_CAPTYPE 29 210#define S_LDT_CMD_CAPTYPE 29
211#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE) 211#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
212#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE) 212#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
213#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE) 213#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
214 214
215/* 215/*
216 * LDT link control register (Table 8-18), and (Table 8-19) 216 * LDT link control register (Table 8-18), and (Table 8-19)
@@ -225,35 +225,35 @@
225#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) 225#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
226 226
227#define S_LDT_LINKCTRL_CRCERR 8 227#define S_LDT_LINKCTRL_CRCERR 8
228#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR) 228#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
229#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR) 229#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
230#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR) 230#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
231 231
232#define S_LDT_LINKCTRL_MAXIN 16 232#define S_LDT_LINKCTRL_MAXIN 16
233#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN) 233#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
234#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN) 234#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
235#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN) 235#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
236 236
237#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) 237#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
238 238
239#define S_LDT_LINKCTRL_MAXOUT 20 239#define S_LDT_LINKCTRL_MAXOUT 20
240#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT) 240#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
241#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT) 241#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
242#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT) 242#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
243 243
244#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) 244#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
245 245
246#define S_LDT_LINKCTRL_WIDTHIN 24 246#define S_LDT_LINKCTRL_WIDTHIN 24
247#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN) 247#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
248#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN) 248#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
249#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN) 249#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
250 250
251#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) 251#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
252 252
253#define S_LDT_LINKCTRL_WIDTHOUT 28 253#define S_LDT_LINKCTRL_WIDTHOUT 28
254#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT) 254#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
255#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT) 255#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
256#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT) 256#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
257 257
258#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) 258#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
259 259
@@ -262,9 +262,9 @@
262 */ 262 */
263 263
264#define S_LDT_LINKFREQ_FREQ 8 264#define S_LDT_LINKFREQ_FREQ 8
265#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ) 265#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
266#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ) 266#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
267#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ) 267#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
268 268
269#define K_LDT_LINKFREQ_200MHZ 0 269#define K_LDT_LINKFREQ_200MHZ 0
270#define K_LDT_LINKFREQ_300MHZ 1 270#define K_LDT_LINKFREQ_300MHZ 1
@@ -293,16 +293,16 @@
293 293
294 294
295#define S_LDT_SRICMD_RXMARGIN 20 295#define S_LDT_SRICMD_RXMARGIN 20
296#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN) 296#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
297#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN) 297#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
298#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN) 298#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
299 299
300#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) 300#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
301 301
302#define S_LDT_SRICMD_TXINITIALOFFSET 28 302#define S_LDT_SRICMD_TXINITIALOFFSET 28
303#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET) 303#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
304#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET) 304#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
305#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET) 305#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
306 306
307#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) 307#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
308 308
@@ -340,73 +340,73 @@
340 */ 340 */
341 341
342#define S_LDT_SRICTRL_NEEDRESP 0 342#define S_LDT_SRICTRL_NEEDRESP 0
343#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP) 343#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
344#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP) 344#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
345#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP) 345#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
346 346
347#define S_LDT_SRICTRL_NEEDNPREQ 2 347#define S_LDT_SRICTRL_NEEDNPREQ 2
348#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ) 348#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
349#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ) 349#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
350#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ) 350#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
351 351
352#define S_LDT_SRICTRL_NEEDPREQ 4 352#define S_LDT_SRICTRL_NEEDPREQ 4
353#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ) 353#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
354#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ) 354#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
355#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ) 355#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
356 356
357#define S_LDT_SRICTRL_WANTRESP 8 357#define S_LDT_SRICTRL_WANTRESP 8
358#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP) 358#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
359#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP) 359#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
360#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP) 360#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
361 361
362#define S_LDT_SRICTRL_WANTNPREQ 10 362#define S_LDT_SRICTRL_WANTNPREQ 10
363#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ) 363#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
364#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ) 364#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
365#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ) 365#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
366 366
367#define S_LDT_SRICTRL_WANTPREQ 12 367#define S_LDT_SRICTRL_WANTPREQ 12
368#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ) 368#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
369#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ) 369#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
370#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ) 370#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
371 371
372#define S_LDT_SRICTRL_BUFRELSPACE 16 372#define S_LDT_SRICTRL_BUFRELSPACE 16
373#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE) 373#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
374#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE) 374#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
375#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE) 375#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
376 376
377/* 377/*
378 * LDT SRI Transmit Buffer Count register (Table 8-26) 378 * LDT SRI Transmit Buffer Count register (Table 8-26)
379 */ 379 */
380 380
381#define S_LDT_TXBUFCNT_PCMD 0 381#define S_LDT_TXBUFCNT_PCMD 0
382#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD) 382#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
383#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD) 383#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
384#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD) 384#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
385 385
386#define S_LDT_TXBUFCNT_PDATA 4 386#define S_LDT_TXBUFCNT_PDATA 4
387#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA) 387#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
388#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA) 388#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
389#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA) 389#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
390 390
391#define S_LDT_TXBUFCNT_NPCMD 8 391#define S_LDT_TXBUFCNT_NPCMD 8
392#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD) 392#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
393#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD) 393#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
394#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD) 394#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
395 395
396#define S_LDT_TXBUFCNT_NPDATA 12 396#define S_LDT_TXBUFCNT_NPDATA 12
397#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA) 397#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
398#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA) 398#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
399#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA) 399#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
400 400
401#define S_LDT_TXBUFCNT_RCMD 16 401#define S_LDT_TXBUFCNT_RCMD 16
402#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD) 402#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
403#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD) 403#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
404#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD) 404#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
405 405
406#define S_LDT_TXBUFCNT_RDATA 20 406#define S_LDT_TXBUFCNT_RDATA 20
407#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA) 407#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
408#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA) 408#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
409#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA) 409#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
410 410
411#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 411#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
412/* 412/*
@@ -414,9 +414,9 @@
414 */ 414 */
415 415
416#define S_LDT_ADDSTATUS_TGTDONE 0 416#define S_LDT_ADDSTATUS_TGTDONE 0
417#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE) 417#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
418#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE) 418#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
419#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE) 419#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
420#endif /* 1250 PASS2 || 112x PASS1 */ 420#endif /* 1250 PASS2 || 112x PASS1 */
421 421
422#endif 422#endif
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 833c8b59d687..b6faf08ca81d 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -55,8 +55,8 @@
55#define M_MAC_BURST_EN _SB_MAKEMASK1(5) 55#define M_MAC_BURST_EN _SB_MAKEMASK1(5)
56 56
57#define S_MAC_TX_PAUSE _SB_MAKE64(6) 57#define S_MAC_TX_PAUSE _SB_MAKE64(6)
58#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 58#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
59#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 59#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
60 60
61#define K_MAC_TX_PAUSE_CNT_512 0 61#define K_MAC_TX_PAUSE_CNT_512 0
62#define K_MAC_TX_PAUSE_CNT_1K 1 62#define K_MAC_TX_PAUSE_CNT_1K 1
@@ -76,7 +76,7 @@
76#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 76#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
77#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 77#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
78 78
79#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 79#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9)
80 80
81#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 81#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
82 82
@@ -91,15 +91,15 @@
91#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 91#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24)
92#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 92#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25)
93 93
94#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 94#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26)
95 95
96#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 96#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32)
97#define M_MAC_HDX_EN _SB_MAKEMASK1(33) 97#define M_MAC_HDX_EN _SB_MAKEMASK1(33)
98 98
99#define S_MAC_SPEED_SEL _SB_MAKE64(34) 99#define S_MAC_SPEED_SEL _SB_MAKE64(34)
100#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 100#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
101#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 101#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
102#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 102#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
103 103
104#define K_MAC_SPEED_SEL_10MBPS 0 104#define K_MAC_SPEED_SEL_10MBPS 0
105#define K_MAC_SPEED_SEL_100MBPS 1 105#define K_MAC_SPEED_SEL_100MBPS 1
@@ -117,9 +117,9 @@
117#define M_MAC_SS_EN _SB_MAKEMASK1(39) 117#define M_MAC_SS_EN _SB_MAKEMASK1(39)
118 118
119#define S_MAC_BYPASS_CFG _SB_MAKE64(40) 119#define S_MAC_BYPASS_CFG _SB_MAKE64(40)
120#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 120#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
121#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 121#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
122#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 122#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
123 123
124#define K_MAC_BYPASS_GMII 0 124#define K_MAC_BYPASS_GMII 0
125#define K_MAC_BYPASS_ENCODED 1 125#define K_MAC_BYPASS_ENCODED 1
@@ -138,9 +138,9 @@
138#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 138#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
139 139
140#define S_MAC_BYPASS_IFG _SB_MAKE64(46) 140#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
141#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 141#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
142#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 142#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
143#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 143#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
144 144
145#define K_MAC_FC_CMD_DISABLED 0 145#define K_MAC_FC_CMD_DISABLED 0
146#define K_MAC_FC_CMD_ENABLED 1 146#define K_MAC_FC_CMD_ENABLED 1
@@ -153,14 +153,14 @@
153#define M_MAC_FC_SEL _SB_MAKEMASK1(54) 153#define M_MAC_FC_SEL _SB_MAKEMASK1(54)
154 154
155#define S_MAC_FC_CMD _SB_MAKE64(55) 155#define S_MAC_FC_CMD _SB_MAKE64(55)
156#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 156#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD)
157#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 157#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD)
158#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 158#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
159 159
160#define S_MAC_RX_CH_SEL _SB_MAKE64(57) 160#define S_MAC_RX_CH_SEL _SB_MAKE64(57)
161#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 161#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
162#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 162#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
163#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 163#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
164 164
165 165
166/* 166/*
@@ -202,14 +202,14 @@
202 */ 202 */
203 203
204#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 204#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0)
205#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 205#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
206#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 206#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
207#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 207#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
208 208
209#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 209#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4)
210#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 210#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
211#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 211#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
213 213
214/* 214/*
215 * MAC Fifo Threshhold registers (Table 9-14) 215 * MAC Fifo Threshhold registers (Table 9-14)
@@ -221,50 +221,50 @@
221#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 221#define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
222#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 222#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
225#endif /* up to 1250 PASS1 */ 225#endif /* up to 1250 PASS1 */
226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
228#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 228#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
231 231
232#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 232#define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
233#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 233#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
236#endif /* up to 1250 PASS1 */ 236#endif /* up to 1250 PASS1 */
237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
239#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 239#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
242 242
243#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 243#define S_MAC_TX_RL_THRSH _SB_MAKE64(16)
244#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 244#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
245#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 245#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
246#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 246#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
247 247
248#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 248#define S_MAC_RX_PL_THRSH _SB_MAKE64(24)
249#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 249#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
250#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 250#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
251#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 251#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
252 252
253#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 253#define S_MAC_RX_RD_THRSH _SB_MAKE64(32)
254#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 254#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
255#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 255#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
256#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 256#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
257 257
258#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 258#define S_MAC_RX_RL_THRSH _SB_MAKE64(40)
259#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 259#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
262 262
263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
268#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 268#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
269 269
270/* 270/*
@@ -276,51 +276,51 @@
276 276
277/* XXXCGD: ??? Unused in pass2? */ 277/* XXXCGD: ??? Unused in pass2? */
278#define S_MAC_IFG_RX _SB_MAKE64(0) 278#define S_MAC_IFG_RX _SB_MAKE64(0)
279#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 279#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX)
280#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 280#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX)
281#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 281#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
282 282
283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
284#define S_MAC_PRE_LEN _SB_MAKE64(0) 284#define S_MAC_PRE_LEN _SB_MAKE64(0)
285#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 285#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN)
286#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 286#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
287#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 287#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
288#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 288#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
289 289
290#define S_MAC_IFG_TX _SB_MAKE64(6) 290#define S_MAC_IFG_TX _SB_MAKE64(6)
291#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 291#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX)
292#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 292#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX)
293#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 293#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
294 294
295#define S_MAC_IFG_THRSH _SB_MAKE64(12) 295#define S_MAC_IFG_THRSH _SB_MAKE64(12)
296#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 296#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
297#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 297#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
298#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 298#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
299 299
300#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 300#define S_MAC_BACKOFF_SEL _SB_MAKE64(18)
301#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 301#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
302#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 302#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
303#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 303#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
304 304
305#define S_MAC_LFSR_SEED _SB_MAKE64(22) 305#define S_MAC_LFSR_SEED _SB_MAKE64(22)
306#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 306#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
307#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 307#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
308#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 308#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
309 309
310#define S_MAC_SLOT_SIZE _SB_MAKE64(30) 310#define S_MAC_SLOT_SIZE _SB_MAKE64(30)
311#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 311#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
312#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 312#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
313#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 313#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
314 314
315#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 315#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40)
316#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 316#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
317#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 317#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
318#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 318#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
319 319
320#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 320#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48)
321#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 321#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
322#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 322#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
323#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 323#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
324 324
325/* 325/*
326 * These constants are used to configure the fields within the Frame 326 * These constants are used to configure the fields within the Frame
@@ -377,20 +377,20 @@
377 */ 377 */
378 378
379#define S_MAC_VLAN_TAG _SB_MAKE64(0) 379#define S_MAC_VLAN_TAG _SB_MAKE64(0)
380#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) 380#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
381#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) 381#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
382#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) 382#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
383 383
384#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 384#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
385#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 385#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
386#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) 386#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
387#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) 387#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
388#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) 388#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
389 389
390#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 390#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
391#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) 391#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
392#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) 392#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
393#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) 393#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
394 394
395#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 395#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
396#endif /* 1250 PASS3 || 112x PASS1 */ 396#endif /* 1250 PASS3 || 112x PASS1 */
@@ -425,7 +425,7 @@
425 * is that you'll use one of the "S_" things above 425 * is that you'll use one of the "S_" things above
426 * and pass just the six bits to a DMA-channel-specific ISR 426 * and pass just the six bits to a DMA-channel-specific ISR
427 */ 427 */
428#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 428#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0)
429#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 429#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0)
430#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 430#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1)
431#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 431#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2)
@@ -440,19 +440,19 @@
440 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 440 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
441 * also DMA_TX/DMA_RX in sb_regs.h). 441 * also DMA_TX/DMA_RX in sb_regs.h).
442 */ 442 */
443#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 443#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
444 444
445#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) 445#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
446#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 446#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
447#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 447#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
448#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 448#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
449#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 449#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
450#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 450#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
451#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 451#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
452#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 452#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
453#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 453#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
454#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 454#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
455#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) 455#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
456 456
457 457
458#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 458#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
@@ -467,9 +467,9 @@
467#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 467#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
468 468
469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
471#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 471#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
472#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 472#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
473 473
474#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 474#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
475#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 475#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
@@ -483,24 +483,24 @@
483 */ 483 */
484 484
485#define S_MAC_TX_WRPTR _SB_MAKE64(0) 485#define S_MAC_TX_WRPTR _SB_MAKE64(0)
486#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 486#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
487#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 487#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
488#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 488#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
489 489
490#define S_MAC_TX_RDPTR _SB_MAKE64(8) 490#define S_MAC_TX_RDPTR _SB_MAKE64(8)
491#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 491#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
492#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 492#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
493#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 493#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
494 494
495#define S_MAC_RX_WRPTR _SB_MAKE64(16) 495#define S_MAC_RX_WRPTR _SB_MAKE64(16)
496#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 496#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
497#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 497#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
498#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 498#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
499 499
500#define S_MAC_RX_RDPTR _SB_MAKE64(24) 500#define S_MAC_RX_RDPTR _SB_MAKE64(24)
501#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 501#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
502#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 502#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
503#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 503#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
504 504
505/* 505/*
506 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 506 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register]
@@ -510,14 +510,14 @@
510 */ 510 */
511 511
512#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 512#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0)
513#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 513#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
514#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 514#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
515#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 515#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
516 516
517#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 517#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8)
518#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 518#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
519#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 519#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
520#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 520#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
521 521
522/* 522/*
523 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 523 * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
@@ -565,24 +565,24 @@
565#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 565#define S_TYPECFG_TYPESIZE _SB_MAKE64(16)
566 566
567#define S_TYPECFG_TYPE0 _SB_MAKE64(0) 567#define S_TYPECFG_TYPE0 _SB_MAKE64(0)
568#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 568#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
569#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 569#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
570#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 570#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
571 571
572#define S_TYPECFG_TYPE1 _SB_MAKE64(0) 572#define S_TYPECFG_TYPE1 _SB_MAKE64(0)
573#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 573#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
574#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 574#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
575#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 575#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
576 576
577#define S_TYPECFG_TYPE2 _SB_MAKE64(0) 577#define S_TYPECFG_TYPE2 _SB_MAKE64(0)
578#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 578#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
579#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 579#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
580#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 580#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
581 581
582#define S_TYPECFG_TYPE3 _SB_MAKE64(0) 582#define S_TYPECFG_TYPE3 _SB_MAKE64(0)
583#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 583#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
584#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 584#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
585#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 585#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
586 586
587/* 587/*
588 * MAC Receive Address Filter Control Registers (Table 9-24) 588 * MAC Receive Address Filter Control Registers (Table 9-24)
@@ -603,28 +603,28 @@
603#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 603#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
604 604
605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
607#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 607#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
608#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 608#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
609 609
610#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 610#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
611#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 611#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
612#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 612#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
613#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 613#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
614#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) 614#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
615 615
616#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 616#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
617#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) 617#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
618#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) 618#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
619#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) 619#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
620 620
621#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 621#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
622#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 622#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
623 623
624#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 624#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
625#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 625#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
626#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 626#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
627#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 627#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
628#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 628#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
629 629
630/* 630/*
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 4fe848ffbc31..1eb1b5a88736 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000, 2001, 2002, 2003
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -40,73 +40,73 @@
40 */ 40 */
41 41
42#define S_MC_RESERVED0 0 42#define S_MC_RESERVED0 0
43#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 43#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0)
44 44
45#define S_MC_CHANNEL_SEL 8 45#define S_MC_CHANNEL_SEL 8
46#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 46#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
47#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 47#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
48#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 48#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
49 49
50#define S_MC_BANK0_MAP 16 50#define S_MC_BANK0_MAP 16
51#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 51#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
52#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 52#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
53#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 53#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
54 54
55#define K_MC_BANK0_MAP_DEFAULT 0x00 55#define K_MC_BANK0_MAP_DEFAULT 0x00
56#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 56#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
57 57
58#define S_MC_BANK1_MAP 20 58#define S_MC_BANK1_MAP 20
59#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 59#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
60#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 60#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
61#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 61#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
62 62
63#define K_MC_BANK1_MAP_DEFAULT 0x08 63#define K_MC_BANK1_MAP_DEFAULT 0x08
64#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 64#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
65 65
66#define S_MC_BANK2_MAP 24 66#define S_MC_BANK2_MAP 24
67#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 67#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
68#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 68#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
69#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 69#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
70 70
71#define K_MC_BANK2_MAP_DEFAULT 0x09 71#define K_MC_BANK2_MAP_DEFAULT 0x09
72#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 72#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
73 73
74#define S_MC_BANK3_MAP 28 74#define S_MC_BANK3_MAP 28
75#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 75#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP)
76#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 76#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
77#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 77#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
78 78
79#define K_MC_BANK3_MAP_DEFAULT 0x0C 79#define K_MC_BANK3_MAP_DEFAULT 0x0C
80#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 80#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
81 81
82#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 82#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32)
83 83
84#define S_MC_QUEUE_SIZE 40 84#define S_MC_QUEUE_SIZE 40
85#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 85#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
86#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 86#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
87#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 87#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
88#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 88#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
89 89
90#define S_MC_AGE_LIMIT 44 90#define S_MC_AGE_LIMIT 44
91#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 91#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
92#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 92#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
93#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 93#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
94#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 94#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
95 95
96#define S_MC_WR_LIMIT 48 96#define S_MC_WR_LIMIT 48
97#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 97#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT)
98#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 98#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
99#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 99#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
100#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 100#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
101 101
102#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 102#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
103 103
104#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 104#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53)
105 105
106#define S_MC_CS_MODE 56 106#define S_MC_CS_MODE 56
107#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 107#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE)
108#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 108#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE)
109#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 109#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
110 110
111#define K_MC_CS_MODE_MSB_CS 0 111#define K_MC_CS_MODE_MSB_CS 0
112#define K_MC_CS_MODE_INTLV_CS 15 112#define K_MC_CS_MODE_INTLV_CS 15
@@ -138,9 +138,9 @@
138 */ 138 */
139 139
140#define S_MC_CLK_RATIO 0 140#define S_MC_CLK_RATIO 0
141#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 141#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO)
142#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 142#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
143#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 143#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
144 144
145#define K_MC_CLK_RATIO_2X 4 145#define K_MC_CLK_RATIO_2X 4
146#define K_MC_CLK_RATIO_25X 5 146#define K_MC_CLK_RATIO_25X 5
@@ -158,9 +158,9 @@
158#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 158#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
159 159
160#define S_MC_REF_RATE 8 160#define S_MC_REF_RATE 8
161#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 161#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE)
162#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 162#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE)
163#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 163#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
164 164
165#define K_MC_REF_RATE_100MHz 0x62 165#define K_MC_REF_RATE_100MHz 0x62
166#define K_MC_REF_RATE_133MHz 0x81 166#define K_MC_REF_RATE_133MHz 0x81
@@ -172,21 +172,21 @@
172#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 172#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
173 173
174#define S_MC_CLOCK_DRIVE 16 174#define S_MC_CLOCK_DRIVE 16
175#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 175#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
176#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 176#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
177#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 177#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
178#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 178#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
179 179
180#define S_MC_DATA_DRIVE 20 180#define S_MC_DATA_DRIVE 20
181#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 181#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
182#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 182#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
183#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 183#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
184#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 184#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
185 185
186#define S_MC_ADDR_DRIVE 24 186#define S_MC_ADDR_DRIVE 24
187#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 187#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
188#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 188#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
189#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 189#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
190#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 190#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
191 191
192#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 192#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
@@ -196,27 +196,27 @@
196#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 196#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
197 197
198#define S_MC_DQI_SKEW 32 198#define S_MC_DQI_SKEW 32
199#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 199#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW)
200#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 200#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
201#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 201#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
202#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 202#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
203 203
204#define S_MC_DQO_SKEW 40 204#define S_MC_DQO_SKEW 40
205#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 205#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW)
206#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 206#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
207#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 207#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
208#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 208#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
209 209
210#define S_MC_ADDR_SKEW 48 210#define S_MC_ADDR_SKEW 48
211#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 211#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
212#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 212#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
213#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 213#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
214#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 214#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
215 215
216#define S_MC_DLL_DEFAULT 56 216#define S_MC_DLL_DEFAULT 56
217#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 217#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
218#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 218#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
219#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 219#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
220#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 220#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
221 221
222#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 222#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
@@ -235,9 +235,9 @@
235 */ 235 */
236 236
237#define S_MC_COMMAND 0 237#define S_MC_COMMAND 0
238#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 238#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND)
239#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 239#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND)
240#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 240#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
241 241
242#define K_MC_COMMAND_EMRS 0 242#define K_MC_COMMAND_EMRS 0
243#define K_MC_COMMAND_MRS 1 243#define K_MC_COMMAND_MRS 1
@@ -267,21 +267,21 @@
267 */ 267 */
268 268
269#define S_MC_EMODE 0 269#define S_MC_EMODE 0
270#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 270#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE)
271#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 271#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE)
272#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 272#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
273#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 273#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
274 274
275#define S_MC_MODE 16 275#define S_MC_MODE 16
276#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 276#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE)
277#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 277#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE)
278#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 278#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
279#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 279#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
280 280
281#define S_MC_DRAM_TYPE 32 281#define S_MC_DRAM_TYPE 32
282#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 282#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
283#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 283#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
284#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 284#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
285 285
286#define K_MC_DRAM_TYPE_JEDEC 0 286#define K_MC_DRAM_TYPE_JEDEC 0
287#define K_MC_DRAM_TYPE_FCRAM 1 287#define K_MC_DRAM_TYPE_FCRAM 1
@@ -309,16 +309,16 @@
309#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 309#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
310 310
311#define S_MC_tFIFO 56 311#define S_MC_tFIFO 56
312#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 312#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO)
313#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 313#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO)
314#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) 314#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
315#define K_MC_tFIFO_DEFAULT 1 315#define K_MC_tFIFO_DEFAULT 1
316#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 316#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
317 317
318#define S_MC_tRFC 52 318#define S_MC_tRFC 52
319#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 319#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC)
320#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 320#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC)
321#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) 321#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
322#define K_MC_tRFC_DEFAULT 12 322#define K_MC_tRFC_DEFAULT 12
323#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 323#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
324 324
@@ -327,44 +327,44 @@
327#endif 327#endif
328 328
329#define S_MC_tCwCr 40 329#define S_MC_tCwCr 40
330#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 330#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr)
331#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 331#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr)
332#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) 332#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
333#define K_MC_tCwCr_DEFAULT 4 333#define K_MC_tCwCr_DEFAULT 4
334#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 334#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
335 335
336#define S_MC_tRCr 28 336#define S_MC_tRCr 28
337#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 337#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr)
338#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 338#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr)
339#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) 339#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
340#define K_MC_tRCr_DEFAULT 9 340#define K_MC_tRCr_DEFAULT 9
341#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 341#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
342 342
343#define S_MC_tRCw 24 343#define S_MC_tRCw 24
344#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 344#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw)
345#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 345#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw)
346#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) 346#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
347#define K_MC_tRCw_DEFAULT 10 347#define K_MC_tRCw_DEFAULT 10
348#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 348#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
349 349
350#define S_MC_tRRD 20 350#define S_MC_tRRD 20
351#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 351#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD)
352#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 352#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD)
353#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) 353#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
354#define K_MC_tRRD_DEFAULT 2 354#define K_MC_tRRD_DEFAULT 2
355#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 355#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
356 356
357#define S_MC_tRP 16 357#define S_MC_tRP 16
358#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 358#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP)
359#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 359#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP)
360#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) 360#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
361#define K_MC_tRP_DEFAULT 4 361#define K_MC_tRP_DEFAULT 4
362#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 362#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
363 363
364#define S_MC_tCwD 8 364#define S_MC_tCwD 8
365#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 365#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD)
366#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 366#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD)
367#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) 367#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
368#define K_MC_tCwD_DEFAULT 1 368#define K_MC_tCwD_DEFAULT 1
369#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 369#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
370 370
@@ -372,16 +372,16 @@
372#define M_MC_tCrDh M_tCrDh 372#define M_MC_tCrDh M_tCrDh
373 373
374#define S_MC_tCrD 4 374#define S_MC_tCrD 4
375#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 375#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD)
376#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 376#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD)
377#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) 377#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
378#define K_MC_tCrD_DEFAULT 2 378#define K_MC_tCrD_DEFAULT 2
379#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 379#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
380 380
381#define S_MC_tRCD 0 381#define S_MC_tRCD 0
382#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 382#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD)
383#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 383#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD)
384#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) 384#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
385#define K_MC_tRCD_DEFAULT 3 385#define K_MC_tRCD_DEFAULT 3
386#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 386#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
387 387
@@ -409,76 +409,76 @@
409 */ 409 */
410 410
411#define S_MC_CS0_START 0 411#define S_MC_CS0_START 0
412#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 412#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START)
413#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 413#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START)
414#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 414#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
415 415
416#define S_MC_CS1_START 16 416#define S_MC_CS1_START 16
417#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 417#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START)
418#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 418#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START)
419#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 419#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
420 420
421#define S_MC_CS2_START 32 421#define S_MC_CS2_START 32
422#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 422#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START)
423#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 423#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START)
424#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 424#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
425 425
426#define S_MC_CS3_START 48 426#define S_MC_CS3_START 48
427#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 427#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START)
428#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 428#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START)
429#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 429#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
430 430
431/* 431/*
432 * Chip Select End Address Register (Table 6-18) 432 * Chip Select End Address Register (Table 6-18)
433 */ 433 */
434 434
435#define S_MC_CS0_END 0 435#define S_MC_CS0_END 0
436#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 436#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END)
437#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 437#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END)
438#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 438#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
439 439
440#define S_MC_CS1_END 16 440#define S_MC_CS1_END 16
441#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 441#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END)
442#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 442#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END)
443#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 443#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
444 444
445#define S_MC_CS2_END 32 445#define S_MC_CS2_END 32
446#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 446#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END)
447#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 447#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END)
448#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 448#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
449 449
450#define S_MC_CS3_END 48 450#define S_MC_CS3_END 48
451#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 451#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END)
452#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 452#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END)
453#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 453#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
454 454
455/* 455/*
456 * Chip Select Interleave Register (Table 6-19) 456 * Chip Select Interleave Register (Table 6-19)
457 */ 457 */
458 458
459#define S_MC_INTLV_RESERVED 0 459#define S_MC_INTLV_RESERVED 0
460#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 460#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
461 461
462#define S_MC_INTERLEAVE 7 462#define S_MC_INTERLEAVE 7
463#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 463#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE)
464#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 464#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
465 465
466#define S_MC_INTLV_MBZ 25 466#define S_MC_INTLV_MBZ 25
467#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 467#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
468 468
469/* 469/*
470 * Row Address Bits Register (Table 6-20) 470 * Row Address Bits Register (Table 6-20)
471 */ 471 */
472 472
473#define S_MC_RAS_RESERVED 0 473#define S_MC_RAS_RESERVED 0
474#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 474#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
475 475
476#define S_MC_RAS_SELECT 12 476#define S_MC_RAS_SELECT 12
477#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 477#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT)
478#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 478#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
479 479
480#define S_MC_RAS_MBZ 37 480#define S_MC_RAS_MBZ 37
481#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 481#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ)
482 482
483 483
484/* 484/*
@@ -486,14 +486,14 @@
486 */ 486 */
487 487
488#define S_MC_CAS_RESERVED 0 488#define S_MC_CAS_RESERVED 0
489#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 489#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
490 490
491#define S_MC_CAS_SELECT 5 491#define S_MC_CAS_SELECT 5
492#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 492#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT)
493#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 493#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
494 494
495#define S_MC_CAS_MBZ 23 495#define S_MC_CAS_MBZ 23
496#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 496#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ)
497 497
498 498
499/* 499/*
@@ -501,14 +501,14 @@
501 */ 501 */
502 502
503#define S_MC_BA_RESERVED 0 503#define S_MC_BA_RESERVED 0
504#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 504#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED)
505 505
506#define S_MC_BA_SELECT 5 506#define S_MC_BA_SELECT 5
507#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 507#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT)
508#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 508#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT)
509 509
510#define S_MC_BA_MBZ 25 510#define S_MC_BA_MBZ 25
511#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 511#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ)
512 512
513/* 513/*
514 * Chip Select Attribute Register (Table 6-23) 514 * Chip Select Attribute Register (Table 6-23)
@@ -520,31 +520,31 @@
520#define K_MC_CS_ATTR_OPEN 3 520#define K_MC_CS_ATTR_OPEN 3
521 521
522#define S_MC_CS0_PAGE 0 522#define S_MC_CS0_PAGE 0
523#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 523#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE)
524#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 524#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
525#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 525#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
526 526
527#define S_MC_CS1_PAGE 16 527#define S_MC_CS1_PAGE 16
528#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 528#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE)
529#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 529#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
530#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 530#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
531 531
532#define S_MC_CS2_PAGE 32 532#define S_MC_CS2_PAGE 32
533#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 533#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE)
534#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 534#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
535#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 535#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
536 536
537#define S_MC_CS3_PAGE 48 537#define S_MC_CS3_PAGE 48
538#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 538#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE)
539#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 539#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
540#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 540#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
541 541
542/* 542/*
543 * ECC Test ECC Register (Table 6-25) 543 * ECC Test ECC Register (Table 6-25)
544 */ 544 */
545 545
546#define S_MC_ECC_INVERT 0 546#define S_MC_ECC_INVERT 0
547#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 547#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT)
548 548
549 549
550#endif 550#endif
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 220b7e94f1bf..8f53ec817a5e 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -66,7 +66,7 @@
66#define MC_REGISTER_SPACING 0x1000 66#define MC_REGISTER_SPACING 0x1000
67 67
68#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 68#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
69#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 69#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg))
70 70
71#define R_MC_CONFIG 0x0000000100 71#define R_MC_CONFIG 0x0000000100
72#define R_MC_DRAMCMD 0x0000000120 72#define R_MC_DRAMCMD 0x0000000120
@@ -173,23 +173,23 @@
173 173
174#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 174#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
175 175
176#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 176#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \
177 ((A_MAC_CHANNEL_BASE(macnum)) + \ 177 ((A_MAC_CHANNEL_BASE(macnum)) + \
178 R_MAC_DMA_CHANNELS + \ 178 R_MAC_DMA_CHANNELS + \
179 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 179 (MAC_DMA_TXRX_SPACING*(txrx)) + \
180 (MAC_DMA_CHANNEL_SPACING*(chan))) 180 (MAC_DMA_CHANNEL_SPACING*(chan)))
181 181
182#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 182#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \
183 (R_MAC_DMA_CHANNELS + \ 183 (R_MAC_DMA_CHANNELS + \
184 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 184 (MAC_DMA_TXRX_SPACING*(txrx)) + \
185 (MAC_DMA_CHANNEL_SPACING*(chan))) 185 (MAC_DMA_CHANNEL_SPACING*(chan)))
186 186
187#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 187#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \
188 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 188 (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \
189 (reg)) 189 (reg))
190 190
191#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 191#define R_MAC_DMA_REGISTER(txrx, chan, reg) \
192 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 192 (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \
193 (reg)) 193 (reg))
194 194
195/* 195/*
@@ -415,8 +415,8 @@
415 R_SER_DMA_CHANNELS + \ 415 R_SER_DMA_CHANNELS + \
416 (SER_DMA_TXRX_SPACING*(txrx))) 416 (SER_DMA_TXRX_SPACING*(txrx)))
417 417
418#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 418#define A_SER_DMA_REGISTER(sernum, txrx, reg) \
419 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 419 (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \
420 (reg)) 420 (reg))
421 421
422 422
@@ -499,7 +499,7 @@
499 499
500#define IO_EXT_REGISTER_SPACING 8 500#define IO_EXT_REGISTER_SPACING 8
501#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 501#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
502#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 502#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg))
503 503
504#define R_IO_EXT_CFG 0x0000 504#define R_IO_EXT_CFG 0x0000
505#define R_IO_EXT_MULT_SIZE 0x0100 505#define R_IO_EXT_MULT_SIZE 0x0100
@@ -587,7 +587,7 @@
587#define A_SMB_1 0x0010060008 587#define A_SMB_1 0x0010060008
588#define SMB_REGISTER_SPACING 0x8 588#define SMB_REGISTER_SPACING 0x8
589#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 589#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
590#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 590#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg))
591 591
592#define R_SMB_XTRA 0x0000000000 592#define R_SMB_XTRA 0x0000000000
593#define R_SMB_FREQ 0x0000000010 593#define R_SMB_FREQ 0x0000000010
@@ -611,7 +611,7 @@
611#define SCD_WDOG_SPACING 0x100 611#define SCD_WDOG_SPACING 0x100
612#define SCD_NUM_WDOGS 2 612#define SCD_NUM_WDOGS 2
613#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 613#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
614#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 614#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r))
615 615
616#define R_SCD_WDOG_INIT 0x0000000000 616#define R_SCD_WDOG_INIT 0x0000000000
617#define R_SCD_WDOG_CNT 0x0000000008 617#define R_SCD_WDOG_CNT 0x0000000008
@@ -635,7 +635,7 @@
635#define A_SCD_TIMER_3 0x0010020178 635#define A_SCD_TIMER_3 0x0010020178
636#define SCD_NUM_TIMERS 4 636#define SCD_NUM_TIMERS 4
637#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 637#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
638#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 638#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r))
639 639
640#define R_SCD_TIMER_INIT 0x0000000000 640#define R_SCD_TIMER_INIT 0x0000000000
641#define R_SCD_TIMER_CNT 0x0000000010 641#define R_SCD_TIMER_CNT 0x0000000010
@@ -714,7 +714,7 @@
714#define IMR_REGISTER_SPACING_SHIFT 13 714#define IMR_REGISTER_SPACING_SHIFT 13
715 715
716#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 716#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
717#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 717#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
718 718
719#define R_IMR_INTERRUPT_DIAG 0x0010 719#define R_IMR_INTERRUPT_DIAG 0x0010
720#define R_IMR_INTERRUPT_LDT 0x0018 720#define R_IMR_INTERRUPT_LDT 0x0018
@@ -821,7 +821,7 @@
821#define DM_REGISTER_SPACING 0x20 821#define DM_REGISTER_SPACING 0x20
822#define DM_NUM_CHANNELS 4 822#define DM_NUM_CHANNELS 4
823#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 823#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
824#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 824#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
825 825
826#define R_DM_DSCR_BASE 0x0000000000 826#define R_DM_DSCR_BASE 0x0000000000
827#define R_DM_DSCR_COUNT 0x0000000008 827#define R_DM_DSCR_COUNT 0x0000000008
@@ -843,7 +843,7 @@
843#define DM_CRC_REGISTER_SPACING 0x10 843#define DM_CRC_REGISTER_SPACING 0x10
844#define DM_CRC_NUM_CHANNELS 2 844#define DM_CRC_NUM_CHANNELS 2
845#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 845#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
846#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) 846#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg))
847 847
848#define R_CRC_DEF_0 0x00 848#define R_CRC_DEF_0 0x00
849#define R_CTCP_DEF_0 0x08 849#define R_CTCP_DEF_0 0x08
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index 9ea3da367ab6..e49c3e89b5ee 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -42,12 +42,12 @@
42 * System Revision Register (Table 4-1) 42 * System Revision Register (Table 4-1)
43 */ 43 */
44 44
45#define M_SYS_RESERVED _SB_MAKEMASK(8,0) 45#define M_SYS_RESERVED _SB_MAKEMASK(8, 0)
46 46
47#define S_SYS_REVISION _SB_MAKE64(8) 47#define S_SYS_REVISION _SB_MAKE64(8)
48#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 48#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION)
49#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 49#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION)
50#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 50#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
51 51
52#define K_SYS_REVISION_BCM1250_PASS1 0x01 52#define K_SYS_REVISION_BCM1250_PASS1 0x01
53 53
@@ -94,9 +94,9 @@
94 94
95/*Cache size - 23:20 of revision register*/ 95/*Cache size - 23:20 of revision register*/
96#define S_SYS_L2C_SIZE _SB_MAKE64(20) 96#define S_SYS_L2C_SIZE _SB_MAKE64(20)
97#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) 97#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
98#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) 98#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
99#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) 99#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
100 100
101#define K_SYS_L2C_SIZE_1MB 0 101#define K_SYS_L2C_SIZE_1MB 0
102#define K_SYS_L2C_SIZE_512KB 5 102#define K_SYS_L2C_SIZE_512KB 5
@@ -110,16 +110,16 @@
110 110
111/* Number of CPU cores, bits 27:24 of revision register*/ 111/* Number of CPU cores, bits 27:24 of revision register*/
112#define S_SYS_NUM_CPUS _SB_MAKE64(24) 112#define S_SYS_NUM_CPUS _SB_MAKE64(24)
113#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) 113#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
114#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) 114#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
115#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) 115#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
116 116
117 117
118/* XXX: discourage people from using these constants. */ 118/* XXX: discourage people from using these constants. */
119#define S_SYS_PART _SB_MAKE64(16) 119#define S_SYS_PART _SB_MAKE64(16)
120#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 120#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART)
121#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 121#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART)
122#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 122#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
123 123
124/* XXX: discourage people from using these constants. */ 124/* XXX: discourage people from using these constants. */
125#define K_SYS_PART_SB1250 0x1250 125#define K_SYS_PART_SB1250 0x1250
@@ -131,9 +131,9 @@
131 131
132/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 132/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
133#define S_SYS_SOC_TYPE _SB_MAKE64(16) 133#define S_SYS_SOC_TYPE _SB_MAKE64(16)
134#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 134#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
135#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 135#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
136#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 136#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
137 137
138#define K_SYS_SOC_TYPE_BCM1250 0x0 138#define K_SYS_SOC_TYPE_BCM1250 0x0
139#define K_SYS_SOC_TYPE_BCM1120 0x1 139#define K_SYS_SOC_TYPE_BCM1120 0x1
@@ -170,9 +170,9 @@
170#endif 170#endif
171 171
172#define S_SYS_WID _SB_MAKE64(32) 172#define S_SYS_WID _SB_MAKE64(32)
173#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 173#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID)
174#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 174#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID)
175#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 175#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
176 176
177/* 177/*
178 * System Manufacturing Register 178 * System Manufacturing Register
@@ -182,36 +182,36 @@
182#if SIBYTE_HDR_FEATURE_1250_112x 182#if SIBYTE_HDR_FEATURE_1250_112x
183/* Wafer ID: bits 31:0 */ 183/* Wafer ID: bits 31:0 */
184#define S_SYS_WAFERID1_200 _SB_MAKE64(0) 184#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
185#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 185#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
186#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 186#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
187#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 187#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
188 188
189#define S_SYS_BIN _SB_MAKE64(32) 189#define S_SYS_BIN _SB_MAKE64(32)
190#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 190#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN)
191#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) 191#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN)
192#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 192#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
193 193
194/* Wafer ID: bits 39:36 */ 194/* Wafer ID: bits 39:36 */
195#define S_SYS_WAFERID2_200 _SB_MAKE64(36) 195#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
196#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 196#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
197#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 197#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
198#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 198#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
199 199
200/* Wafer ID: bits 39:0 */ 200/* Wafer ID: bits 39:0 */
201#define S_SYS_WAFERID_300 _SB_MAKE64(0) 201#define S_SYS_WAFERID_300 _SB_MAKE64(0)
202#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 202#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300)
203#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 203#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
204#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 204#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
205 205
206#define S_SYS_XPOS _SB_MAKE64(40) 206#define S_SYS_XPOS _SB_MAKE64(40)
207#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 207#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS)
208#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 208#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS)
209#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 209#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
210 210
211#define S_SYS_YPOS _SB_MAKE64(46) 211#define S_SYS_YPOS _SB_MAKE64(46)
212#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 212#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS)
213#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 213#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS)
214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 214#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
215#endif 215#endif
216 216
217 217
@@ -227,9 +227,9 @@
227#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 227#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
228 228
229#define S_SYS_PLL_DIV _SB_MAKE64(7) 229#define S_SYS_PLL_DIV _SB_MAKE64(7)
230#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 230#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV)
231#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 231#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
232#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 232#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
233 233
234#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 234#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
235#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 235#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
@@ -238,9 +238,9 @@
238#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 238#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
239 239
240#define S_SYS_BOOT_MODE _SB_MAKE64(17) 240#define S_SYS_BOOT_MODE _SB_MAKE64(17)
241#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 241#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
242#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 242#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
243#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 243#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
244#define K_SYS_BOOT_MODE_ROM32 0 244#define K_SYS_BOOT_MODE_ROM32 0
245#define K_SYS_BOOT_MODE_ROM8 1 245#define K_SYS_BOOT_MODE_ROM8 1
246#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 246#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
@@ -255,9 +255,9 @@
255#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 255#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
256 256
257#define S_SYS_CONFIG 26 257#define S_SYS_CONFIG 26
258#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 258#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG)
259#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 259#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG)
260#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 260#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
261 261
262/* The following bits are writeable by JTAG only. */ 262/* The following bits are writeable by JTAG only. */
263 263
@@ -265,20 +265,20 @@
265#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 265#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
266 266
267#define S_SYS_CLKCOUNT 34 267#define S_SYS_CLKCOUNT 34
268#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 268#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
269#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 269#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
270#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 270#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
271 271
272#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 272#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
273 273
274#define S_SYS_PLL_IREF 43 274#define S_SYS_PLL_IREF 43
275#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 275#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF)
276 276
277#define S_SYS_PLL_VCO 45 277#define S_SYS_PLL_VCO 45
278#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 278#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO)
279 279
280#define S_SYS_PLL_VREG 47 280#define S_SYS_PLL_VREG 47
281#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 281#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG)
282 282
283#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 283#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
284#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 284#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
@@ -314,13 +314,13 @@
314 */ 314 */
315 315
316#define S_MBOX_INT_3 0 316#define S_MBOX_INT_3 0
317#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 317#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3)
318#define S_MBOX_INT_2 16 318#define S_MBOX_INT_2 16
319#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 319#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2)
320#define S_MBOX_INT_1 32 320#define S_MBOX_INT_1 32
321#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 321#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1)
322#define S_MBOX_INT_0 48 322#define S_MBOX_INT_0 48
323#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 323#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0)
324 324
325/* 325/*
326 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 326 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
@@ -330,18 +330,18 @@
330#define V_SCD_WDOG_FREQ 1000000 330#define V_SCD_WDOG_FREQ 1000000
331 331
332#define S_SCD_WDOG_INIT 0 332#define S_SCD_WDOG_INIT 0
333#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 333#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
334 334
335#define S_SCD_WDOG_CNT 0 335#define S_SCD_WDOG_CNT 0
336#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 336#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
337 337
338#define S_SCD_WDOG_ENABLE 0 338#define S_SCD_WDOG_ENABLE 0
339#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) 339#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
340 340
341#define S_SCD_WDOG_RESET_TYPE 2 341#define S_SCD_WDOG_RESET_TYPE 2
342#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) 342#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
343#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) 343#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
344#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) 344#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
345 345
346#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 346#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
347#define K_SCD_WDOG_RESET_SOFT 1 347#define K_SCD_WDOG_RESET_SOFT 1
@@ -363,15 +363,15 @@
363#define V_SCD_TIMER_FREQ 1000000 363#define V_SCD_TIMER_FREQ 1000000
364 364
365#define S_SCD_TIMER_INIT 0 365#define S_SCD_TIMER_INIT 0
366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) 366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
369 369
370#define V_SCD_TIMER_WIDTH 23 370#define V_SCD_TIMER_WIDTH 23
371#define S_SCD_TIMER_CNT 0 371#define S_SCD_TIMER_CNT 0
372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
374#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 374#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
375 375
376#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 376#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
377#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 377#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
@@ -382,24 +382,24 @@
382 */ 382 */
383 383
384#define S_SPC_CFG_SRC0 0 384#define S_SPC_CFG_SRC0 0
385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
387#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 387#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
388 388
389#define S_SPC_CFG_SRC1 8 389#define S_SPC_CFG_SRC1 8
390#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 390#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
391#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 391#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
392#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 392#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
393 393
394#define S_SPC_CFG_SRC2 16 394#define S_SPC_CFG_SRC2 16
395#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 395#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
396#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 396#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
397#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 397#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
398 398
399#define S_SPC_CFG_SRC3 24 399#define S_SPC_CFG_SRC3 24
400#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 400#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
403 403
404#if SIBYTE_HDR_FEATURE_1250_112x 404#if SIBYTE_HDR_FEATURE_1250_112x
405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
@@ -412,57 +412,57 @@
412 */ 412 */
413 413
414#define S_SCD_BERR_TID 8 414#define S_SCD_BERR_TID 8
415#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 415#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID)
416#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 416#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID)
417#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 417#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
418 418
419#define S_SCD_BERR_RID 18 419#define S_SCD_BERR_RID 18
420#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 420#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID)
421#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 421#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID)
422#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 422#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
423 423
424#define S_SCD_BERR_DCODE 22 424#define S_SCD_BERR_DCODE 22
425#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 425#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
426#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 426#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
427#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 427#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
428 428
429#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 429#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
430 430
431 431
432#define S_SCD_L2ECC_CORR_D 0 432#define S_SCD_L2ECC_CORR_D 0
433#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 433#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
434#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 434#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
435#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 435#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
436 436
437#define S_SCD_L2ECC_BAD_D 8 437#define S_SCD_L2ECC_BAD_D 8
438#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 438#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
439#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 439#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
440#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 440#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
441 441
442#define S_SCD_L2ECC_CORR_T 16 442#define S_SCD_L2ECC_CORR_T 16
443#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 443#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
444#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 444#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
445#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 445#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
446 446
447#define S_SCD_L2ECC_BAD_T 24 447#define S_SCD_L2ECC_BAD_T 24
448#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 448#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
449#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 449#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
450#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 450#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
451 451
452#define S_SCD_MEM_ECC_CORR 0 452#define S_SCD_MEM_ECC_CORR 0
453#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 453#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
454#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 454#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
455#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 455#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
456 456
457#define S_SCD_MEM_ECC_BAD 8 457#define S_SCD_MEM_ECC_BAD 8
458#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 458#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
459#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 459#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
460#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 460#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
461 461
462#define S_SCD_MEM_BUSERR 16 462#define S_SCD_MEM_BUSERR 16
463#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 463#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
464#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 464#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
465#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 465#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
466 466
467 467
468/* 468/*
@@ -470,13 +470,13 @@
470 */ 470 */
471 471
472#if SIBYTE_HDR_FEATURE_1250_112x 472#if SIBYTE_HDR_FEATURE_1250_112x
473#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 473#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0)
474#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 474#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
475 475
476#define S_ATRAP_CFG_CNT 0 476#define S_ATRAP_CFG_CNT 0
477#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 477#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
478#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 478#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
479#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 479#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
480 480
481#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 481#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
482#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 482#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
@@ -485,9 +485,9 @@
485#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 485#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
486 486
487#define S_ATRAP_CFG_AGENTID 8 487#define S_ATRAP_CFG_AGENTID 8
488#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 488#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
489#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 489#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
490#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 490#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
491 491
492#define K_BUS_AGENT_CPU0 0 492#define K_BUS_AGENT_CPU0 0
493#define K_BUS_AGENT_CPU1 1 493#define K_BUS_AGENT_CPU1 1
@@ -498,9 +498,9 @@
498#define K_BUS_AGENT_MC 7 498#define K_BUS_AGENT_MC 7
499 499
500#define S_ATRAP_CFG_CATTR 12 500#define S_ATRAP_CFG_CATTR 12
501#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 501#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
502#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 502#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
503#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 503#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
504 504
505#define K_ATRAP_CFG_CATTR_IGNORE 0 505#define K_ATRAP_CFG_CATTR_IGNORE 0
506#define K_ATRAP_CFG_CATTR_UNC 1 506#define K_ATRAP_CFG_CATTR_UNC 1
@@ -541,18 +541,18 @@
541#endif /* 1480 */ 541#endif /* 1480 */
542#endif /* 1250/112x */ 542#endif /* 1250/112x */
543 543
544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
547 547
548/* 548/*
549 * Trace Event registers 549 * Trace Event registers
550 */ 550 */
551 551
552#define S_SCD_TREVT_ADDR_MATCH 0 552#define S_SCD_TREVT_ADDR_MATCH 0
553#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 553#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
554#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 554#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
555#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 555#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
556 556
557#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 557#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
558#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 558#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
@@ -563,48 +563,48 @@
563#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 563#define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
564 564
565#define S_SCD_TREVT_REQID 12 565#define S_SCD_TREVT_REQID 12
566#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 566#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
567#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 567#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
568#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 568#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
569 569
570#define S_SCD_TREVT_RESPID 16 570#define S_SCD_TREVT_RESPID 16
571#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 571#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
572#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 572#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
573#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 573#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
574 574
575#define S_SCD_TREVT_DATAID 20 575#define S_SCD_TREVT_DATAID 20
576#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 576#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
577#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 577#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
578#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 578#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
579 579
580#define S_SCD_TREVT_COUNT 24 580#define S_SCD_TREVT_COUNT 24
581#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 581#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
582#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 582#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
583#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 583#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
584 584
585/* 585/*
586 * Trace Sequence registers 586 * Trace Sequence registers
587 */ 587 */
588 588
589#define S_SCD_TRSEQ_EVENT4 0 589#define S_SCD_TRSEQ_EVENT4 0
590#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 590#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
591#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 591#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
592#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 592#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
593 593
594#define S_SCD_TRSEQ_EVENT3 4 594#define S_SCD_TRSEQ_EVENT3 4
595#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 595#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
596#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 596#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
597#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 597#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
598 598
599#define S_SCD_TRSEQ_EVENT2 8 599#define S_SCD_TRSEQ_EVENT2 8
600#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 600#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
601#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 601#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
602#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 602#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
603 603
604#define S_SCD_TRSEQ_EVENT1 12 604#define S_SCD_TRSEQ_EVENT1 12
605#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 605#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
606#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 606#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
607#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 607#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
608 608
609#define K_SCD_TRSEQ_E0 0 609#define K_SCD_TRSEQ_E0 0
610#define K_SCD_TRSEQ_E1 1 610#define K_SCD_TRSEQ_E1 1
@@ -629,9 +629,9 @@
629 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 629 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
630 630
631#define S_SCD_TRSEQ_FUNCTION 16 631#define S_SCD_TRSEQ_FUNCTION 16
632#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 632#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
633#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 633#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
634#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 634#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
635 635
636#define K_SCD_TRSEQ_FUNC_NOP 0 636#define K_SCD_TRSEQ_FUNC_NOP 0
637#define K_SCD_TRSEQ_FUNC_START 1 637#define K_SCD_TRSEQ_FUNC_START 1
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 279a912213cd..04769923cf1e 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -41,16 +41,16 @@
41 */ 41 */
42 42
43#define S_SMB_FREQ_DIV 0 43#define S_SMB_FREQ_DIV 0
44#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV) 44#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
45#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV) 45#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
46 46
47#define K_SMB_FREQ_400KHZ 0x1F 47#define K_SMB_FREQ_400KHZ 0x1F
48#define K_SMB_FREQ_100KHZ 0x7D 48#define K_SMB_FREQ_100KHZ 0x7D
49#define K_SMB_FREQ_10KHZ 1250 49#define K_SMB_FREQ_10KHZ 1250
50 50
51#define S_SMB_CMD 0 51#define S_SMB_CMD 0
52#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) 52#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD)
53#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD) 53#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD)
54 54
55/* 55/*
56 * SMBus control register (Table 14-4) 56 * SMBus control register (Table 14-4)
@@ -61,7 +61,7 @@
61 61
62#define S_SMB_DATA_OUT 4 62#define S_SMB_DATA_OUT 4
63#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) 63#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
64#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) 64#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
65 65
66#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) 66#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
67#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR 67#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
@@ -79,35 +79,35 @@
79#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 79#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
80#define S_SMB_SCL_IN 5 80#define S_SMB_SCL_IN 5
81#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) 81#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
82#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) 82#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN)
83#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) 83#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
84#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 84#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
85 85
86#define S_SMB_REF 6 86#define S_SMB_REF 6
87#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) 87#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
88#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) 88#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF)
89#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) 89#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
90 90
91#define S_SMB_DATA_IN 7 91#define S_SMB_DATA_IN 7
92#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) 92#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
93#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) 93#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN)
94#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) 94#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
95 95
96/* 96/*
97 * SMBus Start/Command registers (Table 14-9) 97 * SMBus Start/Command registers (Table 14-9)
98 */ 98 */
99 99
100#define S_SMB_ADDR 0 100#define S_SMB_ADDR 0
101#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR) 101#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR)
102#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR) 102#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR)
103#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR) 103#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
104 104
105#define M_SMB_QDATA _SB_MAKEMASK1(7) 105#define M_SMB_QDATA _SB_MAKEMASK1(7)
106 106
107#define S_SMB_TT 8 107#define S_SMB_TT 8
108#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT) 108#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT)
109#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT) 109#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT)
110#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT) 110#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
111 111
112#define K_SMB_TT_WR1BYTE 0 112#define K_SMB_TT_WR1BYTE 0
113#define K_SMB_TT_WR2BYTE 1 113#define K_SMB_TT_WR2BYTE 1
@@ -134,12 +134,12 @@
134 */ 134 */
135 135
136#define S_SMB_LB 0 136#define S_SMB_LB 0
137#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB) 137#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB)
138#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB) 138#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB)
139 139
140#define S_SMB_MB 8 140#define S_SMB_MB 8
141#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB) 141#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB)
142#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB) 142#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB)
143 143
144 144
145/* 145/*
@@ -147,22 +147,22 @@
147 */ 147 */
148 148
149#define S_SPEC_PEC 0 149#define S_SPEC_PEC 0
150#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC) 150#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC)
151#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) 151#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC)
152 152
153 153
154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
155 155
156#define S_SMB_CMDH 8 156#define S_SMB_CMDH 8
157#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) 157#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH)
158#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) 158#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH)
159 159
160#define M_SMB_EXTEND _SB_MAKEMASK1(14) 160#define M_SMB_EXTEND _SB_MAKEMASK1(14)
161 161
162#define S_SMB_DFMT 8 162#define S_SMB_DFMT 8
163#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) 163#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT)
164#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) 164#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT)
165#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT) 165#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
166 166
167#define K_SMB_DFMT_1BYTE 0 167#define K_SMB_DFMT_1BYTE 0
168#define K_SMB_DFMT_2BYTE 1 168#define K_SMB_DFMT_2BYTE 1
@@ -183,9 +183,9 @@
183#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) 183#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
184 184
185#define S_SMB_AFMT 11 185#define S_SMB_AFMT 11
186#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) 186#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT)
187#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) 187#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT)
188#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) 188#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
189 189
190#define K_SMB_AFMT_NONE 0 190#define K_SMB_AFMT_NONE 0
191#define K_SMB_AFMT_ADDR 1 191#define K_SMB_AFMT_ADDR 1
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index dd154ac505d8..d4b8558e0bf1 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -43,8 +43,8 @@
43#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) 43#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1)
44 44
45#define S_SYNCSER_FLAG_NUM 2 45#define S_SYNCSER_FLAG_NUM 2
46#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM) 46#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
47#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM) 47#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
48 48
49#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) 49#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6)
50#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) 50#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7)
@@ -59,8 +59,8 @@
59#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) 59#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1)
60 60
61#define S_SYNCSER_RXSYNC_DLY 2 61#define S_SYNCSER_RXSYNC_DLY 2
62#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY) 62#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
63#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY) 63#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
64 64
65#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) 65#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4)
66#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) 66#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5)
@@ -72,8 +72,8 @@
72#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) 72#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9)
73 73
74#define S_SYNCSER_TXSYNC_DLY 10 74#define S_SYNCSER_TXSYNC_DLY 10
75#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY) 75#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
76#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY) 76#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
77 77
78#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) 78#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12)
79#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) 79#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13)
@@ -137,8 +137,8 @@
137#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) 137#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1)
138 138
139#define S_SYNCSER_SEQ_COUNT 2 139#define S_SYNCSER_SEQ_COUNT 2
140#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT) 140#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
141#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT) 141#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
142 142
143#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) 143#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6)
144#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) 144#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7)
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index cf74fedcbef1..d835bf280140 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -46,8 +46,8 @@
46 */ 46 */
47 47
48#define S_DUART_BITS_PER_CHAR 0 48#define S_DUART_BITS_PER_CHAR 0
49#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) 49#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
50#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) 50#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
51 51
52#define K_DUART_BITS_PER_CHAR_RSV0 0 52#define K_DUART_BITS_PER_CHAR_RSV0 0
53#define K_DUART_BITS_PER_CHAR_RSV1 1 53#define K_DUART_BITS_PER_CHAR_RSV1 1
@@ -64,8 +64,8 @@
64#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 64#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
65 65
66#define S_DUART_PARITY_MODE 3 66#define S_DUART_PARITY_MODE 3
67#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) 67#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
68#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) 68#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
69 69
70#define K_DUART_PARITY_MODE_ADD 0 70#define K_DUART_PARITY_MODE_ADD 0
71#define K_DUART_PARITY_MODE_ADD_FIXED 1 71#define K_DUART_PARITY_MODE_ADD_FIXED 1
@@ -89,7 +89,7 @@
89 * Register: DUART_MODE_REG_2_B 89 * Register: DUART_MODE_REG_2_B
90 */ 90 */
91 91
92#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ 92#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */
93 93
94#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 94#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
95#define M_DUART_STOP_BIT_LEN_1 0 95#define M_DUART_STOP_BIT_LEN_1 0
@@ -100,8 +100,8 @@
100#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 100#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
101 101
102#define S_DUART_CHAN_MODE 6 102#define S_DUART_CHAN_MODE 6
103#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) 103#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
104#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) 104#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
105 105
106#define K_DUART_CHAN_MODE_NORMAL 0 106#define K_DUART_CHAN_MODE_NORMAL 0
107#define K_DUART_CHAN_MODE_LCL_LOOP 2 107#define K_DUART_CHAN_MODE_LCL_LOOP 2
@@ -123,8 +123,8 @@
123#define M_DUART_TX_DIS _SB_MAKEMASK1(3) 123#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
124 124
125#define S_DUART_MISC_CMD 4 125#define S_DUART_MISC_CMD 4
126#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) 126#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD)
127#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) 127#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
128 128
129#define K_DUART_MISC_CMD_NOACTION0 0 129#define K_DUART_MISC_CMD_NOACTION0 0
130#define K_DUART_MISC_CMD_NOACTION1 1 130#define K_DUART_MISC_CMD_NOACTION1 1
@@ -168,7 +168,7 @@
168 * Register: DUART_CLK_SEL_B 168 * Register: DUART_CLK_SEL_B
169 */ 169 */
170 170
171#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) 171#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0)
172#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 172#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
173 173
174/* 174/*
@@ -179,8 +179,8 @@
179 * Register: DUART_TX_HOLD_B 179 * Register: DUART_TX_HOLD_B
180 */ 180 */
181 181
182#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) 182#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0)
183#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) 183#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0)
184 184
185/* 185/*
186 * DUART Input Port Register (Table 10-10) 186 * DUART Input Port Register (Table 10-10)
@@ -202,10 +202,10 @@
202 */ 202 */
203 203
204#define S_DUART_IN_PIN_VAL 0 204#define S_DUART_IN_PIN_VAL 0
205#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) 205#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
206 206
207#define S_DUART_IN_PIN_CHNG 4 207#define S_DUART_IN_PIN_CHNG 4
208#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) 208#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
209 209
210 210
211/* 211/*
@@ -217,7 +217,7 @@
217#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 217#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
218#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 218#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
219#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 219#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
220#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ 220#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */
221 221
222/* 222/*
223 * DUART Aux Control Register (Table 10-15) 223 * DUART Aux Control Register (Table 10-15)
@@ -228,7 +228,7 @@
228#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 228#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
229#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 229#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
230#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 230#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
231#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) 231#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4)
232 232
233#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 233#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
234#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 234#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
@@ -242,18 +242,18 @@
242 242
243#define S_DUART_ISR_RX_A 1 243#define S_DUART_ISR_RX_A 1
244#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) 244#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
245#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) 245#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
246#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) 246#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
247 247
248#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 248#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
249#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 249#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
250#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) 250#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0)
251 251
252#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 252#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
253#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 253#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
254#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 254#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
255#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 255#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
256#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) 256#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4)
257 257
258/* 258/*
259 * DUART Channel A Interrupt Status Register (Table 10-17) 259 * DUART Channel A Interrupt Status Register (Table 10-17)
@@ -266,8 +266,8 @@
266#define M_DUART_ISR_RX _SB_MAKEMASK1(1) 266#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
267#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 267#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
268#define M_DUART_ISR_IN _SB_MAKEMASK1(3) 268#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
269#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) 269#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0)
270#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) 270#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4)
271 271
272/* 272/*
273 * DUART Interrupt Mask Register (Table 10-19) 273 * DUART Interrupt Mask Register (Table 10-19)
@@ -278,13 +278,13 @@
278#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 278#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
279#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 279#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
280#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 280#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
281#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) 281#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0)
282 282
283#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 283#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
284#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 284#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
285#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 285#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
286#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 286#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
287#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) 287#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4)
288 288
289/* 289/*
290 * DUART Channel A Interrupt Mask Register (Table 10-20) 290 * DUART Channel A Interrupt Mask Register (Table 10-20)
@@ -297,8 +297,8 @@
297#define M_DUART_IMR_RX _SB_MAKEMASK1(1) 297#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
298#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 298#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
299#define M_DUART_IMR_IN _SB_MAKEMASK1(3) 299#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
300#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) 300#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0)
301#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) 301#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4)
302 302
303 303
304/* 304/*
@@ -310,7 +310,7 @@
310#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 310#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
311#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 311#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
312#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 312#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
313#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) 313#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4)
314 314
315/* 315/*
316 * DUART Output Port Clear Register (Table 10-23) 316 * DUART Output Port Clear Register (Table 10-23)
@@ -321,7 +321,7 @@
321#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 321#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
322#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 322#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
323#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 323#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
324#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) 324#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4)
325 325
326/* 326/*
327 * DUART Output Port RTS Register (Table 10-24) 327 * DUART Output Port RTS Register (Table 10-24)
@@ -332,7 +332,7 @@
332#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 332#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
333#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 333#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
334#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 334#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
335#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) 335#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4)
336 336
337#define M_DUART_OUT_PIN_SET(chan) \ 337#define M_DUART_OUT_PIN_SET(chan) \
338 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 338 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
@@ -345,14 +345,14 @@
345 */ 345 */
346 346
347#define S_DUART_SIG_FULL _SB_MAKE64(0) 347#define S_DUART_SIG_FULL _SB_MAKE64(0)
348#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) 348#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL)
349#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) 349#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
350#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) 350#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
351 351
352#define S_DUART_INT_TIME _SB_MAKE64(4) 352#define S_DUART_INT_TIME _SB_MAKE64(4)
353#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) 353#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME)
354#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) 354#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME)
355#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) 355#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
356#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 356#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
357 357
358 358
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index 2e32949bd674..96e28f18dad1 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -106,8 +106,8 @@ typedef struct siginfo {
106#undef SI_TIMER 106#undef SI_TIMER
107#undef SI_MESGQ 107#undef SI_MESGQ
108#define SI_ASYNCIO -2 /* sent by AIO completion */ 108#define SI_ASYNCIO -2 /* sent by AIO completion */
109#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ 109#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */
110#define SI_MESGQ __SI_CODE(__SI_MESGQ,-4) /* sent by real time mesq state change */ 110#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */
111 111
112#ifdef __KERNEL__ 112#ifdef __KERNEL__
113 113
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index 67c4fe52bb42..0cd719fabb51 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -18,7 +18,7 @@
18#ifdef CONFIG_32BIT 18#ifdef CONFIG_32BIT
19 19
20#define save_static_function(symbol) \ 20#define save_static_function(symbol) \
21__asm__ ( \ 21__asm__( \
22 ".text\n\t" \ 22 ".text\n\t" \
23 ".globl\t" #symbol "\n\t" \ 23 ".globl\t" #symbol "\n\t" \
24 ".align\t2\n\t" \ 24 ".align\t2\n\t" \
@@ -46,7 +46,7 @@ __asm__ ( \
46#ifdef CONFIG_64BIT 46#ifdef CONFIG_64BIT
47 47
48#define save_static_function(symbol) \ 48#define save_static_function(symbol) \
49__asm__ ( \ 49__asm__( \
50 ".text\n\t" \ 50 ".text\n\t" \
51 ".globl\t" #symbol "\n\t" \ 51 ".globl\t" #symbol "\n\t" \
52 ".align\t2\n\t" \ 52 ".align\t2\n\t" \
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 13aef6af422c..dc770025a9b0 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -60,6 +60,15 @@ extern cpumask_t phys_cpu_present_map;
60 */ 60 */
61extern void core_send_ipi(int cpu, unsigned int action); 61extern void core_send_ipi(int cpu, unsigned int action);
62 62
63static inline void core_send_ipi_mask(cpumask_t mask, unsigned int action)
64{
65 unsigned int i;
66
67 for_each_cpu_mask(i, mask)
68 core_send_ipi(i, action);
69}
70
71
63/* 72/*
64 * Firmware CPU startup hook 73 * Firmware CPU startup hook
65 */ 74 */
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h
index a52a4a7a36e0..e09131a6127d 100644
--- a/include/asm-mips/smtc_ipi.h
+++ b/include/asm-mips/smtc_ipi.h
@@ -34,6 +34,7 @@ struct smtc_ipi {
34 34
35#define LINUX_SMP_IPI 1 35#define LINUX_SMP_IPI 1
36#define SMTC_CLOCK_TICK 2 36#define SMTC_CLOCK_TICK 2
37#define IRQ_AFFINITY_IPI 3
37 38
38/* 39/*
39 * A queue of IPI messages 40 * A queue of IPI messages
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
index 8fa0af6b68d2..fec9bdd34913 100644
--- a/include/asm-mips/sn/addrs.h
+++ b/include/asm-mips/sn/addrs.h
@@ -50,7 +50,7 @@
50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) 50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
51 51
52#define CHANGE_ADDR_NASID(_pa, _nasid) \ 52#define CHANGE_ADDR_NASID(_pa, _nasid) \
53 ((UINT64_CAST (_pa) & ~NASID_MASK) | \ 53 ((UINT64_CAST(_pa) & ~NASID_MASK) | \
54 (UINT64_CAST(_nasid) << NASID_SHFT)) 54 (UINT64_CAST(_nasid) << NASID_SHFT))
55 55
56 56
@@ -75,7 +75,7 @@
75 75
76 76
77#define RAW_NODE_SWIN_BASE(nasid, widget) \ 77#define RAW_NODE_SWIN_BASE(nasid, widget) \
78 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 78 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
79 79
80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) 80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
81 81
@@ -192,31 +192,31 @@
192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ 192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
193 NODE_ADDRSPACE_SIZE * 3 / 4 + \ 193 NODE_ADDRSPACE_SIZE * 3 / 4 + \
194 0x200) | \ 194 0x200) | \
195 UINT64_CAST (_pa) & NASID_MASK | \ 195 UINT64_CAST(_pa) & NASID_MASK | \
196 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 196 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
197 UINT64_CAST (_pa) >> 3 & 0x1f << 4) 197 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
198 198
199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ 199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
200 NODE_ADDRSPACE_SIZE * 3 / 4 + \ 200 NODE_ADDRSPACE_SIZE * 3 / 4 + \
201 0x208) | \ 201 0x208) | \
202 UINT64_CAST (_pa) & NASID_MASK | \ 202 UINT64_CAST(_pa) & NASID_MASK | \
203 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 203 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
204 UINT64_CAST (_pa) >> 3 & 0x1f << 4) 204 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
205 205
206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ 206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
207 NODE_ADDRSPACE_SIZE * 3 / 4) | \ 207 NODE_ADDRSPACE_SIZE * 3 / 4) | \
208 UINT64_CAST (_pa) & NASID_MASK | \ 208 UINT64_CAST(_pa) & NASID_MASK | \
209 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 209 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
210 (_rgn) << 3) 210 (_rgn) << 3)
211#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) 211#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn)))
212#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) 212#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val))
213#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))) 213#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn)))
214 214
215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ 215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
216 NODE_ADDRSPACE_SIZE / 2) | \ 216 NODE_ADDRSPACE_SIZE / 2) | \
217 UINT64_CAST (_pa) & NASID_MASK | \ 217 UINT64_CAST(_pa) & NASID_MASK | \
218 UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \ 218 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \
219 UINT64_CAST (_pa) >> 3 & 3) 219 UINT64_CAST(_pa) >> 3 & 3)
220 220
221/* 221/*
222 * Macro to convert a back door directory or protection address into the 222 * Macro to convert a back door directory or protection address into the
@@ -225,16 +225,16 @@
225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) 225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) 226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
227 227
228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
229 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \ 229 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \
230 (UINT64_CAST (_ba) & 0x1f << 4) << 3) 230 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
231 231
232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
233 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2) 233 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
234 234
235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
236 (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \ 236 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \
237 (UINT64_CAST (_ba) & 3) << 3) 237 (UINT64_CAST(_ba) & 3) << 3)
238#endif /* CONFIG_SGI_IP27 */ 238#endif /* CONFIG_SGI_IP27 */
239 239
240 240
@@ -282,7 +282,7 @@
282 * the base of the register space. 282 * the base of the register space.
283 */ 283 */
284#define HUB_REG_PTR(_base, _off) \ 284#define HUB_REG_PTR(_base, _off) \
285 (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 285 (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
286 286
287#define HUB_REG_PTR_L(_base, _off) \ 287#define HUB_REG_PTR_L(_base, _off) \
288 HUB_L(HUB_REG_PTR((_base), (_off))) 288 HUB_L(HUB_REG_PTR((_base), (_off)))
diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h
index da523de628be..bd75945e10ff 100644
--- a/include/asm-mips/sn/arch.h
+++ b/include/asm-mips/sn/arch.h
@@ -19,8 +19,8 @@
19 19
20typedef u64 hubreg_t; 20typedef u64 hubreg_t;
21 21
22#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid) 22#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid)
23#define cputoslice(cpu) (cpu_data[(cpu)].p_slice) 23#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice)
24#define makespnum(_nasid, _slice) \ 24#define makespnum(_nasid, _slice) \
25 (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) 25 (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
26 26
diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h
index ab2fa8cd2627..24c6775fbb0f 100644
--- a/include/asm-mips/sn/io.h
+++ b/include/asm-mips/sn/io.h
@@ -9,7 +9,7 @@
9#ifndef _ASM_SN_IO_H 9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H 10#define _ASM_SN_IO_H
11 11
12#if defined (CONFIG_SGI_IP27) 12#if defined(CONFIG_SGI_IP27)
13#include <asm/sn/sn0/hubio.h> 13#include <asm/sn/sn0/hubio.h>
14#endif 14#endif
15 15
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
index 82aeb9e322db..96cfd2ab1bcd 100644
--- a/include/asm-mips/sn/klconfig.h
+++ b/include/asm-mips/sn/klconfig.h
@@ -51,8 +51,8 @@
51 51
52#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35) 52#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
53#include <asm/sn/agent.h> 53#include <asm/sn/agent.h>
54#include <asm/arc/types.h> 54#include <asm/fw/arc/types.h>
55#include <asm/arc/hinv.h> 55#include <asm/fw/arc/hinv.h>
56#if defined(CONFIG_SGI_IP35) 56#if defined(CONFIG_SGI_IP35)
57// The hack file has to be before vector and after sn0_fru.... 57// The hack file has to be before vector and after sn0_fru....
58#include <asm/hack.h> 58#include <asm/hack.h>
@@ -405,7 +405,7 @@ typedef struct kl_config_hdr {
405#define KLTYPE(_x) ((_x) & KLTYPE_MASK) 405#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
406#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ 406#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \
407 (l->brd_flags & SECOND_NIC_PRESENT)) 407 (l->brd_flags & SECOND_NIC_PRESENT))
408#define IS_MIO_IOC3(l,n) (IS_MIO_PRESENT(l) && (n > 2)) 408#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2))
409 409
410/* 410/*
411 * board structures 411 * board structures
diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h
index 0573cbffc104..1327e12e9645 100644
--- a/include/asm-mips/sn/kldir.h
+++ b/include/asm-mips/sn/kldir.h
@@ -140,7 +140,7 @@
140 */ 140 */
141#define SYMMON_STACK_SIZE 0x8000 141#define SYMMON_STACK_SIZE 0x8000
142 142
143#if defined (PROM) 143#if defined(PROM)
144 144
145/* 145/*
146 * These defines are prom version dependent. No code other than the IP27 146 * These defines are prom version dependent. No code other than the IP27
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
index 9e8cc52910f6..b06190093bbc 100644
--- a/include/asm-mips/sn/sn0/addrs.h
+++ b/include/asm-mips/sn/sn0/addrs.h
@@ -91,7 +91,7 @@
91 : RAW_NODE_SWIN_BASE(nasid, widget)) 91 : RAW_NODE_SWIN_BASE(nasid, widget))
92#else /* __ASSEMBLY__ */ 92#else /* __ASSEMBLY__ */
93#define NODE_SWIN_BASE(nasid, widget) \ 93#define NODE_SWIN_BASE(nasid, widget) \
94 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 94 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
95#endif /* __ASSEMBLY__ */ 95#endif /* __ASSEMBLY__ */
96 96
97/* 97/*
@@ -106,7 +106,7 @@
106#define BWIN_WIDGET_MASK 0x7 106#define BWIN_WIDGET_MASK 0x7
107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
109 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) 109 (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
110 110
111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
@@ -259,7 +259,7 @@
259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or 259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or
260 * the stack could start at CACHE_ERR_SP_PTR 260 * the stack could start at CACHE_ERR_SP_PTR
261 */ 261 */
262#if defined (HUB_ERR_STS_WAR) 262#if defined(HUB_ERR_STS_WAR)
263#define CACHE_ERR_EFRAME 0x480 263#define CACHE_ERR_EFRAME 0x480
264#else /* HUB_ERR_STS_WAR */ 264#else /* HUB_ERR_STS_WAR */
265#define CACHE_ERR_EFRAME 0x400 265#define CACHE_ERR_EFRAME 0x400
@@ -275,7 +275,7 @@
275 275
276#define _ARCSPROM 276#define _ARCSPROM
277 277
278#if defined (HUB_ERR_STS_WAR) 278#if defined(HUB_ERR_STS_WAR)
279 279
280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR 280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) 281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index ddaf36a1e389..4d43dbb7f8b8 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -194,17 +194,17 @@ extern unsigned int sni_brd_type;
194#define PCIMT_INT_ACKNOWLEDGE 0xba000000 194#define PCIMT_INT_ACKNOWLEDGE 0xba000000
195 195
196/* board specific init functions */ 196/* board specific init functions */
197extern void sni_a20r_init (void); 197extern void sni_a20r_init(void);
198extern void sni_pcit_init (void); 198extern void sni_pcit_init(void);
199extern void sni_rm200_init (void); 199extern void sni_rm200_init(void);
200extern void sni_pcimt_init (void); 200extern void sni_pcimt_init(void);
201 201
202/* board specific irq init functions */ 202/* board specific irq init functions */
203extern void sni_a20r_irq_init (void); 203extern void sni_a20r_irq_init(void);
204extern void sni_pcit_irq_init (void); 204extern void sni_pcit_irq_init(void);
205extern void sni_pcit_cplus_irq_init (void); 205extern void sni_pcit_cplus_irq_init(void);
206extern void sni_rm200_irq_init (void); 206extern void sni_rm200_irq_init(void);
207extern void sni_pcimt_irq_init (void); 207extern void sni_pcimt_irq_init(void);
208 208
209/* timer inits */ 209/* timer inits */
210extern void sni_cpu_time_init(void); 210extern void sni_cpu_time_init(void);
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index ed33366b85b8..fb41a8d76392 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -91,14 +91,14 @@
91#else 91#else
92 MFC0 k0, CP0_CONTEXT 92 MFC0 k0, CP0_CONTEXT
93#endif 93#endif
94#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) 94#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
95 lui k1, %hi(kernelsp)
96#else
95 lui k1, %highest(kernelsp) 97 lui k1, %highest(kernelsp)
96 daddiu k1, %higher(kernelsp) 98 daddiu k1, %higher(kernelsp)
97 dsll k1, 16 99 dsll k1, 16
98 daddiu k1, %hi(kernelsp) 100 daddiu k1, %hi(kernelsp)
99 dsll k1, 16 101 dsll k1, 16
100#else
101 lui k1, %hi(kernelsp)
102#endif 102#endif
103 LONG_SRL k0, PTEBASE_SHIFT 103 LONG_SRL k0, PTEBASE_SHIFT
104 LONG_ADDU k1, k0 104 LONG_ADDU k1, k0
@@ -116,14 +116,14 @@
116 .endm 116 .endm
117#else 117#else
118 .macro get_saved_sp /* Uniprocessor variation */ 118 .macro get_saved_sp /* Uniprocessor variation */
119#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) 119#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
120 lui k1, %hi(kernelsp)
121#else
120 lui k1, %highest(kernelsp) 122 lui k1, %highest(kernelsp)
121 daddiu k1, %higher(kernelsp) 123 daddiu k1, %higher(kernelsp)
122 dsll k1, k1, 16 124 dsll k1, k1, 16
123 daddiu k1, %hi(kernelsp) 125 daddiu k1, %hi(kernelsp)
124 dsll k1, k1, 16 126 dsll k1, k1, 16
125#else
126 lui k1, %hi(kernelsp)
127#endif 127#endif
128 LONG_L k1, %lo(kernelsp)(k1) 128 LONG_L k1, %lo(kernelsp)(k1)
129 .endm 129 .endm
@@ -393,11 +393,11 @@
393 * and disable interrupts only for the 393 * and disable interrupts only for the
394 * current TC, using the TCStatus register. 394 * current TC, using the TCStatus register.
395 */ 395 */
396 mfc0 t0,CP0_TCSTATUS 396 mfc0 t0, CP0_TCSTATUS
397 /* Fortunately CU 0 is in the same place in both registers */ 397 /* Fortunately CU 0 is in the same place in both registers */
398 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ 398 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
399 li t1, ST0_CU0 | 0x08001c00 399 li t1, ST0_CU0 | 0x08001c00
400 or t0,t1 400 or t0, t1
401 /* Clear TKSU, leave IXMT */ 401 /* Clear TKSU, leave IXMT */
402 xori t0, 0x00001800 402 xori t0, 0x00001800
403 mtc0 t0, CP0_TCSTATUS 403 mtc0 t0, CP0_TCSTATUS
@@ -429,11 +429,11 @@
429 * current TC, using the TCStatus register. 429 * current TC, using the TCStatus register.
430 */ 430 */
431 _ehb 431 _ehb
432 mfc0 t0,CP0_TCSTATUS 432 mfc0 t0, CP0_TCSTATUS
433 /* Fortunately CU 0 is in the same place in both registers */ 433 /* Fortunately CU 0 is in the same place in both registers */
434 /* Set TCU0, TKSU (for later inversion) and IXMT */ 434 /* Set TCU0, TKSU (for later inversion) and IXMT */
435 li t1, ST0_CU0 | 0x08001c00 435 li t1, ST0_CU0 | 0x08001c00
436 or t0,t1 436 or t0, t1
437 /* Clear TKSU *and* IXMT */ 437 /* Clear TKSU *and* IXMT */
438 xori t0, 0x00001c00 438 xori t0, 0x00001c00
439 mtc0 t0, CP0_TCSTATUS 439 mtc0 t0, CP0_TCSTATUS
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 480b574e2483..90e4b403f531 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -62,7 +62,7 @@ do { \
62#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) 62#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
63#endif 63#endif
64 64
65#define switch_to(prev,next,last) \ 65#define switch_to(prev, next, last) \
66do { \ 66do { \
67 __mips_mt_fpaff_switch_to(prev); \ 67 __mips_mt_fpaff_switch_to(prev); \
68 if (cpu_has_dsp) \ 68 if (cpu_has_dsp) \
@@ -193,13 +193,13 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
193 return x; 193 return x;
194} 194}
195 195
196#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 196#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
197 197
198extern void set_handler (unsigned long offset, void *addr, unsigned long len); 198extern void set_handler(unsigned long offset, void *addr, unsigned long len);
199extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); 199extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
200 200
201typedef void (*vi_handler_t)(void); 201typedef void (*vi_handler_t)(void);
202extern void *set_vi_handler (int n, vi_handler_t addr); 202extern void *set_vi_handler(int n, vi_handler_t addr);
203 203
204extern void *set_except_vector(int n, void *addr); 204extern void *set_except_vector(int n, void *addr);
205extern unsigned long ebase; 205extern unsigned long ebase;
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index a632cef830a2..35555bd5c52d 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -26,15 +26,13 @@
26extern spinlock_t rtc_lock; 26extern spinlock_t rtc_lock;
27 27
28/* 28/*
29 * RTC ops. By default, they point to no-RTC functions. 29 * RTC ops. By default, they point to weak no-op RTC functions.
30 * rtc_mips_get_time - mktime(year, mon, day, hour, min, sec) in seconds.
31 * rtc_mips_set_time - reverse the above translation and set time to RTC. 30 * rtc_mips_set_time - reverse the above translation and set time to RTC.
32 * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need 31 * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need
33 * to be set. Used by RTC sync-up. 32 * to be set. Used by RTC sync-up.
34 */ 33 */
35extern unsigned long (*rtc_mips_get_time)(void); 34extern int rtc_mips_set_time(unsigned long);
36extern int (*rtc_mips_set_time)(unsigned long); 35extern int rtc_mips_set_mmss(unsigned long);
37extern int (*rtc_mips_set_mmss)(unsigned long);
38 36
39/* 37/*
40 * Timer interrupt functions. 38 * Timer interrupt functions.
@@ -51,35 +49,15 @@ extern void (*mips_timer_ack)(void);
51extern struct clocksource clocksource_mips; 49extern struct clocksource clocksource_mips;
52 50
53/* 51/*
54 * to_tm() converts system time back to (year, mon, day, hour, min, sec).
55 * It is intended to help implement rtc_set_time() functions.
56 * Copied from PPC implementation.
57 */
58extern void to_tm(unsigned long tim, struct rtc_time *tm);
59
60/*
61 * high-level timer interrupt routines.
62 */
63extern irqreturn_t timer_interrupt(int irq, void *dev_id);
64
65/*
66 * the corresponding low-level timer interrupt routine.
67 */
68extern asmlinkage void ll_timer_interrupt(int irq);
69
70/*
71 * profiling and process accouting is done separately in local_timer_interrupt 52 * profiling and process accouting is done separately in local_timer_interrupt
72 */ 53 */
73extern void local_timer_interrupt(int irq, void *dev_id); 54extern void local_timer_interrupt(int irq, void *dev_id);
74extern asmlinkage void ll_local_timer_interrupt(int irq);
75 55
76/* 56/*
77 * board specific routines required by time_init(). 57 * board specific routines required by time_init().
78 * board_time_init is defaulted to NULL and can remain so.
79 * plat_timer_setup must be setup properly in machine setup routine.
80 */ 58 */
81struct irqaction; 59struct irqaction;
82extern void (*board_time_init)(void); 60extern void plat_time_init(void);
83extern void plat_timer_setup(struct irqaction *irq); 61extern void plat_timer_setup(struct irqaction *irq);
84 62
85/* 63/*
@@ -89,4 +67,15 @@ extern void plat_timer_setup(struct irqaction *irq);
89 */ 67 */
90extern unsigned int mips_hpt_frequency; 68extern unsigned int mips_hpt_frequency;
91 69
70/*
71 * The performance counter IRQ on MIPS is a close relative to the timer IRQ
72 * so it lives here.
73 */
74extern int (*perf_irq)(void);
75
76/*
77 * Initialize the calling CPU's compare interrupt as clockevent device
78 */
79extern void mips_clockevent_init(void);
80
92#endif /* _ASM_TIME_H */ 81#endif /* _ASM_TIME_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index b80de8e0fbbd..87c68ae76ff8 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -48,7 +48,7 @@
48 48
49typedef unsigned int cycles_t; 49typedef unsigned int cycles_t;
50 50
51static inline cycles_t get_cycles (void) 51static inline cycles_t get_cycles(void)
52{ 52{
53 return read_c0_count(); 53 return read_c0_count();
54} 54}
diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h
index 276be77c3e85..730e841fb08a 100644
--- a/include/asm-mips/tlbflush.h
+++ b/include/asm-mips/tlbflush.h
@@ -37,10 +37,10 @@ extern void flush_tlb_one(unsigned long vaddr);
37 37
38#define flush_tlb_all() local_flush_tlb_all() 38#define flush_tlb_all() local_flush_tlb_all()
39#define flush_tlb_mm(mm) local_flush_tlb_mm(mm) 39#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
40#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end) 40#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end)
41#define flush_tlb_kernel_range(vmaddr,end) \ 41#define flush_tlb_kernel_range(vmaddr,end) \
42 local_flush_tlb_kernel_range(vmaddr, end) 42 local_flush_tlb_kernel_range(vmaddr, end)
43#define flush_tlb_page(vma,page) local_flush_tlb_page(vma, page) 43#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
44#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) 44#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr)
45 45
46#endif /* CONFIG_SMP */ 46#endif /* CONFIG_SMP */
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index a60649569c2c..b188a659ce02 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -28,24 +28,20 @@
28#define __ASM_TX4927_TOSHIBA_RBTX4927_H 28#define __ASM_TX4927_TOSHIBA_RBTX4927_H
29 29
30#include <asm/tx4927/tx4927.h> 30#include <asm/tx4927/tx4927.h>
31#include <asm/tx4927/tx4927_mips.h>
32#ifdef CONFIG_PCI 31#ifdef CONFIG_PCI
33#include <asm/tx4927/tx4927_pci.h> 32#include <asm/tx4927/tx4927_pci.h>
34#endif 33#endif
35 34
36#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 )
37
38
39#ifdef CONFIG_PCI 35#ifdef CONFIG_PCI
40#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO 36#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
41#else 37#else
42#define TBTX4927_ISA_IO_OFFSET 0 38#define TBTX4927_ISA_IO_OFFSET 0
43#endif 39#endif
44 40
45#define RBTX4927_SW_RESET_DO 0xbc00f000 41#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
46#define RBTX4927_SW_RESET_DO_SET 0x01 42#define RBTX4927_SW_RESET_DO_SET 0x01
47 43
48#define RBTX4927_SW_RESET_ENABLE 0xbc00f002 44#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
49#define RBTX4927_SW_RESET_ENABLE_SET 0x01 45#define RBTX4927_SW_RESET_ENABLE_SET 0x01
50 46
51 47
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 4bd4368e188c..193e80a17c12 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -27,447 +27,8 @@
27#ifndef __ASM_TX4927_TX4927_H 27#ifndef __ASM_TX4927_TX4927_H
28#define __ASM_TX4927_TX4927_H 28#define __ASM_TX4927_TX4927_H
29 29
30#include <asm/tx4927/tx4927_mips.h>
31#include <asm/txx9irq.h> 30#include <asm/txx9irq.h>
32 31
33/*
34 This register naming came from the integrated CPU/controller name TX4927
35 followed by the device name from table 4.2.2 on page 4-3 and then followed
36 by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul
37 used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001".
38 */
39
40#define TX4927_SIO_0_BASE
41
42/* TX4927 controller */
43#define TX4927_BASE 0xfff1f0000
44#define TX4927_BASE 0xfff1f0000
45#define TX4927_LIMIT 0xfff1fffff
46
47
48/* TX4927 SDRAM controller (64-bit registers) */
49#define TX4927_SDRAMC_BASE 0x8000
50#define TX4927_SDRAMC_SDCCR0 0x8000
51#define TX4927_SDRAMC_SDCCR1 0x8008
52#define TX4927_SDRAMC_SDCCR2 0x8010
53#define TX4927_SDRAMC_SDCCR3 0x8018
54#define TX4927_SDRAMC_SDCTR 0x8040
55#define TX4927_SDRAMC_SDCMD 0x8058
56#define TX4927_SDRAMC_LIMIT 0x8fff
57
58
59/* TX4927 external bus controller (64-bit registers) */
60#define TX4927_EBUSC_BASE 0x9000
61#define TX4927_EBUSC_EBCCR0 0x9000
62#define TX4927_EBUSC_EBCCR1 0x9008
63#define TX4927_EBUSC_EBCCR2 0x9010
64#define TX4927_EBUSC_EBCCR3 0x9018
65#define TX4927_EBUSC_EBCCR4 0x9020
66#define TX4927_EBUSC_EBCCR5 0x9028
67#define TX4927_EBUSC_EBCCR6 0x9030
68#define TX4927_EBUSC_EBCCR7 0x9008
69#define TX4927_EBUSC_LIMIT 0x9fff
70
71
72/* TX4927 SDRRAM Error Check Correction (64-bit registers) */
73#define TX4927_ECC_BASE 0xa000
74#define TX4927_ECC_ECCCR 0xa000
75#define TX4927_ECC_ECCSR 0xa008
76#define TX4927_ECC_LIMIT 0xafff
77
78
79/* TX4927 DMA Controller (64-bit registers) */
80#define TX4927_DMAC_BASE 0xb000
81#define TX4927_DMAC_TBD 0xb000
82#define TX4927_DMAC_LIMIT 0xbfff
83
84
85/* TX4927 PCI Controller (32-bit registers) */
86#define TX4927_PCIC_BASE 0xd000
87#define TX4927_PCIC_TBD 0xb000
88#define TX4927_PCIC_LIMIT 0xdfff
89
90
91/* TX4927 Configuration registers (64-bit registers) */
92#define TX4927_CONFIG_BASE 0xe000
93#define TX4927_CONFIG_CCFG 0xe000
94#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42
95#define TX4927_CONFIG_CCFG_WDRST BM_41_41
96#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40
97#define TX4927_CONFIG_CCFG_BCFG BM_39_32
98#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27
99#define TX4927_CONFIG_CCFG_GTOT BM_26_25
100#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25
101#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26
102#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25
103#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25)
104#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24
105#define TX4927_CONFIG_CCFG_PCI66 BM_23_23
106#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22
107#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20
108#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17
109#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19
110#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17)
111#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18
112#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17
113#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17)
114#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17
115#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18
116#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17
117#define TX4927_CONFIG_CCFG_BEOW BM_16_16
118#define TX4927_CONFIG_CCFG_WR BM_15_15
119#define TX4927_CONFIG_CCFG_TOE BM_14_14
120#define TX4927_CONFIG_CCFG_PCIARB BM_13_13
121#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11
122#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08
123#define TX4927_CONFIG_CCFG_SYSSP BM_07_06
124#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03
125#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02
126#define TX4927_CONFIG_CCFG_ARMODE BM_01_01
127#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00
128#define TX4927_CONFIG_REVID 0xe008
129#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63
130#define TX4927_CONFIG_REVID_PCODE BM_16_31
131#define TX4927_CONFIG_REVID_MJERREV BM_12_15
132#define TX4927_CONFIG_REVID_MINEREV BM_08_11
133#define TX4927_CONFIG_REVID_MJREV BM_04_07
134#define TX4927_CONFIG_REVID_MINREV BM_00_03
135#define TX4927_CONFIG_PCFG 0xe010
136#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63
137#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56
138#define TX4927_CONFIG_PCFG_DRVCB BM_55_55
139#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54
140#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53
141#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52
142#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51
143#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50
144#define TX4927_CONFIG_PCFG_DRVWE BM_49_49
145#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48
146#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47
147#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k
148#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45
149#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44
150#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43
151#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42
152#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41
153#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40
154#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39
155#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32
156#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31
157#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29
158#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29)
159#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28
160#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29
161#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29
162#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27
163#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26
164#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25
165#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24
166#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23
167#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22
168#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21
169#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20
170#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19
171#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18
172#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17
173#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16
174#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15
175#define TX4927_CONFIG_PCFG_SEL2 BM_09_09
176#define TX4927_CONFIG_PCFG_SEL1 BM_08_08
177#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07
178#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07)
179#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06
180#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07
181#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07
182#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07
183#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07)
184#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06
185#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07
186#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07
187#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07)
188#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06
189#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07
190#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07
191#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03
192#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03)
193#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02
194#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03
195#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03
196#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01
197#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01)
198#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00
199#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01
200#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01
201#define TX4927_CONFIG_TOEA 0xe018
202#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63
203#define TX4927_CONFIG_TOEA_TOEA BM_00_35
204#define TX4927_CONFIG_CLKCTR 0xe020
205#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63
206#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25
207#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24
208#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23
209#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22
210#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21
211#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20
212#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19
213#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18
214#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17
215#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16
216#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15
217#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09
218#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08
219#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07
220#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06
221#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05
222#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04
223#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03
224#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02
225#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01
226#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00
227#define TX4927_CONFIG_GARBC 0xe030
228#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63
229#define TX4927_CONFIG_GARBC_SET_09 BM_09_09
230#define TX4927_CONFIG_GARBC_ARBMD BM_08_08
231#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07
232#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05
233#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05)
234#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04
235#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05
236#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05
237#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03
238#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03)
239#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02
240#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03
241#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03
242#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01
243#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01)
244#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00
245#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01
246#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01
247#define TX4927_CONFIG_RAMP 0xe048
248#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63
249#define TX4927_CONFIG_RAMP_RAMP BM_00_19
250#define TX4927_CONFIG_LIMIT 0xefff
251
252
253/* TX4927 Timer 0 (32-bit registers) */
254#define TX4927_TMR0_BASE 0xf000
255#define TX4927_TMR0_TMTCR0 0xf000
256#define TX4927_TMR0_TMTISR0 0xf004
257#define TX4927_TMR0_TMCPRA0 0xf008
258#define TX4927_TMR0_TMCPRB0 0xf00c
259#define TX4927_TMR0_TMITMR0 0xf010
260#define TX4927_TMR0_TMCCDR0 0xf020
261#define TX4927_TMR0_TMPGMR0 0xf030
262#define TX4927_TMR0_TMTRR0 0xf0f0
263#define TX4927_TMR0_LIMIT 0xf0ff
264
265
266/* TX4927 Timer 1 (32-bit registers) */
267#define TX4927_TMR1_BASE 0xf100
268#define TX4927_TMR1_TMTCR1 0xf100
269#define TX4927_TMR1_TMTISR1 0xf104
270#define TX4927_TMR1_TMCPRA1 0xf108
271#define TX4927_TMR1_TMCPRB1 0xf10c
272#define TX4927_TMR1_TMITMR1 0xf110
273#define TX4927_TMR1_TMCCDR1 0xf120
274#define TX4927_TMR1_TMPGMR1 0xf130
275#define TX4927_TMR1_TMTRR1 0xf1f0
276#define TX4927_TMR1_LIMIT 0xf1ff
277
278
279/* TX4927 Timer 2 (32-bit registers) */
280#define TX4927_TMR2_BASE 0xf200
281#define TX4927_TMR2_TMTCR2 0xf200
282#define TX4927_TMR2_TMTISR2 0xf204
283#define TX4927_TMR2_TMCPRA2 0xf208
284#define TX4927_TMR2_TMITMR2 0xf210
285#define TX4927_TMR2_TMCCDR2 0xf220
286#define TX4927_TMR2_TMWTMR2 0xf240
287#define TX4927_TMR2_TMTRR2 0xf2f0
288#define TX4927_TMR2_LIMIT 0xf2ff
289
290
291/* TX4927 serial port 0 (32-bit registers) */
292#define TX4927_SIO0_BASE 0xf300
293#define TX4927_SIO0_SILCR0 0xf300
294#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31
295#define TX4927_SIO0_SILCR0_RWUB BM_15_15
296#define TX4927_SIO0_SILCR0_TWUB BM_14_14
297#define TX4927_SIO0_SILCR0_UODE BM_13_13
298#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12
299#define TX4927_SIO0_SILCR0_SCS BM_05_06
300#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06)
301#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05
302#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06
303#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06
304#define TX4927_SIO0_SILCR0_UEPS BM_04_04
305#define TX4927_SIO0_SILCR0_UPEN BM_03_03
306#define TX4927_SIO0_SILCR0_USBL BM_02_02
307#define TX4927_SIO0_SILCR0_UMODE BM_00_01
308#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01
309#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)
310#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01
311#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01
312#define TX4927_SIO0_SIDICR0 0xf304
313#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31
314#define TX4927_SIO0_SIDICR0_TDE BM_15_15
315#define TX4927_SIO0_SIDICR0_RDE BM_14_14
316#define TX4927_SIO0_SIDICR0_TIE BM_13_13
317#define TX4927_SIO0_SIDICR0_RIE BM_12_12
318#define TX4927_SIO0_SIDICR0_SPIE BM_11_11
319#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10
320#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10)
321#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09
322#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10
323#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10
324#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08
325#define TX4927_SIO0_SIDICR0_STIE BM_00_05
326#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05)
327#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05
328#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04
329#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03
330#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02
331#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01
332#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00
333#define TX4927_SIO0_SIDISR0 0xf308
334#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31
335#define TX4927_SIO0_SIDISR0_UBRK BM_15_15
336#define TX4927_SIO0_SIDISR0_UVALID BM_14_14
337#define TX4927_SIO0_SIDISR0_UFER BM_13_13
338#define TX4927_SIO0_SIDISR0_UPER BM_12_12
339#define TX4927_SIO0_SIDISR0_UOER BM_11_11
340#define TX4927_SIO0_SIDISR0_ERI BM_10_10
341#define TX4927_SIO0_SIDISR0_TOUT BM_09_09
342#define TX4927_SIO0_SIDISR0_TDIS BM_08_08
343#define TX4927_SIO0_SIDISR0_RDIS BM_07_07
344#define TX4927_SIO0_SIDISR0_STIS BM_06_06
345#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05
346#define TX4927_SIO0_SIDISR0_RFDN BM_00_04
347#define TX4927_SIO0_SISCISR0 0xf30c
348#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31
349#define TX4927_SIO0_SISCISR0_OERS BM_05_05
350#define TX4927_SIO0_SISCISR0_CTSS BM_04_04
351#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03
352#define TX4927_SIO0_SISCISR0_TRDY BM_02_02
353#define TX4927_SIO0_SISCISR0_TXALS BM_01_01
354#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00
355#define TX4927_SIO0_SIFCR0 0xf310
356#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31
357#define TX4927_SIO0_SIFCR0_SWRST BM_16_31
358#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14
359#define TX4927_SIO0_SIFCR0_RDIL BM_16_31
360#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08)
361#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07
362#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08
363#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08
364#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06
365#define TX4927_SIO0_SIFCR0_TDIL BM_03_04
366#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04)
367#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03
368#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04
369#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04
370#define TX4927_SIO0_SIFCR0_TFRST BM_02_02
371#define TX4927_SIO0_SIFCR0_RFRST BM_01_01
372#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00
373#define TX4927_SIO0_SIFLCR0 0xf314
374#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31
375#define TX4927_SIO0_SIFLCR0_RCS BM_12_12
376#define TX4927_SIO0_SIFLCR0_TES BM_11_11
377#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10
378#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09
379#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08
380#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07
381#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06
382#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04
383#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00
384#define TX4927_SIO0_SIBGR0 0xf318
385#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31
386#define TX4927_SIO0_SIBGR0_BCLK BM_08_09
387#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)
388#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08
389#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09
390#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09
391#define TX4927_SIO0_SIBGR0_BRD BM_00_07
392#define TX4927_SIO0_SITFIF00 0xf31c
393#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31
394#define TX4927_SIO0_SITFIF00_TXD BM_00_07
395#define TX4927_SIO0_SIRFIFO0 0xf320
396#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31
397#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07
398#define TX4927_SIO0_SIRFIFO0 0xf320
399#define TX4927_SIO0_LIMIT 0xf3ff
400
401
402/* TX4927 serial port 1 (32-bit registers) */
403#define TX4927_SIO1_BASE 0xf400
404#define TX4927_SIO1_SILCR1 0xf400
405#define TX4927_SIO1_SIDICR1 0xf404
406#define TX4927_SIO1_SIDISR1 0xf408
407#define TX4927_SIO1_SISCISR1 0xf40c
408#define TX4927_SIO1_SIFCR1 0xf410
409#define TX4927_SIO1_SIFLCR1 0xf414
410#define TX4927_SIO1_SIBGR1 0xf418
411#define TX4927_SIO1_SITFIF01 0xf41c
412#define TX4927_SIO1_SIRFIFO1 0xf420
413#define TX4927_SIO1_LIMIT 0xf4ff
414
415
416/* TX4927 parallel port (32-bit registers) */
417#define TX4927_PIO_BASE 0xf500
418#define TX4927_PIO_PIOD0 0xf500
419#define TX4927_PIO_PIODI 0xf504
420#define TX4927_PIO_PIODIR 0xf508
421#define TX4927_PIO_PIOOD 0xf50c
422#define TX4927_PIO_LIMIT 0xf50f
423
424
425/* TX4927 AC-link controller (32-bit registers) */
426#define TX4927_ACLC_BASE 0xf700
427#define TX4927_ACLC_ACCTLEN 0xf700
428#define TX4927_ACLC_ACCTLDIS 0xf704
429#define TX4927_ACLC_ACREGACC 0xf708
430#define TX4927_ACLC_ACINTSTS 0xf710
431#define TX4927_ACLC_ACINTMSTS 0xf714
432#define TX4927_ACLC_ACINTEN 0xf718
433#define TX4927_ACLC_ACINTDIS 0xf71c
434#define TX4927_ACLC_ACSEMAPH 0xf720
435#define TX4927_ACLC_ACGPIDAT 0xf740
436#define TX4927_ACLC_ACGPODAT 0xf744
437#define TX4927_ACLC_ACSLTEN 0xf748
438#define TX4927_ACLC_ACSLTDIS 0xf74c
439#define TX4927_ACLC_ACFIFOSTS 0xf750
440#define TX4927_ACLC_ACDMASTS 0xf780
441#define TX4927_ACLC_ACDMASEL 0xf784
442#define TX4927_ACLC_ACAUDODAT 0xf7a0
443#define TX4927_ACLC_ACSURRDAT 0xf7a4
444#define TX4927_ACLC_ACCENTDAT 0xf7a8
445#define TX4927_ACLC_ACLFEDAT 0xf7ac
446#define TX4927_ACLC_ACAUDIDAT 0xf7b0
447#define TX4927_ACLC_ACMODODAT 0xf7b8
448#define TX4927_ACLC_ACMODIDAT 0xf7bc
449#define TX4927_ACLC_ACREVID 0xf7fc
450#define TX4927_ACLC_LIMIT 0xf7ff
451
452
453#define TX4927_REG(x) ((TX4927_BASE)+(x))
454
455#define TX4927_RD08( reg ) (*(vu08*)(reg))
456#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val))
457
458#define TX4927_RD16( reg ) (*(vu16*)(reg))
459#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val))
460
461#define TX4927_RD32( reg ) (*(vu32*)(reg))
462#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val))
463
464#define TX4927_RD64( reg ) (*(vu64*)(reg))
465#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val))
466
467#define TX4927_RD( reg ) TX4927_RD32( reg )
468#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
469
470
471#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE 32#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
472#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) 33#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
473 34
diff --git a/include/asm-mips/tx4927/tx4927_mips.h b/include/asm-mips/tx4927/tx4927_mips.h
deleted file mode 100644
index 242ab93bf2e2..000000000000
--- a/include/asm-mips/tx4927/tx4927_mips.h
+++ /dev/null
@@ -1,4177 +0,0 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2002 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TX4927_TX4927_MIPS_H
28#define __ASM_TX4927_TX4927_MIPS_H
29
30#ifndef __ASSEMBLY__
31
32static inline void asm_wait(void)
33{
34 __asm__(".set\tmips3\n\t"
35 "wait\n\t"
36 ".set\tmips0");
37}
38
39#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
40#define reg_rd16(r) ((u16)(*((vu16*)(r))))
41#define reg_rd32(r) ((u32)(*((vu32*)(r))))
42#define reg_rd64(r) ((u64)(*((vu64*)(r))))
43
44#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v)))
45#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v)))
46#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v)))
47#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v)))
48
49typedef volatile __signed char vs8;
50typedef volatile unsigned char vu8;
51
52typedef volatile __signed short vs16;
53typedef volatile unsigned short vu16;
54
55typedef volatile __signed int vs32;
56typedef volatile unsigned int vu32;
57
58typedef s8 s08;
59typedef vs8 vs08;
60
61typedef u8 u08;
62typedef vu8 vu08;
63
64
65#if (_MIPS_SZLONG == 64)
66
67typedef volatile __signed__ long vs64;
68typedef volatile unsigned long vu64;
69
70#else
71
72typedef volatile __signed__ long long vs64;
73typedef volatile unsigned long long vu64;
74
75#endif
76
77
78#define BM_00_00 0x0000000000000001
79#define BM_01_00 0x0000000000000003
80#define BM_00_01 BM_01_00
81#define BM_02_00 0x0000000000000007
82#define BM_00_02 BM_02_00
83#define BM_03_00 0x000000000000000f
84#define BM_00_03 BM_03_00
85#define BM_04_00 0x000000000000001f
86#define BM_00_04 BM_04_00
87#define BM_05_00 0x000000000000003f
88#define BM_00_05 BM_05_00
89#define BM_06_00 0x000000000000007f
90#define BM_00_06 BM_06_00
91#define BM_07_00 0x00000000000000ff
92#define BM_00_07 BM_07_00
93#define BM_08_00 0x00000000000001ff
94#define BM_00_08 BM_08_00
95#define BM_09_00 0x00000000000003ff
96#define BM_00_09 BM_09_00
97#define BM_10_00 0x00000000000007ff
98#define BM_00_10 BM_10_00
99#define BM_11_00 0x0000000000000fff
100#define BM_00_11 BM_11_00
101#define BM_12_00 0x0000000000001fff
102#define BM_00_12 BM_12_00
103#define BM_13_00 0x0000000000003fff
104#define BM_00_13 BM_13_00
105#define BM_14_00 0x0000000000007fff
106#define BM_00_14 BM_14_00
107#define BM_15_00 0x000000000000ffff
108#define BM_00_15 BM_15_00
109#define BM_16_00 0x000000000001ffff
110#define BM_00_16 BM_16_00
111#define BM_17_00 0x000000000003ffff
112#define BM_00_17 BM_17_00
113#define BM_18_00 0x000000000007ffff
114#define BM_00_18 BM_18_00
115#define BM_19_00 0x00000000000fffff
116#define BM_00_19 BM_19_00
117#define BM_20_00 0x00000000001fffff
118#define BM_00_20 BM_20_00
119#define BM_21_00 0x00000000003fffff
120#define BM_00_21 BM_21_00
121#define BM_22_00 0x00000000007fffff
122#define BM_00_22 BM_22_00
123#define BM_23_00 0x0000000000ffffff
124#define BM_00_23 BM_23_00
125#define BM_24_00 0x0000000001ffffff
126#define BM_00_24 BM_24_00
127#define BM_25_00 0x0000000003ffffff
128#define BM_00_25 BM_25_00
129#define BM_26_00 0x0000000007ffffff
130#define BM_00_26 BM_26_00
131#define BM_27_00 0x000000000fffffff
132#define BM_00_27 BM_27_00
133#define BM_28_00 0x000000001fffffff
134#define BM_00_28 BM_28_00
135#define BM_29_00 0x000000003fffffff
136#define BM_00_29 BM_29_00
137#define BM_30_00 0x000000007fffffff
138#define BM_00_30 BM_30_00
139#define BM_31_00 0x00000000ffffffff
140#define BM_00_31 BM_31_00
141#define BM_32_00 0x00000001ffffffff
142#define BM_00_32 BM_32_00
143#define BM_33_00 0x00000003ffffffff
144#define BM_00_33 BM_33_00
145#define BM_34_00 0x00000007ffffffff
146#define BM_00_34 BM_34_00
147#define BM_35_00 0x0000000fffffffff
148#define BM_00_35 BM_35_00
149#define BM_36_00 0x0000001fffffffff
150#define BM_00_36 BM_36_00
151#define BM_37_00 0x0000003fffffffff
152#define BM_00_37 BM_37_00
153#define BM_38_00 0x0000007fffffffff
154#define BM_00_38 BM_38_00
155#define BM_39_00 0x000000ffffffffff
156#define BM_00_39 BM_39_00
157#define BM_40_00 0x000001ffffffffff
158#define BM_00_40 BM_40_00
159#define BM_41_00 0x000003ffffffffff
160#define BM_00_41 BM_41_00
161#define BM_42_00 0x000007ffffffffff
162#define BM_00_42 BM_42_00
163#define BM_43_00 0x00000fffffffffff
164#define BM_00_43 BM_43_00
165#define BM_44_00 0x00001fffffffffff
166#define BM_00_44 BM_44_00
167#define BM_45_00 0x00003fffffffffff
168#define BM_00_45 BM_45_00
169#define BM_46_00 0x00007fffffffffff
170#define BM_00_46 BM_46_00
171#define BM_47_00 0x0000ffffffffffff
172#define BM_00_47 BM_47_00
173#define BM_48_00 0x0001ffffffffffff
174#define BM_00_48 BM_48_00
175#define BM_49_00 0x0003ffffffffffff
176#define BM_00_49 BM_49_00
177#define BM_50_00 0x0007ffffffffffff
178#define BM_00_50 BM_50_00
179#define BM_51_00 0x000fffffffffffff
180#define BM_00_51 BM_51_00
181#define BM_52_00 0x001fffffffffffff
182#define BM_00_52 BM_52_00
183#define BM_53_00 0x003fffffffffffff
184#define BM_00_53 BM_53_00
185#define BM_54_00 0x007fffffffffffff
186#define BM_00_54 BM_54_00
187#define BM_55_00 0x00ffffffffffffff
188#define BM_00_55 BM_55_00
189#define BM_56_00 0x01ffffffffffffff
190#define BM_00_56 BM_56_00
191#define BM_57_00 0x03ffffffffffffff
192#define BM_00_57 BM_57_00
193#define BM_58_00 0x07ffffffffffffff
194#define BM_00_58 BM_58_00
195#define BM_59_00 0x0fffffffffffffff
196#define BM_00_59 BM_59_00
197#define BM_60_00 0x1fffffffffffffff
198#define BM_00_60 BM_60_00
199#define BM_61_00 0x3fffffffffffffff
200#define BM_00_61 BM_61_00
201#define BM_62_00 0x7fffffffffffffff
202#define BM_00_62 BM_62_00
203#define BM_63_00 0xffffffffffffffff
204#define BM_00_63 BM_63_00
205#define BM_01_01 0x0000000000000002
206#define BM_02_01 0x0000000000000006
207#define BM_01_02 BM_02_01
208#define BM_03_01 0x000000000000000e
209#define BM_01_03 BM_03_01
210#define BM_04_01 0x000000000000001e
211#define BM_01_04 BM_04_01
212#define BM_05_01 0x000000000000003e
213#define BM_01_05 BM_05_01
214#define BM_06_01 0x000000000000007e
215#define BM_01_06 BM_06_01
216#define BM_07_01 0x00000000000000fe
217#define BM_01_07 BM_07_01
218#define BM_08_01 0x00000000000001fe
219#define BM_01_08 BM_08_01
220#define BM_09_01 0x00000000000003fe
221#define BM_01_09 BM_09_01
222#define BM_10_01 0x00000000000007fe
223#define BM_01_10 BM_10_01
224#define BM_11_01 0x0000000000000ffe
225#define BM_01_11 BM_11_01
226#define BM_12_01 0x0000000000001ffe
227#define BM_01_12 BM_12_01
228#define BM_13_01 0x0000000000003ffe
229#define BM_01_13 BM_13_01
230#define BM_14_01 0x0000000000007ffe
231#define BM_01_14 BM_14_01
232#define BM_15_01 0x000000000000fffe
233#define BM_01_15 BM_15_01
234#define BM_16_01 0x000000000001fffe
235#define BM_01_16 BM_16_01
236#define BM_17_01 0x000000000003fffe
237#define BM_01_17 BM_17_01
238#define BM_18_01 0x000000000007fffe
239#define BM_01_18 BM_18_01
240#define BM_19_01 0x00000000000ffffe
241#define BM_01_19 BM_19_01
242#define BM_20_01 0x00000000001ffffe
243#define BM_01_20 BM_20_01
244#define BM_21_01 0x00000000003ffffe
245#define BM_01_21 BM_21_01
246#define BM_22_01 0x00000000007ffffe
247#define BM_01_22 BM_22_01
248#define BM_23_01 0x0000000000fffffe
249#define BM_01_23 BM_23_01
250#define BM_24_01 0x0000000001fffffe
251#define BM_01_24 BM_24_01
252#define BM_25_01 0x0000000003fffffe
253#define BM_01_25 BM_25_01
254#define BM_26_01 0x0000000007fffffe
255#define BM_01_26 BM_26_01
256#define BM_27_01 0x000000000ffffffe
257#define BM_01_27 BM_27_01
258#define BM_28_01 0x000000001ffffffe
259#define BM_01_28 BM_28_01
260#define BM_29_01 0x000000003ffffffe
261#define BM_01_29 BM_29_01
262#define BM_30_01 0x000000007ffffffe
263#define BM_01_30 BM_30_01
264#define BM_31_01 0x00000000fffffffe
265#define BM_01_31 BM_31_01
266#define BM_32_01 0x00000001fffffffe
267#define BM_01_32 BM_32_01
268#define BM_33_01 0x00000003fffffffe
269#define BM_01_33 BM_33_01
270#define BM_34_01 0x00000007fffffffe
271#define BM_01_34 BM_34_01
272#define BM_35_01 0x0000000ffffffffe
273#define BM_01_35 BM_35_01
274#define BM_36_01 0x0000001ffffffffe
275#define BM_01_36 BM_36_01
276#define BM_37_01 0x0000003ffffffffe
277#define BM_01_37 BM_37_01
278#define BM_38_01 0x0000007ffffffffe
279#define BM_01_38 BM_38_01
280#define BM_39_01 0x000000fffffffffe
281#define BM_01_39 BM_39_01
282#define BM_40_01 0x000001fffffffffe
283#define BM_01_40 BM_40_01
284#define BM_41_01 0x000003fffffffffe
285#define BM_01_41 BM_41_01
286#define BM_42_01 0x000007fffffffffe
287#define BM_01_42 BM_42_01
288#define BM_43_01 0x00000ffffffffffe
289#define BM_01_43 BM_43_01
290#define BM_44_01 0x00001ffffffffffe
291#define BM_01_44 BM_44_01
292#define BM_45_01 0x00003ffffffffffe
293#define BM_01_45 BM_45_01
294#define BM_46_01 0x00007ffffffffffe
295#define BM_01_46 BM_46_01
296#define BM_47_01 0x0000fffffffffffe
297#define BM_01_47 BM_47_01
298#define BM_48_01 0x0001fffffffffffe
299#define BM_01_48 BM_48_01
300#define BM_49_01 0x0003fffffffffffe
301#define BM_01_49 BM_49_01
302#define BM_50_01 0x0007fffffffffffe
303#define BM_01_50 BM_50_01
304#define BM_51_01 0x000ffffffffffffe
305#define BM_01_51 BM_51_01
306#define BM_52_01 0x001ffffffffffffe
307#define BM_01_52 BM_52_01
308#define BM_53_01 0x003ffffffffffffe
309#define BM_01_53 BM_53_01
310#define BM_54_01 0x007ffffffffffffe
311#define BM_01_54 BM_54_01
312#define BM_55_01 0x00fffffffffffffe
313#define BM_01_55 BM_55_01
314#define BM_56_01 0x01fffffffffffffe
315#define BM_01_56 BM_56_01
316#define BM_57_01 0x03fffffffffffffe
317#define BM_01_57 BM_57_01
318#define BM_58_01 0x07fffffffffffffe
319#define BM_01_58 BM_58_01
320#define BM_59_01 0x0ffffffffffffffe
321#define BM_01_59 BM_59_01
322#define BM_60_01 0x1ffffffffffffffe
323#define BM_01_60 BM_60_01
324#define BM_61_01 0x3ffffffffffffffe
325#define BM_01_61 BM_61_01
326#define BM_62_01 0x7ffffffffffffffe
327#define BM_01_62 BM_62_01
328#define BM_63_01 0xfffffffffffffffe
329#define BM_01_63 BM_63_01
330#define BM_02_02 0x0000000000000004
331#define BM_03_02 0x000000000000000c
332#define BM_02_03 BM_03_02
333#define BM_04_02 0x000000000000001c
334#define BM_02_04 BM_04_02
335#define BM_05_02 0x000000000000003c
336#define BM_02_05 BM_05_02
337#define BM_06_02 0x000000000000007c
338#define BM_02_06 BM_06_02
339#define BM_07_02 0x00000000000000fc
340#define BM_02_07 BM_07_02
341#define BM_08_02 0x00000000000001fc
342#define BM_02_08 BM_08_02
343#define BM_09_02 0x00000000000003fc
344#define BM_02_09 BM_09_02
345#define BM_10_02 0x00000000000007fc
346#define BM_02_10 BM_10_02
347#define BM_11_02 0x0000000000000ffc
348#define BM_02_11 BM_11_02
349#define BM_12_02 0x0000000000001ffc
350#define BM_02_12 BM_12_02
351#define BM_13_02 0x0000000000003ffc
352#define BM_02_13 BM_13_02
353#define BM_14_02 0x0000000000007ffc
354#define BM_02_14 BM_14_02
355#define BM_15_02 0x000000000000fffc
356#define BM_02_15 BM_15_02
357#define BM_16_02 0x000000000001fffc
358#define BM_02_16 BM_16_02
359#define BM_17_02 0x000000000003fffc
360#define BM_02_17 BM_17_02
361#define BM_18_02 0x000000000007fffc
362#define BM_02_18 BM_18_02
363#define BM_19_02 0x00000000000ffffc
364#define BM_02_19 BM_19_02
365#define BM_20_02 0x00000000001ffffc
366#define BM_02_20 BM_20_02
367#define BM_21_02 0x00000000003ffffc
368#define BM_02_21 BM_21_02
369#define BM_22_02 0x00000000007ffffc
370#define BM_02_22 BM_22_02
371#define BM_23_02 0x0000000000fffffc
372#define BM_02_23 BM_23_02
373#define BM_24_02 0x0000000001fffffc
374#define BM_02_24 BM_24_02
375#define BM_25_02 0x0000000003fffffc
376#define BM_02_25 BM_25_02
377#define BM_26_02 0x0000000007fffffc
378#define BM_02_26 BM_26_02
379#define BM_27_02 0x000000000ffffffc
380#define BM_02_27 BM_27_02
381#define BM_28_02 0x000000001ffffffc
382#define BM_02_28 BM_28_02
383#define BM_29_02 0x000000003ffffffc
384#define BM_02_29 BM_29_02
385#define BM_30_02 0x000000007ffffffc
386#define BM_02_30 BM_30_02
387#define BM_31_02 0x00000000fffffffc
388#define BM_02_31 BM_31_02
389#define BM_32_02 0x00000001fffffffc
390#define BM_02_32 BM_32_02
391#define BM_33_02 0x00000003fffffffc
392#define BM_02_33 BM_33_02
393#define BM_34_02 0x00000007fffffffc
394#define BM_02_34 BM_34_02
395#define BM_35_02 0x0000000ffffffffc
396#define BM_02_35 BM_35_02
397#define BM_36_02 0x0000001ffffffffc
398#define BM_02_36 BM_36_02
399#define BM_37_02 0x0000003ffffffffc
400#define BM_02_37 BM_37_02
401#define BM_38_02 0x0000007ffffffffc
402#define BM_02_38 BM_38_02
403#define BM_39_02 0x000000fffffffffc
404#define BM_02_39 BM_39_02
405#define BM_40_02 0x000001fffffffffc
406#define BM_02_40 BM_40_02
407#define BM_41_02 0x000003fffffffffc
408#define BM_02_41 BM_41_02
409#define BM_42_02 0x000007fffffffffc
410#define BM_02_42 BM_42_02
411#define BM_43_02 0x00000ffffffffffc
412#define BM_02_43 BM_43_02
413#define BM_44_02 0x00001ffffffffffc
414#define BM_02_44 BM_44_02
415#define BM_45_02 0x00003ffffffffffc
416#define BM_02_45 BM_45_02
417#define BM_46_02 0x00007ffffffffffc
418#define BM_02_46 BM_46_02
419#define BM_47_02 0x0000fffffffffffc
420#define BM_02_47 BM_47_02
421#define BM_48_02 0x0001fffffffffffc
422#define BM_02_48 BM_48_02
423#define BM_49_02 0x0003fffffffffffc
424#define BM_02_49 BM_49_02
425#define BM_50_02 0x0007fffffffffffc
426#define BM_02_50 BM_50_02
427#define BM_51_02 0x000ffffffffffffc
428#define BM_02_51 BM_51_02
429#define BM_52_02 0x001ffffffffffffc
430#define BM_02_52 BM_52_02
431#define BM_53_02 0x003ffffffffffffc
432#define BM_02_53 BM_53_02
433#define BM_54_02 0x007ffffffffffffc
434#define BM_02_54 BM_54_02
435#define BM_55_02 0x00fffffffffffffc
436#define BM_02_55 BM_55_02
437#define BM_56_02 0x01fffffffffffffc
438#define BM_02_56 BM_56_02
439#define BM_57_02 0x03fffffffffffffc
440#define BM_02_57 BM_57_02
441#define BM_58_02 0x07fffffffffffffc
442#define BM_02_58 BM_58_02
443#define BM_59_02 0x0ffffffffffffffc
444#define BM_02_59 BM_59_02
445#define BM_60_02 0x1ffffffffffffffc
446#define BM_02_60 BM_60_02
447#define BM_61_02 0x3ffffffffffffffc
448#define BM_02_61 BM_61_02
449#define BM_62_02 0x7ffffffffffffffc
450#define BM_02_62 BM_62_02
451#define BM_63_02 0xfffffffffffffffc
452#define BM_02_63 BM_63_02
453#define BM_03_03 0x0000000000000008
454#define BM_04_03 0x0000000000000018
455#define BM_03_04 BM_04_03
456#define BM_05_03 0x0000000000000038
457#define BM_03_05 BM_05_03
458#define BM_06_03 0x0000000000000078
459#define BM_03_06 BM_06_03
460#define BM_07_03 0x00000000000000f8
461#define BM_03_07 BM_07_03
462#define BM_08_03 0x00000000000001f8
463#define BM_03_08 BM_08_03
464#define BM_09_03 0x00000000000003f8
465#define BM_03_09 BM_09_03
466#define BM_10_03 0x00000000000007f8
467#define BM_03_10 BM_10_03
468#define BM_11_03 0x0000000000000ff8
469#define BM_03_11 BM_11_03
470#define BM_12_03 0x0000000000001ff8
471#define BM_03_12 BM_12_03
472#define BM_13_03 0x0000000000003ff8
473#define BM_03_13 BM_13_03
474#define BM_14_03 0x0000000000007ff8
475#define BM_03_14 BM_14_03
476#define BM_15_03 0x000000000000fff8
477#define BM_03_15 BM_15_03
478#define BM_16_03 0x000000000001fff8
479#define BM_03_16 BM_16_03
480#define BM_17_03 0x000000000003fff8
481#define BM_03_17 BM_17_03
482#define BM_18_03 0x000000000007fff8
483#define BM_03_18 BM_18_03
484#define BM_19_03 0x00000000000ffff8
485#define BM_03_19 BM_19_03
486#define BM_20_03 0x00000000001ffff8
487#define BM_03_20 BM_20_03
488#define BM_21_03 0x00000000003ffff8
489#define BM_03_21 BM_21_03
490#define BM_22_03 0x00000000007ffff8
491#define BM_03_22 BM_22_03
492#define BM_23_03 0x0000000000fffff8
493#define BM_03_23 BM_23_03
494#define BM_24_03 0x0000000001fffff8
495#define BM_03_24 BM_24_03
496#define BM_25_03 0x0000000003fffff8
497#define BM_03_25 BM_25_03
498#define BM_26_03 0x0000000007fffff8
499#define BM_03_26 BM_26_03
500#define BM_27_03 0x000000000ffffff8
501#define BM_03_27 BM_27_03
502#define BM_28_03 0x000000001ffffff8
503#define BM_03_28 BM_28_03
504#define BM_29_03 0x000000003ffffff8
505#define BM_03_29 BM_29_03
506#define BM_30_03 0x000000007ffffff8
507#define BM_03_30 BM_30_03
508#define BM_31_03 0x00000000fffffff8
509#define BM_03_31 BM_31_03
510#define BM_32_03 0x00000001fffffff8
511#define BM_03_32 BM_32_03
512#define BM_33_03 0x00000003fffffff8
513#define BM_03_33 BM_33_03
514#define BM_34_03 0x00000007fffffff8
515#define BM_03_34 BM_34_03
516#define BM_35_03 0x0000000ffffffff8
517#define BM_03_35 BM_35_03
518#define BM_36_03 0x0000001ffffffff8
519#define BM_03_36 BM_36_03
520#define BM_37_03 0x0000003ffffffff8
521#define BM_03_37 BM_37_03
522#define BM_38_03 0x0000007ffffffff8
523#define BM_03_38 BM_38_03
524#define BM_39_03 0x000000fffffffff8
525#define BM_03_39 BM_39_03
526#define BM_40_03 0x000001fffffffff8
527#define BM_03_40 BM_40_03
528#define BM_41_03 0x000003fffffffff8
529#define BM_03_41 BM_41_03
530#define BM_42_03 0x000007fffffffff8
531#define BM_03_42 BM_42_03
532#define BM_43_03 0x00000ffffffffff8
533#define BM_03_43 BM_43_03
534#define BM_44_03 0x00001ffffffffff8
535#define BM_03_44 BM_44_03
536#define BM_45_03 0x00003ffffffffff8
537#define BM_03_45 BM_45_03
538#define BM_46_03 0x00007ffffffffff8
539#define BM_03_46 BM_46_03
540#define BM_47_03 0x0000fffffffffff8
541#define BM_03_47 BM_47_03
542#define BM_48_03 0x0001fffffffffff8
543#define BM_03_48 BM_48_03
544#define BM_49_03 0x0003fffffffffff8
545#define BM_03_49 BM_49_03
546#define BM_50_03 0x0007fffffffffff8
547#define BM_03_50 BM_50_03
548#define BM_51_03 0x000ffffffffffff8
549#define BM_03_51 BM_51_03
550#define BM_52_03 0x001ffffffffffff8
551#define BM_03_52 BM_52_03
552#define BM_53_03 0x003ffffffffffff8
553#define BM_03_53 BM_53_03
554#define BM_54_03 0x007ffffffffffff8
555#define BM_03_54 BM_54_03
556#define BM_55_03 0x00fffffffffffff8
557#define BM_03_55 BM_55_03
558#define BM_56_03 0x01fffffffffffff8
559#define BM_03_56 BM_56_03
560#define BM_57_03 0x03fffffffffffff8
561#define BM_03_57 BM_57_03
562#define BM_58_03 0x07fffffffffffff8
563#define BM_03_58 BM_58_03
564#define BM_59_03 0x0ffffffffffffff8
565#define BM_03_59 BM_59_03
566#define BM_60_03 0x1ffffffffffffff8
567#define BM_03_60 BM_60_03
568#define BM_61_03 0x3ffffffffffffff8
569#define BM_03_61 BM_61_03
570#define BM_62_03 0x7ffffffffffffff8
571#define BM_03_62 BM_62_03
572#define BM_63_03 0xfffffffffffffff8
573#define BM_03_63 BM_63_03
574#define BM_04_04 0x0000000000000010
575#define BM_05_04 0x0000000000000030
576#define BM_04_05 BM_05_04
577#define BM_06_04 0x0000000000000070
578#define BM_04_06 BM_06_04
579#define BM_07_04 0x00000000000000f0
580#define BM_04_07 BM_07_04
581#define BM_08_04 0x00000000000001f0
582#define BM_04_08 BM_08_04
583#define BM_09_04 0x00000000000003f0
584#define BM_04_09 BM_09_04
585#define BM_10_04 0x00000000000007f0
586#define BM_04_10 BM_10_04
587#define BM_11_04 0x0000000000000ff0
588#define BM_04_11 BM_11_04
589#define BM_12_04 0x0000000000001ff0
590#define BM_04_12 BM_12_04
591#define BM_13_04 0x0000000000003ff0
592#define BM_04_13 BM_13_04
593#define BM_14_04 0x0000000000007ff0
594#define BM_04_14 BM_14_04
595#define BM_15_04 0x000000000000fff0
596#define BM_04_15 BM_15_04
597#define BM_16_04 0x000000000001fff0
598#define BM_04_16 BM_16_04
599#define BM_17_04 0x000000000003fff0
600#define BM_04_17 BM_17_04
601#define BM_18_04 0x000000000007fff0
602#define BM_04_18 BM_18_04
603#define BM_19_04 0x00000000000ffff0
604#define BM_04_19 BM_19_04
605#define BM_20_04 0x00000000001ffff0
606#define BM_04_20 BM_20_04
607#define BM_21_04 0x00000000003ffff0
608#define BM_04_21 BM_21_04
609#define BM_22_04 0x00000000007ffff0
610#define BM_04_22 BM_22_04
611#define BM_23_04 0x0000000000fffff0
612#define BM_04_23 BM_23_04
613#define BM_24_04 0x0000000001fffff0
614#define BM_04_24 BM_24_04
615#define BM_25_04 0x0000000003fffff0
616#define BM_04_25 BM_25_04
617#define BM_26_04 0x0000000007fffff0
618#define BM_04_26 BM_26_04
619#define BM_27_04 0x000000000ffffff0
620#define BM_04_27 BM_27_04
621#define BM_28_04 0x000000001ffffff0
622#define BM_04_28 BM_28_04
623#define BM_29_04 0x000000003ffffff0
624#define BM_04_29 BM_29_04
625#define BM_30_04 0x000000007ffffff0
626#define BM_04_30 BM_30_04
627#define BM_31_04 0x00000000fffffff0
628#define BM_04_31 BM_31_04
629#define BM_32_04 0x00000001fffffff0
630#define BM_04_32 BM_32_04
631#define BM_33_04 0x00000003fffffff0
632#define BM_04_33 BM_33_04
633#define BM_34_04 0x00000007fffffff0
634#define BM_04_34 BM_34_04
635#define BM_35_04 0x0000000ffffffff0
636#define BM_04_35 BM_35_04
637#define BM_36_04 0x0000001ffffffff0
638#define BM_04_36 BM_36_04
639#define BM_37_04 0x0000003ffffffff0
640#define BM_04_37 BM_37_04
641#define BM_38_04 0x0000007ffffffff0
642#define BM_04_38 BM_38_04
643#define BM_39_04 0x000000fffffffff0
644#define BM_04_39 BM_39_04
645#define BM_40_04 0x000001fffffffff0
646#define BM_04_40 BM_40_04
647#define BM_41_04 0x000003fffffffff0
648#define BM_04_41 BM_41_04
649#define BM_42_04 0x000007fffffffff0
650#define BM_04_42 BM_42_04
651#define BM_43_04 0x00000ffffffffff0
652#define BM_04_43 BM_43_04
653#define BM_44_04 0x00001ffffffffff0
654#define BM_04_44 BM_44_04
655#define BM_45_04 0x00003ffffffffff0
656#define BM_04_45 BM_45_04
657#define BM_46_04 0x00007ffffffffff0
658#define BM_04_46 BM_46_04
659#define BM_47_04 0x0000fffffffffff0
660#define BM_04_47 BM_47_04
661#define BM_48_04 0x0001fffffffffff0
662#define BM_04_48 BM_48_04
663#define BM_49_04 0x0003fffffffffff0
664#define BM_04_49 BM_49_04
665#define BM_50_04 0x0007fffffffffff0
666#define BM_04_50 BM_50_04
667#define BM_51_04 0x000ffffffffffff0
668#define BM_04_51 BM_51_04
669#define BM_52_04 0x001ffffffffffff0
670#define BM_04_52 BM_52_04
671#define BM_53_04 0x003ffffffffffff0
672#define BM_04_53 BM_53_04
673#define BM_54_04 0x007ffffffffffff0
674#define BM_04_54 BM_54_04
675#define BM_55_04 0x00fffffffffffff0
676#define BM_04_55 BM_55_04
677#define BM_56_04 0x01fffffffffffff0
678#define BM_04_56 BM_56_04
679#define BM_57_04 0x03fffffffffffff0
680#define BM_04_57 BM_57_04
681#define BM_58_04 0x07fffffffffffff0
682#define BM_04_58 BM_58_04
683#define BM_59_04 0x0ffffffffffffff0
684#define BM_04_59 BM_59_04
685#define BM_60_04 0x1ffffffffffffff0
686#define BM_04_60 BM_60_04
687#define BM_61_04 0x3ffffffffffffff0
688#define BM_04_61 BM_61_04
689#define BM_62_04 0x7ffffffffffffff0
690#define BM_04_62 BM_62_04
691#define BM_63_04 0xfffffffffffffff0
692#define BM_04_63 BM_63_04
693#define BM_05_05 0x0000000000000020
694#define BM_06_05 0x0000000000000060
695#define BM_05_06 BM_06_05
696#define BM_07_05 0x00000000000000e0
697#define BM_05_07 BM_07_05
698#define BM_08_05 0x00000000000001e0
699#define BM_05_08 BM_08_05
700#define BM_09_05 0x00000000000003e0
701#define BM_05_09 BM_09_05
702#define BM_10_05 0x00000000000007e0
703#define BM_05_10 BM_10_05
704#define BM_11_05 0x0000000000000fe0
705#define BM_05_11 BM_11_05
706#define BM_12_05 0x0000000000001fe0
707#define BM_05_12 BM_12_05
708#define BM_13_05 0x0000000000003fe0
709#define BM_05_13 BM_13_05
710#define BM_14_05 0x0000000000007fe0
711#define BM_05_14 BM_14_05
712#define BM_15_05 0x000000000000ffe0
713#define BM_05_15 BM_15_05
714#define BM_16_05 0x000000000001ffe0
715#define BM_05_16 BM_16_05
716#define BM_17_05 0x000000000003ffe0
717#define BM_05_17 BM_17_05
718#define BM_18_05 0x000000000007ffe0
719#define BM_05_18 BM_18_05
720#define BM_19_05 0x00000000000fffe0
721#define BM_05_19 BM_19_05
722#define BM_20_05 0x00000000001fffe0
723#define BM_05_20 BM_20_05
724#define BM_21_05 0x00000000003fffe0
725#define BM_05_21 BM_21_05
726#define BM_22_05 0x00000000007fffe0
727#define BM_05_22 BM_22_05
728#define BM_23_05 0x0000000000ffffe0
729#define BM_05_23 BM_23_05
730#define BM_24_05 0x0000000001ffffe0
731#define BM_05_24 BM_24_05
732#define BM_25_05 0x0000000003ffffe0
733#define BM_05_25 BM_25_05
734#define BM_26_05 0x0000000007ffffe0
735#define BM_05_26 BM_26_05
736#define BM_27_05 0x000000000fffffe0
737#define BM_05_27 BM_27_05
738#define BM_28_05 0x000000001fffffe0
739#define BM_05_28 BM_28_05
740#define BM_29_05 0x000000003fffffe0
741#define BM_05_29 BM_29_05
742#define BM_30_05 0x000000007fffffe0
743#define BM_05_30 BM_30_05
744#define BM_31_05 0x00000000ffffffe0
745#define BM_05_31 BM_31_05
746#define BM_32_05 0x00000001ffffffe0
747#define BM_05_32 BM_32_05
748#define BM_33_05 0x00000003ffffffe0
749#define BM_05_33 BM_33_05
750#define BM_34_05 0x00000007ffffffe0
751#define BM_05_34 BM_34_05
752#define BM_35_05 0x0000000fffffffe0
753#define BM_05_35 BM_35_05
754#define BM_36_05 0x0000001fffffffe0
755#define BM_05_36 BM_36_05
756#define BM_37_05 0x0000003fffffffe0
757#define BM_05_37 BM_37_05
758#define BM_38_05 0x0000007fffffffe0
759#define BM_05_38 BM_38_05
760#define BM_39_05 0x000000ffffffffe0
761#define BM_05_39 BM_39_05
762#define BM_40_05 0x000001ffffffffe0
763#define BM_05_40 BM_40_05
764#define BM_41_05 0x000003ffffffffe0
765#define BM_05_41 BM_41_05
766#define BM_42_05 0x000007ffffffffe0
767#define BM_05_42 BM_42_05
768#define BM_43_05 0x00000fffffffffe0
769#define BM_05_43 BM_43_05
770#define BM_44_05 0x00001fffffffffe0
771#define BM_05_44 BM_44_05
772#define BM_45_05 0x00003fffffffffe0
773#define BM_05_45 BM_45_05
774#define BM_46_05 0x00007fffffffffe0
775#define BM_05_46 BM_46_05
776#define BM_47_05 0x0000ffffffffffe0
777#define BM_05_47 BM_47_05
778#define BM_48_05 0x0001ffffffffffe0
779#define BM_05_48 BM_48_05
780#define BM_49_05 0x0003ffffffffffe0
781#define BM_05_49 BM_49_05
782#define BM_50_05 0x0007ffffffffffe0
783#define BM_05_50 BM_50_05
784#define BM_51_05 0x000fffffffffffe0
785#define BM_05_51 BM_51_05
786#define BM_52_05 0x001fffffffffffe0
787#define BM_05_52 BM_52_05
788#define BM_53_05 0x003fffffffffffe0
789#define BM_05_53 BM_53_05
790#define BM_54_05 0x007fffffffffffe0
791#define BM_05_54 BM_54_05
792#define BM_55_05 0x00ffffffffffffe0
793#define BM_05_55 BM_55_05
794#define BM_56_05 0x01ffffffffffffe0
795#define BM_05_56 BM_56_05
796#define BM_57_05 0x03ffffffffffffe0
797#define BM_05_57 BM_57_05
798#define BM_58_05 0x07ffffffffffffe0
799#define BM_05_58 BM_58_05
800#define BM_59_05 0x0fffffffffffffe0
801#define BM_05_59 BM_59_05
802#define BM_60_05 0x1fffffffffffffe0
803#define BM_05_60 BM_60_05
804#define BM_61_05 0x3fffffffffffffe0
805#define BM_05_61 BM_61_05
806#define BM_62_05 0x7fffffffffffffe0
807#define BM_05_62 BM_62_05
808#define BM_63_05 0xffffffffffffffe0
809#define BM_05_63 BM_63_05
810#define BM_06_06 0x0000000000000040
811#define BM_07_06 0x00000000000000c0
812#define BM_06_07 BM_07_06
813#define BM_08_06 0x00000000000001c0
814#define BM_06_08 BM_08_06
815#define BM_09_06 0x00000000000003c0
816#define BM_06_09 BM_09_06
817#define BM_10_06 0x00000000000007c0
818#define BM_06_10 BM_10_06
819#define BM_11_06 0x0000000000000fc0
820#define BM_06_11 BM_11_06
821#define BM_12_06 0x0000000000001fc0
822#define BM_06_12 BM_12_06
823#define BM_13_06 0x0000000000003fc0
824#define BM_06_13 BM_13_06
825#define BM_14_06 0x0000000000007fc0
826#define BM_06_14 BM_14_06
827#define BM_15_06 0x000000000000ffc0
828#define BM_06_15 BM_15_06
829#define BM_16_06 0x000000000001ffc0
830#define BM_06_16 BM_16_06
831#define BM_17_06 0x000000000003ffc0
832#define BM_06_17 BM_17_06
833#define BM_18_06 0x000000000007ffc0
834#define BM_06_18 BM_18_06
835#define BM_19_06 0x00000000000fffc0
836#define BM_06_19 BM_19_06
837#define BM_20_06 0x00000000001fffc0
838#define BM_06_20 BM_20_06
839#define BM_21_06 0x00000000003fffc0
840#define BM_06_21 BM_21_06
841#define BM_22_06 0x00000000007fffc0
842#define BM_06_22 BM_22_06
843#define BM_23_06 0x0000000000ffffc0
844#define BM_06_23 BM_23_06
845#define BM_24_06 0x0000000001ffffc0
846#define BM_06_24 BM_24_06
847#define BM_25_06 0x0000000003ffffc0
848#define BM_06_25 BM_25_06
849#define BM_26_06 0x0000000007ffffc0
850#define BM_06_26 BM_26_06
851#define BM_27_06 0x000000000fffffc0
852#define BM_06_27 BM_27_06
853#define BM_28_06 0x000000001fffffc0
854#define BM_06_28 BM_28_06
855#define BM_29_06 0x000000003fffffc0
856#define BM_06_29 BM_29_06
857#define BM_30_06 0x000000007fffffc0
858#define BM_06_30 BM_30_06
859#define BM_31_06 0x00000000ffffffc0
860#define BM_06_31 BM_31_06
861#define BM_32_06 0x00000001ffffffc0
862#define BM_06_32 BM_32_06
863#define BM_33_06 0x00000003ffffffc0
864#define BM_06_33 BM_33_06
865#define BM_34_06 0x00000007ffffffc0
866#define BM_06_34 BM_34_06
867#define BM_35_06 0x0000000fffffffc0
868#define BM_06_35 BM_35_06
869#define BM_36_06 0x0000001fffffffc0
870#define BM_06_36 BM_36_06
871#define BM_37_06 0x0000003fffffffc0
872#define BM_06_37 BM_37_06
873#define BM_38_06 0x0000007fffffffc0
874#define BM_06_38 BM_38_06
875#define BM_39_06 0x000000ffffffffc0
876#define BM_06_39 BM_39_06
877#define BM_40_06 0x000001ffffffffc0
878#define BM_06_40 BM_40_06
879#define BM_41_06 0x000003ffffffffc0
880#define BM_06_41 BM_41_06
881#define BM_42_06 0x000007ffffffffc0
882#define BM_06_42 BM_42_06
883#define BM_43_06 0x00000fffffffffc0
884#define BM_06_43 BM_43_06
885#define BM_44_06 0x00001fffffffffc0
886#define BM_06_44 BM_44_06
887#define BM_45_06 0x00003fffffffffc0
888#define BM_06_45 BM_45_06
889#define BM_46_06 0x00007fffffffffc0
890#define BM_06_46 BM_46_06
891#define BM_47_06 0x0000ffffffffffc0
892#define BM_06_47 BM_47_06
893#define BM_48_06 0x0001ffffffffffc0
894#define BM_06_48 BM_48_06
895#define BM_49_06 0x0003ffffffffffc0
896#define BM_06_49 BM_49_06
897#define BM_50_06 0x0007ffffffffffc0
898#define BM_06_50 BM_50_06
899#define BM_51_06 0x000fffffffffffc0
900#define BM_06_51 BM_51_06
901#define BM_52_06 0x001fffffffffffc0
902#define BM_06_52 BM_52_06
903#define BM_53_06 0x003fffffffffffc0
904#define BM_06_53 BM_53_06
905#define BM_54_06 0x007fffffffffffc0
906#define BM_06_54 BM_54_06
907#define BM_55_06 0x00ffffffffffffc0
908#define BM_06_55 BM_55_06
909#define BM_56_06 0x01ffffffffffffc0
910#define BM_06_56 BM_56_06
911#define BM_57_06 0x03ffffffffffffc0
912#define BM_06_57 BM_57_06
913#define BM_58_06 0x07ffffffffffffc0
914#define BM_06_58 BM_58_06
915#define BM_59_06 0x0fffffffffffffc0
916#define BM_06_59 BM_59_06
917#define BM_60_06 0x1fffffffffffffc0
918#define BM_06_60 BM_60_06
919#define BM_61_06 0x3fffffffffffffc0
920#define BM_06_61 BM_61_06
921#define BM_62_06 0x7fffffffffffffc0
922#define BM_06_62 BM_62_06
923#define BM_63_06 0xffffffffffffffc0
924#define BM_06_63 BM_63_06
925#define BM_07_07 0x0000000000000080
926#define BM_08_07 0x0000000000000180
927#define BM_07_08 BM_08_07
928#define BM_09_07 0x0000000000000380
929#define BM_07_09 BM_09_07
930#define BM_10_07 0x0000000000000780
931#define BM_07_10 BM_10_07
932#define BM_11_07 0x0000000000000f80
933#define BM_07_11 BM_11_07
934#define BM_12_07 0x0000000000001f80
935#define BM_07_12 BM_12_07
936#define BM_13_07 0x0000000000003f80
937#define BM_07_13 BM_13_07
938#define BM_14_07 0x0000000000007f80
939#define BM_07_14 BM_14_07
940#define BM_15_07 0x000000000000ff80
941#define BM_07_15 BM_15_07
942#define BM_16_07 0x000000000001ff80
943#define BM_07_16 BM_16_07
944#define BM_17_07 0x000000000003ff80
945#define BM_07_17 BM_17_07
946#define BM_18_07 0x000000000007ff80
947#define BM_07_18 BM_18_07
948#define BM_19_07 0x00000000000fff80
949#define BM_07_19 BM_19_07
950#define BM_20_07 0x00000000001fff80
951#define BM_07_20 BM_20_07
952#define BM_21_07 0x00000000003fff80
953#define BM_07_21 BM_21_07
954#define BM_22_07 0x00000000007fff80
955#define BM_07_22 BM_22_07
956#define BM_23_07 0x0000000000ffff80
957#define BM_07_23 BM_23_07
958#define BM_24_07 0x0000000001ffff80
959#define BM_07_24 BM_24_07
960#define BM_25_07 0x0000000003ffff80
961#define BM_07_25 BM_25_07
962#define BM_26_07 0x0000000007ffff80
963#define BM_07_26 BM_26_07
964#define BM_27_07 0x000000000fffff80
965#define BM_07_27 BM_27_07
966#define BM_28_07 0x000000001fffff80
967#define BM_07_28 BM_28_07
968#define BM_29_07 0x000000003fffff80
969#define BM_07_29 BM_29_07
970#define BM_30_07 0x000000007fffff80
971#define BM_07_30 BM_30_07
972#define BM_31_07 0x00000000ffffff80
973#define BM_07_31 BM_31_07
974#define BM_32_07 0x00000001ffffff80
975#define BM_07_32 BM_32_07
976#define BM_33_07 0x00000003ffffff80
977#define BM_07_33 BM_33_07
978#define BM_34_07 0x00000007ffffff80
979#define BM_07_34 BM_34_07
980#define BM_35_07 0x0000000fffffff80
981#define BM_07_35 BM_35_07
982#define BM_36_07 0x0000001fffffff80
983#define BM_07_36 BM_36_07
984#define BM_37_07 0x0000003fffffff80
985#define BM_07_37 BM_37_07
986#define BM_38_07 0x0000007fffffff80
987#define BM_07_38 BM_38_07
988#define BM_39_07 0x000000ffffffff80
989#define BM_07_39 BM_39_07
990#define BM_40_07 0x000001ffffffff80
991#define BM_07_40 BM_40_07
992#define BM_41_07 0x000003ffffffff80
993#define BM_07_41 BM_41_07
994#define BM_42_07 0x000007ffffffff80
995#define BM_07_42 BM_42_07
996#define BM_43_07 0x00000fffffffff80
997#define BM_07_43 BM_43_07
998#define BM_44_07 0x00001fffffffff80
999#define BM_07_44 BM_44_07
1000#define BM_45_07 0x00003fffffffff80
1001#define BM_07_45 BM_45_07
1002#define BM_46_07 0x00007fffffffff80
1003#define BM_07_46 BM_46_07
1004#define BM_47_07 0x0000ffffffffff80
1005#define BM_07_47 BM_47_07
1006#define BM_48_07 0x0001ffffffffff80
1007#define BM_07_48 BM_48_07
1008#define BM_49_07 0x0003ffffffffff80
1009#define BM_07_49 BM_49_07
1010#define BM_50_07 0x0007ffffffffff80
1011#define BM_07_50 BM_50_07
1012#define BM_51_07 0x000fffffffffff80
1013#define BM_07_51 BM_51_07
1014#define BM_52_07 0x001fffffffffff80
1015#define BM_07_52 BM_52_07
1016#define BM_53_07 0x003fffffffffff80
1017#define BM_07_53 BM_53_07
1018#define BM_54_07 0x007fffffffffff80
1019#define BM_07_54 BM_54_07
1020#define BM_55_07 0x00ffffffffffff80
1021#define BM_07_55 BM_55_07
1022#define BM_56_07 0x01ffffffffffff80
1023#define BM_07_56 BM_56_07
1024#define BM_57_07 0x03ffffffffffff80
1025#define BM_07_57 BM_57_07
1026#define BM_58_07 0x07ffffffffffff80
1027#define BM_07_58 BM_58_07
1028#define BM_59_07 0x0fffffffffffff80
1029#define BM_07_59 BM_59_07
1030#define BM_60_07 0x1fffffffffffff80
1031#define BM_07_60 BM_60_07
1032#define BM_61_07 0x3fffffffffffff80
1033#define BM_07_61 BM_61_07
1034#define BM_62_07 0x7fffffffffffff80
1035#define BM_07_62 BM_62_07
1036#define BM_63_07 0xffffffffffffff80
1037#define BM_07_63 BM_63_07
1038#define BM_08_08 0x0000000000000100
1039#define BM_09_08 0x0000000000000300
1040#define BM_08_09 BM_09_08
1041#define BM_10_08 0x0000000000000700
1042#define BM_08_10 BM_10_08
1043#define BM_11_08 0x0000000000000f00
1044#define BM_08_11 BM_11_08
1045#define BM_12_08 0x0000000000001f00
1046#define BM_08_12 BM_12_08
1047#define BM_13_08 0x0000000000003f00
1048#define BM_08_13 BM_13_08
1049#define BM_14_08 0x0000000000007f00
1050#define BM_08_14 BM_14_08
1051#define BM_15_08 0x000000000000ff00
1052#define BM_08_15 BM_15_08
1053#define BM_16_08 0x000000000001ff00
1054#define BM_08_16 BM_16_08
1055#define BM_17_08 0x000000000003ff00
1056#define BM_08_17 BM_17_08
1057#define BM_18_08 0x000000000007ff00
1058#define BM_08_18 BM_18_08
1059#define BM_19_08 0x00000000000fff00
1060#define BM_08_19 BM_19_08
1061#define BM_20_08 0x00000000001fff00
1062#define BM_08_20 BM_20_08
1063#define BM_21_08 0x00000000003fff00
1064#define BM_08_21 BM_21_08
1065#define BM_22_08 0x00000000007fff00
1066#define BM_08_22 BM_22_08
1067#define BM_23_08 0x0000000000ffff00
1068#define BM_08_23 BM_23_08
1069#define BM_24_08 0x0000000001ffff00
1070#define BM_08_24 BM_24_08
1071#define BM_25_08 0x0000000003ffff00
1072#define BM_08_25 BM_25_08
1073#define BM_26_08 0x0000000007ffff00
1074#define BM_08_26 BM_26_08
1075#define BM_27_08 0x000000000fffff00
1076#define BM_08_27 BM_27_08
1077#define BM_28_08 0x000000001fffff00
1078#define BM_08_28 BM_28_08
1079#define BM_29_08 0x000000003fffff00
1080#define BM_08_29 BM_29_08
1081#define BM_30_08 0x000000007fffff00
1082#define BM_08_30 BM_30_08
1083#define BM_31_08 0x00000000ffffff00
1084#define BM_08_31 BM_31_08
1085#define BM_32_08 0x00000001ffffff00
1086#define BM_08_32 BM_32_08
1087#define BM_33_08 0x00000003ffffff00
1088#define BM_08_33 BM_33_08
1089#define BM_34_08 0x00000007ffffff00
1090#define BM_08_34 BM_34_08
1091#define BM_35_08 0x0000000fffffff00
1092#define BM_08_35 BM_35_08
1093#define BM_36_08 0x0000001fffffff00
1094#define BM_08_36 BM_36_08
1095#define BM_37_08 0x0000003fffffff00
1096#define BM_08_37 BM_37_08
1097#define BM_38_08 0x0000007fffffff00
1098#define BM_08_38 BM_38_08
1099#define BM_39_08 0x000000ffffffff00
1100#define BM_08_39 BM_39_08
1101#define BM_40_08 0x000001ffffffff00
1102#define BM_08_40 BM_40_08
1103#define BM_41_08 0x000003ffffffff00
1104#define BM_08_41 BM_41_08
1105#define BM_42_08 0x000007ffffffff00
1106#define BM_08_42 BM_42_08
1107#define BM_43_08 0x00000fffffffff00
1108#define BM_08_43 BM_43_08
1109#define BM_44_08 0x00001fffffffff00
1110#define BM_08_44 BM_44_08
1111#define BM_45_08 0x00003fffffffff00
1112#define BM_08_45 BM_45_08
1113#define BM_46_08 0x00007fffffffff00
1114#define BM_08_46 BM_46_08
1115#define BM_47_08 0x0000ffffffffff00
1116#define BM_08_47 BM_47_08
1117#define BM_48_08 0x0001ffffffffff00
1118#define BM_08_48 BM_48_08
1119#define BM_49_08 0x0003ffffffffff00
1120#define BM_08_49 BM_49_08
1121#define BM_50_08 0x0007ffffffffff00
1122#define BM_08_50 BM_50_08
1123#define BM_51_08 0x000fffffffffff00
1124#define BM_08_51 BM_51_08
1125#define BM_52_08 0x001fffffffffff00
1126#define BM_08_52 BM_52_08
1127#define BM_53_08 0x003fffffffffff00
1128#define BM_08_53 BM_53_08
1129#define BM_54_08 0x007fffffffffff00
1130#define BM_08_54 BM_54_08
1131#define BM_55_08 0x00ffffffffffff00
1132#define BM_08_55 BM_55_08
1133#define BM_56_08 0x01ffffffffffff00
1134#define BM_08_56 BM_56_08
1135#define BM_57_08 0x03ffffffffffff00
1136#define BM_08_57 BM_57_08
1137#define BM_58_08 0x07ffffffffffff00
1138#define BM_08_58 BM_58_08
1139#define BM_59_08 0x0fffffffffffff00
1140#define BM_08_59 BM_59_08
1141#define BM_60_08 0x1fffffffffffff00
1142#define BM_08_60 BM_60_08
1143#define BM_61_08 0x3fffffffffffff00
1144#define BM_08_61 BM_61_08
1145#define BM_62_08 0x7fffffffffffff00
1146#define BM_08_62 BM_62_08
1147#define BM_63_08 0xffffffffffffff00
1148#define BM_08_63 BM_63_08
1149#define BM_09_09 0x0000000000000200
1150#define BM_10_09 0x0000000000000600
1151#define BM_09_10 BM_10_09
1152#define BM_11_09 0x0000000000000e00
1153#define BM_09_11 BM_11_09
1154#define BM_12_09 0x0000000000001e00
1155#define BM_09_12 BM_12_09
1156#define BM_13_09 0x0000000000003e00
1157#define BM_09_13 BM_13_09
1158#define BM_14_09 0x0000000000007e00
1159#define BM_09_14 BM_14_09
1160#define BM_15_09 0x000000000000fe00
1161#define BM_09_15 BM_15_09
1162#define BM_16_09 0x000000000001fe00
1163#define BM_09_16 BM_16_09
1164#define BM_17_09 0x000000000003fe00
1165#define BM_09_17 BM_17_09
1166#define BM_18_09 0x000000000007fe00
1167#define BM_09_18 BM_18_09
1168#define BM_19_09 0x00000000000ffe00
1169#define BM_09_19 BM_19_09
1170#define BM_20_09 0x00000000001ffe00
1171#define BM_09_20 BM_20_09
1172#define BM_21_09 0x00000000003ffe00
1173#define BM_09_21 BM_21_09
1174#define BM_22_09 0x00000000007ffe00
1175#define BM_09_22 BM_22_09
1176#define BM_23_09 0x0000000000fffe00
1177#define BM_09_23 BM_23_09
1178#define BM_24_09 0x0000000001fffe00
1179#define BM_09_24 BM_24_09
1180#define BM_25_09 0x0000000003fffe00
1181#define BM_09_25 BM_25_09
1182#define BM_26_09 0x0000000007fffe00
1183#define BM_09_26 BM_26_09
1184#define BM_27_09 0x000000000ffffe00
1185#define BM_09_27 BM_27_09
1186#define BM_28_09 0x000000001ffffe00
1187#define BM_09_28 BM_28_09
1188#define BM_29_09 0x000000003ffffe00
1189#define BM_09_29 BM_29_09
1190#define BM_30_09 0x000000007ffffe00
1191#define BM_09_30 BM_30_09
1192#define BM_31_09 0x00000000fffffe00
1193#define BM_09_31 BM_31_09
1194#define BM_32_09 0x00000001fffffe00
1195#define BM_09_32 BM_32_09
1196#define BM_33_09 0x00000003fffffe00
1197#define BM_09_33 BM_33_09
1198#define BM_34_09 0x00000007fffffe00
1199#define BM_09_34 BM_34_09
1200#define BM_35_09 0x0000000ffffffe00
1201#define BM_09_35 BM_35_09
1202#define BM_36_09 0x0000001ffffffe00
1203#define BM_09_36 BM_36_09
1204#define BM_37_09 0x0000003ffffffe00
1205#define BM_09_37 BM_37_09
1206#define BM_38_09 0x0000007ffffffe00
1207#define BM_09_38 BM_38_09
1208#define BM_39_09 0x000000fffffffe00
1209#define BM_09_39 BM_39_09
1210#define BM_40_09 0x000001fffffffe00
1211#define BM_09_40 BM_40_09
1212#define BM_41_09 0x000003fffffffe00
1213#define BM_09_41 BM_41_09
1214#define BM_42_09 0x000007fffffffe00
1215#define BM_09_42 BM_42_09
1216#define BM_43_09 0x00000ffffffffe00
1217#define BM_09_43 BM_43_09
1218#define BM_44_09 0x00001ffffffffe00
1219#define BM_09_44 BM_44_09
1220#define BM_45_09 0x00003ffffffffe00
1221#define BM_09_45 BM_45_09
1222#define BM_46_09 0x00007ffffffffe00
1223#define BM_09_46 BM_46_09
1224#define BM_47_09 0x0000fffffffffe00
1225#define BM_09_47 BM_47_09
1226#define BM_48_09 0x0001fffffffffe00
1227#define BM_09_48 BM_48_09
1228#define BM_49_09 0x0003fffffffffe00
1229#define BM_09_49 BM_49_09
1230#define BM_50_09 0x0007fffffffffe00
1231#define BM_09_50 BM_50_09
1232#define BM_51_09 0x000ffffffffffe00
1233#define BM_09_51 BM_51_09
1234#define BM_52_09 0x001ffffffffffe00
1235#define BM_09_52 BM_52_09
1236#define BM_53_09 0x003ffffffffffe00
1237#define BM_09_53 BM_53_09
1238#define BM_54_09 0x007ffffffffffe00
1239#define BM_09_54 BM_54_09
1240#define BM_55_09 0x00fffffffffffe00
1241#define BM_09_55 BM_55_09
1242#define BM_56_09 0x01fffffffffffe00
1243#define BM_09_56 BM_56_09
1244#define BM_57_09 0x03fffffffffffe00
1245#define BM_09_57 BM_57_09
1246#define BM_58_09 0x07fffffffffffe00
1247#define BM_09_58 BM_58_09
1248#define BM_59_09 0x0ffffffffffffe00
1249#define BM_09_59 BM_59_09
1250#define BM_60_09 0x1ffffffffffffe00
1251#define BM_09_60 BM_60_09
1252#define BM_61_09 0x3ffffffffffffe00
1253#define BM_09_61 BM_61_09
1254#define BM_62_09 0x7ffffffffffffe00
1255#define BM_09_62 BM_62_09
1256#define BM_63_09 0xfffffffffffffe00
1257#define BM_09_63 BM_63_09
1258#define BM_10_10 0x0000000000000400
1259#define BM_11_10 0x0000000000000c00
1260#define BM_10_11 BM_11_10
1261#define BM_12_10 0x0000000000001c00
1262#define BM_10_12 BM_12_10
1263#define BM_13_10 0x0000000000003c00
1264#define BM_10_13 BM_13_10
1265#define BM_14_10 0x0000000000007c00
1266#define BM_10_14 BM_14_10
1267#define BM_15_10 0x000000000000fc00
1268#define BM_10_15 BM_15_10
1269#define BM_16_10 0x000000000001fc00
1270#define BM_10_16 BM_16_10
1271#define BM_17_10 0x000000000003fc00
1272#define BM_10_17 BM_17_10
1273#define BM_18_10 0x000000000007fc00
1274#define BM_10_18 BM_18_10
1275#define BM_19_10 0x00000000000ffc00
1276#define BM_10_19 BM_19_10
1277#define BM_20_10 0x00000000001ffc00
1278#define BM_10_20 BM_20_10
1279#define BM_21_10 0x00000000003ffc00
1280#define BM_10_21 BM_21_10
1281#define BM_22_10 0x00000000007ffc00
1282#define BM_10_22 BM_22_10
1283#define BM_23_10 0x0000000000fffc00
1284#define BM_10_23 BM_23_10
1285#define BM_24_10 0x0000000001fffc00
1286#define BM_10_24 BM_24_10
1287#define BM_25_10 0x0000000003fffc00
1288#define BM_10_25 BM_25_10
1289#define BM_26_10 0x0000000007fffc00
1290#define BM_10_26 BM_26_10
1291#define BM_27_10 0x000000000ffffc00
1292#define BM_10_27 BM_27_10
1293#define BM_28_10 0x000000001ffffc00
1294#define BM_10_28 BM_28_10
1295#define BM_29_10 0x000000003ffffc00
1296#define BM_10_29 BM_29_10
1297#define BM_30_10 0x000000007ffffc00
1298#define BM_10_30 BM_30_10
1299#define BM_31_10 0x00000000fffffc00
1300#define BM_10_31 BM_31_10
1301#define BM_32_10 0x00000001fffffc00
1302#define BM_10_32 BM_32_10
1303#define BM_33_10 0x00000003fffffc00
1304#define BM_10_33 BM_33_10
1305#define BM_34_10 0x00000007fffffc00
1306#define BM_10_34 BM_34_10
1307#define BM_35_10 0x0000000ffffffc00
1308#define BM_10_35 BM_35_10
1309#define BM_36_10 0x0000001ffffffc00
1310#define BM_10_36 BM_36_10
1311#define BM_37_10 0x0000003ffffffc00
1312#define BM_10_37 BM_37_10
1313#define BM_38_10 0x0000007ffffffc00
1314#define BM_10_38 BM_38_10
1315#define BM_39_10 0x000000fffffffc00
1316#define BM_10_39 BM_39_10
1317#define BM_40_10 0x000001fffffffc00
1318#define BM_10_40 BM_40_10
1319#define BM_41_10 0x000003fffffffc00
1320#define BM_10_41 BM_41_10
1321#define BM_42_10 0x000007fffffffc00
1322#define BM_10_42 BM_42_10
1323#define BM_43_10 0x00000ffffffffc00
1324#define BM_10_43 BM_43_10
1325#define BM_44_10 0x00001ffffffffc00
1326#define BM_10_44 BM_44_10
1327#define BM_45_10 0x00003ffffffffc00
1328#define BM_10_45 BM_45_10
1329#define BM_46_10 0x00007ffffffffc00
1330#define BM_10_46 BM_46_10
1331#define BM_47_10 0x0000fffffffffc00
1332#define BM_10_47 BM_47_10
1333#define BM_48_10 0x0001fffffffffc00
1334#define BM_10_48 BM_48_10
1335#define BM_49_10 0x0003fffffffffc00
1336#define BM_10_49 BM_49_10
1337#define BM_50_10 0x0007fffffffffc00
1338#define BM_10_50 BM_50_10
1339#define BM_51_10 0x000ffffffffffc00
1340#define BM_10_51 BM_51_10
1341#define BM_52_10 0x001ffffffffffc00
1342#define BM_10_52 BM_52_10
1343#define BM_53_10 0x003ffffffffffc00
1344#define BM_10_53 BM_53_10
1345#define BM_54_10 0x007ffffffffffc00
1346#define BM_10_54 BM_54_10
1347#define BM_55_10 0x00fffffffffffc00
1348#define BM_10_55 BM_55_10
1349#define BM_56_10 0x01fffffffffffc00
1350#define BM_10_56 BM_56_10
1351#define BM_57_10 0x03fffffffffffc00
1352#define BM_10_57 BM_57_10
1353#define BM_58_10 0x07fffffffffffc00
1354#define BM_10_58 BM_58_10
1355#define BM_59_10 0x0ffffffffffffc00
1356#define BM_10_59 BM_59_10
1357#define BM_60_10 0x1ffffffffffffc00
1358#define BM_10_60 BM_60_10
1359#define BM_61_10 0x3ffffffffffffc00
1360#define BM_10_61 BM_61_10
1361#define BM_62_10 0x7ffffffffffffc00
1362#define BM_10_62 BM_62_10
1363#define BM_63_10 0xfffffffffffffc00
1364#define BM_10_63 BM_63_10
1365#define BM_11_11 0x0000000000000800
1366#define BM_12_11 0x0000000000001800
1367#define BM_11_12 BM_12_11
1368#define BM_13_11 0x0000000000003800
1369#define BM_11_13 BM_13_11
1370#define BM_14_11 0x0000000000007800
1371#define BM_11_14 BM_14_11
1372#define BM_15_11 0x000000000000f800
1373#define BM_11_15 BM_15_11
1374#define BM_16_11 0x000000000001f800
1375#define BM_11_16 BM_16_11
1376#define BM_17_11 0x000000000003f800
1377#define BM_11_17 BM_17_11
1378#define BM_18_11 0x000000000007f800
1379#define BM_11_18 BM_18_11
1380#define BM_19_11 0x00000000000ff800
1381#define BM_11_19 BM_19_11
1382#define BM_20_11 0x00000000001ff800
1383#define BM_11_20 BM_20_11
1384#define BM_21_11 0x00000000003ff800
1385#define BM_11_21 BM_21_11
1386#define BM_22_11 0x00000000007ff800
1387#define BM_11_22 BM_22_11
1388#define BM_23_11 0x0000000000fff800
1389#define BM_11_23 BM_23_11
1390#define BM_24_11 0x0000000001fff800
1391#define BM_11_24 BM_24_11
1392#define BM_25_11 0x0000000003fff800
1393#define BM_11_25 BM_25_11
1394#define BM_26_11 0x0000000007fff800
1395#define BM_11_26 BM_26_11
1396#define BM_27_11 0x000000000ffff800
1397#define BM_11_27 BM_27_11
1398#define BM_28_11 0x000000001ffff800
1399#define BM_11_28 BM_28_11
1400#define BM_29_11 0x000000003ffff800
1401#define BM_11_29 BM_29_11
1402#define BM_30_11 0x000000007ffff800
1403#define BM_11_30 BM_30_11
1404#define BM_31_11 0x00000000fffff800
1405#define BM_11_31 BM_31_11
1406#define BM_32_11 0x00000001fffff800
1407#define BM_11_32 BM_32_11
1408#define BM_33_11 0x00000003fffff800
1409#define BM_11_33 BM_33_11
1410#define BM_34_11 0x00000007fffff800
1411#define BM_11_34 BM_34_11
1412#define BM_35_11 0x0000000ffffff800
1413#define BM_11_35 BM_35_11
1414#define BM_36_11 0x0000001ffffff800
1415#define BM_11_36 BM_36_11
1416#define BM_37_11 0x0000003ffffff800
1417#define BM_11_37 BM_37_11
1418#define BM_38_11 0x0000007ffffff800
1419#define BM_11_38 BM_38_11
1420#define BM_39_11 0x000000fffffff800
1421#define BM_11_39 BM_39_11
1422#define BM_40_11 0x000001fffffff800
1423#define BM_11_40 BM_40_11
1424#define BM_41_11 0x000003fffffff800
1425#define BM_11_41 BM_41_11
1426#define BM_42_11 0x000007fffffff800
1427#define BM_11_42 BM_42_11
1428#define BM_43_11 0x00000ffffffff800
1429#define BM_11_43 BM_43_11
1430#define BM_44_11 0x00001ffffffff800
1431#define BM_11_44 BM_44_11
1432#define BM_45_11 0x00003ffffffff800
1433#define BM_11_45 BM_45_11
1434#define BM_46_11 0x00007ffffffff800
1435#define BM_11_46 BM_46_11
1436#define BM_47_11 0x0000fffffffff800
1437#define BM_11_47 BM_47_11
1438#define BM_48_11 0x0001fffffffff800
1439#define BM_11_48 BM_48_11
1440#define BM_49_11 0x0003fffffffff800
1441#define BM_11_49 BM_49_11
1442#define BM_50_11 0x0007fffffffff800
1443#define BM_11_50 BM_50_11
1444#define BM_51_11 0x000ffffffffff800
1445#define BM_11_51 BM_51_11
1446#define BM_52_11 0x001ffffffffff800
1447#define BM_11_52 BM_52_11
1448#define BM_53_11 0x003ffffffffff800
1449#define BM_11_53 BM_53_11
1450#define BM_54_11 0x007ffffffffff800
1451#define BM_11_54 BM_54_11
1452#define BM_55_11 0x00fffffffffff800
1453#define BM_11_55 BM_55_11
1454#define BM_56_11 0x01fffffffffff800
1455#define BM_11_56 BM_56_11
1456#define BM_57_11 0x03fffffffffff800
1457#define BM_11_57 BM_57_11
1458#define BM_58_11 0x07fffffffffff800
1459#define BM_11_58 BM_58_11
1460#define BM_59_11 0x0ffffffffffff800
1461#define BM_11_59 BM_59_11
1462#define BM_60_11 0x1ffffffffffff800
1463#define BM_11_60 BM_60_11
1464#define BM_61_11 0x3ffffffffffff800
1465#define BM_11_61 BM_61_11
1466#define BM_62_11 0x7ffffffffffff800
1467#define BM_11_62 BM_62_11
1468#define BM_63_11 0xfffffffffffff800
1469#define BM_11_63 BM_63_11
1470#define BM_12_12 0x0000000000001000
1471#define BM_13_12 0x0000000000003000
1472#define BM_12_13 BM_13_12
1473#define BM_14_12 0x0000000000007000
1474#define BM_12_14 BM_14_12
1475#define BM_15_12 0x000000000000f000
1476#define BM_12_15 BM_15_12
1477#define BM_16_12 0x000000000001f000
1478#define BM_12_16 BM_16_12
1479#define BM_17_12 0x000000000003f000
1480#define BM_12_17 BM_17_12
1481#define BM_18_12 0x000000000007f000
1482#define BM_12_18 BM_18_12
1483#define BM_19_12 0x00000000000ff000
1484#define BM_12_19 BM_19_12
1485#define BM_20_12 0x00000000001ff000
1486#define BM_12_20 BM_20_12
1487#define BM_21_12 0x00000000003ff000
1488#define BM_12_21 BM_21_12
1489#define BM_22_12 0x00000000007ff000
1490#define BM_12_22 BM_22_12
1491#define BM_23_12 0x0000000000fff000
1492#define BM_12_23 BM_23_12
1493#define BM_24_12 0x0000000001fff000
1494#define BM_12_24 BM_24_12
1495#define BM_25_12 0x0000000003fff000
1496#define BM_12_25 BM_25_12
1497#define BM_26_12 0x0000000007fff000
1498#define BM_12_26 BM_26_12
1499#define BM_27_12 0x000000000ffff000
1500#define BM_12_27 BM_27_12
1501#define BM_28_12 0x000000001ffff000
1502#define BM_12_28 BM_28_12
1503#define BM_29_12 0x000000003ffff000
1504#define BM_12_29 BM_29_12
1505#define BM_30_12 0x000000007ffff000
1506#define BM_12_30 BM_30_12
1507#define BM_31_12 0x00000000fffff000
1508#define BM_12_31 BM_31_12
1509#define BM_32_12 0x00000001fffff000
1510#define BM_12_32 BM_32_12
1511#define BM_33_12 0x00000003fffff000
1512#define BM_12_33 BM_33_12
1513#define BM_34_12 0x00000007fffff000
1514#define BM_12_34 BM_34_12
1515#define BM_35_12 0x0000000ffffff000
1516#define BM_12_35 BM_35_12
1517#define BM_36_12 0x0000001ffffff000
1518#define BM_12_36 BM_36_12
1519#define BM_37_12 0x0000003ffffff000
1520#define BM_12_37 BM_37_12
1521#define BM_38_12 0x0000007ffffff000
1522#define BM_12_38 BM_38_12
1523#define BM_39_12 0x000000fffffff000
1524#define BM_12_39 BM_39_12
1525#define BM_40_12 0x000001fffffff000
1526#define BM_12_40 BM_40_12
1527#define BM_41_12 0x000003fffffff000
1528#define BM_12_41 BM_41_12
1529#define BM_42_12 0x000007fffffff000
1530#define BM_12_42 BM_42_12
1531#define BM_43_12 0x00000ffffffff000
1532#define BM_12_43 BM_43_12
1533#define BM_44_12 0x00001ffffffff000
1534#define BM_12_44 BM_44_12
1535#define BM_45_12 0x00003ffffffff000
1536#define BM_12_45 BM_45_12
1537#define BM_46_12 0x00007ffffffff000
1538#define BM_12_46 BM_46_12
1539#define BM_47_12 0x0000fffffffff000
1540#define BM_12_47 BM_47_12
1541#define BM_48_12 0x0001fffffffff000
1542#define BM_12_48 BM_48_12
1543#define BM_49_12 0x0003fffffffff000
1544#define BM_12_49 BM_49_12
1545#define BM_50_12 0x0007fffffffff000
1546#define BM_12_50 BM_50_12
1547#define BM_51_12 0x000ffffffffff000
1548#define BM_12_51 BM_51_12
1549#define BM_52_12 0x001ffffffffff000
1550#define BM_12_52 BM_52_12
1551#define BM_53_12 0x003ffffffffff000
1552#define BM_12_53 BM_53_12
1553#define BM_54_12 0x007ffffffffff000
1554#define BM_12_54 BM_54_12
1555#define BM_55_12 0x00fffffffffff000
1556#define BM_12_55 BM_55_12
1557#define BM_56_12 0x01fffffffffff000
1558#define BM_12_56 BM_56_12
1559#define BM_57_12 0x03fffffffffff000
1560#define BM_12_57 BM_57_12
1561#define BM_58_12 0x07fffffffffff000
1562#define BM_12_58 BM_58_12
1563#define BM_59_12 0x0ffffffffffff000
1564#define BM_12_59 BM_59_12
1565#define BM_60_12 0x1ffffffffffff000
1566#define BM_12_60 BM_60_12
1567#define BM_61_12 0x3ffffffffffff000
1568#define BM_12_61 BM_61_12
1569#define BM_62_12 0x7ffffffffffff000
1570#define BM_12_62 BM_62_12
1571#define BM_63_12 0xfffffffffffff000
1572#define BM_12_63 BM_63_12
1573#define BM_13_13 0x0000000000002000
1574#define BM_14_13 0x0000000000006000
1575#define BM_13_14 BM_14_13
1576#define BM_15_13 0x000000000000e000
1577#define BM_13_15 BM_15_13
1578#define BM_16_13 0x000000000001e000
1579#define BM_13_16 BM_16_13
1580#define BM_17_13 0x000000000003e000
1581#define BM_13_17 BM_17_13
1582#define BM_18_13 0x000000000007e000
1583#define BM_13_18 BM_18_13
1584#define BM_19_13 0x00000000000fe000
1585#define BM_13_19 BM_19_13
1586#define BM_20_13 0x00000000001fe000
1587#define BM_13_20 BM_20_13
1588#define BM_21_13 0x00000000003fe000
1589#define BM_13_21 BM_21_13
1590#define BM_22_13 0x00000000007fe000
1591#define BM_13_22 BM_22_13
1592#define BM_23_13 0x0000000000ffe000
1593#define BM_13_23 BM_23_13
1594#define BM_24_13 0x0000000001ffe000
1595#define BM_13_24 BM_24_13
1596#define BM_25_13 0x0000000003ffe000
1597#define BM_13_25 BM_25_13
1598#define BM_26_13 0x0000000007ffe000
1599#define BM_13_26 BM_26_13
1600#define BM_27_13 0x000000000fffe000
1601#define BM_13_27 BM_27_13
1602#define BM_28_13 0x000000001fffe000
1603#define BM_13_28 BM_28_13
1604#define BM_29_13 0x000000003fffe000
1605#define BM_13_29 BM_29_13
1606#define BM_30_13 0x000000007fffe000
1607#define BM_13_30 BM_30_13
1608#define BM_31_13 0x00000000ffffe000
1609#define BM_13_31 BM_31_13
1610#define BM_32_13 0x00000001ffffe000
1611#define BM_13_32 BM_32_13
1612#define BM_33_13 0x00000003ffffe000
1613#define BM_13_33 BM_33_13
1614#define BM_34_13 0x00000007ffffe000
1615#define BM_13_34 BM_34_13
1616#define BM_35_13 0x0000000fffffe000
1617#define BM_13_35 BM_35_13
1618#define BM_36_13 0x0000001fffffe000
1619#define BM_13_36 BM_36_13
1620#define BM_37_13 0x0000003fffffe000
1621#define BM_13_37 BM_37_13
1622#define BM_38_13 0x0000007fffffe000
1623#define BM_13_38 BM_38_13
1624#define BM_39_13 0x000000ffffffe000
1625#define BM_13_39 BM_39_13
1626#define BM_40_13 0x000001ffffffe000
1627#define BM_13_40 BM_40_13
1628#define BM_41_13 0x000003ffffffe000
1629#define BM_13_41 BM_41_13
1630#define BM_42_13 0x000007ffffffe000
1631#define BM_13_42 BM_42_13
1632#define BM_43_13 0x00000fffffffe000
1633#define BM_13_43 BM_43_13
1634#define BM_44_13 0x00001fffffffe000
1635#define BM_13_44 BM_44_13
1636#define BM_45_13 0x00003fffffffe000
1637#define BM_13_45 BM_45_13
1638#define BM_46_13 0x00007fffffffe000
1639#define BM_13_46 BM_46_13
1640#define BM_47_13 0x0000ffffffffe000
1641#define BM_13_47 BM_47_13
1642#define BM_48_13 0x0001ffffffffe000
1643#define BM_13_48 BM_48_13
1644#define BM_49_13 0x0003ffffffffe000
1645#define BM_13_49 BM_49_13
1646#define BM_50_13 0x0007ffffffffe000
1647#define BM_13_50 BM_50_13
1648#define BM_51_13 0x000fffffffffe000
1649#define BM_13_51 BM_51_13
1650#define BM_52_13 0x001fffffffffe000
1651#define BM_13_52 BM_52_13
1652#define BM_53_13 0x003fffffffffe000
1653#define BM_13_53 BM_53_13
1654#define BM_54_13 0x007fffffffffe000
1655#define BM_13_54 BM_54_13
1656#define BM_55_13 0x00ffffffffffe000
1657#define BM_13_55 BM_55_13
1658#define BM_56_13 0x01ffffffffffe000
1659#define BM_13_56 BM_56_13
1660#define BM_57_13 0x03ffffffffffe000
1661#define BM_13_57 BM_57_13
1662#define BM_58_13 0x07ffffffffffe000
1663#define BM_13_58 BM_58_13
1664#define BM_59_13 0x0fffffffffffe000
1665#define BM_13_59 BM_59_13
1666#define BM_60_13 0x1fffffffffffe000
1667#define BM_13_60 BM_60_13
1668#define BM_61_13 0x3fffffffffffe000
1669#define BM_13_61 BM_61_13
1670#define BM_62_13 0x7fffffffffffe000
1671#define BM_13_62 BM_62_13
1672#define BM_63_13 0xffffffffffffe000
1673#define BM_13_63 BM_63_13
1674#define BM_14_14 0x0000000000004000
1675#define BM_15_14 0x000000000000c000
1676#define BM_14_15 BM_15_14
1677#define BM_16_14 0x000000000001c000
1678#define BM_14_16 BM_16_14
1679#define BM_17_14 0x000000000003c000
1680#define BM_14_17 BM_17_14
1681#define BM_18_14 0x000000000007c000
1682#define BM_14_18 BM_18_14
1683#define BM_19_14 0x00000000000fc000
1684#define BM_14_19 BM_19_14
1685#define BM_20_14 0x00000000001fc000
1686#define BM_14_20 BM_20_14
1687#define BM_21_14 0x00000000003fc000
1688#define BM_14_21 BM_21_14
1689#define BM_22_14 0x00000000007fc000
1690#define BM_14_22 BM_22_14
1691#define BM_23_14 0x0000000000ffc000
1692#define BM_14_23 BM_23_14
1693#define BM_24_14 0x0000000001ffc000
1694#define BM_14_24 BM_24_14
1695#define BM_25_14 0x0000000003ffc000
1696#define BM_14_25 BM_25_14
1697#define BM_26_14 0x0000000007ffc000
1698#define BM_14_26 BM_26_14
1699#define BM_27_14 0x000000000fffc000
1700#define BM_14_27 BM_27_14
1701#define BM_28_14 0x000000001fffc000
1702#define BM_14_28 BM_28_14
1703#define BM_29_14 0x000000003fffc000
1704#define BM_14_29 BM_29_14
1705#define BM_30_14 0x000000007fffc000
1706#define BM_14_30 BM_30_14
1707#define BM_31_14 0x00000000ffffc000
1708#define BM_14_31 BM_31_14
1709#define BM_32_14 0x00000001ffffc000
1710#define BM_14_32 BM_32_14
1711#define BM_33_14 0x00000003ffffc000
1712#define BM_14_33 BM_33_14
1713#define BM_34_14 0x00000007ffffc000
1714#define BM_14_34 BM_34_14
1715#define BM_35_14 0x0000000fffffc000
1716#define BM_14_35 BM_35_14
1717#define BM_36_14 0x0000001fffffc000
1718#define BM_14_36 BM_36_14
1719#define BM_37_14 0x0000003fffffc000
1720#define BM_14_37 BM_37_14
1721#define BM_38_14 0x0000007fffffc000
1722#define BM_14_38 BM_38_14
1723#define BM_39_14 0x000000ffffffc000
1724#define BM_14_39 BM_39_14
1725#define BM_40_14 0x000001ffffffc000
1726#define BM_14_40 BM_40_14
1727#define BM_41_14 0x000003ffffffc000
1728#define BM_14_41 BM_41_14
1729#define BM_42_14 0x000007ffffffc000
1730#define BM_14_42 BM_42_14
1731#define BM_43_14 0x00000fffffffc000
1732#define BM_14_43 BM_43_14
1733#define BM_44_14 0x00001fffffffc000
1734#define BM_14_44 BM_44_14
1735#define BM_45_14 0x00003fffffffc000
1736#define BM_14_45 BM_45_14
1737#define BM_46_14 0x00007fffffffc000
1738#define BM_14_46 BM_46_14
1739#define BM_47_14 0x0000ffffffffc000
1740#define BM_14_47 BM_47_14
1741#define BM_48_14 0x0001ffffffffc000
1742#define BM_14_48 BM_48_14
1743#define BM_49_14 0x0003ffffffffc000
1744#define BM_14_49 BM_49_14
1745#define BM_50_14 0x0007ffffffffc000
1746#define BM_14_50 BM_50_14
1747#define BM_51_14 0x000fffffffffc000
1748#define BM_14_51 BM_51_14
1749#define BM_52_14 0x001fffffffffc000
1750#define BM_14_52 BM_52_14
1751#define BM_53_14 0x003fffffffffc000
1752#define BM_14_53 BM_53_14
1753#define BM_54_14 0x007fffffffffc000
1754#define BM_14_54 BM_54_14
1755#define BM_55_14 0x00ffffffffffc000
1756#define BM_14_55 BM_55_14
1757#define BM_56_14 0x01ffffffffffc000
1758#define BM_14_56 BM_56_14
1759#define BM_57_14 0x03ffffffffffc000
1760#define BM_14_57 BM_57_14
1761#define BM_58_14 0x07ffffffffffc000
1762#define BM_14_58 BM_58_14
1763#define BM_59_14 0x0fffffffffffc000
1764#define BM_14_59 BM_59_14
1765#define BM_60_14 0x1fffffffffffc000
1766#define BM_14_60 BM_60_14
1767#define BM_61_14 0x3fffffffffffc000
1768#define BM_14_61 BM_61_14
1769#define BM_62_14 0x7fffffffffffc000
1770#define BM_14_62 BM_62_14
1771#define BM_63_14 0xffffffffffffc000
1772#define BM_14_63 BM_63_14
1773#define BM_15_15 0x0000000000008000
1774#define BM_16_15 0x0000000000018000
1775#define BM_15_16 BM_16_15
1776#define BM_17_15 0x0000000000038000
1777#define BM_15_17 BM_17_15
1778#define BM_18_15 0x0000000000078000
1779#define BM_15_18 BM_18_15
1780#define BM_19_15 0x00000000000f8000
1781#define BM_15_19 BM_19_15
1782#define BM_20_15 0x00000000001f8000
1783#define BM_15_20 BM_20_15
1784#define BM_21_15 0x00000000003f8000
1785#define BM_15_21 BM_21_15
1786#define BM_22_15 0x00000000007f8000
1787#define BM_15_22 BM_22_15
1788#define BM_23_15 0x0000000000ff8000
1789#define BM_15_23 BM_23_15
1790#define BM_24_15 0x0000000001ff8000
1791#define BM_15_24 BM_24_15
1792#define BM_25_15 0x0000000003ff8000
1793#define BM_15_25 BM_25_15
1794#define BM_26_15 0x0000000007ff8000
1795#define BM_15_26 BM_26_15
1796#define BM_27_15 0x000000000fff8000
1797#define BM_15_27 BM_27_15
1798#define BM_28_15 0x000000001fff8000
1799#define BM_15_28 BM_28_15
1800#define BM_29_15 0x000000003fff8000
1801#define BM_15_29 BM_29_15
1802#define BM_30_15 0x000000007fff8000
1803#define BM_15_30 BM_30_15
1804#define BM_31_15 0x00000000ffff8000
1805#define BM_15_31 BM_31_15
1806#define BM_32_15 0x00000001ffff8000
1807#define BM_15_32 BM_32_15
1808#define BM_33_15 0x00000003ffff8000
1809#define BM_15_33 BM_33_15
1810#define BM_34_15 0x00000007ffff8000
1811#define BM_15_34 BM_34_15
1812#define BM_35_15 0x0000000fffff8000
1813#define BM_15_35 BM_35_15
1814#define BM_36_15 0x0000001fffff8000
1815#define BM_15_36 BM_36_15
1816#define BM_37_15 0x0000003fffff8000
1817#define BM_15_37 BM_37_15
1818#define BM_38_15 0x0000007fffff8000
1819#define BM_15_38 BM_38_15
1820#define BM_39_15 0x000000ffffff8000
1821#define BM_15_39 BM_39_15
1822#define BM_40_15 0x000001ffffff8000
1823#define BM_15_40 BM_40_15
1824#define BM_41_15 0x000003ffffff8000
1825#define BM_15_41 BM_41_15
1826#define BM_42_15 0x000007ffffff8000
1827#define BM_15_42 BM_42_15
1828#define BM_43_15 0x00000fffffff8000
1829#define BM_15_43 BM_43_15
1830#define BM_44_15 0x00001fffffff8000
1831#define BM_15_44 BM_44_15
1832#define BM_45_15 0x00003fffffff8000
1833#define BM_15_45 BM_45_15
1834#define BM_46_15 0x00007fffffff8000
1835#define BM_15_46 BM_46_15
1836#define BM_47_15 0x0000ffffffff8000
1837#define BM_15_47 BM_47_15
1838#define BM_48_15 0x0001ffffffff8000
1839#define BM_15_48 BM_48_15
1840#define BM_49_15 0x0003ffffffff8000
1841#define BM_15_49 BM_49_15
1842#define BM_50_15 0x0007ffffffff8000
1843#define BM_15_50 BM_50_15
1844#define BM_51_15 0x000fffffffff8000
1845#define BM_15_51 BM_51_15
1846#define BM_52_15 0x001fffffffff8000
1847#define BM_15_52 BM_52_15
1848#define BM_53_15 0x003fffffffff8000
1849#define BM_15_53 BM_53_15
1850#define BM_54_15 0x007fffffffff8000
1851#define BM_15_54 BM_54_15
1852#define BM_55_15 0x00ffffffffff8000
1853#define BM_15_55 BM_55_15
1854#define BM_56_15 0x01ffffffffff8000
1855#define BM_15_56 BM_56_15
1856#define BM_57_15 0x03ffffffffff8000
1857#define BM_15_57 BM_57_15
1858#define BM_58_15 0x07ffffffffff8000
1859#define BM_15_58 BM_58_15
1860#define BM_59_15 0x0fffffffffff8000
1861#define BM_15_59 BM_59_15
1862#define BM_60_15 0x1fffffffffff8000
1863#define BM_15_60 BM_60_15
1864#define BM_61_15 0x3fffffffffff8000
1865#define BM_15_61 BM_61_15
1866#define BM_62_15 0x7fffffffffff8000
1867#define BM_15_62 BM_62_15
1868#define BM_63_15 0xffffffffffff8000
1869#define BM_15_63 BM_63_15
1870#define BM_16_16 0x0000000000010000
1871#define BM_17_16 0x0000000000030000
1872#define BM_16_17 BM_17_16
1873#define BM_18_16 0x0000000000070000
1874#define BM_16_18 BM_18_16
1875#define BM_19_16 0x00000000000f0000
1876#define BM_16_19 BM_19_16
1877#define BM_20_16 0x00000000001f0000
1878#define BM_16_20 BM_20_16
1879#define BM_21_16 0x00000000003f0000
1880#define BM_16_21 BM_21_16
1881#define BM_22_16 0x00000000007f0000
1882#define BM_16_22 BM_22_16
1883#define BM_23_16 0x0000000000ff0000
1884#define BM_16_23 BM_23_16
1885#define BM_24_16 0x0000000001ff0000
1886#define BM_16_24 BM_24_16
1887#define BM_25_16 0x0000000003ff0000
1888#define BM_16_25 BM_25_16
1889#define BM_26_16 0x0000000007ff0000
1890#define BM_16_26 BM_26_16
1891#define BM_27_16 0x000000000fff0000
1892#define BM_16_27 BM_27_16
1893#define BM_28_16 0x000000001fff0000
1894#define BM_16_28 BM_28_16
1895#define BM_29_16 0x000000003fff0000
1896#define BM_16_29 BM_29_16
1897#define BM_30_16 0x000000007fff0000
1898#define BM_16_30 BM_30_16
1899#define BM_31_16 0x00000000ffff0000
1900#define BM_16_31 BM_31_16
1901#define BM_32_16 0x00000001ffff0000
1902#define BM_16_32 BM_32_16
1903#define BM_33_16 0x00000003ffff0000
1904#define BM_16_33 BM_33_16
1905#define BM_34_16 0x00000007ffff0000
1906#define BM_16_34 BM_34_16
1907#define BM_35_16 0x0000000fffff0000
1908#define BM_16_35 BM_35_16
1909#define BM_36_16 0x0000001fffff0000
1910#define BM_16_36 BM_36_16
1911#define BM_37_16 0x0000003fffff0000
1912#define BM_16_37 BM_37_16
1913#define BM_38_16 0x0000007fffff0000
1914#define BM_16_38 BM_38_16
1915#define BM_39_16 0x000000ffffff0000
1916#define BM_16_39 BM_39_16
1917#define BM_40_16 0x000001ffffff0000
1918#define BM_16_40 BM_40_16
1919#define BM_41_16 0x000003ffffff0000
1920#define BM_16_41 BM_41_16
1921#define BM_42_16 0x000007ffffff0000
1922#define BM_16_42 BM_42_16
1923#define BM_43_16 0x00000fffffff0000
1924#define BM_16_43 BM_43_16
1925#define BM_44_16 0x00001fffffff0000
1926#define BM_16_44 BM_44_16
1927#define BM_45_16 0x00003fffffff0000
1928#define BM_16_45 BM_45_16
1929#define BM_46_16 0x00007fffffff0000
1930#define BM_16_46 BM_46_16
1931#define BM_47_16 0x0000ffffffff0000
1932#define BM_16_47 BM_47_16
1933#define BM_48_16 0x0001ffffffff0000
1934#define BM_16_48 BM_48_16
1935#define BM_49_16 0x0003ffffffff0000
1936#define BM_16_49 BM_49_16
1937#define BM_50_16 0x0007ffffffff0000
1938#define BM_16_50 BM_50_16
1939#define BM_51_16 0x000fffffffff0000
1940#define BM_16_51 BM_51_16
1941#define BM_52_16 0x001fffffffff0000
1942#define BM_16_52 BM_52_16
1943#define BM_53_16 0x003fffffffff0000
1944#define BM_16_53 BM_53_16
1945#define BM_54_16 0x007fffffffff0000
1946#define BM_16_54 BM_54_16
1947#define BM_55_16 0x00ffffffffff0000
1948#define BM_16_55 BM_55_16
1949#define BM_56_16 0x01ffffffffff0000
1950#define BM_16_56 BM_56_16
1951#define BM_57_16 0x03ffffffffff0000
1952#define BM_16_57 BM_57_16
1953#define BM_58_16 0x07ffffffffff0000
1954#define BM_16_58 BM_58_16
1955#define BM_59_16 0x0fffffffffff0000
1956#define BM_16_59 BM_59_16
1957#define BM_60_16 0x1fffffffffff0000
1958#define BM_16_60 BM_60_16
1959#define BM_61_16 0x3fffffffffff0000
1960#define BM_16_61 BM_61_16
1961#define BM_62_16 0x7fffffffffff0000
1962#define BM_16_62 BM_62_16
1963#define BM_63_16 0xffffffffffff0000
1964#define BM_16_63 BM_63_16
1965#define BM_17_17 0x0000000000020000
1966#define BM_18_17 0x0000000000060000
1967#define BM_17_18 BM_18_17
1968#define BM_19_17 0x00000000000e0000
1969#define BM_17_19 BM_19_17
1970#define BM_20_17 0x00000000001e0000
1971#define BM_17_20 BM_20_17
1972#define BM_21_17 0x00000000003e0000
1973#define BM_17_21 BM_21_17
1974#define BM_22_17 0x00000000007e0000
1975#define BM_17_22 BM_22_17
1976#define BM_23_17 0x0000000000fe0000
1977#define BM_17_23 BM_23_17
1978#define BM_24_17 0x0000000001fe0000
1979#define BM_17_24 BM_24_17
1980#define BM_25_17 0x0000000003fe0000
1981#define BM_17_25 BM_25_17
1982#define BM_26_17 0x0000000007fe0000
1983#define BM_17_26 BM_26_17
1984#define BM_27_17 0x000000000ffe0000
1985#define BM_17_27 BM_27_17
1986#define BM_28_17 0x000000001ffe0000
1987#define BM_17_28 BM_28_17
1988#define BM_29_17 0x000000003ffe0000
1989#define BM_17_29 BM_29_17
1990#define BM_30_17 0x000000007ffe0000
1991#define BM_17_30 BM_30_17
1992#define BM_31_17 0x00000000fffe0000
1993#define BM_17_31 BM_31_17
1994#define BM_32_17 0x00000001fffe0000
1995#define BM_17_32 BM_32_17
1996#define BM_33_17 0x00000003fffe0000
1997#define BM_17_33 BM_33_17
1998#define BM_34_17 0x00000007fffe0000
1999#define BM_17_34 BM_34_17
2000#define BM_35_17 0x0000000ffffe0000
2001#define BM_17_35 BM_35_17
2002#define BM_36_17 0x0000001ffffe0000
2003#define BM_17_36 BM_36_17
2004#define BM_37_17 0x0000003ffffe0000
2005#define BM_17_37 BM_37_17
2006#define BM_38_17 0x0000007ffffe0000
2007#define BM_17_38 BM_38_17
2008#define BM_39_17 0x000000fffffe0000
2009#define BM_17_39 BM_39_17
2010#define BM_40_17 0x000001fffffe0000
2011#define BM_17_40 BM_40_17
2012#define BM_41_17 0x000003fffffe0000
2013#define BM_17_41 BM_41_17
2014#define BM_42_17 0x000007fffffe0000
2015#define BM_17_42 BM_42_17
2016#define BM_43_17 0x00000ffffffe0000
2017#define BM_17_43 BM_43_17
2018#define BM_44_17 0x00001ffffffe0000
2019#define BM_17_44 BM_44_17
2020#define BM_45_17 0x00003ffffffe0000
2021#define BM_17_45 BM_45_17
2022#define BM_46_17 0x00007ffffffe0000
2023#define BM_17_46 BM_46_17
2024#define BM_47_17 0x0000fffffffe0000
2025#define BM_17_47 BM_47_17
2026#define BM_48_17 0x0001fffffffe0000
2027#define BM_17_48 BM_48_17
2028#define BM_49_17 0x0003fffffffe0000
2029#define BM_17_49 BM_49_17
2030#define BM_50_17 0x0007fffffffe0000
2031#define BM_17_50 BM_50_17
2032#define BM_51_17 0x000ffffffffe0000
2033#define BM_17_51 BM_51_17
2034#define BM_52_17 0x001ffffffffe0000
2035#define BM_17_52 BM_52_17
2036#define BM_53_17 0x003ffffffffe0000
2037#define BM_17_53 BM_53_17
2038#define BM_54_17 0x007ffffffffe0000
2039#define BM_17_54 BM_54_17
2040#define BM_55_17 0x00fffffffffe0000
2041#define BM_17_55 BM_55_17
2042#define BM_56_17 0x01fffffffffe0000
2043#define BM_17_56 BM_56_17
2044#define BM_57_17 0x03fffffffffe0000
2045#define BM_17_57 BM_57_17
2046#define BM_58_17 0x07fffffffffe0000
2047#define BM_17_58 BM_58_17
2048#define BM_59_17 0x0ffffffffffe0000
2049#define BM_17_59 BM_59_17
2050#define BM_60_17 0x1ffffffffffe0000
2051#define BM_17_60 BM_60_17
2052#define BM_61_17 0x3ffffffffffe0000
2053#define BM_17_61 BM_61_17
2054#define BM_62_17 0x7ffffffffffe0000
2055#define BM_17_62 BM_62_17
2056#define BM_63_17 0xfffffffffffe0000
2057#define BM_17_63 BM_63_17
2058#define BM_18_18 0x0000000000040000
2059#define BM_19_18 0x00000000000c0000
2060#define BM_18_19 BM_19_18
2061#define BM_20_18 0x00000000001c0000
2062#define BM_18_20 BM_20_18
2063#define BM_21_18 0x00000000003c0000
2064#define BM_18_21 BM_21_18
2065#define BM_22_18 0x00000000007c0000
2066#define BM_18_22 BM_22_18
2067#define BM_23_18 0x0000000000fc0000
2068#define BM_18_23 BM_23_18
2069#define BM_24_18 0x0000000001fc0000
2070#define BM_18_24 BM_24_18
2071#define BM_25_18 0x0000000003fc0000
2072#define BM_18_25 BM_25_18
2073#define BM_26_18 0x0000000007fc0000
2074#define BM_18_26 BM_26_18
2075#define BM_27_18 0x000000000ffc0000
2076#define BM_18_27 BM_27_18
2077#define BM_28_18 0x000000001ffc0000
2078#define BM_18_28 BM_28_18
2079#define BM_29_18 0x000000003ffc0000
2080#define BM_18_29 BM_29_18
2081#define BM_30_18 0x000000007ffc0000
2082#define BM_18_30 BM_30_18
2083#define BM_31_18 0x00000000fffc0000
2084#define BM_18_31 BM_31_18
2085#define BM_32_18 0x00000001fffc0000
2086#define BM_18_32 BM_32_18
2087#define BM_33_18 0x00000003fffc0000
2088#define BM_18_33 BM_33_18
2089#define BM_34_18 0x00000007fffc0000
2090#define BM_18_34 BM_34_18
2091#define BM_35_18 0x0000000ffffc0000
2092#define BM_18_35 BM_35_18
2093#define BM_36_18 0x0000001ffffc0000
2094#define BM_18_36 BM_36_18
2095#define BM_37_18 0x0000003ffffc0000
2096#define BM_18_37 BM_37_18
2097#define BM_38_18 0x0000007ffffc0000
2098#define BM_18_38 BM_38_18
2099#define BM_39_18 0x000000fffffc0000
2100#define BM_18_39 BM_39_18
2101#define BM_40_18 0x000001fffffc0000
2102#define BM_18_40 BM_40_18
2103#define BM_41_18 0x000003fffffc0000
2104#define BM_18_41 BM_41_18
2105#define BM_42_18 0x000007fffffc0000
2106#define BM_18_42 BM_42_18
2107#define BM_43_18 0x00000ffffffc0000
2108#define BM_18_43 BM_43_18
2109#define BM_44_18 0x00001ffffffc0000
2110#define BM_18_44 BM_44_18
2111#define BM_45_18 0x00003ffffffc0000
2112#define BM_18_45 BM_45_18
2113#define BM_46_18 0x00007ffffffc0000
2114#define BM_18_46 BM_46_18
2115#define BM_47_18 0x0000fffffffc0000
2116#define BM_18_47 BM_47_18
2117#define BM_48_18 0x0001fffffffc0000
2118#define BM_18_48 BM_48_18
2119#define BM_49_18 0x0003fffffffc0000
2120#define BM_18_49 BM_49_18
2121#define BM_50_18 0x0007fffffffc0000
2122#define BM_18_50 BM_50_18
2123#define BM_51_18 0x000ffffffffc0000
2124#define BM_18_51 BM_51_18
2125#define BM_52_18 0x001ffffffffc0000
2126#define BM_18_52 BM_52_18
2127#define BM_53_18 0x003ffffffffc0000
2128#define BM_18_53 BM_53_18
2129#define BM_54_18 0x007ffffffffc0000
2130#define BM_18_54 BM_54_18
2131#define BM_55_18 0x00fffffffffc0000
2132#define BM_18_55 BM_55_18
2133#define BM_56_18 0x01fffffffffc0000
2134#define BM_18_56 BM_56_18
2135#define BM_57_18 0x03fffffffffc0000
2136#define BM_18_57 BM_57_18
2137#define BM_58_18 0x07fffffffffc0000
2138#define BM_18_58 BM_58_18
2139#define BM_59_18 0x0ffffffffffc0000
2140#define BM_18_59 BM_59_18
2141#define BM_60_18 0x1ffffffffffc0000
2142#define BM_18_60 BM_60_18
2143#define BM_61_18 0x3ffffffffffc0000
2144#define BM_18_61 BM_61_18
2145#define BM_62_18 0x7ffffffffffc0000
2146#define BM_18_62 BM_62_18
2147#define BM_63_18 0xfffffffffffc0000
2148#define BM_18_63 BM_63_18
2149#define BM_19_19 0x0000000000080000
2150#define BM_20_19 0x0000000000180000
2151#define BM_19_20 BM_20_19
2152#define BM_21_19 0x0000000000380000
2153#define BM_19_21 BM_21_19
2154#define BM_22_19 0x0000000000780000
2155#define BM_19_22 BM_22_19
2156#define BM_23_19 0x0000000000f80000
2157#define BM_19_23 BM_23_19
2158#define BM_24_19 0x0000000001f80000
2159#define BM_19_24 BM_24_19
2160#define BM_25_19 0x0000000003f80000
2161#define BM_19_25 BM_25_19
2162#define BM_26_19 0x0000000007f80000
2163#define BM_19_26 BM_26_19
2164#define BM_27_19 0x000000000ff80000
2165#define BM_19_27 BM_27_19
2166#define BM_28_19 0x000000001ff80000
2167#define BM_19_28 BM_28_19
2168#define BM_29_19 0x000000003ff80000
2169#define BM_19_29 BM_29_19
2170#define BM_30_19 0x000000007ff80000
2171#define BM_19_30 BM_30_19
2172#define BM_31_19 0x00000000fff80000
2173#define BM_19_31 BM_31_19
2174#define BM_32_19 0x00000001fff80000
2175#define BM_19_32 BM_32_19
2176#define BM_33_19 0x00000003fff80000
2177#define BM_19_33 BM_33_19
2178#define BM_34_19 0x00000007fff80000
2179#define BM_19_34 BM_34_19
2180#define BM_35_19 0x0000000ffff80000
2181#define BM_19_35 BM_35_19
2182#define BM_36_19 0x0000001ffff80000
2183#define BM_19_36 BM_36_19
2184#define BM_37_19 0x0000003ffff80000
2185#define BM_19_37 BM_37_19
2186#define BM_38_19 0x0000007ffff80000
2187#define BM_19_38 BM_38_19
2188#define BM_39_19 0x000000fffff80000
2189#define BM_19_39 BM_39_19
2190#define BM_40_19 0x000001fffff80000
2191#define BM_19_40 BM_40_19
2192#define BM_41_19 0x000003fffff80000
2193#define BM_19_41 BM_41_19
2194#define BM_42_19 0x000007fffff80000
2195#define BM_19_42 BM_42_19
2196#define BM_43_19 0x00000ffffff80000
2197#define BM_19_43 BM_43_19
2198#define BM_44_19 0x00001ffffff80000
2199#define BM_19_44 BM_44_19
2200#define BM_45_19 0x00003ffffff80000
2201#define BM_19_45 BM_45_19
2202#define BM_46_19 0x00007ffffff80000
2203#define BM_19_46 BM_46_19
2204#define BM_47_19 0x0000fffffff80000
2205#define BM_19_47 BM_47_19
2206#define BM_48_19 0x0001fffffff80000
2207#define BM_19_48 BM_48_19
2208#define BM_49_19 0x0003fffffff80000
2209#define BM_19_49 BM_49_19
2210#define BM_50_19 0x0007fffffff80000
2211#define BM_19_50 BM_50_19
2212#define BM_51_19 0x000ffffffff80000
2213#define BM_19_51 BM_51_19
2214#define BM_52_19 0x001ffffffff80000
2215#define BM_19_52 BM_52_19
2216#define BM_53_19 0x003ffffffff80000
2217#define BM_19_53 BM_53_19
2218#define BM_54_19 0x007ffffffff80000
2219#define BM_19_54 BM_54_19
2220#define BM_55_19 0x00fffffffff80000
2221#define BM_19_55 BM_55_19
2222#define BM_56_19 0x01fffffffff80000
2223#define BM_19_56 BM_56_19
2224#define BM_57_19 0x03fffffffff80000
2225#define BM_19_57 BM_57_19
2226#define BM_58_19 0x07fffffffff80000
2227#define BM_19_58 BM_58_19
2228#define BM_59_19 0x0ffffffffff80000
2229#define BM_19_59 BM_59_19
2230#define BM_60_19 0x1ffffffffff80000
2231#define BM_19_60 BM_60_19
2232#define BM_61_19 0x3ffffffffff80000
2233#define BM_19_61 BM_61_19
2234#define BM_62_19 0x7ffffffffff80000
2235#define BM_19_62 BM_62_19
2236#define BM_63_19 0xfffffffffff80000
2237#define BM_19_63 BM_63_19
2238#define BM_20_20 0x0000000000100000
2239#define BM_21_20 0x0000000000300000
2240#define BM_20_21 BM_21_20
2241#define BM_22_20 0x0000000000700000
2242#define BM_20_22 BM_22_20
2243#define BM_23_20 0x0000000000f00000
2244#define BM_20_23 BM_23_20
2245#define BM_24_20 0x0000000001f00000
2246#define BM_20_24 BM_24_20
2247#define BM_25_20 0x0000000003f00000
2248#define BM_20_25 BM_25_20
2249#define BM_26_20 0x0000000007f00000
2250#define BM_20_26 BM_26_20
2251#define BM_27_20 0x000000000ff00000
2252#define BM_20_27 BM_27_20
2253#define BM_28_20 0x000000001ff00000
2254#define BM_20_28 BM_28_20
2255#define BM_29_20 0x000000003ff00000
2256#define BM_20_29 BM_29_20
2257#define BM_30_20 0x000000007ff00000
2258#define BM_20_30 BM_30_20
2259#define BM_31_20 0x00000000fff00000
2260#define BM_20_31 BM_31_20
2261#define BM_32_20 0x00000001fff00000
2262#define BM_20_32 BM_32_20
2263#define BM_33_20 0x00000003fff00000
2264#define BM_20_33 BM_33_20
2265#define BM_34_20 0x00000007fff00000
2266#define BM_20_34 BM_34_20
2267#define BM_35_20 0x0000000ffff00000
2268#define BM_20_35 BM_35_20
2269#define BM_36_20 0x0000001ffff00000
2270#define BM_20_36 BM_36_20
2271#define BM_37_20 0x0000003ffff00000
2272#define BM_20_37 BM_37_20
2273#define BM_38_20 0x0000007ffff00000
2274#define BM_20_38 BM_38_20
2275#define BM_39_20 0x000000fffff00000
2276#define BM_20_39 BM_39_20
2277#define BM_40_20 0x000001fffff00000
2278#define BM_20_40 BM_40_20
2279#define BM_41_20 0x000003fffff00000
2280#define BM_20_41 BM_41_20
2281#define BM_42_20 0x000007fffff00000
2282#define BM_20_42 BM_42_20
2283#define BM_43_20 0x00000ffffff00000
2284#define BM_20_43 BM_43_20
2285#define BM_44_20 0x00001ffffff00000
2286#define BM_20_44 BM_44_20
2287#define BM_45_20 0x00003ffffff00000
2288#define BM_20_45 BM_45_20
2289#define BM_46_20 0x00007ffffff00000
2290#define BM_20_46 BM_46_20
2291#define BM_47_20 0x0000fffffff00000
2292#define BM_20_47 BM_47_20
2293#define BM_48_20 0x0001fffffff00000
2294#define BM_20_48 BM_48_20
2295#define BM_49_20 0x0003fffffff00000
2296#define BM_20_49 BM_49_20
2297#define BM_50_20 0x0007fffffff00000
2298#define BM_20_50 BM_50_20
2299#define BM_51_20 0x000ffffffff00000
2300#define BM_20_51 BM_51_20
2301#define BM_52_20 0x001ffffffff00000
2302#define BM_20_52 BM_52_20
2303#define BM_53_20 0x003ffffffff00000
2304#define BM_20_53 BM_53_20
2305#define BM_54_20 0x007ffffffff00000
2306#define BM_20_54 BM_54_20
2307#define BM_55_20 0x00fffffffff00000
2308#define BM_20_55 BM_55_20
2309#define BM_56_20 0x01fffffffff00000
2310#define BM_20_56 BM_56_20
2311#define BM_57_20 0x03fffffffff00000
2312#define BM_20_57 BM_57_20
2313#define BM_58_20 0x07fffffffff00000
2314#define BM_20_58 BM_58_20
2315#define BM_59_20 0x0ffffffffff00000
2316#define BM_20_59 BM_59_20
2317#define BM_60_20 0x1ffffffffff00000
2318#define BM_20_60 BM_60_20
2319#define BM_61_20 0x3ffffffffff00000
2320#define BM_20_61 BM_61_20
2321#define BM_62_20 0x7ffffffffff00000
2322#define BM_20_62 BM_62_20
2323#define BM_63_20 0xfffffffffff00000
2324#define BM_20_63 BM_63_20
2325#define BM_21_21 0x0000000000200000
2326#define BM_22_21 0x0000000000600000
2327#define BM_21_22 BM_22_21
2328#define BM_23_21 0x0000000000e00000
2329#define BM_21_23 BM_23_21
2330#define BM_24_21 0x0000000001e00000
2331#define BM_21_24 BM_24_21
2332#define BM_25_21 0x0000000003e00000
2333#define BM_21_25 BM_25_21
2334#define BM_26_21 0x0000000007e00000
2335#define BM_21_26 BM_26_21
2336#define BM_27_21 0x000000000fe00000
2337#define BM_21_27 BM_27_21
2338#define BM_28_21 0x000000001fe00000
2339#define BM_21_28 BM_28_21
2340#define BM_29_21 0x000000003fe00000
2341#define BM_21_29 BM_29_21
2342#define BM_30_21 0x000000007fe00000
2343#define BM_21_30 BM_30_21
2344#define BM_31_21 0x00000000ffe00000
2345#define BM_21_31 BM_31_21
2346#define BM_32_21 0x00000001ffe00000
2347#define BM_21_32 BM_32_21
2348#define BM_33_21 0x00000003ffe00000
2349#define BM_21_33 BM_33_21
2350#define BM_34_21 0x00000007ffe00000
2351#define BM_21_34 BM_34_21
2352#define BM_35_21 0x0000000fffe00000
2353#define BM_21_35 BM_35_21
2354#define BM_36_21 0x0000001fffe00000
2355#define BM_21_36 BM_36_21
2356#define BM_37_21 0x0000003fffe00000
2357#define BM_21_37 BM_37_21
2358#define BM_38_21 0x0000007fffe00000
2359#define BM_21_38 BM_38_21
2360#define BM_39_21 0x000000ffffe00000
2361#define BM_21_39 BM_39_21
2362#define BM_40_21 0x000001ffffe00000
2363#define BM_21_40 BM_40_21
2364#define BM_41_21 0x000003ffffe00000
2365#define BM_21_41 BM_41_21
2366#define BM_42_21 0x000007ffffe00000
2367#define BM_21_42 BM_42_21
2368#define BM_43_21 0x00000fffffe00000
2369#define BM_21_43 BM_43_21
2370#define BM_44_21 0x00001fffffe00000
2371#define BM_21_44 BM_44_21
2372#define BM_45_21 0x00003fffffe00000
2373#define BM_21_45 BM_45_21
2374#define BM_46_21 0x00007fffffe00000
2375#define BM_21_46 BM_46_21
2376#define BM_47_21 0x0000ffffffe00000
2377#define BM_21_47 BM_47_21
2378#define BM_48_21 0x0001ffffffe00000
2379#define BM_21_48 BM_48_21
2380#define BM_49_21 0x0003ffffffe00000
2381#define BM_21_49 BM_49_21
2382#define BM_50_21 0x0007ffffffe00000
2383#define BM_21_50 BM_50_21
2384#define BM_51_21 0x000fffffffe00000
2385#define BM_21_51 BM_51_21
2386#define BM_52_21 0x001fffffffe00000
2387#define BM_21_52 BM_52_21
2388#define BM_53_21 0x003fffffffe00000
2389#define BM_21_53 BM_53_21
2390#define BM_54_21 0x007fffffffe00000
2391#define BM_21_54 BM_54_21
2392#define BM_55_21 0x00ffffffffe00000
2393#define BM_21_55 BM_55_21
2394#define BM_56_21 0x01ffffffffe00000
2395#define BM_21_56 BM_56_21
2396#define BM_57_21 0x03ffffffffe00000
2397#define BM_21_57 BM_57_21
2398#define BM_58_21 0x07ffffffffe00000
2399#define BM_21_58 BM_58_21
2400#define BM_59_21 0x0fffffffffe00000
2401#define BM_21_59 BM_59_21
2402#define BM_60_21 0x1fffffffffe00000
2403#define BM_21_60 BM_60_21
2404#define BM_61_21 0x3fffffffffe00000
2405#define BM_21_61 BM_61_21
2406#define BM_62_21 0x7fffffffffe00000
2407#define BM_21_62 BM_62_21
2408#define BM_63_21 0xffffffffffe00000
2409#define BM_21_63 BM_63_21
2410#define BM_22_22 0x0000000000400000
2411#define BM_23_22 0x0000000000c00000
2412#define BM_22_23 BM_23_22
2413#define BM_24_22 0x0000000001c00000
2414#define BM_22_24 BM_24_22
2415#define BM_25_22 0x0000000003c00000
2416#define BM_22_25 BM_25_22
2417#define BM_26_22 0x0000000007c00000
2418#define BM_22_26 BM_26_22
2419#define BM_27_22 0x000000000fc00000
2420#define BM_22_27 BM_27_22
2421#define BM_28_22 0x000000001fc00000
2422#define BM_22_28 BM_28_22
2423#define BM_29_22 0x000000003fc00000
2424#define BM_22_29 BM_29_22
2425#define BM_30_22 0x000000007fc00000
2426#define BM_22_30 BM_30_22
2427#define BM_31_22 0x00000000ffc00000
2428#define BM_22_31 BM_31_22
2429#define BM_32_22 0x00000001ffc00000
2430#define BM_22_32 BM_32_22
2431#define BM_33_22 0x00000003ffc00000
2432#define BM_22_33 BM_33_22
2433#define BM_34_22 0x00000007ffc00000
2434#define BM_22_34 BM_34_22
2435#define BM_35_22 0x0000000fffc00000
2436#define BM_22_35 BM_35_22
2437#define BM_36_22 0x0000001fffc00000
2438#define BM_22_36 BM_36_22
2439#define BM_37_22 0x0000003fffc00000
2440#define BM_22_37 BM_37_22
2441#define BM_38_22 0x0000007fffc00000
2442#define BM_22_38 BM_38_22
2443#define BM_39_22 0x000000ffffc00000
2444#define BM_22_39 BM_39_22
2445#define BM_40_22 0x000001ffffc00000
2446#define BM_22_40 BM_40_22
2447#define BM_41_22 0x000003ffffc00000
2448#define BM_22_41 BM_41_22
2449#define BM_42_22 0x000007ffffc00000
2450#define BM_22_42 BM_42_22
2451#define BM_43_22 0x00000fffffc00000
2452#define BM_22_43 BM_43_22
2453#define BM_44_22 0x00001fffffc00000
2454#define BM_22_44 BM_44_22
2455#define BM_45_22 0x00003fffffc00000
2456#define BM_22_45 BM_45_22
2457#define BM_46_22 0x00007fffffc00000
2458#define BM_22_46 BM_46_22
2459#define BM_47_22 0x0000ffffffc00000
2460#define BM_22_47 BM_47_22
2461#define BM_48_22 0x0001ffffffc00000
2462#define BM_22_48 BM_48_22
2463#define BM_49_22 0x0003ffffffc00000
2464#define BM_22_49 BM_49_22
2465#define BM_50_22 0x0007ffffffc00000
2466#define BM_22_50 BM_50_22
2467#define BM_51_22 0x000fffffffc00000
2468#define BM_22_51 BM_51_22
2469#define BM_52_22 0x001fffffffc00000
2470#define BM_22_52 BM_52_22
2471#define BM_53_22 0x003fffffffc00000
2472#define BM_22_53 BM_53_22
2473#define BM_54_22 0x007fffffffc00000
2474#define BM_22_54 BM_54_22
2475#define BM_55_22 0x00ffffffffc00000
2476#define BM_22_55 BM_55_22
2477#define BM_56_22 0x01ffffffffc00000
2478#define BM_22_56 BM_56_22
2479#define BM_57_22 0x03ffffffffc00000
2480#define BM_22_57 BM_57_22
2481#define BM_58_22 0x07ffffffffc00000
2482#define BM_22_58 BM_58_22
2483#define BM_59_22 0x0fffffffffc00000
2484#define BM_22_59 BM_59_22
2485#define BM_60_22 0x1fffffffffc00000
2486#define BM_22_60 BM_60_22
2487#define BM_61_22 0x3fffffffffc00000
2488#define BM_22_61 BM_61_22
2489#define BM_62_22 0x7fffffffffc00000
2490#define BM_22_62 BM_62_22
2491#define BM_63_22 0xffffffffffc00000
2492#define BM_22_63 BM_63_22
2493#define BM_23_23 0x0000000000800000
2494#define BM_24_23 0x0000000001800000
2495#define BM_23_24 BM_24_23
2496#define BM_25_23 0x0000000003800000
2497#define BM_23_25 BM_25_23
2498#define BM_26_23 0x0000000007800000
2499#define BM_23_26 BM_26_23
2500#define BM_27_23 0x000000000f800000
2501#define BM_23_27 BM_27_23
2502#define BM_28_23 0x000000001f800000
2503#define BM_23_28 BM_28_23
2504#define BM_29_23 0x000000003f800000
2505#define BM_23_29 BM_29_23
2506#define BM_30_23 0x000000007f800000
2507#define BM_23_30 BM_30_23
2508#define BM_31_23 0x00000000ff800000
2509#define BM_23_31 BM_31_23
2510#define BM_32_23 0x00000001ff800000
2511#define BM_23_32 BM_32_23
2512#define BM_33_23 0x00000003ff800000
2513#define BM_23_33 BM_33_23
2514#define BM_34_23 0x00000007ff800000
2515#define BM_23_34 BM_34_23
2516#define BM_35_23 0x0000000fff800000
2517#define BM_23_35 BM_35_23
2518#define BM_36_23 0x0000001fff800000
2519#define BM_23_36 BM_36_23
2520#define BM_37_23 0x0000003fff800000
2521#define BM_23_37 BM_37_23
2522#define BM_38_23 0x0000007fff800000
2523#define BM_23_38 BM_38_23
2524#define BM_39_23 0x000000ffff800000
2525#define BM_23_39 BM_39_23
2526#define BM_40_23 0x000001ffff800000
2527#define BM_23_40 BM_40_23
2528#define BM_41_23 0x000003ffff800000
2529#define BM_23_41 BM_41_23
2530#define BM_42_23 0x000007ffff800000
2531#define BM_23_42 BM_42_23
2532#define BM_43_23 0x00000fffff800000
2533#define BM_23_43 BM_43_23
2534#define BM_44_23 0x00001fffff800000
2535#define BM_23_44 BM_44_23
2536#define BM_45_23 0x00003fffff800000
2537#define BM_23_45 BM_45_23
2538#define BM_46_23 0x00007fffff800000
2539#define BM_23_46 BM_46_23
2540#define BM_47_23 0x0000ffffff800000
2541#define BM_23_47 BM_47_23
2542#define BM_48_23 0x0001ffffff800000
2543#define BM_23_48 BM_48_23
2544#define BM_49_23 0x0003ffffff800000
2545#define BM_23_49 BM_49_23
2546#define BM_50_23 0x0007ffffff800000
2547#define BM_23_50 BM_50_23
2548#define BM_51_23 0x000fffffff800000
2549#define BM_23_51 BM_51_23
2550#define BM_52_23 0x001fffffff800000
2551#define BM_23_52 BM_52_23
2552#define BM_53_23 0x003fffffff800000
2553#define BM_23_53 BM_53_23
2554#define BM_54_23 0x007fffffff800000
2555#define BM_23_54 BM_54_23
2556#define BM_55_23 0x00ffffffff800000
2557#define BM_23_55 BM_55_23
2558#define BM_56_23 0x01ffffffff800000
2559#define BM_23_56 BM_56_23
2560#define BM_57_23 0x03ffffffff800000
2561#define BM_23_57 BM_57_23
2562#define BM_58_23 0x07ffffffff800000
2563#define BM_23_58 BM_58_23
2564#define BM_59_23 0x0fffffffff800000
2565#define BM_23_59 BM_59_23
2566#define BM_60_23 0x1fffffffff800000
2567#define BM_23_60 BM_60_23
2568#define BM_61_23 0x3fffffffff800000
2569#define BM_23_61 BM_61_23
2570#define BM_62_23 0x7fffffffff800000
2571#define BM_23_62 BM_62_23
2572#define BM_63_23 0xffffffffff800000
2573#define BM_23_63 BM_63_23
2574#define BM_24_24 0x0000000001000000
2575#define BM_25_24 0x0000000003000000
2576#define BM_24_25 BM_25_24
2577#define BM_26_24 0x0000000007000000
2578#define BM_24_26 BM_26_24
2579#define BM_27_24 0x000000000f000000
2580#define BM_24_27 BM_27_24
2581#define BM_28_24 0x000000001f000000
2582#define BM_24_28 BM_28_24
2583#define BM_29_24 0x000000003f000000
2584#define BM_24_29 BM_29_24
2585#define BM_30_24 0x000000007f000000
2586#define BM_24_30 BM_30_24
2587#define BM_31_24 0x00000000ff000000
2588#define BM_24_31 BM_31_24
2589#define BM_32_24 0x00000001ff000000
2590#define BM_24_32 BM_32_24
2591#define BM_33_24 0x00000003ff000000
2592#define BM_24_33 BM_33_24
2593#define BM_34_24 0x00000007ff000000
2594#define BM_24_34 BM_34_24
2595#define BM_35_24 0x0000000fff000000
2596#define BM_24_35 BM_35_24
2597#define BM_36_24 0x0000001fff000000
2598#define BM_24_36 BM_36_24
2599#define BM_37_24 0x0000003fff000000
2600#define BM_24_37 BM_37_24
2601#define BM_38_24 0x0000007fff000000
2602#define BM_24_38 BM_38_24
2603#define BM_39_24 0x000000ffff000000
2604#define BM_24_39 BM_39_24
2605#define BM_40_24 0x000001ffff000000
2606#define BM_24_40 BM_40_24
2607#define BM_41_24 0x000003ffff000000
2608#define BM_24_41 BM_41_24
2609#define BM_42_24 0x000007ffff000000
2610#define BM_24_42 BM_42_24
2611#define BM_43_24 0x00000fffff000000
2612#define BM_24_43 BM_43_24
2613#define BM_44_24 0x00001fffff000000
2614#define BM_24_44 BM_44_24
2615#define BM_45_24 0x00003fffff000000
2616#define BM_24_45 BM_45_24
2617#define BM_46_24 0x00007fffff000000
2618#define BM_24_46 BM_46_24
2619#define BM_47_24 0x0000ffffff000000
2620#define BM_24_47 BM_47_24
2621#define BM_48_24 0x0001ffffff000000
2622#define BM_24_48 BM_48_24
2623#define BM_49_24 0x0003ffffff000000
2624#define BM_24_49 BM_49_24
2625#define BM_50_24 0x0007ffffff000000
2626#define BM_24_50 BM_50_24
2627#define BM_51_24 0x000fffffff000000
2628#define BM_24_51 BM_51_24
2629#define BM_52_24 0x001fffffff000000
2630#define BM_24_52 BM_52_24
2631#define BM_53_24 0x003fffffff000000
2632#define BM_24_53 BM_53_24
2633#define BM_54_24 0x007fffffff000000
2634#define BM_24_54 BM_54_24
2635#define BM_55_24 0x00ffffffff000000
2636#define BM_24_55 BM_55_24
2637#define BM_56_24 0x01ffffffff000000
2638#define BM_24_56 BM_56_24
2639#define BM_57_24 0x03ffffffff000000
2640#define BM_24_57 BM_57_24
2641#define BM_58_24 0x07ffffffff000000
2642#define BM_24_58 BM_58_24
2643#define BM_59_24 0x0fffffffff000000
2644#define BM_24_59 BM_59_24
2645#define BM_60_24 0x1fffffffff000000
2646#define BM_24_60 BM_60_24
2647#define BM_61_24 0x3fffffffff000000
2648#define BM_24_61 BM_61_24
2649#define BM_62_24 0x7fffffffff000000
2650#define BM_24_62 BM_62_24
2651#define BM_63_24 0xffffffffff000000
2652#define BM_24_63 BM_63_24
2653#define BM_25_25 0x0000000002000000
2654#define BM_26_25 0x0000000006000000
2655#define BM_25_26 BM_26_25
2656#define BM_27_25 0x000000000e000000
2657#define BM_25_27 BM_27_25
2658#define BM_28_25 0x000000001e000000
2659#define BM_25_28 BM_28_25
2660#define BM_29_25 0x000000003e000000
2661#define BM_25_29 BM_29_25
2662#define BM_30_25 0x000000007e000000
2663#define BM_25_30 BM_30_25
2664#define BM_31_25 0x00000000fe000000
2665#define BM_25_31 BM_31_25
2666#define BM_32_25 0x00000001fe000000
2667#define BM_25_32 BM_32_25
2668#define BM_33_25 0x00000003fe000000
2669#define BM_25_33 BM_33_25
2670#define BM_34_25 0x00000007fe000000
2671#define BM_25_34 BM_34_25
2672#define BM_35_25 0x0000000ffe000000
2673#define BM_25_35 BM_35_25
2674#define BM_36_25 0x0000001ffe000000
2675#define BM_25_36 BM_36_25
2676#define BM_37_25 0x0000003ffe000000
2677#define BM_25_37 BM_37_25
2678#define BM_38_25 0x0000007ffe000000
2679#define BM_25_38 BM_38_25
2680#define BM_39_25 0x000000fffe000000
2681#define BM_25_39 BM_39_25
2682#define BM_40_25 0x000001fffe000000
2683#define BM_25_40 BM_40_25
2684#define BM_41_25 0x000003fffe000000
2685#define BM_25_41 BM_41_25
2686#define BM_42_25 0x000007fffe000000
2687#define BM_25_42 BM_42_25
2688#define BM_43_25 0x00000ffffe000000
2689#define BM_25_43 BM_43_25
2690#define BM_44_25 0x00001ffffe000000
2691#define BM_25_44 BM_44_25
2692#define BM_45_25 0x00003ffffe000000
2693#define BM_25_45 BM_45_25
2694#define BM_46_25 0x00007ffffe000000
2695#define BM_25_46 BM_46_25
2696#define BM_47_25 0x0000fffffe000000
2697#define BM_25_47 BM_47_25
2698#define BM_48_25 0x0001fffffe000000
2699#define BM_25_48 BM_48_25
2700#define BM_49_25 0x0003fffffe000000
2701#define BM_25_49 BM_49_25
2702#define BM_50_25 0x0007fffffe000000
2703#define BM_25_50 BM_50_25
2704#define BM_51_25 0x000ffffffe000000
2705#define BM_25_51 BM_51_25
2706#define BM_52_25 0x001ffffffe000000
2707#define BM_25_52 BM_52_25
2708#define BM_53_25 0x003ffffffe000000
2709#define BM_25_53 BM_53_25
2710#define BM_54_25 0x007ffffffe000000
2711#define BM_25_54 BM_54_25
2712#define BM_55_25 0x00fffffffe000000
2713#define BM_25_55 BM_55_25
2714#define BM_56_25 0x01fffffffe000000
2715#define BM_25_56 BM_56_25
2716#define BM_57_25 0x03fffffffe000000
2717#define BM_25_57 BM_57_25
2718#define BM_58_25 0x07fffffffe000000
2719#define BM_25_58 BM_58_25
2720#define BM_59_25 0x0ffffffffe000000
2721#define BM_25_59 BM_59_25
2722#define BM_60_25 0x1ffffffffe000000
2723#define BM_25_60 BM_60_25
2724#define BM_61_25 0x3ffffffffe000000
2725#define BM_25_61 BM_61_25
2726#define BM_62_25 0x7ffffffffe000000
2727#define BM_25_62 BM_62_25
2728#define BM_63_25 0xfffffffffe000000
2729#define BM_25_63 BM_63_25
2730#define BM_26_26 0x0000000004000000
2731#define BM_27_26 0x000000000c000000
2732#define BM_26_27 BM_27_26
2733#define BM_28_26 0x000000001c000000
2734#define BM_26_28 BM_28_26
2735#define BM_29_26 0x000000003c000000
2736#define BM_26_29 BM_29_26
2737#define BM_30_26 0x000000007c000000
2738#define BM_26_30 BM_30_26
2739#define BM_31_26 0x00000000fc000000
2740#define BM_26_31 BM_31_26
2741#define BM_32_26 0x00000001fc000000
2742#define BM_26_32 BM_32_26
2743#define BM_33_26 0x00000003fc000000
2744#define BM_26_33 BM_33_26
2745#define BM_34_26 0x00000007fc000000
2746#define BM_26_34 BM_34_26
2747#define BM_35_26 0x0000000ffc000000
2748#define BM_26_35 BM_35_26
2749#define BM_36_26 0x0000001ffc000000
2750#define BM_26_36 BM_36_26
2751#define BM_37_26 0x0000003ffc000000
2752#define BM_26_37 BM_37_26
2753#define BM_38_26 0x0000007ffc000000
2754#define BM_26_38 BM_38_26
2755#define BM_39_26 0x000000fffc000000
2756#define BM_26_39 BM_39_26
2757#define BM_40_26 0x000001fffc000000
2758#define BM_26_40 BM_40_26
2759#define BM_41_26 0x000003fffc000000
2760#define BM_26_41 BM_41_26
2761#define BM_42_26 0x000007fffc000000
2762#define BM_26_42 BM_42_26
2763#define BM_43_26 0x00000ffffc000000
2764#define BM_26_43 BM_43_26
2765#define BM_44_26 0x00001ffffc000000
2766#define BM_26_44 BM_44_26
2767#define BM_45_26 0x00003ffffc000000
2768#define BM_26_45 BM_45_26
2769#define BM_46_26 0x00007ffffc000000
2770#define BM_26_46 BM_46_26
2771#define BM_47_26 0x0000fffffc000000
2772#define BM_26_47 BM_47_26
2773#define BM_48_26 0x0001fffffc000000
2774#define BM_26_48 BM_48_26
2775#define BM_49_26 0x0003fffffc000000
2776#define BM_26_49 BM_49_26
2777#define BM_50_26 0x0007fffffc000000
2778#define BM_26_50 BM_50_26
2779#define BM_51_26 0x000ffffffc000000
2780#define BM_26_51 BM_51_26
2781#define BM_52_26 0x001ffffffc000000
2782#define BM_26_52 BM_52_26
2783#define BM_53_26 0x003ffffffc000000
2784#define BM_26_53 BM_53_26
2785#define BM_54_26 0x007ffffffc000000
2786#define BM_26_54 BM_54_26
2787#define BM_55_26 0x00fffffffc000000
2788#define BM_26_55 BM_55_26
2789#define BM_56_26 0x01fffffffc000000
2790#define BM_26_56 BM_56_26
2791#define BM_57_26 0x03fffffffc000000
2792#define BM_26_57 BM_57_26
2793#define BM_58_26 0x07fffffffc000000
2794#define BM_26_58 BM_58_26
2795#define BM_59_26 0x0ffffffffc000000
2796#define BM_26_59 BM_59_26
2797#define BM_60_26 0x1ffffffffc000000
2798#define BM_26_60 BM_60_26
2799#define BM_61_26 0x3ffffffffc000000
2800#define BM_26_61 BM_61_26
2801#define BM_62_26 0x7ffffffffc000000
2802#define BM_26_62 BM_62_26
2803#define BM_63_26 0xfffffffffc000000
2804#define BM_26_63 BM_63_26
2805#define BM_27_27 0x0000000008000000
2806#define BM_28_27 0x0000000018000000
2807#define BM_27_28 BM_28_27
2808#define BM_29_27 0x0000000038000000
2809#define BM_27_29 BM_29_27
2810#define BM_30_27 0x0000000078000000
2811#define BM_27_30 BM_30_27
2812#define BM_31_27 0x00000000f8000000
2813#define BM_27_31 BM_31_27
2814#define BM_32_27 0x00000001f8000000
2815#define BM_27_32 BM_32_27
2816#define BM_33_27 0x00000003f8000000
2817#define BM_27_33 BM_33_27
2818#define BM_34_27 0x00000007f8000000
2819#define BM_27_34 BM_34_27
2820#define BM_35_27 0x0000000ff8000000
2821#define BM_27_35 BM_35_27
2822#define BM_36_27 0x0000001ff8000000
2823#define BM_27_36 BM_36_27
2824#define BM_37_27 0x0000003ff8000000
2825#define BM_27_37 BM_37_27
2826#define BM_38_27 0x0000007ff8000000
2827#define BM_27_38 BM_38_27
2828#define BM_39_27 0x000000fff8000000
2829#define BM_27_39 BM_39_27
2830#define BM_40_27 0x000001fff8000000
2831#define BM_27_40 BM_40_27
2832#define BM_41_27 0x000003fff8000000
2833#define BM_27_41 BM_41_27
2834#define BM_42_27 0x000007fff8000000
2835#define BM_27_42 BM_42_27
2836#define BM_43_27 0x00000ffff8000000
2837#define BM_27_43 BM_43_27
2838#define BM_44_27 0x00001ffff8000000
2839#define BM_27_44 BM_44_27
2840#define BM_45_27 0x00003ffff8000000
2841#define BM_27_45 BM_45_27
2842#define BM_46_27 0x00007ffff8000000
2843#define BM_27_46 BM_46_27
2844#define BM_47_27 0x0000fffff8000000
2845#define BM_27_47 BM_47_27
2846#define BM_48_27 0x0001fffff8000000
2847#define BM_27_48 BM_48_27
2848#define BM_49_27 0x0003fffff8000000
2849#define BM_27_49 BM_49_27
2850#define BM_50_27 0x0007fffff8000000
2851#define BM_27_50 BM_50_27
2852#define BM_51_27 0x000ffffff8000000
2853#define BM_27_51 BM_51_27
2854#define BM_52_27 0x001ffffff8000000
2855#define BM_27_52 BM_52_27
2856#define BM_53_27 0x003ffffff8000000
2857#define BM_27_53 BM_53_27
2858#define BM_54_27 0x007ffffff8000000
2859#define BM_27_54 BM_54_27
2860#define BM_55_27 0x00fffffff8000000
2861#define BM_27_55 BM_55_27
2862#define BM_56_27 0x01fffffff8000000
2863#define BM_27_56 BM_56_27
2864#define BM_57_27 0x03fffffff8000000
2865#define BM_27_57 BM_57_27
2866#define BM_58_27 0x07fffffff8000000
2867#define BM_27_58 BM_58_27
2868#define BM_59_27 0x0ffffffff8000000
2869#define BM_27_59 BM_59_27
2870#define BM_60_27 0x1ffffffff8000000
2871#define BM_27_60 BM_60_27
2872#define BM_61_27 0x3ffffffff8000000
2873#define BM_27_61 BM_61_27
2874#define BM_62_27 0x7ffffffff8000000
2875#define BM_27_62 BM_62_27
2876#define BM_63_27 0xfffffffff8000000
2877#define BM_27_63 BM_63_27
2878#define BM_28_28 0x0000000010000000
2879#define BM_29_28 0x0000000030000000
2880#define BM_28_29 BM_29_28
2881#define BM_30_28 0x0000000070000000
2882#define BM_28_30 BM_30_28
2883#define BM_31_28 0x00000000f0000000
2884#define BM_28_31 BM_31_28
2885#define BM_32_28 0x00000001f0000000
2886#define BM_28_32 BM_32_28
2887#define BM_33_28 0x00000003f0000000
2888#define BM_28_33 BM_33_28
2889#define BM_34_28 0x00000007f0000000
2890#define BM_28_34 BM_34_28
2891#define BM_35_28 0x0000000ff0000000
2892#define BM_28_35 BM_35_28
2893#define BM_36_28 0x0000001ff0000000
2894#define BM_28_36 BM_36_28
2895#define BM_37_28 0x0000003ff0000000
2896#define BM_28_37 BM_37_28
2897#define BM_38_28 0x0000007ff0000000
2898#define BM_28_38 BM_38_28
2899#define BM_39_28 0x000000fff0000000
2900#define BM_28_39 BM_39_28
2901#define BM_40_28 0x000001fff0000000
2902#define BM_28_40 BM_40_28
2903#define BM_41_28 0x000003fff0000000
2904#define BM_28_41 BM_41_28
2905#define BM_42_28 0x000007fff0000000
2906#define BM_28_42 BM_42_28
2907#define BM_43_28 0x00000ffff0000000
2908#define BM_28_43 BM_43_28
2909#define BM_44_28 0x00001ffff0000000
2910#define BM_28_44 BM_44_28
2911#define BM_45_28 0x00003ffff0000000
2912#define BM_28_45 BM_45_28
2913#define BM_46_28 0x00007ffff0000000
2914#define BM_28_46 BM_46_28
2915#define BM_47_28 0x0000fffff0000000
2916#define BM_28_47 BM_47_28
2917#define BM_48_28 0x0001fffff0000000
2918#define BM_28_48 BM_48_28
2919#define BM_49_28 0x0003fffff0000000
2920#define BM_28_49 BM_49_28
2921#define BM_50_28 0x0007fffff0000000
2922#define BM_28_50 BM_50_28
2923#define BM_51_28 0x000ffffff0000000
2924#define BM_28_51 BM_51_28
2925#define BM_52_28 0x001ffffff0000000
2926#define BM_28_52 BM_52_28
2927#define BM_53_28 0x003ffffff0000000
2928#define BM_28_53 BM_53_28
2929#define BM_54_28 0x007ffffff0000000
2930#define BM_28_54 BM_54_28
2931#define BM_55_28 0x00fffffff0000000
2932#define BM_28_55 BM_55_28
2933#define BM_56_28 0x01fffffff0000000
2934#define BM_28_56 BM_56_28
2935#define BM_57_28 0x03fffffff0000000
2936#define BM_28_57 BM_57_28
2937#define BM_58_28 0x07fffffff0000000
2938#define BM_28_58 BM_58_28
2939#define BM_59_28 0x0ffffffff0000000
2940#define BM_28_59 BM_59_28
2941#define BM_60_28 0x1ffffffff0000000
2942#define BM_28_60 BM_60_28
2943#define BM_61_28 0x3ffffffff0000000
2944#define BM_28_61 BM_61_28
2945#define BM_62_28 0x7ffffffff0000000
2946#define BM_28_62 BM_62_28
2947#define BM_63_28 0xfffffffff0000000
2948#define BM_28_63 BM_63_28
2949#define BM_29_29 0x0000000020000000
2950#define BM_30_29 0x0000000060000000
2951#define BM_29_30 BM_30_29
2952#define BM_31_29 0x00000000e0000000
2953#define BM_29_31 BM_31_29
2954#define BM_32_29 0x00000001e0000000
2955#define BM_29_32 BM_32_29
2956#define BM_33_29 0x00000003e0000000
2957#define BM_29_33 BM_33_29
2958#define BM_34_29 0x00000007e0000000
2959#define BM_29_34 BM_34_29
2960#define BM_35_29 0x0000000fe0000000
2961#define BM_29_35 BM_35_29
2962#define BM_36_29 0x0000001fe0000000
2963#define BM_29_36 BM_36_29
2964#define BM_37_29 0x0000003fe0000000
2965#define BM_29_37 BM_37_29
2966#define BM_38_29 0x0000007fe0000000
2967#define BM_29_38 BM_38_29
2968#define BM_39_29 0x000000ffe0000000
2969#define BM_29_39 BM_39_29
2970#define BM_40_29 0x000001ffe0000000
2971#define BM_29_40 BM_40_29
2972#define BM_41_29 0x000003ffe0000000
2973#define BM_29_41 BM_41_29
2974#define BM_42_29 0x000007ffe0000000
2975#define BM_29_42 BM_42_29
2976#define BM_43_29 0x00000fffe0000000
2977#define BM_29_43 BM_43_29
2978#define BM_44_29 0x00001fffe0000000
2979#define BM_29_44 BM_44_29
2980#define BM_45_29 0x00003fffe0000000
2981#define BM_29_45 BM_45_29
2982#define BM_46_29 0x00007fffe0000000
2983#define BM_29_46 BM_46_29
2984#define BM_47_29 0x0000ffffe0000000
2985#define BM_29_47 BM_47_29
2986#define BM_48_29 0x0001ffffe0000000
2987#define BM_29_48 BM_48_29
2988#define BM_49_29 0x0003ffffe0000000
2989#define BM_29_49 BM_49_29
2990#define BM_50_29 0x0007ffffe0000000
2991#define BM_29_50 BM_50_29
2992#define BM_51_29 0x000fffffe0000000
2993#define BM_29_51 BM_51_29
2994#define BM_52_29 0x001fffffe0000000
2995#define BM_29_52 BM_52_29
2996#define BM_53_29 0x003fffffe0000000
2997#define BM_29_53 BM_53_29
2998#define BM_54_29 0x007fffffe0000000
2999#define BM_29_54 BM_54_29
3000#define BM_55_29 0x00ffffffe0000000
3001#define BM_29_55 BM_55_29
3002#define BM_56_29 0x01ffffffe0000000
3003#define BM_29_56 BM_56_29
3004#define BM_57_29 0x03ffffffe0000000
3005#define BM_29_57 BM_57_29
3006#define BM_58_29 0x07ffffffe0000000
3007#define BM_29_58 BM_58_29
3008#define BM_59_29 0x0fffffffe0000000
3009#define BM_29_59 BM_59_29
3010#define BM_60_29 0x1fffffffe0000000
3011#define BM_29_60 BM_60_29
3012#define BM_61_29 0x3fffffffe0000000
3013#define BM_29_61 BM_61_29
3014#define BM_62_29 0x7fffffffe0000000
3015#define BM_29_62 BM_62_29
3016#define BM_63_29 0xffffffffe0000000
3017#define BM_29_63 BM_63_29
3018#define BM_30_30 0x0000000040000000
3019#define BM_31_30 0x00000000c0000000
3020#define BM_30_31 BM_31_30
3021#define BM_32_30 0x00000001c0000000
3022#define BM_30_32 BM_32_30
3023#define BM_33_30 0x00000003c0000000
3024#define BM_30_33 BM_33_30
3025#define BM_34_30 0x00000007c0000000
3026#define BM_30_34 BM_34_30
3027#define BM_35_30 0x0000000fc0000000
3028#define BM_30_35 BM_35_30
3029#define BM_36_30 0x0000001fc0000000
3030#define BM_30_36 BM_36_30
3031#define BM_37_30 0x0000003fc0000000
3032#define BM_30_37 BM_37_30
3033#define BM_38_30 0x0000007fc0000000
3034#define BM_30_38 BM_38_30
3035#define BM_39_30 0x000000ffc0000000
3036#define BM_30_39 BM_39_30
3037#define BM_40_30 0x000001ffc0000000
3038#define BM_30_40 BM_40_30
3039#define BM_41_30 0x000003ffc0000000
3040#define BM_30_41 BM_41_30
3041#define BM_42_30 0x000007ffc0000000
3042#define BM_30_42 BM_42_30
3043#define BM_43_30 0x00000fffc0000000
3044#define BM_30_43 BM_43_30
3045#define BM_44_30 0x00001fffc0000000
3046#define BM_30_44 BM_44_30
3047#define BM_45_30 0x00003fffc0000000
3048#define BM_30_45 BM_45_30
3049#define BM_46_30 0x00007fffc0000000
3050#define BM_30_46 BM_46_30
3051#define BM_47_30 0x0000ffffc0000000
3052#define BM_30_47 BM_47_30
3053#define BM_48_30 0x0001ffffc0000000
3054#define BM_30_48 BM_48_30
3055#define BM_49_30 0x0003ffffc0000000
3056#define BM_30_49 BM_49_30
3057#define BM_50_30 0x0007ffffc0000000
3058#define BM_30_50 BM_50_30
3059#define BM_51_30 0x000fffffc0000000
3060#define BM_30_51 BM_51_30
3061#define BM_52_30 0x001fffffc0000000
3062#define BM_30_52 BM_52_30
3063#define BM_53_30 0x003fffffc0000000
3064#define BM_30_53 BM_53_30
3065#define BM_54_30 0x007fffffc0000000
3066#define BM_30_54 BM_54_30
3067#define BM_55_30 0x00ffffffc0000000
3068#define BM_30_55 BM_55_30
3069#define BM_56_30 0x01ffffffc0000000
3070#define BM_30_56 BM_56_30
3071#define BM_57_30 0x03ffffffc0000000
3072#define BM_30_57 BM_57_30
3073#define BM_58_30 0x07ffffffc0000000
3074#define BM_30_58 BM_58_30
3075#define BM_59_30 0x0fffffffc0000000
3076#define BM_30_59 BM_59_30
3077#define BM_60_30 0x1fffffffc0000000
3078#define BM_30_60 BM_60_30
3079#define BM_61_30 0x3fffffffc0000000
3080#define BM_30_61 BM_61_30
3081#define BM_62_30 0x7fffffffc0000000
3082#define BM_30_62 BM_62_30
3083#define BM_63_30 0xffffffffc0000000
3084#define BM_30_63 BM_63_30
3085#define BM_31_31 0x0000000080000000
3086#define BM_32_31 0x0000000180000000
3087#define BM_31_32 BM_32_31
3088#define BM_33_31 0x0000000380000000
3089#define BM_31_33 BM_33_31
3090#define BM_34_31 0x0000000780000000
3091#define BM_31_34 BM_34_31
3092#define BM_35_31 0x0000000f80000000
3093#define BM_31_35 BM_35_31
3094#define BM_36_31 0x0000001f80000000
3095#define BM_31_36 BM_36_31
3096#define BM_37_31 0x0000003f80000000
3097#define BM_31_37 BM_37_31
3098#define BM_38_31 0x0000007f80000000
3099#define BM_31_38 BM_38_31
3100#define BM_39_31 0x000000ff80000000
3101#define BM_31_39 BM_39_31
3102#define BM_40_31 0x000001ff80000000
3103#define BM_31_40 BM_40_31
3104#define BM_41_31 0x000003ff80000000
3105#define BM_31_41 BM_41_31
3106#define BM_42_31 0x000007ff80000000
3107#define BM_31_42 BM_42_31
3108#define BM_43_31 0x00000fff80000000
3109#define BM_31_43 BM_43_31
3110#define BM_44_31 0x00001fff80000000
3111#define BM_31_44 BM_44_31
3112#define BM_45_31 0x00003fff80000000
3113#define BM_31_45 BM_45_31
3114#define BM_46_31 0x00007fff80000000
3115#define BM_31_46 BM_46_31
3116#define BM_47_31 0x0000ffff80000000
3117#define BM_31_47 BM_47_31
3118#define BM_48_31 0x0001ffff80000000
3119#define BM_31_48 BM_48_31
3120#define BM_49_31 0x0003ffff80000000
3121#define BM_31_49 BM_49_31
3122#define BM_50_31 0x0007ffff80000000
3123#define BM_31_50 BM_50_31
3124#define BM_51_31 0x000fffff80000000
3125#define BM_31_51 BM_51_31
3126#define BM_52_31 0x001fffff80000000
3127#define BM_31_52 BM_52_31
3128#define BM_53_31 0x003fffff80000000
3129#define BM_31_53 BM_53_31
3130#define BM_54_31 0x007fffff80000000
3131#define BM_31_54 BM_54_31
3132#define BM_55_31 0x00ffffff80000000
3133#define BM_31_55 BM_55_31
3134#define BM_56_31 0x01ffffff80000000
3135#define BM_31_56 BM_56_31
3136#define BM_57_31 0x03ffffff80000000
3137#define BM_31_57 BM_57_31
3138#define BM_58_31 0x07ffffff80000000
3139#define BM_31_58 BM_58_31
3140#define BM_59_31 0x0fffffff80000000
3141#define BM_31_59 BM_59_31
3142#define BM_60_31 0x1fffffff80000000
3143#define BM_31_60 BM_60_31
3144#define BM_61_31 0x3fffffff80000000
3145#define BM_31_61 BM_61_31
3146#define BM_62_31 0x7fffffff80000000
3147#define BM_31_62 BM_62_31
3148#define BM_63_31 0xffffffff80000000
3149#define BM_31_63 BM_63_31
3150#define BM_32_32 0x0000000100000000
3151#define BM_33_32 0x0000000300000000
3152#define BM_32_33 BM_33_32
3153#define BM_34_32 0x0000000700000000
3154#define BM_32_34 BM_34_32
3155#define BM_35_32 0x0000000f00000000
3156#define BM_32_35 BM_35_32
3157#define BM_36_32 0x0000001f00000000
3158#define BM_32_36 BM_36_32
3159#define BM_37_32 0x0000003f00000000
3160#define BM_32_37 BM_37_32
3161#define BM_38_32 0x0000007f00000000
3162#define BM_32_38 BM_38_32
3163#define BM_39_32 0x000000ff00000000
3164#define BM_32_39 BM_39_32
3165#define BM_40_32 0x000001ff00000000
3166#define BM_32_40 BM_40_32
3167#define BM_41_32 0x000003ff00000000
3168#define BM_32_41 BM_41_32
3169#define BM_42_32 0x000007ff00000000
3170#define BM_32_42 BM_42_32
3171#define BM_43_32 0x00000fff00000000
3172#define BM_32_43 BM_43_32
3173#define BM_44_32 0x00001fff00000000
3174#define BM_32_44 BM_44_32
3175#define BM_45_32 0x00003fff00000000
3176#define BM_32_45 BM_45_32
3177#define BM_46_32 0x00007fff00000000
3178#define BM_32_46 BM_46_32
3179#define BM_47_32 0x0000ffff00000000
3180#define BM_32_47 BM_47_32
3181#define BM_48_32 0x0001ffff00000000
3182#define BM_32_48 BM_48_32
3183#define BM_49_32 0x0003ffff00000000
3184#define BM_32_49 BM_49_32
3185#define BM_50_32 0x0007ffff00000000
3186#define BM_32_50 BM_50_32
3187#define BM_51_32 0x000fffff00000000
3188#define BM_32_51 BM_51_32
3189#define BM_52_32 0x001fffff00000000
3190#define BM_32_52 BM_52_32
3191#define BM_53_32 0x003fffff00000000
3192#define BM_32_53 BM_53_32
3193#define BM_54_32 0x007fffff00000000
3194#define BM_32_54 BM_54_32
3195#define BM_55_32 0x00ffffff00000000
3196#define BM_32_55 BM_55_32
3197#define BM_56_32 0x01ffffff00000000
3198#define BM_32_56 BM_56_32
3199#define BM_57_32 0x03ffffff00000000
3200#define BM_32_57 BM_57_32
3201#define BM_58_32 0x07ffffff00000000
3202#define BM_32_58 BM_58_32
3203#define BM_59_32 0x0fffffff00000000
3204#define BM_32_59 BM_59_32
3205#define BM_60_32 0x1fffffff00000000
3206#define BM_32_60 BM_60_32
3207#define BM_61_32 0x3fffffff00000000
3208#define BM_32_61 BM_61_32
3209#define BM_62_32 0x7fffffff00000000
3210#define BM_32_62 BM_62_32
3211#define BM_63_32 0xffffffff00000000
3212#define BM_32_63 BM_63_32
3213#define BM_33_33 0x0000000200000000
3214#define BM_34_33 0x0000000600000000
3215#define BM_33_34 BM_34_33
3216#define BM_35_33 0x0000000e00000000
3217#define BM_33_35 BM_35_33
3218#define BM_36_33 0x0000001e00000000
3219#define BM_33_36 BM_36_33
3220#define BM_37_33 0x0000003e00000000
3221#define BM_33_37 BM_37_33
3222#define BM_38_33 0x0000007e00000000
3223#define BM_33_38 BM_38_33
3224#define BM_39_33 0x000000fe00000000
3225#define BM_33_39 BM_39_33
3226#define BM_40_33 0x000001fe00000000
3227#define BM_33_40 BM_40_33
3228#define BM_41_33 0x000003fe00000000
3229#define BM_33_41 BM_41_33
3230#define BM_42_33 0x000007fe00000000
3231#define BM_33_42 BM_42_33
3232#define BM_43_33 0x00000ffe00000000
3233#define BM_33_43 BM_43_33
3234#define BM_44_33 0x00001ffe00000000
3235#define BM_33_44 BM_44_33
3236#define BM_45_33 0x00003ffe00000000
3237#define BM_33_45 BM_45_33
3238#define BM_46_33 0x00007ffe00000000
3239#define BM_33_46 BM_46_33
3240#define BM_47_33 0x0000fffe00000000
3241#define BM_33_47 BM_47_33
3242#define BM_48_33 0x0001fffe00000000
3243#define BM_33_48 BM_48_33
3244#define BM_49_33 0x0003fffe00000000
3245#define BM_33_49 BM_49_33
3246#define BM_50_33 0x0007fffe00000000
3247#define BM_33_50 BM_50_33
3248#define BM_51_33 0x000ffffe00000000
3249#define BM_33_51 BM_51_33
3250#define BM_52_33 0x001ffffe00000000
3251#define BM_33_52 BM_52_33
3252#define BM_53_33 0x003ffffe00000000
3253#define BM_33_53 BM_53_33
3254#define BM_54_33 0x007ffffe00000000
3255#define BM_33_54 BM_54_33
3256#define BM_55_33 0x00fffffe00000000
3257#define BM_33_55 BM_55_33
3258#define BM_56_33 0x01fffffe00000000
3259#define BM_33_56 BM_56_33
3260#define BM_57_33 0x03fffffe00000000
3261#define BM_33_57 BM_57_33
3262#define BM_58_33 0x07fffffe00000000
3263#define BM_33_58 BM_58_33
3264#define BM_59_33 0x0ffffffe00000000
3265#define BM_33_59 BM_59_33
3266#define BM_60_33 0x1ffffffe00000000
3267#define BM_33_60 BM_60_33
3268#define BM_61_33 0x3ffffffe00000000
3269#define BM_33_61 BM_61_33
3270#define BM_62_33 0x7ffffffe00000000
3271#define BM_33_62 BM_62_33
3272#define BM_63_33 0xfffffffe00000000
3273#define BM_33_63 BM_63_33
3274#define BM_34_34 0x0000000400000000
3275#define BM_35_34 0x0000000c00000000
3276#define BM_34_35 BM_35_34
3277#define BM_36_34 0x0000001c00000000
3278#define BM_34_36 BM_36_34
3279#define BM_37_34 0x0000003c00000000
3280#define BM_34_37 BM_37_34
3281#define BM_38_34 0x0000007c00000000
3282#define BM_34_38 BM_38_34
3283#define BM_39_34 0x000000fc00000000
3284#define BM_34_39 BM_39_34
3285#define BM_40_34 0x000001fc00000000
3286#define BM_34_40 BM_40_34
3287#define BM_41_34 0x000003fc00000000
3288#define BM_34_41 BM_41_34
3289#define BM_42_34 0x000007fc00000000
3290#define BM_34_42 BM_42_34
3291#define BM_43_34 0x00000ffc00000000
3292#define BM_34_43 BM_43_34
3293#define BM_44_34 0x00001ffc00000000
3294#define BM_34_44 BM_44_34
3295#define BM_45_34 0x00003ffc00000000
3296#define BM_34_45 BM_45_34
3297#define BM_46_34 0x00007ffc00000000
3298#define BM_34_46 BM_46_34
3299#define BM_47_34 0x0000fffc00000000
3300#define BM_34_47 BM_47_34
3301#define BM_48_34 0x0001fffc00000000
3302#define BM_34_48 BM_48_34
3303#define BM_49_34 0x0003fffc00000000
3304#define BM_34_49 BM_49_34
3305#define BM_50_34 0x0007fffc00000000
3306#define BM_34_50 BM_50_34
3307#define BM_51_34 0x000ffffc00000000
3308#define BM_34_51 BM_51_34
3309#define BM_52_34 0x001ffffc00000000
3310#define BM_34_52 BM_52_34
3311#define BM_53_34 0x003ffffc00000000
3312#define BM_34_53 BM_53_34
3313#define BM_54_34 0x007ffffc00000000
3314#define BM_34_54 BM_54_34
3315#define BM_55_34 0x00fffffc00000000
3316#define BM_34_55 BM_55_34
3317#define BM_56_34 0x01fffffc00000000
3318#define BM_34_56 BM_56_34
3319#define BM_57_34 0x03fffffc00000000
3320#define BM_34_57 BM_57_34
3321#define BM_58_34 0x07fffffc00000000
3322#define BM_34_58 BM_58_34
3323#define BM_59_34 0x0ffffffc00000000
3324#define BM_34_59 BM_59_34
3325#define BM_60_34 0x1ffffffc00000000
3326#define BM_34_60 BM_60_34
3327#define BM_61_34 0x3ffffffc00000000
3328#define BM_34_61 BM_61_34
3329#define BM_62_34 0x7ffffffc00000000
3330#define BM_34_62 BM_62_34
3331#define BM_63_34 0xfffffffc00000000
3332#define BM_34_63 BM_63_34
3333#define BM_35_35 0x0000000800000000
3334#define BM_36_35 0x0000001800000000
3335#define BM_35_36 BM_36_35
3336#define BM_37_35 0x0000003800000000
3337#define BM_35_37 BM_37_35
3338#define BM_38_35 0x0000007800000000
3339#define BM_35_38 BM_38_35
3340#define BM_39_35 0x000000f800000000
3341#define BM_35_39 BM_39_35
3342#define BM_40_35 0x000001f800000000
3343#define BM_35_40 BM_40_35
3344#define BM_41_35 0x000003f800000000
3345#define BM_35_41 BM_41_35
3346#define BM_42_35 0x000007f800000000
3347#define BM_35_42 BM_42_35
3348#define BM_43_35 0x00000ff800000000
3349#define BM_35_43 BM_43_35
3350#define BM_44_35 0x00001ff800000000
3351#define BM_35_44 BM_44_35
3352#define BM_45_35 0x00003ff800000000
3353#define BM_35_45 BM_45_35
3354#define BM_46_35 0x00007ff800000000
3355#define BM_35_46 BM_46_35
3356#define BM_47_35 0x0000fff800000000
3357#define BM_35_47 BM_47_35
3358#define BM_48_35 0x0001fff800000000
3359#define BM_35_48 BM_48_35
3360#define BM_49_35 0x0003fff800000000
3361#define BM_35_49 BM_49_35
3362#define BM_50_35 0x0007fff800000000
3363#define BM_35_50 BM_50_35
3364#define BM_51_35 0x000ffff800000000
3365#define BM_35_51 BM_51_35
3366#define BM_52_35 0x001ffff800000000
3367#define BM_35_52 BM_52_35
3368#define BM_53_35 0x003ffff800000000
3369#define BM_35_53 BM_53_35
3370#define BM_54_35 0x007ffff800000000
3371#define BM_35_54 BM_54_35
3372#define BM_55_35 0x00fffff800000000
3373#define BM_35_55 BM_55_35
3374#define BM_56_35 0x01fffff800000000
3375#define BM_35_56 BM_56_35
3376#define BM_57_35 0x03fffff800000000
3377#define BM_35_57 BM_57_35
3378#define BM_58_35 0x07fffff800000000
3379#define BM_35_58 BM_58_35
3380#define BM_59_35 0x0ffffff800000000
3381#define BM_35_59 BM_59_35
3382#define BM_60_35 0x1ffffff800000000
3383#define BM_35_60 BM_60_35
3384#define BM_61_35 0x3ffffff800000000
3385#define BM_35_61 BM_61_35
3386#define BM_62_35 0x7ffffff800000000
3387#define BM_35_62 BM_62_35
3388#define BM_63_35 0xfffffff800000000
3389#define BM_35_63 BM_63_35
3390#define BM_36_36 0x0000001000000000
3391#define BM_37_36 0x0000003000000000
3392#define BM_36_37 BM_37_36
3393#define BM_38_36 0x0000007000000000
3394#define BM_36_38 BM_38_36
3395#define BM_39_36 0x000000f000000000
3396#define BM_36_39 BM_39_36
3397#define BM_40_36 0x000001f000000000
3398#define BM_36_40 BM_40_36
3399#define BM_41_36 0x000003f000000000
3400#define BM_36_41 BM_41_36
3401#define BM_42_36 0x000007f000000000
3402#define BM_36_42 BM_42_36
3403#define BM_43_36 0x00000ff000000000
3404#define BM_36_43 BM_43_36
3405#define BM_44_36 0x00001ff000000000
3406#define BM_36_44 BM_44_36
3407#define BM_45_36 0x00003ff000000000
3408#define BM_36_45 BM_45_36
3409#define BM_46_36 0x00007ff000000000
3410#define BM_36_46 BM_46_36
3411#define BM_47_36 0x0000fff000000000
3412#define BM_36_47 BM_47_36
3413#define BM_48_36 0x0001fff000000000
3414#define BM_36_48 BM_48_36
3415#define BM_49_36 0x0003fff000000000
3416#define BM_36_49 BM_49_36
3417#define BM_50_36 0x0007fff000000000
3418#define BM_36_50 BM_50_36
3419#define BM_51_36 0x000ffff000000000
3420#define BM_36_51 BM_51_36
3421#define BM_52_36 0x001ffff000000000
3422#define BM_36_52 BM_52_36
3423#define BM_53_36 0x003ffff000000000
3424#define BM_36_53 BM_53_36
3425#define BM_54_36 0x007ffff000000000
3426#define BM_36_54 BM_54_36
3427#define BM_55_36 0x00fffff000000000
3428#define BM_36_55 BM_55_36
3429#define BM_56_36 0x01fffff000000000
3430#define BM_36_56 BM_56_36
3431#define BM_57_36 0x03fffff000000000
3432#define BM_36_57 BM_57_36
3433#define BM_58_36 0x07fffff000000000
3434#define BM_36_58 BM_58_36
3435#define BM_59_36 0x0ffffff000000000
3436#define BM_36_59 BM_59_36
3437#define BM_60_36 0x1ffffff000000000
3438#define BM_36_60 BM_60_36
3439#define BM_61_36 0x3ffffff000000000
3440#define BM_36_61 BM_61_36
3441#define BM_62_36 0x7ffffff000000000
3442#define BM_36_62 BM_62_36
3443#define BM_63_36 0xfffffff000000000
3444#define BM_36_63 BM_63_36
3445#define BM_37_37 0x0000002000000000
3446#define BM_38_37 0x0000006000000000
3447#define BM_37_38 BM_38_37
3448#define BM_39_37 0x000000e000000000
3449#define BM_37_39 BM_39_37
3450#define BM_40_37 0x000001e000000000
3451#define BM_37_40 BM_40_37
3452#define BM_41_37 0x000003e000000000
3453#define BM_37_41 BM_41_37
3454#define BM_42_37 0x000007e000000000
3455#define BM_37_42 BM_42_37
3456#define BM_43_37 0x00000fe000000000
3457#define BM_37_43 BM_43_37
3458#define BM_44_37 0x00001fe000000000
3459#define BM_37_44 BM_44_37
3460#define BM_45_37 0x00003fe000000000
3461#define BM_37_45 BM_45_37
3462#define BM_46_37 0x00007fe000000000
3463#define BM_37_46 BM_46_37
3464#define BM_47_37 0x0000ffe000000000
3465#define BM_37_47 BM_47_37
3466#define BM_48_37 0x0001ffe000000000
3467#define BM_37_48 BM_48_37
3468#define BM_49_37 0x0003ffe000000000
3469#define BM_37_49 BM_49_37
3470#define BM_50_37 0x0007ffe000000000
3471#define BM_37_50 BM_50_37
3472#define BM_51_37 0x000fffe000000000
3473#define BM_37_51 BM_51_37
3474#define BM_52_37 0x001fffe000000000
3475#define BM_37_52 BM_52_37
3476#define BM_53_37 0x003fffe000000000
3477#define BM_37_53 BM_53_37
3478#define BM_54_37 0x007fffe000000000
3479#define BM_37_54 BM_54_37
3480#define BM_55_37 0x00ffffe000000000
3481#define BM_37_55 BM_55_37
3482#define BM_56_37 0x01ffffe000000000
3483#define BM_37_56 BM_56_37
3484#define BM_57_37 0x03ffffe000000000
3485#define BM_37_57 BM_57_37
3486#define BM_58_37 0x07ffffe000000000
3487#define BM_37_58 BM_58_37
3488#define BM_59_37 0x0fffffe000000000
3489#define BM_37_59 BM_59_37
3490#define BM_60_37 0x1fffffe000000000
3491#define BM_37_60 BM_60_37
3492#define BM_61_37 0x3fffffe000000000
3493#define BM_37_61 BM_61_37
3494#define BM_62_37 0x7fffffe000000000
3495#define BM_37_62 BM_62_37
3496#define BM_63_37 0xffffffe000000000
3497#define BM_37_63 BM_63_37
3498#define BM_38_38 0x0000004000000000
3499#define BM_39_38 0x000000c000000000
3500#define BM_38_39 BM_39_38
3501#define BM_40_38 0x000001c000000000
3502#define BM_38_40 BM_40_38
3503#define BM_41_38 0x000003c000000000
3504#define BM_38_41 BM_41_38
3505#define BM_42_38 0x000007c000000000
3506#define BM_38_42 BM_42_38
3507#define BM_43_38 0x00000fc000000000
3508#define BM_38_43 BM_43_38
3509#define BM_44_38 0x00001fc000000000
3510#define BM_38_44 BM_44_38
3511#define BM_45_38 0x00003fc000000000
3512#define BM_38_45 BM_45_38
3513#define BM_46_38 0x00007fc000000000
3514#define BM_38_46 BM_46_38
3515#define BM_47_38 0x0000ffc000000000
3516#define BM_38_47 BM_47_38
3517#define BM_48_38 0x0001ffc000000000
3518#define BM_38_48 BM_48_38
3519#define BM_49_38 0x0003ffc000000000
3520#define BM_38_49 BM_49_38
3521#define BM_50_38 0x0007ffc000000000
3522#define BM_38_50 BM_50_38
3523#define BM_51_38 0x000fffc000000000
3524#define BM_38_51 BM_51_38
3525#define BM_52_38 0x001fffc000000000
3526#define BM_38_52 BM_52_38
3527#define BM_53_38 0x003fffc000000000
3528#define BM_38_53 BM_53_38
3529#define BM_54_38 0x007fffc000000000
3530#define BM_38_54 BM_54_38
3531#define BM_55_38 0x00ffffc000000000
3532#define BM_38_55 BM_55_38
3533#define BM_56_38 0x01ffffc000000000
3534#define BM_38_56 BM_56_38
3535#define BM_57_38 0x03ffffc000000000
3536#define BM_38_57 BM_57_38
3537#define BM_58_38 0x07ffffc000000000
3538#define BM_38_58 BM_58_38
3539#define BM_59_38 0x0fffffc000000000
3540#define BM_38_59 BM_59_38
3541#define BM_60_38 0x1fffffc000000000
3542#define BM_38_60 BM_60_38
3543#define BM_61_38 0x3fffffc000000000
3544#define BM_38_61 BM_61_38
3545#define BM_62_38 0x7fffffc000000000
3546#define BM_38_62 BM_62_38
3547#define BM_63_38 0xffffffc000000000
3548#define BM_38_63 BM_63_38
3549#define BM_39_39 0x0000008000000000
3550#define BM_40_39 0x0000018000000000
3551#define BM_39_40 BM_40_39
3552#define BM_41_39 0x0000038000000000
3553#define BM_39_41 BM_41_39
3554#define BM_42_39 0x0000078000000000
3555#define BM_39_42 BM_42_39
3556#define BM_43_39 0x00000f8000000000
3557#define BM_39_43 BM_43_39
3558#define BM_44_39 0x00001f8000000000
3559#define BM_39_44 BM_44_39
3560#define BM_45_39 0x00003f8000000000
3561#define BM_39_45 BM_45_39
3562#define BM_46_39 0x00007f8000000000
3563#define BM_39_46 BM_46_39
3564#define BM_47_39 0x0000ff8000000000
3565#define BM_39_47 BM_47_39
3566#define BM_48_39 0x0001ff8000000000
3567#define BM_39_48 BM_48_39
3568#define BM_49_39 0x0003ff8000000000
3569#define BM_39_49 BM_49_39
3570#define BM_50_39 0x0007ff8000000000
3571#define BM_39_50 BM_50_39
3572#define BM_51_39 0x000fff8000000000
3573#define BM_39_51 BM_51_39
3574#define BM_52_39 0x001fff8000000000
3575#define BM_39_52 BM_52_39
3576#define BM_53_39 0x003fff8000000000
3577#define BM_39_53 BM_53_39
3578#define BM_54_39 0x007fff8000000000
3579#define BM_39_54 BM_54_39
3580#define BM_55_39 0x00ffff8000000000
3581#define BM_39_55 BM_55_39
3582#define BM_56_39 0x01ffff8000000000
3583#define BM_39_56 BM_56_39
3584#define BM_57_39 0x03ffff8000000000
3585#define BM_39_57 BM_57_39
3586#define BM_58_39 0x07ffff8000000000
3587#define BM_39_58 BM_58_39
3588#define BM_59_39 0x0fffff8000000000
3589#define BM_39_59 BM_59_39
3590#define BM_60_39 0x1fffff8000000000
3591#define BM_39_60 BM_60_39
3592#define BM_61_39 0x3fffff8000000000
3593#define BM_39_61 BM_61_39
3594#define BM_62_39 0x7fffff8000000000
3595#define BM_39_62 BM_62_39
3596#define BM_63_39 0xffffff8000000000
3597#define BM_39_63 BM_63_39
3598#define BM_40_40 0x0000010000000000
3599#define BM_41_40 0x0000030000000000
3600#define BM_40_41 BM_41_40
3601#define BM_42_40 0x0000070000000000
3602#define BM_40_42 BM_42_40
3603#define BM_43_40 0x00000f0000000000
3604#define BM_40_43 BM_43_40
3605#define BM_44_40 0x00001f0000000000
3606#define BM_40_44 BM_44_40
3607#define BM_45_40 0x00003f0000000000
3608#define BM_40_45 BM_45_40
3609#define BM_46_40 0x00007f0000000000
3610#define BM_40_46 BM_46_40
3611#define BM_47_40 0x0000ff0000000000
3612#define BM_40_47 BM_47_40
3613#define BM_48_40 0x0001ff0000000000
3614#define BM_40_48 BM_48_40
3615#define BM_49_40 0x0003ff0000000000
3616#define BM_40_49 BM_49_40
3617#define BM_50_40 0x0007ff0000000000
3618#define BM_40_50 BM_50_40
3619#define BM_51_40 0x000fff0000000000
3620#define BM_40_51 BM_51_40
3621#define BM_52_40 0x001fff0000000000
3622#define BM_40_52 BM_52_40
3623#define BM_53_40 0x003fff0000000000
3624#define BM_40_53 BM_53_40
3625#define BM_54_40 0x007fff0000000000
3626#define BM_40_54 BM_54_40
3627#define BM_55_40 0x00ffff0000000000
3628#define BM_40_55 BM_55_40
3629#define BM_56_40 0x01ffff0000000000
3630#define BM_40_56 BM_56_40
3631#define BM_57_40 0x03ffff0000000000
3632#define BM_40_57 BM_57_40
3633#define BM_58_40 0x07ffff0000000000
3634#define BM_40_58 BM_58_40
3635#define BM_59_40 0x0fffff0000000000
3636#define BM_40_59 BM_59_40
3637#define BM_60_40 0x1fffff0000000000
3638#define BM_40_60 BM_60_40
3639#define BM_61_40 0x3fffff0000000000
3640#define BM_40_61 BM_61_40
3641#define BM_62_40 0x7fffff0000000000
3642#define BM_40_62 BM_62_40
3643#define BM_63_40 0xffffff0000000000
3644#define BM_40_63 BM_63_40
3645#define BM_41_41 0x0000020000000000
3646#define BM_42_41 0x0000060000000000
3647#define BM_41_42 BM_42_41
3648#define BM_43_41 0x00000e0000000000
3649#define BM_41_43 BM_43_41
3650#define BM_44_41 0x00001e0000000000
3651#define BM_41_44 BM_44_41
3652#define BM_45_41 0x00003e0000000000
3653#define BM_41_45 BM_45_41
3654#define BM_46_41 0x00007e0000000000
3655#define BM_41_46 BM_46_41
3656#define BM_47_41 0x0000fe0000000000
3657#define BM_41_47 BM_47_41
3658#define BM_48_41 0x0001fe0000000000
3659#define BM_41_48 BM_48_41
3660#define BM_49_41 0x0003fe0000000000
3661#define BM_41_49 BM_49_41
3662#define BM_50_41 0x0007fe0000000000
3663#define BM_41_50 BM_50_41
3664#define BM_51_41 0x000ffe0000000000
3665#define BM_41_51 BM_51_41
3666#define BM_52_41 0x001ffe0000000000
3667#define BM_41_52 BM_52_41
3668#define BM_53_41 0x003ffe0000000000
3669#define BM_41_53 BM_53_41
3670#define BM_54_41 0x007ffe0000000000
3671#define BM_41_54 BM_54_41
3672#define BM_55_41 0x00fffe0000000000
3673#define BM_41_55 BM_55_41
3674#define BM_56_41 0x01fffe0000000000
3675#define BM_41_56 BM_56_41
3676#define BM_57_41 0x03fffe0000000000
3677#define BM_41_57 BM_57_41
3678#define BM_58_41 0x07fffe0000000000
3679#define BM_41_58 BM_58_41
3680#define BM_59_41 0x0ffffe0000000000
3681#define BM_41_59 BM_59_41
3682#define BM_60_41 0x1ffffe0000000000
3683#define BM_41_60 BM_60_41
3684#define BM_61_41 0x3ffffe0000000000
3685#define BM_41_61 BM_61_41
3686#define BM_62_41 0x7ffffe0000000000
3687#define BM_41_62 BM_62_41
3688#define BM_63_41 0xfffffe0000000000
3689#define BM_41_63 BM_63_41
3690#define BM_42_42 0x0000040000000000
3691#define BM_43_42 0x00000c0000000000
3692#define BM_42_43 BM_43_42
3693#define BM_44_42 0x00001c0000000000
3694#define BM_42_44 BM_44_42
3695#define BM_45_42 0x00003c0000000000
3696#define BM_42_45 BM_45_42
3697#define BM_46_42 0x00007c0000000000
3698#define BM_42_46 BM_46_42
3699#define BM_47_42 0x0000fc0000000000
3700#define BM_42_47 BM_47_42
3701#define BM_48_42 0x0001fc0000000000
3702#define BM_42_48 BM_48_42
3703#define BM_49_42 0x0003fc0000000000
3704#define BM_42_49 BM_49_42
3705#define BM_50_42 0x0007fc0000000000
3706#define BM_42_50 BM_50_42
3707#define BM_51_42 0x000ffc0000000000
3708#define BM_42_51 BM_51_42
3709#define BM_52_42 0x001ffc0000000000
3710#define BM_42_52 BM_52_42
3711#define BM_53_42 0x003ffc0000000000
3712#define BM_42_53 BM_53_42
3713#define BM_54_42 0x007ffc0000000000
3714#define BM_42_54 BM_54_42
3715#define BM_55_42 0x00fffc0000000000
3716#define BM_42_55 BM_55_42
3717#define BM_56_42 0x01fffc0000000000
3718#define BM_42_56 BM_56_42
3719#define BM_57_42 0x03fffc0000000000
3720#define BM_42_57 BM_57_42
3721#define BM_58_42 0x07fffc0000000000
3722#define BM_42_58 BM_58_42
3723#define BM_59_42 0x0ffffc0000000000
3724#define BM_42_59 BM_59_42
3725#define BM_60_42 0x1ffffc0000000000
3726#define BM_42_60 BM_60_42
3727#define BM_61_42 0x3ffffc0000000000
3728#define BM_42_61 BM_61_42
3729#define BM_62_42 0x7ffffc0000000000
3730#define BM_42_62 BM_62_42
3731#define BM_63_42 0xfffffc0000000000
3732#define BM_42_63 BM_63_42
3733#define BM_43_43 0x0000080000000000
3734#define BM_44_43 0x0000180000000000
3735#define BM_43_44 BM_44_43
3736#define BM_45_43 0x0000380000000000
3737#define BM_43_45 BM_45_43
3738#define BM_46_43 0x0000780000000000
3739#define BM_43_46 BM_46_43
3740#define BM_47_43 0x0000f80000000000
3741#define BM_43_47 BM_47_43
3742#define BM_48_43 0x0001f80000000000
3743#define BM_43_48 BM_48_43
3744#define BM_49_43 0x0003f80000000000
3745#define BM_43_49 BM_49_43
3746#define BM_50_43 0x0007f80000000000
3747#define BM_43_50 BM_50_43
3748#define BM_51_43 0x000ff80000000000
3749#define BM_43_51 BM_51_43
3750#define BM_52_43 0x001ff80000000000
3751#define BM_43_52 BM_52_43
3752#define BM_53_43 0x003ff80000000000
3753#define BM_43_53 BM_53_43
3754#define BM_54_43 0x007ff80000000000
3755#define BM_43_54 BM_54_43
3756#define BM_55_43 0x00fff80000000000
3757#define BM_43_55 BM_55_43
3758#define BM_56_43 0x01fff80000000000
3759#define BM_43_56 BM_56_43
3760#define BM_57_43 0x03fff80000000000
3761#define BM_43_57 BM_57_43
3762#define BM_58_43 0x07fff80000000000
3763#define BM_43_58 BM_58_43
3764#define BM_59_43 0x0ffff80000000000
3765#define BM_43_59 BM_59_43
3766#define BM_60_43 0x1ffff80000000000
3767#define BM_43_60 BM_60_43
3768#define BM_61_43 0x3ffff80000000000
3769#define BM_43_61 BM_61_43
3770#define BM_62_43 0x7ffff80000000000
3771#define BM_43_62 BM_62_43
3772#define BM_63_43 0xfffff80000000000
3773#define BM_43_63 BM_63_43
3774#define BM_44_44 0x0000100000000000
3775#define BM_45_44 0x0000300000000000
3776#define BM_44_45 BM_45_44
3777#define BM_46_44 0x0000700000000000
3778#define BM_44_46 BM_46_44
3779#define BM_47_44 0x0000f00000000000
3780#define BM_44_47 BM_47_44
3781#define BM_48_44 0x0001f00000000000
3782#define BM_44_48 BM_48_44
3783#define BM_49_44 0x0003f00000000000
3784#define BM_44_49 BM_49_44
3785#define BM_50_44 0x0007f00000000000
3786#define BM_44_50 BM_50_44
3787#define BM_51_44 0x000ff00000000000
3788#define BM_44_51 BM_51_44
3789#define BM_52_44 0x001ff00000000000
3790#define BM_44_52 BM_52_44
3791#define BM_53_44 0x003ff00000000000
3792#define BM_44_53 BM_53_44
3793#define BM_54_44 0x007ff00000000000
3794#define BM_44_54 BM_54_44
3795#define BM_55_44 0x00fff00000000000
3796#define BM_44_55 BM_55_44
3797#define BM_56_44 0x01fff00000000000
3798#define BM_44_56 BM_56_44
3799#define BM_57_44 0x03fff00000000000
3800#define BM_44_57 BM_57_44
3801#define BM_58_44 0x07fff00000000000
3802#define BM_44_58 BM_58_44
3803#define BM_59_44 0x0ffff00000000000
3804#define BM_44_59 BM_59_44
3805#define BM_60_44 0x1ffff00000000000
3806#define BM_44_60 BM_60_44
3807#define BM_61_44 0x3ffff00000000000
3808#define BM_44_61 BM_61_44
3809#define BM_62_44 0x7ffff00000000000
3810#define BM_44_62 BM_62_44
3811#define BM_63_44 0xfffff00000000000
3812#define BM_44_63 BM_63_44
3813#define BM_45_45 0x0000200000000000
3814#define BM_46_45 0x0000600000000000
3815#define BM_45_46 BM_46_45
3816#define BM_47_45 0x0000e00000000000
3817#define BM_45_47 BM_47_45
3818#define BM_48_45 0x0001e00000000000
3819#define BM_45_48 BM_48_45
3820#define BM_49_45 0x0003e00000000000
3821#define BM_45_49 BM_49_45
3822#define BM_50_45 0x0007e00000000000
3823#define BM_45_50 BM_50_45
3824#define BM_51_45 0x000fe00000000000
3825#define BM_45_51 BM_51_45
3826#define BM_52_45 0x001fe00000000000
3827#define BM_45_52 BM_52_45
3828#define BM_53_45 0x003fe00000000000
3829#define BM_45_53 BM_53_45
3830#define BM_54_45 0x007fe00000000000
3831#define BM_45_54 BM_54_45
3832#define BM_55_45 0x00ffe00000000000
3833#define BM_45_55 BM_55_45
3834#define BM_56_45 0x01ffe00000000000
3835#define BM_45_56 BM_56_45
3836#define BM_57_45 0x03ffe00000000000
3837#define BM_45_57 BM_57_45
3838#define BM_58_45 0x07ffe00000000000
3839#define BM_45_58 BM_58_45
3840#define BM_59_45 0x0fffe00000000000
3841#define BM_45_59 BM_59_45
3842#define BM_60_45 0x1fffe00000000000
3843#define BM_45_60 BM_60_45
3844#define BM_61_45 0x3fffe00000000000
3845#define BM_45_61 BM_61_45
3846#define BM_62_45 0x7fffe00000000000
3847#define BM_45_62 BM_62_45
3848#define BM_63_45 0xffffe00000000000
3849#define BM_45_63 BM_63_45
3850#define BM_46_46 0x0000400000000000
3851#define BM_47_46 0x0000c00000000000
3852#define BM_46_47 BM_47_46
3853#define BM_48_46 0x0001c00000000000
3854#define BM_46_48 BM_48_46
3855#define BM_49_46 0x0003c00000000000
3856#define BM_46_49 BM_49_46
3857#define BM_50_46 0x0007c00000000000
3858#define BM_46_50 BM_50_46
3859#define BM_51_46 0x000fc00000000000
3860#define BM_46_51 BM_51_46
3861#define BM_52_46 0x001fc00000000000
3862#define BM_46_52 BM_52_46
3863#define BM_53_46 0x003fc00000000000
3864#define BM_46_53 BM_53_46
3865#define BM_54_46 0x007fc00000000000
3866#define BM_46_54 BM_54_46
3867#define BM_55_46 0x00ffc00000000000
3868#define BM_46_55 BM_55_46
3869#define BM_56_46 0x01ffc00000000000
3870#define BM_46_56 BM_56_46
3871#define BM_57_46 0x03ffc00000000000
3872#define BM_46_57 BM_57_46
3873#define BM_58_46 0x07ffc00000000000
3874#define BM_46_58 BM_58_46
3875#define BM_59_46 0x0fffc00000000000
3876#define BM_46_59 BM_59_46
3877#define BM_60_46 0x1fffc00000000000
3878#define BM_46_60 BM_60_46
3879#define BM_61_46 0x3fffc00000000000
3880#define BM_46_61 BM_61_46
3881#define BM_62_46 0x7fffc00000000000
3882#define BM_46_62 BM_62_46
3883#define BM_63_46 0xffffc00000000000
3884#define BM_46_63 BM_63_46
3885#define BM_47_47 0x0000800000000000
3886#define BM_48_47 0x0001800000000000
3887#define BM_47_48 BM_48_47
3888#define BM_49_47 0x0003800000000000
3889#define BM_47_49 BM_49_47
3890#define BM_50_47 0x0007800000000000
3891#define BM_47_50 BM_50_47
3892#define BM_51_47 0x000f800000000000
3893#define BM_47_51 BM_51_47
3894#define BM_52_47 0x001f800000000000
3895#define BM_47_52 BM_52_47
3896#define BM_53_47 0x003f800000000000
3897#define BM_47_53 BM_53_47
3898#define BM_54_47 0x007f800000000000
3899#define BM_47_54 BM_54_47
3900#define BM_55_47 0x00ff800000000000
3901#define BM_47_55 BM_55_47
3902#define BM_56_47 0x01ff800000000000
3903#define BM_47_56 BM_56_47
3904#define BM_57_47 0x03ff800000000000
3905#define BM_47_57 BM_57_47
3906#define BM_58_47 0x07ff800000000000
3907#define BM_47_58 BM_58_47
3908#define BM_59_47 0x0fff800000000000
3909#define BM_47_59 BM_59_47
3910#define BM_60_47 0x1fff800000000000
3911#define BM_47_60 BM_60_47
3912#define BM_61_47 0x3fff800000000000
3913#define BM_47_61 BM_61_47
3914#define BM_62_47 0x7fff800000000000
3915#define BM_47_62 BM_62_47
3916#define BM_63_47 0xffff800000000000
3917#define BM_47_63 BM_63_47
3918#define BM_48_48 0x0001000000000000
3919#define BM_49_48 0x0003000000000000
3920#define BM_48_49 BM_49_48
3921#define BM_50_48 0x0007000000000000
3922#define BM_48_50 BM_50_48
3923#define BM_51_48 0x000f000000000000
3924#define BM_48_51 BM_51_48
3925#define BM_52_48 0x001f000000000000
3926#define BM_48_52 BM_52_48
3927#define BM_53_48 0x003f000000000000
3928#define BM_48_53 BM_53_48
3929#define BM_54_48 0x007f000000000000
3930#define BM_48_54 BM_54_48
3931#define BM_55_48 0x00ff000000000000
3932#define BM_48_55 BM_55_48
3933#define BM_56_48 0x01ff000000000000
3934#define BM_48_56 BM_56_48
3935#define BM_57_48 0x03ff000000000000
3936#define BM_48_57 BM_57_48
3937#define BM_58_48 0x07ff000000000000
3938#define BM_48_58 BM_58_48
3939#define BM_59_48 0x0fff000000000000
3940#define BM_48_59 BM_59_48
3941#define BM_60_48 0x1fff000000000000
3942#define BM_48_60 BM_60_48
3943#define BM_61_48 0x3fff000000000000
3944#define BM_48_61 BM_61_48
3945#define BM_62_48 0x7fff000000000000
3946#define BM_48_62 BM_62_48
3947#define BM_63_48 0xffff000000000000
3948#define BM_48_63 BM_63_48
3949#define BM_49_49 0x0002000000000000
3950#define BM_50_49 0x0006000000000000
3951#define BM_49_50 BM_50_49
3952#define BM_51_49 0x000e000000000000
3953#define BM_49_51 BM_51_49
3954#define BM_52_49 0x001e000000000000
3955#define BM_49_52 BM_52_49
3956#define BM_53_49 0x003e000000000000
3957#define BM_49_53 BM_53_49
3958#define BM_54_49 0x007e000000000000
3959#define BM_49_54 BM_54_49
3960#define BM_55_49 0x00fe000000000000
3961#define BM_49_55 BM_55_49
3962#define BM_56_49 0x01fe000000000000
3963#define BM_49_56 BM_56_49
3964#define BM_57_49 0x03fe000000000000
3965#define BM_49_57 BM_57_49
3966#define BM_58_49 0x07fe000000000000
3967#define BM_49_58 BM_58_49
3968#define BM_59_49 0x0ffe000000000000
3969#define BM_49_59 BM_59_49
3970#define BM_60_49 0x1ffe000000000000
3971#define BM_49_60 BM_60_49
3972#define BM_61_49 0x3ffe000000000000
3973#define BM_49_61 BM_61_49
3974#define BM_62_49 0x7ffe000000000000
3975#define BM_49_62 BM_62_49
3976#define BM_63_49 0xfffe000000000000
3977#define BM_49_63 BM_63_49
3978#define BM_50_50 0x0004000000000000
3979#define BM_51_50 0x000c000000000000
3980#define BM_50_51 BM_51_50
3981#define BM_52_50 0x001c000000000000
3982#define BM_50_52 BM_52_50
3983#define BM_53_50 0x003c000000000000
3984#define BM_50_53 BM_53_50
3985#define BM_54_50 0x007c000000000000
3986#define BM_50_54 BM_54_50
3987#define BM_55_50 0x00fc000000000000
3988#define BM_50_55 BM_55_50
3989#define BM_56_50 0x01fc000000000000
3990#define BM_50_56 BM_56_50
3991#define BM_57_50 0x03fc000000000000
3992#define BM_50_57 BM_57_50
3993#define BM_58_50 0x07fc000000000000
3994#define BM_50_58 BM_58_50
3995#define BM_59_50 0x0ffc000000000000
3996#define BM_50_59 BM_59_50
3997#define BM_60_50 0x1ffc000000000000
3998#define BM_50_60 BM_60_50
3999#define BM_61_50 0x3ffc000000000000
4000#define BM_50_61 BM_61_50
4001#define BM_62_50 0x7ffc000000000000
4002#define BM_50_62 BM_62_50
4003#define BM_63_50 0xfffc000000000000
4004#define BM_50_63 BM_63_50
4005#define BM_51_51 0x0008000000000000
4006#define BM_52_51 0x0018000000000000
4007#define BM_51_52 BM_52_51
4008#define BM_53_51 0x0038000000000000
4009#define BM_51_53 BM_53_51
4010#define BM_54_51 0x0078000000000000
4011#define BM_51_54 BM_54_51
4012#define BM_55_51 0x00f8000000000000
4013#define BM_51_55 BM_55_51
4014#define BM_56_51 0x01f8000000000000
4015#define BM_51_56 BM_56_51
4016#define BM_57_51 0x03f8000000000000
4017#define BM_51_57 BM_57_51
4018#define BM_58_51 0x07f8000000000000
4019#define BM_51_58 BM_58_51
4020#define BM_59_51 0x0ff8000000000000
4021#define BM_51_59 BM_59_51
4022#define BM_60_51 0x1ff8000000000000
4023#define BM_51_60 BM_60_51
4024#define BM_61_51 0x3ff8000000000000
4025#define BM_51_61 BM_61_51
4026#define BM_62_51 0x7ff8000000000000
4027#define BM_51_62 BM_62_51
4028#define BM_63_51 0xfff8000000000000
4029#define BM_51_63 BM_63_51
4030#define BM_52_52 0x0010000000000000
4031#define BM_53_52 0x0030000000000000
4032#define BM_52_53 BM_53_52
4033#define BM_54_52 0x0070000000000000
4034#define BM_52_54 BM_54_52
4035#define BM_55_52 0x00f0000000000000
4036#define BM_52_55 BM_55_52
4037#define BM_56_52 0x01f0000000000000
4038#define BM_52_56 BM_56_52
4039#define BM_57_52 0x03f0000000000000
4040#define BM_52_57 BM_57_52
4041#define BM_58_52 0x07f0000000000000
4042#define BM_52_58 BM_58_52
4043#define BM_59_52 0x0ff0000000000000
4044#define BM_52_59 BM_59_52
4045#define BM_60_52 0x1ff0000000000000
4046#define BM_52_60 BM_60_52
4047#define BM_61_52 0x3ff0000000000000
4048#define BM_52_61 BM_61_52
4049#define BM_62_52 0x7ff0000000000000
4050#define BM_52_62 BM_62_52
4051#define BM_63_52 0xfff0000000000000
4052#define BM_52_63 BM_63_52
4053#define BM_53_53 0x0020000000000000
4054#define BM_54_53 0x0060000000000000
4055#define BM_53_54 BM_54_53
4056#define BM_55_53 0x00e0000000000000
4057#define BM_53_55 BM_55_53
4058#define BM_56_53 0x01e0000000000000
4059#define BM_53_56 BM_56_53
4060#define BM_57_53 0x03e0000000000000
4061#define BM_53_57 BM_57_53
4062#define BM_58_53 0x07e0000000000000
4063#define BM_53_58 BM_58_53
4064#define BM_59_53 0x0fe0000000000000
4065#define BM_53_59 BM_59_53
4066#define BM_60_53 0x1fe0000000000000
4067#define BM_53_60 BM_60_53
4068#define BM_61_53 0x3fe0000000000000
4069#define BM_53_61 BM_61_53
4070#define BM_62_53 0x7fe0000000000000
4071#define BM_53_62 BM_62_53
4072#define BM_63_53 0xffe0000000000000
4073#define BM_53_63 BM_63_53
4074#define BM_54_54 0x0040000000000000
4075#define BM_55_54 0x00c0000000000000
4076#define BM_54_55 BM_55_54
4077#define BM_56_54 0x01c0000000000000
4078#define BM_54_56 BM_56_54
4079#define BM_57_54 0x03c0000000000000
4080#define BM_54_57 BM_57_54
4081#define BM_58_54 0x07c0000000000000
4082#define BM_54_58 BM_58_54
4083#define BM_59_54 0x0fc0000000000000
4084#define BM_54_59 BM_59_54
4085#define BM_60_54 0x1fc0000000000000
4086#define BM_54_60 BM_60_54
4087#define BM_61_54 0x3fc0000000000000
4088#define BM_54_61 BM_61_54
4089#define BM_62_54 0x7fc0000000000000
4090#define BM_54_62 BM_62_54
4091#define BM_63_54 0xffc0000000000000
4092#define BM_54_63 BM_63_54
4093#define BM_55_55 0x0080000000000000
4094#define BM_56_55 0x0180000000000000
4095#define BM_55_56 BM_56_55
4096#define BM_57_55 0x0380000000000000
4097#define BM_55_57 BM_57_55
4098#define BM_58_55 0x0780000000000000
4099#define BM_55_58 BM_58_55
4100#define BM_59_55 0x0f80000000000000
4101#define BM_55_59 BM_59_55
4102#define BM_60_55 0x1f80000000000000
4103#define BM_55_60 BM_60_55
4104#define BM_61_55 0x3f80000000000000
4105#define BM_55_61 BM_61_55
4106#define BM_62_55 0x7f80000000000000
4107#define BM_55_62 BM_62_55
4108#define BM_63_55 0xff80000000000000
4109#define BM_55_63 BM_63_55
4110#define BM_56_56 0x0100000000000000
4111#define BM_57_56 0x0300000000000000
4112#define BM_56_57 BM_57_56
4113#define BM_58_56 0x0700000000000000
4114#define BM_56_58 BM_58_56
4115#define BM_59_56 0x0f00000000000000
4116#define BM_56_59 BM_59_56
4117#define BM_60_56 0x1f00000000000000
4118#define BM_56_60 BM_60_56
4119#define BM_61_56 0x3f00000000000000
4120#define BM_56_61 BM_61_56
4121#define BM_62_56 0x7f00000000000000
4122#define BM_56_62 BM_62_56
4123#define BM_63_56 0xff00000000000000
4124#define BM_56_63 BM_63_56
4125#define BM_57_57 0x0200000000000000
4126#define BM_58_57 0x0600000000000000
4127#define BM_57_58 BM_58_57
4128#define BM_59_57 0x0e00000000000000
4129#define BM_57_59 BM_59_57
4130#define BM_60_57 0x1e00000000000000
4131#define BM_57_60 BM_60_57
4132#define BM_61_57 0x3e00000000000000
4133#define BM_57_61 BM_61_57
4134#define BM_62_57 0x7e00000000000000
4135#define BM_57_62 BM_62_57
4136#define BM_63_57 0xfe00000000000000
4137#define BM_57_63 BM_63_57
4138#define BM_58_58 0x0400000000000000
4139#define BM_59_58 0x0c00000000000000
4140#define BM_58_59 BM_59_58
4141#define BM_60_58 0x1c00000000000000
4142#define BM_58_60 BM_60_58
4143#define BM_61_58 0x3c00000000000000
4144#define BM_58_61 BM_61_58
4145#define BM_62_58 0x7c00000000000000
4146#define BM_58_62 BM_62_58
4147#define BM_63_58 0xfc00000000000000
4148#define BM_58_63 BM_63_58
4149#define BM_59_59 0x0800000000000000
4150#define BM_60_59 0x1800000000000000
4151#define BM_59_60 BM_60_59
4152#define BM_61_59 0x3800000000000000
4153#define BM_59_61 BM_61_59
4154#define BM_62_59 0x7800000000000000
4155#define BM_59_62 BM_62_59
4156#define BM_63_59 0xf800000000000000
4157#define BM_59_63 BM_63_59
4158#define BM_60_60 0x1000000000000000
4159#define BM_61_60 0x3000000000000000
4160#define BM_60_61 BM_61_60
4161#define BM_62_60 0x7000000000000000
4162#define BM_60_62 BM_62_60
4163#define BM_63_60 0xf000000000000000
4164#define BM_60_63 BM_63_60
4165#define BM_61_61 0x2000000000000000
4166#define BM_62_61 0x6000000000000000
4167#define BM_61_62 BM_62_61
4168#define BM_63_61 0xe000000000000000
4169#define BM_61_63 BM_63_61
4170#define BM_62_62 0x4000000000000000
4171#define BM_63_62 0xc000000000000000
4172#define BM_62_63 BM_63_62
4173#define BM_63_63 0x8000000000000000
4174
4175#endif
4176
4177#endif /* __ASM_TX4927_TX4927_MIPS_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index b14acb575be2..b180488dcdc4 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -153,7 +153,7 @@
153#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) 153#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
154#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) 154#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
155#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) 155#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
156#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) 156#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
157#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) 157#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
158#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) 158#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
159#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) 159#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index afdb19813ca1..650b010761f9 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -16,7 +16,7 @@
16#include <asm/tx4938/tx4938_mips.h> 16#include <asm/tx4938/tx4938_mips.h>
17 17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
19#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) 19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
20 20
21#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG 21#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG
22 22
@@ -84,27 +84,27 @@
84#include <asm/byteorder.h> 84#include <asm/byteorder.h>
85 85
86#ifdef __BIG_ENDIAN 86#ifdef __BIG_ENDIAN
87#define endian_def_l2(e1,e2) \ 87#define endian_def_l2(e1, e2) \
88 volatile unsigned long e1,e2 88 volatile unsigned long e1, e2
89#define endian_def_s2(e1,e2) \ 89#define endian_def_s2(e1, e2) \
90 volatile unsigned short e1,e2 90 volatile unsigned short e1, e2
91#define endian_def_sb2(e1,e2,e3) \ 91#define endian_def_sb2(e1, e2, e3) \
92 volatile unsigned short e1;volatile unsigned char e2,e3 92 volatile unsigned short e1;volatile unsigned char e2, e3
93#define endian_def_b2s(e1,e2,e3) \ 93#define endian_def_b2s(e1, e2, e3) \
94 volatile unsigned char e1,e2;volatile unsigned short e3 94 volatile unsigned char e1, e2;volatile unsigned short e3
95#define endian_def_b4(e1,e2,e3,e4) \ 95#define endian_def_b4(e1, e2, e3, e4) \
96 volatile unsigned char e1,e2,e3,e4 96 volatile unsigned char e1, e2, e3, e4
97#else 97#else
98#define endian_def_l2(e1,e2) \ 98#define endian_def_l2(e1, e2) \
99 volatile unsigned long e2,e1 99 volatile unsigned long e2, e1
100#define endian_def_s2(e1,e2) \ 100#define endian_def_s2(e1, e2) \
101 volatile unsigned short e2,e1 101 volatile unsigned short e2, e1
102#define endian_def_sb2(e1,e2,e3) \ 102#define endian_def_sb2(e1, e2, e3) \
103 volatile unsigned char e3,e2;volatile unsigned short e1 103 volatile unsigned char e3, e2;volatile unsigned short e1
104#define endian_def_b2s(e1,e2,e3) \ 104#define endian_def_b2s(e1, e2, e3) \
105 volatile unsigned short e3;volatile unsigned char e2,e1 105 volatile unsigned short e3;volatile unsigned char e2, e1
106#define endian_def_b4(e1,e2,e3,e4) \ 106#define endian_def_b4(e1, e2, e3, e4) \
107 volatile unsigned char e4,e3,e2,e1 107 volatile unsigned char e4, e3, e2, e1
108#endif 108#endif
109 109
110 110
@@ -354,7 +354,7 @@ struct tx4938_ccfg_reg {
354#define TX4938_NUM_IR_SIO 2 354#define TX4938_NUM_IR_SIO 2
355#define TX4938_IR_SIO(n) (8 + (n)) 355#define TX4938_IR_SIO(n) (8 + (n))
356#define TX4938_NUM_IR_DMA 4 356#define TX4938_NUM_IR_DMA 4
357#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ 357#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
358#define TX4938_IR_PIO 14 358#define TX4938_IR_PIO 14
359#define TX4938_IR_PDMAC 15 359#define TX4938_IR_PDMAC 15
360#define TX4938_IR_PCIC 16 360#define TX4938_IR_PCIC 16
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
index 5f8498fef005..f346ff58b947 100644
--- a/include/asm-mips/tx4938/tx4938_mips.h
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -19,10 +19,10 @@
19#define reg_rd32(r) ((u32)(*((vu32*)(r)))) 19#define reg_rd32(r) ((u32)(*((vu32*)(r))))
20#define reg_rd64(r) ((u64)(*((vu64*)(r)))) 20#define reg_rd64(r) ((u64)(*((vu64*)(r))))
21 21
22#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) 22#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v)))
23#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) 23#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v)))
24#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) 24#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v)))
25#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) 25#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v)))
26 26
27typedef volatile __signed char vs8; 27typedef volatile __signed char vs8;
28typedef volatile unsigned char vu8; 28typedef volatile unsigned char vu8;
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index b25511787ee0..c30c718994c9 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -63,7 +63,7 @@
63#define get_fs() (current_thread_info()->addr_limit) 63#define get_fs() (current_thread_info()->addr_limit)
64#define set_fs(x) (current_thread_info()->addr_limit = (x)) 64#define set_fs(x) (current_thread_info()->addr_limit = (x))
65 65
66#define segment_eq(a,b) ((a).seg == (b).seg) 66#define segment_eq(a, b) ((a).seg == (b).seg)
67 67
68 68
69/* 69/*
@@ -108,7 +108,7 @@
108 (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) 108 (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0)
109 109
110#define access_ok(type, addr, size) \ 110#define access_ok(type, addr, size) \
111 likely(__access_ok((unsigned long)(addr), (size),__access_mask)) 111 likely(__access_ok((unsigned long)(addr), (size), __access_mask))
112 112
113/* 113/*
114 * put_user: - Write a simple value into user space. 114 * put_user: - Write a simple value into user space.
@@ -127,7 +127,7 @@
127 * Returns zero on success, or -EFAULT on error. 127 * Returns zero on success, or -EFAULT on error.
128 */ 128 */
129#define put_user(x,ptr) \ 129#define put_user(x,ptr) \
130 __put_user_check((x),(ptr),sizeof(*(ptr))) 130 __put_user_check((x), (ptr), sizeof(*(ptr)))
131 131
132/* 132/*
133 * get_user: - Get a simple variable from user space. 133 * get_user: - Get a simple variable from user space.
@@ -147,7 +147,7 @@
147 * On error, the variable @x is set to zero. 147 * On error, the variable @x is set to zero.
148 */ 148 */
149#define get_user(x,ptr) \ 149#define get_user(x,ptr) \
150 __get_user_check((x),(ptr),sizeof(*(ptr))) 150 __get_user_check((x), (ptr), sizeof(*(ptr)))
151 151
152/* 152/*
153 * __put_user: - Write a simple value into user space, with less checking. 153 * __put_user: - Write a simple value into user space, with less checking.
@@ -169,7 +169,7 @@
169 * Returns zero on success, or -EFAULT on error. 169 * Returns zero on success, or -EFAULT on error.
170 */ 170 */
171#define __put_user(x,ptr) \ 171#define __put_user(x,ptr) \
172 __put_user_nocheck((x),(ptr),sizeof(*(ptr))) 172 __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
173 173
174/* 174/*
175 * __get_user: - Get a simple variable from user space, with less checking. 175 * __get_user: - Get a simple variable from user space, with less checking.
@@ -192,7 +192,7 @@
192 * On error, the variable @x is set to zero. 192 * On error, the variable @x is set to zero.
193 */ 193 */
194#define __get_user(x,ptr) \ 194#define __get_user(x,ptr) \
195 __get_user_nocheck((x),(ptr),sizeof(*(ptr))) 195 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
196 196
197struct __large_struct { unsigned long buf[100]; }; 197struct __large_struct { unsigned long buf[100]; };
198#define __m(x) (*(struct __large_struct __user *)(x)) 198#define __m(x) (*(struct __large_struct __user *)(x))
@@ -221,7 +221,7 @@ do { \
221 } \ 221 } \
222} while (0) 222} while (0)
223 223
224#define __get_user_nocheck(x,ptr,size) \ 224#define __get_user_nocheck(x, ptr, size) \
225({ \ 225({ \
226 long __gu_err; \ 226 long __gu_err; \
227 \ 227 \
@@ -229,7 +229,7 @@ do { \
229 __gu_err; \ 229 __gu_err; \
230}) 230})
231 231
232#define __get_user_check(x,ptr,size) \ 232#define __get_user_check(x, ptr, size) \
233({ \ 233({ \
234 long __gu_err = -EFAULT; \ 234 long __gu_err = -EFAULT; \
235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ 235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \
@@ -300,7 +300,7 @@ do { \
300#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) 300#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
301#endif 301#endif
302 302
303#define __put_user_nocheck(x,ptr,size) \ 303#define __put_user_nocheck(x, ptr, size) \
304({ \ 304({ \
305 __typeof__(*(ptr)) __pu_val; \ 305 __typeof__(*(ptr)) __pu_val; \
306 long __pu_err = 0; \ 306 long __pu_err = 0; \
@@ -316,7 +316,7 @@ do { \
316 __pu_err; \ 316 __pu_err; \
317}) 317})
318 318
319#define __put_user_check(x,ptr,size) \ 319#define __put_user_check(x, ptr, size) \
320({ \ 320({ \
321 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ 321 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
322 __typeof__(*(ptr)) __pu_val = (x); \ 322 __typeof__(*(ptr)) __pu_val = (x); \
@@ -389,11 +389,11 @@ extern void __put_user_unknown(void);
389 389
390extern size_t __copy_user(void *__to, const void *__from, size_t __n); 390extern size_t __copy_user(void *__to, const void *__from, size_t __n);
391 391
392#define __invoke_copy_to_user(to,from,n) \ 392#define __invoke_copy_to_user(to, from, n) \
393({ \ 393({ \
394 register void __user *__cu_to_r __asm__ ("$4"); \ 394 register void __user *__cu_to_r __asm__("$4"); \
395 register const void *__cu_from_r __asm__ ("$5"); \ 395 register const void *__cu_from_r __asm__("$5"); \
396 register long __cu_len_r __asm__ ("$6"); \ 396 register long __cu_len_r __asm__("$6"); \
397 \ 397 \
398 __cu_to_r = (to); \ 398 __cu_to_r = (to); \
399 __cu_from_r = (from); \ 399 __cu_from_r = (from); \
@@ -421,7 +421,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
421 * Returns number of bytes that could not be copied. 421 * Returns number of bytes that could not be copied.
422 * On success, this will be zero. 422 * On success, this will be zero.
423 */ 423 */
424#define __copy_to_user(to,from,n) \ 424#define __copy_to_user(to, from, n) \
425({ \ 425({ \
426 void __user *__cu_to; \ 426 void __user *__cu_to; \
427 const void *__cu_from; \ 427 const void *__cu_from; \
@@ -437,7 +437,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
437 437
438extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); 438extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
439 439
440#define __copy_to_user_inatomic(to,from,n) \ 440#define __copy_to_user_inatomic(to, from, n) \
441({ \ 441({ \
442 void __user *__cu_to; \ 442 void __user *__cu_to; \
443 const void *__cu_from; \ 443 const void *__cu_from; \
@@ -450,7 +450,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
450 __cu_len; \ 450 __cu_len; \
451}) 451})
452 452
453#define __copy_from_user_inatomic(to,from,n) \ 453#define __copy_from_user_inatomic(to, from, n) \
454({ \ 454({ \
455 void *__cu_to; \ 455 void *__cu_to; \
456 const void __user *__cu_from; \ 456 const void __user *__cu_from; \
@@ -477,7 +477,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
477 * Returns number of bytes that could not be copied. 477 * Returns number of bytes that could not be copied.
478 * On success, this will be zero. 478 * On success, this will be zero.
479 */ 479 */
480#define copy_to_user(to,from,n) \ 480#define copy_to_user(to, from, n) \
481({ \ 481({ \
482 void __user *__cu_to; \ 482 void __user *__cu_to; \
483 const void *__cu_from; \ 483 const void *__cu_from; \
@@ -493,11 +493,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
493 __cu_len; \ 493 __cu_len; \
494}) 494})
495 495
496#define __invoke_copy_from_user(to,from,n) \ 496#define __invoke_copy_from_user(to, from, n) \
497({ \ 497({ \
498 register void *__cu_to_r __asm__ ("$4"); \ 498 register void *__cu_to_r __asm__("$4"); \
499 register const void __user *__cu_from_r __asm__ ("$5"); \ 499 register const void __user *__cu_from_r __asm__("$5"); \
500 register long __cu_len_r __asm__ ("$6"); \ 500 register long __cu_len_r __asm__("$6"); \
501 \ 501 \
502 __cu_to_r = (to); \ 502 __cu_to_r = (to); \
503 __cu_from_r = (from); \ 503 __cu_from_r = (from); \
@@ -516,11 +516,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
516 __cu_len_r; \ 516 __cu_len_r; \
517}) 517})
518 518
519#define __invoke_copy_from_user_inatomic(to,from,n) \ 519#define __invoke_copy_from_user_inatomic(to, from, n) \
520({ \ 520({ \
521 register void *__cu_to_r __asm__ ("$4"); \ 521 register void *__cu_to_r __asm__("$4"); \
522 register const void __user *__cu_from_r __asm__ ("$5"); \ 522 register const void __user *__cu_from_r __asm__("$5"); \
523 register long __cu_len_r __asm__ ("$6"); \ 523 register long __cu_len_r __asm__("$6"); \
524 \ 524 \
525 __cu_to_r = (to); \ 525 __cu_to_r = (to); \
526 __cu_from_r = (from); \ 526 __cu_from_r = (from); \
@@ -556,7 +556,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
556 * If some data could not be copied, this function will pad the copied 556 * If some data could not be copied, this function will pad the copied
557 * data to the requested size using zero bytes. 557 * data to the requested size using zero bytes.
558 */ 558 */
559#define __copy_from_user(to,from,n) \ 559#define __copy_from_user(to, from, n) \
560({ \ 560({ \
561 void *__cu_to; \ 561 void *__cu_to; \
562 const void __user *__cu_from; \ 562 const void __user *__cu_from; \
@@ -587,7 +587,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
587 * If some data could not be copied, this function will pad the copied 587 * If some data could not be copied, this function will pad the copied
588 * data to the requested size using zero bytes. 588 * data to the requested size using zero bytes.
589 */ 589 */
590#define copy_from_user(to,from,n) \ 590#define copy_from_user(to, from, n) \
591({ \ 591({ \
592 void *__cu_to; \ 592 void *__cu_to; \
593 const void __user *__cu_from; \ 593 const void __user *__cu_from; \
@@ -605,7 +605,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
605 605
606#define __copy_in_user(to, from, n) __copy_from_user(to, from, n) 606#define __copy_in_user(to, from, n) __copy_from_user(to, from, n)
607 607
608#define copy_in_user(to,from,n) \ 608#define copy_in_user(to, from, n) \
609({ \ 609({ \
610 void __user *__cu_to; \ 610 void __user *__cu_to; \
611 const void __user *__cu_from; \ 611 const void __user *__cu_from; \
diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h
index a0042563838a..3249049e93aa 100644
--- a/include/asm-mips/unaligned.h
+++ b/include/asm-mips/unaligned.h
@@ -3,12 +3,27 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1996, 1999, 2000, 2001, 2003 by Ralf Baechle 6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 */ 7 */
9#ifndef _ASM_UNALIGNED_H 8#ifndef __ASM_GENERIC_UNALIGNED_H
10#define _ASM_UNALIGNED_H 9#define __ASM_GENERIC_UNALIGNED_H
11 10
12#include <asm-generic/unaligned.h> 11#include <linux/compiler.h>
13 12
14#endif /* _ASM_UNALIGNED_H */ 13#define get_unaligned(ptr) \
14({ \
15 struct __packed { \
16 typeof(*(ptr)) __v; \
17 } *__p = (void *) (ptr); \
18 __p->__v; \
19})
20
21#define put_unaligned(val, ptr) \
22do { \
23 struct __packed { \
24 typeof(*(ptr)) __v; \
25 } *__p = (void *) (ptr); \
26 __p->__v = (val); \
27} while(0)
28
29#endif /* __ASM_GENERIC_UNALIGNED_H */
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
index c1dd0b10bc27..f4cff7e4fa8a 100644
--- a/include/asm-mips/vga.h
+++ b/include/asm-mips/vga.h
@@ -13,10 +13,10 @@
13 * access the videoram directly without any black magic. 13 * access the videoram directly without any black magic.
14 */ 14 */
15 15
16#define VGA_MAP_MEM(x,s) (0xb0000000L + (unsigned long)(x)) 16#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x))
17 17
18#define vga_readb(x) (*(x)) 18#define vga_readb(x) (*(x))
19#define vga_writeb(x,y) (*(y) = (x)) 19#define vga_writeb(x, y) (*(y) = (x))
20 20
21#define VT_BUF_HAVE_RW 21#define VT_BUF_HAVE_RW
22/* 22/*
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c0715d0a6b28..d2808edfd4e9 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -3,20 +3,22 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2002, 2004 by Ralf Baechle 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
7 */ 7 */
8#ifndef _ASM_WAR_H 8#ifndef _ASM_WAR_H
9#define _ASM_WAR_H 9#define _ASM_WAR_H
10 10
11#include <war.h>
11 12
12/* 13/*
13 * Another R4600 erratum. Due to the lack of errata information the exact 14 * Another R4600 erratum. Due to the lack of errata information the exact
14 * technical details aren't known. I've experimentally found that disabling 15 * technical details aren't known. I've experimentally found that disabling
15 * interrupts during indexed I-cache flushes seems to be sufficient to deal 16 * interrupts during indexed I-cache flushes seems to be sufficient to deal
16 * with the issue. 17 * with the issue.
17 *
18 * #define R4600_V1_INDEX_ICACHEOP_WAR 1
19 */ 18 */
19#ifndef R4600_V1_INDEX_ICACHEOP_WAR
20#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
21#endif
20 22
21/* 23/*
22 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: 24 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
@@ -43,9 +45,10 @@
43 * nop 45 * nop
44 * nop 46 * nop
45 * cache Hit_Writeback_Invalidate_D 47 * cache Hit_Writeback_Invalidate_D
46 *
47 * #define R4600_V1_HIT_CACHEOP_WAR 1
48 */ 48 */
49#ifndef R4600_V1_HIT_CACHEOP_WAR
50#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
51#endif
49 52
50 53
51/* 54/*
@@ -58,32 +61,11 @@
58 * by a load instruction to an uncached address to empty the response buffer." 61 * by a load instruction to an uncached address to empty the response buffer."
59 * (Revision 2.0 device errata from IDT available on http://www.idt.com/ 62 * (Revision 2.0 device errata from IDT available on http://www.idt.com/
60 * in .pdf format.) 63 * in .pdf format.)
61 *
62 * #define R4600_V2_HIT_CACHEOP_WAR 1
63 */
64
65/*
66 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
67 */
68#ifdef CONFIG_SGI_IP22
69
70#define R4600_V1_INDEX_ICACHEOP_WAR 1
71#define R4600_V1_HIT_CACHEOP_WAR 1
72#define R4600_V2_HIT_CACHEOP_WAR 1
73
74#endif
75
76/*
77 * But the RM200C seems to have been shipped only with V2.0 R4600s
78 */ 64 */
79#ifdef CONFIG_SNI_RM 65#ifndef R4600_V2_HIT_CACHEOP_WAR
80 66#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
81#define R4600_V2_HIT_CACHEOP_WAR 1
82
83#endif 67#endif
84 68
85#ifdef CONFIG_CPU_R5432
86
87/* 69/*
88 * When an interrupt happens on a CP0 register read instruction, CPU may 70 * When an interrupt happens on a CP0 register read instruction, CPU may
89 * lock up or read corrupted values of CP0 registers after it enters 71 * lock up or read corrupted values of CP0 registers after it enters
@@ -93,13 +75,10 @@
93 * first thing in the exception handler, which breaks one of the 75 * first thing in the exception handler, which breaks one of the
94 * pre-conditions for this problem. 76 * pre-conditions for this problem.
95 */ 77 */
96#define R5432_CP0_INTERRUPT_WAR 1 78#ifndef R5432_CP0_INTERRUPT_WAR
97 79#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
98#endif 80#endif
99 81
100#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
101 defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
102
103/* 82/*
104 * Workaround for the Sibyte M3 errata the text of which can be found at 83 * Workaround for the Sibyte M3 errata the text of which can be found at
105 * 84 *
@@ -110,13 +89,15 @@
110 * will just return and take the exception again if the information was 89 * will just return and take the exception again if the information was
111 * found to be inconsistent. 90 * found to be inconsistent.
112 */ 91 */
113#define BCM1250_M3_WAR 1 92#ifndef BCM1250_M3_WAR
93#error Check setting of BCM1250_M3_WAR for your platform
94#endif
114 95
115/* 96/*
116 * This is a DUART workaround related to glitches around register accesses 97 * This is a DUART workaround related to glitches around register accesses
117 */ 98 */
118#define SIBYTE_1956_WAR 1 99#ifndef SIBYTE_1956_WAR
119 100#error Check setting of SIBYTE_1956_WAR for your platform
120#endif 101#endif
121 102
122/* 103/*
@@ -131,9 +112,8 @@
131 * Affects: 112 * Affects:
132 * MIPS 4K RTL revision <3.0, PRID revision <4 113 * MIPS 4K RTL revision <3.0, PRID revision <4
133 */ 114 */
134#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ 115#ifndef MIPS4K_ICACHE_REFILL_WAR
135 defined(CONFIG_MIPS_SEAD) 116#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
136#define MIPS4K_ICACHE_REFILL_WAR 1
137#endif 117#endif
138 118
139/* 119/*
@@ -151,9 +131,8 @@
151 * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 131 * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
152 * MIPS 20Kc RTL revision <4.0, PRID revision <? 132 * MIPS 20Kc RTL revision <4.0, PRID revision <?
153 */ 133 */
154#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ 134#ifndef MIPS_CACHE_SYNC_WAR
155 defined(CONFIG_MIPS_SEAD) 135#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
156#define MIPS_CACHE_SYNC_WAR 1
157#endif 136#endif
158 137
159/* 138/*
@@ -163,16 +142,16 @@
163 * 142 *
164 * Workaround: do two phase flushing for Index_Invalidate_I 143 * Workaround: do two phase flushing for Index_Invalidate_I
165 */ 144 */
166#ifdef CONFIG_CPU_TX49XX 145#ifndef TX49XX_ICACHE_INDEX_INV_WAR
167#define TX49XX_ICACHE_INDEX_INV_WAR 1 146#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
168#endif 147#endif
169 148
170/* 149/*
171 * On the RM9000 there is a problem which makes the CreateDirtyExclusive 150 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
172 * eache operation unusable on SMP systems. 151 * eache operation unusable on SMP systems.
173 */ 152 */
174#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) 153#ifndef RM9000_CDEX_SMP_WAR
175#define RM9000_CDEX_SMP_WAR 1 154#error Check setting of RM9000_CDEX_SMP_WAR for your platform
176#endif 155#endif
177 156
178/* 157/*
@@ -181,69 +160,23 @@
181 * I-cache line worth of instructions being fetched may case spurious 160 * I-cache line worth of instructions being fetched may case spurious
182 * exceptions. 161 * exceptions.
183 */ 162 */
184#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ 163#ifndef ICACHE_REFILLS_WORKAROUND_WAR
185 defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \ 164#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
186 defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
187#define ICACHE_REFILLS_WORKAROUND_WAR 1
188#endif 165#endif
189 166
190/* 167/*
191 * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that 168 * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
192 * may cause ll / sc and lld / scd sequences to execute non-atomically. 169 * may cause ll / sc and lld / scd sequences to execute non-atomically.
193 */ 170 */
194#ifdef CONFIG_SGI_IP27 171#ifndef R10000_LLSC_WAR
195#define R10000_LLSC_WAR 1 172#error Check setting of R10000_LLSC_WAR for your platform
196#endif 173#endif
197 174
198/* 175/*
199 * 34K core erratum: "Problems Executing the TLBR Instruction" 176 * 34K core erratum: "Problems Executing the TLBR Instruction"
200 */ 177 */
201#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
202 defined(CONFIG_PMC_MSP7120_FPGA)
203#define MIPS34K_MISSED_ITLB_WAR 1
204#endif
205
206/*
207 * Workarounds default to off
208 */
209#ifndef ICACHE_REFILLS_WORKAROUND_WAR
210#define ICACHE_REFILLS_WORKAROUND_WAR 0
211#endif
212#ifndef R4600_V1_INDEX_ICACHEOP_WAR
213#define R4600_V1_INDEX_ICACHEOP_WAR 0
214#endif
215#ifndef R4600_V1_HIT_CACHEOP_WAR
216#define R4600_V1_HIT_CACHEOP_WAR 0
217#endif
218#ifndef R4600_V2_HIT_CACHEOP_WAR
219#define R4600_V2_HIT_CACHEOP_WAR 0
220#endif
221#ifndef R5432_CP0_INTERRUPT_WAR
222#define R5432_CP0_INTERRUPT_WAR 0
223#endif
224#ifndef BCM1250_M3_WAR
225#define BCM1250_M3_WAR 0
226#endif
227#ifndef SIBYTE_1956_WAR
228#define SIBYTE_1956_WAR 0
229#endif
230#ifndef MIPS4K_ICACHE_REFILL_WAR
231#define MIPS4K_ICACHE_REFILL_WAR 0
232#endif
233#ifndef MIPS_CACHE_SYNC_WAR
234#define MIPS_CACHE_SYNC_WAR 0
235#endif
236#ifndef TX49XX_ICACHE_INDEX_INV_WAR
237#define TX49XX_ICACHE_INDEX_INV_WAR 0
238#endif
239#ifndef RM9000_CDEX_SMP_WAR
240#define RM9000_CDEX_SMP_WAR 0
241#endif
242#ifndef R10000_LLSC_WAR
243#define R10000_LLSC_WAR 0
244#endif
245#ifndef MIPS34K_MISSED_ITLB_WAR 178#ifndef MIPS34K_MISSED_ITLB_WAR
246#define MIPS34K_MISSED_ITLB_WAR 0 179#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
247#endif 180#endif
248 181
249#endif /* _ASM_WAR_H */ 182#endif /* _ASM_WAR_H */
diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h
index 4a60f27c8817..79bac882a739 100644
--- a/include/asm-mips/xtalk/xtalk.h
+++ b/include/asm-mips/xtalk/xtalk.h
@@ -45,7 +45,7 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
45#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) 45#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0)
46#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) 46#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS)
47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48#define XIO_PACK(p,o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
49 49
50#endif /* !__ASSEMBLY__ */ 50#endif /* !__ASSEMBLY__ */
51 51
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 10:59:47 -0500