aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h229
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h446
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c32
-rw-r--r--arch/arm/mach-omap2/prcm.c2
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h46
-rw-r--r--arch/arm/mach-omap2/prm44xx.h693
6 files changed, 718 insertions, 730 deletions
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index f3bba2180c5a..aa2ee7802631 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -28,229 +28,224 @@
28/* CM1 base address */ 28/* CM1 base address */
29#define OMAP4430_CM1_BASE 0x4a004000 29#define OMAP4430_CM1_BASE 0x4a004000
30 30
31#define OMAP44XX_CM1_REGADDR(module, reg) \ 31#define OMAP44XX_CM1_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) 32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
33 33
34/* CM1 instances */ 34/* CM1 instances */
35#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 35#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
36#define OMAP4430_CM1_CKGEN_MOD 0x0100 36#define OMAP4430_CM1_CKGEN_INST 0x0100
37#define OMAP4430_CM1_MPU_MOD 0x0300 37#define OMAP4430_CM1_MPU_INST 0x0300
38#define OMAP4430_CM1_TESLA_MOD 0x0400 38#define OMAP4430_CM1_TESLA_INST 0x0400
39#define OMAP4430_CM1_ABE_MOD 0x0500 39#define OMAP4430_CM1_ABE_INST 0x0500
40#define OMAP4430_CM1_RESTORE_MOD 0x0e00 40#define OMAP4430_CM1_RESTORE_INST 0x0e00
41#define OMAP4430_CM1_INSTR_MOD 0x0f00 41#define OMAP4430_CM1_INSTR_INST 0x0f00
42 42
43/* CM1 */ 43/* CM1 */
44 44
45/* CM1.OCP_SOCKET_CM1 register offsets */ 45/* CM1.OCP_SOCKET_CM1 register offsets */
46#define OMAP4_REVISION_CM1_OFFSET 0x0000 46#define OMAP4_REVISION_CM1_OFFSET 0x0000
47#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) 47#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
48#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 48#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
49#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) 49#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
50 50
51/* CM1.CKGEN_CM1 register offsets */ 51/* CM1.CKGEN_CM1 register offsets */
52#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 52#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
53#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) 53#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
54#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 54#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
55#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) 55#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
56#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 56#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
57#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) 57#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
58#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 58#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
59#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) 59#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
60#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 60#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
61#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) 61#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
62#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 62#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
63#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) 63#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
64#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 64#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
65#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) 65#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
66#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 66#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
67#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) 67#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
68#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 68#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
69#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) 69#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
70#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 70#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
71#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) 71#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
72#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 72#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
73#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) 73#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
74#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 74#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
75#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) 75#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
76#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 76#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
77#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) 77#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
78#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 78#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
79#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) 79#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
80#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 80#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
81#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) 81#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
82#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 82#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
83#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) 83#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
84#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 84#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
85#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) 85#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
86#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 86#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
87#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) 87#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
88#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 88#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
89#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) 89#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
90#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 90#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
91#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) 91#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
92#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 92#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
93#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) 93#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
94#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 94#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
95#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) 95#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
96#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 96#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
97#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) 97#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
98#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 98#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
99#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) 99#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
100#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 100#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
101#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) 101#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
102#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 102#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
103#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) 103#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
104#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 104#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
105#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) 105#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
106#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 106#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
107#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) 107#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
108#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 108#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
109#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) 109#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
110#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 110#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
111#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) 111#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
112#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 112#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
113#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) 113#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
114#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 114#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
115#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) 115#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
116#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 116#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
117#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) 117#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
118#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 118#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
119#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) 119#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
120#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 120#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
121#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) 121#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
122#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 122#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
123#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) 123#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
124#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 124#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
125#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) 125#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
126#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 126#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
127#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) 127#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
128#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 128#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
129#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) 129#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
130#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 130#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
131#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) 131#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
132#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 132#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
133#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) 133#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
134#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 134#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
135#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) 135#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
136#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 136#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
137#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) 137#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
138#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 138#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
139#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) 139#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
140#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 140#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
141#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) 141#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
142#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 142#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
143#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) 143#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
144#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 144#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
145#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) 145#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
146#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 146#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
147#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) 147#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
148#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 148#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
149#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) 149#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
150#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 150#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
151#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) 151#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
152#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 152#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
153#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) 153#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
154#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 154#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
155#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) 155#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
156#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 156#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
157#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) 157#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
158#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 158#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
159#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) 159#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
160#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 160#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
161#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) 161#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
162 162
163/* CM1.MPU_CM1 register offsets */ 163/* CM1.MPU_CM1 register offsets */
164#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 164#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
165#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) 165#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
166#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 166#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
167#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) 167#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
168#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 168#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
169#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) 169#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
170#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 170#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
171#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) 171#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
172 172
173/* CM1.TESLA_CM1 register offsets */ 173/* CM1.TESLA_CM1 register offsets */
174#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 174#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
175#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) 175#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
176#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 176#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
177#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) 177#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
178#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 178#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
179#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) 179#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
180#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 180#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
181#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) 181#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
182 182
183/* CM1.ABE_CM1 register offsets */ 183/* CM1.ABE_CM1 register offsets */
184#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 184#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
185#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) 185#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
186#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 186#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
187#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) 187#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
188#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 188#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
189#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) 189#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
190#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 190#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
191#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) 191#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
192#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 192#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
193#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) 193#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
194#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 194#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
195#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) 195#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
196#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 196#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
197#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) 197#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
198#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 198#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
199#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) 199#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
200#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 200#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
201#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) 201#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
202#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 202#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
203#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) 203#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
204#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 204#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
205#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) 205#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
206#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 206#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
207#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) 207#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
208#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 208#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
209#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) 209#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
210#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 210#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
211#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) 211#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
212#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 212#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
213#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) 213#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
214 214
215/* CM1.RESTORE_CM1 register offsets */ 215/* CM1.RESTORE_CM1 register offsets */
216#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 216#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
217#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) 217#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
218#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 218#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
219#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) 219#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
220#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 220#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
221#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) 221#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
222#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c 222#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
223#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) 223#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
224#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 224#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
225#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) 225#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
226#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 226#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
227#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) 227#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
228#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 228#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
229#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) 229#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
230#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c 230#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
231#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) 231#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
232#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 232#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
233#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) 233#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
234#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 234#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
235#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) 235#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
236#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 236#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
237#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) 237#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
238#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c 238#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
239#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) 239#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
240#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 240#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
241#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) 241#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
242#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 242#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
243#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) 243#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
244#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 244#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
245#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) 245#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
246#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c 246#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
247#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) 247#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
248#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 248#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
249#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) 249#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
250
251/* Function prototypes */
252extern u32 omap4_cm1_read_mod_reg(s16 module, u16 idx);
253extern void omap4_cm1_write_mod_reg(u32 val, s16 module, u16 idx);
254extern u32 omap4_cm1_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
255 250
256#endif 251#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index 678cff6e0472..89c95220d3e9 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -28,456 +28,456 @@
28/* CM2 base address */ 28/* CM2 base address */
29#define OMAP4430_CM2_BASE 0x4a008000 29#define OMAP4430_CM2_BASE 0x4a008000
30 30
31#define OMAP44XX_CM2_REGADDR(module, reg) \ 31#define OMAP44XX_CM2_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) 32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
33 33
34/* CM2 instances */ 34/* CM2 instances */
35#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 35#define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
36#define OMAP4430_CM2_CKGEN_MOD 0x0100 36#define OMAP4430_CM2_CKGEN_INST 0x0100
37#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 37#define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
38#define OMAP4430_CM2_CORE_MOD 0x0700 38#define OMAP4430_CM2_CORE_INST 0x0700
39#define OMAP4430_CM2_IVAHD_MOD 0x0f00 39#define OMAP4430_CM2_IVAHD_INST 0x0f00
40#define OMAP4430_CM2_CAM_MOD 0x1000 40#define OMAP4430_CM2_CAM_INST 0x1000
41#define OMAP4430_CM2_DSS_MOD 0x1100 41#define OMAP4430_CM2_DSS_INST 0x1100
42#define OMAP4430_CM2_GFX_MOD 0x1200 42#define OMAP4430_CM2_GFX_INST 0x1200
43#define OMAP4430_CM2_L3INIT_MOD 0x1300 43#define OMAP4430_CM2_L3INIT_INST 0x1300
44#define OMAP4430_CM2_L4PER_MOD 0x1400 44#define OMAP4430_CM2_L4PER_INST 0x1400
45#define OMAP4430_CM2_CEFUSE_MOD 0x1600 45#define OMAP4430_CM2_CEFUSE_INST 0x1600
46#define OMAP4430_CM2_RESTORE_MOD 0x1e00 46#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_MOD 0x1f00 47#define OMAP4430_CM2_INSTR_INST 0x1f00
48 48
49 49
50/* CM2 */ 50/* CM2 */
51 51
52/* CM2.OCP_SOCKET_CM2 register offsets */ 52/* CM2.OCP_SOCKET_CM2 register offsets */
53#define OMAP4_REVISION_CM2_OFFSET 0x0000 53#define OMAP4_REVISION_CM2_OFFSET 0x0000
54#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) 54#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
55#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 55#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
56#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) 56#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
57 57
58/* CM2.CKGEN_CM2 register offsets */ 58/* CM2.CKGEN_CM2 register offsets */
59#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 59#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
60#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) 60#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
61#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 61#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
62#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) 62#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
63#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 63#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
64#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) 64#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
65#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 65#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
66#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) 66#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
67#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 67#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
68#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) 68#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
69#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 69#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
70#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) 70#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
71#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c 71#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
72#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) 72#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
73#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 73#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
74#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) 74#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
75#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 75#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
76#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) 76#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
77#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c 77#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
78#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) 78#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
79#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 79#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
80#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) 80#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
81#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 81#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
82#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) 82#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
83#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 83#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
84#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) 84#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
85#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 85#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
86#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) 86#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
87#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 87#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
88#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) 88#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
89#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 89#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
90#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) 90#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
91#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 91#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
92#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) 92#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
93#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 93#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
94#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) 94#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
95#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 95#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
96#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) 96#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
97#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c 97#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
98#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) 98#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
99#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 99#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
100#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) 100#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
101#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 101#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
102#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) 102#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
103#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 103#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
104#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) 104#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
105#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 105#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c
106#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) 106#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
107#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 107#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
108#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) 108#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
109#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 109#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
110#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) 110#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
111#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 111#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
112#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) 112#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
113#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 113#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
114#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) 114#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
115#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 115#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
116#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) 116#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) 118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
119#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 119#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac
120#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) 120#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
121#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 121#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
122#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) 122#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
123#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 123#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
124#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) 124#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
125#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 125#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
126#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) 126#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
127#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 127#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
128#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) 128#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
129#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc 129#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
130#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) 130#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
131#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 131#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
132#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) 132#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
133#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 133#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
134#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) 134#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
135#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 135#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
136#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) 136#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
137 137
138/* CM2.ALWAYS_ON_CM2 register offsets */ 138/* CM2.ALWAYS_ON_CM2 register offsets */
139#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 139#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
140#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) 140#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
141#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 141#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
142#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) 142#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
143#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 143#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
144#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) 144#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
145#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 145#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
146#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) 146#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
147#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 147#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
148#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) 148#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
149#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 149#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
150#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) 150#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
151 151
152/* CM2.CORE_CM2 register offsets */ 152/* CM2.CORE_CM2 register offsets */
153#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 153#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
154#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) 154#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
155#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 155#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
156#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) 156#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
157#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 157#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
158#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) 158#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
159#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 159#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
160#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) 160#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
161#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 161#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
162#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) 162#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
163#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 163#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
164#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) 164#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
165#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 165#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
166#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) 166#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
167#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 167#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
168#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) 168#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
169#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 169#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
170#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) 170#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
171#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 171#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
172#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) 172#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
173#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 173#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
174#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) 174#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
175#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 175#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
176#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) 176#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
177#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 177#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
178#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) 178#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
179#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 179#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
180#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) 180#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
181#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 181#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
182#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) 182#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
183#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 183#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
184#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) 184#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
185#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 185#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
186#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) 186#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
187#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 187#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
188#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) 188#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
189#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 189#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
190#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) 190#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
191#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 191#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
192#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) 192#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
193#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 193#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
194#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) 194#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
195#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 195#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
196#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) 196#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
197#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 197#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
198#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) 198#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
199#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 199#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
200#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) 200#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
201#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 201#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
202#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) 202#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
203#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 203#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
204#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) 204#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
205#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 205#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
206#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) 206#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
207#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 207#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
208#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) 208#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
209#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 209#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
210#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) 210#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
211#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 211#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528
212#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) 212#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
213#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 213#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
214#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) 214#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
215#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 215#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
216#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) 216#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
217#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 217#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
218#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) 218#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
219#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 219#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
220#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) 220#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
221#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 221#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
222#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) 222#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
223#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 223#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
224#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) 224#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
225#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 225#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
226#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) 226#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
227#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 227#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
228#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) 228#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
229#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 229#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
230#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) 230#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
231#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 231#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
232#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) 232#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
233#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 233#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
234#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) 234#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
235 235
236/* CM2.IVAHD_CM2 register offsets */ 236/* CM2.IVAHD_CM2 register offsets */
237#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 237#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
238#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) 238#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
239#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 239#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
240#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) 240#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
241#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 241#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
242#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) 242#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
243#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 243#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
244#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) 244#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
245#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 245#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
246#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) 246#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
247 247
248/* CM2.CAM_CM2 register offsets */ 248/* CM2.CAM_CM2 register offsets */
249#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 249#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
250#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) 250#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
251#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 251#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
252#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) 252#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
253#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 253#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
254#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) 254#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
255#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 255#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
256#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) 256#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
257#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 257#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
258#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) 258#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
259 259
260/* CM2.DSS_CM2 register offsets */ 260/* CM2.DSS_CM2 register offsets */
261#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 261#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
262#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) 262#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
263#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 263#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
264#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) 264#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
265#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 265#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
266#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) 266#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
267#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 267#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
268#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) 268#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
269#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 269#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
270#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) 270#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
271 271
272/* CM2.GFX_CM2 register offsets */ 272/* CM2.GFX_CM2 register offsets */
273#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 273#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
274#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) 274#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
275#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 275#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
276#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) 276#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
277#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 277#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
278#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) 278#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
279#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 279#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
280#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) 280#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
281 281
282/* CM2.L3INIT_CM2 register offsets */ 282/* CM2.L3INIT_CM2 register offsets */
283#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 283#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
284#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) 284#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
285#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 285#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
286#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) 286#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
287#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 287#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
288#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) 288#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
289#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 289#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
290#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) 290#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
291#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 291#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
292#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) 292#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
293#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 293#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
294#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) 294#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
295#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 295#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
296#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) 296#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
297#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 297#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
298#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) 298#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
299#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 299#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
300#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) 300#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
301#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 301#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
302#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) 302#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
303#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 303#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
304#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) 304#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
305#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 305#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
306#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) 306#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
307#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 307#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
308#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) 308#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
309#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 309#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
310#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) 310#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
311#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 311#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
312#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) 312#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
313#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 313#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
314#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) 314#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
315#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 315#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
316#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) 316#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
317#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 317#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
318#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) 318#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
319#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 319#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
320#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) 320#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
321#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 321#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
322#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) 322#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
323 323
324/* CM2.L4PER_CM2 register offsets */ 324/* CM2.L4PER_CM2 register offsets */
325#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 325#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
326#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) 326#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
327#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 327#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
328#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) 328#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
329#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 329#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
330#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) 330#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
331#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 331#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
332#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) 332#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
333#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 333#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
334#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) 334#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
335#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 335#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
336#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) 336#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
337#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 337#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
338#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) 338#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
339#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 339#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
340#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) 340#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
341#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 341#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
342#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) 342#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
343#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 343#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
344#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) 344#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
345#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 345#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
346#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) 346#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
347#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 347#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
348#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) 348#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
349#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 349#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
350#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) 350#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
351#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 351#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
352#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) 352#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
353#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 353#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
354#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) 354#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
355#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 355#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
356#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) 356#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
357#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 357#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
358#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) 358#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
359#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 359#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
360#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) 360#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
361#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 361#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
362#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) 362#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
363#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 363#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
364#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) 364#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
365#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 365#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
366#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) 366#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
367#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 367#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
368#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) 368#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
369#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 369#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
370#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) 370#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
371#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 371#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
372#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) 372#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
373#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 373#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
374#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) 374#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
375#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 375#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
376#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) 376#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
377#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 377#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
378#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) 378#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
379#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 379#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
380#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) 380#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
381#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 381#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
382#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) 382#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
383#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 383#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
384#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) 384#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
385#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 385#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
386#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) 386#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
387#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 387#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
388#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) 388#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
389#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 389#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
390#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) 390#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
391#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 391#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
392#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) 392#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
393#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 393#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
394#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) 394#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
395#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 395#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
396#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) 396#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
397#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 397#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
398#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) 398#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
399#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 399#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
400#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) 400#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
401#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 401#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
402#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) 402#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
403#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 403#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
404#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) 404#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
405#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 405#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
406#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) 406#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
407#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 407#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
408#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) 408#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
409#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 409#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
410#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) 410#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
411#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 411#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
412#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) 412#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
413#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 413#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
414#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) 414#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
415#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 415#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
416#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) 416#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
417#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 417#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
418#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) 418#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
419#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 419#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
420#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) 420#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
421#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 421#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
422#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) 422#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
423#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 423#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
424#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) 424#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
425#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 425#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
426#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) 426#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
427 427
428/* CM2.CEFUSE_CM2 register offsets */ 428/* CM2.CEFUSE_CM2 register offsets */
429#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 429#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
430#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) 430#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
431#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 431#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
432#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) 432#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
433 433
434/* CM2.RESTORE_CM2 register offsets */ 434/* CM2.RESTORE_CM2 register offsets */
435#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 435#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
436#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) 436#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
437#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 437#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
438#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) 438#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
439#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 439#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
440#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) 440#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
441#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c 441#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
442#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) 442#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
443#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 443#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
444#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) 444#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
445#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 445#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
446#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) 446#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
447#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 447#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
448#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) 448#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
449#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c 449#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
450#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) 450#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
451#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 451#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
452#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) 452#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
453#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 453#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
454#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) 454#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
455#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 455#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
456#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) 456#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
457#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c 457#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
458#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) 458#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
459#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 459#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
460#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) 460#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
461#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 461#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
462#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) 462#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
463#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 463#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
464#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) 464#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
465#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c 465#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
466#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) 466#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
467#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 467#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
468#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) 468#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
469#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 469#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
470#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) 470#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
471#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 471#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
472#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) 472#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
473#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c 473#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
474#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) 474#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
475#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 475#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
476#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) 476#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
477#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 477#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
478#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) 478#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
479#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 479#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
480#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) 480#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
481#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c 481#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
482#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) 482#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
483#endif 483#endif
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index d078c8825d7c..cf6adfcf035f 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -34,7 +34,7 @@
34/* core_44xx_pwrdm: CORE power domain */ 34/* core_44xx_pwrdm: CORE power domain */
35static struct powerdomain core_44xx_pwrdm = { 35static struct powerdomain core_44xx_pwrdm = {
36 .name = "core_pwrdm", 36 .name = "core_pwrdm",
37 .prcm_offs = OMAP4430_PRM_CORE_MOD, 37 .prcm_offs = OMAP4430_PRM_CORE_INST,
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
39 .pwrsts = PWRSTS_RET_ON, 39 .pwrsts = PWRSTS_RET_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF_RET, 40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -59,7 +59,7 @@ static struct powerdomain core_44xx_pwrdm = {
59/* gfx_44xx_pwrdm: 3D accelerator power domain */ 59/* gfx_44xx_pwrdm: 3D accelerator power domain */
60static struct powerdomain gfx_44xx_pwrdm = { 60static struct powerdomain gfx_44xx_pwrdm = {
61 .name = "gfx_pwrdm", 61 .name = "gfx_pwrdm",
62 .prcm_offs = OMAP4430_PRM_GFX_MOD, 62 .prcm_offs = OMAP4430_PRM_GFX_INST,
63 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 63 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
64 .pwrsts = PWRSTS_OFF_ON, 64 .pwrsts = PWRSTS_OFF_ON,
65 .banks = 1, 65 .banks = 1,
@@ -75,7 +75,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
75/* abe_44xx_pwrdm: Audio back end power domain */ 75/* abe_44xx_pwrdm: Audio back end power domain */
76static struct powerdomain abe_44xx_pwrdm = { 76static struct powerdomain abe_44xx_pwrdm = {
77 .name = "abe_pwrdm", 77 .name = "abe_pwrdm",
78 .prcm_offs = OMAP4430_PRM_ABE_MOD, 78 .prcm_offs = OMAP4430_PRM_ABE_INST,
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
80 .pwrsts = PWRSTS_OFF_RET_ON, 80 .pwrsts = PWRSTS_OFF_RET_ON,
81 .pwrsts_logic_ret = PWRDM_POWER_OFF, 81 .pwrsts_logic_ret = PWRDM_POWER_OFF,
@@ -94,7 +94,7 @@ static struct powerdomain abe_44xx_pwrdm = {
94/* dss_44xx_pwrdm: Display subsystem power domain */ 94/* dss_44xx_pwrdm: Display subsystem power domain */
95static struct powerdomain dss_44xx_pwrdm = { 95static struct powerdomain dss_44xx_pwrdm = {
96 .name = "dss_pwrdm", 96 .name = "dss_pwrdm",
97 .prcm_offs = OMAP4430_PRM_DSS_MOD, 97 .prcm_offs = OMAP4430_PRM_DSS_INST,
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
99 .pwrsts = PWRSTS_OFF_RET_ON, 99 .pwrsts = PWRSTS_OFF_RET_ON,
100 .pwrsts_logic_ret = PWRSTS_OFF, 100 .pwrsts_logic_ret = PWRSTS_OFF,
@@ -111,7 +111,7 @@ static struct powerdomain dss_44xx_pwrdm = {
111/* tesla_44xx_pwrdm: Tesla processor power domain */ 111/* tesla_44xx_pwrdm: Tesla processor power domain */
112static struct powerdomain tesla_44xx_pwrdm = { 112static struct powerdomain tesla_44xx_pwrdm = {
113 .name = "tesla_pwrdm", 113 .name = "tesla_pwrdm",
114 .prcm_offs = OMAP4430_PRM_TESLA_MOD, 114 .prcm_offs = OMAP4430_PRM_TESLA_INST,
115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
116 .pwrsts = PWRSTS_OFF_RET_ON, 116 .pwrsts = PWRSTS_OFF_RET_ON,
117 .pwrsts_logic_ret = PWRSTS_OFF_RET, 117 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -132,7 +132,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
132/* wkup_44xx_pwrdm: Wake-up power domain */ 132/* wkup_44xx_pwrdm: Wake-up power domain */
133static struct powerdomain wkup_44xx_pwrdm = { 133static struct powerdomain wkup_44xx_pwrdm = {
134 .name = "wkup_pwrdm", 134 .name = "wkup_pwrdm",
135 .prcm_offs = OMAP4430_PRM_WKUP_MOD, 135 .prcm_offs = OMAP4430_PRM_WKUP_INST,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
137 .pwrsts = PWRSTS_ON, 137 .pwrsts = PWRSTS_ON,
138 .banks = 1, 138 .banks = 1,
@@ -147,7 +147,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
147/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 147/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
148static struct powerdomain cpu0_44xx_pwrdm = { 148static struct powerdomain cpu0_44xx_pwrdm = {
149 .name = "cpu0_pwrdm", 149 .name = "cpu0_pwrdm",
150 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, 150 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
152 .pwrsts = PWRSTS_OFF_RET_ON, 152 .pwrsts = PWRSTS_OFF_RET_ON,
153 .pwrsts_logic_ret = PWRSTS_OFF_RET, 153 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -163,7 +163,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
163/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 163/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
164static struct powerdomain cpu1_44xx_pwrdm = { 164static struct powerdomain cpu1_44xx_pwrdm = {
165 .name = "cpu1_pwrdm", 165 .name = "cpu1_pwrdm",
166 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, 166 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
168 .pwrsts = PWRSTS_OFF_RET_ON, 168 .pwrsts = PWRSTS_OFF_RET_ON,
169 .pwrsts_logic_ret = PWRSTS_OFF_RET, 169 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
179/* emu_44xx_pwrdm: Emulation power domain */ 179/* emu_44xx_pwrdm: Emulation power domain */
180static struct powerdomain emu_44xx_pwrdm = { 180static struct powerdomain emu_44xx_pwrdm = {
181 .name = "emu_pwrdm", 181 .name = "emu_pwrdm",
182 .prcm_offs = OMAP4430_PRM_EMU_MOD, 182 .prcm_offs = OMAP4430_PRM_EMU_INST,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
184 .pwrsts = PWRSTS_OFF_ON, 184 .pwrsts = PWRSTS_OFF_ON,
185 .banks = 1, 185 .banks = 1,
@@ -194,7 +194,7 @@ static struct powerdomain emu_44xx_pwrdm = {
194/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 194/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
195static struct powerdomain mpu_44xx_pwrdm = { 195static struct powerdomain mpu_44xx_pwrdm = {
196 .name = "mpu_pwrdm", 196 .name = "mpu_pwrdm",
197 .prcm_offs = OMAP4430_PRM_MPU_MOD, 197 .prcm_offs = OMAP4430_PRM_MPU_INST,
198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
199 .pwrsts = PWRSTS_OFF_RET_ON, 199 .pwrsts = PWRSTS_OFF_RET_ON,
200 .pwrsts_logic_ret = PWRSTS_OFF_RET, 200 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -214,7 +214,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
214/* ivahd_44xx_pwrdm: IVA-HD power domain */ 214/* ivahd_44xx_pwrdm: IVA-HD power domain */
215static struct powerdomain ivahd_44xx_pwrdm = { 215static struct powerdomain ivahd_44xx_pwrdm = {
216 .name = "ivahd_pwrdm", 216 .name = "ivahd_pwrdm",
217 .prcm_offs = OMAP4430_PRM_IVAHD_MOD, 217 .prcm_offs = OMAP4430_PRM_IVAHD_INST,
218 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 218 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
219 .pwrsts = PWRSTS_OFF_RET_ON, 219 .pwrsts = PWRSTS_OFF_RET_ON,
220 .pwrsts_logic_ret = PWRDM_POWER_OFF, 220 .pwrsts_logic_ret = PWRDM_POWER_OFF,
@@ -237,7 +237,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
237/* cam_44xx_pwrdm: Camera subsystem power domain */ 237/* cam_44xx_pwrdm: Camera subsystem power domain */
238static struct powerdomain cam_44xx_pwrdm = { 238static struct powerdomain cam_44xx_pwrdm = {
239 .name = "cam_pwrdm", 239 .name = "cam_pwrdm",
240 .prcm_offs = OMAP4430_PRM_CAM_MOD, 240 .prcm_offs = OMAP4430_PRM_CAM_INST,
241 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 241 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
242 .pwrsts = PWRSTS_OFF_ON, 242 .pwrsts = PWRSTS_OFF_ON,
243 .banks = 1, 243 .banks = 1,
@@ -253,7 +253,7 @@ static struct powerdomain cam_44xx_pwrdm = {
253/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ 253/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
254static struct powerdomain l3init_44xx_pwrdm = { 254static struct powerdomain l3init_44xx_pwrdm = {
255 .name = "l3init_pwrdm", 255 .name = "l3init_pwrdm",
256 .prcm_offs = OMAP4430_PRM_L3INIT_MOD, 256 .prcm_offs = OMAP4430_PRM_L3INIT_INST,
257 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 257 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
258 .pwrsts = PWRSTS_OFF_RET_ON, 258 .pwrsts = PWRSTS_OFF_RET_ON,
259 .pwrsts_logic_ret = PWRSTS_OFF_RET, 259 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -270,7 +270,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
270/* l4per_44xx_pwrdm: Target peripherals power domain */ 270/* l4per_44xx_pwrdm: Target peripherals power domain */
271static struct powerdomain l4per_44xx_pwrdm = { 271static struct powerdomain l4per_44xx_pwrdm = {
272 .name = "l4per_pwrdm", 272 .name = "l4per_pwrdm",
273 .prcm_offs = OMAP4430_PRM_L4PER_MOD, 273 .prcm_offs = OMAP4430_PRM_L4PER_INST,
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
275 .pwrsts = PWRSTS_OFF_RET_ON, 275 .pwrsts = PWRSTS_OFF_RET_ON,
276 .pwrsts_logic_ret = PWRSTS_OFF_RET, 276 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -292,7 +292,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
292 */ 292 */
293static struct powerdomain always_on_core_44xx_pwrdm = { 293static struct powerdomain always_on_core_44xx_pwrdm = {
294 .name = "always_on_core_pwrdm", 294 .name = "always_on_core_pwrdm",
295 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, 295 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
296 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 296 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
297 .pwrsts = PWRSTS_ON, 297 .pwrsts = PWRSTS_ON,
298}; 298};
@@ -300,7 +300,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
300/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ 300/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
301static struct powerdomain cefuse_44xx_pwrdm = { 301static struct powerdomain cefuse_44xx_pwrdm = {
302 .name = "cefuse_pwrdm", 302 .name = "cefuse_pwrdm",
303 .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, 303 .prcm_offs = OMAP4430_PRM_CEFUSE_INST,
304 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 304 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
305 .pwrsts = PWRSTS_OFF_ON, 305 .pwrsts = PWRSTS_OFF_ON,
306}; 306};
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index df55fdfdeae0..aac8070fadcd 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -146,7 +146,7 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
146 prcm_offs = OMAP3430_GR_MOD; 146 prcm_offs = OMAP3430_GR_MOD;
147 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); 147 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
148 } else if (cpu_is_omap44xx()) 148 } else if (cpu_is_omap44xx())
149 prcm_offs = OMAP4430_PRM_DEVICE_MOD; 149 prcm_offs = OMAP4430_PRM_DEVICE_INST;
150 else 150 else
151 WARN_ON(1); 151 WARN_ON(1);
152 152
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 5b828dfe9505..80e00c16d36f 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -27,15 +27,15 @@
27 27
28#define OMAP4430_PRCM_MPU_BASE 0x48243000 28#define OMAP4430_PRCM_MPU_BASE 0x48243000
29 29
30#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \ 30#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg)) 31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
32 32
33/* PRCM_MPU instances */ 33/* PRCM_MPU instances */
34 34
35#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000 35#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
36#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 36#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
37#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 37#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
38#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 39
40/* 40/*
41 * PRCM_MPU 41 * PRCM_MPU
@@ -48,44 +48,44 @@
48 48
49/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ 49/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
50#define OMAP4_REVISION_PRCM_OFFSET 0x0000 50#define OMAP4_REVISION_PRCM_OFFSET 0x0000
51#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000) 51#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
52 52
53/* PRCM_MPU.DEVICE_PRM register offsets */ 53/* PRCM_MPU.DEVICE_PRM register offsets */
54#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 54#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
55#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) 55#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
56#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 56#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
57#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) 57#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
58 58
59/* PRCM_MPU.CPU0 register offsets */ 59/* PRCM_MPU.CPU0 register offsets */
60#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 60#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
61#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000) 61#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
62#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 62#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
63#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004) 63#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
64#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 64#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
65#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008) 65#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
66#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c 66#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
67#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c) 67#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
68#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 68#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
69#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010) 69#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
70#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 70#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
71#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014) 71#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
72#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 72#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
73#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018) 73#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
74 74
75/* PRCM_MPU.CPU1 register offsets */ 75/* PRCM_MPU.CPU1 register offsets */
76#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 76#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
77#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000) 77#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
78#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 78#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
79#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004) 79#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
80#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 80#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
81#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008) 81#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
82#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c 82#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
83#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c) 83#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
84#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 84#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
85#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010) 85#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
86#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 86#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
87#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014) 87#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
88#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 88#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
89#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018) 89#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
90 90
91#endif 91#endif
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 4343881b5ed5..0d444a5c939c 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -29,31 +29,31 @@
29 29
30#define OMAP4430_PRM_BASE 0x4a306000 30#define OMAP4430_PRM_BASE 0x4a306000
31 31
32#define OMAP44XX_PRM_REGADDR(module, reg) \ 32#define OMAP44XX_PRM_REGADDR(inst, reg) \
33 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 33 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
34 34
35 35
36/* PRM instances */ 36/* PRM instances */
37#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 37#define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
38#define OMAP4430_PRM_CKGEN_MOD 0x0100 38#define OMAP4430_PRM_CKGEN_INST 0x0100
39#define OMAP4430_PRM_MPU_MOD 0x0300 39#define OMAP4430_PRM_MPU_INST 0x0300
40#define OMAP4430_PRM_TESLA_MOD 0x0400 40#define OMAP4430_PRM_TESLA_INST 0x0400
41#define OMAP4430_PRM_ABE_MOD 0x0500 41#define OMAP4430_PRM_ABE_INST 0x0500
42#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 42#define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
43#define OMAP4430_PRM_CORE_MOD 0x0700 43#define OMAP4430_PRM_CORE_INST 0x0700
44#define OMAP4430_PRM_IVAHD_MOD 0x0f00 44#define OMAP4430_PRM_IVAHD_INST 0x0f00
45#define OMAP4430_PRM_CAM_MOD 0x1000 45#define OMAP4430_PRM_CAM_INST 0x1000
46#define OMAP4430_PRM_DSS_MOD 0x1100 46#define OMAP4430_PRM_DSS_INST 0x1100
47#define OMAP4430_PRM_GFX_MOD 0x1200 47#define OMAP4430_PRM_GFX_INST 0x1200
48#define OMAP4430_PRM_L3INIT_MOD 0x1300 48#define OMAP4430_PRM_L3INIT_INST 0x1300
49#define OMAP4430_PRM_L4PER_MOD 0x1400 49#define OMAP4430_PRM_L4PER_INST 0x1400
50#define OMAP4430_PRM_CEFUSE_MOD 0x1600 50#define OMAP4430_PRM_CEFUSE_INST 0x1600
51#define OMAP4430_PRM_WKUP_MOD 0x1700 51#define OMAP4430_PRM_WKUP_INST 0x1700
52#define OMAP4430_PRM_WKUP_CM_MOD 0x1800 52#define OMAP4430_PRM_WKUP_CM_INST 0x1800
53#define OMAP4430_PRM_EMU_MOD 0x1900 53#define OMAP4430_PRM_EMU_INST 0x1900
54#define OMAP4430_PRM_EMU_CM_MOD 0x1a00 54#define OMAP4430_PRM_EMU_CM_INST 0x1a00
55#define OMAP4430_PRM_DEVICE_MOD 0x1b00 55#define OMAP4430_PRM_DEVICE_INST 0x1b00
56#define OMAP4430_PRM_INSTR_MOD 0x1f00 56#define OMAP4430_PRM_INSTR_INST 0x1f00
57 57
58 58
59/* OMAP4 specific register offsets */ 59/* OMAP4 specific register offsets */
@@ -68,689 +68,682 @@
68 68
69/* PRM.OCP_SOCKET_PRM register offsets */ 69/* PRM.OCP_SOCKET_PRM register offsets */
70#define OMAP4_REVISION_PRM_OFFSET 0x0000 70#define OMAP4_REVISION_PRM_OFFSET 0x0000
71#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) 71#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
72#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 72#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010
73#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) 73#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
74#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 74#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
75#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) 75#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
76#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 76#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018
77#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) 77#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
78#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 78#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
79#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) 79#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
80#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 80#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020
81#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) 81#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
82#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 82#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028
83#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) 83#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
84#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 84#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030
85#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) 85#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
86#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 86#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
87#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) 87#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
88#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 88#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
89#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) 89#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
90 90
91/* PRM.CKGEN_PRM register offsets */ 91/* PRM.CKGEN_PRM register offsets */
92#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 92#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
93#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) 93#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
94#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 94#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
95#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) 95#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
96#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c 96#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
97#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) 97#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
98#define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 98#define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010
99#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) 99#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
100 100
101/* PRM.MPU_PRM register offsets */ 101/* PRM.MPU_PRM register offsets */
102#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 102#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000
103#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) 103#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
104#define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 104#define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004
105#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) 105#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
106#define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 106#define OMAP4_RM_MPU_RSTST_OFFSET 0x0014
107#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) 107#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
108#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 108#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
109#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) 109#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
110 110
111/* PRM.TESLA_PRM register offsets */ 111/* PRM.TESLA_PRM register offsets */
112#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 112#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000
113#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) 113#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
114#define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 114#define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004
115#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) 115#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
116#define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 116#define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010
117#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) 117#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
118#define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 118#define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014
119#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) 119#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
120#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 120#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024
121#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) 121#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
122 122
123/* PRM.ABE_PRM register offsets */ 123/* PRM.ABE_PRM register offsets */
124#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 124#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000
125#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) 125#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
126#define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 126#define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004
127#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) 127#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
128#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 128#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
129#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) 129#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
130#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 130#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030
131#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) 131#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
132#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 132#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034
133#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) 133#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
134#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 134#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
135#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) 135#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
136#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 136#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
137#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) 137#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
138#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 138#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
139#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) 139#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
140#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 140#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
141#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) 141#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
142#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 142#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
143#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) 143#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
144#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 144#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
145#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) 145#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
146#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 146#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
147#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) 147#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
148#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 148#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
149#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) 149#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
150#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 150#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
151#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) 151#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
152#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 152#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
153#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) 153#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
154#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 154#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060
155#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) 155#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
156#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 156#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064
157#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) 157#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
158#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 158#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
159#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) 159#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
160#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 160#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
161#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) 161#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
162#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 162#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
163#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) 163#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
164#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 164#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
165#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) 165#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
166#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 166#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
167#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) 167#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
168#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 168#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
169#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) 169#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
170#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 170#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
171#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) 171#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
172#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 172#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
173#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) 173#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
174#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 174#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088
175#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) 175#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
176#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c 176#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c
177#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) 177#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
178 178
179/* PRM.ALWAYS_ON_PRM register offsets */ 179/* PRM.ALWAYS_ON_PRM register offsets */
180#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 180#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024
181#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) 181#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
182#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 182#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028
183#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) 183#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
184#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c 184#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c
185#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) 185#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
186#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 186#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030
187#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) 187#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
188#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 188#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034
189#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) 189#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
190#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 190#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038
191#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) 191#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
192#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c 192#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c
193#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) 193#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
194 194
195/* PRM.CORE_PRM register offsets */ 195/* PRM.CORE_PRM register offsets */
196#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 196#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000
197#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) 197#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
198#define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 198#define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004
199#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) 199#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
200#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 200#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024
201#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) 201#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
202#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 202#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124
203#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) 203#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
204#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c 204#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c
205#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) 205#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
206#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 206#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134
207#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) 207#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
208#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 208#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210
209#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) 209#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
210#define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 210#define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214
211#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) 211#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
212#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 212#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224
213#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) 213#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
214#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 214#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324
215#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) 215#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
216#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 216#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424
217#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) 217#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
218#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c 218#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c
219#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) 219#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
220#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 220#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434
221#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) 221#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
222#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c 222#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c
223#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) 223#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
224#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 224#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444
225#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) 225#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
226#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 226#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454
227#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) 227#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
228#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c 228#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c
229#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) 229#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
230#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 230#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464
231#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) 231#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
232#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 232#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
233#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) 233#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
234#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c 234#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c
235#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) 235#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
236#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 236#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
237#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) 237#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
238#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 238#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
239#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) 239#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
240#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c 240#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c
241#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) 241#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
242#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 242#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
243#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) 243#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
244#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 244#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
245#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) 245#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
246#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 246#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724
247#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) 247#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
248#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 248#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
249#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) 249#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
250#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 250#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744
251#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) 251#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
252 252
253/* PRM.IVAHD_PRM register offsets */ 253/* PRM.IVAHD_PRM register offsets */
254#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 254#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000
255#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) 255#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
256#define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 256#define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004
257#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) 257#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
258#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 258#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010
259#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) 259#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
260#define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 260#define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014
261#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) 261#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
262#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 262#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024
263#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) 263#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
264#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c 264#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c
265#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) 265#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
266 266
267/* PRM.CAM_PRM register offsets */ 267/* PRM.CAM_PRM register offsets */
268#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 268#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000
269#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) 269#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
270#define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 270#define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004
271#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) 271#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
272#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 272#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
273#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) 273#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
274#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 274#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
275#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) 275#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
276 276
277/* PRM.DSS_PRM register offsets */ 277/* PRM.DSS_PRM register offsets */
278#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 278#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000
279#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) 279#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
280#define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 280#define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004
281#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) 281#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
282#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 282#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020
283#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) 283#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
284#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 284#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
285#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) 285#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
286#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c 286#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c
287#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) 287#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
288 288
289/* PRM.GFX_PRM register offsets */ 289/* PRM.GFX_PRM register offsets */
290#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 290#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000
291#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) 291#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
292#define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 292#define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004
293#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) 293#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
294#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 294#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024
295#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) 295#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
296 296
297/* PRM.L3INIT_PRM register offsets */ 297/* PRM.L3INIT_PRM register offsets */
298#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 298#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
299#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) 299#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
300#define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 300#define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004
301#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) 301#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
302#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 302#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
303#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) 303#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
304#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 304#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
305#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) 305#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
306#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 306#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
307#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) 307#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
308#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 308#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
309#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) 309#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
310#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 310#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
311#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) 311#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
312#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 312#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
313#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) 313#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
314#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 314#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040
315#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) 315#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
316#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 316#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044
317#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) 317#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
318#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 318#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058
319#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) 319#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
320#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c 320#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c
321#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) 321#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
322#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 322#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060
323#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) 323#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
324#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 324#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064
325#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) 325#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
326#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 326#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068
327#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) 327#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
328#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c 328#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c
329#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) 329#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
330#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c 330#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c
331#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) 331#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
332#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 332#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084
333#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) 333#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
334#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 334#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
335#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) 335#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
336#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 336#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
337#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) 337#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
338#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 338#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094
339#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) 339#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
340#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 340#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098
341#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) 341#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
342#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c 342#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c
343#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) 343#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
344#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac 344#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac
345#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) 345#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
346#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 346#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0
347#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) 347#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
348#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 348#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4
349#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) 349#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
350#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 350#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8
351#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) 351#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
352#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc 352#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc
353#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) 353#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
354#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 354#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0
355#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) 355#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
356#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 356#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4
357#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) 357#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
358#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 358#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4
359#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) 359#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
360 360
361/* PRM.L4PER_PRM register offsets */ 361/* PRM.L4PER_PRM register offsets */
362#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 362#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
363#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) 363#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
364#define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 364#define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004
365#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) 365#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
366#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 366#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024
367#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) 367#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
368#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 368#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028
369#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) 369#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
370#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c 370#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c
371#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) 371#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
372#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 372#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030
373#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) 373#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
374#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 374#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034
375#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) 375#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
376#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 376#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038
377#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) 377#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
378#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c 378#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c
379#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) 379#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
380#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 380#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040
381#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) 381#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
382#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 382#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044
383#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) 383#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
384#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 384#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048
385#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) 385#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
386#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c 386#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c
387#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) 387#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
388#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 388#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050
389#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) 389#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
390#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 390#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054
391#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) 391#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
392#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 392#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
393#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) 393#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
394#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 394#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
395#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) 395#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
396#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 396#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
397#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) 397#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
398#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 398#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
399#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) 399#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
400#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 400#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
401#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) 401#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
402#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 402#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
403#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) 403#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
404#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 404#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
405#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) 405#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
406#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 406#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
407#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) 407#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
408#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 408#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
409#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) 409#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
410#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 410#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
411#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) 411#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
412#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 412#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
413#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) 413#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
414#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 414#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
415#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) 415#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
416#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 416#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090
417#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) 417#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
418#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 418#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094
419#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) 419#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
420#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 420#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098
421#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) 421#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
422#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c 422#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c
423#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) 423#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
424#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 424#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
425#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) 425#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
426#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 426#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
427#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) 427#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
428#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 428#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
429#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) 429#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
430#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 430#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
431#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) 431#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
432#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 432#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
433#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) 433#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
434#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 434#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
435#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) 435#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
436#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 436#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
437#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) 437#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
438#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 438#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
439#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) 439#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
440#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 440#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0
441#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) 441#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
442#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 442#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0
443#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) 443#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
444#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 444#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4
445#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) 445#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
446#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 446#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8
447#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) 447#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
448#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc 448#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc
449#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) 449#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
450#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 450#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0
451#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) 451#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
452#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 452#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4
453#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) 453#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
454#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec 454#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec
455#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) 455#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
456#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 456#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
457#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) 457#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
458#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 458#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
459#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) 459#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
460#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 460#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
461#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) 461#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
462#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 462#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
463#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) 463#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
464#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 464#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
465#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) 465#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
466#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 466#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
467#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) 467#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
468#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 468#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
469#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) 469#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
470#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 470#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
471#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) 471#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
472#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 472#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120
473#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) 473#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
474#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 474#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124
475#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) 475#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
476#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 476#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128
477#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) 477#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
478#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c 478#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c
479#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) 479#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
480#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 480#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134
481#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) 481#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
482#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 482#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138
483#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) 483#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
484#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c 484#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c
485#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) 485#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
486#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 486#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
487#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) 487#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
488#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 488#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
489#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) 489#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
490#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 490#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
491#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) 491#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
492#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 492#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
493#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) 493#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
494#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 494#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
495#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) 495#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
496#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 496#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
497#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) 497#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
498#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 498#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
499#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) 499#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
500#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 500#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
501#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) 501#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
502#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 502#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160
503#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) 503#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
504#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 504#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164
505#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) 505#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
506#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 506#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168
507#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) 507#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
508#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c 508#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c
509#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) 509#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
510#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 510#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
511#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) 511#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
512#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 512#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
513#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) 513#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
514#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 514#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
515#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) 515#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
516#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc 516#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc
517#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) 517#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
518#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 518#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
519#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) 519#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
520#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 520#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
521#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) 521#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
522#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc 522#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc
523#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) 523#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
524 524
525/* PRM.CEFUSE_PRM register offsets */ 525/* PRM.CEFUSE_PRM register offsets */
526#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 526#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
527#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) 527#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
528#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 528#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004
529#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) 529#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
530#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 530#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024
531#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) 531#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
532 532
533/* PRM.WKUP_PRM register offsets */ 533/* PRM.WKUP_PRM register offsets */
534#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 534#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024
535#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) 535#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
536#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c 536#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c
537#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) 537#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
538#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 538#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030
539#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) 539#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
540#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 540#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034
541#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) 541#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
542#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 542#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038
543#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) 543#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
544#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c 544#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c
545#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) 545#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
546#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 546#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040
547#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) 547#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
548#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 548#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044
549#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) 549#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
550#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 550#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048
551#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) 551#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
552#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c 552#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c
553#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) 553#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
554#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 554#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054
555#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) 555#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
556#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 556#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058
557#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) 557#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
558#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c 558#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c
559#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) 559#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
560#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 560#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064
561#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) 561#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
562#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 562#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078
563#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) 563#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
564#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c 564#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c
565#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) 565#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
566#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 566#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080
567#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) 567#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
568#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 568#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084
569#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) 569#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
570 570
571/* PRM.WKUP_CM register offsets */ 571/* PRM.WKUP_CM register offsets */
572#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 572#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
573#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) 573#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
574#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 574#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020
575#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) 575#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
576#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 576#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028
577#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) 577#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
578#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 578#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030
579#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) 579#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
580#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 580#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038
581#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) 581#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
582#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 582#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040
583#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) 583#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
584#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 584#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048
585#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) 585#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
586#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 586#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050
587#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) 587#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
588#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 588#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058
589#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) 589#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
590#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 590#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060
591#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) 591#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
592#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 592#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078
593#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) 593#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
594#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 594#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080
595#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) 595#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
596#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 596#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088
597#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) 597#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
598 598
599/* PRM.EMU_PRM register offsets */ 599/* PRM.EMU_PRM register offsets */
600#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 600#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000
601#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) 601#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
602#define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 602#define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004
603#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) 603#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
604#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 604#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
605#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) 605#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
606 606
607/* PRM.EMU_CM register offsets */ 607/* PRM.EMU_CM register offsets */
608#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 608#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000
609#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) 609#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
610#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 610#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008
611#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) 611#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
612#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 612#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
613#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) 613#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
614 614
615/* PRM.DEVICE_PRM register offsets */ 615/* PRM.DEVICE_PRM register offsets */
616#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 616#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000
617#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) 617#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
618#define OMAP4_PRM_RSTST_OFFSET 0x0004 618#define OMAP4_PRM_RSTST_OFFSET 0x0004
619#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) 619#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
620#define OMAP4_PRM_RSTTIME_OFFSET 0x0008 620#define OMAP4_PRM_RSTTIME_OFFSET 0x0008
621#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) 621#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
622#define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c 622#define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c
623#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) 623#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
624#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 624#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010
625#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) 625#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
626#define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 626#define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014
627#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) 627#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
628#define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 628#define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018
629#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) 629#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
630#define OMAP4_PRM_IO_COUNT_OFFSET 0x001c 630#define OMAP4_PRM_IO_COUNT_OFFSET 0x001c
631#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) 631#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
632#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 632#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020
633#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) 633#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
634#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 634#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
635#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) 635#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
636#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 636#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
637#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) 637#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
638#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 638#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
639#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) 639#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
640#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 640#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030
641#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) 641#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
642#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 642#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
643#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) 643#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
644#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 644#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
645#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) 645#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
646#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c 646#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c
647#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) 647#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
648#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 648#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040
649#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) 649#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
650#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 650#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044
651#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) 651#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
652#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 652#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
653#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) 653#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
654#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 654#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
655#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) 655#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
656#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 656#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
657#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) 657#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
658#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 658#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
659#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) 659#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
660#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 660#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058
661#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) 661#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
662#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c 662#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c
663#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) 663#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
664#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 664#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
665#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) 665#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
666#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 666#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
667#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) 667#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
668#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 668#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
669#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) 669#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
670#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 670#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
671#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) 671#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
672#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 672#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070
673#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) 673#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
674#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 674#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074
675#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) 675#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
676#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 676#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078
677#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) 677#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
678#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c 678#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c
679#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) 679#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
680#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 680#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080
681#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) 681#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
682#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 682#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084
683#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) 683#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
684#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 684#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088
685#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) 685#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
686#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c 686#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c
687#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) 687#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
688#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 688#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090
689#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) 689#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
690#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 690#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
691#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) 691#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
692#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 692#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098
693#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) 693#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
694#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c 694#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c
695#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) 695#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
696#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 696#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
697#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) 697#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
698#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 698#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
699#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) 699#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
700#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 700#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8
701#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) 701#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
702#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac 702#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
703#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) 703#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
704#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 704#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
705#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) 705#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
706#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 706#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4
707#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) 707#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
708#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 708#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8
709#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) 709#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
710#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc 710#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc
711#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) 711#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
712#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 712#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0
713#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) 713#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
714#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 714#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4
715#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) 715#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
716#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 716#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8
717#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) 717#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
718#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc 718#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc
719#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) 719#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
720#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 720#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0
721#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) 721#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
722#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 722#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4
723#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) 723#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
724#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 724#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8
725#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) 725#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
726#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc 726#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
727#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) 727#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
728#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 728#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0
729#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) 729#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
730#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 730#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
731#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) 731#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
732#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 732#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
733#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) 733#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
734#define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec 734#define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec
735#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) 735#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
736#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 736#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
737#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) 737#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
738#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 738#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4
739#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) 739#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
740#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 740#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
741#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) 741#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
742 742
743/* Function prototypes */ 743/* Function prototypes */
744# ifndef __ASSEMBLER__ 744# ifndef __ASSEMBLER__
745 745
746extern u32 omap4_prm_read_mod_reg(s16 module, u16 idx);
747extern void omap4_prm_write_mod_reg(u32 val, s16 module, u16 idx);
748extern u32 omap4_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
749extern u32 omap4_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
750extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); 746extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
751extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
752extern u32 omap4_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
753extern u32 omap4_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
754 747
755extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); 748extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
756extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); 749extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 15:23:57 -0500