1 files changed, 16 insertions, 16 deletions

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 1e7a135de7b3..e4efb5203e22 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7809,6 +7809,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
                 tg3_abort_hw(tp, 1);
 
+        /* Enable MAC control of LPI */
+        if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
+                tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
+                       TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
+                       TG3_CPMU_EEE_LNKIDL_UART_IDL);
+
+                tw32_f(TG3_CPMU_EEE_CTRL,
+                       TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
+
+                tw32_f(TG3_CPMU_EEE_MODE,
+                       TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
+                       TG3_CPMU_EEEMD_LPI_IN_TX |
+                       TG3_CPMU_EEEMD_LPI_IN_RX |
+                       TG3_CPMU_EEEMD_EEE_ENABLE);
+        }
+
         if (reset_phy)
                 tg3_phy_reset(tp);
 
@@ -7890,22 +7906,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
         }
 
-        /* Enable MAC control of LPI */
-        if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-                tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
-                       TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
-                       TG3_CPMU_EEE_LNKIDL_UART_IDL);
-
-                tw32_f(TG3_CPMU_EEE_CTRL,
-                       TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
-
-                tw32_f(TG3_CPMU_EEE_MODE,
-                       TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
-                       TG3_CPMU_EEEMD_LPI_IN_TX |
-                       TG3_CPMU_EEEMD_LPI_IN_RX |
-                       TG3_CPMU_EEEMD_EEE_ENABLE);
-        }
-
         /* This works around an issue with Athlon chipsets on
          * B3 tigon3 silicon.  This bit has no effect on any
          * other revision.  But do not set this on PCI Express