2 files changed, 8 insertions, 17 deletions

diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 192357a3b9fe..d55b45d54f4d 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -30,6 +30,7 @@
 
 
 #include <asm/psw.h>
+#include <asm/cache.h>          /* for L1_CACHE_SHIFT */
 #include <asm/assembly.h>       /* for LDREG/STREG defines */
 #include <asm/pgtable.h>
 #include <asm/signal.h>
@@ -478,11 +479,7 @@
         bb,>=,n         \pmd,_PxD_PRESENT_BIT,\fault
         DEP             %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
         copy            \pmd,%r9
-#ifdef CONFIG_64BIT
-        shld            %r9,PxD_VALUE_SHIFT,\pmd
-#else
-        shlw            %r9,PxD_VALUE_SHIFT,\pmd
-#endif
+        SHLREG          %r9,PxD_VALUE_SHIFT,\pmd
         EXTR            \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
         DEP             %r0,31,PAGE_SHIFT,\pmd  /* clear offset */
         shladd          \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
@@ -970,11 +967,7 @@ intr_return:
         /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
         ** irq_stat[] is defined using ____cacheline_aligned.
         */
-#ifdef CONFIG_64BIT
-        shld    %r1, 6, %r20
-#else
-        shlw    %r1, 5, %r20
-#endif
+        SHLREG  %r1,L1_CACHE_SHIFT,%r20
         add     %r19,%r20,%r19  /* now have &irq_stat[smp_processor_id()] */
 #endif /* CONFIG_SMP */
 
@@ -2115,11 +2108,7 @@ syscall_check_bh:
         ldw     TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
 
         /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
-#ifdef CONFIG_64BIT
-        shld    %r26, 6, %r20
-#else
-        shlw    %r26, 5, %r20
-#endif
+        SHLREG  %r26,L1_CACHE_SHIFT,%r20
         add     %r19,%r20,%r19  /* now have &irq_stat[smp_processor_id()] */
 #endif /* CONFIG_SMP */
 
diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
index 1a7bfe699e0c..5a1e0e8b1c32 100644
--- a/include/asm-parisc/assembly.h
+++ b/include/asm-parisc/assembly.h
@@ -29,7 +29,8 @@
 #define LDREGX  ldd,s
 #define LDREGM  ldd,mb
 #define STREGM  std,ma
-#define SHRREG  shrd
+#define SHRREG  shrd
+#define SHLREG  shld
 #define RP_OFFSET       16
 #define FRAME_SIZE      128
 #define CALLEE_REG_FRAME_SIZE   144
@@ -39,7 +40,8 @@
 #define LDREGX  ldwx,s
 #define LDREGM  ldwm
 #define STREGM  stwm
-#define SHRREG  shr
+#define SHRREG  shr
+#define SHLREG  shlw
 #define RP_OFFSET       20
 #define FRAME_SIZE      64
 #define CALLEE_REG_FRAME_SIZE   128