137 files changed, 10745 insertions, 1383 deletions

diff --git a/Documentation/hwspinlock.txt b/Documentation/hwspinlock.txt
new file mode 100644
index 000000000000..7dcd1a4e726c
--- /dev/null
+++ b/Documentation/hwspinlock.txt
@@ -0,0 +1,293 @@
+Hardware Spinlock Framework
+
+1. Introduction
+
+Hardware spinlock modules provide hardware assistance for synchronization
+and mutual exclusion between heterogeneous processors and those not operating
+under a single, shared operating system.
+
+For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
+each of which is running a different Operating System (the master, A9,
+is usually running Linux and the slave processors, the M3 and the DSP,
+are running some flavor of RTOS).
+
+A generic hwspinlock framework allows platform-independent drivers to use
+the hwspinlock device in order to access data structures that are shared
+between remote processors, that otherwise have no alternative mechanism
+to accomplish synchronization and mutual exclusion operations.
+
+This is necessary, for example, for Inter-processor communications:
+on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the
+remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink).
+
+To achieve fast message-based communications, a minimal kernel support
+is needed to deliver messages arriving from a remote processor to the
+appropriate user process.
+
+This communication is based on simple data structures that is shared between
+the remote processors, and access to it is synchronized using the hwspinlock
+module (remote processor directly places new messages in this shared data
+structure).
+
+A common hwspinlock interface makes it possible to have generic, platform-
+independent, drivers.
+
+2. User API
+
+  struct hwspinlock *hwspin_lock_request(void);
+   - dynamically assign an hwspinlock and return its address, or NULL
+     in case an unused hwspinlock isn't available. Users of this
+     API will usually want to communicate the lock's id to the remote core
+     before it can be used to achieve synchronization.
+     Can be called from an atomic context (this function will not sleep) but
+     not from within interrupt context.
+
+  struct hwspinlock *hwspin_lock_request_specific(unsigned int id);
+   - assign a specific hwspinlock id and return its address, or NULL
+     if that hwspinlock is already in use. Usually board code will
+     be calling this function in order to reserve specific hwspinlock
+     ids for predefined purposes.
+     Can be called from an atomic context (this function will not sleep) but
+     not from within interrupt context.
+
+  int hwspin_lock_free(struct hwspinlock *hwlock);
+   - free a previously-assigned hwspinlock; returns 0 on success, or an
+     appropriate error code on failure (e.g. -EINVAL if the hwspinlock
+     is already free).
+     Can be called from an atomic context (this function will not sleep) but
+     not from within interrupt context.
+
+  int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout);
+   - lock a previously-assigned hwspinlock with a timeout limit (specified in
+     msecs). If the hwspinlock is already taken, the function will busy loop
+     waiting for it to be released, but give up when the timeout elapses.
+     Upon a successful return from this function, preemption is disabled so
+     the caller must not sleep, and is advised to release the hwspinlock as
+     soon as possible, in order to minimize remote cores polling on the
+     hardware interconnect.
+     Returns 0 when successful and an appropriate error code otherwise (most
+     notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
+     The function will never sleep.
+
+  int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int timeout);
+   - lock a previously-assigned hwspinlock with a timeout limit (specified in
+     msecs). If the hwspinlock is already taken, the function will busy loop
+     waiting for it to be released, but give up when the timeout elapses.
+     Upon a successful return from this function, preemption and the local
+     interrupts are disabled, so the caller must not sleep, and is advised to
+     release the hwspinlock as soon as possible.
+     Returns 0 when successful and an appropriate error code otherwise (most
+     notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
+     The function will never sleep.
+
+  int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, unsigned int to,
+                                                        unsigned long *flags);
+   - lock a previously-assigned hwspinlock with a timeout limit (specified in
+     msecs). If the hwspinlock is already taken, the function will busy loop
+     waiting for it to be released, but give up when the timeout elapses.
+     Upon a successful return from this function, preemption is disabled,
+     local interrupts are disabled and their previous state is saved at the
+     given flags placeholder. The caller must not sleep, and is advised to
+     release the hwspinlock as soon as possible.
+     Returns 0 when successful and an appropriate error code otherwise (most
+     notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
+     The function will never sleep.
+
+  int hwspin_trylock(struct hwspinlock *hwlock);
+   - attempt to lock a previously-assigned hwspinlock, but immediately fail if
+     it is already taken.
+     Upon a successful return from this function, preemption is disabled so
+     caller must not sleep, and is advised to release the hwspinlock as soon as
+     possible, in order to minimize remote cores polling on the hardware
+     interconnect.
+     Returns 0 on success and an appropriate error code otherwise (most
+     notably -EBUSY if the hwspinlock was already taken).
+     The function will never sleep.
+
+  int hwspin_trylock_irq(struct hwspinlock *hwlock);
+   - attempt to lock a previously-assigned hwspinlock, but immediately fail if
+     it is already taken.
+     Upon a successful return from this function, preemption and the local
+     interrupts are disabled so caller must not sleep, and is advised to
+     release the hwspinlock as soon as possible.
+     Returns 0 on success and an appropriate error code otherwise (most
+     notably -EBUSY if the hwspinlock was already taken).
+     The function will never sleep.
+
+  int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags);
+   - attempt to lock a previously-assigned hwspinlock, but immediately fail if
+     it is already taken.
+     Upon a successful return from this function, preemption is disabled,
+     the local interrupts are disabled and their previous state is saved
+     at the given flags placeholder. The caller must not sleep, and is advised
+     to release the hwspinlock as soon as possible.
+     Returns 0 on success and an appropriate error code otherwise (most
+     notably -EBUSY if the hwspinlock was already taken).
+     The function will never sleep.
+
+  void hwspin_unlock(struct hwspinlock *hwlock);
+   - unlock a previously-locked hwspinlock. Always succeed, and can be called
+     from any context (the function never sleeps). Note: code should _never_
+     unlock an hwspinlock which is already unlocked (there is no protection
+     against this).
+
+  void hwspin_unlock_irq(struct hwspinlock *hwlock);
+   - unlock a previously-locked hwspinlock and enable local interrupts.
+     The caller should _never_ unlock an hwspinlock which is already unlocked.
+     Doing so is considered a bug (there is no protection against this).
+     Upon a successful return from this function, preemption and local
+     interrupts are enabled. This function will never sleep.
+
+  void
+  hwspin_unlock_irqrestore(struct hwspinlock *hwlock, unsigned long *flags);
+   - unlock a previously-locked hwspinlock.
+     The caller should _never_ unlock an hwspinlock which is already unlocked.
+     Doing so is considered a bug (there is no protection against this).
+     Upon a successful return from this function, preemption is reenabled,
+     and the state of the local interrupts is restored to the state saved at
+     the given flags. This function will never sleep.
+
+  int hwspin_lock_get_id(struct hwspinlock *hwlock);
+   - retrieve id number of a given hwspinlock. This is needed when an
+     hwspinlock is dynamically assigned: before it can be used to achieve
+     mutual exclusion with a remote cpu, the id number should be communicated
+     to the remote task with which we want to synchronize.
+     Returns the hwspinlock id number, or -EINVAL if hwlock is null.
+
+3. Typical usage
+
+#include <linux/hwspinlock.h>
+#include <linux/err.h>
+
+int hwspinlock_example1(void)
+{
+        struct hwspinlock *hwlock;
+        int ret;
+
+        /* dynamically assign a hwspinlock */
+        hwlock = hwspin_lock_request();
+        if (!hwlock)
+                ...
+
+        id = hwspin_lock_get_id(hwlock);
+        /* probably need to communicate id to a remote processor now */
+
+        /* take the lock, spin for 1 sec if it's already taken */
+        ret = hwspin_lock_timeout(hwlock, 1000);
+        if (ret)
+                ...
+
+        /*
+         * we took the lock, do our thing now, but do NOT sleep
+         */
+
+        /* release the lock */
+        hwspin_unlock(hwlock);
+
+        /* free the lock */
+        ret = hwspin_lock_free(hwlock);
+        if (ret)
+                ...
+
+        return ret;
+}
+
+int hwspinlock_example2(void)
+{
+        struct hwspinlock *hwlock;
+        int ret;
+
+        /*
+         * assign a specific hwspinlock id - this should be called early
+         * by board init code.
+         */
+        hwlock = hwspin_lock_request_specific(PREDEFINED_LOCK_ID);
+        if (!hwlock)
+                ...
+
+        /* try to take it, but don't spin on it */
+        ret = hwspin_trylock(hwlock);
+        if (!ret) {
+                pr_info("lock is already taken\n");
+                return -EBUSY;
+        }
+
+        /*
+         * we took the lock, do our thing now, but do NOT sleep
+         */
+
+        /* release the lock */
+        hwspin_unlock(hwlock);
+
+        /* free the lock */
+        ret = hwspin_lock_free(hwlock);
+        if (ret)
+                ...
+
+        return ret;
+}
+
+
+4. API for implementors
+
+  int hwspin_lock_register(struct hwspinlock *hwlock);
+   - to be called from the underlying platform-specific implementation, in
+     order to register a new hwspinlock instance. Can be called from an atomic
+     context (this function will not sleep) but not from within interrupt
+     context. Returns 0 on success, or appropriate error code on failure.
+
+  struct hwspinlock *hwspin_lock_unregister(unsigned int id);
+   - to be called from the underlying vendor-specific implementation, in order
+     to unregister an existing (and unused) hwspinlock instance.
+     Can be called from an atomic context (will not sleep) but not from
+     within interrupt context.
+     Returns the address of hwspinlock on success, or NULL on error (e.g.
+     if the hwspinlock is sill in use).
+
+5. struct hwspinlock
+
+This struct represents an hwspinlock instance. It is registered by the
+underlying hwspinlock implementation using the hwspin_lock_register() API.
+
+/**
+ * struct hwspinlock - vendor-specific hwspinlock implementation
+ *
+ * @dev: underlying device, will be used with runtime PM api
+ * @ops: vendor-specific hwspinlock handlers
+ * @id: a global, unique, system-wide, index of the lock.
+ * @lock: initialized and used by hwspinlock core
+ * @owner: underlying implementation module, used to maintain module ref count
+ */
+struct hwspinlock {
+        struct device *dev;
+        const struct hwspinlock_ops *ops;
+        int id;
+        spinlock_t lock;
+        struct module *owner;
+};
+
+The underlying implementation is responsible to assign the dev, ops, id and
+owner members. The lock member, OTOH, is initialized and used by the hwspinlock
+core.
+
+6. Implementation callbacks
+
+There are three possible callbacks defined in 'struct hwspinlock_ops':
+
+struct hwspinlock_ops {
+        int (*trylock)(struct hwspinlock *lock);
+        void (*unlock)(struct hwspinlock *lock);
+        void (*relax)(struct hwspinlock *lock);
+};
+
+The first two callbacks are mandatory:
+
+The ->trylock() callback should make a single attempt to take the lock, and
+return 0 on failure and 1 on success. This callback may _not_ sleep.
+
+The ->unlock() callback releases the lock. It always succeed, and it, too,
+may _not_ sleep.
+
+The ->relax() callback is optional. It is called by hwspinlock core while
+spinning on a lock, and can be used by the underlying implementation to force
+a delay between two successive invocations of ->trylock(). It may _not_ sleep.
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index ae890caa17a7..019fb7c67dc3 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=2
 # CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index ba6009f27677..af98117043d2 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
-obj-y += clock.o clock_data.o opp_data.o
+obj-y += clock.o clock_data.o opp_data.o reset.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 22cc8c8df6cb..de88c9297b68 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -165,7 +165,7 @@ static struct map_desc ams_delta_io_desc[] __initdata = {
         }
 };
 
-static struct omap_lcd_config ams_delta_lcd_config __initdata = {
+static struct omap_lcd_config ams_delta_lcd_config = {
         .ctrl_name      = "internal",
 };
 
@@ -175,7 +175,7 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
         .pins[0]        = 2,
 };
 
-static struct omap_board_config_kernel ams_delta_config[] = {
+static struct omap_board_config_kernel ams_delta_config[] __initdata = {
         { OMAP_TAG_LCD,         &ams_delta_lcd_config },
 };
 
@@ -208,14 +208,14 @@ static const struct matrix_keymap_data ams_delta_keymap_data = {
         .keymap_size    = ARRAY_SIZE(ams_delta_keymap),
 };
 
-static struct omap_kp_platform_data ams_delta_kp_data = {
+static struct omap_kp_platform_data ams_delta_kp_data __initdata = {
         .rows           = 8,
         .cols           = 8,
         .keymap_data    = &ams_delta_keymap_data,
         .delay          = 9,
 };
 
-static struct platform_device ams_delta_kp_device = {
+static struct platform_device ams_delta_kp_device __initdata = {
         .name           = "omap-keypad",
         .id             = -1,
         .dev            = {
@@ -225,12 +225,12 @@ static struct platform_device ams_delta_kp_device = {
         .resource       = ams_delta_kp_resources,
 };
 
-static struct platform_device ams_delta_lcd_device = {
+static struct platform_device ams_delta_lcd_device __initdata = {
         .name   = "lcd_ams_delta",
         .id     = -1,
 };
 
-static struct platform_device ams_delta_led_device = {
+static struct platform_device ams_delta_led_device __initdata = {
         .name   = "ams-delta-led",
         .id     = -1
 };
@@ -259,7 +259,7 @@ static int ams_delta_camera_power(struct device *dev, int power)
 #define ams_delta_camera_power  NULL
 #endif
 
-static struct soc_camera_link __initdata ams_delta_iclink = {
+static struct soc_camera_link ams_delta_iclink = {
         .bus_id         = 0,    /* OMAP1 SoC camera bus */
         .i2c_adapter_id = 1,
         .board_info     = &ams_delta_camera_board_info[0],
@@ -267,7 +267,7 @@ static struct soc_camera_link __initdata ams_delta_iclink = {
         .power          = ams_delta_camera_power,
 };
 
-static struct platform_device ams_delta_camera_device = {
+static struct platform_device ams_delta_camera_device __initdata = {
         .name   = "soc-camera-pdrv",
         .id     = 0,
         .dev    = {
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 0efb9dbae44c..87f173d93557 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -287,11 +287,11 @@ static struct platform_device *devices[] __initdata = {
         &lcd_device,
 };
 
-static struct omap_lcd_config fsample_lcd_config __initdata = {
+static struct omap_lcd_config fsample_lcd_config = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel fsample_config[] = {
+static struct omap_board_config_kernel fsample_config[] __initdata = {
         { OMAP_TAG_LCD,         &fsample_lcd_config },
 };
 
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 28b84aa9bdba..ba3bd09c4754 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -202,7 +202,7 @@ static int h2_nand_dev_ready(struct mtd_info *mtd)
 
 static const char *h2_part_probes[] = { "cmdlinepart", NULL };
 
-struct platform_nand_data h2_nand_platdata = {
+static struct platform_nand_data h2_nand_platdata = {
         .chip   = {
                 .nr_chips               = 1,
                 .chip_offset            = 0,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index dbc8b8d882ba..ac48677672ee 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -204,7 +204,7 @@ static int nand_dev_ready(struct mtd_info *mtd)
 
 static const char *part_probes[] = { "cmdlinepart", NULL };
 
-struct platform_nand_data nand_platdata = {
+static struct platform_nand_data nand_platdata = {
         .chip   = {
                 .nr_chips               = 1,
                 .chip_offset            = 0,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index f2c5c585bc83..ba05a51f9408 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -331,7 +331,7 @@ static struct resource htcpld_resources[] = {
         },
 };
 
-struct htcpld_chip_platform_data htcpld_chips[] = {
+static struct htcpld_chip_platform_data htcpld_chips[] = {
         [0] = {
                 .addr           = 0x03,
                 .reset          = 0x04,
@@ -366,7 +366,7 @@ struct htcpld_chip_platform_data htcpld_chips[] = {
         },
 };
 
-struct htcpld_core_platform_data htcpld_pfdata = {
+static struct htcpld_core_platform_data htcpld_pfdata = {
         .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI,
         .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO,
         .i2c_adapter_id    = 1,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index a36e6742bf9b..2d9b8cbd7a14 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -365,7 +365,7 @@ static struct omap_mmc_platform_data mmc1_data = {
 
 static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC];
 
-void __init innovator_mmc_init(void)
+static void __init innovator_mmc_init(void)
 {
         mmc_data[0] = &mmc1_data;
         omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC);
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index d21f09dc78f4..cfd084926146 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -115,7 +115,7 @@ static struct mipid_platform_data nokia770_mipid_platform_data = {
         .shutdown = mipid_shutdown,
 };
 
-static void mipid_dev_init(void)
+static void __init mipid_dev_init(void)
 {
         const struct omap_lcd_config *conf;
 
@@ -126,7 +126,7 @@ static void mipid_dev_init(void)
         }
 }
 
-static void ads7846_dev_init(void)
+static void __init ads7846_dev_init(void)
 {
         if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0)
                 printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
@@ -170,7 +170,7 @@ static struct hwa742_platform_data nokia770_hwa742_platform_data = {
         .te_connected           = 1,
 };
 
-static void hwa742_dev_init(void)
+static void __init hwa742_dev_init(void)
 {
         clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
         omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index fb51ce6123d8..c9d38f47845f 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -230,19 +230,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
         },
 };
 
-static void palmte_headphones_detect(void *data, int state)
-{
-        if (state) {
-                /* Headphones connected, disable speaker */
-                gpio_set_value(PALMTE_SPEAKER_GPIO, 0);
-                printk(KERN_INFO "PM: speaker off\n");
-        } else {
-                /* Headphones unplugged, re-enable speaker */
-                gpio_set_value(PALMTE_SPEAKER_GPIO, 1);
-                printk(KERN_INFO "PM: speaker on\n");
-        }
-}
-
 static void __init palmte_misc_gpio_setup(void)
 {
         /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 815a69ce821d..bdc0ac8dc21f 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,10 +26,12 @@
 #include <linux/smc91x.h>
 
 #include <mach/hardware.h>
+#include <mach/system.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <plat/board-voiceblue.h>
 #include <plat/common.h>
 #include <mach/gpio.h>
 #include <plat/flash.h>
@@ -163,52 +165,6 @@ static void __init voiceblue_init_irq(void)
         omap_init_irq();
 }
 
-static void __init voiceblue_init(void)
-{
-        /* mux pins for uarts */
-        omap_cfg_reg(UART1_TX);
-        omap_cfg_reg(UART1_RTS);
-        omap_cfg_reg(UART2_TX);
-        omap_cfg_reg(UART2_RTS);
-        omap_cfg_reg(UART3_TX);
-        omap_cfg_reg(UART3_RX);
-
-        /* Watchdog */
-        gpio_request(0, "Watchdog");
-        /* smc91x reset */
-        gpio_request(7, "SMC91x reset");
-        gpio_direction_output(7, 1);
-        udelay(2);      /* wait at least 100ns */
-        gpio_set_value(7, 0);
-        mdelay(50);     /* 50ms until PHY ready */
-        /* smc91x interrupt pin */
-        gpio_request(8, "SMC91x irq");
-        /* 16C554 reset*/
-        gpio_request(6, "16C554 reset");
-        gpio_direction_output(6, 0);
-        /* 16C554 interrupt pins */
-        gpio_request(12, "16C554 irq");
-        gpio_request(13, "16C554 irq");
-        gpio_request(14, "16C554 irq");
-        gpio_request(15, "16C554 irq");
-        set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
-
-        platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
-        omap_board_config = voiceblue_config;
-        omap_board_config_size = ARRAY_SIZE(voiceblue_config);
-        omap_serial_init();
-        omap1_usb_init(&voiceblue_usb_config);
-        omap_register_i2c_bus(1, 100, NULL, 0);
-
-        /* There is a good chance board is going up, so enable power LED
-         * (it is connected through invertor) */
-        omap_writeb(0x00, OMAP_LPG1_LCR);
-        omap_writeb(0x00, OMAP_LPG1_PMR);       /* Disable clock */
-}
-
 static void __init voiceblue_map_io(void)
 {
         omap1_map_common_io();
@@ -275,8 +231,17 @@ void voiceblue_wdt_ping(void)
         gpio_set_value(0, wdt_gpio_state);
 }
 
-void voiceblue_reset(void)
+static void voiceblue_reset(char mode, const char *cmd)
 {
+        /*
+         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+         * "Global Software Reset Affects Traffic Controller Frequency".
+         */
+        if (cpu_is_omap5912()) {
+                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
+                omap_writew(0x8, ARM_RSTCT1);
+        }
+
         set_bit(MACHINE_REBOOT, &machine_state);
         voiceblue_wdt_enable();
         while (1) ;
@@ -286,6 +251,54 @@ EXPORT_SYMBOL(voiceblue_wdt_enable);
 EXPORT_SYMBOL(voiceblue_wdt_disable);
 EXPORT_SYMBOL(voiceblue_wdt_ping);
 
+static void __init voiceblue_init(void)
+{
+        /* mux pins for uarts */
+        omap_cfg_reg(UART1_TX);
+        omap_cfg_reg(UART1_RTS);
+        omap_cfg_reg(UART2_TX);
+        omap_cfg_reg(UART2_RTS);
+        omap_cfg_reg(UART3_TX);
+        omap_cfg_reg(UART3_RX);
+
+        /* Watchdog */
+        gpio_request(0, "Watchdog");
+        /* smc91x reset */
+        gpio_request(7, "SMC91x reset");
+        gpio_direction_output(7, 1);
+        udelay(2);      /* wait at least 100ns */
+        gpio_set_value(7, 0);
+        mdelay(50);     /* 50ms until PHY ready */
+        /* smc91x interrupt pin */
+        gpio_request(8, "SMC91x irq");
+        /* 16C554 reset*/
+        gpio_request(6, "16C554 reset");
+        gpio_direction_output(6, 0);
+        /* 16C554 interrupt pins */
+        gpio_request(12, "16C554 irq");
+        gpio_request(13, "16C554 irq");
+        gpio_request(14, "16C554 irq");
+        gpio_request(15, "16C554 irq");
+        set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
+
+        platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
+        omap_board_config = voiceblue_config;
+        omap_board_config_size = ARRAY_SIZE(voiceblue_config);
+        omap_serial_init();
+        omap1_usb_init(&voiceblue_usb_config);
+        omap_register_i2c_bus(1, 100, NULL, 0);
+
+        /* There is a good chance board is going up, so enable power LED
+         * (it is connected through invertor) */
+        omap_writeb(0x00, OMAP_LPG1_LCR);
+        omap_writeb(0x00, OMAP_LPG1_PMR);       /* Disable clock */
+
+        arch_reset = voiceblue_reset;
+}
+
 MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
         /* Maintainer: Ladislav Michl <michl@2n.cz> */
         .boot_params    = 0x10000100,
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
new file mode 100644
index 000000000000..ad951ee69205
--- /dev/null
+++ b/arch/arm/mach-omap1/reset.c
@@ -0,0 +1,25 @@
+/*
+ * OMAP1 reset support
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/system.h>
+#include <plat/prcm.h>
+
+void omap1_arch_reset(char mode, const char *cmd)
+{
+        /*
+         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+         * "Global Software Reset Affects Traffic Controller Frequency".
+         */
+        if (cpu_is_omap5912()) {
+                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
+                omap_writew(0x8, ARM_RSTCT1);
+        }
+
+        omap_writew(1, ARM_RSTCT1);
+}
+
+void (*arch_reset)(char, const char *) = omap1_arch_reset;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1a2cf6226a55..b9d8a7b2a862 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -53,25 +53,30 @@ config ARCH_OMAP4
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
 
-config ARCH_OMAP2420
+config SOC_OMAP2420
         bool "OMAP2420 support"
         depends on ARCH_OMAP2
         default y
         select OMAP_DM_TIMER
         select ARCH_OMAP_OTG
 
-config ARCH_OMAP2430
+config SOC_OMAP2430
         bool "OMAP2430 support"
         depends on ARCH_OMAP2
         default y
         select ARCH_OMAP_OTG
 
-config ARCH_OMAP3430
+config SOC_OMAP3430
         bool "OMAP3430 support"
         depends on ARCH_OMAP3
         default y
         select ARCH_OMAP_OTG
 
+config SOC_OMAPTI816X
+        bool "TI816X support"
+        depends on ARCH_OMAP3
+        default y
+
 config OMAP_PACKAGE_ZAF
        bool
 
@@ -106,25 +111,25 @@ config MACH_OMAP_GENERIC
 
 config MACH_OMAP2_TUSB6010
         bool
-        depends on ARCH_OMAP2 && ARCH_OMAP2420
+        depends on ARCH_OMAP2 && SOC_OMAP2420
         default y if MACH_NOKIA_N8X0
 
 config MACH_OMAP_H4
         bool "OMAP 2420 H4 board"
-        depends on ARCH_OMAP2420
+        depends on SOC_OMAP2420
         default y
         select OMAP_PACKAGE_ZAF
         select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
         bool "OMAP 2420 Apollon board"
-        depends on ARCH_OMAP2420
+        depends on SOC_OMAP2420
         default y
         select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
         bool "OMAP 2430 SDP board"
-        depends on ARCH_OMAP2430
+        depends on SOC_OMAP2430
         default y
         select OMAP_PACKAGE_ZAC
 
@@ -219,7 +224,7 @@ config MACH_NOKIA_N810_WIMAX
 
 config MACH_NOKIA_N8X0
         bool "Nokia N800/N810"
-        depends on ARCH_OMAP2420
+        depends on SOC_OMAP2420
         default y
         select OMAP_PACKAGE_ZAC
         select MACH_NOKIA_N800
@@ -294,12 +299,18 @@ config MACH_OMAP_3630SDP
         default y
         select OMAP_PACKAGE_CBP
 
+config MACH_TI8168EVM
+        bool "TI8168 Evaluation Module"
+        depends on SOC_OMAPTI816X
+        default y
+
 config MACH_OMAP_4430SDP
         bool "OMAP 4430 SDP board"
         default y
         depends on ARCH_OMAP4
         select OMAP_PACKAGE_CBL
         select OMAP_PACKAGE_CBS
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP4_PANDA
         bool "OMAP4 Panda Board"
@@ -307,6 +318,7 @@ config MACH_OMAP4_PANDA
         depends on ARCH_OMAP4
         select OMAP_PACKAGE_CBL
         select OMAP_PACKAGE_CBS
+        select REGULATOR_FIXED_VOLTAGE
 
 config OMAP3_EMU
         bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1c0c2b02d870..1c3635d7f4cf 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -31,8 +31,8 @@ AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
 AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a$(plus_sec)
 
 # Functions loaded to SRAM
-obj-$(CONFIG_ARCH_OMAP2420)             += sram242x.o
-obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
+obj-$(CONFIG_SOC_OMAP2420)              += sram242x.o
+obj-$(CONFIG_SOC_OMAP2430)              += sram243x.o
 obj-$(CONFIG_ARCH_OMAP3)                += sram34xx.o
 
 AFLAGS_sram242x.o                       :=-Wa,-march=armv6
@@ -40,8 +40,8 @@ AFLAGS_sram243x.o			:=-Wa,-march=armv6
 AFLAGS_sram34xx.o                       :=-Wa,-march=armv7-a
 
 # Pin multiplexing
-obj-$(CONFIG_ARCH_OMAP2420)             += mux2420.o
-obj-$(CONFIG_ARCH_OMAP2430)             += mux2430.o
+obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
+obj-$(CONFIG_SOC_OMAP2430)              += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += mux44xx.o
 
@@ -113,8 +113,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= $(clock-common) clock2xxx.o \
                                            clkt2xxx_dpllcore.o \
                                            clkt2xxx_virt_prcm_set.o \
                                            clkt2xxx_apll.o clkt2xxx_osc.o
-obj-$(CONFIG_ARCH_OMAP2420)             += clock2420_data.o
-obj-$(CONFIG_ARCH_OMAP2430)             += clock2430.o clock2430_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o \
                                            clock34xx.o clkt34xx_dpll3m2.o \
                                            clock3517.o clock36xx.o \
@@ -123,12 +123,12 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \
                                            dpll3xxx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
-obj-$(CONFIG_ARCH_OMAP2420)             += opp2420_data.o
-obj-$(CONFIG_ARCH_OMAP2430)             += opp2430_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
-obj-$(CONFIG_ARCH_OMAP2420)             += omap_hwmod_2420_data.o
-obj-$(CONFIG_ARCH_OMAP2430)             += omap_hwmod_2430_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
@@ -218,12 +218,14 @@ obj-$(CONFIG_MACH_OMAP4_PANDA)		+= board-omap4panda.o \
                                            hsmmc.o \
                                            omap_phy_internal.o
 
-obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
+obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o \
+                                           omap_phy_internal.o \
 
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
 
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
 # Platform specific device init code
 usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
 obj-y                                   += $(usbfs-m) $(usbfs-y)
@@ -242,3 +244,7 @@ obj-y					+= $(smc91x-m) $(smc91x-y)
 
 smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
 obj-y                                   += $(smsc911x-m) $(smsc911x-y)
+obj-$(CONFIG_ARCH_OMAP4)                += hwspinlock.o
+
+disp-$(CONFIG_OMAP2_DSS)                := display.o
+obj-y                                   += $(disp-m) $(disp-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index e0661777f599..cc42d474c443 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -22,6 +22,7 @@
 #include <linux/mmc/host.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
+#include <linux/regulator/machine.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -139,15 +140,33 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
         {OMAP_TAG_LCD, &sdp2430_lcd_config},
 };
 
-static void __init omap_2430sdp_init_irq(void)
+static void __init omap_2430sdp_init_early(void)
 {
         omap_board_config = sdp2430_config;
         omap_board_config_size = ARRAY_SIZE(sdp2430_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
+static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data sdp2430_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(sdp2430_vmmc1_supplies),
+        .consumer_supplies      = &sdp2430_vmmc1_supplies[0],
+};
+
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -160,6 +179,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
 
         /* platform_data for children goes here */
         .gpio           = &sdp2430_gpio_data,
+        .vmmc1          = &sdp2430_vmmc1,
 };
 
 static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
@@ -253,9 +273,10 @@ static void __init omap_2430sdp_map_io(void)
 MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
         .boot_params    = 0x80000100,
-        .map_io         = omap_2430sdp_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_2430sdp_init_irq,
+        .map_io         = omap_2430sdp_map_io,
+        .init_early     = omap_2430sdp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_2430sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index d4e41ef86aa5..8950ecc9b940 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -307,34 +307,19 @@ static struct omap_dss_board_info sdp3430_dss_data = {
         .default_device = &sdp3430_lcd_device,
 };
 
-static struct platform_device sdp3430_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &sdp3430_dss_data,
-        },
-};
-
-static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &sdp3430_dss_device.dev,
-};
-
-static struct platform_device *sdp3430_devices[] __initdata = {
-        &sdp3430_dss_device,
-};
+static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
 };
 
-static void __init omap_3430sdp_init_irq(void)
+static void __init omap_3430sdp_init_early(void)
 {
         omap_board_config = sdp3430_config;
         omap_board_config_size = ARRAY_SIZE(sdp3430_config);
         omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
-        omap_init_irq();
 }
 
 static int sdp3430_batt_table[] = {
@@ -370,18 +355,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
-        .supply                 = "vmmc",
-};
-
-static struct regulator_consumer_supply sdp3430_vsim_supply = {
-        .supply                 = "vmmc_aux",
-};
-
-static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
-        .supply                 = "vmmc",
-};
-
 static int sdp3430_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -392,13 +365,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
         mmc[1].gpio_cd = gpio + 1;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
-         * regulators will be set up only *after* we return.
-         */
-        sdp3430_vmmc1_supply.dev = mmc[0].dev;
-        sdp3430_vsim_supply.dev = mmc[0].dev;
-        sdp3430_vmmc2_supply.dev = mmc[1].dev;
-
         /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
         gpio_request(gpio + 7, "sub_lcd_en_bkl");
         gpio_direction_output(gpio + 7, 0);
@@ -427,6 +393,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
         .irq_line       = 1,
 };
 
+/* regulator consumer mappings */
+
+/* ads7846 on SPI */
+static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
+        REGULATOR_SUPPLY("vdda_dac", "omapdss"),
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
+};
+
 /*
  * Apply all the fixed voltages since most versions of U-Boot
  * don't bother with that initialization.
@@ -469,6 +463,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies          = ARRAY_SIZE(sdp3430_vaux3_supplies),
+        .consumer_supplies              = sdp3430_vaux3_supplies,
 };
 
 /* VAUX4 for OMAP VDD_CSI2 (camera) */
@@ -495,8 +491,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc1_supplies),
+        .consumer_supplies      = sdp3430_vmmc1_supplies,
 };
 
 /* VMMC2 for MMC2 card */
@@ -510,8 +506,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vmmc2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc2_supplies),
+        .consumer_supplies      = sdp3430_vmmc2_supplies,
 };
 
 /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -525,8 +521,8 @@ static struct regulator_init_data sdp3430_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vsim_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vsim_supplies),
+        .consumer_supplies      = sdp3430_vsim_supplies,
 };
 
 /* VDAC for DSS driving S-Video */
@@ -540,16 +536,8 @@ static struct regulator_init_data sdp3430_vdac = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
-        {
-                .supply         = "vdds_dsi",
-                .dev            = &sdp3430_dss_device.dev,
-        }
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
+        .consumer_supplies      = sdp3430_vdda_dac_supplies,
 };
 
 static struct regulator_init_data sdp3430_vpll2 = {
@@ -801,7 +789,7 @@ static void __init omap_3430sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3430_i2c_init();
-        platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
+        omap_display_init(&sdp3430_dss_data);
         if (omap_rev() > OMAP3430_REV_ES1_0)
                 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
         else
@@ -813,7 +801,7 @@ static void __init omap_3430sdp_init(void)
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_3430);
+        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
         usb_ehci_init(&ehci_pdata);
@@ -822,9 +810,10 @@ static void __init omap_3430sdp_init(void)
 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_3430sdp_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_3430sdp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_3430sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 62645640f5e4..8d1c4358ecf9 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -11,6 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -69,14 +70,13 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_config_kernel sdp_config[] __initdata = {
 };
 
-static void __init omap_sdp_init_irq(void)
+static void __init omap_sdp_init_early(void)
 {
         omap_board_config = sdp_config;
         omap_board_config_size = ARRAY_SIZE(sdp_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
                                   h8mbx00u0mer0em_sdrc_params);
-        omap_init_irq();
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -209,16 +209,17 @@ static void __init omap_sdp_init(void)
         zoom_peripherals_init();
         zoom_display_init();
         board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_sdp);
+        board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
         usb_ehci_init(&ehci_pdata);
 }
 
 MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_sdp_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_sdp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 07d1b20b1148..1a943be822c3 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include <plat/omap4-keypad.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -44,10 +45,93 @@
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
 #define ETH_KS8851_QUART                138
-#define OMAP4SDP_MDM_PWR_EN_GPIO        157
 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
 #define OMAP4_SFH7741_ENABLE_GPIO               188
 
+static const int sdp4430_keymap[] = {
+        KEY(0, 0, KEY_E),
+        KEY(0, 1, KEY_R),
+        KEY(0, 2, KEY_T),
+        KEY(0, 3, KEY_HOME),
+        KEY(0, 4, KEY_F5),
+        KEY(0, 5, KEY_UNKNOWN),
+        KEY(0, 6, KEY_I),
+        KEY(0, 7, KEY_LEFTSHIFT),
+
+        KEY(1, 0, KEY_D),
+        KEY(1, 1, KEY_F),
+        KEY(1, 2, KEY_G),
+        KEY(1, 3, KEY_SEND),
+        KEY(1, 4, KEY_F6),
+        KEY(1, 5, KEY_UNKNOWN),
+        KEY(1, 6, KEY_K),
+        KEY(1, 7, KEY_ENTER),
+
+        KEY(2, 0, KEY_X),
+        KEY(2, 1, KEY_C),
+        KEY(2, 2, KEY_V),
+        KEY(2, 3, KEY_END),
+        KEY(2, 4, KEY_F7),
+        KEY(2, 5, KEY_UNKNOWN),
+        KEY(2, 6, KEY_DOT),
+        KEY(2, 7, KEY_CAPSLOCK),
+
+        KEY(3, 0, KEY_Z),
+        KEY(3, 1, KEY_KPPLUS),
+        KEY(3, 2, KEY_B),
+        KEY(3, 3, KEY_F1),
+        KEY(3, 4, KEY_F8),
+        KEY(3, 5, KEY_UNKNOWN),
+        KEY(3, 6, KEY_O),
+        KEY(3, 7, KEY_SPACE),
+
+        KEY(4, 0, KEY_W),
+        KEY(4, 1, KEY_Y),
+        KEY(4, 2, KEY_U),
+        KEY(4, 3, KEY_F2),
+        KEY(4, 4, KEY_VOLUMEUP),
+        KEY(4, 5, KEY_UNKNOWN),
+        KEY(4, 6, KEY_L),
+        KEY(4, 7, KEY_LEFT),
+
+        KEY(5, 0, KEY_S),
+        KEY(5, 1, KEY_H),
+        KEY(5, 2, KEY_J),
+        KEY(5, 3, KEY_F3),
+        KEY(5, 4, KEY_F9),
+        KEY(5, 5, KEY_VOLUMEDOWN),
+        KEY(5, 6, KEY_M),
+        KEY(5, 7, KEY_RIGHT),
+
+        KEY(6, 0, KEY_Q),
+        KEY(6, 1, KEY_A),
+        KEY(6, 2, KEY_N),
+        KEY(6, 3, KEY_BACK),
+        KEY(6, 4, KEY_BACKSPACE),
+        KEY(6, 5, KEY_UNKNOWN),
+        KEY(6, 6, KEY_P),
+        KEY(6, 7, KEY_UP),
+
+        KEY(7, 0, KEY_PROG1),
+        KEY(7, 1, KEY_PROG2),
+        KEY(7, 2, KEY_PROG3),
+        KEY(7, 3, KEY_PROG4),
+        KEY(7, 4, KEY_F4),
+        KEY(7, 5, KEY_UNKNOWN),
+        KEY(7, 6, KEY_OK),
+        KEY(7, 7, KEY_DOWN),
+};
+
+static struct matrix_keymap_data sdp4430_keymap_data = {
+        .keymap                 = sdp4430_keymap,
+        .keymap_size            = ARRAY_SIZE(sdp4430_keymap),
+};
+
+static struct omap4_keypad_platform_data sdp4430_keypad_data = {
+        .keymap_data            = &sdp4430_keymap_data,
+        .rows                   = 8,
+        .cols                   = 8,
+};
 static struct gpio_led sdp4430_gpio_leds[] = {
         {
                 .name   = "omap4:green:debug0",
@@ -239,7 +323,7 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
-static void __init omap_4430sdp_init_irq(void)
+static void __init omap_4430sdp_init_early(void)
 {
         omap_board_config = sdp4430_config;
         omap_board_config_size = ARRAY_SIZE(sdp4430_config);
@@ -248,19 +332,8 @@ static void __init omap_4430sdp_init_irq(void)
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(1);
 #endif
-        gic_init_irq();
 }
 
-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0]   = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1]   = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[2]   = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .phy_reset      = false,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL,
-};
-
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
         .mode                   = MUSB_OTG,
@@ -434,7 +507,6 @@ static struct regulator_init_data sdp4430_vana = {
         .constraints = {
                 .min_uV                 = 2100000,
                 .max_uV                 = 2100000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -446,7 +518,6 @@ static struct regulator_init_data sdp4430_vcxio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -458,7 +529,6 @@ static struct regulator_init_data sdp4430_vdac = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -576,14 +646,6 @@ static void __init omap_4430sdp_init(void)
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
 
-        /* Power on the ULPI PHY */
-        status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3");
-        if (status)
-                pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__);
-        else
-                gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1);
-
-        usb_ehci_init(&ehci_pdata);
         usb_musb_init(&musb_board_data);
 
         status = omap_ethernet_init();
@@ -594,6 +656,10 @@ static void __init omap_4430sdp_init(void)
                 spi_register_board_info(sdp4430_spi_board_info,
                                 ARRAY_SIZE(sdp4430_spi_board_info));
         }
+
+        status = omap4_keyboard_init(&sdp4430_keypad_data);
+        if (status)
+                pr_err("Keypad initialization failed: %d\n", status);
 }
 
 static void __init omap_4430sdp_map_io(void)
@@ -605,9 +671,10 @@ static void __init omap_4430sdp_map_io(void)
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
         .boot_params    = 0x80000100,
-        .map_io         = omap_4430sdp_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_4430sdp_init_irq,
+        .map_io         = omap_4430sdp_map_io,
+        .init_early     = omap_4430sdp_init_early,
+        .init_irq       = gic_init_irq,
         .init_machine   = omap_4430sdp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 71acb5ab281c..ae3a83d47dab 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -49,14 +49,13 @@ static struct omap_board_mux board_mux[] __initdata = {
 #define board_mux       NULL
 #endif
 
-static void __init am3517_crane_init_irq(void)
+static void __init am3517_crane_init_early(void)
 {
         omap_board_config = am3517_crane_config;
         omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
 
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
@@ -108,9 +107,10 @@ static void __init am3517_crane_init(void)
 
 MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = am3517_crane_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = am3517_crane_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = am3517_crane_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 10d60b7743cf..634fe65b33c8 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -378,37 +378,28 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
         .default_device = &am3517_evm_lcd_device,
 };
 
-static struct platform_device am3517_evm_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &am3517_evm_dss_data,
-        },
-};
-
 /*
  * Board initialization
  */
 static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
 };
 
-static struct platform_device *am3517_evm_devices[] __initdata = {
-        &am3517_evm_dss_device,
-};
-
-static void __init am3517_evm_init_irq(void)
+static void __init am3517_evm_init_early(void)
 {
         omap_board_config = am3517_evm_config;
         omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_ULPI,
         .mode                   = MUSB_OTG,
         .power                  = 500,
+        .set_phy_power          = am35x_musb_phy_power,
+        .clear_irq              = am35x_musb_clear_irq,
+        .set_mode               = am35x_musb_set_mode,
+        .reset                  = am35x_musb_reset,
 };
 
 static __init void am3517_evm_musb_init(void)
@@ -495,9 +486,7 @@ static void __init am3517_evm_init(void)
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         am3517_evm_i2c_init();
-        platform_add_devices(am3517_evm_devices,
-                                ARRAY_SIZE(am3517_evm_devices));
-
+        omap_display_init(&am3517_evm_dss_data);
         omap_serial_init();
 
         /* Configure GPIO for EHCI port */
@@ -521,9 +510,10 @@ static void __init am3517_evm_init(void)
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = am3517_evm_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = am3517_evm_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = am3517_evm_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 9f55b68687f7..4ef4aad4e719 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -274,13 +274,12 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
         { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
 
-static void __init omap_apollon_init_irq(void)
+static void __init omap_apollon_init_early(void)
 {
         omap_board_config = apollon_config;
         omap_board_config_size = ARRAY_SIZE(apollon_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 static void __init apollon_led_init(void)
@@ -355,9 +354,10 @@ static void __init omap_apollon_map_io(void)
 MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
         .boot_params    = 0x80000100,
-        .map_io         = omap_apollon_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_apollon_init_irq,
+        .map_io         = omap_apollon_map_io,
+        .init_early     = omap_apollon_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_apollon_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index dac141610666..7311824be993 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
         .default_device = &cm_t35_dvi_device,
 };
 
-static struct platform_device cm_t35_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &cm_t35_dss_data,
-        },
-};
-
 static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
         .turbo_mode     = 0,
         .single_channel = 1,    /* 0: slave, 1: master */
@@ -468,7 +460,7 @@ static void __init cm_t35_init_display(void)
         msleep(50);
         gpio_set_value(lcd_en_gpio, 1);
 
-        err = platform_device_register(&cm_t35_dss_device);
+        err = omap_display_init(&cm_t35_dss_data);
         if (err) {
                 pr_err("CM-T35: failed to register DSS device\n");
                 goto err_dev_reg;
@@ -495,15 +487,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
         .supply                 = "vmmc_aux",
 };
 
-static struct regulator_consumer_supply cm_t35_vdac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &cm_t35_dss_device.dev,
-};
+static struct regulator_consumer_supply cm_t35_vdac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
-static struct regulator_consumer_supply cm_t35_vdvi_supply = {
-        .supply         = "vdvi",
-        .dev            = &cm_t35_dss_device.dev,
-};
+static struct regulator_consumer_supply cm_t35_vdvi_supply =
+        REGULATOR_SUPPLY("vdvi", "omapdss");
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data cm_t35_vmmc1 = {
@@ -683,7 +671,7 @@ static void __init cm_t35_init_i2c(void)
 static struct omap_board_config_kernel cm_t35_config[] __initdata = {
 };
 
-static void __init cm_t35_init_irq(void)
+static void __init cm_t35_init_early(void)
 {
         omap_board_config = cm_t35_config;
         omap_board_config_size = ARRAY_SIZE(cm_t35_config);
@@ -691,7 +679,6 @@ static void __init cm_t35_init_irq(void)
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
 }
 
 static struct omap_board_mux board_mux[] __initdata = {
@@ -815,9 +802,10 @@ static void __init cm_t35_init(void)
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = cm_t35_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = cm_t35_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = cm_t35_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 8f9a64d650ee..38bef6d004c9 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -254,14 +254,13 @@ static inline void cm_t3517_init_nand(void) {}
 static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
 };
 
-static void __init cm_t3517_init_irq(void)
+static void __init cm_t3517_init_early(void)
 {
         omap_board_config = cm_t3517_config;
         omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
 
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 static struct omap_board_mux board_mux[] __initdata = {
@@ -303,9 +302,10 @@ static void __init cm_t3517_init(void)
 
 MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = cm_t3517_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = cm_t3517_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = cm_t3517_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 9a2a31e011ce..54abdd064364 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
         .default_device = &devkit8000_lcd_device,
 };
 
-static struct platform_device devkit8000_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &devkit8000_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
@@ -456,11 +448,15 @@ static struct platform_device keys_gpio = {
 };
 
 
-static void __init devkit8000_init_irq(void)
+static void __init devkit8000_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
+}
+
+static void __init devkit8000_init_irq(void)
+{
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -575,7 +571,6 @@ static void __init omap_dm9000_init(void)
 }
 
 static struct platform_device *devkit8000_devices[] __initdata = {
-        &devkit8000_dss_device,
         &leds_gpio,
         &keys_gpio,
         &omap_dm9000_dev,
@@ -797,6 +792,7 @@ static void __init devkit8000_init(void)
         platform_add_devices(devkit8000_devices,
                         ARRAY_SIZE(devkit8000_devices));
 
+        omap_display_init(&devkit8000_dss_data);
         spi_register_board_info(devkit8000_spi_board_info,
         ARRAY_SIZE(devkit8000_spi_board_info));
 
@@ -813,8 +809,9 @@ static void __init devkit8000_init(void)
 
 MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = devkit8000_init_early,
         .init_irq       = devkit8000_init_irq,
         .init_machine   = devkit8000_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index fd38c05bb47f..c32c06828f08 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -1,5 +1,5 @@
 /*
- * board-sdp-flash.c
+ * board-flash.c
  * Modified from mach-omap2/board-3430sdp-flash.c
  *
  * Copyright (C) 2009 Nokia Corporation
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
+#include <plat/irqs.h>
 
 #include <plat/gpmc.h>
 #include <plat/nand.h>
@@ -73,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
                                         + FLASH_SIZE_SDPV1 - 1;
         }
         if (err < 0) {
-                printk(KERN_ERR "NOR: Can't request GPMC CS\n");
+                pr_err("NOR: Can't request GPMC CS\n");
                 return;
         }
         if (platform_device_register(&board_nor_device) < 0)
-                printk(KERN_ERR "Unable to register NOR device\n");
+                pr_err("Unable to register NOR device\n");
 }
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@@ -139,12 +140,16 @@ static struct omap_nand_platform_data board_nand_data = {
 };
 
 void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
+__init board_nand_init(struct mtd_partition *nand_parts,
+                        u8 nr_parts, u8 cs, int nand_type)
 {
         board_nand_data.cs              = cs;
         board_nand_data.parts           = nand_parts;
-        board_nand_data.nr_parts                = nr_parts;
+        board_nand_data.nr_parts        = nr_parts;
+        board_nand_data.devsize         = nand_type;
 
+        board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+        board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
         gpmc_nand_init(&board_nand_data);
 }
 #else
@@ -189,12 +194,12 @@ unmap:
 }
 
 /**
- * sdp3430_flash_init - Identify devices connected to GPMC and register.
+ * board_flash_init - Identify devices connected to GPMC and register.
  *
  * @return - void.
  */
 void board_flash_init(struct flash_partitions partition_info[],
-                                        char chip_sel_board[][GPMC_CS_NUM])
+                        char chip_sel_board[][GPMC_CS_NUM], int nand_type)
 {
         u8              cs = 0;
         u8              norcs = GPMC_CS_NUM + 1;
@@ -208,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
          */
         idx = get_gpmc0_type();
         if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
-                printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
+                pr_err("%s: Invalid chip select: %d\n", __func__, cs);
                 return;
         }
         config_sel = (unsigned char *)(chip_sel_board[idx]);
@@ -232,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
         }
 
         if (norcs > GPMC_CS_NUM)
-                printk(KERN_INFO "NOR: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("NOR: Unable to find configuration in GPMC\n");
         else
                 board_nor_init(partition_info[0].parts,
                                 partition_info[0].nr_parts, norcs);
 
         if (onenandcs > GPMC_CS_NUM)
-                printk(KERN_INFO "OneNAND: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("OneNAND: Unable to find configuration in GPMC\n");
         else
                 board_onenand_init(partition_info[1].parts,
                                         partition_info[1].nr_parts, onenandcs);
 
         if (nandcs > GPMC_CS_NUM)
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("NAND: Unable to find configuration in GPMC\n");
         else
                 board_nand_init(partition_info[2].parts,
-                                partition_info[2].nr_parts, nandcs);
+                        partition_info[2].nr_parts, nandcs, nand_type);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 69befe00dd2f..c240a3f8d163 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -25,6 +25,6 @@ struct flash_partitions {
 };
 
 extern void board_flash_init(struct flash_partitions [],
-                                char chip_sel[][GPMC_CS_NUM]);
+                                char chip_sel[][GPMC_CS_NUM], int nand_type);
 extern void board_nand_init(struct mtd_partition *nand_parts,
-                                        u8 nr_parts, u8 cs);
+                                        u8 nr_parts, u8 cs, int nand_type);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 0e3d81e09f89..682da9251db6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,13 +33,12 @@
 static struct omap_board_config_kernel generic_config[] = {
 };
 
-static void __init omap_generic_init_irq(void)
+static void __init omap_generic_init_early(void)
 {
         omap_board_config = generic_config;
         omap_board_config_size = ARRAY_SIZE(generic_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 static void __init omap_generic_init(void)
@@ -68,9 +67,10 @@ static void __init omap_generic_map_io(void)
 MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
         .boot_params    = 0x80000100,
-        .map_io         = omap_generic_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_generic_init_irq,
+        .map_io         = omap_generic_map_io,
+        .init_early     = omap_generic_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 25cc9dad4b02..f6a3872f72fa 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -290,12 +290,16 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
         { OMAP_TAG_LCD,         &h4_lcd_config },
 };
 
-static void __init omap_h4_init_irq(void)
+static void __init omap_h4_init_early(void)
 {
         omap_board_config = h4_config;
         omap_board_config_size = ARRAY_SIZE(h4_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
+}
+
+static void __init omap_h4_init_irq(void)
+{
         omap_init_irq();
         h4_init_flash();
 }
@@ -378,8 +382,9 @@ static void __init omap_h4_map_io(void)
 MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
         .boot_params    = 0x80000100,
-        .map_io         = omap_h4_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap_h4_map_io,
+        .init_early     = omap_h4_init_early,
         .init_irq       = omap_h4_init_irq,
         .init_machine   = omap_h4_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 3be85a1f55f4..54e6318f4a8f 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -485,18 +485,8 @@ static struct omap_dss_board_info igep2_dss_data = {
         .default_device = &igep2_dvi_device,
 };
 
-static struct platform_device igep2_dss_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &igep2_dss_data,
-        },
-};
-
-static struct regulator_consumer_supply igep2_vpll2_supply = {
-        .supply = "vdds_dsi",
-        .dev    = &igep2_dss_device.dev,
-};
+static struct regulator_consumer_supply igep2_vpll2_supply =
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
 
 static struct regulator_init_data igep2_vpll2 = {
         .constraints = {
@@ -521,16 +511,14 @@ static void __init igep2_display_init(void)
 }
 
 static struct platform_device *igep2_devices[] __initdata = {
-        &igep2_dss_device,
         &igep2_vwlan_device,
 };
 
-static void __init igep2_init_irq(void)
+static void __init igep2_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(m65kxxxxam_sdrc_params,
                                   m65kxxxxam_sdrc_params);
-        omap_init_irq();
 }
 
 static struct twl4030_codec_audio_data igep2_audio_data = {
@@ -697,6 +685,7 @@ static void __init igep2_init(void)
         /* Register I2C busses and drivers */
         igep2_i2c_init();
         platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
+        omap_display_init(&igep2_dss_data);
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         usb_ehci_init(&ehci_pdata);
@@ -716,9 +705,10 @@ static void __init igep2_init(void)
 
 MACHINE_START(IGEP0020, "IGEP v2 board")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = igep2_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = igep2_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = igep2_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index 4dc62a9b9cb2..d75028e48f5d 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -331,12 +331,11 @@ static struct platform_device *igep3_devices[] __initdata = {
         &igep3_vwlan_device,
 };
 
-static void __init igep3_init_irq(void)
+static void __init igep3_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(m65kxxxxam_sdrc_params,
                                   m65kxxxxam_sdrc_params);
-        omap_init_irq();
 }
 
 static struct twl4030_platform_data igep3_twl4030_pdata = {
@@ -452,7 +451,8 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
         .boot_params    = 0x80000100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_irq       = igep3_init_irq,
+        .init_early     = igep3_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = igep3_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index e5dc74875f9d..a3fae5697a72 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -288,13 +288,12 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
         { OMAP_TAG_LCD,         &ldp_lcd_config },
 };
 
-static void __init omap_ldp_init_irq(void)
+static void __init omap_ldp_init_early(void)
 {
         omap_board_config = ldp_config;
         omap_board_config_size = ARRAY_SIZE(ldp_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 static struct twl4030_usb_data ldp_usb_data = {
@@ -434,7 +433,7 @@ static void __init omap_ldp_init(void)
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         board_nand_init(ldp_nand_partitions,
-                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS);
+                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
         omap2_hsmmc_init(mmc);
         /* link regulators to MMC adapters */
@@ -443,9 +442,10 @@ static void __init omap_ldp_init(void)
 
 MACHINE_START(OMAP_LDP, "OMAP LDP board")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_ldp_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_ldp_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_ldp_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index f396756872b7..b36cbd21e2d0 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -628,11 +628,10 @@ static void __init n8x0_map_io(void)
         omap242x_map_common_io();
 }
 
-static void __init n8x0_init_irq(void)
+static void __init n8x0_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -703,27 +702,30 @@ static void __init n8x0_init_machine(void)
 
 MACHINE_START(NOKIA_N800, "Nokia N800")
         .boot_params    = 0x80000100,
-        .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = n8x0_init_irq,
+        .map_io         = n8x0_map_io,
+        .init_early     = n8x0_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810, "Nokia N810")
         .boot_params    = 0x80000100,
-        .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = n8x0_init_irq,
+        .map_io         = n8x0_map_io,
+        .init_early     = n8x0_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
         .boot_params    = 0x80000100,
-        .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = n8x0_init_irq,
+        .map_io         = n8x0_map_io,
+        .init_early     = n8x0_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 46d814ab5656..a1faea3b7764 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -228,14 +228,6 @@ static struct omap_dss_board_info beagle_dss_data = {
         .default_device = &beagle_dvi_device,
 };
 
-static struct platform_device beagle_dss_device = {
-        .name          = "omapdss",
-        .id            = -1,
-        .dev            = {
-                .platform_data = &beagle_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply beagle_vdac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
@@ -536,11 +528,15 @@ static struct platform_device keys_gpio = {
         },
 };
 
-static void __init omap3_beagle_init_irq(void)
+static void __init omap3_beagle_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
+}
+
+static void __init omap3_beagle_init_irq(void)
+{
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -550,7 +546,6 @@ static void __init omap3_beagle_init_irq(void)
 static struct platform_device *omap3_beagle_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
-        &beagle_dss_device,
 };
 
 static void __init omap3beagle_flash_init(void)
@@ -617,6 +612,7 @@ static void __init omap3_beagle_init(void)
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
+        omap_display_init(&beagle_dss_data);
         omap_serial_init();
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
@@ -638,8 +634,9 @@ static void __init omap3_beagle_init(void)
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3_beagle_init_early,
         .init_irq       = omap3_beagle_init_irq,
         .init_machine   = omap3_beagle_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 323c3809ce39..7341f966bf1a 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -30,6 +30,8 @@
 #include <linux/usb/otg.h>
 #include <linux/smsc911x.h>
 
+#include <linux/wl12xx.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
 
@@ -58,6 +60,13 @@
 #define OMAP3EVM_ETHR_ID_REV    0x50
 #define OMAP3EVM_ETHR_GPIO_IRQ  176
 #define OMAP3EVM_SMSC911X_CS    5
+/*
+ * Eth Reset signal
+ *      64 = Generation 1 (<=RevD)
+ *      7 = Generation 2 (>=RevE)
+ */
+#define OMAP3EVM_GEN1_ETHR_GPIO_RST     64
+#define OMAP3EVM_GEN2_ETHR_GPIO_RST     7
 
 static u8 omap3_evm_version;
 
@@ -124,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = {
 
 static inline void __init omap3evm_init_smsc911x(void)
 {
-        int eth_cs;
+        int eth_cs, eth_rst;
         struct clk *l3ck;
         unsigned int rate;
 
+        if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
+                eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
+        else
+                eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
+
         eth_cs = OMAP3EVM_SMSC911X_CS;
 
         l3ck = clk_get(NULL, "l3_ck");
@@ -136,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void)
         else
                 rate = clk_get_rate(l3ck);
 
+        /* Configure ethernet controller reset gpio */
+        if (cpu_is_omap3430()) {
+                if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
+                        pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
+                                        eth_rst);
+                        return;
+                }
+
+                if (gpio_direction_output(eth_rst, 1) < 0) {
+                        pr_err(KERN_ERR "Failed to set direction of %d for" \
+                                        " smsc911x\n", eth_rst);
+                        return;
+                }
+                /* reset pulse to ethernet controller*/
+                usleep_range(150, 220);
+                gpio_set_value(eth_rst, 0);
+                usleep_range(150, 220);
+                gpio_set_value(eth_rst, 1);
+                usleep_range(1, 2);
+        }
+
         if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
                         OMAP3EVM_ETHR_GPIO_IRQ);
@@ -235,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
         else
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
 
         lcd_enabled = 1;
         return 0;
@@ -248,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
         else
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
 
         lcd_enabled = 0;
 }
@@ -289,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
+        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
 
         dvi_enabled = 1;
         return 0;
@@ -297,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
 
 static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
 {
-        gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
+        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
 
         dvi_enabled = 0;
 }
@@ -328,14 +363,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
         .default_device = &omap3_evm_lcd_device,
 };
 
-static struct platform_device omap3_evm_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &omap3_evm_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
         .supply                 = "vmmc",
 };
@@ -381,6 +408,16 @@ static struct omap2_hsmmc_info mmc[] = {
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
         },
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        {
+                .name           = "wl1271",
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .nonremovable   = true,
+        },
+#endif
         {}      /* Terminator */
 };
 
@@ -411,6 +448,8 @@ static struct platform_device leds_gpio = {
 static int omap3evm_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int r;
+
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
@@ -426,8 +465,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
          */
 
         /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
+        if (!r)
+                r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
+                        (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
+        if (r)
+                printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
 
         /* gpio + 7 == DVI Enable */
         gpio_request(gpio + 7, "EN_DVI");
@@ -500,10 +543,8 @@ static struct twl4030_codec_data omap3evm_codec_data = {
         .audio = &omap3evm_audio_data,
 };
 
-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &omap3_evm_dss_device.dev,
-};
+static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 /* VDAC for DSS driving S-Video */
 static struct regulator_init_data omap3_evm_vdac = {
@@ -538,6 +579,66 @@ static struct regulator_init_data omap3_evm_vpll2 = {
         .consumer_supplies      = &omap3_evm_vpll2_supply,
 };
 
+/* ads7846 on SPI */
+static struct regulator_consumer_supply omap3evm_vio_supply =
+        REGULATOR_SUPPLY("vcc", "spi1.0");
+
+/* VIO for ads7846 */
+static struct regulator_init_data omap3evm_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &omap3evm_vio_supply,
+};
+
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+
+#define OMAP3EVM_WLAN_PMENA_GPIO        (150)
+#define OMAP3EVM_WLAN_IRQ_GPIO          (149)
+
+static struct regulator_consumer_supply omap3evm_vmmc2_supply =
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+
+/* VMMC2 for driving the WL12xx module */
+static struct regulator_init_data omap3evm_vmmc2 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies = &omap3evm_vmmc2_supply,
+};
+
+static struct fixed_voltage_config omap3evm_vwlan = {
+        .supply_name            = "vwl1271",
+        .microvolts             = 1800000, /* 1.80V */
+        .gpio                   = OMAP3EVM_WLAN_PMENA_GPIO,
+        .startup_delay          = 70000, /* 70ms */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &omap3evm_vmmc2,
+};
+
+static struct platform_device omap3evm_wlan_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &omap3evm_vwlan,
+        },
+};
+
+struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
+        .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
+        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
+};
+#endif
+
 static struct twl4030_platform_data omap3evm_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -550,6 +651,7 @@ static struct twl4030_platform_data omap3evm_twldata = {
         .codec          = &omap3evm_codec_data,
         .vdac           = &omap3_evm_vdac,
         .vpll2          = &omap3_evm_vpll2,
+        .vio            = &omap3evm_vio,
 };
 
 static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
@@ -625,19 +727,14 @@ static struct spi_board_info omap3evm_spi_board_info[] = {
 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 };
 
-static void __init omap3_evm_init_irq(void)
+static void __init omap3_evm_init_early(void)
 {
         omap_board_config = omap3_evm_config;
         omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
-        omap_init_irq();
 }
 
-static struct platform_device *omap3_evm_devices[] __initdata = {
-        &omap3_evm_dss_device,
-};
-
 static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
 
         .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -652,14 +749,76 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
 };
 
 #ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
+static struct omap_board_mux omap35x_board_mux[] __initdata = {
         OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
                                 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
                                 OMAP_PIN_OFF_WAKEUPENABLE),
         OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
-                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_NONE),
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WLAN IRQ - GPIO 149 */
+        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* WLAN POWER ENABLE - GPIO 150 */
+        OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* MMC2 SDIO pin muxes for WL12xx */
+        OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+#endif
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+
+static struct omap_board_mux omap36x_board_mux[] __initdata = {
+        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WLAN IRQ - GPIO 149 */
+        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* WLAN POWER ENABLE - GPIO 150 */
+        OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* MMC2 SDIO pin muxes for WL12xx */
+        OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+#endif
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap35x_board_mux       NULL
+#define omap36x_board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
@@ -671,11 +830,15 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init omap3_evm_init(void)
 {
         omap3_evm_get_revision();
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        if (cpu_is_omap3630())
+                omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
+        else
+                omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
 
         omap3_evm_i2c_init();
 
-        platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
+        omap_display_init(&omap3_evm_dss_data);
 
         spi_register_board_info(omap3evm_spi_board_info,
                                 ARRAY_SIZE(omap3evm_spi_board_info));
@@ -715,14 +878,22 @@ static void __init omap3_evm_init(void)
         ads7846_dev_init();
         omap3evm_init_smsc911x();
         omap3_evm_display_init();
+
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WL12xx WLAN Init */
+        if (wl12xx_set_platform_data(&omap3evm_wlan_data))
+                pr_err("error setting wl12xx data\n");
+        platform_device_register(&omap3evm_wlan_regulator);
+#endif
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
         /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap3_evm_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3_evm_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap3_evm_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 15e4b08e99ba..b726943d7c93 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -195,11 +195,10 @@ static inline void __init board_smsc911x_init(void)
         gpmc_smsc911x_init(&board_smsc911x_data);
 }
 
-static void __init omap3logic_init_irq(void)
+static void __init omap3logic_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        omap_init_irq();
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -225,7 +224,8 @@ static void __init omap3logic_init(void)
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
-        .init_irq       = omap3logic_init_irq,
+        .init_early     = omap3logic_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap3logic_init,
         .timer          = &omap_timer,
 MACHINE_END
@@ -233,7 +233,8 @@ MACHINE_END
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
-        .init_irq       = omap3logic_init_irq,
+        .init_early     = omap3logic_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap3logic_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 0b34beded11f..17ef5479c7ff 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = {
         .default_device = &pandora_lcd_device,
 };
 
-static struct platform_device pandora_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &pandora_dss_data,
-        },
-};
-
 static void pandora_wl1251_init_card(struct mmc_card *card)
 {
         /*
@@ -634,12 +626,11 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         }
 };
 
-static void __init omap3pandora_init_irq(void)
+static void __init omap3pandora_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
 }
 
 static void __init pandora_wl1251_init(void)
@@ -677,7 +668,6 @@ fail:
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
-        &pandora_dss_device,
         &pandora_vwlan_device,
 };
 
@@ -712,6 +702,7 @@ static void __init omap3pandora_init(void)
         pandora_wl1251_init();
         platform_add_devices(omap3pandora_devices,
                         ARRAY_SIZE(omap3pandora_devices));
+        omap_display_init(&pandora_dss_data);
         omap_serial_init();
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
@@ -727,9 +718,10 @@ static void __init omap3pandora_init(void)
 
 MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap3pandora_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3pandora_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap3pandora_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 2a2dad447e86..07006c323fc2 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
         .default_device = &omap3_stalker_dvi_device,
 };
 
-static struct platform_device omap3_stalker_dss_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &omap3_stalker_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
         .supply         = "vmmc",
 };
@@ -448,10 +440,8 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
         .audio          = &omap3stalker_audio_data,
 };
 
-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &omap3_stalker_dss_device.dev,
-};
+static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 /* VDAC for DSS driving S-Video */
 static struct regulator_init_data omap3_stalker_vdac = {
@@ -469,10 +459,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
 };
 
 /* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
-        .supply         = "vdds_dsi",
-        .dev            = &omap3_stalker_lcd_device.dev,
-};
+static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
 
 static struct regulator_init_data omap3_stalker_vpll2 = {
         .constraints            = {
@@ -591,12 +579,16 @@ static struct spi_board_info omap3stalker_spi_board_info[] = {
 static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
 };
 
-static void __init omap3_stalker_init_irq(void)
+static void __init omap3_stalker_init_early(void)
 {
         omap_board_config = omap3_stalker_config;
         omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
+}
+
+static void __init omap3_stalker_init_irq(void)
+{
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -604,7 +596,6 @@ static void __init omap3_stalker_init_irq(void)
 }
 
 static struct platform_device *omap3_stalker_devices[] __initdata = {
-        &omap3_stalker_dss_device,
         &keys_gpio,
 };
 
@@ -644,6 +635,7 @@ static void __init omap3_stalker_init(void)
         platform_add_devices(omap3_stalker_devices,
                              ARRAY_SIZE(omap3_stalker_devices));
 
+        omap_display_init(&omap3_stalker_dss_data);
         spi_register_board_info(omap3stalker_spi_board_info,
                                 ARRAY_SIZE(omap3stalker_spi_board_info));
 
@@ -666,6 +658,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
         /* Maintainer: Jason Lam -lzg@ema-tech.com */
         .boot_params            = 0x80000100,
         .map_io                 = omap3_map_io,
+        .init_early             = omap3_stalker_init_early,
         .init_irq               = omap3_stalker_init_irq,
         .init_machine           = omap3_stalker_init,
         .timer                  = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index db1f74fe6c4f..6a60f79dcccb 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -415,7 +415,7 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static void __init omap3_touchbook_init_irq(void)
+static void __init omap3_touchbook_init_early(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_board_config = omap3_touchbook_config;
@@ -423,6 +423,10 @@ static void __init omap3_touchbook_init_irq(void)
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
+}
+
+static void __init omap3_touchbook_init_irq(void)
+{
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -538,8 +542,9 @@ static void __init omap3_touchbook_init(void)
 MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3_touchbook_init_early,
         .init_irq       = omap3_touchbook_init_irq,
         .init_machine   = omap3_touchbook_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e944025d5ef8..3dd241b95159 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -26,6 +26,8 @@
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/wl12xx.h>
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -45,6 +47,8 @@
 
 #define GPIO_HUB_POWER          1
 #define GPIO_HUB_NRESET         62
+#define GPIO_WIFI_PMENA         43
+#define GPIO_WIFI_IRQ           53
 
 static struct gpio_led gpio_leds[] = {
         {
@@ -76,11 +80,10 @@ static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
 };
 
-static void __init omap4_panda_init_irq(void)
+static void __init omap4_panda_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-        gic_init_irq();
 }
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -162,6 +165,15 @@ static struct omap2_hsmmc_info mmc[] = {
                 .gpio_wp        = -EINVAL,
                 .gpio_cd        = -EINVAL,
         },
+        {
+                .name           = "wl1271",
+                .mmc            = 5,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .ocr_mask       = MMC_VDD_165_195,
+                .nonremovable   = true,
+        },
         {}      /* Terminator */
 };
 
@@ -172,6 +184,43 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
         },
 };
 
+static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
+        .supply = "vmmc",
+        .dev_name = "mmci-omap-hs.4",
+};
+
+static struct regulator_init_data panda_vmmc5 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &omap4_panda_vmmc5_supply,
+};
+
+static struct fixed_voltage_config panda_vwlan = {
+        .supply_name = "vwl1271",
+        .microvolts = 1800000, /* 1.8V */
+        .gpio = GPIO_WIFI_PMENA,
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,
+        .enabled_at_boot = 0,
+        .init_data = &panda_vmmc5,
+};
+
+static struct platform_device omap_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &panda_vwlan,
+        },
+};
+
+struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
+        .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
+        /* PANDA ref clock is 38.4 MHz */
+        .board_ref_clock = 2,
+};
+
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
         int ret = 0;
@@ -305,7 +354,6 @@ static struct regulator_init_data omap4_panda_vana = {
         .constraints = {
                 .min_uV                 = 2100000,
                 .max_uV                 = 2100000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -317,7 +365,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -329,7 +376,6 @@ static struct regulator_init_data omap4_panda_vdac = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -391,6 +437,19 @@ static int __init omap4_panda_i2c_init(void)
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* WLAN IRQ - GPIO 53 */
+        OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
+        /* WLAN POWER ENABLE - GPIO 43 */
+        OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* WLAN SDIO: MMC5 CMD */
+        OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC5 CLK */
+        OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC5 DAT[0-3] */
+        OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -405,8 +464,12 @@ static void __init omap4_panda_init(void)
                 package = OMAP_PACKAGE_CBL;
         omap4_mux_init(board_mux, package);
 
+        if (wl12xx_set_platform_data(&omap_panda_wlan_data))
+                pr_err("error setting wl12xx data\n");
+
         omap4_panda_i2c_init();
         platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
+        platform_device_register(&omap_vwlan_device);
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
         omap4_ehci_init();
@@ -424,7 +487,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         .boot_params    = 0x80000100,
         .reserve        = omap_reserve,
         .map_io         = omap4_panda_map_io,
-        .init_irq       = omap4_panda_init_irq,
+        .init_early     = omap4_panda_init_early,
+        .init_irq       = gic_init_irq,
         .init_machine   = omap4_panda_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index cb26e5d8268d..a33ec0edec13 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -409,14 +409,13 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
         { OMAP_TAG_LCD,         &overo_lcd_config },
 };
 
-static void __init overo_init_irq(void)
+static void __init overo_init_early(void)
 {
         omap_board_config = overo_config;
         omap_board_config_size = ARRAY_SIZE(overo_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
 }
 
 static struct platform_device *overo_devices[] __initdata = {
@@ -501,9 +500,10 @@ static void __init overo_init(void)
 
 MACHINE_START(OVERO, "Gumstix Overo")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = overo_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = overo_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = overo_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 39a71bb8a308..bdebcb7328e6 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -138,14 +138,13 @@ static void __init rm680_peripherals_init(void)
         omap2_hsmmc_init(mmc);
 }
 
-static void __init rm680_init_irq(void)
+static void __init rm680_init_early(void)
 {
         struct omap_sdrc_params *sdrc_params;
 
         omap2_init_common_infrastructure();
         sdrc_params = nokia_get_sdram_timings();
         omap2_init_common_devices(sdrc_params, sdrc_params);
-        omap_init_irq();
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -176,9 +175,10 @@ static void __init rm680_map_io(void)
 
 MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
         .boot_params    = 0x80000100,
-        .map_io         = rm680_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = rm680_init_irq,
+        .map_io         = rm680_map_io,
+        .init_early     = rm680_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = rm680_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index acd670054d9a..89a66db8b77d 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
         .default_device = &rx51_lcd_device,
 };
 
-struct platform_device rx51_display_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &rx51_dss_board_info,
-        },
-};
-
-static struct platform_device *rx51_video_devices[] __initdata = {
-        &rx51_display_device,
-};
-
 static int __init rx51_video_init(void)
 {
         if (!machine_is_nokia_rx51())
@@ -95,8 +83,7 @@ static int __init rx51_video_init(void)
 
         gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
 
-        platform_add_devices(rx51_video_devices,
-                                ARRAY_SIZE(rx51_video_devices));
+        omap_display_init(&rx51_dss_board_info);
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index f53fc551c58f..3cf72fe6d75b 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -98,7 +98,7 @@ static struct omap_board_config_kernel rx51_config[] = {
         { OMAP_TAG_LCD,         &rx51_lcd_config },
 };
 
-static void __init rx51_init_irq(void)
+static void __init rx51_init_early(void)
 {
         struct omap_sdrc_params *sdrc_params;
 
@@ -108,7 +108,6 @@ static void __init rx51_init_irq(void)
         omap2_init_common_infrastructure();
         sdrc_params = nokia_get_sdram_timings();
         omap2_init_common_devices(sdrc_params, sdrc_params);
-        omap_init_irq();
 }
 
 extern void __init rx51_peripherals_init(void);
@@ -149,9 +148,10 @@ static void __init rx51_map_io(void)
 MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
         .boot_params    = 0x80000100,
-        .map_io         = rx51_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = rx51_init_irq,
+        .map_io         = rx51_map_io,
+        .init_early     = rx51_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = rx51_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
new file mode 100644
index 000000000000..f2b097190e07
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -0,0 +1,62 @@
+/*
+ * Code for TI8168 EVM.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/irqs.h>
+#include <plat/board.h>
+#include <plat/common.h>
+
+static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+};
+
+static void __init ti8168_init_early(void)
+{
+        omap_board_config = ti8168_evm_config;
+        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+}
+
+static void __init ti8168_evm_init_irq(void)
+{
+        omap_init_irq();
+}
+
+static void __init ti8168_evm_init(void)
+{
+        omap_serial_init();
+}
+
+static void __init ti8168_evm_map_io(void)
+{
+        omap2_set_globals_ti816x();
+        omapti816x_map_common_io();
+}
+
+MACHINE_START(TI8168EVM, "ti8168evm")
+        /* Maintainer: Texas Instruments */
+        .boot_params    = 0x80000100,
+        .map_io         = ti8168_evm_map_io,
+        .init_early     = ti8168_init_early,
+        .init_irq       = ti8168_evm_init_irq,
+        .timer          = &omap_timer,
+        .init_machine   = ti8168_evm_init,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 6bcd43657aed..37b84c2b850f 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = {
         .default_device         = &zoom_lcd_device,
 };
 
-static struct platform_device zoom_dss_device = {
-        .name                           = "omapdss",
-        .id                             = -1,
-        .dev                            = {
-                .platform_data          = &zoom_dss_data,
-        },
-};
-
 static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
         .turbo_mode             = 1,
         .single_channel = 1,  /* 0: slave, 1: master */
@@ -153,14 +145,9 @@ static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
         },
 };
 
-static struct platform_device *zoom_display_devices[] __initdata = {
-        &zoom_dss_device,
-};
-
 void __init zoom_display_init(void)
 {
-        platform_add_devices(zoom_display_devices,
-                                ARRAY_SIZE(zoom_display_devices));
+        omap_display_init(&zoom_dss_data);
         spi_register_board_info(nec_8048_spi_board_info,
                                 ARRAY_SIZE(nec_8048_spi_board_info));
         zoom_lcd_panel_init();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index e26754c24ee8..7e3f1595d77b 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -16,6 +16,7 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -33,7 +34,7 @@
 
 #define ZOOM3_EHCI_RESET_GPIO           64
 
-static void __init omap_zoom_init_irq(void)
+static void __init omap_zoom_init_early(void)
 {
         omap2_init_common_infrastructure();
         if (machine_is_omap_zoom2())
@@ -42,8 +43,6 @@ static void __init omap_zoom_init_irq(void)
         else if (machine_is_omap_zoom3())
                 omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
                                           h8mbx00u0mer0em_sdrc_params);
-
-        omap_init_irq();
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -126,8 +125,8 @@ static void __init omap_zoom_init(void)
                 usb_ehci_init(&ehci_pdata);
         }
 
-        board_nand_init(zoom_nand_partitions,
-                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
+        board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
+                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
         zoom_debugboard_init();
         zoom_peripherals_init();
         zoom_display_init();
@@ -135,18 +134,20 @@ static void __init omap_zoom_init(void)
 
 MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_zoom_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_zoom_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_zoom_init,
         .timer          = &omap_timer,
 MACHINE_END
 
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
         .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
-        .init_irq       = omap_zoom_init_irq,
+        .map_io         = omap3_map_io,
+        .init_early     = omap_zoom_init_early,
+        .init_irq       = omap_init_irq,
         .init_machine   = omap_zoom_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index a781cd6795a4..e25364de028a 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
                                 u32 *field_val)
 {
         const struct clksel *clks;
-        const struct clksel_rate *clkr, *max_clkr;
+        const struct clksel_rate *clkr, *max_clkr = NULL;
         u8 max_div = 0;
 
         clks = _get_clksel_by_parent(clk, src_clk);
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 6a658b890c17..cc5c8d422c5b 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -20,13 +20,13 @@ u32 omap2xxx_get_apll_clkin(void);
 u32 omap2xxx_get_sysclkdiv(void);
 void omap2xxx_clk_prepare_for_reboot(void);
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 int omap2420_clk_init(void);
 #else
 #define omap2420_clk_init()     0
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 int omap2430_clk_init(void);
 #else
 #define omap2430_clk_init()     0
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 403a4a1d3f9c..f14d986f0b5d 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void)
         } else if (cpu_is_omap3630()) {
                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
                 cpu_clkflg = CK_36XX;
+        } else if (cpu_is_ti816x()) {
+                cpu_mask = RATE_IN_TI816X;
+                cpu_clkflg = CK_TI816X;
         } else if (cpu_is_omap34xx()) {
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
                         cpu_mask = RATE_IN_3430ES1;
@@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void)
         /*
          * Lock DPLL5 and put it in autoidle.
          */
-        if (omap_rev() >= OMAP3430_REV_ES2_0)
+        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
                 omap3_clk_lock_dpll5();
 
         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index e4a7133ea3b3..e6f0d18d5e8d 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -171,7 +171,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
 
 /* 2430-specific possible wakeup dependencies */
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 
 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
 static struct clkdm_dep mdm_2430_wkdeps[] = {
@@ -194,7 +194,7 @@ static struct clkdm_dep mdm_2430_wkdeps[] = {
         { NULL },
 };
 
-#endif /* CONFIG_ARCH_OMAP2430 */
+#endif /* CONFIG_SOC_OMAP2430 */
 
 
 /* OMAP3-specific possible dependencies */
@@ -450,7 +450,7 @@ static struct clockdomain cm_clkdm = {
  * 2420-only clockdomains
  */
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 
 static struct clockdomain mpu_2420_clkdm = {
         .name           = "mpu_clkdm",
@@ -514,14 +514,14 @@ static struct clockdomain dss_2420_clkdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-#endif   /* CONFIG_ARCH_OMAP2420 */
+#endif   /* CONFIG_SOC_OMAP2420 */
 
 
 /*
  * 2430-only clockdomains
  */
 
-#if defined(CONFIG_ARCH_OMAP2430)
+#if defined(CONFIG_SOC_OMAP2430)
 
 static struct clockdomain mpu_2430_clkdm = {
         .name           = "mpu_clkdm",
@@ -600,7 +600,7 @@ static struct clockdomain dss_2430_clkdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-#endif    /* CONFIG_ARCH_OMAP2430 */
+#endif    /* CONFIG_SOC_OMAP2430 */
 
 
 /*
@@ -811,7 +811,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
         &cm_clkdm,
         &prm_clkdm,
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
         &mpu_2420_clkdm,
         &iva1_2420_clkdm,
         &dsp_2420_clkdm,
@@ -821,7 +821,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
         &dss_2420_clkdm,
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
         &mpu_2430_clkdm,
         &mdm_clkdm,
         &dsp_2430_clkdm,
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 778929f7e92d..48de4513de49 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -40,7 +40,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 
 static struct omap_globals omap242x_globals = {
         .class  = OMAP242X_CLASS,
@@ -61,7 +61,7 @@ void __init omap2_set_globals_242x(void)
 }
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2430)
+#if defined(CONFIG_SOC_OMAP2430)
 
 static struct omap_globals omap243x_globals = {
         .class  = OMAP243X_CLASS,
@@ -108,6 +108,27 @@ void __init omap3_map_io(void)
         omap2_set_globals_3xxx();
         omap34xx_map_common_io();
 }
+
+/*
+ * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * TI816X register for checking device ID (it adds 0x204 to tap base while
+ * TI816X DEVICE ID register is at offset 0x600 from control base).
+ */
+#define TI816X_TAP_BASE         (TI816X_CTRL_BASE + \
+                                TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals ti816x_globals = {
+        .class  = OMAP343X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
+        .ctrl   = TI816X_CTRL_BASE,
+        .prm    = TI816X_PRCM_BASE,
+        .cm     = TI816X_PRCM_BASE,
+};
+
+void __init omap2_set_globals_ti816x(void)
+{
+        __omap2_set_globals(&ti816x_globals);
+}
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index f0629ae04102..c2804c1c4efd 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,6 +52,9 @@
 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
 
+/* TI816X spefic control submodules */
+#define TI816X_CONTROL_DEVCONF          0x600
+
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
 
 #define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
@@ -241,6 +244,9 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
+/* TI816X CONTROL_DEVCONF register offsets */
+#define TI816X_CONTROL_DEVICE_ID        (TI816X_CONTROL_DEVCONF + 0x000)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2c9c912f2c42..9ee876fd367a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -30,6 +31,7 @@
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap4-keypad.h>
 
 #include "mux.h"
 #include "control.h"
@@ -141,6 +143,46 @@ static inline void omap_init_camera(void)
 }
 #endif
 
+struct omap_device_pm_latency omap_keyboard_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+int __init omap4_keyboard_init(struct omap4_keypad_platform_data
+                                                *sdp4430_keypad_data)
+{
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        struct omap4_keypad_platform_data *keypad_data;
+        unsigned int id = -1;
+        char *oh_name = "kbd";
+        char *name = "omap4-keypad";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
+
+        keypad_data = sdp4430_keypad_data;
+
+        od = omap_device_build(name, id, oh, keypad_data,
+                        sizeof(struct omap4_keypad_platform_data),
+                        omap_keyboard_latency,
+                        ARRAY_SIZE(omap_keyboard_latency), 0);
+
+        if (IS_ERR(od)) {
+                WARN(1, "Cant build omap_device for %s:%s.\n",
+                                                name, oh->name);
+                return PTR_ERR(od);
+        }
+
+        return 0;
+}
+
 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 
 #define MBOX_REG_SIZE   0x120
@@ -279,163 +321,55 @@ static inline void omap_init_audio(void) {}
 
 #include <plat/mcspi.h>
 
-#define OMAP2_MCSPI1_BASE               0x48098000
-#define OMAP2_MCSPI2_BASE               0x4809a000
-#define OMAP2_MCSPI3_BASE               0x480b8000
-#define OMAP2_MCSPI4_BASE               0x480ba000
-
-#define OMAP4_MCSPI1_BASE               0x48098100
-#define OMAP4_MCSPI2_BASE               0x4809a100
-#define OMAP4_MCSPI3_BASE               0x480b8100
-#define OMAP4_MCSPI4_BASE               0x480ba100
-
-static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
-        .num_cs         = 4,
-};
-
-static struct resource omap2_mcspi1_resources[] = {
-        {
-                .start          = OMAP2_MCSPI1_BASE,
-                .end            = OMAP2_MCSPI1_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap2_mcspi1 = {
-        .name           = "omap2_mcspi",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
-        .resource       = omap2_mcspi1_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi1_config,
-        },
-};
-
-static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
-        .num_cs         = 2,
-};
-
-static struct resource omap2_mcspi2_resources[] = {
-        {
-                .start          = OMAP2_MCSPI2_BASE,
-                .end            = OMAP2_MCSPI2_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap2_mcspi2 = {
-        .name           = "omap2_mcspi",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
-        .resource       = omap2_mcspi2_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi2_config,
-        },
-};
-
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
-        defined(CONFIG_ARCH_OMAP4)
-static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
-        .num_cs         = 2,
-};
-
-static struct resource omap2_mcspi3_resources[] = {
-        {
-        .start          = OMAP2_MCSPI3_BASE,
-        .end            = OMAP2_MCSPI3_BASE + 0xff,
-        .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap2_mcspi3 = {
-        .name           = "omap2_mcspi",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
-        .resource       = omap2_mcspi3_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi3_config,
-        },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
-        .num_cs         = 1,
-};
-
-static struct resource omap2_mcspi4_resources[] = {
-        {
-                .start          = OMAP2_MCSPI4_BASE,
-                .end            = OMAP2_MCSPI4_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap2_mcspi4 = {
-        .name           = "omap2_mcspi",
-        .id             = 4,
-        .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
-        .resource       = omap2_mcspi4_resources,
-        .dev            = {
-                .platform_data = &omap2_mcspi4_config,
+struct omap_device_pm_latency omap_mcspi_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
 };
-#endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static inline void omap4_mcspi_fixup(void)
-{
-        omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
-        omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
-        omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
-        omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
-        omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
-        omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
-        omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
-        omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
-}
-#else
-static inline void omap4_mcspi_fixup(void)
+static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
-}
-#endif
+        struct omap_device *od;
+        char *name = "omap2_mcspi";
+        struct omap2_mcspi_platform_config *pdata;
+        static int spi_num;
+        struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
+
+        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("Memory allocation for McSPI device failed\n");
+                return -ENOMEM;
+        }
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
-        defined(CONFIG_ARCH_OMAP4)
-static inline void omap2_mcspi3_init(void)
-{
-        platform_device_register(&omap2_mcspi3);
-}
-#else
-static inline void omap2_mcspi3_init(void)
-{
-}
-#endif
+        pdata->num_cs = mcspi_attrib->num_chipselect;
+        switch (oh->class->rev) {
+        case OMAP2_MCSPI_REV:
+        case OMAP3_MCSPI_REV:
+                        pdata->regs_offset = 0;
+                        break;
+        case OMAP4_MCSPI_REV:
+                        pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
+                        break;
+        default:
+                        pr_err("Invalid McSPI Revision value\n");
+                        return -EINVAL;
+        }
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static inline void omap2_mcspi4_init(void)
-{
-        platform_device_register(&omap2_mcspi4);
-}
-#else
-static inline void omap2_mcspi4_init(void)
-{
+        spi_num++;
+        od = omap_device_build(name, spi_num, oh, pdata,
+                                sizeof(*pdata), omap_mcspi_latency,
+                                ARRAY_SIZE(omap_mcspi_latency), 0);
+        WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
+                                name, oh->name);
+        kfree(pdata);
+        return 0;
 }
-#endif
 
 static void omap_init_mcspi(void)
 {
-        if (cpu_is_omap44xx())
-                omap4_mcspi_fixup();
-
-        platform_device_register(&omap2_mcspi1);
-        platform_device_register(&omap2_mcspi2);
-
-        if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
-                omap2_mcspi3_init();
-
-        if (cpu_is_omap343x() || cpu_is_omap44xx())
-                omap2_mcspi4_init();
+        omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
 }
 
 #else
@@ -895,7 +829,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
 #define OMAP_HDQ_BASE   0x480B2000
 #endif
 static struct resource omap_hdq_resources[] = {
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
new file mode 100644
index 000000000000..b18db84b0349
--- /dev/null
+++ b/arch/arm/mach-omap2/display.c
@@ -0,0 +1,45 @@
+/*
+ * OMAP2plus display device setup / initialization.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Senthilvadivu Guruswamy
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/display.h>
+
+static struct platform_device omap_display_device = {
+        .name          = "omapdss",
+        .id            = -1,
+        .dev            = {
+                .platform_data = NULL,
+        },
+};
+
+int __init omap_display_init(struct omap_dss_board_info *board_data)
+{
+        int r = 0;
+        omap_display_device.dev.platform_data = board_data;
+
+        r = platform_device_register(&omap_display_device);
+        if (r < 0)
+                printk(KERN_ERR "Unable to register OMAP-Display device\n");
+
+        return r;
+}
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 2bb29c160702..c1791d08ae56 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach/flash.h>
 
@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
         t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
 
         /* Configure GPMC */
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                                GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize);
+        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
+        else
+                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
         gpmc_cs_configure(gpmc_nand_data->cs,
                         GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a7d25fb00ef..d776ded9830d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-                                int sync_read, int sync_write, int hf)
+                                int sync_read, int sync_write, int hf, int vhf)
 {
         u32 reg;
 
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
                 reg |= ONENAND_SYS_CFG1_HF;
         else
                 reg &= ~ONENAND_SYS_CFG1_HF;
+        if (vhf)
+                reg |= ONENAND_SYS_CFG1_VHF;
+        else
+                reg &= ~ONENAND_SYS_CFG1_VHF;
         writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
+static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
+                                  void __iomem *onenand_base, bool *clk_dep)
+{
+        u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
+        int freq = 0;
+
+        if (cfg->get_freq) {
+                struct onenand_freq_info fi;
+
+                fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
+                fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
+                fi.ver_id = ver;
+                freq = cfg->get_freq(&fi, clk_dep);
+                if (freq)
+                        return freq;
+        }
+
+        switch ((ver >> 4) & 0xf) {
+        case 0:
+                freq = 40;
+                break;
+        case 1:
+                freq = 54;
+                break;
+        case 2:
+                freq = 66;
+                break;
+        case 3:
+                freq = 83;
+                break;
+        case 4:
+                freq = 104;
+                break;
+        default:
+                freq = 54;
+                break;
+        }
+
+        return freq;
+}
+
 static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                                         void __iomem *onenand_base,
-                                        int freq)
+                                        int *freq_ptr)
 {
         struct gpmc_timings t;
         const int t_cer  = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         const int t_wph  = 30;
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-        int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
+        int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
         int err, ticks_cez;
-        int cs = cfg->cs;
+        int cs = cfg->cs, freq = *freq_ptr;
         u32 reg;
+        bool clk_dep = false;
 
         if (cfg->flags & ONENAND_SYNC_READ) {
                 sync_read = 1;
@@ -148,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 err = omap2_onenand_set_async_mode(cs, onenand_base);
                 if (err)
                         return err;
-                reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
-                switch ((reg >> 4) & 0xf) {
-                case 0:
-                        freq = 40;
-                        break;
-                case 1:
-                        freq = 54;
-                        break;
-                case 2:
-                        freq = 66;
-                        break;
-                case 3:
-                        freq = 83;
-                        break;
-                case 4:
-                        freq = 104;
-                        break;
-                default:
-                        freq = 54;
-                        break;
-                }
+                freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
                 first_time = 1;
         }
 
@@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_avdh  = 2;
                 t_ach   = 3;
                 t_aavdh = 6;
-                t_rdyo  = 9;
+                t_rdyo  = 6;
                 break;
         case 83:
                 min_gpmc_clk_period = 12000; /* 83 MHz */
@@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         gpmc_clk_ns = gpmc_ticks_to_ns(div);
         if (gpmc_clk_ns < 15) /* >66Mhz */
                 hf = 1;
-        if (hf)
+        if (gpmc_clk_ns < 12) /* >83Mhz */
+                vhf = 1;
+        if (vhf)
+                latency = 8;
+        else if (hf)
                 latency = 6;
         else if (gpmc_clk_ns >= 25) /* 40 MHz*/
                 latency = 3;
         else
                 latency = 4;
 
+        if (clk_dep) {
+                if (gpmc_clk_ns < 12) { /* >83Mhz */
+                        t_ces   = 3;
+                        t_avds  = 4;
+                } else if (gpmc_clk_ns < 15) { /* >66Mhz */
+                        t_ces   = 5;
+                        t_avds  = 4;
+                } else if (gpmc_clk_ns < 25) { /* >40Mhz */
+                        t_ces   = 6;
+                        t_avds  = 5;
+                } else {
+                        t_ces   = 7;
+                        t_avds  = 7;
+                }
+        }
+
         if (first_time)
                 set_onenand_cfg(onenand_base, latency,
-                                        sync_read, sync_write, hf);
+                                        sync_read, sync_write, hf, vhf);
 
         if (div == 1) {
                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         /* Read */
         t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
         t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
+        /* Force at least 1 clk between AVD High to OE Low */
+        if (t.oe_on <= t.adv_rd_off)
+                t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
         t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
         t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
         t.cs_rd_off = t.oe_off;
@@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         if (err)
                 return err;
 
-        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
+        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+
+        *freq_ptr = freq;
 
         return 0;
 }
 
-static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
+static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
         struct device *dev = &gpmc_onenand_device.dev;
 
         /* Set sync timings in GPMC */
         if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
-                        freq) < 0) {
+                        freq_ptr) < 0) {
                 dev_err(dev, "Unable to set synchronous mode\n");
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1b7b3e7d02f7..674174365f78 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
  */
 #undef DEBUG
 
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/err.h>
@@ -22,6 +23,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
@@ -58,7 +60,6 @@
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 
-#define PREFETCH_FIFOTHRESHOLD  (0x40 << 8)
 #define CS_NUM_SHIFT            24
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
@@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
 
+static irqreturn_t gpmc_handle_irq(int irq, void *dev);
+
 static void gpmc_write_reg(int idx, u32 val)
 {
         __raw_writel(val, gpmc_base + idx);
@@ -497,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
         u32 regval = 0;
 
         switch (cmd) {
+        case GPMC_ENABLE_IRQ:
+                gpmc_write_reg(GPMC_IRQENABLE, wval);
+                break;
+
         case GPMC_SET_IRQ_STATUS:
                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
                 break;
@@ -598,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
 /**
  * gpmc_prefetch_enable - configures and starts prefetch transfer
  * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
  * @dma_mode: dma mode enable (1) or disable (0)
  * @u32_count: number of bytes to be transferred
  * @is_write: prefetch read(0) or write post(1) mode
  */
-int gpmc_prefetch_enable(int cs, int dma_mode,
+int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                 unsigned int u32_count, int is_write)
 {
 
-        if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
+        if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
+                pr_err("gpmc: fifo threshold is not supported\n");
+                return -1;
+        } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
                 /* Set the amount of bytes to be prefetched */
                 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 
@@ -614,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
                  * enable the engine. Set which cs is has requested for.
                  */
                 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
-                                        PREFETCH_FIFOTHRESHOLD |
+                                        PREFETCH_FIFOTHRESHOLD(fifo_th) |
                                         ENABLE_PREFETCH |
                                         (dma_mode << DMA_MPU_MODE) |
                                         (0x1 & is_write)));
@@ -678,9 +689,10 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-void __init gpmc_init(void)
+static int __init gpmc_init(void)
 {
-        u32 l;
+        u32 l, irq;
+        int cs, ret = -EINVAL;
         char *ck = NULL;
 
         if (cpu_is_omap24xx()) {
@@ -698,7 +710,7 @@ void __init gpmc_init(void)
         }
 
         if (WARN_ON(!ck))
-                return;
+                return ret;
 
         gpmc_l3_clk = clk_get(NULL, ck);
         if (IS_ERR(gpmc_l3_clk)) {
@@ -723,6 +735,36 @@ void __init gpmc_init(void)
         l |= (0x02 << 3) | (1 << 0);
         gpmc_write_reg(GPMC_SYSCONFIG, l);
         gpmc_mem_init();
+
+        /* initalize the irq_chained */
+        irq = OMAP_GPMC_IRQ_BASE;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                set_irq_handler(irq, handle_simple_irq);
+                set_irq_flags(irq, IRQF_VALID);
+                irq++;
+        }
+
+        ret = request_irq(INT_34XX_GPMC_IRQ,
+                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
+        if (ret)
+                pr_err("gpmc: irq-%d could not claim: err %d\n",
+                                                INT_34XX_GPMC_IRQ, ret);
+        return ret;
+}
+postcore_initcall(gpmc_init);
+
+static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+{
+        u8 cs;
+
+        if (irq != INT_34XX_GPMC_IRQ)
+                return IRQ_HANDLED;
+        /* check cs to invoke the irq */
+        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
+        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
+                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+
+        return IRQ_HANDLED;
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 34272e4863fd..5496bc7d40ad 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -350,6 +350,11 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                                 mmc->slots[0].after_set_reg = NULL;
                         }
                         break;
+                case 4:
+                case 5:
+                        mmc->slots[0].before_set_reg = NULL;
+                        mmc->slots[0].after_set_reg = NULL;
+                        break;
                 default:
                         pr_err("MMC%d configuration not supported!\n", c->mmc);
                         kfree(mmc);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
new file mode 100644
index 000000000000..06d4a80660a5
--- /dev/null
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -0,0 +1,63 @@
+/*
+ * OMAP hardware spinlock device initialization
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Contact: Simon Que <sque@ti.com>
+ *          Hari Kanigeri <h-kanigeri2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+struct omap_device_pm_latency omap_spinlock_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        }
+};
+
+int __init hwspinlocks_init(void)
+{
+        int retval = 0;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        const char *oh_name = "spinlock";
+        const char *dev_name = "omap_hwspinlock";
+
+        /*
+         * Hwmod lookup will fail in case our platform doesn't support the
+         * hardware spinlock module, so it is safe to run this initcall
+         * on all omaps
+         */
+        oh = omap_hwmod_lookup(oh_name);
+        if (oh == NULL)
+                return -EINVAL;
+
+        od = omap_device_build(dev_name, 0, oh, NULL, 0,
+                                omap_spinlock_latency,
+                                ARRAY_SIZE(omap_spinlock_latency), false);
+        if (IS_ERR(od)) {
+                pr_err("Can't build omap_device for %s:%s\n", dev_name,
+                                                                oh_name);
+                retval = PTR_ERR(od);
+        }
+
+        return retval;
+}
+/* early board code might need to reserve specific hwspinlock instances */
+postcore_initcall(hwspinlocks_init);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5f9086c65e48..3168b17bc264 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
  * Copyright (C) 2005 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
  *
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-11 Texas Instruments
  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -191,12 +191,19 @@ static void __init omap3_check_features(void)
         if (!cpu_is_omap3505() && !cpu_is_omap3517())
                 omap3_features |= OMAP3_HAS_IO_WAKEUP;
 
+        omap3_features |= OMAP3_HAS_SDRC;
+
         /*
          * TODO: Get additional info (where applicable)
          *       e.g. Size of L2 cache.
          */
 }
 
+static void __init ti816x_check_features(void)
+{
+        omap3_features = OMAP3_HAS_NEON;
+}
+
 static void __init omap3_check_revision(void)
 {
         u32 cpuid, idcode;
@@ -287,6 +294,20 @@ static void __init omap3_check_revision(void)
                         omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
                 }
                 break;
+        case 0xb81e:
+                omap_chip.oc = CHIP_IS_TI816X;
+
+                switch (rev) {
+                case 0:
+                        omap_revision = TI8168_REV_ES1_0;
+                        break;
+                case 1:
+                        omap_revision = TI8168_REV_ES1_1;
+                        break;
+                default:
+                        omap_revision =  TI8168_REV_ES1_1;
+                }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default*/
                 omap_revision =  OMAP3630_REV_ES1_2;
@@ -307,7 +328,7 @@ static void __init omap4_check_revision(void)
          */
         idcode = read_tap_reg(OMAP_TAP_IDCODE);
         hawkeye = (idcode >> 12) & 0xffff;
-        rev = (idcode >> 28) & 0xff;
+        rev = (idcode >> 28) & 0xf;
 
         /*
          * Few initial ES2.0 samples IDCODE is same as ES1.0
@@ -326,22 +347,31 @@ static void __init omap4_check_revision(void)
                         omap_chip.oc |= CHIP_IS_OMAP4430ES1;
                         break;
                 case 1:
+                default:
                         omap_revision = OMAP4430_REV_ES2_0;
                         omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                }
+                break;
+        case 0xb95c:
+                switch (rev) {
+                case 3:
+                        omap_revision = OMAP4430_REV_ES2_1;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
                         break;
+                case 4:
                 default:
-                        omap_revision = OMAP4430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
-        }
-        break;
+                        omap_revision = OMAP4430_REV_ES2_2;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
+                }
+                break;
         default:
-                /* Unknown default to latest silicon rev as default*/
-                omap_revision = OMAP4430_REV_ES2_0;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                /* Unknown default to latest silicon rev as default */
+                omap_revision = OMAP4430_REV_ES2_2;
+                omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
         }
 
-        pr_info("OMAP%04x ES%d.0\n",
-                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
+        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
+                ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
 #define OMAP3_SHOW_FEATURE(feat)                \
@@ -372,6 +402,8 @@ static void __init omap3_cpuinfo(void)
                         /* Already set in omap3_check_revision() */
                         strcpy(cpu_name, "AM3505");
                 }
+        } else if (cpu_is_ti816x()) {
+                strcpy(cpu_name, "TI816X");
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                 strcpy(cpu_name, "OMAP3430/3530");
@@ -386,7 +418,7 @@ static void __init omap3_cpuinfo(void)
                 strcpy(cpu_name, "OMAP3503");
         }
 
-        if (cpu_is_omap3630()) {
+        if (cpu_is_omap3630() || cpu_is_ti816x()) {
                 switch (rev) {
                 case OMAP_REVBITS_00:
                         strcpy(cpu_rev, "1.0");
@@ -462,7 +494,13 @@ void __init omap2_check_revision(void)
                 omap24xx_check_revision();
         } else if (cpu_is_omap34xx()) {
                 omap3_check_revision();
-                omap3_check_features();
+
+                /* TI816X doesn't have feature register */
+                if (!cpu_is_ti816x())
+                        omap3_check_features();
+                else
+                        ti816x_check_features();
+
                 omap3_cpuinfo();
                 return;
         } else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 6a4d4136002e..e1b0f17b0927 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -69,6 +69,12 @@ omap_uart_lsr:	.word	0
                 beq     34f                     @ configure OMAP3UART4
                 cmp     \rp, #OMAP4UART4        @ only on 44xx
                 beq     44f                     @ configure OMAP4UART4
+                cmp     \rp, #TI816XUART1       @ ti816x UART offsets different
+                beq     81f                     @ configure UART1
+                cmp     \rp, #TI816XUART2       @ ti816x UART offsets different
+                beq     82f                     @ configure UART2
+                cmp     \rp, #TI816XUART3       @ ti816x UART offsets different
+                beq     83f                     @ configure UART3
                 cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
 
@@ -91,6 +97,12 @@ omap_uart_lsr:	.word	0
                 b       98f
 44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                 b       98f
+81:             mov     \rp, #UART_OFFSET(TI816X_UART1_BASE)
+                b       98f
+82:             mov     \rp, #UART_OFFSET(TI816X_UART2_BASE)
+                b       98f
+83:             mov     \rp, #UART_OFFSET(TI816X_UART3_BASE)
+                b       98f
 95:             ldr     \rp, =ZOOM_UART_BASE
                 mrc     p15, 0, \rv, c1, c0
                 tst     \rv, #1                 @ MMU enabled?
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 81985a665cb3..a48690b90990 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -61,6 +61,14 @@
                 bne     9998f
                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
                 cmp     \irqnr, #0x0
+                bne     9998f
+
+                /*
+                 * ti816x has additional IRQ pending register. Checking this
+                 * register on omap2 & omap3 has no effect (read as 0).
+                 */
+                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+                cmp     \irqnr, #0x0
 9998:
                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
@@ -133,6 +141,11 @@
                 bne     9999f
                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
                 cmp     \irqnr, #0x0
+#ifdef CONFIG_SOC_OMAPTI816X
+                bne     9999f
+                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+                cmp     \irqnr, #0x0
+#endif
 9999:
                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c2032041d26f..657f3c84687c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,7 +30,6 @@
 
 #include <plat/sram.h>
 #include <plat/sdrc.h>
-#include <plat/gpmc.h>
 #include <plat/serial.h>
 
 #include "clock2xxx.h"
@@ -66,7 +65,7 @@ static struct map_desc omap24xx_io_desc[] __initdata = {
         },
 };
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static struct map_desc omap242x_io_desc[] __initdata = {
         {
                 .virtual        = DSP_MEM_2420_VIRT,
@@ -90,7 +89,7 @@ static struct map_desc omap242x_io_desc[] __initdata = {
 
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static struct map_desc omap243x_io_desc[] __initdata = {
         {
                 .virtual        = L4_WK_243X_VIRT,
@@ -175,6 +174,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 #endif
 };
 #endif
+
+#ifdef CONFIG_SOC_OMAPTI816X
+static struct map_desc omapti816x_io_desc[] __initdata = {
+        {
+                .virtual        = L4_34XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
+                .length         = L4_34XX_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+#endif
+
 #ifdef  CONFIG_ARCH_OMAP4
 static struct map_desc omap44xx_io_desc[] __initdata = {
         {
@@ -241,7 +252,7 @@ static void __init _omap2_map_common_io(void)
         omap_sram_init();
 }
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 void __init omap242x_map_common_io(void)
 {
         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
@@ -250,7 +261,7 @@ void __init omap242x_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 void __init omap243x_map_common_io(void)
 {
         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
@@ -267,6 +278,14 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPTI816X
+void __init omapti816x_map_common_io(void)
+{
+        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+        _omap2_map_common_io();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap44xx_map_common_io(void)
 {
@@ -398,15 +417,10 @@ void __init omap2_init_common_infrastructure(void)
 void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1)
 {
-        omap_serial_early_init();
-
-        omap_hwmod_late_init();
-
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+        if (cpu_is_omap24xx() || omap3_has_sdrc()) {
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
         }
-        gpmc_init();
 
         omap_irq_base_init();
 }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 23049c487c47..bc524b94fd59 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -61,8 +61,6 @@ struct omap3_intc_regs {
         u32 mir[INTCPS_NR_MIR_REGS];
 };
 
-static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
-
 /* INTC bank register get/set */
 
 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@@ -110,7 +108,7 @@ static void omap_mask_irq(struct irq_data *d)
         unsigned int irq = d->irq;
         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
                 int spurious = 0;
 
                 /*
@@ -205,6 +203,9 @@ void __init omap_init_irq(void)
 
                 BUG_ON(!base);
 
+                if (cpu_is_ti816x())
+                        bank->nr_irqs = 128;
+
                 /* Static mapping, never released */
                 bank->base_reg = ioremap(base, SZ_4K);
                 if (!bank->base_reg) {
@@ -229,6 +230,8 @@ void __init omap_init_irq(void)
 }
 
 #ifdef CONFIG_ARCH_OMAP3
+static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
+
 void omap_intc_save_context(void)
 {
         int ind = 0, i = 0;
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 0a585dfa9874..537d3484b475 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -310,7 +310,7 @@ struct omap_mbox mbox_dsp_info = {
 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 /* IVA */
 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
         .tx_fifo = {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index f9c9df5b5ff1..0526b758bdcc 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -104,7 +104,7 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
 
 /* Platform data */
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
         {
                 .phys_base      = OMAP24XX_MCBSP1_BASE,
@@ -129,7 +129,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
 #define OMAP2420_MCBSP_REG_NUM          0
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
         {
                 .phys_base      = OMAP24XX_MCBSP1_BASE,
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index e282e35769fd..f76f133780c8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod implementation for OMAP2/3/4
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Paul Walmsley, Benoît Cousson, Kevin Hilman
  *
@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
-/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
-static u8 inited;
-
 
 /* Private functions */
 
@@ -904,18 +901,16 @@ static struct omap_hwmod *_lookup(const char *name)
  * @oh: struct omap_hwmod *
  * @data: not used; pass NULL
  *
- * Called by omap_hwmod_late_init() (after omap2_clk_init()).
- * Resolves all clock names embedded in the hwmod.  Returns -EINVAL if
- * the omap_hwmod has not yet been registered or if the clocks have
- * already been initialized, 0 on success, or a non-zero error on
- * failure.
+ * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
+ * Resolves all clock names embedded in the hwmod.  Returns 0 on
+ * success, or a negative error code on failure.
  */
 static int _init_clocks(struct omap_hwmod *oh, void *data)
 {
         int ret = 0;
 
-        if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED))
-                return -EINVAL;
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
+                return 0;
 
         pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
 
@@ -1354,14 +1349,16 @@ static int _shutdown(struct omap_hwmod *oh)
  * @oh: struct omap_hwmod *
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Returns -EINVAL if the hwmod is in the
- * wrong state or returns 0.
+ * OCP_SYSCONFIG register.  Returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {
         int i, r;
         u8 postsetup_state;
 
+        if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+                return 0;
+
         /* Set iclk autoidle mode */
         if (oh->slaves_cnt > 0) {
                 for (i = 0; i < oh->slaves_cnt; i++) {
@@ -1455,7 +1452,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
  */
 static int __init _register(struct omap_hwmod *oh)
 {
-        int ret, ms_id;
+        int ms_id;
 
         if (!oh || !oh->name || !oh->class || !oh->class->name ||
             (oh->_state != _HWMOD_STATE_UNKNOWN))
@@ -1467,12 +1464,10 @@ static int __init _register(struct omap_hwmod *oh)
                 return -EEXIST;
 
         ms_id = _find_mpu_port_index(oh);
-        if (!IS_ERR_VALUE(ms_id)) {
+        if (!IS_ERR_VALUE(ms_id))
                 oh->_mpu_port_index = ms_id;
-                oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-        } else {
+        else
                 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
-        }
 
         list_add_tail(&oh->node, &omap_hwmod_list);
 
@@ -1480,9 +1475,14 @@ static int __init _register(struct omap_hwmod *oh)
 
         oh->_state = _HWMOD_STATE_REGISTERED;
 
-        ret = 0;
+        /*
+         * XXX Rather than doing a strcmp(), this should test a flag
+         * set in the hwmod data, inserted by the autogenerator code.
+         */
+        if (!strcmp(oh->name, MPU_INITIATOR_NAME))
+                mpu_oh = oh;
 
-        return ret;
+        return 0;
 }
 
 
@@ -1585,65 +1585,132 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
         return ret;
 }
 
-
 /**
- * omap_hwmod_init - init omap_hwmod code and register hwmods
+ * omap_hwmod_register - register an array of hwmods
  * @ohs: pointer to an array of omap_hwmods to register
  *
  * Intended to be called early in boot before the clock framework is
  * initialized.  If @ohs is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip.  Returns -EINVAL if
- * omap_hwmod_init() has already been called or 0 otherwise.
+ * listed in @ohs that are valid for this chip.  Returns 0.
+ */
+int __init omap_hwmod_register(struct omap_hwmod **ohs)
+{
+        int r, i;
+
+        if (!ohs)
+                return 0;
+
+        i = 0;
+        do {
+                if (!omap_chip_is(ohs[i]->omap_chip))
+                        continue;
+
+                r = _register(ohs[i]);
+                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
+                     r);
+        } while (ohs[++i]);
+
+        return 0;
+}
+
+/*
+ * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ *
+ * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
+ * Assumes the caller takes care of locking if needed.
  */
-int __init omap_hwmod_init(struct omap_hwmod **ohs)
+static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+{
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
+                return 0;
+
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+        if (!oh->_mpu_rt_va)
+                pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
+                                __func__, oh->name);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_setup_one - set up a single hwmod
+ * @oh_name: const char * name of the already-registered hwmod to set up
+ *
+ * Must be called after omap2_clk_init().  Resolves the struct clk
+ * names to struct clk pointers for each registered omap_hwmod.  Also
+ * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
+ * success.
+ */
+int __init omap_hwmod_setup_one(const char *oh_name)
 {
         struct omap_hwmod *oh;
         int r;
 
-        if (inited)
+        pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
+
+        if (!mpu_oh) {
+                pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
+                       oh_name, MPU_INITIATOR_NAME);
                 return -EINVAL;
+        }
 
-        inited = 1;
+        oh = _lookup(oh_name);
+        if (!oh) {
+                WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
+                return -EINVAL;
+        }
 
-        if (!ohs)
-                return 0;
+        if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
 
-        oh = *ohs;
-        while (oh) {
-                if (omap_chip_is(oh->omap_chip)) {
-                        r = _register(oh);
-                        WARN(r, "omap_hwmod: %s: _register returned "
-                             "%d\n", oh->name, r);
-                }
-                oh = *++ohs;
+        r = _populate_mpu_rt_base(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
+                return -EINVAL;
+        }
+
+        r = _init_clocks(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
+                return -EINVAL;
         }
 
+        _setup(oh, NULL);
+
         return 0;
 }
 
 /**
- * omap_hwmod_late_init - do some post-clock framework initialization
+ * omap_hwmod_setup - do some post-clock framework initialization
  *
  * Must be called after omap2_clk_init().  Resolves the struct clk names
  * to struct clk pointers for each registered omap_hwmod.  Also calls
- * _setup() on each hwmod.  Returns 0.
+ * _setup() on each hwmod.  Returns 0 upon success.
  */
-int omap_hwmod_late_init(void)
+static int __init omap_hwmod_setup_all(void)
 {
         int r;
 
-        /* XXX check return value */
-        r = omap_hwmod_for_each(_init_clocks, NULL);
-        WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
+        if (!mpu_oh) {
+                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+                       __func__, MPU_INITIATOR_NAME);
+                return -EINVAL;
+        }
+
+        r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
 
-        mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
-        WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
-             MPU_INITIATOR_NAME);
+        r = omap_hwmod_for_each(_init_clocks, NULL);
+        WARN(IS_ERR_VALUE(r),
+             "omap_hwmod: %s: _init_clocks failed\n", __func__);
 
         omap_hwmod_for_each(_setup, NULL);
 
         return 0;
 }
+core_initcall(omap_hwmod_setup_all);
 
 /**
  * omap_hwmod_enable - enable an omap_hwmod
@@ -2162,11 +2229,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
  * @oh: struct omap_hwmod *
  * @state: state that _setup() should leave the hwmod in
  *
- * Sets the hwmod state that @oh will enter at the end of _setup() (called by
- * omap_hwmod_late_init()).  Only valid to call between calls to
- * omap_hwmod_init() and omap_hwmod_late_init().  Returns 0 upon success or
- * -EINVAL if there is a problem with the arguments or if the hwmod is
- * in the wrong state.
+ * Sets the hwmod state that @oh will enter at the end of _setup()
+ * (called by omap_hwmod_setup_*()).  Only valid to call between
+ * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
+ * 0 upon success or -EINVAL if there is a problem with the arguments
+ * or if the hwmod is in the wrong state.
  */
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
 {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b85c630b64d6..e58621aa9b34 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -18,6 +18,10 @@
 #include <plat/serial.h>
 #include <plat/i2c.h>
 #include <plat/gpio.h>
+#include <plat/mcspi.h>
+#include <plat/dmtimer.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -38,12 +42,18 @@ static struct omap_hwmod omap2420_mpu_hwmod;
 static struct omap_hwmod omap2420_iva_hwmod;
 static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
+static struct omap_hwmod omap2420_dss_core_hwmod;
+static struct omap_hwmod omap2420_dss_dispc_hwmod;
+static struct omap_hwmod omap2420_dss_rfbi_hwmod;
+static struct omap_hwmod omap2420_dss_venc_hwmod;
 static struct omap_hwmod omap2420_wd_timer2_hwmod;
 static struct omap_hwmod omap2420_gpio1_hwmod;
 static struct omap_hwmod omap2420_gpio2_hwmod;
 static struct omap_hwmod omap2420_gpio3_hwmod;
 static struct omap_hwmod omap2420_gpio4_hwmod;
 static struct omap_hwmod omap2420_dma_system_hwmod;
+static struct omap_hwmod omap2420_mcspi1_hwmod;
+static struct omap_hwmod omap2420_mcspi2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -64,6 +74,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
         &omap2420_mpu__l3_main,
 };
 
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
+        .master         = &omap2420_dss_core_hwmod,
+        .slave          = &omap2420_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Master interfaces on the L3 interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
         &omap2420_l3_main__l4_core,
@@ -88,6 +111,42 @@ static struct omap_hwmod omap2420_uart3_hwmod;
 static struct omap_hwmod omap2420_i2c1_hwmod;
 static struct omap_hwmod omap2420_i2c2_hwmod;
 
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480980ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcspi1_hwmod,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2420_mcspi1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcspi1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcspi2_hwmod,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2420_mcspi2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcspi2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
         .master = &omap2420_l4_core_hwmod,
@@ -279,6 +338,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap2420_timer_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2420_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48028000,
+                .pa_end         = 0x48028000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2420_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+        &omap2420_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2420_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2420_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2420_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2420_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+        &omap2420_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2420_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2420_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2420_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2420_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
+        &omap2420_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2420_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2420_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2420_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2420_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+        &omap2420_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2420_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2420_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2420_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2420_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+        &omap2420_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2420_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2420_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+
+/* timer6 */
+static struct omap_hwmod omap2420_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2420_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
+        &omap2420_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2420_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2420_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2420_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2420_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
+        &omap2420_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2420_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2420_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2420_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2420_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+        &omap2420_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2420_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2420_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2420_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2420_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
+        &omap2420_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2420_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2420_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2420_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2420_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+        &omap2420_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2420_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2420_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2420_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2420_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+        &omap2420_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2420_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2420_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2420_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2420_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
+        &omap2420_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2420_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2420_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
         {
@@ -470,6 +1148,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_dss_hwmod_class = {
+        .name = "dss",
+        .sysc = &omap2420_dss_sysc,
+};
+
+/* dss */
+static struct omap_hwmod_irq_info omap2420_dss_irqs[] = {
+        { .irq = 25 },
+};
+
+static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
+        &omap2420_dss__l3,
+};
+
+static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x480503FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2420_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
+        &omap2420_l4_core__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "tv_clk", .clk = "dss_54m_fck" },
+        { .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+static struct omap_hwmod omap2420_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2420_dss_hwmod_class,
+        .main_clk       = "dss1_fck", /* instead of dss_fck */
+        .mpu_irqs       = omap2420_dss_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dss_irqs),
+        .sdma_reqs      = omap2420_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap2420_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
+        .masters        = omap2420_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
+        .name = "dispc",
+        .sysc = &omap2420_dispc_sysc,
+};
+
+static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x480507FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2420_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_dispc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
+        &omap2420_l4_core__dss_dispc,
+};
+
+static struct omap_hwmod omap2420_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap2420_dispc_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
+        .name = "rfbi",
+        .sysc = &omap2420_rfbi_sysc,
+};
+
+static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050BFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2420_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
+        &omap2420_l4_core__dss_rfbi,
+};
+
+static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2420_rfbi_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2420_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap2420_venc_hwmod_class = {
+        .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050FFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dss_venc_hwmod,
+        .clk            = "dss_54m_fck",
+        .addr           = omap2420_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dss_venc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
+        &omap2420_l4_core__dss_venc,
+};
+
+static struct omap_hwmod omap2420_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap2420_venc_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2420_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 /* I2C common */
 static struct omap_hwmod_class_sysconfig i2c_sysc = {
         .rev_offs       = 0x00,
@@ -864,16 +1827,149 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mcspi_class = {
+        .name = "mcspi",
+        .sysc = &omap2420_mcspi_sysc,
+        .rev = OMAP2_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
+        { .irq = 65 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
+        &omap2420_l4_core__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap2420_mcspi1_hwmod = {
+        .name           = "mcspi1_hwmod",
+        .mpu_irqs       = omap2420_mcspi1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
+        .sdma_reqs      = omap2420_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
+        .class          = &omap2420_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
+        { .irq = 66 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
+        &omap2420_l4_core__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap2420_mcspi2_hwmod = {
+        .name           = "mcspi2_hwmod",
+        .mpu_irqs       = omap2420_mcspi2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
+        .sdma_reqs      = omap2420_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
+        .class          = &omap2420_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_l3_main_hwmod,
         &omap2420_l4_core_hwmod,
         &omap2420_l4_wkup_hwmod,
         &omap2420_mpu_hwmod,
         &omap2420_iva_hwmod,
+
+        &omap2420_timer1_hwmod,
+        &omap2420_timer2_hwmod,
+        &omap2420_timer3_hwmod,
+        &omap2420_timer4_hwmod,
+        &omap2420_timer5_hwmod,
+        &omap2420_timer6_hwmod,
+        &omap2420_timer7_hwmod,
+        &omap2420_timer8_hwmod,
+        &omap2420_timer9_hwmod,
+        &omap2420_timer10_hwmod,
+        &omap2420_timer11_hwmod,
+        &omap2420_timer12_hwmod,
+
         &omap2420_wd_timer2_hwmod,
         &omap2420_uart1_hwmod,
         &omap2420_uart2_hwmod,
         &omap2420_uart3_hwmod,
+        /* dss class */
+        &omap2420_dss_core_hwmod,
+        &omap2420_dss_dispc_hwmod,
+        &omap2420_dss_rfbi_hwmod,
+        &omap2420_dss_venc_hwmod,
+        /* i2c class */
         &omap2420_i2c1_hwmod,
         &omap2420_i2c2_hwmod,
 
@@ -885,10 +1981,14 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 
         /* dma_system class*/
         &omap2420_dma_system_hwmod,
+
+        /* mcspi class */
+        &omap2420_mcspi1_hwmod,
+        &omap2420_mcspi2_hwmod,
         NULL,
 };
 
 int __init omap2420_hwmod_init(void)
 {
-        return omap_hwmod_init(omap2420_hwmods);
+        return omap_hwmod_register(omap2420_hwmods);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8ecfbcde13ba..b46a54ce1a41 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,6 +18,9 @@
 #include <plat/serial.h>
 #include <plat/i2c.h>
 #include <plat/gpio.h>
+#include <plat/mcspi.h>
+#include <plat/dmtimer.h>
+#include <plat/l3_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -38,6 +41,10 @@ static struct omap_hwmod omap2430_mpu_hwmod;
 static struct omap_hwmod omap2430_iva_hwmod;
 static struct omap_hwmod omap2430_l3_main_hwmod;
 static struct omap_hwmod omap2430_l4_core_hwmod;
+static struct omap_hwmod omap2430_dss_core_hwmod;
+static struct omap_hwmod omap2430_dss_dispc_hwmod;
+static struct omap_hwmod omap2430_dss_rfbi_hwmod;
+static struct omap_hwmod omap2430_dss_venc_hwmod;
 static struct omap_hwmod omap2430_wd_timer2_hwmod;
 static struct omap_hwmod omap2430_gpio1_hwmod;
 static struct omap_hwmod omap2430_gpio2_hwmod;
@@ -45,6 +52,9 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
 static struct omap_hwmod omap2430_gpio4_hwmod;
 static struct omap_hwmod omap2430_gpio5_hwmod;
 static struct omap_hwmod omap2430_dma_system_hwmod;
+static struct omap_hwmod omap2430_mcspi1_hwmod;
+static struct omap_hwmod omap2430_mcspi2_hwmod;
+static struct omap_hwmod omap2430_mcspi3_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -65,6 +75,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
         &omap2430_mpu__l3_main,
 };
 
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
+        .master         = &omap2430_dss_core_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Master interfaces on the L3 interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
         &omap2430_l3_main__l4_core,
@@ -89,6 +112,16 @@ static struct omap_hwmod omap2430_uart3_hwmod;
 static struct omap_hwmod omap2430_i2c1_hwmod;
 static struct omap_hwmod omap2430_i2c2_hwmod;
 
+static struct omap_hwmod omap2430_usbhsotg_hwmod;
+
+/* l3_core -> usbhsotg  interface */
+static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
+        .master         = &omap2430_usbhsotg_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU,
+};
+
 /* I2C IP block address space length (in bytes) */
 #define OMAP2_I2C_AS_LEN                128
 
@@ -189,6 +222,35 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/*
+* usbhsotg interface data
+*/
+static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP243X_HS_BASE,
+                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/*  l4_core ->usbhsotg  interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_usbhsotg_hwmod,
+        .clk            = "usb_l4_ick",
+        .addr           = omap2430_usbhsotg_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
+        &omap2430_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
+        &omap2430_l4_core__usbhsotg,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
         &omap2430_l3_main__l4_core,
@@ -223,6 +285,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 };
 
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480980ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcspi1_hwmod,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2430_mcspi1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcspi2_hwmod,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2430_mcspi2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b80ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcspi3_hwmod,
+        .clk            = "mcspi3_ick",
+        .addr           = omap2430_mcspi3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* L4 WKUP */
 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
         .name           = "l4_wkup",
@@ -278,6 +394,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap2430_timer_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2430_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+        {
+                .pa_start       = 0x49018000,
+                .pa_end         = 0x49018000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2430_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+        &omap2430_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2430_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2430_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2430_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2430_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+        &omap2430_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2430_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2430_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2430_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2430_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
+        &omap2430_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2430_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2430_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2430_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2430_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
+        &omap2430_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2430_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2430_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2430_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2430_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
+        &omap2430_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2430_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2430_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap2430_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2430_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
+        &omap2430_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2430_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2430_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2430_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2430_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
+        &omap2430_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2430_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2430_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2430_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2430_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
+        &omap2430_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2430_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2430_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2430_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2430_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
+        &omap2430_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2430_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2430_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2430_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2430_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
+        &omap2430_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2430_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2430_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2430_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2430_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
+        &omap2430_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2430_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2430_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2430_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2430_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
+        &omap2430_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2430_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2430_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
         {
@@ -469,6 +1203,266 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_dss_hwmod_class = {
+        .name = "dss",
+        .sysc = &omap2430_dss_sysc,
+};
+
+/* dss */
+static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
+        { .irq = 25 },
+};
+static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
+        &omap2430_dss__l3,
+};
+
+static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x480503FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2430_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
+        &omap2430_l4_core__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "tv_clk", .clk = "dss_54m_fck" },
+        { .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+static struct omap_hwmod omap2430_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2430_dss_hwmod_class,
+        .main_clk       = "dss1_fck", /* instead of dss_fck */
+        .mpu_irqs       = omap2430_dss_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dss_irqs),
+        .sdma_reqs      = omap2430_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap2430_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
+        .masters        = omap2430_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
+        .name = "dispc",
+        .sysc = &omap2430_dispc_sysc,
+};
+
+static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x480507FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2430_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
+        &omap2430_l4_core__dss_dispc,
+};
+
+static struct omap_hwmod omap2430_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap2430_dispc_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
+        .name = "rfbi",
+        .sysc = &omap2430_rfbi_sysc,
+};
+
+static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050BFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2430_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
+        &omap2430_l4_core__dss_rfbi,
+};
+
+static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2430_rfbi_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2430_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap2430_venc_hwmod_class = {
+        .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050FFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dss_venc_hwmod,
+        .clk            = "dss_54m_fck",
+        .addr           = omap2430_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
+        &omap2430_l4_core__dss_venc,
+};
+
+static struct omap_hwmod omap2430_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap2430_venc_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .slaves         = omap2430_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 /* I2C common */
 static struct omap_hwmod_class_sysconfig i2c_sysc = {
         .rev_offs       = 0x00,
@@ -919,16 +1913,250 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mcspi_class = {
+        .name = "mcspi",
+        .sysc = &omap2430_mcspi_sysc,
+        .rev = OMAP2_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
+        { .irq = 65 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
+        &omap2430_l4_core__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap2430_mcspi1_hwmod = {
+        .name           = "mcspi1_hwmod",
+        .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
+        .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
+        .class          = &omap2430_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
+        { .irq = 66 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
+        &omap2430_l4_core__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap2430_mcspi2_hwmod = {
+        .name           = "mcspi2_hwmod",
+        .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
+        .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
+        .class          = &omap2430_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
+        { .irq = 91 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
+        { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
+        { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
+        { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
+        &omap2430_l4_core__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap2430_mcspi3_hwmod = {
+        .name           = "mcspi3_hwmod",
+        .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
+        .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
+        .main_clk       = "mcspi3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcspi3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
+        .class          = &omap2430_mcspi_class,
+        .dev_attr       = &omap_mcspi3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * usbhsotg
+ */
+static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
+        .rev_offs       = 0x0400,
+        .sysc_offs      = 0x0404,
+        .syss_offs      = 0x0408,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class usbotg_class = {
+        .name = "usbotg",
+        .sysc = &omap2430_usbhsotg_sysc,
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
+
+        { .name = "mc", .irq = 92 },
+        { .name = "dma", .irq = 93 },
+};
+
+static struct omap_hwmod omap2430_usbhsotg_hwmod = {
+        .name           = "usb_otg_hs",
+        .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
+        .main_clk       = "usbhs_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_USBHS_MASK,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
+                },
+        },
+        .masters        = omap2430_usbhsotg_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
+        .slaves         = omap2430_usbhsotg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
+        .class          = &usbotg_class,
+        /*
+         * Erratum ID: i479  idle_req / idle_ack mechanism potentially
+         * broken when autoidle is enabled
+         * workaround is to disable the autoidle bit at module level.
+         */
+        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+                                | HWMOD_SWSUP_MSTANDBY,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
         &omap2430_l4_core_hwmod,
         &omap2430_l4_wkup_hwmod,
         &omap2430_mpu_hwmod,
         &omap2430_iva_hwmod,
+
+        &omap2430_timer1_hwmod,
+        &omap2430_timer2_hwmod,
+        &omap2430_timer3_hwmod,
+        &omap2430_timer4_hwmod,
+        &omap2430_timer5_hwmod,
+        &omap2430_timer6_hwmod,
+        &omap2430_timer7_hwmod,
+        &omap2430_timer8_hwmod,
+        &omap2430_timer9_hwmod,
+        &omap2430_timer10_hwmod,
+        &omap2430_timer11_hwmod,
+        &omap2430_timer12_hwmod,
+
         &omap2430_wd_timer2_hwmod,
         &omap2430_uart1_hwmod,
         &omap2430_uart2_hwmod,
         &omap2430_uart3_hwmod,
+        /* dss class */
+        &omap2430_dss_core_hwmod,
+        &omap2430_dss_dispc_hwmod,
+        &omap2430_dss_rfbi_hwmod,
+        &omap2430_dss_venc_hwmod,
+        /* i2c class */
         &omap2430_i2c1_hwmod,
         &omap2430_i2c2_hwmod,
 
@@ -941,10 +2169,19 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 
         /* dma_system class*/
         &omap2430_dma_system_hwmod,
+
+        /* mcspi class */
+        &omap2430_mcspi1_hwmod,
+        &omap2430_mcspi2_hwmod,
+        &omap2430_mcspi3_hwmod,
+
+        /* usbotg class*/
+        &omap2430_usbhsotg_hwmod,
+
         NULL,
 };
 
 int __init omap2430_hwmod_init(void)
 {
-        return omap_hwmod_init(omap2430_hwmods);
+        return omap_hwmod_register(omap2430_hwmods);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d8181334f86..fc1b2b963bb9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -18,16 +18,20 @@
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
+#include <plat/l3_3xxx.h>
 #include <plat/l4_3xxx.h>
 #include <plat/i2c.h>
 #include <plat/gpio.h>
 #include <plat/smartreflex.h>
+#include <plat/mcspi.h>
+#include <plat/dmtimer.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
+#include <mach/am35xx.h>
 
 /*
  * OMAP3xxx hardware module integration data
@@ -44,6 +48,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
+static struct omap_hwmod omap3430es1_dss_core_hwmod;
+static struct omap_hwmod omap3xxx_dss_core_hwmod;
+static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
+static struct omap_hwmod omap3xxx_dss_venc_hwmod;
 static struct omap_hwmod omap3xxx_i2c1_hwmod;
 static struct omap_hwmod omap3xxx_i2c2_hwmod;
 static struct omap_hwmod omap3xxx_i2c3_hwmod;
@@ -55,6 +65,11 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
 static struct omap_hwmod omap3xxx_gpio6_hwmod;
 static struct omap_hwmod omap34xx_sr1_hwmod;
 static struct omap_hwmod omap34xx_sr2_hwmod;
+static struct omap_hwmod omap34xx_mcspi1;
+static struct omap_hwmod omap34xx_mcspi2;
+static struct omap_hwmod omap34xx_mcspi3;
+static struct omap_hwmod omap34xx_mcspi4;
+static struct omap_hwmod am35xx_usbhsotg_hwmod;
 
 static struct omap_hwmod omap3xxx_dma_system_hwmod;
 
@@ -84,6 +99,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
         &omap3xxx_mpu__l3_main,
 };
 
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
+        .master         = &omap3xxx_dss_core_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Master interfaces on the L3 interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
         &omap3xxx_l3_main__l4_core,
@@ -107,7 +135,23 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
 static struct omap_hwmod omap3xxx_uart2_hwmod;
 static struct omap_hwmod omap3xxx_uart3_hwmod;
 static struct omap_hwmod omap3xxx_uart4_hwmod;
+static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
+
+/* l3_core -> usbhsotg interface */
+static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
+        .master         = &omap3xxx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
 
+/* l3_core -> am35xx_usbhsotg interface */
+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
+        .master         = &am35xx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -301,6 +345,61 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
         .user           = OCP_USER_MPU,
 };
 
+/*
+* usbhsotg interface data
+*/
+
+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
+                .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = omap3xxx_usbhsotg_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
+        &omap3xxx_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
+        &omap3xxx_l4_core__usbhsotg,
+};
+
+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
+                .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = am35xx_usbhsotg_addrs,
+        .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
+        &am35xx_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
+        &am35xx_l4_core__usbhsotg,
+};
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
@@ -417,6 +516,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* timer class */
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap3xxx_timer_1ms_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap3xxx_timer_sysc,
+        .rev =  OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap3xxx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48318000,
+                .pa_end         = 0x48318000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap3xxx_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+        &omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap3xxx_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap3xxx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x49032000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap3xxx_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
+        &omap3xxx_l4_per__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap3xxx_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap3xxx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x49034000,
+                .pa_end         = 0x49034000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap3xxx_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
+        &omap3xxx_l4_per__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap3xxx_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap3xxx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x49036000,
+                .pa_end         = 0x49036000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap3xxx_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
+        &omap3xxx_l4_per__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap3xxx_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap3xxx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x49038000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap3xxx_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
+        &omap3xxx_l4_per__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap3xxx_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT5_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap3xxx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4903A000,
+                .pa_end         = 0x4903A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap3xxx_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
+        &omap3xxx_l4_per__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap3xxx_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT6_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap3xxx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4903C000,
+                .pa_end         = 0x4903C000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap3xxx_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
+        &omap3xxx_l4_per__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap3xxx_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT7_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap3xxx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4903E000,
+                .pa_end         = 0x4903E000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap3xxx_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
+        &omap3xxx_l4_per__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap3xxx_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT8_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap3xxx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x49040000,
+                .pa_end         = 0x49040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap3xxx_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
+        &omap3xxx_l4_per__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap3xxx_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT9_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap3xxx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap3xxx_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
+        &omap3xxx_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap3xxx_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap3xxx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap3xxx_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
+        &omap3xxx_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap3xxx_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer12*/
+static struct omap_hwmod omap3xxx_timer12_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
+        { .irq = 95, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap3xxx_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
+        &omap3xxx_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap3xxx_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT12_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
         {
@@ -664,6 +1397,410 @@ static struct omap_hwmod_class i2c_class = {
         .sysc = &i2c_sysc,
 };
 
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
+        .name = "dss",
+        .sysc = &omap3xxx_dss_sysc,
+};
+
+/* dss */
+static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
+        { .irq = 25 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+        { .name = "dsi1", .dma_req = 74 },
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
+        &omap3xxx_dss__l3,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x480503FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3430es1_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
+        &omap3430es1_l4_core__dss,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
+        &omap3xxx_l4_core__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "tv_clk", .clk = "dss_tv_fck" },
+        { .role = "dssclk", .clk = "dss_96m_fck" },
+        { .role = "sys_clk", .clk = "dss2_alwon_fck" },
+};
+
+static struct omap_hwmod omap3430es1_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap3xxx_dss_hwmod_class,
+        .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
+        .mpu_irqs       = omap3xxx_dss_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
+        .sdma_reqs      = omap3xxx_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
+
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap3430es1_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
+        .masters        = omap3xxx_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+static struct omap_hwmod omap3xxx_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap3xxx_dss_hwmod_class,
+        .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
+        .mpu_irqs       = omap3xxx_dss_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
+        .sdma_reqs      = omap3xxx_dss_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
+
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
+                        .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap3xxx_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
+        .masters        = omap3xxx_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
+                                CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
+        .name = "dispc",
+        .sysc = &omap3xxx_dispc_sysc,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x480507FF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
+        &omap3xxx_l4_core__dss_dispc,
+};
+
+static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap3xxx_dispc_hwmod_class,
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'dsi' class
+ * display serial interface controller
+ */
+
+static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
+        .name = "dsi",
+};
+
+/* dss_dsi1 */
+static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x4804FC00,
+                .pa_end         = 0x4804FFFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dsi1_hwmod,
+        .addr           = omap3xxx_dss_dsi1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_dsi1 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
+        &omap3xxx_l4_core__dss_dsi1,
+};
+
+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
+        .name           = "dss_dsi1",
+        .class          = &omap3xxx_dsi_hwmod_class,
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_dsi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
+        .name = "rfbi",
+        .sysc = &omap3xxx_rfbi_sysc,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050BFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
+        &omap3xxx_l4_core__dss_rfbi,
+};
+
+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap3xxx_rfbi_hwmod_class,
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
+        .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050FFF,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_venc_hwmod,
+        .clk            = "dss_tv_fck",
+        .addr           = omap3xxx_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
+        &omap3xxx_l4_core__dss_venc,
+};
+
+static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap3xxx_venc_hwmod_class,
+        .main_clk       = "dss1_alwon_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_DSS1_SHIFT,
+                        .module_offs = OMAP3430_DSS_MOD,
+                },
+        },
+        .slaves         = omap3xxx_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
+                                CHIP_GE_OMAP3630ES1_1),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 /* I2C1 */
 
 static struct omap_i2c_dev_attr i2c1_dev_attr = {
@@ -1356,6 +2493,360 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480980ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi1,
+        .clk            = "mcspi1_ick",
+        .addr           = omap34xx_mcspi1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi2,
+        .clk            = "mcspi2_ick",
+        .addr           = omap34xx_mcspi2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b80ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi3,
+        .clk            = "mcspi3_ick",
+        .addr           = omap34xx_mcspi3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi4 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi4,
+        .clk            = "mcspi4_ick",
+        .addr           = omap34xx_mcspi4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap34xx_mcspi_class = {
+        .name = "mcspi",
+        .sysc = &omap34xx_mcspi_sysc,
+        .rev = OMAP3_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
+        { .name = "irq", .irq = 65 },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 },
+        { .name = "rx0", .dma_req = 36 },
+        { .name = "tx1", .dma_req = 37 },
+        { .name = "rx1", .dma_req = 38 },
+        { .name = "tx2", .dma_req = 39 },
+        { .name = "rx2", .dma_req = 40 },
+        { .name = "tx3", .dma_req = 41 },
+        { .name = "rx3", .dma_req = 42 },
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
+        &omap34xx_l4_core__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap34xx_mcspi1 = {
+        .name           = "mcspi1",
+        .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
+        { .name = "irq", .irq = 66 },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 },
+        { .name = "rx0", .dma_req = 44 },
+        { .name = "tx1", .dma_req = 45 },
+        { .name = "rx1", .dma_req = 46 },
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
+        &omap34xx_l4_core__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap34xx_mcspi2 = {
+        .name           = "mcspi2",
+        .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
+        { .name = "irq", .irq = 91 }, /* 91 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 15 },
+        { .name = "rx0", .dma_req = 16 },
+        { .name = "tx1", .dma_req = 23 },
+        { .name = "rx1", .dma_req = 24 },
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
+        &omap34xx_l4_core__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap34xx_mcspi3 = {
+        .name           = "mcspi3",
+        .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
+        .main_clk       = "mcspi3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* SPI4 */
+static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
+        { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
+        { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
+        &omap34xx_l4_core__mcspi4,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap34xx_mcspi4 = {
+        .name           = "mcspi4",
+        .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
+        .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
+        .main_clk       = "mcspi4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
+                },
+        },
+        .slaves         = omap34xx_mcspi4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
+        .class          = &omap34xx_mcspi_class,
+        .dev_attr       = &omap_mcspi4_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/*
+ * usbhsotg
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
+        .rev_offs       = 0x0400,
+        .sysc_offs      = 0x0404,
+        .syss_offs      = 0x0408,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class usbotg_class = {
+        .name = "usbotg",
+        .sysc = &omap3xxx_usbhsotg_sysc,
+};
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
+
+        { .name = "mc", .irq = 92 },
+        { .name = "dma", .irq = 93 },
+};
+
+static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+        .name           = "usb_otg_hs",
+        .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
+        .main_clk       = "hsotgusb_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
+                        .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
+                },
+        },
+        .masters        = omap3xxx_usbhsotg_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
+        .slaves         = omap3xxx_usbhsotg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
+        .class          = &usbotg_class,
+
+        /*
+         * Erratum ID: i479  idle_req / idle_ack mechanism potentially
+         * broken when autoidle is enabled
+         * workaround is to disable the autoidle bit at module level.
+         */
+        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+                                | HWMOD_SWSUP_MSTANDBY,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+
+        { .name = "mc", .irq = 71 },
+};
+
+static struct omap_hwmod_class am35xx_usbotg_class = {
+        .name = "am35xx_usbotg",
+        .sysc = NULL,
+};
+
+static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+        .name           = "am35x_otg_hs",
+        .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
+        .main_clk       = NULL,
+        .prcm = {
+                .omap2 = {
+                },
+        },
+        .masters        = am35xx_usbhsotg_masters,
+        .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
+        .slaves         = am35xx_usbhsotg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
+        .class          = &am35xx_usbotg_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
@@ -1363,11 +2854,34 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l4_wkup_hwmod,
         &omap3xxx_mpu_hwmod,
         &omap3xxx_iva_hwmod,
+
+        &omap3xxx_timer1_hwmod,
+        &omap3xxx_timer2_hwmod,
+        &omap3xxx_timer3_hwmod,
+        &omap3xxx_timer4_hwmod,
+        &omap3xxx_timer5_hwmod,
+        &omap3xxx_timer6_hwmod,
+        &omap3xxx_timer7_hwmod,
+        &omap3xxx_timer8_hwmod,
+        &omap3xxx_timer9_hwmod,
+        &omap3xxx_timer10_hwmod,
+        &omap3xxx_timer11_hwmod,
+        &omap3xxx_timer12_hwmod,
+
         &omap3xxx_wd_timer2_hwmod,
         &omap3xxx_uart1_hwmod,
         &omap3xxx_uart2_hwmod,
         &omap3xxx_uart3_hwmod,
         &omap3xxx_uart4_hwmod,
+        /* dss class */
+        &omap3430es1_dss_core_hwmod,
+        &omap3xxx_dss_core_hwmod,
+        &omap3xxx_dss_dispc_hwmod,
+        &omap3xxx_dss_dsi1_hwmod,
+        &omap3xxx_dss_rfbi_hwmod,
+        &omap3xxx_dss_venc_hwmod,
+
+        /* i2c class */
         &omap3xxx_i2c1_hwmod,
         &omap3xxx_i2c2_hwmod,
         &omap3xxx_i2c3_hwmod,
@@ -1387,10 +2901,23 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 
         /* dma_system class*/
         &omap3xxx_dma_system_hwmod,
+
+        /* mcspi class */
+        &omap34xx_mcspi1,
+        &omap34xx_mcspi2,
+        &omap34xx_mcspi3,
+        &omap34xx_mcspi4,
+
+        /* usbotg class */
+        &omap3xxx_usbhsotg_hwmod,
+
+        /* usbotg for am35x */
+        &am35xx_usbhsotg_hwmod,
+
         NULL,
 };
 
 int __init omap3xxx_hwmod_init(void)
 {
-        return omap_hwmod_init(omap3xxx_hwmods);
+        return omap_hwmod_register(omap3xxx_hwmods);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd11fbf..2c5882792e01 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
 /*
  * Hardware modules present on the OMAP44xx chips
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley
@@ -24,6 +24,7 @@
 #include <plat/cpu.h>
 #include <plat/gpio.h>
 #include <plat/dma.h>
+#include <plat/mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -40,10 +41,15 @@
 #define OMAP44XX_DMA_REQ_START  1
 
 /* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_aess_hwmod;
 static struct omap_hwmod omap44xx_dma_system_hwmod;
 static struct omap_hwmod omap44xx_dmm_hwmod;
 static struct omap_hwmod omap44xx_dsp_hwmod;
+static struct omap_hwmod omap44xx_dss_hwmod;
 static struct omap_hwmod omap44xx_emif_fw_hwmod;
+static struct omap_hwmod omap44xx_hsi_hwmod;
+static struct omap_hwmod omap44xx_ipu_hwmod;
+static struct omap_hwmod omap44xx_iss_hwmod;
 static struct omap_hwmod omap44xx_iva_hwmod;
 static struct omap_hwmod omap44xx_l3_instr_hwmod;
 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
@@ -53,8 +59,11 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod;
 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
 static struct omap_hwmod omap44xx_l4_per_hwmod;
 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
+static struct omap_hwmod omap44xx_mmc1_hwmod;
+static struct omap_hwmod omap44xx_mmc2_hwmod;
 static struct omap_hwmod omap44xx_mpu_hwmod;
 static struct omap_hwmod omap44xx_mpu_private_hwmod;
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
 
 /*
  * Interconnects omap_hwmod structures
@@ -213,6 +222,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+        .master         = &omap44xx_dss_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_2 -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
         .master         = &omap44xx_l3_main_2_hwmod,
@@ -229,6 +246,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* mmc1 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
+        .master         = &omap44xx_mmc1_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+        .master         = &omap44xx_mmc2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
         .master         = &omap44xx_mpu_hwmod,
@@ -240,8 +273,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 /* l3_main_1 slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
         &omap44xx_dsp__l3_main_1,
+        &omap44xx_dss__l3_main_1,
         &omap44xx_l3_main_2__l3_main_1,
         &omap44xx_l4_cfg__l3_main_1,
+        &omap44xx_mmc1__l3_main_1,
+        &omap44xx_mmc2__l3_main_1,
         &omap44xx_mpu__l3_main_1,
 };
 
@@ -262,6 +298,30 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* hsi -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
+        .master         = &omap44xx_hsi_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
+        .master         = &omap44xx_ipu_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
+        .master         = &omap44xx_iss_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* iva -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
         .master         = &omap44xx_iva_hwmod,
@@ -286,12 +346,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_otg_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_2 slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
         &omap44xx_dma_system__l3_main_2,
+        &omap44xx_hsi__l3_main_2,
+        &omap44xx_ipu__l3_main_2,
+        &omap44xx_iss__l3_main_2,
         &omap44xx_iva__l3_main_2,
         &omap44xx_l3_main_1__l3_main_2,
         &omap44xx_l4_cfg__l3_main_2,
+        &omap44xx_usb_otg_hs__l3_main_2,
 };
 
 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
@@ -351,6 +423,14 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 };
 
 /* l4_abe interface data */
+/* aess -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
+        .master         = &omap44xx_aess_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* dsp -> l4_abe */
 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
         .master         = &omap44xx_dsp_hwmod,
@@ -377,6 +457,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 
 /* l4_abe slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
+        &omap44xx_aess__l4_abe,
         &omap44xx_dsp__l4_abe,
         &omap44xx_l3_main_1__l4_abe,
         &omap44xx_mpu__l4_abe,
@@ -494,26 +575,15 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  * - They still need to be validated with the driver
  *   properly adapted to omap_hwmod / omap_device
  *
- *  aess
- *  bandgap
  *  c2c
  *  c2c_target_fw
  *  cm_core
  *  cm_core_aon
- *  counter_32k
  *  ctrl_module_core
  *  ctrl_module_pad_core
  *  ctrl_module_pad_wkup
  *  ctrl_module_wkup
  *  debugss
- *  dmic
- *  dss
- *  dss_dispc
- *  dss_dsi1
- *  dss_dsi2
- *  dss_hdmi
- *  dss_rfbi
- *  dss_venc
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
  *  elm
@@ -524,58 +594,211 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  gpu
  *  hdq1w
  *  hsi
- *  ipu
- *  iss
- *  kbd
- *  mailbox
- *  mcasp
- *  mcbsp1
- *  mcbsp2
- *  mcbsp3
- *  mcbsp4
- *  mcpdm
- *  mcspi1
- *  mcspi2
- *  mcspi3
- *  mcspi4
- *  mmc1
- *  mmc2
- *  mmc3
- *  mmc4
- *  mmc5
- *  mpu_c0
- *  mpu_c1
  *  ocmc_ram
  *  ocp2scp_usb_phy
  *  ocp_wp_noc
- *  prcm
  *  prcm_mpu
  *  prm
  *  scrm
  *  sl2if
  *  slimbus1
  *  slimbus2
- *  spinlock
- *  timer1
- *  timer10
- *  timer11
- *  timer2
- *  timer3
- *  timer4
- *  timer5
- *  timer6
- *  timer7
- *  timer8
- *  timer9
  *  usb_host_fs
  *  usb_host_hs
- *  usb_otg_hs
  *  usb_phy_cm
  *  usb_tll_hs
  *  usim
  */
 
 /*
+ * 'aess' class
+ * audio engine sub system
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
+        .name   = "aess",
+        .sysc   = &omap44xx_aess_sysc,
+};
+
+/* aess */
+static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
+        { .irq = 99 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
+        { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
+        { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
+};
+
+/* aess master ports */
+static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
+        &omap44xx_aess__l4_abe,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
+        {
+                .pa_start       = 0x401f1000,
+                .pa_end         = 0x401f13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> aess */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_aess_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
+        {
+                .pa_start       = 0x490f1000,
+                .pa_end         = 0x490f13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> aess (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_aess_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* aess slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
+        &omap44xx_l4_abe__aess,
+        &omap44xx_l4_abe__aess_dma,
+};
+
+static struct omap_hwmod omap44xx_aess_hwmod = {
+        .name           = "aess",
+        .class          = &omap44xx_aess_hwmod_class,
+        .mpu_irqs       = omap44xx_aess_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
+        .sdma_reqs      = omap44xx_aess_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
+        .main_clk       = "aess_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_aess_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
+        .masters        = omap44xx_aess_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'bandgap' class
+ * bangap reference for ldo regulators
+ */
+
+static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
+        .name   = "bandgap",
+};
+
+/* bandgap */
+static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
+        { .role = "fclk", .clk = "bandgap_fclk" },
+};
+
+static struct omap_hwmod omap44xx_bandgap_hwmod = {
+        .name           = "bandgap",
+        .class          = &omap44xx_bandgap_hwmod_class,
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+                },
+        },
+        .opt_clks       = bandgap_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0004,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap44xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod omap44xx_counter_32k_hwmod;
+static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x4a304000,
+                .pa_end         = 0x4a30401f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_counter_32k_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_counter_32k_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* counter_32k slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
+        &omap44xx_l4_wkup__counter_32k,
+};
+
+static struct omap_hwmod omap44xx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap44xx_counter_hwmod_class,
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "sys_32k_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_counter_32k_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'dma' class
  * dma controller for data exchange between memory to memory (i.e. internal or
  * external memory) and gp peripherals to memory or memory to gp peripherals
@@ -662,6 +885,96 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
 };
 
 /*
+ * 'dmic' class
+ * digital microphone controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
+        .name   = "dmic",
+        .sysc   = &omap44xx_dmic_sysc,
+};
+
+/* dmic */
+static struct omap_hwmod omap44xx_dmic_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
+        { .irq = 114 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
+        { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
+        {
+                .pa_start       = 0x4012e000,
+                .pa_end         = 0x4012e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
+        {
+                .pa_start       = 0x4902e000,
+                .pa_end         = 0x4902e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> dmic (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* dmic slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
+        &omap44xx_l4_abe__dmic,
+        &omap44xx_l4_abe__dmic_dma,
+};
+
+static struct omap_hwmod omap44xx_dmic_hwmod = {
+        .name           = "dmic",
+        .class          = &omap44xx_dmic_hwmod_class,
+        .mpu_irqs       = omap44xx_dmic_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
+        .sdma_reqs      = omap44xx_dmic_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
+        .main_clk       = "dmic_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dmic_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'dsp' class
  * dsp sub-system
  */
@@ -747,6 +1060,590 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
 };
 
 /*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
+        .name   = "dss",
+        .sysc   = &omap44xx_dss_sysc,
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
+        &omap44xx_dss__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+        {
+                .pa_start       = 0x58000000,
+                .pa_end         = 0x5800007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x4804007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
+        &omap44xx_l3_main_2__dss,
+        &omap44xx_l4_per__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+        { .role = "tv_clk", .clk = "dss_tv_clk" },
+        { .role = "dss_clk", .clk = "dss_dss_clk" },
+        { .role = "video_clk", .clk = "dss_48mhz_clk" },
+};
+
+static struct omap_hwmod omap44xx_dss_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap44xx_dss_hwmod_class,
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
+        .slaves         = omap44xx_dss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
+        .masters        = omap44xx_dss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
+        .name   = "dispc",
+        .sysc   = &omap44xx_dispc_sysc,
+};
+
+/* dss_dispc */
+static struct omap_hwmod omap44xx_dss_dispc_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+        { .irq = 25 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
+        { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58001000,
+                .pa_end         = 0x58001fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dispc_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48041000,
+                .pa_end         = 0x48041fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dispc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
+        &omap44xx_l3_main_2__dss_dispc,
+        &omap44xx_l4_per__dss_dispc,
+};
+
+static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap44xx_dispc_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_dispc_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
+        .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_dispc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dsi' class
+ * display serial interface controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
+        .name   = "dsi",
+        .sysc   = &omap44xx_dsi_sysc,
+};
+
+/* dss_dsi1 */
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
+        { .irq = 53 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
+        { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+        {
+                .pa_start       = 0x58004000,
+                .pa_end         = 0x580041ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dsi1_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x480441ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_dsi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
+        &omap44xx_l3_main_2__dss_dsi1,
+        &omap44xx_l4_per__dss_dsi1,
+};
+
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+        .name           = "dss_dsi1",
+        .class          = &omap44xx_dsi_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_dsi1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
+        .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_dsi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* dss_dsi2 */
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
+        { .irq = 84 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
+        { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+        {
+                .pa_start       = 0x58005000,
+                .pa_end         = 0x580051ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_dsi2_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+        {
+                .pa_start       = 0x48045000,
+                .pa_end         = 0x480451ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_dsi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
+        &omap44xx_l3_main_2__dss_dsi2,
+        &omap44xx_l4_per__dss_dsi2,
+};
+
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+        .name           = "dss_dsi2",
+        .class          = &omap44xx_dsi_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_dsi2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
+        .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_dsi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
+        .name   = "hdmi",
+        .sysc   = &omap44xx_hdmi_sysc,
+};
+
+/* dss_hdmi */
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
+        { .irq = 101 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
+        { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58006000,
+                .pa_end         = 0x58006fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_hdmi_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_hdmi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_hdmi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
+        &omap44xx_l3_main_2__dss_hdmi,
+        &omap44xx_l4_per__dss_hdmi,
+};
+
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+        .name           = "dss_hdmi",
+        .class          = &omap44xx_hdmi_hwmod_class,
+        .mpu_irqs       = omap44xx_dss_hdmi_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
+        .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_hdmi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
+        .name   = "rfbi",
+        .sysc   = &omap44xx_rfbi_sysc,
+};
+
+/* dss_rfbi */
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
+static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
+        { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58002000,
+                .pa_end         = 0x580020ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_rfbi_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x480420ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_rfbi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
+        &omap44xx_l3_main_2__dss_rfbi,
+        &omap44xx_l4_per__dss_rfbi,
+};
+
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap44xx_rfbi_hwmod_class,
+        .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_rfbi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
+        .name   = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod omap44xx_dss_venc_hwmod;
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58003000,
+                .pa_end         = 0x580030ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dss_venc_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48043000,
+                .pa_end         = 0x480430ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_venc_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+        &omap44xx_l3_main_2__dss_venc,
+        &omap44xx_l4_per__dss_venc,
+};
+
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap44xx_venc_hwmod_class,
+        .main_clk       = "dss_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dss_venc_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'gpio' class
  * general purpose io module
  */
@@ -1093,6 +1990,83 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
 };
 
 /*
+ * 'hsi' class
+ * mipi high-speed synchronous serial interface (multichannel and full-duplex
+ * serial if)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
+        .name   = "hsi",
+        .sysc   = &omap44xx_hsi_sysc,
+};
+
+/* hsi */
+static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
+        { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
+        { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
+        { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* hsi master ports */
+static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
+        &omap44xx_hsi__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
+        {
+                .pa_start       = 0x4a058000,
+                .pa_end         = 0x4a05bfff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> hsi */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_hsi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_hsi_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* hsi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
+        &omap44xx_l4_cfg__hsi,
+};
+
+static struct omap_hwmod omap44xx_hsi_hwmod = {
+        .name           = "hsi",
+        .class          = &omap44xx_hsi_hwmod_class,
+        .mpu_irqs       = omap44xx_hsi_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
+        .main_clk       = "hsi_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_hsi_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
+        .masters        = omap44xx_hsi_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'i2c' class
  * multimaster high-speed i2c controller
  */
@@ -1326,6 +2300,188 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
 };
 
 /*
+ * 'ipu' class
+ * imaging processor unit
+ */
+
+static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
+        .name   = "ipu",
+};
+
+/* ipu */
+static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
+        { .irq = 100 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+        { .name = "cpu0", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
+        { .name = "cpu1", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+
+/* ipu master ports */
+static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
+        &omap44xx_ipu__l3_main_2,
+};
+
+/* l3_main_2 -> ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
+        &omap44xx_l3_main_2__ipu,
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
+        .name           = "ipu_c0",
+        .class          = &omap44xx_ipu_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_ipu_c0_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
+        .prcm           = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
+        .name           = "ipu_c1",
+        .class          = &omap44xx_ipu_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_ipu_c1_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
+        .prcm           = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct omap_hwmod omap44xx_ipu_hwmod = {
+        .name           = "ipu",
+        .class          = &omap44xx_ipu_hwmod_class,
+        .mpu_irqs       = omap44xx_ipu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
+        .rst_lines      = omap44xx_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
+        .main_clk       = "ipu_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                },
+        },
+        .slaves         = omap44xx_ipu_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
+        .masters        = omap44xx_ipu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'iss' class
+ * external images sensor pixel data processor
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
+        .name   = "iss",
+        .sysc   = &omap44xx_iss_sysc,
+};
+
+/* iss */
+static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
+        { .irq = 24 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
+        { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
+        { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
+        { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
+        { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
+};
+
+/* iss master ports */
+static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
+        &omap44xx_iss__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
+        {
+                .pa_start       = 0x52000000,
+                .pa_end         = 0x520000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> iss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iss_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iss_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iss slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
+        &omap44xx_l3_main_2__iss,
+};
+
+static struct omap_hwmod_opt_clk iss_opt_clks[] = {
+        { .role = "ctrlclk", .clk = "iss_ctrlclk" },
+};
+
+static struct omap_hwmod omap44xx_iss_hwmod = {
+        .name           = "iss",
+        .class          = &omap44xx_iss_hwmod_class,
+        .mpu_irqs       = omap44xx_iss_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
+        .sdma_reqs      = omap44xx_iss_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
+        .main_clk       = "iss_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
+                },
+        },
+        .opt_clks       = iss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
+        .slaves         = omap44xx_iss_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
+        .masters        = omap44xx_iss_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'iva' class
  * multi-standard video encoder/decoder hardware accelerator
  */
@@ -1435,6 +2591,1070 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
 };
 
 /*
+ * 'kbd' class
+ * keyboard controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
+        .name   = "kbd",
+        .sysc   = &omap44xx_kbd_sysc,
+};
+
+/* kbd */
+static struct omap_hwmod omap44xx_kbd_hwmod;
+static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
+        { .irq = 120 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+        {
+                .pa_start       = 0x4a31c000,
+                .pa_end         = 0x4a31c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_kbd_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_kbd_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* kbd slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
+        &omap44xx_l4_wkup__kbd,
+};
+
+static struct omap_hwmod omap44xx_kbd_hwmod = {
+        .name           = "kbd",
+        .class          = &omap44xx_kbd_hwmod_class,
+        .mpu_irqs       = omap44xx_kbd_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
+        .main_clk       = "kbd_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_kbd_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &omap44xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+        { .irq = 26 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x4a0f4000,
+                .pa_end         = 0x4a0f41ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mailbox_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+        &omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap44xx_mailbox_hwmod_class,
+        .mpu_irqs       = omap44xx_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
+        .name   = "mcbsp",
+        .sysc   = &omap44xx_mcbsp_sysc,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod omap44xx_mcbsp1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
+        { .irq = 17 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+        {
+                .pa_start       = 0x40122000,
+                .pa_end         = 0x401220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+        {
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
+        &omap44xx_l4_abe__mcbsp1,
+        &omap44xx_l4_abe__mcbsp1_dma,
+};
+
+static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
+        .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod omap44xx_mcbsp2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
+        { .irq = 22 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+        {
+                .pa_start       = 0x40124000,
+                .pa_end         = 0x401240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+        {
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp2 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
+        &omap44xx_l4_abe__mcbsp2,
+        &omap44xx_l4_abe__mcbsp2_dma,
+};
+
+static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
+        .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod omap44xx_mcbsp3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
+        { .irq = 23 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+        {
+                .pa_start       = 0x40126000,
+                .pa_end         = 0x401260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+        {
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcbsp3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
+        &omap44xx_l4_abe__mcbsp3,
+        &omap44xx_l4_abe__mcbsp3_dma,
+};
+
+static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
+        .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod omap44xx_mcbsp4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
+        { .irq = 16 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+        {
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcbsp4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
+        &omap44xx_l4_per__mcbsp4,
+};
+
+static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap44xx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap44xx_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
+        .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
+        .name   = "mcpdm",
+        .sysc   = &omap44xx_mcpdm_sysc,
+};
+
+/* mcpdm */
+static struct omap_hwmod omap44xx_mcpdm_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
+        { .irq = 112 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
+        { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
+        { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+        {
+                .pa_start       = 0x40132000,
+                .pa_end         = 0x4013207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x4903207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> mcpdm (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* mcpdm slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
+        &omap44xx_l4_abe__mcpdm,
+        &omap44xx_l4_abe__mcpdm_dma,
+};
+
+static struct omap_hwmod omap44xx_mcpdm_hwmod = {
+        .name           = "mcpdm",
+        .class          = &omap44xx_mcpdm_hwmod_class,
+        .mpu_irqs       = omap44xx_mcpdm_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
+        .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
+        .main_clk       = "mcpdm_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mcpdm_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+        .name   = "mcspi",
+        .sysc   = &omap44xx_mcspi_sysc,
+        .rev    = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+        { .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480981ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+        &omap44xx_l4_per__mcspi1,
+};
+
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
+        .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+        .main_clk       = "mcspi1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi1_dev_attr,
+        .slaves         = omap44xx_mcspi1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+        { .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+        &omap44xx_l4_per__mcspi2,
+};
+
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
+        .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+        .main_clk       = "mcspi2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi2_dev_attr,
+        .slaves         = omap44xx_mcspi2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+        { .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b81ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+        &omap44xx_l4_per__mcspi3,
+};
+
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
+        .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+        .main_clk       = "mcspi3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi3_dev_attr,
+        .slaves         = omap44xx_mcspi3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+        { .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+        &omap44xx_l4_per__mcspi4,
+};
+
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .class          = &omap44xx_mcspi_hwmod_class,
+        .mpu_irqs       = omap44xx_mcspi4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
+        .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+        .main_clk       = "mcspi4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+                },
+        },
+        .dev_attr       = &mcspi4_dev_attr,
+        .slaves         = omap44xx_mcspi4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
+        .name   = "mmc",
+        .sysc   = &omap44xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
+        { .irq = 83 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
+};
+
+/* mmc1 master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
+        &omap44xx_mmc1__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
+        &omap44xx_l4_per__mmc1,
+};
+
+static struct omap_hwmod omap44xx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
+        .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
+        .main_clk       = "mmc1_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
+        .masters        = omap44xx_mmc1_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
+        { .irq = 86 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
+};
+
+/* mmc2 master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
+        &omap44xx_mmc2__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b43ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
+        &omap44xx_l4_per__mmc2,
+};
+
+static struct omap_hwmod omap44xx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
+        .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
+        .main_clk       = "mmc2_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
+        .masters        = omap44xx_mmc2_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc3 */
+static struct omap_hwmod omap44xx_mmc3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
+        { .irq = 94 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
+        &omap44xx_l4_per__mmc3,
+};
+
+static struct omap_hwmod omap44xx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
+        .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
+        .main_clk       = "mmc3_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc4 */
+static struct omap_hwmod omap44xx_mmc4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
+        { .irq = 96 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+        {
+                .pa_start       = 0x480d1000,
+                .pa_end         = 0x480d13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
+        &omap44xx_l4_per__mmc4,
+};
+
+static struct omap_hwmod omap44xx_mmc4_hwmod = {
+        .name           = "mmc4",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
+        .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
+        .main_clk       = "mmc4_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mmc5 */
+static struct omap_hwmod omap44xx_mmc5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
+        { .irq = 59 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+        {
+                .pa_start       = 0x480d5000,
+                .pa_end         = 0x480d53ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
+        &omap44xx_l4_per__mmc5,
+};
+
+static struct omap_hwmod omap44xx_mmc5_hwmod = {
+        .name           = "mmc5",
+        .class          = &omap44xx_mmc_hwmod_class,
+        .mpu_irqs       = omap44xx_mmc5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
+        .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
+        .main_clk       = "mmc5_fck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_mmc5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'mpu' class
  * mpu sub-system
  */
@@ -1639,6 +3859,677 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 };
 
 /*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the processes
+ * running on multiple processors
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
+        .name   = "spinlock",
+        .sysc   = &omap44xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod omap44xx_spinlock_hwmod;
+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x4a0f6000,
+                .pa_end         = 0x4a0f6fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_spinlock_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_spinlock_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* spinlock slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
+        &omap44xx_l4_cfg__spinlock,
+};
+
+static struct omap_hwmod omap44xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &omap44xx_spinlock_hwmod_class,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_spinlock_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap44xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap44xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap44xx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x4a318000,
+                .pa_end         = 0x4a31807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_timer1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+        &omap44xx_l4_wkup__timer1,
+};
+
+static struct omap_hwmod omap44xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &omap44xx_timer_1ms_hwmod_class,
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_timer1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
+        .main_clk       = "timer1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer2 */
+static struct omap_hwmod omap44xx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+        { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48032000,
+                .pa_end         = 0x4803207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+        &omap44xx_l4_per__timer2,
+};
+
+static struct omap_hwmod omap44xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &omap44xx_timer_1ms_hwmod_class,
+        .mpu_irqs       = omap44xx_timer2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
+        .main_clk       = "timer2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer3 */
+static struct omap_hwmod omap44xx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
+        { .irq = 39 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48034000,
+                .pa_end         = 0x4803407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
+        &omap44xx_l4_per__timer3,
+};
+
+static struct omap_hwmod omap44xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
+        .main_clk       = "timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer4 */
+static struct omap_hwmod omap44xx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
+        { .irq = 40 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x48036000,
+                .pa_end         = 0x4803607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
+        &omap44xx_l4_per__timer4,
+};
+
+static struct omap_hwmod omap44xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
+        .main_clk       = "timer4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer5 */
+static struct omap_hwmod omap44xx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
+        { .irq = 41 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x40138000,
+                .pa_end         = 0x4013807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x4903807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
+        &omap44xx_l4_abe__timer5,
+        &omap44xx_l4_abe__timer5_dma,
+};
+
+static struct omap_hwmod omap44xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
+        .main_clk       = "timer5_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer6 */
+static struct omap_hwmod omap44xx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
+        { .irq = 42 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4013a000,
+                .pa_end         = 0x4013a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903a000,
+                .pa_end         = 0x4903a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
+        &omap44xx_l4_abe__timer6,
+        &omap44xx_l4_abe__timer6_dma,
+};
+
+static struct omap_hwmod omap44xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer6_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
+        .main_clk       = "timer6_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer7 */
+static struct omap_hwmod omap44xx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
+        { .irq = 43 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4013c000,
+                .pa_end         = 0x4013c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903c000,
+                .pa_end         = 0x4903c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer7 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
+        &omap44xx_l4_abe__timer7,
+        &omap44xx_l4_abe__timer7_dma,
+};
+
+static struct omap_hwmod omap44xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer7_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
+        .main_clk       = "timer7_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer8 */
+static struct omap_hwmod omap44xx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
+        { .irq = 44 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4013e000,
+                .pa_end         = 0x4013e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903e000,
+                .pa_end         = 0x4903e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* timer8 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
+        &omap44xx_l4_abe__timer8,
+        &omap44xx_l4_abe__timer8_dma,
+};
+
+static struct omap_hwmod omap44xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer8_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
+        .main_clk       = "timer8_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer9 */
+static struct omap_hwmod omap44xx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
+        { .irq = 45 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x4803e000,
+                .pa_end         = 0x4803e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer9_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
+        &omap44xx_l4_per__timer9,
+};
+
+static struct omap_hwmod omap44xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer9_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
+        .main_clk       = "timer9_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer10 */
+static struct omap_hwmod omap44xx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
+        { .irq = 46 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x4808607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer10_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
+        &omap44xx_l4_per__timer10,
+};
+
+static struct omap_hwmod omap44xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &omap44xx_timer_1ms_hwmod_class,
+        .mpu_irqs       = omap44xx_timer10_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
+        .main_clk       = "timer10_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer11 */
+static struct omap_hwmod omap44xx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
+        { .irq = 47 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x4808807f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer11_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
+        &omap44xx_l4_per__timer11,
+};
+
+static struct omap_hwmod omap44xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &omap44xx_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_timer11_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
+        .main_clk       = "timer11_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'uart' class
  * universal asynchronous receiver/transmitter (uart)
  */
@@ -1870,6 +4761,88 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
 };
 
 /*
+ * 'usb_otg_hs' class
+ * high-speed on-the-go universal serial bus (usb_otg_hs) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
+        .rev_offs       = 0x0400,
+        .sysc_offs      = 0x0404,
+        .syss_offs      = 0x0408,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
+        .name = "usb_otg_hs",
+        .sysc = &omap44xx_usb_otg_hs_sysc,
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
+        { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
+        { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* usb_otg_hs master ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
+        &omap44xx_usb_otg_hs__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+        {
+                .pa_start       = 0x4a0ab000,
+                .pa_end         = 0x4a0ab003,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> usb_otg_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_otg_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_otg_hs_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
+        &omap44xx_l4_cfg__usb_otg_hs,
+};
+
+static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
+        { .role = "xclk", .clk = "usb_otg_hs_xclk" },
+};
+
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+        .name           = "usb_otg_hs",
+        .class          = &omap44xx_usb_otg_hs_hwmod_class,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
+        .main_clk       = "usb_otg_hs_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_hs_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+        .slaves         = omap44xx_usb_otg_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
+        .masters        = omap44xx_usb_otg_hs_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'wd_timer' class
  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  * overflow condition
@@ -2024,13 +4997,34 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
         /* mpu_bus class */
         &omap44xx_mpu_private_hwmod,
 
+        /* aess class */
+/*      &omap44xx_aess_hwmod, */
+
+        /* bandgap class */
+        &omap44xx_bandgap_hwmod,
+
+        /* counter class */
+/*      &omap44xx_counter_32k_hwmod, */
+
         /* dma class */
         &omap44xx_dma_system_hwmod,
 
+        /* dmic class */
+        &omap44xx_dmic_hwmod,
+
         /* dsp class */
         &omap44xx_dsp_hwmod,
         &omap44xx_dsp_c0_hwmod,
 
+        /* dss class */
+        &omap44xx_dss_hwmod,
+        &omap44xx_dss_dispc_hwmod,
+        &omap44xx_dss_dsi1_hwmod,
+        &omap44xx_dss_dsi2_hwmod,
+        &omap44xx_dss_hdmi_hwmod,
+        &omap44xx_dss_rfbi_hwmod,
+        &omap44xx_dss_venc_hwmod,
+
         /* gpio class */
         &omap44xx_gpio1_hwmod,
         &omap44xx_gpio2_hwmod,
@@ -2039,17 +5033,56 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
         &omap44xx_gpio5_hwmod,
         &omap44xx_gpio6_hwmod,
 
+        /* hsi class */
+/*      &omap44xx_hsi_hwmod, */
+
         /* i2c class */
         &omap44xx_i2c1_hwmod,
         &omap44xx_i2c2_hwmod,
         &omap44xx_i2c3_hwmod,
         &omap44xx_i2c4_hwmod,
 
+        /* ipu class */
+        &omap44xx_ipu_hwmod,
+        &omap44xx_ipu_c0_hwmod,
+        &omap44xx_ipu_c1_hwmod,
+
+        /* iss class */
+/*      &omap44xx_iss_hwmod, */
+
         /* iva class */
         &omap44xx_iva_hwmod,
         &omap44xx_iva_seq0_hwmod,
         &omap44xx_iva_seq1_hwmod,
 
+        /* kbd class */
+/*      &omap44xx_kbd_hwmod, */
+
+        /* mailbox class */
+        &omap44xx_mailbox_hwmod,
+
+        /* mcbsp class */
+        &omap44xx_mcbsp1_hwmod,
+        &omap44xx_mcbsp2_hwmod,
+        &omap44xx_mcbsp3_hwmod,
+        &omap44xx_mcbsp4_hwmod,
+
+        /* mcpdm class */
+/*      &omap44xx_mcpdm_hwmod, */
+
+        /* mcspi class */
+        &omap44xx_mcspi1_hwmod,
+        &omap44xx_mcspi2_hwmod,
+        &omap44xx_mcspi3_hwmod,
+        &omap44xx_mcspi4_hwmod,
+
+        /* mmc class */
+/*      &omap44xx_mmc1_hwmod, */
+/*      &omap44xx_mmc2_hwmod, */
+/*      &omap44xx_mmc3_hwmod, */
+/*      &omap44xx_mmc4_hwmod, */
+/*      &omap44xx_mmc5_hwmod, */
+
         /* mpu class */
         &omap44xx_mpu_hwmod,
 
@@ -2058,12 +5091,31 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
         &omap44xx_smartreflex_iva_hwmod,
         &omap44xx_smartreflex_mpu_hwmod,
 
+        /* spinlock class */
+        &omap44xx_spinlock_hwmod,
+
+        /* timer class */
+        &omap44xx_timer1_hwmod,
+        &omap44xx_timer2_hwmod,
+        &omap44xx_timer3_hwmod,
+        &omap44xx_timer4_hwmod,
+        &omap44xx_timer5_hwmod,
+        &omap44xx_timer6_hwmod,
+        &omap44xx_timer7_hwmod,
+        &omap44xx_timer8_hwmod,
+        &omap44xx_timer9_hwmod,
+        &omap44xx_timer10_hwmod,
+        &omap44xx_timer11_hwmod,
+
         /* uart class */
         &omap44xx_uart1_hwmod,
         &omap44xx_uart2_hwmod,
         &omap44xx_uart3_hwmod,
         &omap44xx_uart4_hwmod,
 
+        /* usb_otg_hs class */
+        &omap44xx_usb_otg_hs_hwmod,
+
         /* wd_timer class */
         &omap44xx_wd_timer2_hwmod,
         &omap44xx_wd_timer3_hwmod,
@@ -2073,6 +5125,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 int __init omap44xx_hwmod_init(void)
 {
-        return omap_hwmod_init(omap44xx_hwmods);
+        return omap_hwmod_register(omap44xx_hwmods);
 }
 
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 745252c60e32..f172ec06c06a 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -29,6 +29,7 @@
 #include <linux/usb.h>
 
 #include <plat/usb.h>
+#include "control.h"
 
 /* OMAP control module register for UTMI PHY */
 #define CONTROL_DEV_CONF                0x300
@@ -147,3 +148,95 @@ int omap4430_phy_exit(struct device *dev)
 
         return 0;
 }
+
+void am35x_musb_reset(void)
+{
+        u32     regval;
+
+        /* Reset the musb interface */
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+
+        regval |= AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+
+        regval &= ~AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+}
+
+void am35x_musb_phy_power(u8 on)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(100);
+        u32 devconf2;
+
+        if (on) {
+                /*
+                 * Start the on-chip PHY and its PLL.
+                 */
+                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+                devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+                devconf2 |= CONF2_PHY_PLLON;
+
+                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+
+                pr_info(KERN_INFO "Waiting for PHY clock good...\n");
+                while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
+                                & CONF2_PHYCLKGD)) {
+                        cpu_relax();
+
+                        if (time_after(jiffies, timeout)) {
+                                pr_err(KERN_ERR "musb PHY clock good timed out\n");
+                                break;
+                        }
+                }
+        } else {
+                /*
+                 * Power down the on-chip PHY.
+                 */
+                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+                devconf2 &= ~CONF2_PHY_PLLON;
+                devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
+                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+        }
+}
+
+void am35x_musb_clear_irq(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval |= AM35XX_USBOTGSS_INT_CLR;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+void am35x_musb_set_mode(u8 musb_mode)
+{
+        u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        devconf2 &= ~CONF2_OTGMODE;
+        switch (musb_mode) {
+#ifdef  CONFIG_USB_MUSB_HDRC_HCD
+        case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
+                devconf2 |= CONF2_FORCE_HOST;
+                break;
+#endif
+#ifdef  CONFIG_USB_GADGET_MUSB_HDRC
+        case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
+                devconf2 |= CONF2_FORCE_DEVICE;
+                break;
+#endif
+#ifdef  CONFIG_USB_MUSB_OTG
+        case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
+                devconf2 |= CONF2_NO_OVERRIDE;
+                break;
+#endif
+        default:
+                pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
+        }
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 38b730550506..8affc66a92c2 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -418,7 +418,7 @@ struct prcm_config {
 
 extern const struct prcm_config omap2420_rate_table[];
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 extern const struct prcm_config omap2430_rate_table[];
 #else
 #define omap2430_rate_table     NULL
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 9b1a33500577..78739e10f5b9 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -78,7 +78,7 @@ static struct powerdomain core_24xx_pwrdm = {
  * 2430-specific powerdomains
  */
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 
 /* XXX 2430 KILLDOMAINWKUP bit?  No current users apparently */
 
@@ -97,7 +97,7 @@ static struct powerdomain mdm_pwrdm = {
         },
 };
 
-#endif     /* CONFIG_ARCH_OMAP2430 */
+#endif     /* CONFIG_SOC_OMAP2430 */
 
 /* As powerdomains are added or removed above, this list must also be changed */
 static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
@@ -111,7 +111,7 @@ static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
         &core_24xx_pwrdm,
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
         &mdm_pwrdm,
 #endif
         NULL
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 679bcd28576e..6be14389e4f3 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 
+#include <mach/system.h>
 #include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
@@ -57,7 +58,7 @@ u32 omap_prcm_get_reset_sources(void)
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
 /* Resets clock rates and reboots the system. Only called from system.h */
-void omap_prcm_arch_reset(char mode, const char *cmd)
+static void omap_prcm_arch_reset(char mode, const char *cmd)
 {
         s16 prcm_offs = 0;
 
@@ -108,6 +109,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
         omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
 }
 
+void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
+
 /**
  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
  * @reg: physical address of module IDLEST register
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 32e91a9c8b6b..1ac361b7b8cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 mod_timer(&uart->timer, jiffies + uart->timeout);
         omap_uart_smart_idle_enable(uart, 0);
 
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
                 u32 wk_mask = 0;
                 u32 padconf = 0;
@@ -655,7 +655,7 @@ static void serial_out_override(struct uart_port *up, int offset, int value)
 }
 #endif
 
-void __init omap_serial_early_init(void)
+static int __init omap_serial_early_init(void)
 {
         int i = 0;
 
@@ -672,7 +672,7 @@ void __init omap_serial_early_init(void)
 
                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
                 if (WARN_ON(!uart))
-                        return;
+                        return -ENODEV;
 
                 uart->oh = oh;
                 uart->num = i++;
@@ -680,7 +680,7 @@ void __init omap_serial_early_init(void)
                 num_uarts++;
 
                 /*
-                 * NOTE: omap_hwmod_init() has not yet been called,
+                 * NOTE: omap_hwmod_setup*() has not yet been called,
                  *       so no hwmod functions will work yet.
                  */
 
@@ -691,7 +691,10 @@ void __init omap_serial_early_init(void)
                  */
                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
         } while (1);
+
+        return 0;
 }
+core_initcall(omap_serial_early_init);
 
 /**
  * omap_serial_init_port() - initialize single serial port
@@ -759,13 +762,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         p->private_data = uart;
 
         /*
-         * omap44xx: Never read empty UART fifo
+         * omap44xx, ti816x: Never read empty UART fifo
          * omap3xxx: Never read empty UART fifo on UARTs
          * with IP rev >=0x52
          */
         uart->regshift = p->regshift;
         uart->membase = p->membase;
-        if (cpu_is_omap44xx())
+        if (cpu_is_omap44xx() || cpu_is_ti816x())
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@@ -847,7 +850,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         }
 
         /* Enable the MDR1 errata for OMAP3 */
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx() && !cpu_is_ti816x())
                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 0fc550e7e482..3b9cf85f4bb9 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -40,10 +40,11 @@
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
 
 #include "timer-gp.h"
 
-#include <plat/common.h>
 
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
@@ -133,9 +134,13 @@ static void __init omap2_gp_clockevent_init(void)
 {
         u32 tick_rate;
         int src;
+        char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
 
         inited = 1;
 
+        sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
+        omap_hwmod_setup_one(clockevent_hwmod_name);
+
         gptimer = omap_dm_timer_request_specific(gptimer_id);
         BUG_ON(gptimer == NULL);
         gptimer_wakeup = gptimer;
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 5298949d4b11..a9d4d143086d 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -30,118 +30,11 @@
 #include <mach/irqs.h>
 #include <mach/am35xx.h>
 #include <plat/usb.h>
-#include "control.h"
+#include <plat/omap_device.h>
+#include "mux.h"
 
 #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
 
-static void am35x_musb_reset(void)
-{
-        u32     regval;
-
-        /* Reset the musb interface */
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-        regval |= AM35XX_USBOTGSS_SW_RST;
-        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-
-        regval &= ~AM35XX_USBOTGSS_SW_RST;
-        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-}
-
-static void am35x_musb_phy_power(u8 on)
-{
-        unsigned long timeout = jiffies + msecs_to_jiffies(100);
-        u32 devconf2;
-
-        if (on) {
-                /*
-                 * Start the on-chip PHY and its PLL.
-                 */
-                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
-
-                devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
-                devconf2 |= CONF2_PHY_PLLON;
-
-                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
-
-                pr_info(KERN_INFO "Waiting for PHY clock good...\n");
-                while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
-                                & CONF2_PHYCLKGD)) {
-                        cpu_relax();
-
-                        if (time_after(jiffies, timeout)) {
-                                pr_err(KERN_ERR "musb PHY clock good timed out\n");
-                                break;
-                        }
-                }
-        } else {
-                /*
-                 * Power down the on-chip PHY.
-                 */
-                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
-
-                devconf2 &= ~CONF2_PHY_PLLON;
-                devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
-                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
-        }
-}
-
-static void am35x_musb_clear_irq(void)
-{
-        u32 regval;
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval |= AM35XX_USBOTGSS_INT_CLR;
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am35x_musb_set_mode(u8 musb_mode)
-{
-        u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
-
-        devconf2 &= ~CONF2_OTGMODE;
-        switch (musb_mode) {
-#ifdef  CONFIG_USB_MUSB_HDRC_HCD
-        case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
-                devconf2 |= CONF2_FORCE_HOST;
-                break;
-#endif
-#ifdef  CONFIG_USB_GADGET_MUSB_HDRC
-        case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
-                devconf2 |= CONF2_FORCE_DEVICE;
-                break;
-#endif
-#ifdef  CONFIG_USB_MUSB_OTG
-        case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
-                devconf2 |= CONF2_NO_OVERRIDE;
-                break;
-#endif
-        default:
-                pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
-        }
-
-        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
-}
-
-static struct resource musb_resources[] = {
-        [0] = { /* start and end set dynamically */
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = { /* general IRQ */
-                .start  = INT_243X_HS_USB_MC,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "mc",
-        },
-        [2] = { /* DMA IRQ */
-                .start  = INT_243X_HS_USB_DMA,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "dma",
-        },
-};
-
 static struct musb_hdrc_config musb_config = {
         .multipoint     = 1,
         .dyn_fifo       = 1,
@@ -169,38 +62,65 @@ static struct musb_hdrc_platform_data musb_plat = {
 
 static u64 musb_dmamask = DMA_BIT_MASK(32);
 
-static struct platform_device musb_device = {
-        .name           = "musb-omap2430",
-        .id             = -1,
-        .dev = {
-                .dma_mask               = &musb_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &musb_plat,
+static struct omap_device_pm_latency omap_musb_latency[] = {
+        {
+                .deactivate_func        = omap_device_idle_hwmods,
+                .activate_func          = omap_device_enable_hwmods,
+                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
-        .num_resources  = ARRAY_SIZE(musb_resources),
-        .resource       = musb_resources,
 };
 
+static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
+{
+        switch (board_data->interface_type) {
+        case MUSB_INTERFACE_UTMI:
+                omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT);
+                omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT);
+                break;
+        case MUSB_INTERFACE_ULPI:
+                omap_mux_init_signal("usba0_ulpiphy_clk",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_stp",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dir",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_nxt",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat0",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat1",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat2",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat3",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat4",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat5",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat6",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usba0_ulpiphy_dat7",
+                                                OMAP_PIN_INPUT_PULLDOWN);
+                break;
+        default:
+                break;
+        }
+}
+
 void __init usb_musb_init(struct omap_musb_board_data *board_data)
 {
-        if (cpu_is_omap243x()) {
-                musb_resources[0].start = OMAP243X_HS_BASE;
-        } else if (cpu_is_omap3517() || cpu_is_omap3505()) {
-                musb_device.name = "musb-am35x";
-                musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
-                musb_resources[1].start = INT_35XX_USBOTG_IRQ;
-                board_data->set_phy_power = am35x_musb_phy_power;
-                board_data->clear_irq = am35x_musb_clear_irq;
-                board_data->set_mode = am35x_musb_set_mode;
-                board_data->reset = am35x_musb_reset;
-        } else if (cpu_is_omap34xx()) {
-                musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
+        struct omap_hwmod               *oh;
+        struct omap_device              *od;
+        struct platform_device          *pdev;
+        struct device                   *dev;
+        int                             bus_id = -1;
+        const char                      *oh_name, *name;
+
+        if (cpu_is_omap3517() || cpu_is_omap3505()) {
         } else if (cpu_is_omap44xx()) {
-                musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
-                musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
-                musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
+                usb_musb_mux_init(board_data);
         }
-        musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
 
         /*
          * REVISIT: This line can be removed once all the platforms using
@@ -212,8 +132,35 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
         musb_plat.mode = board_data->mode;
         musb_plat.extvbus = board_data->extvbus;
 
-        if (platform_device_register(&musb_device) < 0)
-                printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
+        if (cpu_is_omap3517() || cpu_is_omap3505()) {
+                oh_name = "am35x_otg_hs";
+                name = "musb-am35x";
+        } else {
+                oh_name = "usb_otg_hs";
+                name = "musb-omap2430";
+        }
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return;
+        }
+
+        od = omap_device_build(name, bus_id, oh, &musb_plat,
+                               sizeof(musb_plat), omap_musb_latency,
+                               ARRAY_SIZE(omap_musb_latency), false);
+        if (IS_ERR(od)) {
+                pr_err("Could not build omap_device for %s %s\n",
+                                                name, oh_name);
+                return;
+        }
+
+        pdev = &od->pdev;
+        dev = &pdev->dev;
+        get_device(dev);
+        dev->dma_mask = &musb_dmamask;
+        dev->coherent_dma_mask = musb_dmamask;
+        put_device(dev);
 }
 
 #else
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f04731820301..d9f10a31e604 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -24,10 +24,11 @@
 
 #define NO_LENGTH_CHECK 0xffffffff
 
-struct omap_board_config_kernel *omap_board_config;
+struct omap_board_config_kernel *omap_board_config __initdata;
 int omap_board_config_size;
 
-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
+static const void *__init get_config(u16 tag, size_t len,
+                int skip, size_t *len_out)
 {
         struct omap_board_config_kernel *kinfo = NULL;
         int i;
@@ -49,17 +50,15 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
         return kinfo->data;
 }
 
-const void *__omap_get_config(u16 tag, size_t len, int nr)
+const void *__init __omap_get_config(u16 tag, size_t len, int nr)
 {
         return get_config(tag, len, nr, NULL);
 }
-EXPORT_SYMBOL(__omap_get_config);
 
-const void *omap_get_var_config(u16 tag, size_t *len)
+const void *__init omap_get_var_config(u16 tag, size_t *len)
 {
         return get_config(tag, NO_LENGTH_CHECK, 0, len);
 }
-EXPORT_SYMBOL(omap_get_var_config);
 
 void __init omap_reserve(void)
 {
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 862dda95d61d..f7fed6080190 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -54,7 +54,7 @@ static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
 #define omap16xx_32k_read       NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
@@ -63,7 +63,7 @@ static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
 #define omap2420_32k_read       NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 85363084cc1a..2ec3b5d9f214 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -134,7 +134,7 @@ static inline void omap_enable_channel_irq(int lch);
 
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-int omap_dma_in_1510_mode(void)
+static int omap_dma_in_1510_mode(void)
 {
         return enable_1510_mode;
 }
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a4f8003de664..3341ca4703e9 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -112,6 +112,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
 }
 
 
+#ifdef CONFIG_ARCH_OMAP2PLUS
 /*
  * XXX This function is a temporary compatibility wrapper - only
  * needed until the I2C driver can be converted to call
@@ -130,7 +131,6 @@ static struct omap_device_pm_latency omap_i2c_latency[] = {
         },
 };
 
-#ifdef CONFIG_ARCH_OMAP2PLUS
 static inline int omap2_i2c_add_bus(int bus_id)
 {
         int l;
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 3cf4fa25ab3d..97126dfd2888 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -151,14 +151,14 @@ struct omap_board_config_kernel {
         const void *data;
 };
 
-extern const void *__omap_get_config(u16 tag, size_t len, int nr);
+extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
 
 #define omap_get_config(tag, type) \
         ((const type *) __omap_get_config((tag), sizeof(type), 0))
 #define omap_get_nr_config(tag, type, nr) \
         ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
 
-extern const void *omap_get_var_config(u16 tag, size_t *len);
+extern const void *__init omap_get_var_config(u16 tag, size_t *len);
 
 extern struct omap_board_config_kernel *omap_board_config;
 extern int omap_board_config_size;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 256ab3f1ec8f..f1899a3e4174 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -38,6 +38,7 @@ struct omap_clk {
 #define CK_3517         (1 << 9)
 #define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
 #define CK_443X         (1 << 11)
+#define CK_TI816X       (1 << 12)
 
 
 #define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0adab19ea..d43e6234dbbb 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -53,6 +53,7 @@ struct clkops {
 #define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
 #define RATE_IN_36XX            (1 << 4)
 #define RATE_IN_4430            (1 << 5)
+#define RATE_IN_TI816X          (1 << 6)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 29b2afb4288f..1dd97e7461c9 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -66,6 +66,7 @@ void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
+void omap2_set_globals_ti816x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 3fd8b4055727..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2004, 2008 Nokia Corporation
  *
- * Copyright (C) 2009 Texas Instruments.
+ * Copyright (C) 2009-11 Texas Instruments.
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
@@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void)		\
         return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
 }
 
+#define IS_TI_SUBCLASS(subclass, id)                    \
+static inline int is_ti ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
@@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 
+IS_TI_SUBCLASS(816x, 0x816)
+
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
 #define cpu_is_omap16xx()               0
@@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_ti816x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 
@@ -170,11 +179,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             is_omap24xx()
 # endif
-# if defined (CONFIG_ARCH_OMAP2420)
+# if defined (CONFIG_SOC_OMAP2420)
 #  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             is_omap242x()
 # endif
-# if defined (CONFIG_ARCH_OMAP2430)
+# if defined (CONFIG_SOC_OMAP2430)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             is_omap243x()
 # endif
@@ -189,11 +198,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP2420)
+# if defined(CONFIG_SOC_OMAP2420)
 #  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP2430)
+# if defined(CONFIG_SOC_OMAP2430)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             1
 # endif
@@ -201,7 +210,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap34xx
 #  define cpu_is_omap34xx()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP3430)
+# if defined(CONFIG_SOC_OMAP3430)
 #  undef  cpu_is_omap343x
 #  define cpu_is_omap343x()             1
 # endif
@@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3530
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
+# undef cpu_is_ti816x
 # define cpu_is_omap3430()              is_omap3430()
 # define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
                                                 (!omap3_has_iva()) &&   \
@@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # define cpu_is_omap3517()              is_omap3517()
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti816x()                is_ti816x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
@@ -389,9 +400,15 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
 #define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
 
+#define TI816X_CLASS            0x81600034
+#define TI8168_REV_ES1_0        TI816X_CLASS
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+
 #define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      OMAP443X_CLASS
-#define OMAP4430_REV_ES2_0      0x44301044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
 
 /*
  * omap_chip bits
@@ -419,11 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP3630ES1_1           (1 << 9)
 #define CHIP_IS_OMAP3630ES1_2           (1 << 10)
 #define CHIP_IS_OMAP4430ES2             (1 << 11)
+#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
+#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
+#define CHIP_IS_TI816X                  (1 << 14)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 | \
-                                                 CHIP_IS_OMAP4430ES2)
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
+                                         CHIP_IS_OMAP4430ES2 |          \
+                                         CHIP_IS_OMAP4430ES2_1 |        \
+                                         CHIP_IS_OMAP4430ES2_2)
 
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
@@ -455,6 +477,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_ISP                   BIT(4)
 #define OMAP3_HAS_192MHZ_CLK            BIT(5)
 #define OMAP3_HAS_IO_WAKEUP             BIT(6)
+#define OMAP3_HAS_SDRC                  BIT(7)
 
 #define OMAP3_HAS_FEATURE(feat,flag)                    \
 static inline unsigned int omap3_has_ ##feat(void)      \
@@ -469,5 +492,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
 OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
 OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 537f4e449f50..0f140ecedb01 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -23,6 +23,7 @@
 #include <linux/list.h>
 #include <linux/kobject.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 #include <asm/atomic.h>
 
 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
@@ -226,6 +227,16 @@ struct omap_dss_board_info {
         struct omap_dss_device *default_device;
 };
 
+#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
+/* Init with the board info */
+extern int omap_display_init(struct omap_dss_board_info *board_data);
+#else
+static inline int omap_display_init(struct omap_dss_board_info *board_data)
+{
+        return 0;
+}
+#endif
+
 struct omap_video_timings {
         /* Unit: pixels */
         u16 x_res;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dfa3aff9761b..d6c70d2f4030 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,12 @@
  *
  * OMAP Dual-Mode Timers
  *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Platform device conversion and hwmod support.
+ *
  * Copyright (C) 2005 Nokia Corporation
  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  * PWM and clock framwork support by Timo Teras.
@@ -44,6 +50,11 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
+/*
+ * IP revision identifier so that Highlander IP
+ * in OMAP4 can be distinguished.
+ */
+#define OMAP_TIMER_IP_VERSION_1                        0x1
 struct omap_dm_timer;
 extern struct omap_dm_timer *gptimer_wakeup;
 extern struct sys_timer omap_timer;
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index ae39bcb3f5ba..bd3c6324ae1f 100644
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
@@ -30,18 +30,18 @@ extern void omap1510_fpga_init_irq(void);
  * ---------------------------------------------------------------------------
  */
 /* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
+#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
 #define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
 #define H2P2_DBG_FPGA_START             0x04000000              /* PA */
 
 #define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
+#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
+#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
 
 /* NOTE:  most boards don't have a static mapping for the FPGA ... */
 struct h2p2_dbg_fpga {
@@ -81,55 +81,55 @@ struct h2p2_dbg_fpga {
  *  OMAP-1510 FPGA
  * ---------------------------------------------------------------------------
  */
-#define OMAP1510_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
+#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
 #define OMAP1510_FPGA_SIZE              SZ_4K
 #define OMAP1510_FPGA_START             0x08000000              /* PA */
 
 /* Revision */
-#define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
+#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
 
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
 
 /* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
+#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
 
 /* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
+#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
 
 /* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
-
-#define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
-
-#define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
-
-#define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
+#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
 
 #define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
 
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 85ded598853e..12b316165037 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
 #define GPMC_NAND_ADDRESS       0x0000000b
 #define GPMC_NAND_DATA          0x0000000c
 
+#define GPMC_ENABLE_IRQ         0x0000000d
+
 /* ECC commands */
 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
@@ -78,6 +80,19 @@
 #define WR_RD_PIN_MONITORING            0x00600000
 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      ((val >> 24) & 0x7F)
 #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define GPMC_IRQ_FIFOEVENTENABLE        0x01
+#define GPMC_IRQ_COUNT_EVENT            0x02
+
+#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
+#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
+
+enum omap_ecc {
+                /* 1-bit ecc: stored at end of spare area */
+        OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+        OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
+                /* 1-bit ecc: stored at begining of spare area as romcode */
+        OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+};
 
 /*
  * Note that all values in this struct are in nanoseconds except sync_clk
@@ -130,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern int gpmc_prefetch_enable(int cs, int dma_mode,
+extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                         unsigned int u32_count, int is_write);
 extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern void gpmc_init(void);
 extern int gpmc_read_status(int cmd);
 extern int gpmc_cs_configure(int cs, int cmd, int wval);
 extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index d5b26adfb890..e87efe1499b8 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,5 +286,6 @@
 #include <plat/omap24xx.h>
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
+#include <plat/ti816x.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index ef4106c13183..d72ec85c97e6 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -259,7 +259,7 @@ struct omap_sdrc_params;
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
 static inline void omap242x_map_common_io(void)
@@ -267,7 +267,7 @@ static inline void omap242x_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 extern void omap243x_map_common_io(void);
 #else
 static inline void omap243x_map_common_io(void)
@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPTI816X
+extern void omapti816x_map_common_io(void);
+#else
+static inline void omapti816x_map_common_io(void)
+{
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d685538..19cbb5e9ece2 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -154,6 +154,8 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
 
 extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
+                                   u32 **ppte);
 extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
 
 extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2910de921c52..1b911681e911 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -318,6 +318,7 @@
 #define INT_34XX_PRCM_MPU_IRQ   11
 #define INT_34XX_MCBSP1_IRQ     16
 #define INT_34XX_MCBSP2_IRQ     17
+#define INT_34XX_GPMC_IRQ       20
 #define INT_34XX_MCBSP3_IRQ     22
 #define INT_34XX_MCBSP4_IRQ     23
 #define INT_34XX_CAM_IRQ        24
@@ -411,7 +412,13 @@
 #define TWL_IRQ_END             TWL6030_IRQ_END
 #endif
 
-#define NR_IRQS                 TWL_IRQ_END
+/* GPMC related */
+#define OMAP_GPMC_IRQ_BASE      (TWL_IRQ_END)
+#define OMAP_GPMC_NR_IRQS       7
+#define OMAP_GPMC_IRQ_END       (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
+
+
+#define NR_IRQS                 OMAP_GPMC_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
new file mode 100644
index 000000000000..b8b5641379b0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+
+/* L3 CONNIDs */
+/* Display Sub system (DSS) */
+#define OMAP2_L3_CORE_FW_CONNID_DSS                     8
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
new file mode 100644
index 000000000000..cde1938c5f82
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+
+/* L3 Initiator IDs */
+/* Display Sub system (DSS) */
+#define OMAP3_L3_CORE_FW_INIT_ID_DSS                    29
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
new file mode 100644
index 000000000000..3f39cf8a35c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+
+/* L4 CORE */
+/* Display Sub system (DSS) */
+#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION                     28
+#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION                    29
+#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION                     30
+#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION                     31
+#define OMAP2420_L4_CORE_FW_DSS_TA_REGION                       32
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
index 5e1949375422..881a858b1ffc 100644
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -21,4 +21,14 @@
 #define OMAP3_L4_CORE_FW_I2C3_REGION                            73
 #define OMAP3_L4_CORE_FW_I2C3_TA_REGION                         74
 
+/* Display Sub system (DSS) */
+#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP                         2
+
+#define OMAP3_L4_CORE_FW_DSS_DSI_REGION                         104
+#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION                     3
+#define OMAP3_L4_CORE_FW_DSS_CORE_REGION                        4
+#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION                       4
+#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION                        5
+#define OMAP3_L4_CORE_FW_DSS_VENC_REGION                        6
+#define OMAP3_L4_CORE_FW_DSS_TA_REGION                          7
 #endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b87d83ccd545..6ecf1051e5f4 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -106,13 +106,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_MCBSP_REG_XCCR     0x00
 #define OMAP_MCBSP_REG_RCCR     0x00
 
-#define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
-
-#define AUDIO_MCBSP             OMAP_MCBSP1
-#define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
-#define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
-
 #else
 
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -168,13 +161,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_ST_REG_SFIRCR      0x28
 #define OMAP_ST_REG_SSELCR      0x2C
 
-#define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
-
-#define AUDIO_MCBSP             OMAP_MCBSP2
-#define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
-#define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
-
 #endif
 
 /************************** McBSP SPCR1 bit definitions ***********************/
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..3d51b18131cc 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -1,8 +1,19 @@
 #ifndef _OMAP2_MCSPI_H
 #define _OMAP2_MCSPI_H
 
+#define OMAP2_MCSPI_REV 0
+#define OMAP3_MCSPI_REV 1
+#define OMAP4_MCSPI_REV 2
+
+#define OMAP4_MCSPI_REG_OFFSET 0x100
+
 struct omap2_mcspi_platform_config {
         unsigned short  num_cs;
+        unsigned int regs_offset;
+};
+
+struct omap2_mcspi_dev_attr {
+        unsigned short num_chipselect;
 };
 
 struct omap2_mcspi_device_config {
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index ffd909fa5287..999ffba2690c 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -66,7 +66,7 @@
 #  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
 #  define MULTI_OMAP2
@@ -74,7 +74,7 @@
 #  define OMAP_NAME omap2420
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
 #  define MULTI_OMAP2
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
  * published by the Free Software Foundation.
  */
 
+#include <plat/gpmc.h>
 #include <linux/mtd/partitions.h>
 
+enum nand_io {
+        NAND_OMAP_PREFETCH_POLLED = 0,  /* prefetch polled mode, default */
+        NAND_OMAP_POLLED,               /* polled mode, without prefetch */
+        NAND_OMAP_PREFETCH_DMA,         /* prefetch enabled sDMA mode */
+        NAND_OMAP_PREFETCH_IRQ          /* prefetch enabled irq mode */
+};
+
 struct omap_nand_platform_data {
         unsigned int            options;
         int                     cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
         int                     (*nand_setup)(void);
         int                     (*dev_ready)(struct omap_nand_platform_data *);
         int                     dma_channel;
+        int                     gpmc_irq;
+        enum nand_io            xfer_type;
         unsigned long           phys_base;
         int                     devsize;
+        enum omap_ecc           ecc_opt;
 };
 
 /* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1eee85a8abb3..f96e72ed4db1 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod macros, structures
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -30,6 +30,7 @@
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 
 #include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
@@ -370,8 +371,10 @@ struct omap_hwmod_omap4_prcm {
  *     of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
+ *     XXX Should be HWMOD_SETUP_NO_RESET
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
  *     controller, etc. XXX probably belongs outside the main hwmod file
+ *     XXX Should be HWMOD_SETUP_NO_IDLE
  * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
  *     when module is enabled, rather than the default, which is to
  *     enable autoidle
@@ -535,11 +538,12 @@ struct omap_hwmod {
         const struct omap_chip_id       omap_chip;
 };
 
-int omap_hwmod_init(struct omap_hwmod **ohs);
+int omap_hwmod_register(struct omap_hwmod **ohs);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                         void *data);
-int omap_hwmod_late_init(void);
+
+int __init omap_hwmod_setup_one(const char *name);
 
 int omap_hwmod_enable(struct omap_hwmod *oh);
 int _omap_hwmod_enable(struct omap_hwmod *oh);
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index affe87e9ece7..cbe897ca7f9e 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,12 +15,20 @@
 #define ONENAND_SYNC_READ       (1 << 0)
 #define ONENAND_SYNC_READWRITE  (1 << 1)
 
+struct onenand_freq_info {
+        u16                     maf_id;
+        u16                     dev_id;
+        u16                     ver_id;
+};
+
 struct omap_onenand_platform_data {
         int                     cs;
         int                     gpio_irq;
         struct mtd_partition    *parts;
         int                     nr_parts;
-        int                     (*onenand_setup)(void __iomem *, int freq);
+        int                     (*onenand_setup)(void __iomem *, int *freq_ptr);
+        int             (*get_freq)(const struct onenand_freq_info *freq_info,
+                                    bool *clk_dep);
         int                     dma_channel;
         u8                      flags;
         u8                      regulator_can_sleep;
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 2fdf8c80d390..267f43bb2a4e 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -28,7 +28,6 @@
 #define __ASM_ARM_ARCH_OMAP_PRCM_H
 
 u32 omap_prcm_get_reset_sources(void);
-void omap_prcm_arch_reset(char mode, const char *cmd);
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                          const char *name);
 
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index efd87c8dda69..925b12b500dc 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -124,8 +124,14 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                             struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
+
 int omap2_sdrc_get_params(unsigned long r,
                           struct omap_sdrc_params **sdrc_cs0,
                           struct omap_sdrc_params **sdrc_cs1);
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index cec5d56db2eb..8061695aa523 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,6 +51,11 @@
 #define OMAP4_UART3_BASE        0x48020000
 #define OMAP4_UART4_BASE        0x4806e000
 
+/* TI816X serial ports */
+#define TI816X_UART1_BASE       0x48020000
+#define TI816X_UART2_BASE       0x48022000
+#define TI816X_UART3_BASE       0x48024000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -81,6 +86,9 @@
 #define OMAP4UART2              OMAP2UART2
 #define OMAP4UART3              43
 #define OMAP4UART4              44
+#define TI816XUART1             81
+#define TI816XUART2             82
+#define TI816XUART3             83
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
@@ -96,7 +104,6 @@
 
 struct omap_board_data;
 
-extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
 extern void omap_serial_init_port(struct omap_board_data *bdata);
 extern int omap_uart_can_sleep(void);
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
index d0a119f735b4..c5fa9e929009 100644
--- a/arch/arm/plat-omap/include/plat/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -4,48 +4,14 @@
  */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/clk.h>
 
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-
-#include <plat/prcm.h>
-
-#ifndef CONFIG_MACH_VOICEBLUE
-#define voiceblue_reset()               do {} while (0)
-#else
-extern void voiceblue_reset(void);
-#endif
+#include <asm/proc-fns.h>
 
 static inline void arch_idle(void)
 {
         cpu_do_idle();
 }
 
-static inline void omap1_arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
-         * "Global Software Reset Affects Traffic Controller Frequency".
-         */
-        if (cpu_is_omap5912()) {
-                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
-                                 DPLL_CTL);
-                omap_writew(0x8, ARM_RSTCT1);
-        }
-
-        if (machine_is_voiceblue())
-                voiceblue_reset();
-        else
-                omap_writew(1, ARM_RSTCT1);
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (!cpu_class_is_omap2())
-                omap1_arch_reset(mode, cmd);
-        else
-                omap_prcm_arch_reset(mode, cmd);
-}
+extern void (*arch_reset)(char, const char *);
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
new file mode 100644
index 000000000000..50510f5dda1e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ti816x.h
@@ -0,0 +1,27 @@
+/*
+ * This file contains the address data for various TI816X modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TI816X_H
+#define __ASM_ARCH_TI816X_H
+
+#define L4_SLOW_TI816X_BASE     0x48000000
+
+#define TI816X_SCM_BASE         0x48140000
+#define TI816X_CTRL_BASE        TI816X_SCM_BASE
+#define TI816X_PRCM_BASE        0x48180000
+
+#define TI816X_ARM_INTC_BASE    0x48200000
+
+#endif /* __ASM_ARCH_TI816X_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ad98b85cae21..30b891c4a93f 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,6 +93,10 @@ static inline void flush(void)
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
 
+#define DEBUG_LL_TI816X(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI816XUART##p)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
         int port = 0;
@@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_ZOOM(omap_zoom2);
                 DEBUG_LL_ZOOM(omap_zoom3);
 
+                /* TI8168 base boards using UART3 */
+                DEBUG_LL_TI816X(3, ti8168evm);
+
         } while (0);
 }
 
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 450a332f1009..077192759afc 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -91,6 +91,10 @@ extern int omap4430_phy_exit(struct device *dev);
 
 #endif
 
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+extern void am35x_musb_set_mode(u8 musb_mode);
 
 /*
  * FIXME correct answer depends on hmc_mode,
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1295fafcd31..f1ecfa9fc61d 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_ti816x()) {
+                if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+                        return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+        } else if (cpu_is_omap34xx()) {
                 if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
                         return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
                 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e26e50487d60..9d80064e979b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -312,7 +312,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static int __init omap242x_sram_init(void)
 {
         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
@@ -333,7 +333,7 @@ static inline int omap242x_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static int __init omap243x_sram_init(void)
 {
         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static int __init omap44xx_sram_init(void)
-{
-        printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
-
-        return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
-        return 0;
-}
-#endif
-
 int __init omap_sram_init(void)
 {
         omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
                 omap243x_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
-        else if (cpu_is_omap44xx())
-                omap44xx_sram_init();
 
         return 0;
 }
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9bfb71ff3a6a..177c7d156933 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -117,4 +117,6 @@ source "drivers/staging/Kconfig"
 source "drivers/platform/Kconfig"
 
 source "drivers/clk/Kconfig"
+
+source "drivers/hwspinlock/Kconfig"
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index b423bb16c3a8..3f135b6fb014 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -117,3 +117,5 @@ obj-y				+= platform/
 obj-y                           += ieee802154/
 #common clk code
 obj-y                           += clk/
+
+obj-$(CONFIG_HWSPINLOCK)        += hwspinlock/
diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
new file mode 100644
index 000000000000..eb4af28f8567
--- /dev/null
+++ b/drivers/hwspinlock/Kconfig
@@ -0,0 +1,22 @@
+#
+# Generic HWSPINLOCK framework
+#
+
+config HWSPINLOCK
+        tristate "Generic Hardware Spinlock framework"
+        help
+          Say y here to support the generic hardware spinlock framework.
+          You only need to enable this if you have hardware spinlock module
+          on your system (usually only relevant if your system has remote slave
+          coprocessors).
+
+          If unsure, say N.
+
+config HWSPINLOCK_OMAP
+        tristate "OMAP Hardware Spinlock device"
+        depends on HWSPINLOCK && ARCH_OMAP4
+        help
+          Say y here to support the OMAP Hardware Spinlock device (firstly
+          introduced in OMAP4).
+
+          If unsure, say N.
diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
new file mode 100644
index 000000000000..5729a3f7ed3d
--- /dev/null
+++ b/drivers/hwspinlock/Makefile
@@ -0,0 +1,6 @@
+#
+# Generic Hardware Spinlock framework
+#
+
+obj-$(CONFIG_HWSPINLOCK)                += hwspinlock_core.o
+obj-$(CONFIG_HWSPINLOCK_OMAP)           += omap_hwspinlock.o
diff --git a/drivers/hwspinlock/hwspinlock_core.c b/drivers/hwspinlock/hwspinlock_core.c
new file mode 100644
index 000000000000..43a62714b4fb
--- /dev/null
+++ b/drivers/hwspinlock/hwspinlock_core.c
@@ -0,0 +1,548 @@
+/*
+ * Hardware spinlock framework
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Contact: Ohad Ben-Cohen <ohad@wizery.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)    "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/jiffies.h>
+#include <linux/radix-tree.h>
+#include <linux/hwspinlock.h>
+#include <linux/pm_runtime.h>
+
+#include "hwspinlock_internal.h"
+
+/* radix tree tags */
+#define HWSPINLOCK_UNUSED       (0) /* tags an hwspinlock as unused */
+
+/*
+ * A radix tree is used to maintain the available hwspinlock instances.
+ * The tree associates hwspinlock pointers with their integer key id,
+ * and provides easy-to-use API which makes the hwspinlock core code simple
+ * and easy to read.
+ *
+ * Radix trees are quick on lookups, and reasonably efficient in terms of
+ * storage, especially with high density usages such as this framework
+ * requires (a continuous range of integer keys, beginning with zero, is
+ * used as the ID's of the hwspinlock instances).
+ *
+ * The radix tree API supports tagging items in the tree, which this
+ * framework uses to mark unused hwspinlock instances (see the
+ * HWSPINLOCK_UNUSED tag above). As a result, the process of querying the
+ * tree, looking for an unused hwspinlock instance, is now reduced to a
+ * single radix tree API call.
+ */
+static RADIX_TREE(hwspinlock_tree, GFP_KERNEL);
+
+/*
+ * Synchronization of access to the tree is achieved using this spinlock,
+ * as the radix-tree API requires that users provide all synchronisation.
+ */
+static DEFINE_SPINLOCK(hwspinlock_tree_lock);
+
+/**
+ * __hwspin_trylock() - attempt to lock a specific hwspinlock
+ * @hwlock: an hwspinlock which we want to trylock
+ * @mode: controls whether local interrupts are disabled or not
+ * @flags: a pointer where the caller's interrupt state will be saved at (if
+ *         requested)
+ *
+ * This function attempts to lock an hwspinlock, and will immediately
+ * fail if the hwspinlock is already taken.
+ *
+ * Upon a successful return from this function, preemption (and possibly
+ * interrupts) is disabled, so the caller must not sleep, and is advised to
+ * release the hwspinlock as soon as possible. This is required in order to
+ * minimize remote cores polling on the hardware interconnect.
+ *
+ * The user decides whether local interrupts are disabled or not, and if yes,
+ * whether he wants their previous state to be saved. It is up to the user
+ * to choose the appropriate @mode of operation, exactly the same way users
+ * should decide between spin_trylock, spin_trylock_irq and
+ * spin_trylock_irqsave.
+ *
+ * Returns 0 if we successfully locked the hwspinlock or -EBUSY if
+ * the hwspinlock was already taken.
+ * This function will never sleep.
+ */
+int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
+{
+        int ret;
+
+        BUG_ON(!hwlock);
+        BUG_ON(!flags && mode == HWLOCK_IRQSTATE);
+
+        /*
+         * This spin_lock{_irq, _irqsave} serves three purposes:
+         *
+         * 1. Disable preemption, in order to minimize the period of time
+         *    in which the hwspinlock is taken. This is important in order
+         *    to minimize the possible polling on the hardware interconnect
+         *    by a remote user of this lock.
+         * 2. Make the hwspinlock SMP-safe (so we can take it from
+         *    additional contexts on the local host).
+         * 3. Ensure that in_atomic/might_sleep checks catch potential
+         *    problems with hwspinlock usage (e.g. scheduler checks like
+         *    'scheduling while atomic' etc.)
+         */
+        if (mode == HWLOCK_IRQSTATE)
+                ret = spin_trylock_irqsave(&hwlock->lock, *flags);
+        else if (mode == HWLOCK_IRQ)
+                ret = spin_trylock_irq(&hwlock->lock);
+        else
+                ret = spin_trylock(&hwlock->lock);
+
+        /* is lock already taken by another context on the local cpu ? */
+        if (!ret)
+                return -EBUSY;
+
+        /* try to take the hwspinlock device */
+        ret = hwlock->ops->trylock(hwlock);
+
+        /* if hwlock is already taken, undo spin_trylock_* and exit */
+        if (!ret) {
+                if (mode == HWLOCK_IRQSTATE)
+                        spin_unlock_irqrestore(&hwlock->lock, *flags);
+                else if (mode == HWLOCK_IRQ)
+                        spin_unlock_irq(&hwlock->lock);
+                else
+                        spin_unlock(&hwlock->lock);
+
+                return -EBUSY;
+        }
+
+        /*
+         * We can be sure the other core's memory operations
+         * are observable to us only _after_ we successfully take
+         * the hwspinlock, and we must make sure that subsequent memory
+         * operations (both reads and writes) will not be reordered before
+         * we actually took the hwspinlock.
+         *
+         * Note: the implicit memory barrier of the spinlock above is too
+         * early, so we need this additional explicit memory barrier.
+         */
+        mb();
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(__hwspin_trylock);
+
+/**
+ * __hwspin_lock_timeout() - lock an hwspinlock with timeout limit
+ * @hwlock: the hwspinlock to be locked
+ * @timeout: timeout value in msecs
+ * @mode: mode which controls whether local interrupts are disabled or not
+ * @flags: a pointer to where the caller's interrupt state will be saved at (if
+ *         requested)
+ *
+ * This function locks the given @hwlock. If the @hwlock
+ * is already taken, the function will busy loop waiting for it to
+ * be released, but give up after @timeout msecs have elapsed.
+ *
+ * Upon a successful return from this function, preemption is disabled
+ * (and possibly local interrupts, too), so the caller must not sleep,
+ * and is advised to release the hwspinlock as soon as possible.
+ * This is required in order to minimize remote cores polling on the
+ * hardware interconnect.
+ *
+ * The user decides whether local interrupts are disabled or not, and if yes,
+ * whether he wants their previous state to be saved. It is up to the user
+ * to choose the appropriate @mode of operation, exactly the same way users
+ * should decide between spin_lock, spin_lock_irq and spin_lock_irqsave.
+ *
+ * Returns 0 when the @hwlock was successfully taken, and an appropriate
+ * error code otherwise (most notably -ETIMEDOUT if the @hwlock is still
+ * busy after @timeout msecs). The function will never sleep.
+ */
+int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to,
+                                        int mode, unsigned long *flags)
+{
+        int ret;
+        unsigned long expire;
+
+        expire = msecs_to_jiffies(to) + jiffies;
+
+        for (;;) {
+                /* Try to take the hwspinlock */
+                ret = __hwspin_trylock(hwlock, mode, flags);
+                if (ret != -EBUSY)
+                        break;
+
+                /*
+                 * The lock is already taken, let's check if the user wants
+                 * us to try again
+                 */
+                if (time_is_before_eq_jiffies(expire))
+                        return -ETIMEDOUT;
+
+                /*
+                 * Allow platform-specific relax handlers to prevent
+                 * hogging the interconnect (no sleeping, though)
+                 */
+                if (hwlock->ops->relax)
+                        hwlock->ops->relax(hwlock);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(__hwspin_lock_timeout);
+
+/**
+ * __hwspin_unlock() - unlock a specific hwspinlock
+ * @hwlock: a previously-acquired hwspinlock which we want to unlock
+ * @mode: controls whether local interrupts needs to be restored or not
+ * @flags: previous caller's interrupt state to restore (if requested)
+ *
+ * This function will unlock a specific hwspinlock, enable preemption and
+ * (possibly) enable interrupts or restore their previous state.
+ * @hwlock must be already locked before calling this function: it is a bug
+ * to call unlock on a @hwlock that is already unlocked.
+ *
+ * The user decides whether local interrupts should be enabled or not, and
+ * if yes, whether he wants their previous state to be restored. It is up
+ * to the user to choose the appropriate @mode of operation, exactly the
+ * same way users decide between spin_unlock, spin_unlock_irq and
+ * spin_unlock_irqrestore.
+ *
+ * The function will never sleep.
+ */
+void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
+{
+        BUG_ON(!hwlock);
+        BUG_ON(!flags && mode == HWLOCK_IRQSTATE);
+
+        /*
+         * We must make sure that memory operations (both reads and writes),
+         * done before unlocking the hwspinlock, will not be reordered
+         * after the lock is released.
+         *
+         * That's the purpose of this explicit memory barrier.
+         *
+         * Note: the memory barrier induced by the spin_unlock below is too
+         * late; the other core is going to access memory soon after it will
+         * take the hwspinlock, and by then we want to be sure our memory
+         * operations are already observable.
+         */
+        mb();
+
+        hwlock->ops->unlock(hwlock);
+
+        /* Undo the spin_trylock{_irq, _irqsave} called while locking */
+        if (mode == HWLOCK_IRQSTATE)
+                spin_unlock_irqrestore(&hwlock->lock, *flags);
+        else if (mode == HWLOCK_IRQ)
+                spin_unlock_irq(&hwlock->lock);
+        else
+                spin_unlock(&hwlock->lock);
+}
+EXPORT_SYMBOL_GPL(__hwspin_unlock);
+
+/**
+ * hwspin_lock_register() - register a new hw spinlock
+ * @hwlock: hwspinlock to register.
+ *
+ * This function should be called from the underlying platform-specific
+ * implementation, to register a new hwspinlock instance.
+ *
+ * Can be called from an atomic context (will not sleep) but not from
+ * within interrupt context.
+ *
+ * Returns 0 on success, or an appropriate error code on failure
+ */
+int hwspin_lock_register(struct hwspinlock *hwlock)
+{
+        struct hwspinlock *tmp;
+        int ret;
+
+        if (!hwlock || !hwlock->ops ||
+                !hwlock->ops->trylock || !hwlock->ops->unlock) {
+                pr_err("invalid parameters\n");
+                return -EINVAL;
+        }
+
+        spin_lock_init(&hwlock->lock);
+
+        spin_lock(&hwspinlock_tree_lock);
+
+        ret = radix_tree_insert(&hwspinlock_tree, hwlock->id, hwlock);
+        if (ret)
+                goto out;
+
+        /* mark this hwspinlock as available */
+        tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id,
+                                                        HWSPINLOCK_UNUSED);
+
+        /* self-sanity check which should never fail */
+        WARN_ON(tmp != hwlock);
+
+out:
+        spin_unlock(&hwspinlock_tree_lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(hwspin_lock_register);
+
+/**
+ * hwspin_lock_unregister() - unregister an hw spinlock
+ * @id: index of the specific hwspinlock to unregister
+ *
+ * This function should be called from the underlying platform-specific
+ * implementation, to unregister an existing (and unused) hwspinlock.
+ *
+ * Can be called from an atomic context (will not sleep) but not from
+ * within interrupt context.
+ *
+ * Returns the address of hwspinlock @id on success, or NULL on failure
+ */
+struct hwspinlock *hwspin_lock_unregister(unsigned int id)
+{
+        struct hwspinlock *hwlock = NULL;
+        int ret;
+
+        spin_lock(&hwspinlock_tree_lock);
+
+        /* make sure the hwspinlock is not in use (tag is set) */
+        ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED);
+        if (ret == 0) {
+                pr_err("hwspinlock %d still in use (or not present)\n", id);
+                goto out;
+        }
+
+        hwlock = radix_tree_delete(&hwspinlock_tree, id);
+        if (!hwlock) {
+                pr_err("failed to delete hwspinlock %d\n", id);
+                goto out;
+        }
+
+out:
+        spin_unlock(&hwspinlock_tree_lock);
+        return hwlock;
+}
+EXPORT_SYMBOL_GPL(hwspin_lock_unregister);
+
+/**
+ * __hwspin_lock_request() - tag an hwspinlock as used and power it up
+ *
+ * This is an internal function that prepares an hwspinlock instance
+ * before it is given to the user. The function assumes that
+ * hwspinlock_tree_lock is taken.
+ *
+ * Returns 0 or positive to indicate success, and a negative value to
+ * indicate an error (with the appropriate error code)
+ */
+static int __hwspin_lock_request(struct hwspinlock *hwlock)
+{
+        struct hwspinlock *tmp;
+        int ret;
+
+        /* prevent underlying implementation from being removed */
+        if (!try_module_get(hwlock->owner)) {
+                dev_err(hwlock->dev, "%s: can't get owner\n", __func__);
+                return -EINVAL;
+        }
+
+        /* notify PM core that power is now needed */
+        ret = pm_runtime_get_sync(hwlock->dev);
+        if (ret < 0) {
+                dev_err(hwlock->dev, "%s: can't power on device\n", __func__);
+                return ret;
+        }
+
+        /* mark hwspinlock as used, should not fail */
+        tmp = radix_tree_tag_clear(&hwspinlock_tree, hwlock->id,
+                                                        HWSPINLOCK_UNUSED);
+
+        /* self-sanity check that should never fail */
+        WARN_ON(tmp != hwlock);
+
+        return ret;
+}
+
+/**
+ * hwspin_lock_get_id() - retrieve id number of a given hwspinlock
+ * @hwlock: a valid hwspinlock instance
+ *
+ * Returns the id number of a given @hwlock, or -EINVAL if @hwlock is invalid.
+ */
+int hwspin_lock_get_id(struct hwspinlock *hwlock)
+{
+        if (!hwlock) {
+                pr_err("invalid hwlock\n");
+                return -EINVAL;
+        }
+
+        return hwlock->id;
+}
+EXPORT_SYMBOL_GPL(hwspin_lock_get_id);
+
+/**
+ * hwspin_lock_request() - request an hwspinlock
+ *
+ * This function should be called by users of the hwspinlock device,
+ * in order to dynamically assign them an unused hwspinlock.
+ * Usually the user of this lock will then have to communicate the lock's id
+ * to the remote core before it can be used for synchronization (to get the
+ * id of a given hwlock, use hwspin_lock_get_id()).
+ *
+ * Can be called from an atomic context (will not sleep) but not from
+ * within interrupt context (simply because there is no use case for
+ * that yet).
+ *
+ * Returns the address of the assigned hwspinlock, or NULL on error
+ */
+struct hwspinlock *hwspin_lock_request(void)
+{
+        struct hwspinlock *hwlock;
+        int ret;
+
+        spin_lock(&hwspinlock_tree_lock);
+
+        /* look for an unused lock */
+        ret = radix_tree_gang_lookup_tag(&hwspinlock_tree, (void **)&hwlock,
+                                                0, 1, HWSPINLOCK_UNUSED);
+        if (ret == 0) {
+                pr_warn("a free hwspinlock is not available\n");
+                hwlock = NULL;
+                goto out;
+        }
+
+        /* sanity check that should never fail */
+        WARN_ON(ret > 1);
+
+        /* mark as used and power up */
+        ret = __hwspin_lock_request(hwlock);
+        if (ret < 0)
+                hwlock = NULL;
+
+out:
+        spin_unlock(&hwspinlock_tree_lock);
+        return hwlock;
+}
+EXPORT_SYMBOL_GPL(hwspin_lock_request);
+
+/**
+ * hwspin_lock_request_specific() - request for a specific hwspinlock
+ * @id: index of the specific hwspinlock that is requested
+ *
+ * This function should be called by users of the hwspinlock module,
+ * in order to assign them a specific hwspinlock.
+ * Usually early board code will be calling this function in order to
+ * reserve specific hwspinlock ids for predefined purposes.
+ *
+ * Can be called from an atomic context (will not sleep) but not from
+ * within interrupt context (simply because there is no use case for
+ * that yet).
+ *
+ * Returns the address of the assigned hwspinlock, or NULL on error
+ */
+struct hwspinlock *hwspin_lock_request_specific(unsigned int id)
+{
+        struct hwspinlock *hwlock;
+        int ret;
+
+        spin_lock(&hwspinlock_tree_lock);
+
+        /* make sure this hwspinlock exists */
+        hwlock = radix_tree_lookup(&hwspinlock_tree, id);
+        if (!hwlock) {
+                pr_warn("hwspinlock %u does not exist\n", id);
+                goto out;
+        }
+
+        /* sanity check (this shouldn't happen) */
+        WARN_ON(hwlock->id != id);
+
+        /* make sure this hwspinlock is unused */
+        ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED);
+        if (ret == 0) {
+                pr_warn("hwspinlock %u is already in use\n", id);
+                hwlock = NULL;
+                goto out;
+        }
+
+        /* mark as used and power up */
+        ret = __hwspin_lock_request(hwlock);
+        if (ret < 0)
+                hwlock = NULL;
+
+out:
+        spin_unlock(&hwspinlock_tree_lock);
+        return hwlock;
+}
+EXPORT_SYMBOL_GPL(hwspin_lock_request_specific);
+
+/**
+ * hwspin_lock_free() - free a specific hwspinlock
+ * @hwlock: the specific hwspinlock to free
+ *
+ * This function mark @hwlock as free again.
+ * Should only be called with an @hwlock that was retrieved from
+ * an earlier call to omap_hwspin_lock_request{_specific}.
+ *
+ * Can be called from an atomic context (will not sleep) but not from
+ * within interrupt context (simply because there is no use case for
+ * that yet).
+ *
+ * Returns 0 on success, or an appropriate error code on failure
+ */
+int hwspin_lock_free(struct hwspinlock *hwlock)
+{
+        struct hwspinlock *tmp;
+        int ret;
+
+        if (!hwlock) {
+                pr_err("invalid hwlock\n");
+                return -EINVAL;
+        }
+
+        spin_lock(&hwspinlock_tree_lock);
+
+        /* make sure the hwspinlock is used */
+        ret = radix_tree_tag_get(&hwspinlock_tree, hwlock->id,
+                                                        HWSPINLOCK_UNUSED);
+        if (ret == 1) {
+                dev_err(hwlock->dev, "%s: hwlock is already free\n", __func__);
+                dump_stack();
+                ret = -EINVAL;
+                goto out;
+        }
+
+        /* notify the underlying device that power is not needed */
+        ret = pm_runtime_put(hwlock->dev);
+        if (ret < 0)
+                goto out;
+
+        /* mark this hwspinlock as available */
+        tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id,
+                                                        HWSPINLOCK_UNUSED);
+
+        /* sanity check (this shouldn't happen) */
+        WARN_ON(tmp != hwlock);
+
+        module_put(hwlock->owner);
+
+out:
+        spin_unlock(&hwspinlock_tree_lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(hwspin_lock_free);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Hardware spinlock interface");
+MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
diff --git a/drivers/hwspinlock/hwspinlock_internal.h b/drivers/hwspinlock/hwspinlock_internal.h
new file mode 100644
index 000000000000..69935e6b93e5
--- /dev/null
+++ b/drivers/hwspinlock/hwspinlock_internal.h
@@ -0,0 +1,61 @@
+/*
+ * Hardware spinlocks internal header
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Contact: Ohad Ben-Cohen <ohad@wizery.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HWSPINLOCK_HWSPINLOCK_H
+#define __HWSPINLOCK_HWSPINLOCK_H
+
+#include <linux/spinlock.h>
+#include <linux/device.h>
+
+/**
+ * struct hwspinlock_ops - platform-specific hwspinlock handlers
+ *
+ * @trylock: make a single attempt to take the lock. returns 0 on
+ *           failure and true on success. may _not_ sleep.
+ * @unlock:  release the lock. always succeed. may _not_ sleep.
+ * @relax:   optional, platform-specific relax handler, called by hwspinlock
+ *           core while spinning on a lock, between two successive
+ *           invocations of @trylock. may _not_ sleep.
+ */
+struct hwspinlock_ops {
+        int (*trylock)(struct hwspinlock *lock);
+        void (*unlock)(struct hwspinlock *lock);
+        void (*relax)(struct hwspinlock *lock);
+};
+
+/**
+ * struct hwspinlock - this struct represents a single hwspinlock instance
+ *
+ * @dev: underlying device, will be used to invoke runtime PM api
+ * @ops: platform-specific hwspinlock handlers
+ * @id: a global, unique, system-wide, index of the lock.
+ * @lock: initialized and used by hwspinlock core
+ * @owner: underlying implementation module, used to maintain module ref count
+ *
+ * Note: currently simplicity was opted for, but later we can squeeze some
+ * memory bytes by grouping the dev, ops and owner members in a single
+ * per-platform struct, and have all hwspinlocks point at it.
+ */
+struct hwspinlock {
+        struct device *dev;
+        const struct hwspinlock_ops *ops;
+        int id;
+        spinlock_t lock;
+        struct module *owner;
+};
+
+#endif /* __HWSPINLOCK_HWSPINLOCK_H */
diff --git a/drivers/hwspinlock/omap_hwspinlock.c b/drivers/hwspinlock/omap_hwspinlock.c
new file mode 100644
index 000000000000..a8f02734c026
--- /dev/null
+++ b/drivers/hwspinlock/omap_hwspinlock.c
@@ -0,0 +1,231 @@
+/*
+ * OMAP hardware spinlock driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Contact: Simon Que <sque@ti.com>
+ *          Hari Kanigeri <h-kanigeri2@ti.com>
+ *          Ohad Ben-Cohen <ohad@wizery.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/hwspinlock.h>
+#include <linux/platform_device.h>
+
+#include "hwspinlock_internal.h"
+
+/* Spinlock register offsets */
+#define SYSSTATUS_OFFSET                0x0014
+#define LOCK_BASE_OFFSET                0x0800
+
+#define SPINLOCK_NUMLOCKS_BIT_OFFSET    (24)
+
+/* Possible values of SPINLOCK_LOCK_REG */
+#define SPINLOCK_NOTTAKEN               (0)     /* free */
+#define SPINLOCK_TAKEN                  (1)     /* locked */
+
+#define to_omap_hwspinlock(lock)        \
+        container_of(lock, struct omap_hwspinlock, lock)
+
+struct omap_hwspinlock {
+        struct hwspinlock lock;
+        void __iomem *addr;
+};
+
+struct omap_hwspinlock_state {
+        int num_locks;                  /* Total number of locks in system */
+        void __iomem *io_base;          /* Mapped base address */
+};
+
+static int omap_hwspinlock_trylock(struct hwspinlock *lock)
+{
+        struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock);
+
+        /* attempt to acquire the lock by reading its value */
+        return (SPINLOCK_NOTTAKEN == readl(omap_lock->addr));
+}
+
+static void omap_hwspinlock_unlock(struct hwspinlock *lock)
+{
+        struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock);
+
+        /* release the lock by writing 0 to it */
+        writel(SPINLOCK_NOTTAKEN, omap_lock->addr);
+}
+
+/*
+ * relax the OMAP interconnect while spinning on it.
+ *
+ * The specs recommended that the retry delay time will be
+ * just over half of the time that a requester would be
+ * expected to hold the lock.
+ *
+ * The number below is taken from an hardware specs example,
+ * obviously it is somewhat arbitrary.
+ */
+static void omap_hwspinlock_relax(struct hwspinlock *lock)
+{
+        ndelay(50);
+}
+
+static const struct hwspinlock_ops omap_hwspinlock_ops = {
+        .trylock = omap_hwspinlock_trylock,
+        .unlock = omap_hwspinlock_unlock,
+        .relax = omap_hwspinlock_relax,
+};
+
+static int __devinit omap_hwspinlock_probe(struct platform_device *pdev)
+{
+        struct omap_hwspinlock *omap_lock;
+        struct omap_hwspinlock_state *state;
+        struct hwspinlock *lock;
+        struct resource *res;
+        void __iomem *io_base;
+        int i, ret;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -ENODEV;
+
+        state = kzalloc(sizeof(*state), GFP_KERNEL);
+        if (!state)
+                return -ENOMEM;
+
+        io_base = ioremap(res->start, resource_size(res));
+        if (!io_base) {
+                ret = -ENOMEM;
+                goto free_state;
+        }
+
+        /* Determine number of locks */
+        i = readl(io_base + SYSSTATUS_OFFSET);
+        i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET;
+
+        /* one of the four lsb's must be set, and nothing else */
+        if (hweight_long(i & 0xf) != 1 || i > 8) {
+                ret = -EINVAL;
+                goto iounmap_base;
+        }
+
+        state->num_locks = i * 32;
+        state->io_base = io_base;
+
+        platform_set_drvdata(pdev, state);
+
+        /*
+         * runtime PM will make sure the clock of this module is
+         * enabled iff at least one lock is requested
+         */
+        pm_runtime_enable(&pdev->dev);
+
+        for (i = 0; i < state->num_locks; i++) {
+                omap_lock = kzalloc(sizeof(*omap_lock), GFP_KERNEL);
+                if (!omap_lock) {
+                        ret = -ENOMEM;
+                        goto free_locks;
+                }
+
+                omap_lock->lock.dev = &pdev->dev;
+                omap_lock->lock.owner = THIS_MODULE;
+                omap_lock->lock.id = i;
+                omap_lock->lock.ops = &omap_hwspinlock_ops;
+                omap_lock->addr = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
+
+                ret = hwspin_lock_register(&omap_lock->lock);
+                if (ret) {
+                        kfree(omap_lock);
+                        goto free_locks;
+                }
+        }
+
+        return 0;
+
+free_locks:
+        while (--i >= 0) {
+                lock = hwspin_lock_unregister(i);
+                /* this should't happen, but let's give our best effort */
+                if (!lock) {
+                        dev_err(&pdev->dev, "%s: cleanups failed\n", __func__);
+                        continue;
+                }
+                omap_lock = to_omap_hwspinlock(lock);
+                kfree(omap_lock);
+        }
+        pm_runtime_disable(&pdev->dev);
+iounmap_base:
+        iounmap(io_base);
+free_state:
+        kfree(state);
+        return ret;
+}
+
+static int omap_hwspinlock_remove(struct platform_device *pdev)
+{
+        struct omap_hwspinlock_state *state = platform_get_drvdata(pdev);
+        struct hwspinlock *lock;
+        struct omap_hwspinlock *omap_lock;
+        int i;
+
+        for (i = 0; i < state->num_locks; i++) {
+                lock = hwspin_lock_unregister(i);
+                /* this shouldn't happen at this point. if it does, at least
+                 * don't continue with the remove */
+                if (!lock) {
+                        dev_err(&pdev->dev, "%s: failed on %d\n", __func__, i);
+                        return -EBUSY;
+                }
+
+                omap_lock = to_omap_hwspinlock(lock);
+                kfree(omap_lock);
+        }
+
+        pm_runtime_disable(&pdev->dev);
+        iounmap(state->io_base);
+        kfree(state);
+
+        return 0;
+}
+
+static struct platform_driver omap_hwspinlock_driver = {
+        .probe          = omap_hwspinlock_probe,
+        .remove         = omap_hwspinlock_remove,
+        .driver         = {
+                .name   = "omap_hwspinlock",
+        },
+};
+
+static int __init omap_hwspinlock_init(void)
+{
+        return platform_driver_register(&omap_hwspinlock_driver);
+}
+/* board init code might need to reserve hwspinlocks for predefined purposes */
+postcore_initcall(omap_hwspinlock_init);
+
+static void __exit omap_hwspinlock_exit(void)
+{
+        platform_driver_unregister(&omap_hwspinlock_driver);
+}
+module_exit(omap_hwspinlock_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Hardware spinlock driver for OMAP");
+MODULE_AUTHOR("Simon Que <sque@ti.com>");
+MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
+MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index afe8c6fa166a..54f91321749a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -225,7 +225,7 @@ config MMC_OMAP
 
 config MMC_OMAP_HS
         tristate "TI OMAP High Speed Multimedia Card Interface support"
-        depends on ARCH_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
+        depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
         help
           This selects the TI OMAP High Speed Multimedia card Interface.
           If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 078fdf11af03..8c42573f42ea 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -260,7 +260,7 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
         return ret;
 }
 
-static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
+static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
                                    int vdd)
 {
         struct omap_hsmmc_host *host =
@@ -316,6 +316,12 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
         return ret;
 }
 
+static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
+                                        int vdd)
+{
+        return 0;
+}
+
 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
                                   int vdd, int cardsleep)
 {
@@ -326,7 +332,7 @@ static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
         return regulator_set_mode(host->vcc, mode);
 }
 
-static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
+static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
                                    int vdd, int cardsleep)
 {
         struct omap_hsmmc_host *host =
@@ -365,6 +371,12 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
                 return regulator_enable(host->vcc_aux);
 }
 
+static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
+                                        int vdd, int cardsleep)
+{
+        return 0;
+}
+
 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 {
         struct regulator *reg;
@@ -379,10 +391,14 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
                 break;
         case OMAP_MMC2_DEVID:
         case OMAP_MMC3_DEVID:
+        case OMAP_MMC5_DEVID:
                 /* Off-chip level shifting, or none */
-                mmc_slot(host).set_power = omap_hsmmc_23_set_power;
-                mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
+                mmc_slot(host).set_power = omap_hsmmc_235_set_power;
+                mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
                 break;
+        case OMAP_MMC4_DEVID:
+                mmc_slot(host).set_power = omap_hsmmc_4_set_power;
+                mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
         default:
                 pr_err("MMC%d configuration not supported!\n", host->id);
                 return -EINVAL;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index c89592239bc7..178e2006063d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -106,23 +106,6 @@ config MTD_NAND_OMAP2
         help
           Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms.
 
-config MTD_NAND_OMAP_PREFETCH
-        bool "GPMC prefetch support for NAND Flash device"
-        depends on MTD_NAND_OMAP2
-        default y
-        help
-         The NAND device can be accessed for Read/Write using GPMC PREFETCH engine
-         to improve the performance.
-
-config MTD_NAND_OMAP_PREFETCH_DMA
-        depends on MTD_NAND_OMAP_PREFETCH
-        bool "DMA mode"
-        default n
-        help
-         The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode
-         or in DMA interrupt mode.
-         Say y for DMA mode or MPU mode will be used
-
 config MTD_NAND_IDS
         tristate
 
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 15682ec8530e..4e33972ad17a 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -11,6 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/delay.h>
+#include <linux/interrupt.h>
 #include <linux/jiffies.h>
 #include <linux/sched.h>
 #include <linux/mtd/mtd.h>
@@ -24,6 +25,7 @@
 #include <plat/nand.h>
 
 #define DRIVER_NAME     "omap2-nand"
+#define OMAP_NAND_TIMEOUT_MS    5000
 
 #define NAND_Ecc_P1e            (1 << 0)
 #define NAND_Ecc_P2e            (1 << 1)
@@ -96,26 +98,19 @@
 static const char *part_probes[] = { "cmdlinepart", NULL };
 #endif
 
-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
-static int use_prefetch = 1;
-
-/* "modprobe ... use_prefetch=0" etc */
-module_param(use_prefetch, bool, 0);
-MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
-
-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
-static int use_dma = 1;
+/* oob info generated runtime depending on ecc algorithm and layout selected */
+static struct nand_ecclayout omap_oobinfo;
+/* Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks
+ */
+static uint8_t scan_ff_pattern[] = { 0xff };
+static struct nand_bbt_descr bb_descrip_flashbased = {
+        .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
+        .offs = 0,
+        .len = 1,
+        .pattern = scan_ff_pattern,
+};
 
-/* "modprobe ... use_dma=0" etc */
-module_param(use_dma, bool, 0);
-MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
-#else
-static const int use_dma;
-#endif
-#else
-const int use_prefetch;
-static const int use_dma;
-#endif
 
 struct omap_nand_info {
         struct nand_hw_control          controller;
@@ -129,6 +124,13 @@ struct omap_nand_info {
         unsigned long                   phys_base;
         struct completion               comp;
         int                             dma_ch;
+        int                             gpmc_irq;
+        enum {
+                OMAP_NAND_IO_READ = 0,  /* read */
+                OMAP_NAND_IO_WRITE,     /* write */
+        } iomode;
+        u_char                          *buf;
+        int                                     buf_len;
 };
 
 /**
@@ -256,7 +258,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
         }
 
         /* configure and start prefetch transfer */
-        ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
+        ret = gpmc_prefetch_enable(info->gpmc_cs,
+                        PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
         if (ret) {
                 /* PFPW engine is busy, use cpu copy method */
                 if (info->nand.options & NAND_BUSWIDTH_16)
@@ -288,9 +291,10 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
 {
         struct omap_nand_info *info = container_of(mtd,
                                                 struct omap_nand_info, mtd);
-        uint32_t pref_count = 0, w_count = 0;
+        uint32_t w_count = 0;
         int i = 0, ret = 0;
         u16 *p;
+        unsigned long tim, limit;
 
         /* take care of subpage writes */
         if (len % 2 != 0) {
@@ -300,7 +304,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
         }
 
         /*  configure and start prefetch transfer */
-        ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
+        ret = gpmc_prefetch_enable(info->gpmc_cs,
+                        PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
         if (ret) {
                 /* PFPW engine is busy, use cpu copy method */
                 if (info->nand.options & NAND_BUSWIDTH_16)
@@ -316,15 +321,17 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
                                 iowrite16(*p++, info->nand.IO_ADDR_W);
                 }
                 /* wait for data to flushed-out before reset the prefetch */
-                do {
-                        pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT);
-                } while (pref_count);
+                tim = 0;
+                limit = (loops_per_jiffy *
+                                        msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
+                while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
+                        cpu_relax();
+
                 /* disable and stop the PFPW engine */
                 gpmc_prefetch_reset(info->gpmc_cs);
         }
 }
 
-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
 /*
  * omap_nand_dma_cb: callback on the completion of dma transfer
  * @lch: logical channel
@@ -348,14 +355,15 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 {
         struct omap_nand_info *info = container_of(mtd,
                                         struct omap_nand_info, mtd);
-        uint32_t prefetch_status = 0;
         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
                                                         DMA_FROM_DEVICE;
         dma_addr_t dma_addr;
         int ret;
+        unsigned long tim, limit;
 
-        /* The fifo depth is 64 bytes. We have a sync at each frame and frame
-         * length is 64 bytes.
+        /* The fifo depth is 64 bytes max.
+         * But configure the FIFO-threahold to 32 to get a sync at each frame
+         * and frame length is 32 bytes.
          */
         int buf_len = len >> 6;
 
@@ -396,9 +404,10 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
         }
         /*  configure and start prefetch transfer */
-        ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
+        ret = gpmc_prefetch_enable(info->gpmc_cs,
+                        PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
         if (ret)
-                /* PFPW engine is busy, use cpu copy methode */
+                /* PFPW engine is busy, use cpu copy method */
                 goto out_copy;
 
         init_completion(&info->comp);
@@ -407,10 +416,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 
         /* setup and start DMA using dma_addr */
         wait_for_completion(&info->comp);
+        tim = 0;
+        limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
+        while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
+                cpu_relax();
 
-        do {
-                prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT);
-        } while (prefetch_status);
         /* disable and stop the PFPW engine */
         gpmc_prefetch_reset(info->gpmc_cs);
 
@@ -426,14 +436,6 @@ out_copy:
                         : omap_write_buf8(mtd, (u_char *) addr, len);
         return 0;
 }
-#else
-static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
-static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
-                                        unsigned int len, int is_write)
-{
-        return 0;
-}
-#endif
 
 /**
  * omap_read_buf_dma_pref - read data from NAND controller into buffer
@@ -466,6 +468,157 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd,
                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 }
 
+/*
+ * omap_nand_irq - GMPC irq handler
+ * @this_irq: gpmc irq number
+ * @dev: omap_nand_info structure pointer is passed here
+ */
+static irqreturn_t omap_nand_irq(int this_irq, void *dev)
+{
+        struct omap_nand_info *info = (struct omap_nand_info *) dev;
+        u32 bytes;
+        u32 irq_stat;
+
+        irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
+        bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
+        bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
+        if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
+                if (irq_stat & 0x2)
+                        goto done;
+
+                if (info->buf_len && (info->buf_len < bytes))
+                        bytes = info->buf_len;
+                else if (!info->buf_len)
+                        bytes = 0;
+                iowrite32_rep(info->nand.IO_ADDR_W,
+                                                (u32 *)info->buf, bytes >> 2);
+                info->buf = info->buf + bytes;
+                info->buf_len -= bytes;
+
+        } else {
+                ioread32_rep(info->nand.IO_ADDR_R,
+                                                (u32 *)info->buf, bytes >> 2);
+                info->buf = info->buf + bytes;
+
+                if (irq_stat & 0x2)
+                        goto done;
+        }
+        gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
+
+        return IRQ_HANDLED;
+
+done:
+        complete(&info->comp);
+        /* disable irq */
+        gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
+
+        /* clear status */
+        gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
+
+        return IRQ_HANDLED;
+}
+
+/*
+ * omap_read_buf_irq_pref - read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
+{
+        struct omap_nand_info *info = container_of(mtd,
+                                                struct omap_nand_info, mtd);
+        int ret = 0;
+
+        if (len <= mtd->oobsize) {
+                omap_read_buf_pref(mtd, buf, len);
+                return;
+        }
+
+        info->iomode = OMAP_NAND_IO_READ;
+        info->buf = buf;
+        init_completion(&info->comp);
+
+        /*  configure and start prefetch transfer */
+        ret = gpmc_prefetch_enable(info->gpmc_cs,
+                        PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
+        if (ret)
+                /* PFPW engine is busy, use cpu copy method */
+                goto out_copy;
+
+        info->buf_len = len;
+        /* enable irq */
+        gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
+                (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
+
+        /* waiting for read to complete */
+        wait_for_completion(&info->comp);
+
+        /* disable and stop the PFPW engine */
+        gpmc_prefetch_reset(info->gpmc_cs);
+        return;
+
+out_copy:
+        if (info->nand.options & NAND_BUSWIDTH_16)
+                omap_read_buf16(mtd, buf, len);
+        else
+                omap_read_buf8(mtd, buf, len);
+}
+
+/*
+ * omap_write_buf_irq_pref - write buffer to NAND controller
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void omap_write_buf_irq_pref(struct mtd_info *mtd,
+                                        const u_char *buf, int len)
+{
+        struct omap_nand_info *info = container_of(mtd,
+                                                struct omap_nand_info, mtd);
+        int ret = 0;
+        unsigned long tim, limit;
+
+        if (len <= mtd->oobsize) {
+                omap_write_buf_pref(mtd, buf, len);
+                return;
+        }
+
+        info->iomode = OMAP_NAND_IO_WRITE;
+        info->buf = (u_char *) buf;
+        init_completion(&info->comp);
+
+        /* configure and start prefetch transfer : size=24 */
+        ret = gpmc_prefetch_enable(info->gpmc_cs,
+                        (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
+        if (ret)
+                /* PFPW engine is busy, use cpu copy method */
+                goto out_copy;
+
+        info->buf_len = len;
+        /* enable irq */
+        gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
+                        (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
+
+        /* waiting for write to complete */
+        wait_for_completion(&info->comp);
+        /* wait for data to flushed-out before reset the prefetch */
+        tim = 0;
+        limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
+        while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
+                cpu_relax();
+
+        /* disable and stop the PFPW engine */
+        gpmc_prefetch_reset(info->gpmc_cs);
+        return;
+
+out_copy:
+        if (info->nand.options & NAND_BUSWIDTH_16)
+                omap_write_buf16(mtd, buf, len);
+        else
+                omap_write_buf8(mtd, buf, len);
+}
+
 /**
  * omap_verify_buf - Verify chip data against buffer
  * @mtd: MTD device structure
@@ -487,8 +640,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
         return 0;
 }
 
-#ifdef CONFIG_MTD_NAND_OMAP_HWECC
-
 /**
  * gen_true_ecc - This function will generate true ECC value
  * @ecc_buf: buffer to store ecc code
@@ -708,8 +859,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 }
 
-#endif
-
 /**
  * omap_wait - wait until the command is done
  * @mtd: MTD device structure
@@ -779,6 +928,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         struct omap_nand_info           *info;
         struct omap_nand_platform_data  *pdata;
         int                             err;
+        int                             i, offset;
 
         pdata = pdev->dev.platform_data;
         if (pdata == NULL) {
@@ -804,7 +954,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         info->mtd.name          = dev_name(&pdev->dev);
         info->mtd.owner         = THIS_MODULE;
 
-        info->nand.options      |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
+        info->nand.options      = pdata->devsize;
         info->nand.options      |= NAND_SKIP_BBTSCAN;
 
         /* NAND write protect off */
@@ -842,28 +992,13 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                 info->nand.chip_delay = 50;
         }
 
-        if (use_prefetch) {
-
+        switch (pdata->xfer_type) {
+        case NAND_OMAP_PREFETCH_POLLED:
                 info->nand.read_buf   = omap_read_buf_pref;
                 info->nand.write_buf  = omap_write_buf_pref;
-                if (use_dma) {
-                        err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
-                                omap_nand_dma_cb, &info->comp, &info->dma_ch);
-                        if (err < 0) {
-                                info->dma_ch = -1;
-                                printk(KERN_WARNING "DMA request failed."
-                                        " Non-dma data transfer mode\n");
-                        } else {
-                                omap_set_dma_dest_burst_mode(info->dma_ch,
-                                                OMAP_DMA_DATA_BURST_16);
-                                omap_set_dma_src_burst_mode(info->dma_ch,
-                                                OMAP_DMA_DATA_BURST_16);
-
-                                info->nand.read_buf   = omap_read_buf_dma_pref;
-                                info->nand.write_buf  = omap_write_buf_dma_pref;
-                        }
-                }
-        } else {
+                break;
+
+        case NAND_OMAP_POLLED:
                 if (info->nand.options & NAND_BUSWIDTH_16) {
                         info->nand.read_buf   = omap_read_buf16;
                         info->nand.write_buf  = omap_write_buf16;
@@ -871,20 +1006,61 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                         info->nand.read_buf   = omap_read_buf8;
                         info->nand.write_buf  = omap_write_buf8;
                 }
+                break;
+
+        case NAND_OMAP_PREFETCH_DMA:
+                err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
+                                omap_nand_dma_cb, &info->comp, &info->dma_ch);
+                if (err < 0) {
+                        info->dma_ch = -1;
+                        dev_err(&pdev->dev, "DMA request failed!\n");
+                        goto out_release_mem_region;
+                } else {
+                        omap_set_dma_dest_burst_mode(info->dma_ch,
+                                        OMAP_DMA_DATA_BURST_16);
+                        omap_set_dma_src_burst_mode(info->dma_ch,
+                                        OMAP_DMA_DATA_BURST_16);
+
+                        info->nand.read_buf   = omap_read_buf_dma_pref;
+                        info->nand.write_buf  = omap_write_buf_dma_pref;
+                }
+                break;
+
+        case NAND_OMAP_PREFETCH_IRQ:
+                err = request_irq(pdata->gpmc_irq,
+                                omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
+                if (err) {
+                        dev_err(&pdev->dev, "requesting irq(%d) error:%d",
+                                                        pdata->gpmc_irq, err);
+                        goto out_release_mem_region;
+                } else {
+                        info->gpmc_irq       = pdata->gpmc_irq;
+                        info->nand.read_buf  = omap_read_buf_irq_pref;
+                        info->nand.write_buf = omap_write_buf_irq_pref;
+                }
+                break;
+
+        default:
+                dev_err(&pdev->dev,
+                        "xfer_type(%d) not supported!\n", pdata->xfer_type);
+                err = -EINVAL;
+                goto out_release_mem_region;
         }
-        info->nand.verify_buf = omap_verify_buf;
 
-#ifdef CONFIG_MTD_NAND_OMAP_HWECC
-        info->nand.ecc.bytes            = 3;
-        info->nand.ecc.size             = 512;
-        info->nand.ecc.calculate        = omap_calculate_ecc;
-        info->nand.ecc.hwctl            = omap_enable_hwecc;
-        info->nand.ecc.correct          = omap_correct_data;
-        info->nand.ecc.mode             = NAND_ECC_HW;
+        info->nand.verify_buf = omap_verify_buf;
 
-#else
-        info->nand.ecc.mode = NAND_ECC_SOFT;
-#endif
+        /* selsect the ecc type */
+        if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
+                info->nand.ecc.mode = NAND_ECC_SOFT;
+        else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
+                (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
+                info->nand.ecc.bytes            = 3;
+                info->nand.ecc.size             = 512;
+                info->nand.ecc.calculate        = omap_calculate_ecc;
+                info->nand.ecc.hwctl            = omap_enable_hwecc;
+                info->nand.ecc.correct          = omap_correct_data;
+                info->nand.ecc.mode             = NAND_ECC_HW;
+        }
 
         /* DIP switches on some boards change between 8 and 16 bit
          * bus widths for flash.  Try the other width if the first try fails.
@@ -897,6 +1073,26 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                 }
         }
 
+        /* rom code layout */
+        if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
+
+                if (info->nand.options & NAND_BUSWIDTH_16)
+                        offset = 2;
+                else {
+                        offset = 1;
+                        info->nand.badblock_pattern = &bb_descrip_flashbased;
+                }
+                omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
+                for (i = 0; i < omap_oobinfo.eccbytes; i++)
+                        omap_oobinfo.eccpos[i] = i+offset;
+
+                omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
+                omap_oobinfo.oobfree->length = info->mtd.oobsize -
+                                        (offset + omap_oobinfo.eccbytes);
+
+                info->nand.ecc.layout = &omap_oobinfo;
+        }
+
 #ifdef CONFIG_MTD_PARTITIONS
         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
         if (err > 0)
@@ -926,9 +1122,12 @@ static int omap_nand_remove(struct platform_device *pdev)
                                                         mtd);
 
         platform_set_drvdata(pdev, NULL);
-        if (use_dma)
+        if (info->dma_ch != -1)
                 omap_free_dma(info->dma_ch);
 
+        if (info->gpmc_irq)
+                free_irq(info->gpmc_irq, info);
+
         /* Release NAND device, its internal structures and partitions */
         nand_release(&info->mtd);
         iounmap(info->nand.IO_ADDR_R);
@@ -947,16 +1146,8 @@ static struct platform_driver omap_nand_driver = {
 
 static int __init omap_nand_init(void)
 {
-        printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
+        pr_info("%s driver initializing\n", DRIVER_NAME);
 
-        /* This check is required if driver is being
-         * loaded run time as a module
-         */
-        if ((1 == use_dma) && (0 == use_prefetch)) {
-                printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
-                                "without use_prefetch'. Prefetch will not be"
-                                " used in either mode (mpu or dma)\n");
-        }
         return platform_driver_register(&omap_nand_driver);
 }
 
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index ac31f461cc1c..ec26399e3cf2 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -63,7 +63,7 @@ struct omap2_onenand {
         struct completion dma_done;
         int dma_channel;
         int freq;
-        int (*setup)(void __iomem *base, int freq);
+        int (*setup)(void __iomem *base, int *freq_ptr);
         struct regulator *regulator;
 };
 
@@ -148,11 +148,9 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
                         wait_err("controller error", state, ctrl, intr);
                         return -EIO;
                 }
-                if ((intr & intr_flags) != intr_flags) {
-                        wait_err("timeout", state, ctrl, intr);
-                        return -EIO;
-                }
-                return 0;
+                if ((intr & intr_flags) == intr_flags)
+                        return 0;
+                /* Continue in wait for interrupt branch */
         }
 
         if (state != FL_READING) {
@@ -581,7 +579,7 @@ static int __adjust_timing(struct device *dev, void *data)
 
         /* DMA is not in use so this is all that is needed */
         /* Revisit for OMAP3! */
-        ret = c->setup(c->onenand.base, c->freq);
+        ret = c->setup(c->onenand.base, &c->freq);
 
         return ret;
 }
@@ -673,7 +671,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
         }
 
         if (pdata->onenand_setup != NULL) {
-                r = pdata->onenand_setup(c->onenand.base, c->freq);
+                r = pdata->onenand_setup(c->onenand.base, &c->freq);
                 if (r < 0) {
                         dev_err(&pdev->dev, "Onenand platform setup failed: "
                                 "%d\n", r);
@@ -718,8 +716,8 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
         }
 
         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
-                 "base %p\n", c->gpmc_cs, c->phys_base,
-                 c->onenand.base);
+                 "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
+                 c->onenand.base, c->freq);
 
         c->pdev = pdev;
         c->mtd.name = dev_name(&pdev->dev);
@@ -754,24 +752,6 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
         if ((r = onenand_scan(&c->mtd, 1)) < 0)
                 goto err_release_regulator;
 
-        switch ((c->onenand.version_id >> 4) & 0xf) {
-        case 0:
-                c->freq = 40;
-                break;
-        case 1:
-                c->freq = 54;
-                break;
-        case 2:
-                c->freq = 66;
-                break;
-        case 3:
-                c->freq = 83;
-                break;
-        case 4:
-                c->freq = 104;
-                break;
-        }
-
 #ifdef CONFIG_MTD_PARTITIONS
         r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0);
         if (r > 0)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index abb1ffbf3d20..36501adc125d 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2005, 2006 Nokia Corporation
  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
- *              Juha Yrjölä <juha.yrjola@nokia.com>
+ *              Juha Yrj�l� <juha.yrjola@nokia.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,6 +33,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <linux/spi/spi.h>
 
@@ -46,7 +47,6 @@
 #define OMAP2_MCSPI_MAX_CTRL            4
 
 #define OMAP2_MCSPI_REVISION            0x00
-#define OMAP2_MCSPI_SYSCONFIG           0x10
 #define OMAP2_MCSPI_SYSSTATUS           0x14
 #define OMAP2_MCSPI_IRQSTATUS           0x18
 #define OMAP2_MCSPI_IRQENABLE           0x1c
@@ -63,13 +63,6 @@
 
 /* per-register bitmasks: */
 
-#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
-#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  BIT(0)
-#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
@@ -122,13 +115,12 @@ struct omap2_mcspi {
         spinlock_t              lock;
         struct list_head        msg_queue;
         struct spi_master       *master;
-        struct clk              *ick;
-        struct clk              *fck;
         /* Virtual base address of the controller */
         void __iomem            *base;
         unsigned long           phys;
         /* SPI1 has 4 channels, while SPI2 has 2 */
         struct omap2_mcspi_dma  *dma_channels;
+        struct  device          *dev;
 };
 
 struct omap2_mcspi_cs {
@@ -144,7 +136,6 @@ struct omap2_mcspi_cs {
  * corresponding registers are modified.
  */
 struct omap2_mcspi_regs {
-        u32 sysconfig;
         u32 modulctrl;
         u32 wakeupenable;
         struct list_head cs;
@@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
 
-        mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
-                        omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
-
         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
 
@@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 }
 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
 {
-        clk_disable(mcspi->ick);
-        clk_disable(mcspi->fck);
+        pm_runtime_put_sync(mcspi->dev);
 }
 
 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
 {
-        if (clk_enable(mcspi->ick))
-                return -ENODEV;
-        if (clk_enable(mcspi->fck))
-                return -ENODEV;
-
-        omap2_mcspi_restore_ctx(mcspi);
-
-        return 0;
+        return pm_runtime_get_sync(mcspi->dev);
 }
 
 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
@@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi)
                         return ret;
         }
 
-        if (omap2_mcspi_enable_clocks(mcspi))
-                return -ENODEV;
+        ret = omap2_mcspi_enable_clocks(mcspi);
+        if (ret < 0)
+                return ret;
 
         ret = omap2_mcspi_setup_transfer(spi, NULL);
         omap2_mcspi_disable_clocks(mcspi);
@@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work)
         struct omap2_mcspi      *mcspi;
 
         mcspi = container_of(work, struct omap2_mcspi, work);
-        spin_lock_irq(&mcspi->lock);
 
-        if (omap2_mcspi_enable_clocks(mcspi))
-                goto out;
+        if (omap2_mcspi_enable_clocks(mcspi) < 0)
+                return;
+
+        spin_lock_irq(&mcspi->lock);
 
         /* We only enable one channel at a time -- the one whose message is
          * at the head of the queue -- although this controller would gladly
@@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work)
                 spin_lock_irq(&mcspi->lock);
         }
 
-        omap2_mcspi_disable_clocks(mcspi);
-
-out:
         spin_unlock_irq(&mcspi->lock);
+
+        omap2_mcspi_disable_clocks(mcspi);
 }
 
 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
@@ -1058,25 +1039,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
         return 0;
 }
 
-static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
+static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
 {
         struct spi_master       *master = mcspi->master;
         u32                     tmp;
+        int ret = 0;
 
-        if (omap2_mcspi_enable_clocks(mcspi))
-                return -1;
-
-        mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
-                        OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
-        do {
-                tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
-        } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
-
-        tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
-                OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
-                OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
-        mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
-        omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
+        ret = omap2_mcspi_enable_clocks(mcspi);
+        if (ret < 0)
+                return ret;
 
         tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
@@ -1087,91 +1058,26 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
         return 0;
 }
 
-static u8 __initdata spi1_rxdma_id [] = {
-        OMAP24XX_DMA_SPI1_RX0,
-        OMAP24XX_DMA_SPI1_RX1,
-        OMAP24XX_DMA_SPI1_RX2,
-        OMAP24XX_DMA_SPI1_RX3,
-};
-
-static u8 __initdata spi1_txdma_id [] = {
-        OMAP24XX_DMA_SPI1_TX0,
-        OMAP24XX_DMA_SPI1_TX1,
-        OMAP24XX_DMA_SPI1_TX2,
-        OMAP24XX_DMA_SPI1_TX3,
-};
-
-static u8 __initdata spi2_rxdma_id[] = {
-        OMAP24XX_DMA_SPI2_RX0,
-        OMAP24XX_DMA_SPI2_RX1,
-};
-
-static u8 __initdata spi2_txdma_id[] = {
-        OMAP24XX_DMA_SPI2_TX0,
-        OMAP24XX_DMA_SPI2_TX1,
-};
-
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
-        || defined(CONFIG_ARCH_OMAP4)
-static u8 __initdata spi3_rxdma_id[] = {
-        OMAP24XX_DMA_SPI3_RX0,
-        OMAP24XX_DMA_SPI3_RX1,
-};
+static int omap_mcspi_runtime_resume(struct device *dev)
+{
+        struct omap2_mcspi      *mcspi;
+        struct spi_master       *master;
 
-static u8 __initdata spi3_txdma_id[] = {
-        OMAP24XX_DMA_SPI3_TX0,
-        OMAP24XX_DMA_SPI3_TX1,
-};
-#endif
+        master = dev_get_drvdata(dev);
+        mcspi = spi_master_get_devdata(master);
+        omap2_mcspi_restore_ctx(mcspi);
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static u8 __initdata spi4_rxdma_id[] = {
-        OMAP34XX_DMA_SPI4_RX0,
-};
+        return 0;
+}
 
-static u8 __initdata spi4_txdma_id[] = {
-        OMAP34XX_DMA_SPI4_TX0,
-};
-#endif
 
 static int __init omap2_mcspi_probe(struct platform_device *pdev)
 {
         struct spi_master       *master;
+        struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
         struct omap2_mcspi      *mcspi;
         struct resource         *r;
         int                     status = 0, i;
-        const u8                *rxdma_id, *txdma_id;
-        unsigned                num_chipselect;
-
-        switch (pdev->id) {
-        case 1:
-                rxdma_id = spi1_rxdma_id;
-                txdma_id = spi1_txdma_id;
-                num_chipselect = 4;
-                break;
-        case 2:
-                rxdma_id = spi2_rxdma_id;
-                txdma_id = spi2_txdma_id;
-                num_chipselect = 2;
-                break;
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
-        || defined(CONFIG_ARCH_OMAP4)
-        case 3:
-                rxdma_id = spi3_rxdma_id;
-                txdma_id = spi3_txdma_id;
-                num_chipselect = 2;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        case 4:
-                rxdma_id = spi4_rxdma_id;
-                txdma_id = spi4_txdma_id;
-                num_chipselect = 1;
-                break;
-#endif
-        default:
-                return -EINVAL;
-        }
 
         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
         if (master == NULL) {
@@ -1188,7 +1094,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
         master->setup = omap2_mcspi_setup;
         master->transfer = omap2_mcspi_transfer;
         master->cleanup = omap2_mcspi_cleanup;
-        master->num_chipselect = num_chipselect;
+        master->num_chipselect = pdata->num_cs;
 
         dev_set_drvdata(&pdev->dev, master);
 
@@ -1206,49 +1112,62 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
                 goto err1;
         }
 
+        r->start += pdata->regs_offset;
+        r->end += pdata->regs_offset;
         mcspi->phys = r->start;
         mcspi->base = ioremap(r->start, r->end - r->start + 1);
         if (!mcspi->base) {
                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
                 status = -ENOMEM;
-                goto err1aa;
+                goto err2;
         }
 
+        mcspi->dev = &pdev->dev;
         INIT_WORK(&mcspi->work, omap2_mcspi_work);
 
         spin_lock_init(&mcspi->lock);
         INIT_LIST_HEAD(&mcspi->msg_queue);
         INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
 
-        mcspi->ick = clk_get(&pdev->dev, "ick");
-        if (IS_ERR(mcspi->ick)) {
-                dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
-                status = PTR_ERR(mcspi->ick);
-                goto err1a;
-        }
-        mcspi->fck = clk_get(&pdev->dev, "fck");
-        if (IS_ERR(mcspi->fck)) {
-                dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
-                status = PTR_ERR(mcspi->fck);
-                goto err2;
-        }
-
         mcspi->dma_channels = kcalloc(master->num_chipselect,
                         sizeof(struct omap2_mcspi_dma),
                         GFP_KERNEL);
 
         if (mcspi->dma_channels == NULL)
-                goto err3;
+                goto err2;
+
+        for (i = 0; i < master->num_chipselect; i++) {
+                char dma_ch_name[14];
+                struct resource *dma_res;
+
+                sprintf(dma_ch_name, "rx%d", i);
+                dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
+                                                        dma_ch_name);
+                if (!dma_res) {
+                        dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
+                        status = -ENODEV;
+                        break;
+                }
 
-        for (i = 0; i < num_chipselect; i++) {
                 mcspi->dma_channels[i].dma_rx_channel = -1;
-                mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
+                mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
+                sprintf(dma_ch_name, "tx%d", i);
+                dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
+                                                        dma_ch_name);
+                if (!dma_res) {
+                        dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
+                        status = -ENODEV;
+                        break;
+                }
+
                 mcspi->dma_channels[i].dma_tx_channel = -1;
-                mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
+                mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
         }
 
-        if (omap2_mcspi_reset(mcspi) < 0)
-                goto err4;
+        pm_runtime_enable(&pdev->dev);
+
+        if (status || omap2_mcspi_master_setup(mcspi) < 0)
+                goto err3;
 
         status = spi_register_master(master);
         if (status < 0)
@@ -1257,17 +1176,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
         return status;
 
 err4:
-        kfree(mcspi->dma_channels);
+        spi_master_put(master);
 err3:
-        clk_put(mcspi->fck);
+        kfree(mcspi->dma_channels);
 err2:
-        clk_put(mcspi->ick);
-err1a:
-        iounmap(mcspi->base);
-err1aa:
         release_mem_region(r->start, (r->end - r->start) + 1);
+        iounmap(mcspi->base);
 err1:
-        spi_master_put(master);
         return status;
 }
 
@@ -1283,9 +1198,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
         mcspi = spi_master_get_devdata(master);
         dma_channels = mcspi->dma_channels;
 
-        clk_put(mcspi->fck);
-        clk_put(mcspi->ick);
-
+        omap2_mcspi_disable_clocks(mcspi);
         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         release_mem_region(r->start, (r->end - r->start) + 1);
 
@@ -1336,6 +1249,7 @@ static int omap2_mcspi_resume(struct device *dev)
 
 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
         .resume = omap2_mcspi_resume,
+        .runtime_resume = omap_mcspi_runtime_resume,
 };
 
 static struct platform_driver omap2_mcspi_driver = {
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index c292d5c499e7..e550f35eff0f 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -1530,7 +1530,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
         defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
         defined(CONFIG_ARCH_U5500)
 
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index e6400be8a0f8..3fb617ef9e72 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -212,8 +212,8 @@ enum musb_g_ep0_state {
  * directly with the "flat" model, or after setting up an index register.
  */
 
-#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \
-                || defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN) \
+#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
+                || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
                 || defined(CONFIG_ARCH_OMAP4)
 /* REVISIT indexed access seemed to
  * misbehave (on DaVinci) for at least peripheral IN ...
@@ -358,7 +358,7 @@ struct musb_csr_regs {
 
 struct musb_context_registers {
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
     defined(CONFIG_ARCH_OMAP4)
         u32 otg_sysconfig, otg_forcestandby;
 #endif
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
index 21056c924c74..320fd4afb93f 100644
--- a/drivers/usb/musb/musbhsdma.h
+++ b/drivers/usb/musb/musbhsdma.h
@@ -31,7 +31,7 @@
  *
  */
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
 #include "omap2430.h"
 #endif
 
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index e00fa1b22ecd..8c6fdef61d1c 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -1510,7 +1510,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
 
 /*-------------------------------------------------------------------------*/
 
-static int __init
+static int __devinit
 isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
 {
         int                     status;
diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig
index 80b3b123dd7f..7c608c5ccf84 100644
--- a/drivers/w1/masters/Kconfig
+++ b/drivers/w1/masters/Kconfig
@@ -60,7 +60,7 @@ config W1_MASTER_GPIO
 
 config HDQ_MASTER_OMAP
         tristate "OMAP HDQ driver"
-        depends on ARCH_OMAP2430 || ARCH_OMAP3
+        depends on SOC_OMAP2430 || ARCH_OMAP3
         help
           Say Y here if you want support for the 1-wire or HDQ Interface
           on an OMAP processor.
diff --git a/include/linux/hwspinlock.h b/include/linux/hwspinlock.h
new file mode 100644
index 000000000000..8390efc457eb
--- /dev/null
+++ b/include/linux/hwspinlock.h
@@ -0,0 +1,292 @@
+/*
+ * Hardware spinlock public header
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Contact: Ohad Ben-Cohen <ohad@wizery.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_HWSPINLOCK_H
+#define __LINUX_HWSPINLOCK_H
+
+#include <linux/err.h>
+#include <linux/sched.h>
+
+/* hwspinlock mode argument */
+#define HWLOCK_IRQSTATE 0x01    /* Disable interrupts, save state */
+#define HWLOCK_IRQ      0x02    /* Disable interrupts, don't save state */
+
+struct hwspinlock;
+
+#if defined(CONFIG_HWSPINLOCK) || defined(CONFIG_HWSPINLOCK_MODULE)
+
+int hwspin_lock_register(struct hwspinlock *lock);
+struct hwspinlock *hwspin_lock_unregister(unsigned int id);
+struct hwspinlock *hwspin_lock_request(void);
+struct hwspinlock *hwspin_lock_request_specific(unsigned int id);
+int hwspin_lock_free(struct hwspinlock *hwlock);
+int hwspin_lock_get_id(struct hwspinlock *hwlock);
+int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int,
+                                                        unsigned long *);
+int __hwspin_trylock(struct hwspinlock *, int, unsigned long *);
+void __hwspin_unlock(struct hwspinlock *, int, unsigned long *);
+
+#else /* !CONFIG_HWSPINLOCK */
+
+/*
+ * We don't want these functions to fail if CONFIG_HWSPINLOCK is not
+ * enabled. We prefer to silently succeed in this case, and let the
+ * code path get compiled away. This way, if CONFIG_HWSPINLOCK is not
+ * required on a given setup, users will still work.
+ *
+ * The only exception is hwspin_lock_register/hwspin_lock_unregister, with which
+ * we _do_ want users to fail (no point in registering hwspinlock instances if
+ * the framework is not available).
+ *
+ * Note: ERR_PTR(-ENODEV) will still be considered a success for NULL-checking
+ * users. Others, which care, can still check this with IS_ERR.
+ */
+static inline struct hwspinlock *hwspin_lock_request(void)
+{
+        return ERR_PTR(-ENODEV);
+}
+
+static inline struct hwspinlock *hwspin_lock_request_specific(unsigned int id)
+{
+        return ERR_PTR(-ENODEV);
+}
+
+static inline int hwspin_lock_free(struct hwspinlock *hwlock)
+{
+        return 0;
+}
+
+static inline
+int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to,
+                                        int mode, unsigned long *flags)
+{
+        return 0;
+}
+
+static inline
+int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
+{
+        return 0;
+}
+
+static inline
+void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
+{
+        return 0;
+}
+
+static inline int hwspin_lock_get_id(struct hwspinlock *hwlock)
+{
+        return 0;
+}
+
+static inline int hwspin_lock_register(struct hwspinlock *hwlock)
+{
+        return -ENODEV;
+}
+
+static inline struct hwspinlock *hwspin_lock_unregister(unsigned int id)
+{
+        return NULL;
+}
+
+#endif /* !CONFIG_HWSPINLOCK */
+
+/**
+ * hwspin_trylock_irqsave() - try to lock an hwspinlock, disable interrupts
+ * @hwlock: an hwspinlock which we want to trylock
+ * @flags: a pointer to where the caller's interrupt state will be saved at
+ *
+ * This function attempts to lock the underlying hwspinlock, and will
+ * immediately fail if the hwspinlock is already locked.
+ *
+ * Upon a successful return from this function, preemption and local
+ * interrupts are disabled (previous interrupts state is saved at @flags),
+ * so the caller must not sleep, and is advised to release the hwspinlock
+ * as soon as possible.
+ *
+ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if
+ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid.
+ */
+static inline
+int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags)
+{
+        return __hwspin_trylock(hwlock, HWLOCK_IRQSTATE, flags);
+}
+
+/**
+ * hwspin_trylock_irq() - try to lock an hwspinlock, disable interrupts
+ * @hwlock: an hwspinlock which we want to trylock
+ *
+ * This function attempts to lock the underlying hwspinlock, and will
+ * immediately fail if the hwspinlock is already locked.
+ *
+ * Upon a successful return from this function, preemption and local
+ * interrupts are disabled, so the caller must not sleep, and is advised
+ * to release the hwspinlock as soon as possible.
+ *
+ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if
+ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid.
+ */
+static inline int hwspin_trylock_irq(struct hwspinlock *hwlock)
+{
+        return __hwspin_trylock(hwlock, HWLOCK_IRQ, NULL);
+}
+
+/**
+ * hwspin_trylock() - attempt to lock a specific hwspinlock
+ * @hwlock: an hwspinlock which we want to trylock
+ *
+ * This function attempts to lock an hwspinlock, and will immediately fail
+ * if the hwspinlock is already taken.
+ *
+ * Upon a successful return from this function, preemption is disabled,
+ * so the caller must not sleep, and is advised to release the hwspinlock
+ * as soon as possible. This is required in order to minimize remote cores
+ * polling on the hardware interconnect.
+ *
+ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if
+ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid.
+ */
+static inline int hwspin_trylock(struct hwspinlock *hwlock)
+{
+        return __hwspin_trylock(hwlock, 0, NULL);
+}
+
+/**
+ * hwspin_lock_timeout_irqsave() - lock hwspinlock, with timeout, disable irqs
+ * @hwlock: the hwspinlock to be locked
+ * @to: timeout value in msecs
+ * @flags: a pointer to where the caller's interrupt state will be saved at
+ *
+ * This function locks the underlying @hwlock. If the @hwlock
+ * is already taken, the function will busy loop waiting for it to
+ * be released, but give up when @timeout msecs have elapsed.
+ *
+ * Upon a successful return from this function, preemption and local interrupts
+ * are disabled (plus previous interrupt state is saved), so the caller must
+ * not sleep, and is advised to release the hwspinlock as soon as possible.
+ *
+ * Returns 0 when the @hwlock was successfully taken, and an appropriate
+ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still
+ * busy after @timeout msecs). The function will never sleep.
+ */
+static inline int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock,
+                                unsigned int to, unsigned long *flags)
+{
+        return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQSTATE, flags);
+}
+
+/**
+ * hwspin_lock_timeout_irq() - lock hwspinlock, with timeout, disable irqs
+ * @hwlock: the hwspinlock to be locked
+ * @to: timeout value in msecs
+ *
+ * This function locks the underlying @hwlock. If the @hwlock
+ * is already taken, the function will busy loop waiting for it to
+ * be released, but give up when @timeout msecs have elapsed.
+ *
+ * Upon a successful return from this function, preemption and local interrupts
+ * are disabled so the caller must not sleep, and is advised to release the
+ * hwspinlock as soon as possible.
+ *
+ * Returns 0 when the @hwlock was successfully taken, and an appropriate
+ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still
+ * busy after @timeout msecs). The function will never sleep.
+ */
+static inline
+int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int to)
+{
+        return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQ, NULL);
+}
+
+/**
+ * hwspin_lock_timeout() - lock an hwspinlock with timeout limit
+ * @hwlock: the hwspinlock to be locked
+ * @to: timeout value in msecs
+ *
+ * This function locks the underlying @hwlock. If the @hwlock
+ * is already taken, the function will busy loop waiting for it to
+ * be released, but give up when @timeout msecs have elapsed.
+ *
+ * Upon a successful return from this function, preemption is disabled
+ * so the caller must not sleep, and is advised to release the hwspinlock
+ * as soon as possible.
+ * This is required in order to minimize remote cores polling on the
+ * hardware interconnect.
+ *
+ * Returns 0 when the @hwlock was successfully taken, and an appropriate
+ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still
+ * busy after @timeout msecs). The function will never sleep.
+ */
+static inline
+int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to)
+{
+        return __hwspin_lock_timeout(hwlock, to, 0, NULL);
+}
+
+/**
+ * hwspin_unlock_irqrestore() - unlock hwspinlock, restore irq state
+ * @hwlock: a previously-acquired hwspinlock which we want to unlock
+ * @flags: previous caller's interrupt state to restore
+ *
+ * This function will unlock a specific hwspinlock, enable preemption and
+ * restore the previous state of the local interrupts. It should be used
+ * to undo, e.g., hwspin_trylock_irqsave().
+ *
+ * @hwlock must be already locked before calling this function: it is a bug
+ * to call unlock on a @hwlock that is already unlocked.
+ */
+static inline void hwspin_unlock_irqrestore(struct hwspinlock *hwlock,
+                                                        unsigned long *flags)
+{
+        __hwspin_unlock(hwlock, HWLOCK_IRQSTATE, flags);
+}
+
+/**
+ * hwspin_unlock_irq() - unlock hwspinlock, enable interrupts
+ * @hwlock: a previously-acquired hwspinlock which we want to unlock
+ *
+ * This function will unlock a specific hwspinlock, enable preemption and
+ * enable local interrupts. Should be used to undo hwspin_lock_irq().
+ *
+ * @hwlock must be already locked (e.g. by hwspin_trylock_irq()) before
+ * calling this function: it is a bug to call unlock on a @hwlock that is
+ * already unlocked.
+ */
+static inline void hwspin_unlock_irq(struct hwspinlock *hwlock)
+{
+        __hwspin_unlock(hwlock, HWLOCK_IRQ, NULL);
+}
+
+/**
+ * hwspin_unlock() - unlock hwspinlock
+ * @hwlock: a previously-acquired hwspinlock which we want to unlock
+ *
+ * This function will unlock a specific hwspinlock and enable preemption
+ * back.
+ *
+ * @hwlock must be already locked (e.g. by hwspin_trylock()) before calling
+ * this function: it is a bug to call unlock on a @hwlock that is already
+ * unlocked.
+ */
+static inline void hwspin_unlock(struct hwspinlock *hwlock)
+{
+        __hwspin_unlock(hwlock, 0, NULL);
+}
+
+#endif /* __LINUX_HWSPINLOCK_H */
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index cd6f3b431195..d60130f88eed 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -168,6 +168,7 @@
 #define ONENAND_SYS_CFG1_INT            (1 << 6)
 #define ONENAND_SYS_CFG1_IOBE           (1 << 5)
 #define ONENAND_SYS_CFG1_RDY_CONF       (1 << 4)
+#define ONENAND_SYS_CFG1_VHF            (1 << 3)
 #define ONENAND_SYS_CFG1_HF             (1 << 2)
 #define ONENAND_SYS_CFG1_SYNC_WRITE     (1 << 1)
 
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index d203f4da18a0..ede6afde7d2f 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -92,7 +92,7 @@ static const unsigned long omap1_mcbsp_port[][2] = {};
 static const int omap24xx_dma_reqs[][2] = {
         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
@@ -113,7 +113,7 @@ static const int omap44xx_dma_reqs[][2] = {
 static const int omap44xx_dma_reqs[][2] = {};
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 static const unsigned long omap2420_mcbsp_port[][2] = {
         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
@@ -124,7 +124,7 @@ static const unsigned long omap2420_mcbsp_port[][2] = {
 static const unsigned long omap2420_mcbsp_port[][2] = {};
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2430)
+#if defined(CONFIG_SOC_OMAP2430)
 static const unsigned long omap2430_mcbsp_port[][2] = {
         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index 110c106611d3..37dc7211ed3f 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -43,7 +43,7 @@ enum omap_mcbsp_div {
         OMAP_MCBSP_CLKGDV,              /* Sample rate generator divider */
 };
 
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_SOC_OMAP2420)
 #define NUM_LINKS       2
 #endif
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
@@ -54,7 +54,7 @@ enum omap_mcbsp_div {
 #undef  NUM_LINKS
 #define NUM_LINKS       4
 #endif
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430)
 #undef  NUM_LINKS
 #define NUM_LINKS       5
 #endif