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-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/Kconfig.debug26
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi11
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi11
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts36
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts188
-rw-r--r--arch/arm/mach-vexpress/Kconfig5
-rw-r--r--arch/arm/mach-vexpress/Makefile.boot3
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c64
-rw-r--r--arch/arm/mach-vexpress/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-vexpress/include/mach/debug-macro.S41
-rw-r--r--arch/arm/mach-vexpress/include/mach/motherboard.h28
-rw-r--r--arch/arm/mach-vexpress/include/mach/uncompress.h14
-rw-r--r--arch/arm/mach-vexpress/v2m.c296
-rw-r--r--arch/arm/plat-versatile/Kconfig3
-rw-r--r--arch/arm/plat-versatile/Makefile2
16 files changed, 506 insertions, 243 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8b0b743b4fb1..5cade3cec718 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -260,6 +260,7 @@ config ARCH_INTEGRATOR
260 select ICST 260 select ICST
261 select GENERIC_CLOCKEVENTS 261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE 262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_CLOCK
263 select PLAT_VERSATILE_FPGA_IRQ 264 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_IO_H 265 select NEED_MACH_IO_H
265 select NEED_MACH_MEMORY_H 266 select NEED_MACH_MEMORY_H
@@ -277,6 +278,7 @@ config ARCH_REALVIEW
277 select GENERIC_CLOCKEVENTS 278 select GENERIC_CLOCKEVENTS
278 select ARCH_WANT_OPTIONAL_GPIOLIB 279 select ARCH_WANT_OPTIONAL_GPIOLIB
279 select PLAT_VERSATILE 280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLOCK
280 select PLAT_VERSATILE_CLCD 282 select PLAT_VERSATILE_CLCD
281 select ARM_TIMER_SP804 283 select ARM_TIMER_SP804
282 select GPIO_PL061 if GPIOLIB 284 select GPIO_PL061 if GPIOLIB
@@ -295,6 +297,7 @@ config ARCH_VERSATILE
295 select ARCH_WANT_OPTIONAL_GPIOLIB 297 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select NEED_MACH_IO_H if PCI 298 select NEED_MACH_IO_H if PCI
297 select PLAT_VERSATILE 299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
298 select PLAT_VERSATILE_CLCD 301 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ 302 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804 303 select ARM_TIMER_SP804
@@ -307,7 +310,7 @@ config ARCH_VEXPRESS
307 select ARM_AMBA 310 select ARM_AMBA
308 select ARM_TIMER_SP804 311 select ARM_TIMER_SP804
309 select CLKDEV_LOOKUP 312 select CLKDEV_LOOKUP
310 select HAVE_MACH_CLKDEV 313 select COMMON_CLK
311 select GENERIC_CLOCKEVENTS 314 select GENERIC_CLOCKEVENTS
312 select HAVE_CLK 315 select HAVE_CLK
313 select HAVE_PATA_PLATFORM 316 select HAVE_PATA_PLATFORM
@@ -315,6 +318,7 @@ config ARCH_VEXPRESS
315 select NO_IOPORT 318 select NO_IOPORT
316 select PLAT_VERSATILE 319 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLCD 320 select PLAT_VERSATILE_CLCD
321 select REGULATOR_FIXED_VOLTAGE if REGULATOR
318 help 322 help
319 This enables support for the ARM Ltd Versatile Express boards. 323 This enables support for the ARM Ltd Versatile Express boards.
320 324
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 01a134141216..a03b5a7059e2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -310,6 +310,32 @@ choice
310 The uncompressor code port configuration is now handled 310 The uncompressor code port configuration is now handled
311 by CONFIG_S3C_LOWLEVEL_UART_PORT. 311 by CONFIG_S3C_LOWLEVEL_UART_PORT.
312 312
313 config DEBUG_VEXPRESS_UART0_DETECT
314 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
315 depends on ARCH_VEXPRESS && CPU_CP15_MMU
316 help
317 This option enables a simple heuristic which tries to determine
318 the motherboard's memory map variant (original or RS1) and then
319 choose the relevant UART0 base address.
320
321 Note that this will only work with standard A-class core tiles,
322 and may fail with non-standard SMM or custom software models.
323
324 config DEBUG_VEXPRESS_UART0_CA9
325 bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
326 depends on ARCH_VEXPRESS
327 help
328 This option selects UART0 at 0x10009000. Except for custom models,
329 this applies only to the V2P-CA9 tile.
330
331 config DEBUG_VEXPRESS_UART0_RS1
332 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
333 depends on ARCH_VEXPRESS
334 help
335 This option selects UART0 at 0x1c090000. This applies to most
336 of the tiles using the RS1 memory map, including all new A-class
337 core tiles, FPGA-based SMMs and software models.
338
313 config DEBUG_LL_UART_NONE 339 config DEBUG_LL_UART_NONE
314 bool "No low-level debugging UART" 340 bool "No low-level debugging UART"
315 help 341 help
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 16076e2d0934..d8a827bd2bf3 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -55,6 +55,8 @@
55 reg-io-width = <4>; 55 reg-io-width = <4>;
56 smsc,irq-active-high; 56 smsc,irq-active-high;
57 smsc,irq-push-pull; 57 smsc,irq-push-pull;
58 vdd33a-supply = <&v2m_fixed_3v3>;
59 vddvario-supply = <&v2m_fixed_3v3>;
58 }; 60 };
59 61
60 usb@2,03000000 { 62 usb@2,03000000 {
@@ -157,6 +159,7 @@
157 v2m_timer23: timer@120000 { 159 v2m_timer23: timer@120000 {
158 compatible = "arm,sp804", "arm,primecell"; 160 compatible = "arm,sp804", "arm,primecell";
159 reg = <0x120000 0x1000>; 161 reg = <0x120000 0x1000>;
162 interrupts = <3>;
160 }; 163 };
161 164
162 /* DVI I2C bus */ 165 /* DVI I2C bus */
@@ -197,5 +200,13 @@
197 interrupts = <14>; 200 interrupts = <14>;
198 }; 201 };
199 }; 202 };
203
204 v2m_fixed_3v3: fixedregulator@0 {
205 compatible = "regulator-fixed";
206 regulator-name = "3V3";
207 regulator-min-microvolt = <3300000>;
208 regulator-max-microvolt = <3300000>;
209 regulator-always-on;
210 };
200 }; 211 };
201}; 212};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index a6c9c7c82d53..dba53fd026bb 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -54,6 +54,8 @@
54 reg-io-width = <4>; 54 reg-io-width = <4>;
55 smsc,irq-active-high; 55 smsc,irq-active-high;
56 smsc,irq-push-pull; 56 smsc,irq-push-pull;
57 vdd33a-supply = <&v2m_fixed_3v3>;
58 vddvario-supply = <&v2m_fixed_3v3>;
57 }; 59 };
58 60
59 usb@3,03000000 { 61 usb@3,03000000 {
@@ -156,6 +158,7 @@
156 v2m_timer23: timer@12000 { 158 v2m_timer23: timer@12000 {
157 compatible = "arm,sp804", "arm,primecell"; 159 compatible = "arm,sp804", "arm,primecell";
158 reg = <0x12000 0x1000>; 160 reg = <0x12000 0x1000>;
161 interrupts = <3>;
159 }; 162 };
160 163
161 /* DVI I2C bus */ 164 /* DVI I2C bus */
@@ -196,5 +199,13 @@
196 interrupts = <14>; 199 interrupts = <14>;
197 }; 200 };
198 }; 201 };
202
203 v2m_fixed_3v3: fixedregulator@0 {
204 compatible = "regulator-fixed";
205 regulator-name = "3V3";
206 regulator-min-microvolt = <3300000>;
207 regulator-max-microvolt = <3300000>;
208 regulator-always-on;
209 };
199 }; 210 };
200}; 211};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 7e1091d91af8..d12b34ca0568 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -14,8 +14,8 @@
14 arm,hbi = <0x237>; 14 arm,hbi = <0x237>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <1>; 17 #address-cells = <2>;
18 #size-cells = <1>; 18 #size-cells = <2>;
19 19
20 chosen { }; 20 chosen { };
21 21
@@ -47,23 +47,23 @@
47 47
48 memory@80000000 { 48 memory@80000000 {
49 device_type = "memory"; 49 device_type = "memory";
50 reg = <0x80000000 0x40000000>; 50 reg = <0 0x80000000 0 0x40000000>;
51 }; 51 };
52 52
53 hdlcd@2b000000 { 53 hdlcd@2b000000 {
54 compatible = "arm,hdlcd"; 54 compatible = "arm,hdlcd";
55 reg = <0x2b000000 0x1000>; 55 reg = <0 0x2b000000 0 0x1000>;
56 interrupts = <0 85 4>; 56 interrupts = <0 85 4>;
57 }; 57 };
58 58
59 memory-controller@2b0a0000 { 59 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell"; 60 compatible = "arm,pl341", "arm,primecell";
61 reg = <0x2b0a0000 0x1000>; 61 reg = <0 0x2b0a0000 0 0x1000>;
62 }; 62 };
63 63
64 wdt@2b060000 { 64 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell"; 65 compatible = "arm,sp805", "arm,primecell";
66 reg = <0x2b060000 0x1000>; 66 reg = <0 0x2b060000 0 0x1000>;
67 interrupts = <98>; 67 interrupts = <98>;
68 }; 68 };
69 69
@@ -72,23 +72,23 @@
72 #interrupt-cells = <3>; 72 #interrupt-cells = <3>;
73 #address-cells = <0>; 73 #address-cells = <0>;
74 interrupt-controller; 74 interrupt-controller;
75 reg = <0x2c001000 0x1000>, 75 reg = <0 0x2c001000 0 0x1000>,
76 <0x2c002000 0x1000>, 76 <0 0x2c002000 0 0x1000>,
77 <0x2c004000 0x2000>, 77 <0 0x2c004000 0 0x2000>,
78 <0x2c006000 0x2000>; 78 <0 0x2c006000 0 0x2000>;
79 interrupts = <1 9 0xf04>; 79 interrupts = <1 9 0xf04>;
80 }; 80 };
81 81
82 memory-controller@7ffd0000 { 82 memory-controller@7ffd0000 {
83 compatible = "arm,pl354", "arm,primecell"; 83 compatible = "arm,pl354", "arm,primecell";
84 reg = <0x7ffd0000 0x1000>; 84 reg = <0 0x7ffd0000 0 0x1000>;
85 interrupts = <0 86 4>, 85 interrupts = <0 86 4>,
86 <0 87 4>; 86 <0 87 4>;
87 }; 87 };
88 88
89 dma@7ffb0000 { 89 dma@7ffb0000 {
90 compatible = "arm,pl330", "arm,primecell"; 90 compatible = "arm,pl330", "arm,primecell";
91 reg = <0x7ffb0000 0x1000>; 91 reg = <0 0x7ffb0000 0 0x1000>;
92 interrupts = <0 92 4>, 92 interrupts = <0 92 4>,
93 <0 88 4>, 93 <0 88 4>,
94 <0 89 4>, 94 <0 89 4>,
@@ -111,12 +111,12 @@
111 }; 111 };
112 112
113 motherboard { 113 motherboard {
114 ranges = <0 0 0x08000000 0x04000000>, 114 ranges = <0 0 0 0x08000000 0x04000000>,
115 <1 0 0x14000000 0x04000000>, 115 <1 0 0 0x14000000 0x04000000>,
116 <2 0 0x18000000 0x04000000>, 116 <2 0 0 0x18000000 0x04000000>,
117 <3 0 0x1c000000 0x04000000>, 117 <3 0 0 0x1c000000 0x04000000>,
118 <4 0 0x0c000000 0x04000000>, 118 <4 0 0 0x0c000000 0x04000000>,
119 <5 0 0x10000000 0x04000000>; 119 <5 0 0 0x10000000 0x04000000>;
120 120
121 interrupt-map-mask = <0 0 63>; 121 interrupt-map-mask = <0 0 63>;
122 interrupt-map = <0 0 0 &gic 0 0 4>, 122 interrupt-map = <0 0 0 &gic 0 0 4>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
new file mode 100644
index 000000000000..4890a81c5467
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -0,0 +1,188 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>;
15 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 };
40
41 cpu1: cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <1>;
45 };
46
47/* A7s disabled till big.LITTLE patches are available...
48 cpu2: cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a7";
51 reg = <0x100>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0x101>;
58 };
59
60 cpu4: cpu@4 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 reg = <0x102>;
64 };
65*/
66 };
67
68 memory@80000000 {
69 device_type = "memory";
70 reg = <0 0x80000000 0 0x40000000>;
71 };
72
73 wdt@2a490000 {
74 compatible = "arm,sp805", "arm,primecell";
75 reg = <0 0x2a490000 0 0x1000>;
76 interrupts = <98>;
77 };
78
79 hdlcd@2b000000 {
80 compatible = "arm,hdlcd";
81 reg = <0 0x2b000000 0 0x1000>;
82 interrupts = <0 85 4>;
83 };
84
85 memory-controller@2b0a0000 {
86 compatible = "arm,pl341", "arm,primecell";
87 reg = <0 0x2b0a0000 0 0x1000>;
88 };
89
90 gic: interrupt-controller@2c001000 {
91 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
94 interrupt-controller;
95 reg = <0 0x2c001000 0 0x1000>,
96 <0 0x2c002000 0 0x1000>,
97 <0 0x2c004000 0 0x2000>,
98 <0 0x2c006000 0 0x2000>;
99 interrupts = <1 9 0xf04>;
100 };
101
102 memory-controller@7ffd0000 {
103 compatible = "arm,pl354", "arm,primecell";
104 reg = <0 0x7ffd0000 0 0x1000>;
105 interrupts = <0 86 4>,
106 <0 87 4>;
107 };
108
109 dma@7ff00000 {
110 compatible = "arm,pl330", "arm,primecell";
111 reg = <0 0x7ff00000 0 0x1000>;
112 interrupts = <0 92 4>,
113 <0 88 4>,
114 <0 89 4>,
115 <0 90 4>,
116 <0 91 4>;
117 };
118
119 timer {
120 compatible = "arm,armv7-timer";
121 interrupts = <1 13 0xf08>,
122 <1 14 0xf08>,
123 <1 11 0xf08>,
124 <1 10 0xf08>;
125 };
126
127 pmu {
128 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
129 interrupts = <0 68 4>,
130 <0 69 4>;
131 };
132
133 motherboard {
134 ranges = <0 0 0 0x08000000 0x04000000>,
135 <1 0 0 0x14000000 0x04000000>,
136 <2 0 0 0x18000000 0x04000000>,
137 <3 0 0 0x1c000000 0x04000000>,
138 <4 0 0 0x0c000000 0x04000000>,
139 <5 0 0 0x10000000 0x04000000>;
140
141 interrupt-map-mask = <0 0 63>;
142 interrupt-map = <0 0 0 &gic 0 0 4>,
143 <0 0 1 &gic 0 1 4>,
144 <0 0 2 &gic 0 2 4>,
145 <0 0 3 &gic 0 3 4>,
146 <0 0 4 &gic 0 4 4>,
147 <0 0 5 &gic 0 5 4>,
148 <0 0 6 &gic 0 6 4>,
149 <0 0 7 &gic 0 7 4>,
150 <0 0 8 &gic 0 8 4>,
151 <0 0 9 &gic 0 9 4>,
152 <0 0 10 &gic 0 10 4>,
153 <0 0 11 &gic 0 11 4>,
154 <0 0 12 &gic 0 12 4>,
155 <0 0 13 &gic 0 13 4>,
156 <0 0 14 &gic 0 14 4>,
157 <0 0 15 &gic 0 15 4>,
158 <0 0 16 &gic 0 16 4>,
159 <0 0 17 &gic 0 17 4>,
160 <0 0 18 &gic 0 18 4>,
161 <0 0 19 &gic 0 19 4>,
162 <0 0 20 &gic 0 20 4>,
163 <0 0 21 &gic 0 21 4>,
164 <0 0 22 &gic 0 22 4>,
165 <0 0 23 &gic 0 23 4>,
166 <0 0 24 &gic 0 24 4>,
167 <0 0 25 &gic 0 25 4>,
168 <0 0 26 &gic 0 26 4>,
169 <0 0 27 &gic 0 27 4>,
170 <0 0 28 &gic 0 28 4>,
171 <0 0 29 &gic 0 29 4>,
172 <0 0 30 &gic 0 30 4>,
173 <0 0 31 &gic 0 31 4>,
174 <0 0 32 &gic 0 32 4>,
175 <0 0 33 &gic 0 33 4>,
176 <0 0 34 &gic 0 34 4>,
177 <0 0 35 &gic 0 35 4>,
178 <0 0 36 &gic 0 36 4>,
179 <0 0 37 &gic 0 37 4>,
180 <0 0 38 &gic 0 38 4>,
181 <0 0 39 &gic 0 39 4>,
182 <0 0 40 &gic 0 40 4>,
183 <0 0 41 &gic 0 41 4>,
184 <0 0 42 &gic 0 42 4>;
185 };
186};
187
188/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index cf8730d35e70..fc3730f01650 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -2,7 +2,8 @@ menu "Versatile Express platform type"
2 depends on ARCH_VEXPRESS 2 depends on ARCH_VEXPRESS
3 3
4config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA 4config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
5 bool 5 bool "Enable A5 and A9 only errata work-arounds"
6 default y
6 select ARM_ERRATA_720789 7 select ARM_ERRATA_720789
7 select ARM_ERRATA_751472 8 select ARM_ERRATA_751472
8 select PL310_ERRATA_753970 if CACHE_PL310 9 select PL310_ERRATA_753970 if CACHE_PL310
@@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
14 15
15config ARCH_VEXPRESS_CA9X4 16config ARCH_VEXPRESS_CA9X4
16 bool "Versatile Express Cortex-A9x4 tile" 17 bool "Versatile Express Cortex-A9x4 tile"
17 select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
18 select ARM_GIC 18 select ARM_GIC
19 select CPU_V7 19 select CPU_V7
20 select HAVE_SMP 20 select HAVE_SMP
@@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
22 22
23config ARCH_VEXPRESS_DT 23config ARCH_VEXPRESS_DT
24 bool "Device Tree support for Versatile Express platforms" 24 bool "Device Tree support for Versatile Express platforms"
25 select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
26 select ARM_GIC 25 select ARM_GIC
27 select ARM_PATCH_PHYS_VIRT 26 select ARM_PATCH_PHYS_VIRT
28 select AUTO_ZRELADDR 27 select AUTO_ZRELADDR
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 909f85ebf5f4..318d308dfb93 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -6,4 +6,5 @@ initrd_phys-y := 0x60800000
6 6
7dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \ 7dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
8 vexpress-v2p-ca9.dtb \ 8 vexpress-v2p-ca9.dtb \
9 vexpress-v2p-ca15-tc1.dtb 9 vexpress-v2p-ca15-tc1.dtb \
10 vexpress-v2p-ca15_a7.dtb
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index c65cc3b462a5..61c492403b05 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void)
66 66
67static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) 67static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
68{ 68{
69 v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); 69 u32 site = v2m_get_master_site();
70 v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2); 70
71 /*
72 * Old firmware was using the "site" component of the command
73 * to control the DVI muxer (while it should be always 0 ie. MB).
74 * Newer firmware uses the data register. Keep both for compatibility.
75 */
76 v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
77 v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
71} 78}
72 79
73static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) 80static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@@ -105,43 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
105}; 112};
106 113
107 114
108static long ct_round(struct clk *clk, unsigned long rate) 115static struct v2m_osc ct_osc1 = {
109{ 116 .osc = 1,
110 return rate; 117 .rate_min = 10000000,
111} 118 .rate_max = 80000000,
112 119 .rate_default = 23750000,
113static int ct_set(struct clk *clk, unsigned long rate)
114{
115 return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
116}
117
118static const struct clk_ops osc1_clk_ops = {
119 .round = ct_round,
120 .set = ct_set,
121};
122
123static struct clk osc1_clk = {
124 .ops = &osc1_clk_ops,
125 .rate = 24000000,
126};
127
128static struct clk ct_sp804_clk = {
129 .rate = 1000000,
130};
131
132static struct clk_lookup lookups[] = {
133 { /* CLCD */
134 .dev_id = "ct:clcd",
135 .clk = &osc1_clk,
136 }, { /* SP804 timers */
137 .dev_id = "sp804",
138 .con_id = "ct-timer0",
139 .clk = &ct_sp804_clk,
140 }, { /* SP804 timers */
141 .dev_id = "sp804",
142 .con_id = "ct-timer1",
143 .clk = &ct_sp804_clk,
144 },
145}; 120};
146 121
147static struct resource pmu_resources[] = { 122static struct resource pmu_resources[] = {
@@ -174,14 +149,10 @@ static struct platform_device pmu_device = {
174 .resource = pmu_resources, 149 .resource = pmu_resources,
175}; 150};
176 151
177static void __init ct_ca9x4_init_early(void)
178{
179 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
180}
181
182static void __init ct_ca9x4_init(void) 152static void __init ct_ca9x4_init(void)
183{ 153{
184 int i; 154 int i;
155 struct clk *clk;
185 156
186#ifdef CONFIG_CACHE_L2X0 157#ifdef CONFIG_CACHE_L2X0
187 void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); 158 void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -193,6 +164,10 @@ static void __init ct_ca9x4_init(void)
193 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); 164 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
194#endif 165#endif
195 166
167 ct_osc1.site = v2m_get_master_site();
168 clk = v2m_osc_register("ct:osc1", &ct_osc1);
169 clk_register_clkdev(clk, NULL, "ct:clcd");
170
196 for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) 171 for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
197 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); 172 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
198 173
@@ -234,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
234 .id = V2M_CT_ID_CA9, 209 .id = V2M_CT_ID_CA9,
235 .name = "CA9x4", 210 .name = "CA9x4",
236 .map_io = ct_ca9x4_map_io, 211 .map_io = ct_ca9x4_map_io,
237 .init_early = ct_ca9x4_init_early,
238 .init_irq = ct_ca9x4_init_irq, 212 .init_irq = ct_ca9x4_init_irq,
239 .init_tile = ct_ca9x4_init, 213 .init_tile = ct_ca9x4_init,
240#ifdef CONFIG_SMP 214#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h
deleted file mode 100644
index 3f8307d73cad..000000000000
--- a/arch/arm/mach-vexpress/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#include <plat/clock.h>
5
6struct clk {
7 const struct clk_ops *ops;
8 unsigned long rate;
9 const struct icst_params *params;
10};
11
12#define __clk_get(clk) ({ 1; })
13#define __clk_put(clk) do { } while (0)
14
15#endif
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fa8224794e0b..9f509f55d078 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -18,6 +18,8 @@
18 18
19#define DEBUG_LL_VIRT_BASE 0xf8000000 19#define DEBUG_LL_VIRT_BASE 0xf8000000
20 20
21#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
22
21 .macro addruart,rp,rv,tmp 23 .macro addruart,rp,rv,tmp
22 24
23 @ Make an educated guess regarding the memory map: 25 @ Make an educated guess regarding the memory map:
@@ -41,3 +43,42 @@
41 .endm 43 .endm
42 44
43#include <asm/hardware/debug-pl01x.S> 45#include <asm/hardware/debug-pl01x.S>
46
47#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
48
49 .macro addruart,rp,rv,tmp
50 mov \rp, #DEBUG_LL_UART_OFFSET
51 orr \rv, \rp, #DEBUG_LL_VIRT_BASE
52 orr \rp, \rp, #DEBUG_LL_PHYS_BASE
53 .endm
54
55#include <asm/hardware/debug-pl01x.S>
56
57#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
58
59 .macro addruart,rp,rv,tmp
60 mov \rp, #DEBUG_LL_UART_OFFSET_RS1
61 orr \rv, \rp, #DEBUG_LL_VIRT_BASE
62 orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
63 .endm
64
65#include <asm/hardware/debug-pl01x.S>
66
67#else /* CONFIG_DEBUG_LL_UART_NONE */
68
69 .macro addruart, rp, rv, tmp
70 /* Safe dummy values */
71 mov \rp, #0
72 mov \rv, #DEBUG_LL_VIRT_BASE
73 .endm
74
75 .macro senduart,rd,rx
76 .endm
77
78 .macro waituart,rd,rx
79 .endm
80
81 .macro busyuart,rd,rx
82 .endm
83
84#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 31a92890893d..1e388c7bf4d7 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,6 +1,8 @@
1#ifndef __MACH_MOTHERBOARD_H 1#ifndef __MACH_MOTHERBOARD_H
2#define __MACH_MOTHERBOARD_H 2#define __MACH_MOTHERBOARD_H
3 3
4#include <linux/clk-provider.h>
5
4/* 6/*
5 * Physical addresses, offset from V2M_PA_CS0-3 7 * Physical addresses, offset from V2M_PA_CS0-3
6 */ 8 */
@@ -104,9 +106,10 @@
104#define SYS_CFG_REBOOT (9 << 20) 106#define SYS_CFG_REBOOT (9 << 20)
105#define SYS_CFG_DVIMODE (11 << 20) 107#define SYS_CFG_DVIMODE (11 << 20)
106#define SYS_CFG_POWER (12 << 20) 108#define SYS_CFG_POWER (12 << 20)
107#define SYS_CFG_SITE_MB (0 << 16) 109#define SYS_CFG_SITE(n) ((n) << 16)
108#define SYS_CFG_SITE_DB1 (1 << 16) 110#define SYS_CFG_SITE_MB 0
109#define SYS_CFG_SITE_DB2 (2 << 16) 111#define SYS_CFG_SITE_DB1 1
112#define SYS_CFG_SITE_DB2 2
110#define SYS_CFG_STACK(n) ((n) << 12) 113#define SYS_CFG_STACK(n) ((n) << 12)
111 114
112#define SYS_CFG_ERR (1 << 1) 115#define SYS_CFG_ERR (1 << 1)
@@ -122,6 +125,8 @@ void v2m_flags_set(u32 data);
122#define SYS_MISC_MASTERSITE (1 << 14) 125#define SYS_MISC_MASTERSITE (1 << 14)
123#define SYS_PROCIDx_HBI_MASK 0xfff 126#define SYS_PROCIDx_HBI_MASK 0xfff
124 127
128int v2m_get_master_site(void);
129
125/* 130/*
126 * Core tile IDs 131 * Core tile IDs
127 */ 132 */
@@ -144,4 +149,21 @@ struct ct_desc {
144 149
145extern struct ct_desc *ct_desc; 150extern struct ct_desc *ct_desc;
146 151
152/*
153 * OSC clock provider
154 */
155struct v2m_osc {
156 struct clk_hw hw;
157 u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
158 u8 stack; /* board stack position */
159 u16 osc;
160 unsigned long rate_min;
161 unsigned long rate_max;
162 unsigned long rate_default;
163};
164
165#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
166
167struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
168
147#endif 169#endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7dab5596b868..1e472eb0bbdc 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -27,6 +27,7 @@
27 27
28static unsigned long get_uart_base(void) 28static unsigned long get_uart_base(void)
29{ 29{
30#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
30 unsigned long mpcore_periph; 31 unsigned long mpcore_periph;
31 32
32 /* 33 /*
@@ -42,6 +43,13 @@ static unsigned long get_uart_base(void)
42 return UART_BASE; 43 return UART_BASE;
43 else 44 else
44 return UART_BASE_RS1; 45 return UART_BASE_RS1;
46#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
47 return UART_BASE;
48#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
49 return UART_BASE_RS1;
50#else
51 return 0;
52#endif
45} 53}
46 54
47/* 55/*
@@ -51,6 +59,9 @@ static inline void putc(int c)
51{ 59{
52 unsigned long base = get_uart_base(); 60 unsigned long base = get_uart_base();
53 61
62 if (!base)
63 return;
64
54 while (AMBA_UART_FR(base) & (1 << 5)) 65 while (AMBA_UART_FR(base) & (1 << 5))
55 barrier(); 66 barrier();
56 67
@@ -61,6 +72,9 @@ static inline void flush(void)
61{ 72{
62 unsigned long base = get_uart_base(); 73 unsigned long base = get_uart_base();
63 74
75 if (!base)
76 return;
77
64 while (AMBA_UART_FR(base) & (1 << 3)) 78 while (AMBA_UART_FR(base) & (1 << 3))
65 barrier(); 79 barrier();
66} 80}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fde26adaef32..37608f22ee31 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,7 +16,10 @@
16#include <linux/spinlock.h> 16#include <linux/spinlock.h>
17#include <linux/usb/isp1760.h> 17#include <linux/usb/isp1760.h>
18#include <linux/clkdev.h> 18#include <linux/clkdev.h>
19#include <linux/clk-provider.h>
19#include <linux/mtd/physmap.h> 20#include <linux/mtd/physmap.h>
21#include <linux/regulator/fixed.h>
22#include <linux/regulator/machine.h>
20 23
21#include <asm/arch_timer.h> 24#include <asm/arch_timer.h>
22#include <asm/mach-types.h> 25#include <asm/mach-types.h>
@@ -81,16 +84,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
81 sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); 84 sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
82} 85}
83 86
84static void __init v2m_timer_init(void)
85{
86 v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
87 v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
88}
89
90static struct sys_timer v2m_timer = {
91 .init = v2m_timer_init,
92};
93
94 87
95static DEFINE_SPINLOCK(v2m_cfg_lock); 88static DEFINE_SPINLOCK(v2m_cfg_lock);
96 89
@@ -147,6 +140,13 @@ void __init v2m_flags_set(u32 data)
147 writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET); 140 writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
148} 141}
149 142
143int v2m_get_master_site(void)
144{
145 u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
146
147 return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
148}
149
150 150
151static struct resource v2m_pcie_i2c_resource = { 151static struct resource v2m_pcie_i2c_resource = {
152 .start = V2M_SERIAL_BUS_PCI, 152 .start = V2M_SERIAL_BUS_PCI,
@@ -201,6 +201,11 @@ static struct platform_device v2m_eth_device = {
201 .dev.platform_data = &v2m_eth_config, 201 .dev.platform_data = &v2m_eth_config,
202}; 202};
203 203
204static struct regulator_consumer_supply v2m_eth_supplies[] = {
205 REGULATOR_SUPPLY("vddvario", "smsc911x"),
206 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
207};
208
204static struct resource v2m_usb_resources[] = { 209static struct resource v2m_usb_resources[] = {
205 { 210 {
206 .start = V2M_ISP1761, 211 .start = V2M_ISP1761,
@@ -319,98 +324,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
319}; 324};
320 325
321 326
322static long v2m_osc_round(struct clk *clk, unsigned long rate) 327static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
328 unsigned long parent_rate)
329{
330 struct v2m_osc *osc = to_v2m_osc(hw);
331
332 return !parent_rate ? osc->rate_default : parent_rate;
333}
334
335static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
336 unsigned long *parent_rate)
323{ 337{
338 struct v2m_osc *osc = to_v2m_osc(hw);
339
340 if (WARN_ON(rate < osc->rate_min))
341 rate = osc->rate_min;
342
343 if (WARN_ON(rate > osc->rate_max))
344 rate = osc->rate_max;
345
324 return rate; 346 return rate;
325} 347}
326 348
327static int v2m_osc1_set(struct clk *clk, unsigned long rate) 349static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
350 unsigned long parent_rate)
328{ 351{
329 return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate); 352 struct v2m_osc *osc = to_v2m_osc(hw);
353
354 v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
355 SYS_CFG_STACK(osc->stack) | osc->osc, rate);
356
357 return 0;
330} 358}
331 359
332static const struct clk_ops osc1_clk_ops = { 360static struct clk_ops v2m_osc_ops = {
333 .round = v2m_osc_round, 361 .recalc_rate = v2m_osc_recalc_rate,
334 .set = v2m_osc1_set, 362 .round_rate = v2m_osc_round_rate,
335}; 363 .set_rate = v2m_osc_set_rate,
336 364};
337static struct clk osc1_clk = { 365
338 .ops = &osc1_clk_ops, 366struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
339 .rate = 24000000, 367{
340}; 368 struct clk_init_data init;
341 369
342static struct clk osc2_clk = { 370 WARN_ON(osc->site > 2);
343 .rate = 24000000, 371 WARN_ON(osc->stack > 15);
344}; 372 WARN_ON(osc->osc > 4095);
345 373
346static struct clk v2m_sp804_clk = { 374 init.name = name;
347 .rate = 1000000, 375 init.ops = &v2m_osc_ops;
348}; 376 init.flags = CLK_IS_ROOT;
349 377 init.num_parents = 0;
350static struct clk v2m_ref_clk = { 378
351 .rate = 32768, 379 osc->hw.init = &init;
352}; 380
353 381 return clk_register(NULL, &osc->hw);
354static struct clk dummy_apb_pclk; 382}
355 383
356static struct clk_lookup v2m_lookups[] = { 384static struct v2m_osc v2m_mb_osc1 = {
357 { /* AMBA bus clock */ 385 .site = SYS_CFG_SITE_MB,
358 .con_id = "apb_pclk", 386 .osc = 1,
359 .clk = &dummy_apb_pclk, 387 .rate_min = 23750000,
360 }, { /* UART0 */ 388 .rate_max = 63500000,
361 .dev_id = "mb:uart0", 389 .rate_default = 23750000,
362 .clk = &osc2_clk, 390};
363 }, { /* UART1 */ 391
364 .dev_id = "mb:uart1", 392static const char *v2m_ref_clk_periphs[] __initconst = {
365 .clk = &osc2_clk, 393 "mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */
366 }, { /* UART2 */ 394};
367 .dev_id = "mb:uart2", 395
368 .clk = &osc2_clk, 396static const char *v2m_osc1_periphs[] __initconst = {
369 }, { /* UART3 */ 397 "mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */
370 .dev_id = "mb:uart3", 398};
371 .clk = &osc2_clk, 399
372 }, { /* KMI0 */ 400static const char *v2m_osc2_periphs[] __initconst = {
373 .dev_id = "mb:kmi0", 401 "mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */
374 .clk = &osc2_clk, 402 "mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */
375 }, { /* KMI1 */ 403 "mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */
376 .dev_id = "mb:kmi1", 404 "mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */
377 .clk = &osc2_clk, 405 "mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */
378 }, { /* MMC0 */ 406 "mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */
379 .dev_id = "mb:mmci", 407 "mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */
380 .clk = &osc2_clk, 408};
381 }, { /* CLCD */ 409
382 .dev_id = "mb:clcd", 410static void __init v2m_clk_init(void)
383 .clk = &osc1_clk, 411{
384 }, { /* SP805 WDT */ 412 struct clk *clk;
385 .dev_id = "mb:wdt", 413 int i;
386 .clk = &v2m_ref_clk, 414
387 }, { /* SP804 timers */ 415 clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
388 .dev_id = "sp804", 416 CLK_IS_ROOT, 0);
389 .con_id = "v2m-timer0", 417 WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
390 .clk = &v2m_sp804_clk, 418
391 }, { /* SP804 timers */ 419 clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
392 .dev_id = "sp804", 420 CLK_IS_ROOT, 32768);
393 .con_id = "v2m-timer1", 421 for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
394 .clk = &v2m_sp804_clk, 422 WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
395 }, 423
424 clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
425 CLK_IS_ROOT, 1000000);
426 WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
427 WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
428
429 clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
430 for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
431 WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
432
433 clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
434 CLK_IS_ROOT, 24000000);
435 for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
436 WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
437}
438
439static void __init v2m_timer_init(void)
440{
441 v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
442 v2m_clk_init();
443 v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
444}
445
446static struct sys_timer v2m_timer = {
447 .init = v2m_timer_init,
396}; 448};
397 449
398static void __init v2m_init_early(void) 450static void __init v2m_init_early(void)
399{ 451{
400 ct_desc->init_early(); 452 if (ct_desc->init_early)
401 clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); 453 ct_desc->init_early();
402 versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); 454 versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
403} 455}
404 456
405static void v2m_power_off(void) 457static void v2m_power_off(void)
406{ 458{
407 if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) 459 if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
408 printk(KERN_EMERG "Unable to shutdown\n"); 460 printk(KERN_EMERG "Unable to shutdown\n");
409} 461}
410 462
411static void v2m_restart(char str, const char *cmd) 463static void v2m_restart(char str, const char *cmd)
412{ 464{
413 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) 465 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
414 printk(KERN_EMERG "Unable to reboot\n"); 466 printk(KERN_EMERG "Unable to reboot\n");
415} 467}
416 468
@@ -458,6 +510,9 @@ static void __init v2m_init(void)
458{ 510{
459 int i; 511 int i;
460 512
513 regulator_register_fixed(0, v2m_eth_supplies,
514 ARRAY_SIZE(v2m_eth_supplies));
515
461 platform_device_register(&v2m_pcie_i2c_device); 516 platform_device_register(&v2m_pcie_i2c_device);
462 platform_device_register(&v2m_ddc_i2c_device); 517 platform_device_register(&v2m_ddc_i2c_device);
463 platform_device_register(&v2m_flash_device); 518 platform_device_register(&v2m_flash_device);
@@ -522,77 +577,6 @@ void __init v2m_dt_map_io(void)
522#endif 577#endif
523} 578}
524 579
525static struct clk_lookup v2m_dt_lookups[] = {
526 { /* AMBA bus clock */
527 .con_id = "apb_pclk",
528 .clk = &dummy_apb_pclk,
529 }, { /* SP804 timers */
530 .dev_id = "sp804",
531 .con_id = "v2m-timer0",
532 .clk = &v2m_sp804_clk,
533 }, { /* SP804 timers */
534 .dev_id = "sp804",
535 .con_id = "v2m-timer1",
536 .clk = &v2m_sp804_clk,
537 }, { /* PL180 MMCI */
538 .dev_id = "mb:mmci", /* 10005000.mmci */
539 .clk = &osc2_clk,
540 }, { /* PL050 KMI0 */
541 .dev_id = "10006000.kmi",
542 .clk = &osc2_clk,
543 }, { /* PL050 KMI1 */
544 .dev_id = "10007000.kmi",
545 .clk = &osc2_clk,
546 }, { /* PL011 UART0 */
547 .dev_id = "10009000.uart",
548 .clk = &osc2_clk,
549 }, { /* PL011 UART1 */
550 .dev_id = "1000a000.uart",
551 .clk = &osc2_clk,
552 }, { /* PL011 UART2 */
553 .dev_id = "1000b000.uart",
554 .clk = &osc2_clk,
555 }, { /* PL011 UART3 */
556 .dev_id = "1000c000.uart",
557 .clk = &osc2_clk,
558 }, { /* SP805 WDT */
559 .dev_id = "1000f000.wdt",
560 .clk = &v2m_ref_clk,
561 }, { /* PL111 CLCD */
562 .dev_id = "1001f000.clcd",
563 .clk = &osc1_clk,
564 },
565 /* RS1 memory map */
566 { /* PL180 MMCI */
567 .dev_id = "mb:mmci", /* 1c050000.mmci */
568 .clk = &osc2_clk,
569 }, { /* PL050 KMI0 */
570 .dev_id = "1c060000.kmi",
571 .clk = &osc2_clk,
572 }, { /* PL050 KMI1 */
573 .dev_id = "1c070000.kmi",
574 .clk = &osc2_clk,
575 }, { /* PL011 UART0 */
576 .dev_id = "1c090000.uart",
577 .clk = &osc2_clk,
578 }, { /* PL011 UART1 */
579 .dev_id = "1c0a0000.uart",
580 .clk = &osc2_clk,
581 }, { /* PL011 UART2 */
582 .dev_id = "1c0b0000.uart",
583 .clk = &osc2_clk,
584 }, { /* PL011 UART3 */
585 .dev_id = "1c0c0000.uart",
586 .clk = &osc2_clk,
587 }, { /* SP805 WDT */
588 .dev_id = "1c0f0000.wdt",
589 .clk = &v2m_ref_clk,
590 }, { /* PL111 CLCD */
591 .dev_id = "1c1f0000.clcd",
592 .clk = &osc1_clk,
593 },
594};
595
596void __init v2m_dt_init_early(void) 580void __init v2m_dt_init_early(void)
597{ 581{
598 struct device_node *node; 582 struct device_node *node;
@@ -605,8 +589,8 @@ void __init v2m_dt_init_early(void)
605 589
606 /* Confirm board type against DT property, if available */ 590 /* Confirm board type against DT property, if available */
607 if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { 591 if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
608 u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); 592 int site = v2m_get_master_site();
609 u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ? 593 u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
610 V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); 594 V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
611 u32 hbi = id & SYS_PROCIDx_HBI_MASK; 595 u32 hbi = id & SYS_PROCIDx_HBI_MASK;
612 596
@@ -614,8 +598,6 @@ void __init v2m_dt_init_early(void)
614 pr_warning("vexpress: DT HBI (%x) is not matching " 598 pr_warning("vexpress: DT HBI (%x) is not matching "
615 "hardware (%x)!\n", dt_hbi, hbi); 599 "hardware (%x)!\n", dt_hbi, hbi);
616 } 600 }
617
618 clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
619} 601}
620 602
621static struct of_device_id vexpress_irq_match[] __initdata = { 603static struct of_device_id vexpress_irq_match[] __initdata = {
@@ -637,6 +619,8 @@ static void __init v2m_dt_timer_init(void)
637 node = of_find_compatible_node(NULL, NULL, "arm,sp810"); 619 node = of_find_compatible_node(NULL, NULL, "arm,sp810");
638 v2m_sysctl_init(of_iomap(node, 0)); 620 v2m_sysctl_init(of_iomap(node, 0));
639 621
622 v2m_clk_init();
623
640 err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); 624 err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
641 if (WARN_ON(err)) 625 if (WARN_ON(err))
642 return; 626 return;
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 81ee7cc34457..8d5c10a5084d 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -1,5 +1,8 @@
1if PLAT_VERSATILE 1if PLAT_VERSATILE
2 2
3config PLAT_VERSATILE_CLOCK
4 bool
5
3config PLAT_VERSATILE_CLCD 6config PLAT_VERSATILE_CLCD
4 bool 7 bool
5 8
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index a5cb1945bdcc..272769a8a7d6 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,4 +1,4 @@
1obj-y := clock.o 1obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
2obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o 2obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
3obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o 3obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
4obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o 4obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 06:57:28 -0400