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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c101
1 files changed, 3 insertions, 98 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6abc75753e42..dd2f733649df 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1107,11 +1107,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1107}; 1107};
1108 1108
1109static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 1109static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110 { .name = "mmu_cache", .rst_shift = 1 },
1111};
1112
1113static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1114 { .name = "dsp", .rst_shift = 0 }, 1110 { .name = "dsp", .rst_shift = 0 },
1111 { .name = "mmu_cache", .rst_shift = 1 },
1115}; 1112};
1116 1113
1117/* dsp -> iva */ 1114/* dsp -> iva */
@@ -1141,21 +1138,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1141 &omap44xx_l4_cfg__dsp, 1138 &omap44xx_l4_cfg__dsp,
1142}; 1139};
1143 1140
1144/* Pseudo hwmod for reset control purpose only */
1145static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1146 .name = "dsp_c0",
1147 .class = &omap44xx_dsp_hwmod_class,
1148 .clkdm_name = "tesla_clkdm",
1149 .flags = HWMOD_INIT_NO_RESET,
1150 .rst_lines = omap44xx_dsp_c0_resets,
1151 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1152 .prcm = {
1153 .omap4 = {
1154 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1155 },
1156 },
1157};
1158
1159static struct omap_hwmod omap44xx_dsp_hwmod = { 1141static struct omap_hwmod omap44xx_dsp_hwmod = {
1160 .name = "dsp", 1142 .name = "dsp",
1161 .class = &omap44xx_dsp_hwmod_class, 1143 .class = &omap44xx_dsp_hwmod_class,
@@ -2504,15 +2486,9 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2504 { .irq = -1 } 2486 { .irq = -1 }
2505}; 2487};
2506 2488
2507static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { 2489static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2508 { .name = "cpu0", .rst_shift = 0 }, 2490 { .name = "cpu0", .rst_shift = 0 },
2509};
2510
2511static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2512 { .name = "cpu1", .rst_shift = 1 }, 2491 { .name = "cpu1", .rst_shift = 1 },
2513};
2514
2515static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2516 { .name = "mmu_cache", .rst_shift = 2 }, 2492 { .name = "mmu_cache", .rst_shift = 2 },
2517}; 2493};
2518 2494
@@ -2534,36 +2510,6 @@ static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2534 &omap44xx_l3_main_2__ipu, 2510 &omap44xx_l3_main_2__ipu,
2535}; 2511};
2536 2512
2537/* Pseudo hwmod for reset control purpose only */
2538static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2539 .name = "ipu_c0",
2540 .class = &omap44xx_ipu_hwmod_class,
2541 .clkdm_name = "ducati_clkdm",
2542 .flags = HWMOD_INIT_NO_RESET,
2543 .rst_lines = omap44xx_ipu_c0_resets,
2544 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2545 .prcm = {
2546 .omap4 = {
2547 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548 },
2549 },
2550};
2551
2552/* Pseudo hwmod for reset control purpose only */
2553static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2554 .name = "ipu_c1",
2555 .class = &omap44xx_ipu_hwmod_class,
2556 .clkdm_name = "ducati_clkdm",
2557 .flags = HWMOD_INIT_NO_RESET,
2558 .rst_lines = omap44xx_ipu_c1_resets,
2559 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2560 .prcm = {
2561 .omap4 = {
2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563 },
2564 },
2565};
2566
2567static struct omap_hwmod omap44xx_ipu_hwmod = { 2513static struct omap_hwmod omap44xx_ipu_hwmod = {
2568 .name = "ipu", 2514 .name = "ipu",
2569 .class = &omap44xx_ipu_hwmod_class, 2515 .class = &omap44xx_ipu_hwmod_class,
@@ -2702,15 +2648,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2702}; 2648};
2703 2649
2704static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 2650static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2705 { .name = "logic", .rst_shift = 2 },
2706};
2707
2708static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2709 { .name = "seq0", .rst_shift = 0 }, 2651 { .name = "seq0", .rst_shift = 0 },
2710};
2711
2712static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2713 { .name = "seq1", .rst_shift = 1 }, 2652 { .name = "seq1", .rst_shift = 1 },
2653 { .name = "logic", .rst_shift = 2 },
2714}; 2654};
2715 2655
2716/* iva master ports */ 2656/* iva master ports */
@@ -2743,36 +2683,6 @@ static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2743 &omap44xx_l3_main_2__iva, 2683 &omap44xx_l3_main_2__iva,
2744}; 2684};
2745 2685
2746/* Pseudo hwmod for reset control purpose only */
2747static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2748 .name = "iva_seq0",
2749 .class = &omap44xx_iva_hwmod_class,
2750 .clkdm_name = "ivahd_clkdm",
2751 .flags = HWMOD_INIT_NO_RESET,
2752 .rst_lines = omap44xx_iva_seq0_resets,
2753 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2754 .prcm = {
2755 .omap4 = {
2756 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2757 },
2758 },
2759};
2760
2761/* Pseudo hwmod for reset control purpose only */
2762static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2763 .name = "iva_seq1",
2764 .class = &omap44xx_iva_hwmod_class,
2765 .clkdm_name = "ivahd_clkdm",
2766 .flags = HWMOD_INIT_NO_RESET,
2767 .rst_lines = omap44xx_iva_seq1_resets,
2768 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2769 .prcm = {
2770 .omap4 = {
2771 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2772 },
2773 },
2774};
2775
2776static struct omap_hwmod omap44xx_iva_hwmod = { 2686static struct omap_hwmod omap44xx_iva_hwmod = {
2777 .name = "iva", 2687 .name = "iva",
2778 .class = &omap44xx_iva_hwmod_class, 2688 .class = &omap44xx_iva_hwmod_class,
@@ -5571,7 +5481,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5571 5481
5572 /* dsp class */ 5482 /* dsp class */
5573 &omap44xx_dsp_hwmod, 5483 &omap44xx_dsp_hwmod,
5574 &omap44xx_dsp_c0_hwmod,
5575 5484
5576 /* dss class */ 5485 /* dss class */
5577 &omap44xx_dss_hwmod, 5486 &omap44xx_dss_hwmod,
@@ -5601,16 +5510,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5601 5510
5602 /* ipu class */ 5511 /* ipu class */
5603 &omap44xx_ipu_hwmod, 5512 &omap44xx_ipu_hwmod,
5604 &omap44xx_ipu_c0_hwmod,
5605 &omap44xx_ipu_c1_hwmod,
5606 5513
5607 /* iss class */ 5514 /* iss class */
5608/* &omap44xx_iss_hwmod, */ 5515/* &omap44xx_iss_hwmod, */
5609 5516
5610 /* iva class */ 5517 /* iva class */
5611 &omap44xx_iva_hwmod, 5518 &omap44xx_iva_hwmod,
5612 &omap44xx_iva_seq0_hwmod,
5613 &omap44xx_iva_seq1_hwmod,
5614 5519
5615 /* kbd class */ 5520 /* kbd class */
5616 &omap44xx_kbd_hwmod, 5521 &omap44xx_kbd_hwmod,