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-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c79
1 files changed, 59 insertions, 20 deletions
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 2767ea8e98a7..debf745c0268 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -38,21 +38,21 @@
38/* Transmit operation: */ 38/* Transmit operation: */
39/* */ 39/* */
40/* 0 byte transmit */ 40/* 0 byte transmit */
41/* BUS: S A8 ACK P */ 41/* BUS: S A8 ACK P(*) */
42/* IRQ: DTE WAIT */ 42/* IRQ: DTE WAIT */
43/* ICIC: */ 43/* ICIC: */
44/* ICCR: 0x94 0x90 */ 44/* ICCR: 0x94 0x90 */
45/* ICDR: A8 */ 45/* ICDR: A8 */
46/* */ 46/* */
47/* 1 byte transmit */ 47/* 1 byte transmit */
48/* BUS: S A8 ACK D8(1) ACK P */ 48/* BUS: S A8 ACK D8(1) ACK P(*) */
49/* IRQ: DTE WAIT WAIT */ 49/* IRQ: DTE WAIT WAIT */
50/* ICIC: -DTE */ 50/* ICIC: -DTE */
51/* ICCR: 0x94 0x90 */ 51/* ICCR: 0x94 0x90 */
52/* ICDR: A8 D8(1) */ 52/* ICDR: A8 D8(1) */
53/* */ 53/* */
54/* 2 byte transmit */ 54/* 2 byte transmit */
55/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */ 55/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
56/* IRQ: DTE WAIT WAIT WAIT */ 56/* IRQ: DTE WAIT WAIT WAIT */
57/* ICIC: -DTE */ 57/* ICIC: -DTE */
58/* ICCR: 0x94 0x90 */ 58/* ICCR: 0x94 0x90 */
@@ -66,20 +66,20 @@
66/* 0 byte receive - not supported since slave may hold SDA low */ 66/* 0 byte receive - not supported since slave may hold SDA low */
67/* */ 67/* */
68/* 1 byte receive [TX] | [RX] */ 68/* 1 byte receive [TX] | [RX] */
69/* BUS: S A8 ACK | D8(1) ACK P */ 69/* BUS: S A8 ACK | D8(1) ACK P(*) */
70/* IRQ: DTE WAIT | WAIT DTE */ 70/* IRQ: DTE WAIT | WAIT DTE */
71/* ICIC: -DTE | +DTE */ 71/* ICIC: -DTE | +DTE */
72/* ICCR: 0x94 0x81 | 0xc0 */ 72/* ICCR: 0x94 0x81 | 0xc0 */
73/* ICDR: A8 | D8(1) */ 73/* ICDR: A8 | D8(1) */
74/* */ 74/* */
75/* 2 byte receive [TX]| [RX] */ 75/* 2 byte receive [TX]| [RX] */
76/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */ 76/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
77/* IRQ: DTE WAIT | WAIT WAIT DTE */ 77/* IRQ: DTE WAIT | WAIT WAIT DTE */
78/* ICIC: -DTE | +DTE */ 78/* ICIC: -DTE | +DTE */
79/* ICCR: 0x94 0x81 | 0xc0 */ 79/* ICCR: 0x94 0x81 | 0xc0 */
80/* ICDR: A8 | D8(1) D8(2) */ 80/* ICDR: A8 | D8(1) D8(2) */
81/* */ 81/* */
82/* 3 byte receive [TX] | [RX] */ 82/* 3 byte receive [TX] | [RX] (*) */
83/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 83/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 84/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85/* ICIC: -DTE | +DTE */ 85/* ICIC: -DTE | +DTE */
@@ -94,7 +94,7 @@
94/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 94/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 95/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
96/* */ 96/* */
97/* S D7 D6 D5 D4 D3 D2 D1 D0 P */ 97/* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
98/* ___ */ 98/* ___ */
99/* WAIT IRQ ________________________________/ \___________ */ 99/* WAIT IRQ ________________________________/ \___________ */
100/* TACK IRQ ____________________________________/ \_______ */ 100/* TACK IRQ ____________________________________/ \_______ */
@@ -103,6 +103,11 @@
103/* _______________________________________________ */ 103/* _______________________________________________ */
104/* BUSY __/ \_ */ 104/* BUSY __/ \_ */
105/* */ 105/* */
106/* (*) The STOP condition is only sent by the master at the end of the last */
107/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108/* only cleared after the STOP condition, so, between messages we have to */
109/* poll for the DTE bit. */
110/* */
106 111
107enum sh_mobile_i2c_op { 112enum sh_mobile_i2c_op {
108 OP_START = 0, 113 OP_START = 0,
@@ -132,6 +137,7 @@ struct sh_mobile_i2c_data {
132 struct i2c_msg *msg; 137 struct i2c_msg *msg;
133 int pos; 138 int pos;
134 int sr; 139 int sr;
140 bool send_stop;
135}; 141};
136 142
137#define IIC_FLAG_HAS_ICIC67 (1 << 0) 143#define IIC_FLAG_HAS_ICIC67 (1 << 0)
@@ -322,7 +328,7 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
322 break; 328 break;
323 case OP_TX_STOP: /* write data and issue a stop afterwards */ 329 case OP_TX_STOP: /* write data and issue a stop afterwards */
324 iic_wr(pd, ICDR, data); 330 iic_wr(pd, ICDR, data);
325 iic_wr(pd, ICCR, 0x90); 331 iic_wr(pd, ICCR, pd->send_stop ? 0x90 : 0x94);
326 break; 332 break;
327 case OP_TX_TO_RX: /* select read mode */ 333 case OP_TX_TO_RX: /* select read mode */
328 iic_wr(pd, ICCR, 0x81); 334 iic_wr(pd, ICCR, 0x81);
@@ -469,22 +475,25 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
469 return IRQ_HANDLED; 475 return IRQ_HANDLED;
470} 476}
471 477
472static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg) 478static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
479 bool do_init)
473{ 480{
474 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 481 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
475 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 482 dev_err(pd->dev, "Unsupported zero length i2c read\n");
476 return -EIO; 483 return -EIO;
477 } 484 }
478 485
479 /* Initialize channel registers */ 486 if (do_init) {
480 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 487 /* Initialize channel registers */
488 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
481 489
482 /* Enable channel and configure rx ack */ 490 /* Enable channel and configure rx ack */
483 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 491 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
484 492
485 /* Set the clock */ 493 /* Set the clock */
486 iic_wr(pd, ICCL, pd->iccl & 0xff); 494 iic_wr(pd, ICCL, pd->iccl & 0xff);
487 iic_wr(pd, ICCH, pd->icch & 0xff); 495 iic_wr(pd, ICCH, pd->icch & 0xff);
496 }
488 497
489 pd->msg = usr_msg; 498 pd->msg = usr_msg;
490 pd->pos = -1; 499 pd->pos = -1;
@@ -495,6 +504,30 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
495 return 0; 504 return 0;
496} 505}
497 506
507static int poll_dte(struct sh_mobile_i2c_data *pd)
508{
509 int i;
510
511 for (i = 1000; i; i--) {
512 u_int8_t val = iic_rd(pd, ICSR);
513
514 if (val & ICSR_DTE)
515 break;
516
517 if (val & ICSR_TACK)
518 return -EIO;
519
520 udelay(10);
521 }
522
523 if (!i) {
524 dev_warn(pd->dev, "Timeout polling for DTE!\n");
525 return -ETIMEDOUT;
526 }
527
528 return 0;
529}
530
498static int poll_busy(struct sh_mobile_i2c_data *pd) 531static int poll_busy(struct sh_mobile_i2c_data *pd)
499{ 532{
500 int i; 533 int i;
@@ -539,13 +572,16 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
539 572
540 /* Process all messages */ 573 /* Process all messages */
541 for (i = 0; i < num; i++) { 574 for (i = 0; i < num; i++) {
575 bool do_start = pd->send_stop || !i;
542 msg = &msgs[i]; 576 msg = &msgs[i];
577 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
543 578
544 err = start_ch(pd, msg); 579 err = start_ch(pd, msg, do_start);
545 if (err) 580 if (err)
546 break; 581 break;
547 582
548 i2c_op(pd, OP_START, 0); 583 if (do_start)
584 i2c_op(pd, OP_START, 0);
549 585
550 /* The interrupt handler takes care of the rest... */ 586 /* The interrupt handler takes care of the rest... */
551 k = wait_event_timeout(pd->wait, 587 k = wait_event_timeout(pd->wait,
@@ -557,7 +593,10 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
557 break; 593 break;
558 } 594 }
559 595
560 err = poll_busy(pd); 596 if (pd->send_stop)
597 err = poll_busy(pd);
598 else
599 err = poll_dte(pd);
561 if (err < 0) 600 if (err < 0)
562 break; 601 break;
563 } 602 }
@@ -571,7 +610,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
571 610
572static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 611static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
573{ 612{
574 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 613 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
575} 614}
576 615
577static struct i2c_algorithm sh_mobile_i2c_algorithm = { 616static struct i2c_algorithm sh_mobile_i2c_algorithm = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 11:33:05 -0500