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-rw-r--r--drivers/mfd/Kconfig10
-rw-r--r--drivers/mfd/Makefile1
-rw-r--r--drivers/mfd/db5500-prcmu.c451
-rw-r--r--include/linux/mfd/db5500-prcmu.h105
-rw-r--r--include/linux/mfd/dbx500-prcmu.h242
5 files changed, 43 insertions, 766 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 11e44386fa9b..fcda9b6a9b28 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -711,16 +711,6 @@ config MFD_DB8500_PRCMU
711 system controller running an XP70 microprocessor, which is accessed 711 system controller running an XP70 microprocessor, which is accessed
712 through a register map. 712 through a register map.
713 713
714config MFD_DB5500_PRCMU
715 bool "ST-Ericsson DB5500 Power Reset Control Management Unit"
716 depends on UX500_SOC_DB5500
717 select MFD_CORE
718 help
719 Select this option to enable support for the DB5500 Power Reset
720 and Control Management Unit. This is basically an autonomous
721 system controller running an XP70 microprocessor, which is accessed
722 through a register map.
723
724config MFD_CS5535 714config MFD_CS5535
725 tristate "Support for CS5535 and CS5536 southbridge core functions" 715 tristate "Support for CS5535 and CS5536 southbridge core functions"
726 select MFD_CORE 716 select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 05fa538c5efe..2f53081216a8 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -95,7 +95,6 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o
95obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o 95obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o
96# ab8500-i2c need to come after db8500-prcmu (which provides the channel) 96# ab8500-i2c need to come after db8500-prcmu (which provides the channel)
97obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o 97obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o
98obj-$(CONFIG_MFD_DB5500_PRCMU) += db5500-prcmu.o
99obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o 98obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
100obj-$(CONFIG_PMIC_ADP5520) += adp5520.o 99obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
101obj-$(CONFIG_LPC_SCH) += lpc_sch.o 100obj-$(CONFIG_LPC_SCH) += lpc_sch.o
diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c
deleted file mode 100644
index bb115b2f04e9..000000000000
--- a/drivers/mfd/db5500-prcmu.c
+++ /dev/null
@@ -1,451 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
6 *
7 * U5500 PRCM Unit interface driver
8 */
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/mutex.h>
18#include <linux/completion.h>
19#include <linux/irq.h>
20#include <linux/jiffies.h>
21#include <linux/bitops.h>
22#include <linux/interrupt.h>
23#include <linux/mfd/dbx500-prcmu.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <mach/db5500-regs.h>
27#include "dbx500-prcmu-regs.h"
28
29#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
30#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
31#define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
32#define PRCM_REQ_MB2_HEADER (_PRCM_MB_HEADER + 0x2)
33#define PRCM_REQ_MB3_HEADER (_PRCM_MB_HEADER + 0x3)
34#define PRCM_REQ_MB4_HEADER (_PRCM_MB_HEADER + 0x4)
35#define PRCM_REQ_MB5_HEADER (_PRCM_MB_HEADER + 0x5)
36#define PRCM_REQ_MB6_HEADER (_PRCM_MB_HEADER + 0x6)
37#define PRCM_REQ_MB7_HEADER (_PRCM_MB_HEADER + 0x7)
38#define PRCM_ACK_MB0_HEADER (_PRCM_MB_HEADER + 0x8)
39#define PRCM_ACK_MB1_HEADER (_PRCM_MB_HEADER + 0x9)
40#define PRCM_ACK_MB2_HEADER (_PRCM_MB_HEADER + 0xa)
41#define PRCM_ACK_MB3_HEADER (_PRCM_MB_HEADER + 0xb)
42#define PRCM_ACK_MB4_HEADER (_PRCM_MB_HEADER + 0xc)
43#define PRCM_ACK_MB5_HEADER (_PRCM_MB_HEADER + 0xd)
44#define PRCM_ACK_MB6_HEADER (_PRCM_MB_HEADER + 0xe)
45#define PRCM_ACK_MB7_HEADER (_PRCM_MB_HEADER + 0xf)
46
47/* Req Mailboxes */
48#define PRCM_REQ_MB0 (tcdm_base + 0xFD8)
49#define PRCM_REQ_MB1 (tcdm_base + 0xFCC)
50#define PRCM_REQ_MB2 (tcdm_base + 0xFC4)
51#define PRCM_REQ_MB3 (tcdm_base + 0xFC0)
52#define PRCM_REQ_MB4 (tcdm_base + 0xF98)
53#define PRCM_REQ_MB5 (tcdm_base + 0xF90)
54#define PRCM_REQ_MB6 (tcdm_base + 0xF8C)
55#define PRCM_REQ_MB7 (tcdm_base + 0xF84)
56
57/* Ack Mailboxes */
58#define PRCM_ACK_MB0 (tcdm_base + 0xF38)
59#define PRCM_ACK_MB1 (tcdm_base + 0xF30)
60#define PRCM_ACK_MB2 (tcdm_base + 0xF24)
61#define PRCM_ACK_MB3 (tcdm_base + 0xF20)
62#define PRCM_ACK_MB4 (tcdm_base + 0xF1C)
63#define PRCM_ACK_MB5 (tcdm_base + 0xF14)
64#define PRCM_ACK_MB6 (tcdm_base + 0xF0C)
65#define PRCM_ACK_MB7 (tcdm_base + 0xF08)
66
67enum mb_return_code {
68 RC_SUCCESS,
69 RC_FAIL,
70};
71
72/* Mailbox 0 headers. */
73enum mb0_header {
74 /* request */
75 RMB0H_PWR_STATE_TRANS = 1,
76 RMB0H_WAKE_UP_CFG,
77 RMB0H_RD_WAKE_UP_ACK,
78 /* acknowledge */
79 AMB0H_WAKE_UP = 1,
80};
81
82/* Mailbox 5 headers. */
83enum mb5_header {
84 MB5H_I2C_WRITE = 1,
85 MB5H_I2C_READ,
86};
87
88/* Request mailbox 5 fields. */
89#define PRCM_REQ_MB5_I2C_SLAVE (PRCM_REQ_MB5 + 0)
90#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 1)
91#define PRCM_REQ_MB5_I2C_SIZE (PRCM_REQ_MB5 + 2)
92#define PRCM_REQ_MB5_I2C_DATA (PRCM_REQ_MB5 + 4)
93
94/* Acknowledge mailbox 5 fields. */
95#define PRCM_ACK_MB5_RETURN_CODE (PRCM_ACK_MB5 + 0)
96#define PRCM_ACK_MB5_I2C_DATA (PRCM_ACK_MB5 + 4)
97
98#define NUM_MB 8
99#define MBOX_BIT BIT
100#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
101
102/*
103* Used by MCDE to setup all necessary PRCMU registers
104*/
105#define PRCMU_RESET_DSIPLL 0x00004000
106#define PRCMU_UNCLAMP_DSIPLL 0x00400800
107
108/* HDMI CLK MGT PLLSW=001 (PLLSOC0), PLLDIV=0x8, = 50 Mhz*/
109#define PRCMU_DSI_CLOCK_SETTING 0x00000128
110/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
111#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
112#define PRCMU_PLLDSI_FREQ_SETTING 0x00020121
113#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
114#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000201
115#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
116
117#define PRCMU_ENABLE_PLLDSI 0x00000001
118#define PRCMU_DISABLE_PLLDSI 0x00000000
119
120#define PRCMU_DSI_RESET_SW 0x00000003
121#define PRCMU_RESOUTN0_PIN 0x00000001
122#define PRCMU_RESOUTN1_PIN 0x00000002
123#define PRCMU_RESOUTN2_PIN 0x00000004
124
125#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
126
127/*
128 * mb0_transfer - state needed for mailbox 0 communication.
129 * @lock: The transaction lock.
130 */
131static struct {
132 spinlock_t lock;
133} mb0_transfer;
134
135/*
136 * mb5_transfer - state needed for mailbox 5 communication.
137 * @lock: The transaction lock.
138 * @work: The transaction completion structure.
139 * @ack: Reply ("acknowledge") data.
140 */
141static struct {
142 struct mutex lock;
143 struct completion work;
144 struct {
145 u8 header;
146 u8 status;
147 u8 value[4];
148 } ack;
149} mb5_transfer;
150
151/* PRCMU TCDM base IO address. */
152static __iomem void *tcdm_base;
153
154/**
155 * db5500_prcmu_abb_read() - Read register value(s) from the ABB.
156 * @slave: The I2C slave address.
157 * @reg: The (start) register address.
158 * @value: The read out value(s).
159 * @size: The number of registers to read.
160 *
161 * Reads register value(s) from the ABB.
162 * @size has to be <= 4.
163 */
164int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
165{
166 int r;
167
168 if ((size < 1) || (4 < size))
169 return -EINVAL;
170
171 mutex_lock(&mb5_transfer.lock);
172
173 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
174 cpu_relax();
175 writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
176 writeb(reg, PRCM_REQ_MB5_I2C_REG);
177 writeb(size, PRCM_REQ_MB5_I2C_SIZE);
178 writeb(MB5H_I2C_READ, PRCM_REQ_MB5_HEADER);
179
180 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
181 wait_for_completion(&mb5_transfer.work);
182
183 r = 0;
184 if ((mb5_transfer.ack.header == MB5H_I2C_READ) &&
185 (mb5_transfer.ack.status == RC_SUCCESS))
186 memcpy(value, mb5_transfer.ack.value, (size_t)size);
187 else
188 r = -EIO;
189
190 mutex_unlock(&mb5_transfer.lock);
191
192 return r;
193}
194
195/**
196 * db5500_prcmu_abb_write() - Write register value(s) to the ABB.
197 * @slave: The I2C slave address.
198 * @reg: The (start) register address.
199 * @value: The value(s) to write.
200 * @size: The number of registers to write.
201 *
202 * Writes register value(s) to the ABB.
203 * @size has to be <= 4.
204 */
205int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
206{
207 int r;
208
209 if ((size < 1) || (4 < size))
210 return -EINVAL;
211
212 mutex_lock(&mb5_transfer.lock);
213
214 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
215 cpu_relax();
216 writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
217 writeb(reg, PRCM_REQ_MB5_I2C_REG);
218 writeb(size, PRCM_REQ_MB5_I2C_SIZE);
219 memcpy_toio(PRCM_REQ_MB5_I2C_DATA, value, size);
220 writeb(MB5H_I2C_WRITE, PRCM_REQ_MB5_HEADER);
221
222 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
223 wait_for_completion(&mb5_transfer.work);
224
225 if ((mb5_transfer.ack.header == MB5H_I2C_WRITE) &&
226 (mb5_transfer.ack.status == RC_SUCCESS))
227 r = 0;
228 else
229 r = -EIO;
230
231 mutex_unlock(&mb5_transfer.lock);
232
233 return r;
234}
235
236int db5500_prcmu_enable_dsipll(void)
237{
238 int i;
239
240 /* Enable DSIPLL_RESETN resets */
241 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
242 /* Unclamp DSIPLL in/out */
243 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
244 /* Set DSI PLL FREQ */
245 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
246 writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
247 PRCM_DSI_PLLOUT_SEL);
248 /* Enable Escape clocks */
249 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
250
251 /* Start DSI PLL */
252 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
253 /* Reset DSI PLL */
254 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
255 for (i = 0; i < 10; i++) {
256 if ((readl(PRCM_PLLDSI_LOCKP) &
257 PRCMU_PLLDSI_LOCKP_LOCKED) == PRCMU_PLLDSI_LOCKP_LOCKED)
258 break;
259 udelay(100);
260 }
261 /* Release DSIPLL_RESETN */
262 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
263 return 0;
264}
265
266int db5500_prcmu_disable_dsipll(void)
267{
268 /* Disable dsi pll */
269 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
270 /* Disable escapeclock */
271 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
272 return 0;
273}
274
275int db5500_prcmu_set_display_clocks(void)
276{
277 /* HDMI and TVCLK Should be handled somewhere else */
278 /* PLLDIV=8, PLLSW=2, CLKEN=1 */
279 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
280 /* PLLDIV=14, PLLSW=2, CLKEN=1 */
281 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
282 return 0;
283}
284
285static void ack_dbb_wakeup(void)
286{
287 unsigned long flags;
288
289 spin_lock_irqsave(&mb0_transfer.lock, flags);
290
291 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
292 cpu_relax();
293
294 writeb(RMB0H_RD_WAKE_UP_ACK, PRCM_REQ_MB0_HEADER);
295 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
296
297 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
298}
299
300static inline void print_unknown_header_warning(u8 n, u8 header)
301{
302 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
303 header, n);
304}
305
306static bool read_mailbox_0(void)
307{
308 bool r;
309 u8 header;
310
311 header = readb(PRCM_ACK_MB0_HEADER);
312 switch (header) {
313 case AMB0H_WAKE_UP:
314 r = true;
315 break;
316 default:
317 print_unknown_header_warning(0, header);
318 r = false;
319 break;
320 }
321 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
322 return r;
323}
324
325static bool read_mailbox_1(void)
326{
327 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
328 return false;
329}
330
331static bool read_mailbox_2(void)
332{
333 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
334 return false;
335}
336
337static bool read_mailbox_3(void)
338{
339 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
340 return false;
341}
342
343static bool read_mailbox_4(void)
344{
345 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
346 return false;
347}
348
349static bool read_mailbox_5(void)
350{
351 u8 header;
352
353 header = readb(PRCM_ACK_MB5_HEADER);
354 switch (header) {
355 case MB5H_I2C_READ:
356 memcpy_fromio(mb5_transfer.ack.value, PRCM_ACK_MB5_I2C_DATA, 4);
357 case MB5H_I2C_WRITE:
358 mb5_transfer.ack.header = header;
359 mb5_transfer.ack.status = readb(PRCM_ACK_MB5_RETURN_CODE);
360 complete(&mb5_transfer.work);
361 break;
362 default:
363 print_unknown_header_warning(5, header);
364 break;
365 }
366 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
367 return false;
368}
369
370static bool read_mailbox_6(void)
371{
372 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
373 return false;
374}
375
376static bool read_mailbox_7(void)
377{
378 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
379 return false;
380}
381
382static bool (* const read_mailbox[NUM_MB])(void) = {
383 read_mailbox_0,
384 read_mailbox_1,
385 read_mailbox_2,
386 read_mailbox_3,
387 read_mailbox_4,
388 read_mailbox_5,
389 read_mailbox_6,
390 read_mailbox_7
391};
392
393static irqreturn_t prcmu_irq_handler(int irq, void *data)
394{
395 u32 bits;
396 u8 n;
397 irqreturn_t r;
398
399 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
400 if (unlikely(!bits))
401 return IRQ_NONE;
402
403 r = IRQ_HANDLED;
404 for (n = 0; bits; n++) {
405 if (bits & MBOX_BIT(n)) {
406 bits -= MBOX_BIT(n);
407 if (read_mailbox[n]())
408 r = IRQ_WAKE_THREAD;
409 }
410 }
411 return r;
412}
413
414static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
415{
416 ack_dbb_wakeup();
417 return IRQ_HANDLED;
418}
419
420void __init db5500_prcmu_early_init(void)
421{
422 tcdm_base = __io_address(U5500_PRCMU_TCDM_BASE);
423 spin_lock_init(&mb0_transfer.lock);
424 mutex_init(&mb5_transfer.lock);
425 init_completion(&mb5_transfer.work);
426}
427
428/**
429 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
430 *
431 */
432int __init db5500_prcmu_init(void)
433{
434 int r = 0;
435
436 if (ux500_is_svp() || !cpu_is_u5500())
437 return -ENODEV;
438
439 /* Clean up the mailbox interrupts after pre-kernel code. */
440 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
441
442 r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
443 prcmu_irq_thread_fn, 0, "prcmu", NULL);
444 if (r < 0) {
445 pr_err("prcmu: Failed to allocate IRQ_DB5500_PRCMU1.\n");
446 return -EBUSY;
447 }
448 return 0;
449}
450
451arch_initcall(db5500_prcmu_init);
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
deleted file mode 100644
index 5a049dfaf153..000000000000
--- a/include/linux/mfd/db5500-prcmu.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * U5500 PRCMU API.
7 */
8#ifndef __MFD_DB5500_PRCMU_H
9#define __MFD_DB5500_PRCMU_H
10
11static inline int prcmu_resetout(u8 resoutn, u8 state)
12{
13 return 0;
14}
15
16static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
17{
18 return 0;
19}
20
21static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
22{
23 return 0;
24}
25
26static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
27 bool keep_ap_pll)
28{
29 return 0;
30}
31
32static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
33{
34 return 0;
35}
36
37static inline u16 db5500_prcmu_get_reset_code(void)
38{
39 return 0;
40}
41
42static inline bool db5500_prcmu_is_ac_wake_requested(void)
43{
44 return 0;
45}
46
47static inline int db5500_prcmu_set_arm_opp(u8 opp)
48{
49 return 0;
50}
51
52static inline int db5500_prcmu_get_arm_opp(void)
53{
54 return 0;
55}
56
57static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
58
59static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
60
61static inline void db5500_prcmu_system_reset(u16 reset_code) {}
62
63static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
64
65#ifdef CONFIG_MFD_DB5500_PRCMU
66
67void db5500_prcmu_early_init(void);
68int db5500_prcmu_set_display_clocks(void);
69int db5500_prcmu_disable_dsipll(void);
70int db5500_prcmu_enable_dsipll(void);
71int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
72int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
73
74#else /* !CONFIG_UX500_SOC_DB5500 */
75
76static inline void db5500_prcmu_early_init(void) {}
77
78static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
79{
80 return -ENOSYS;
81}
82
83static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
84{
85 return -ENOSYS;
86}
87
88static inline int db5500_prcmu_set_display_clocks(void)
89{
90 return 0;
91}
92
93static inline int db5500_prcmu_disable_dsipll(void)
94{
95 return 0;
96}
97
98static inline int db5500_prcmu_enable_dsipll(void)
99{
100 return 0;
101}
102
103#endif /* CONFIG_MFD_DB5500_PRCMU */
104
105#endif /* __MFD_DB5500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index d7674eb7305f..5a13f93d8f1c 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -55,17 +55,6 @@ enum prcmu_wakeup_index {
55#define NUM_EPOD_ID 8 55#define NUM_EPOD_ID 8
56 56
57/* 57/*
58 * DB5500 EPODs
59 */
60#define DB5500_EPOD_ID_BASE 0x0100
61#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66#define DB5500_NUM_EPOD_ID 7
67
68/*
69 * state definition for EPOD (power domain) 58 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 59 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off 60 * - EPOD_STATE_OFF: The EPOD is switched off
@@ -80,29 +69,6 @@ enum prcmu_wakeup_index {
80#define EPOD_STATE_ON_CLK_OFF 0x03 69#define EPOD_STATE_ON_CLK_OFF 0x03
81#define EPOD_STATE_ON 0x04 70#define EPOD_STATE_ON 0x04
82 71
83/* DB5500 CLKOUT IDs */
84enum {
85 DB5500_CLKOUT0 = 0,
86 DB5500_CLKOUT1,
87};
88
89/* DB5500 CLKOUTx sources */
90enum {
91 DB5500_CLKOUT_REF_CLK_SEL0,
92 DB5500_CLKOUT_RTC_CLK0_SEL0,
93 DB5500_CLKOUT_ULP_CLK_SEL0,
94 DB5500_CLKOUT_STATIC0,
95 DB5500_CLKOUT_REFCLK,
96 DB5500_CLKOUT_ULPCLK,
97 DB5500_CLKOUT_ARMCLK,
98 DB5500_CLKOUT_SYSACC0CLK,
99 DB5500_CLKOUT_SOC0PLLCLK,
100 DB5500_CLKOUT_SOC1PLLCLK,
101 DB5500_CLKOUT_DDRPLLCLK,
102 DB5500_CLKOUT_TVCLK,
103 DB5500_CLKOUT_IRDACLK,
104};
105
106/* 72/*
107 * CLKOUT sources 73 * CLKOUT sources
108 */ 74 */
@@ -248,101 +214,66 @@ enum ddr_pwrst {
248}; 214};
249 215
250#include <linux/mfd/db8500-prcmu.h> 216#include <linux/mfd/db8500-prcmu.h>
251#include <linux/mfd/db5500-prcmu.h>
252 217
253#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 218#if defined(CONFIG_UX500_SOC_DB8500)
254 219
255#include <mach/id.h> 220#include <mach/id.h>
256 221
257static inline void __init prcmu_early_init(void) 222static inline void __init prcmu_early_init(void)
258{ 223{
259 if (cpu_is_u5500()) 224 return db8500_prcmu_early_init();
260 return db5500_prcmu_early_init();
261 else
262 return db8500_prcmu_early_init();
263} 225}
264 226
265static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 227static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
266 bool keep_ap_pll) 228 bool keep_ap_pll)
267{ 229{
268 if (cpu_is_u5500()) 230 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
269 return db5500_prcmu_set_power_state(state, keep_ulp_clk, 231 keep_ap_pll);
270 keep_ap_pll);
271 else
272 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
273 keep_ap_pll);
274} 232}
275 233
276static inline u8 prcmu_get_power_state_result(void) 234static inline u8 prcmu_get_power_state_result(void)
277{ 235{
278 if (cpu_is_u5500()) 236 return db8500_prcmu_get_power_state_result();
279 return -EINVAL;
280 else
281 return db8500_prcmu_get_power_state_result();
282} 237}
283 238
284static inline int prcmu_gic_decouple(void) 239static inline int prcmu_gic_decouple(void)
285{ 240{
286 if (cpu_is_u5500()) 241 return db8500_prcmu_gic_decouple();
287 return -EINVAL;
288 else
289 return db8500_prcmu_gic_decouple();
290} 242}
291 243
292static inline int prcmu_gic_recouple(void) 244static inline int prcmu_gic_recouple(void)
293{ 245{
294 if (cpu_is_u5500()) 246 return db8500_prcmu_gic_recouple();
295 return -EINVAL;
296 else
297 return db8500_prcmu_gic_recouple();
298} 247}
299 248
300static inline bool prcmu_gic_pending_irq(void) 249static inline bool prcmu_gic_pending_irq(void)
301{ 250{
302 if (cpu_is_u5500()) 251 return db8500_prcmu_gic_pending_irq();
303 return -EINVAL;
304 else
305 return db8500_prcmu_gic_pending_irq();
306} 252}
307 253
308static inline bool prcmu_is_cpu_in_wfi(int cpu) 254static inline bool prcmu_is_cpu_in_wfi(int cpu)
309{ 255{
310 if (cpu_is_u5500()) 256 return db8500_prcmu_is_cpu_in_wfi(cpu);
311 return -EINVAL;
312 else
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
314} 257}
315 258
316static inline int prcmu_copy_gic_settings(void) 259static inline int prcmu_copy_gic_settings(void)
317{ 260{
318 if (cpu_is_u5500()) 261 return db8500_prcmu_copy_gic_settings();
319 return -EINVAL;
320 else
321 return db8500_prcmu_copy_gic_settings();
322} 262}
323 263
324static inline bool prcmu_pending_irq(void) 264static inline bool prcmu_pending_irq(void)
325{ 265{
326 if (cpu_is_u5500()) 266 return db8500_prcmu_pending_irq();
327 return -EINVAL;
328 else
329 return db8500_prcmu_pending_irq();
330} 267}
331 268
332static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 269static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
333{ 270{
334 if (cpu_is_u5500()) 271 return db8500_prcmu_set_epod(epod_id, epod_state);
335 return -EINVAL;
336 else
337 return db8500_prcmu_set_epod(epod_id, epod_state);
338} 272}
339 273
340static inline void prcmu_enable_wakeups(u32 wakeups) 274static inline void prcmu_enable_wakeups(u32 wakeups)
341{ 275{
342 if (cpu_is_u5500()) 276 db8500_prcmu_enable_wakeups(wakeups);
343 db5500_prcmu_enable_wakeups(wakeups);
344 else
345 db8500_prcmu_enable_wakeups(wakeups);
346} 277}
347 278
348static inline void prcmu_disable_wakeups(void) 279static inline void prcmu_disable_wakeups(void)
@@ -352,18 +283,12 @@ static inline void prcmu_disable_wakeups(void)
352 283
353static inline void prcmu_config_abb_event_readout(u32 abb_events) 284static inline void prcmu_config_abb_event_readout(u32 abb_events)
354{ 285{
355 if (cpu_is_u5500()) 286 db8500_prcmu_config_abb_event_readout(abb_events);
356 db5500_prcmu_config_abb_event_readout(abb_events);
357 else
358 db8500_prcmu_config_abb_event_readout(abb_events);
359} 287}
360 288
361static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 289static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
362{ 290{
363 if (cpu_is_u5500()) 291 db8500_prcmu_get_abb_event_buffer(buf);
364 db5500_prcmu_get_abb_event_buffer(buf);
365 else
366 db8500_prcmu_get_abb_event_buffer(buf);
367} 292}
368 293
369int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 294int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
@@ -374,10 +299,7 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
374 299
375static inline int prcmu_request_clock(u8 clock, bool enable) 300static inline int prcmu_request_clock(u8 clock, bool enable)
376{ 301{
377 if (cpu_is_u5500()) 302 return db8500_prcmu_request_clock(clock, enable);
378 return db5500_prcmu_request_clock(clock, enable);
379 else
380 return db8500_prcmu_request_clock(clock, enable);
381} 303}
382 304
383unsigned long prcmu_clock_rate(u8 clock); 305unsigned long prcmu_clock_rate(u8 clock);
@@ -386,211 +308,133 @@ int prcmu_set_clock_rate(u8 clock, unsigned long rate);
386 308
387static inline int prcmu_set_ddr_opp(u8 opp) 309static inline int prcmu_set_ddr_opp(u8 opp)
388{ 310{
389 if (cpu_is_u5500()) 311 return db8500_prcmu_set_ddr_opp(opp);
390 return -EINVAL;
391 else
392 return db8500_prcmu_set_ddr_opp(opp);
393} 312}
394static inline int prcmu_get_ddr_opp(void) 313static inline int prcmu_get_ddr_opp(void)
395{ 314{
396 if (cpu_is_u5500()) 315 return db8500_prcmu_get_ddr_opp();
397 return -EINVAL;
398 else
399 return db8500_prcmu_get_ddr_opp();
400} 316}
401 317
402static inline int prcmu_set_arm_opp(u8 opp) 318static inline int prcmu_set_arm_opp(u8 opp)
403{ 319{
404 if (cpu_is_u5500()) 320 return db8500_prcmu_set_arm_opp(opp);
405 return -EINVAL;
406 else
407 return db8500_prcmu_set_arm_opp(opp);
408} 321}
409 322
410static inline int prcmu_get_arm_opp(void) 323static inline int prcmu_get_arm_opp(void)
411{ 324{
412 if (cpu_is_u5500()) 325 return db8500_prcmu_get_arm_opp();
413 return -EINVAL;
414 else
415 return db8500_prcmu_get_arm_opp();
416} 326}
417 327
418static inline int prcmu_set_ape_opp(u8 opp) 328static inline int prcmu_set_ape_opp(u8 opp)
419{ 329{
420 if (cpu_is_u5500()) 330 return db8500_prcmu_set_ape_opp(opp);
421 return -EINVAL;
422 else
423 return db8500_prcmu_set_ape_opp(opp);
424} 331}
425 332
426static inline int prcmu_get_ape_opp(void) 333static inline int prcmu_get_ape_opp(void)
427{ 334{
428 if (cpu_is_u5500()) 335 return db8500_prcmu_get_ape_opp();
429 return -EINVAL;
430 else
431 return db8500_prcmu_get_ape_opp();
432} 336}
433 337
434static inline void prcmu_system_reset(u16 reset_code) 338static inline void prcmu_system_reset(u16 reset_code)
435{ 339{
436 if (cpu_is_u5500()) 340 return db8500_prcmu_system_reset(reset_code);
437 return db5500_prcmu_system_reset(reset_code);
438 else
439 return db8500_prcmu_system_reset(reset_code);
440} 341}
441 342
442static inline u16 prcmu_get_reset_code(void) 343static inline u16 prcmu_get_reset_code(void)
443{ 344{
444 if (cpu_is_u5500()) 345 return db8500_prcmu_get_reset_code();
445 return db5500_prcmu_get_reset_code();
446 else
447 return db8500_prcmu_get_reset_code();
448} 346}
449 347
450void prcmu_ac_wake_req(void); 348void prcmu_ac_wake_req(void);
451void prcmu_ac_sleep_req(void); 349void prcmu_ac_sleep_req(void);
452static inline void prcmu_modem_reset(void) 350static inline void prcmu_modem_reset(void)
453{ 351{
454 if (cpu_is_u5500()) 352 return db8500_prcmu_modem_reset();
455 return;
456 else
457 return db8500_prcmu_modem_reset();
458} 353}
459 354
460static inline bool prcmu_is_ac_wake_requested(void) 355static inline bool prcmu_is_ac_wake_requested(void)
461{ 356{
462 if (cpu_is_u5500()) 357 return db8500_prcmu_is_ac_wake_requested();
463 return db5500_prcmu_is_ac_wake_requested();
464 else
465 return db8500_prcmu_is_ac_wake_requested();
466} 358}
467 359
468static inline int prcmu_set_display_clocks(void) 360static inline int prcmu_set_display_clocks(void)
469{ 361{
470 if (cpu_is_u5500()) 362 return db8500_prcmu_set_display_clocks();
471 return db5500_prcmu_set_display_clocks();
472 else
473 return db8500_prcmu_set_display_clocks();
474} 363}
475 364
476static inline int prcmu_disable_dsipll(void) 365static inline int prcmu_disable_dsipll(void)
477{ 366{
478 if (cpu_is_u5500()) 367 return db8500_prcmu_disable_dsipll();
479 return db5500_prcmu_disable_dsipll();
480 else
481 return db8500_prcmu_disable_dsipll();
482} 368}
483 369
484static inline int prcmu_enable_dsipll(void) 370static inline int prcmu_enable_dsipll(void)
485{ 371{
486 if (cpu_is_u5500()) 372 return db8500_prcmu_enable_dsipll();
487 return db5500_prcmu_enable_dsipll();
488 else
489 return db8500_prcmu_enable_dsipll();
490} 373}
491 374
492static inline int prcmu_config_esram0_deep_sleep(u8 state) 375static inline int prcmu_config_esram0_deep_sleep(u8 state)
493{ 376{
494 if (cpu_is_u5500()) 377 return db8500_prcmu_config_esram0_deep_sleep(state);
495 return -EINVAL;
496 else
497 return db8500_prcmu_config_esram0_deep_sleep(state);
498} 378}
499 379
500static inline int prcmu_config_hotdog(u8 threshold) 380static inline int prcmu_config_hotdog(u8 threshold)
501{ 381{
502 if (cpu_is_u5500()) 382 return db8500_prcmu_config_hotdog(threshold);
503 return -EINVAL;
504 else
505 return db8500_prcmu_config_hotdog(threshold);
506} 383}
507 384
508static inline int prcmu_config_hotmon(u8 low, u8 high) 385static inline int prcmu_config_hotmon(u8 low, u8 high)
509{ 386{
510 if (cpu_is_u5500()) 387 return db8500_prcmu_config_hotmon(low, high);
511 return -EINVAL;
512 else
513 return db8500_prcmu_config_hotmon(low, high);
514} 388}
515 389
516static inline int prcmu_start_temp_sense(u16 cycles32k) 390static inline int prcmu_start_temp_sense(u16 cycles32k)
517{ 391{
518 if (cpu_is_u5500()) 392 return db8500_prcmu_start_temp_sense(cycles32k);
519 return -EINVAL;
520 else
521 return db8500_prcmu_start_temp_sense(cycles32k);
522} 393}
523 394
524static inline int prcmu_stop_temp_sense(void) 395static inline int prcmu_stop_temp_sense(void)
525{ 396{
526 if (cpu_is_u5500()) 397 return db8500_prcmu_stop_temp_sense();
527 return -EINVAL;
528 else
529 return db8500_prcmu_stop_temp_sense();
530} 398}
531 399
532static inline u32 prcmu_read(unsigned int reg) 400static inline u32 prcmu_read(unsigned int reg)
533{ 401{
534 if (cpu_is_u5500()) 402 return db8500_prcmu_read(reg);
535 return -EINVAL;
536 else
537 return db8500_prcmu_read(reg);
538} 403}
539 404
540static inline void prcmu_write(unsigned int reg, u32 value) 405static inline void prcmu_write(unsigned int reg, u32 value)
541{ 406{
542 if (cpu_is_u5500()) 407 db8500_prcmu_write(reg, value);
543 return;
544 else
545 db8500_prcmu_write(reg, value);
546} 408}
547 409
548static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 410static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
549{ 411{
550 if (cpu_is_u5500()) 412 db8500_prcmu_write_masked(reg, mask, value);
551 return;
552 else
553 db8500_prcmu_write_masked(reg, mask, value);
554} 413}
555 414
556static inline int prcmu_enable_a9wdog(u8 id) 415static inline int prcmu_enable_a9wdog(u8 id)
557{ 416{
558 if (cpu_is_u5500()) 417 return db8500_prcmu_enable_a9wdog(id);
559 return -EINVAL;
560 else
561 return db8500_prcmu_enable_a9wdog(id);
562} 418}
563 419
564static inline int prcmu_disable_a9wdog(u8 id) 420static inline int prcmu_disable_a9wdog(u8 id)
565{ 421{
566 if (cpu_is_u5500()) 422 return db8500_prcmu_disable_a9wdog(id);
567 return -EINVAL;
568 else
569 return db8500_prcmu_disable_a9wdog(id);
570} 423}
571 424
572static inline int prcmu_kick_a9wdog(u8 id) 425static inline int prcmu_kick_a9wdog(u8 id)
573{ 426{
574 if (cpu_is_u5500()) 427 return db8500_prcmu_kick_a9wdog(id);
575 return -EINVAL;
576 else
577 return db8500_prcmu_kick_a9wdog(id);
578} 428}
579 429
580static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 430static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
581{ 431{
582 if (cpu_is_u5500()) 432 return db8500_prcmu_load_a9wdog(id, timeout);
583 return -EINVAL;
584 else
585 return db8500_prcmu_load_a9wdog(id, timeout);
586} 433}
587 434
588static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 435static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
589{ 436{
590 if (cpu_is_u5500()) 437 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
591 return -EINVAL;
592 else
593 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
594} 438}
595#else 439#else
596 440
@@ -768,7 +612,7 @@ static inline void prcmu_clear(unsigned int reg, u32 bits)
768 prcmu_write_masked(reg, bits, 0); 612 prcmu_write_masked(reg, bits, 0);
769} 613}
770 614
771#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 615#if defined(CONFIG_UX500_SOC_DB8500)
772 616
773/** 617/**
774 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. 618 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 13:44:40 -0500