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-rw-r--r--include/linux/Kbuild2
-rw-r--r--include/linux/cd1400.h292
-rw-r--r--include/linux/cdk.h486
-rw-r--r--include/linux/comstats.h119
-rw-r--r--include/linux/istallion.h123
-rw-r--r--include/linux/sc26198.h533
-rw-r--r--include/linux/serial167.h157
-rw-r--r--include/linux/stallion.h147
8 files changed, 0 insertions, 1859 deletions
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 8760be30b375..0a8bcb6b9e2f 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -84,7 +84,6 @@ header-y += capability.h
84header-y += capi.h 84header-y += capi.h
85header-y += cciss_defs.h 85header-y += cciss_defs.h
86header-y += cciss_ioctl.h 86header-y += cciss_ioctl.h
87header-y += cdk.h
88header-y += cdrom.h 87header-y += cdrom.h
89header-y += cgroupstats.h 88header-y += cgroupstats.h
90header-y += chio.h 89header-y += chio.h
@@ -93,7 +92,6 @@ header-y += cn_proc.h
93header-y += coda.h 92header-y += coda.h
94header-y += coda_psdev.h 93header-y += coda_psdev.h
95header-y += coff.h 94header-y += coff.h
96header-y += comstats.h
97header-y += connector.h 95header-y += connector.h
98header-y += const.h 96header-y += const.h
99header-y += cramfs_fs.h 97header-y += cramfs_fs.h
diff --git a/include/linux/cd1400.h b/include/linux/cd1400.h
deleted file mode 100644
index 1dc3ab0523fd..000000000000
--- a/include/linux/cd1400.h
+++ /dev/null
@@ -1,292 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * cd1400.h -- cd1400 UART hardware info.
5 *
6 * Copyright (C) 1996-1998 Stallion Technologies
7 * Copyright (C) 1994-1996 Greg Ungerer.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24/*****************************************************************************/
25#ifndef _CD1400_H
26#define _CD1400_H
27/*****************************************************************************/
28
29/*
30 * Define the number of async ports per cd1400 uart chip.
31 */
32#define CD1400_PORTS 4
33
34/*
35 * Define the cd1400 uarts internal FIFO sizes.
36 */
37#define CD1400_TXFIFOSIZE 12
38#define CD1400_RXFIFOSIZE 12
39
40/*
41 * Local RX FIFO thresh hold level. Also define the RTS thresh hold
42 * based on the RX thresh hold.
43 */
44#define FIFO_RXTHRESHOLD 6
45#define FIFO_RTSTHRESHOLD 7
46
47/*****************************************************************************/
48
49/*
50 * Define the cd1400 register addresses. These are all the valid
51 * registers with the cd1400. Some are global, some virtual, some
52 * per port.
53 */
54#define GFRCR 0x40
55#define CAR 0x68
56#define GCR 0x4b
57#define SVRR 0x67
58#define RICR 0x44
59#define TICR 0x45
60#define MICR 0x46
61#define RIR 0x6b
62#define TIR 0x6a
63#define MIR 0x69
64#define PPR 0x7e
65
66#define RIVR 0x43
67#define TIVR 0x42
68#define MIVR 0x41
69#define TDR 0x63
70#define RDSR 0x62
71#define MISR 0x4c
72#define EOSRR 0x60
73
74#define LIVR 0x18
75#define CCR 0x05
76#define SRER 0x06
77#define COR1 0x08
78#define COR2 0x09
79#define COR3 0x0a
80#define COR4 0x1e
81#define COR5 0x1f
82#define CCSR 0x0b
83#define RDCR 0x0e
84#define SCHR1 0x1a
85#define SCHR2 0x1b
86#define SCHR3 0x1c
87#define SCHR4 0x1d
88#define SCRL 0x22
89#define SCRH 0x23
90#define LNC 0x24
91#define MCOR1 0x15
92#define MCOR2 0x16
93#define RTPR 0x21
94#define MSVR1 0x6c
95#define MSVR2 0x6d
96#define PSVR 0x6f
97#define RBPR 0x78
98#define RCOR 0x7c
99#define TBPR 0x72
100#define TCOR 0x76
101
102/*****************************************************************************/
103
104/*
105 * Define the set of baud rate clock divisors.
106 */
107#define CD1400_CLK0 8
108#define CD1400_CLK1 32
109#define CD1400_CLK2 128
110#define CD1400_CLK3 512
111#define CD1400_CLK4 2048
112
113#define CD1400_NUMCLKS 5
114
115/*****************************************************************************/
116
117/*
118 * Define the clock pre-scalar value to be a 5 ms clock. This should be
119 * OK for now. It would probably be better to make it 10 ms, but we
120 * can't fit that divisor into 8 bits!
121 */
122#define PPR_SCALAR 244
123
124/*****************************************************************************/
125
126/*
127 * Define values used to set character size options.
128 */
129#define COR1_CHL5 0x00
130#define COR1_CHL6 0x01
131#define COR1_CHL7 0x02
132#define COR1_CHL8 0x03
133
134/*
135 * Define values used to set the number of stop bits.
136 */
137#define COR1_STOP1 0x00
138#define COR1_STOP15 0x04
139#define COR1_STOP2 0x08
140
141/*
142 * Define values used to set the parity scheme in use.
143 */
144#define COR1_PARNONE 0x00
145#define COR1_PARFORCE 0x20
146#define COR1_PARENB 0x40
147#define COR1_PARIGNORE 0x10
148
149#define COR1_PARODD 0x80
150#define COR1_PAREVEN 0x00
151
152#define COR2_IXM 0x80
153#define COR2_TXIBE 0x40
154#define COR2_ETC 0x20
155#define COR2_LLM 0x10
156#define COR2_RLM 0x08
157#define COR2_RTSAO 0x04
158#define COR2_CTSAE 0x02
159
160#define COR3_SCDRNG 0x80
161#define COR3_SCD34 0x40
162#define COR3_FCT 0x20
163#define COR3_SCD12 0x10
164
165/*
166 * Define values used by COR4.
167 */
168#define COR4_BRKINT 0x08
169#define COR4_IGNBRK 0x18
170
171/*****************************************************************************/
172
173/*
174 * Define the modem control register values.
175 * Note that the actual hardware is a little different to the conventional
176 * pin names on the cd1400.
177 */
178#define MSVR1_DTR 0x01
179#define MSVR1_DSR 0x10
180#define MSVR1_RI 0x20
181#define MSVR1_CTS 0x40
182#define MSVR1_DCD 0x80
183
184#define MSVR2_RTS 0x02
185#define MSVR2_DSR 0x10
186#define MSVR2_RI 0x20
187#define MSVR2_CTS 0x40
188#define MSVR2_DCD 0x80
189
190#define MCOR1_DCD 0x80
191#define MCOR1_CTS 0x40
192#define MCOR1_RI 0x20
193#define MCOR1_DSR 0x10
194
195#define MCOR2_DCD 0x80
196#define MCOR2_CTS 0x40
197#define MCOR2_RI 0x20
198#define MCOR2_DSR 0x10
199
200/*****************************************************************************/
201
202/*
203 * Define the bits used with the service (interrupt) enable register.
204 */
205#define SRER_NNDT 0x01
206#define SRER_TXEMPTY 0x02
207#define SRER_TXDATA 0x04
208#define SRER_RXDATA 0x10
209#define SRER_MODEM 0x80
210
211/*****************************************************************************/
212
213/*
214 * Define operational commands for the command register.
215 */
216#define CCR_RESET 0x80
217#define CCR_CORCHANGE 0x4e
218#define CCR_SENDCH 0x20
219#define CCR_CHANCTRL 0x10
220
221#define CCR_TXENABLE (CCR_CHANCTRL | 0x08)
222#define CCR_TXDISABLE (CCR_CHANCTRL | 0x04)
223#define CCR_RXENABLE (CCR_CHANCTRL | 0x02)
224#define CCR_RXDISABLE (CCR_CHANCTRL | 0x01)
225
226#define CCR_SENDSCHR1 (CCR_SENDCH | 0x01)
227#define CCR_SENDSCHR2 (CCR_SENDCH | 0x02)
228#define CCR_SENDSCHR3 (CCR_SENDCH | 0x03)
229#define CCR_SENDSCHR4 (CCR_SENDCH | 0x04)
230
231#define CCR_RESETCHAN (CCR_RESET | 0x00)
232#define CCR_RESETFULL (CCR_RESET | 0x01)
233#define CCR_TXFLUSHFIFO (CCR_RESET | 0x02)
234
235#define CCR_MAXWAIT 10000
236
237/*****************************************************************************/
238
239/*
240 * Define the valid acknowledgement types (for hw ack cycle).
241 */
242#define ACK_TYPMASK 0x07
243#define ACK_TYPTX 0x02
244#define ACK_TYPMDM 0x01
245#define ACK_TYPRXGOOD 0x03
246#define ACK_TYPRXBAD 0x07
247
248#define SVRR_RX 0x01
249#define SVRR_TX 0x02
250#define SVRR_MDM 0x04
251
252#define ST_OVERRUN 0x01
253#define ST_FRAMING 0x02
254#define ST_PARITY 0x04
255#define ST_BREAK 0x08
256#define ST_SCHAR1 0x10
257#define ST_SCHAR2 0x20
258#define ST_SCHAR3 0x30
259#define ST_SCHAR4 0x40
260#define ST_RANGE 0x70
261#define ST_SCHARMASK 0x70
262#define ST_TIMEOUT 0x80
263
264#define MISR_DCD 0x80
265#define MISR_CTS 0x40
266#define MISR_RI 0x20
267#define MISR_DSR 0x10
268
269/*****************************************************************************/
270
271/*
272 * Defines for the CCSR status register.
273 */
274#define CCSR_RXENABLED 0x80
275#define CCSR_RXFLOWON 0x40
276#define CCSR_RXFLOWOFF 0x20
277#define CCSR_TXENABLED 0x08
278#define CCSR_TXFLOWON 0x04
279#define CCSR_TXFLOWOFF 0x02
280
281/*****************************************************************************/
282
283/*
284 * Define the embedded commands.
285 */
286#define ETC_CMD 0x00
287#define ETC_STARTBREAK 0x81
288#define ETC_DELAY 0x82
289#define ETC_STOPBREAK 0x83
290
291/*****************************************************************************/
292#endif
diff --git a/include/linux/cdk.h b/include/linux/cdk.h
deleted file mode 100644
index 80093a8d4f64..000000000000
--- a/include/linux/cdk.h
+++ /dev/null
@@ -1,486 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * cdk.h -- CDK interface definitions.
5 *
6 * Copyright (C) 1996-1998 Stallion Technologies
7 * Copyright (C) 1994-1996 Greg Ungerer.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24/*****************************************************************************/
25#ifndef _CDK_H
26#define _CDK_H
27/*****************************************************************************/
28
29#pragma pack(2)
30
31/*
32 * The following set of definitions is used to communicate with the
33 * shared memory interface of the Stallion intelligent multiport serial
34 * boards. The definitions in this file are taken directly from the
35 * document titled "Generic Stackable Interface, Downloader and
36 * Communications Development Kit".
37 */
38
39/*
40 * Define the set of important shared memory addresses. These are
41 * required to initialize the board and get things started. All of these
42 * addresses are relative to the start of the shared memory.
43 */
44#define CDK_SIGADDR 0x200
45#define CDK_FEATADDR 0x280
46#define CDK_CDKADDR 0x300
47#define CDK_RDYADDR 0x262
48
49#define CDK_ALIVEMARKER 13
50
51/*
52 * On hardware power up the ROMs located on the EasyConnection 8/64 will
53 * fill out the following signature information into shared memory. This
54 * way the host system can quickly determine that the board is present
55 * and is operational.
56 */
57typedef struct cdkecpsig {
58 unsigned long magic;
59 unsigned short romver;
60 unsigned short cputype;
61 unsigned char panelid[8];
62} cdkecpsig_t;
63
64#define ECP_MAGIC 0x21504345
65
66/*
67 * On hardware power up the ROMs located on the ONboard, Stallion and
68 * Brumbys will fill out the following signature information into shared
69 * memory. This way the host system can quickly determine that the board
70 * is present and is operational.
71 */
72typedef struct cdkonbsig {
73 unsigned short magic0;
74 unsigned short magic1;
75 unsigned short magic2;
76 unsigned short magic3;
77 unsigned short romver;
78 unsigned short memoff;
79 unsigned short memseg;
80 unsigned short amask0;
81 unsigned short pic;
82 unsigned short status;
83 unsigned short btype;
84 unsigned short clkticks;
85 unsigned short clkspeed;
86 unsigned short amask1;
87 unsigned short amask2;
88} cdkonbsig_t;
89
90#define ONB_MAGIC0 0xf2a7
91#define ONB_MAGIC1 0xa149
92#define ONB_MAGIC2 0x6352
93#define ONB_MAGIC3 0xf121
94
95/*
96 * Define the feature area structure. The feature area is the set of
97 * startup parameters used by the slave image when it starts executing.
98 * They allow for the specification of buffer sizes, debug trace, etc.
99 */
100typedef struct cdkfeature {
101 unsigned long debug;
102 unsigned long banner;
103 unsigned long etype;
104 unsigned long nrdevs;
105 unsigned long brdspec;
106 unsigned long txrqsize;
107 unsigned long rxrqsize;
108 unsigned long flags;
109} cdkfeature_t;
110
111#define ETYP_DDK 0
112#define ETYP_CDK 1
113
114/*
115 * Define the CDK header structure. This is the info that the slave
116 * environment sets up after it has been downloaded and started. It
117 * essentially provides a memory map for the shared memory interface.
118 */
119typedef struct cdkhdr {
120 unsigned short command;
121 unsigned short status;
122 unsigned short port;
123 unsigned short mode;
124 unsigned long cmd_buf[14];
125 unsigned short alive_cnt;
126 unsigned short intrpt_mode;
127 unsigned char intrpt_id[8];
128 unsigned char ver_release;
129 unsigned char ver_modification;
130 unsigned char ver_fix;
131 unsigned char deadman_restart;
132 unsigned short deadman;
133 unsigned short nrdevs;
134 unsigned long memp;
135 unsigned long hostp;
136 unsigned long slavep;
137 unsigned char hostreq;
138 unsigned char slavereq;
139 unsigned char cmd_reserved[30];
140} cdkhdr_t;
141
142#define MODE_DDK 0
143#define MODE_CDK 1
144
145#define IMD_INTR 0x0
146#define IMD_PPINTR 0x1
147#define IMD_POLL 0xff
148
149/*
150 * Define the memory mapping structure. This structure is pointed to by
151 * the memp field in the stlcdkhdr struct. As many as these structures
152 * as required are laid out in shared memory to define how the rest of
153 * shared memory is divided up. There will be one for each port.
154 */
155typedef struct cdkmem {
156 unsigned short dtype;
157 unsigned long offset;
158} cdkmem_t;
159
160#define TYP_UNDEFINED 0x0
161#define TYP_ASYNCTRL 0x1
162#define TYP_ASYNC 0x20
163#define TYP_PARALLEL 0x40
164#define TYP_SYNCX21 0x60
165
166/*****************************************************************************/
167
168/*
169 * Following is a set of defines and structures used to actually deal
170 * with the serial ports on the board. Firstly is the set of commands
171 * that can be applied to ports.
172 */
173#define ASYCMD (((unsigned long) 'a') << 8)
174
175#define A_NULL (ASYCMD | 0)
176#define A_FLUSH (ASYCMD | 1)
177#define A_BREAK (ASYCMD | 2)
178#define A_GETPORT (ASYCMD | 3)
179#define A_SETPORT (ASYCMD | 4)
180#define A_SETPORTF (ASYCMD | 5)
181#define A_SETPORTFTX (ASYCMD | 6)
182#define A_SETPORTFRX (ASYCMD | 7)
183#define A_GETSIGNALS (ASYCMD | 8)
184#define A_SETSIGNALS (ASYCMD | 9)
185#define A_SETSIGNALSF (ASYCMD | 10)
186#define A_SETSIGNALSFTX (ASYCMD | 11)
187#define A_SETSIGNALSFRX (ASYCMD | 12)
188#define A_GETNOTIFY (ASYCMD | 13)
189#define A_SETNOTIFY (ASYCMD | 14)
190#define A_NOTIFY (ASYCMD | 15)
191#define A_PORTCTRL (ASYCMD | 16)
192#define A_GETSTATS (ASYCMD | 17)
193#define A_RQSTATE (ASYCMD | 18)
194#define A_FLOWSTATE (ASYCMD | 19)
195#define A_CLEARSTATS (ASYCMD | 20)
196
197/*
198 * Define those arguments used for simple commands.
199 */
200#define FLUSHRX 0x1
201#define FLUSHTX 0x2
202
203#define BREAKON -1
204#define BREAKOFF -2
205
206/*
207 * Define the port setting structure, and all those defines that go along
208 * with it. Basically this structure defines the characteristics of this
209 * port: baud rate, chars, parity, input/output char cooking etc.
210 */
211typedef struct asyport {
212 unsigned long baudout;
213 unsigned long baudin;
214 unsigned long iflag;
215 unsigned long oflag;
216 unsigned long lflag;
217 unsigned long pflag;
218 unsigned long flow;
219 unsigned long spare1;
220 unsigned short vtime;
221 unsigned short vmin;
222 unsigned short txlo;
223 unsigned short txhi;
224 unsigned short rxlo;
225 unsigned short rxhi;
226 unsigned short rxhog;
227 unsigned short spare2;
228 unsigned char csize;
229 unsigned char stopbs;
230 unsigned char parity;
231 unsigned char stopin;
232 unsigned char startin;
233 unsigned char stopout;
234 unsigned char startout;
235 unsigned char parmark;
236 unsigned char brkmark;
237 unsigned char cc[11];
238} asyport_t;
239
240#define PT_STOP1 0x0
241#define PT_STOP15 0x1
242#define PT_STOP2 0x2
243
244#define PT_NOPARITY 0x0
245#define PT_ODDPARITY 0x1
246#define PT_EVENPARITY 0x2
247#define PT_MARKPARITY 0x3
248#define PT_SPACEPARITY 0x4
249
250#define F_NONE 0x0
251#define F_IXON 0x1
252#define F_IXOFF 0x2
253#define F_IXANY 0x4
254#define F_IOXANY 0x8
255#define F_RTSFLOW 0x10
256#define F_CTSFLOW 0x20
257#define F_DTRFLOW 0x40
258#define F_DCDFLOW 0x80
259#define F_DSROFLOW 0x100
260#define F_DSRIFLOW 0x200
261
262#define FI_NORX 0x1
263#define FI_RAW 0x2
264#define FI_ISTRIP 0x4
265#define FI_UCLC 0x8
266#define FI_INLCR 0x10
267#define FI_ICRNL 0x20
268#define FI_IGNCR 0x40
269#define FI_IGNBREAK 0x80
270#define FI_DSCRDBREAK 0x100
271#define FI_1MARKBREAK 0x200
272#define FI_2MARKBREAK 0x400
273#define FI_XCHNGBREAK 0x800
274#define FI_IGNRXERRS 0x1000
275#define FI_DSCDRXERRS 0x2000
276#define FI_1MARKRXERRS 0x4000
277#define FI_2MARKRXERRS 0x8000
278#define FI_XCHNGRXERRS 0x10000
279#define FI_DSCRDNULL 0x20000
280
281#define FO_OLCUC 0x1
282#define FO_ONLCR 0x2
283#define FO_OOCRNL 0x4
284#define FO_ONOCR 0x8
285#define FO_ONLRET 0x10
286#define FO_ONL 0x20
287#define FO_OBS 0x40
288#define FO_OVT 0x80
289#define FO_OFF 0x100
290#define FO_OTAB1 0x200
291#define FO_OTAB2 0x400
292#define FO_OTAB3 0x800
293#define FO_OCR1 0x1000
294#define FO_OCR2 0x2000
295#define FO_OCR3 0x4000
296#define FO_OFILL 0x8000
297#define FO_ODELL 0x10000
298
299#define P_RTSLOCK 0x1
300#define P_CTSLOCK 0x2
301#define P_MAPRTS 0x4
302#define P_MAPCTS 0x8
303#define P_LOOPBACK 0x10
304#define P_DTRFOLLOW 0x20
305#define P_FAKEDCD 0x40
306
307#define P_RXIMIN 0x10000
308#define P_RXITIME 0x20000
309#define P_RXTHOLD 0x40000
310
311/*
312 * Define a structure to communicate serial port signal and data state
313 * information.
314 */
315typedef struct asysigs {
316 unsigned long data;
317 unsigned long signal;
318 unsigned long sigvalue;
319} asysigs_t;
320
321#define DT_TXBUSY 0x1
322#define DT_TXEMPTY 0x2
323#define DT_TXLOW 0x4
324#define DT_TXHIGH 0x8
325#define DT_TXFULL 0x10
326#define DT_TXHOG 0x20
327#define DT_TXFLOWED 0x40
328#define DT_TXBREAK 0x80
329
330#define DT_RXBUSY 0x100
331#define DT_RXEMPTY 0x200
332#define DT_RXLOW 0x400
333#define DT_RXHIGH 0x800
334#define DT_RXFULL 0x1000
335#define DT_RXHOG 0x2000
336#define DT_RXFLOWED 0x4000
337#define DT_RXBREAK 0x8000
338
339#define SG_DTR 0x1
340#define SG_DCD 0x2
341#define SG_RTS 0x4
342#define SG_CTS 0x8
343#define SG_DSR 0x10
344#define SG_RI 0x20
345
346/*
347 * Define the notification setting structure. This is used to tell the
348 * port what events we want to be informed about. Fields here use the
349 * same defines as for the asysigs structure above.
350 */
351typedef struct asynotify {
352 unsigned long ctrl;
353 unsigned long data;
354 unsigned long signal;
355 unsigned long sigvalue;
356} asynotify_t;
357
358/*
359 * Define the port control structure. It is used to do fine grain
360 * control operations on the port.
361 */
362typedef struct {
363 unsigned long rxctrl;
364 unsigned long txctrl;
365 char rximdch;
366 char tximdch;
367 char spare1;
368 char spare2;
369} asyctrl_t;
370
371#define CT_ENABLE 0x1
372#define CT_DISABLE 0x2
373#define CT_STOP 0x4
374#define CT_START 0x8
375#define CT_STARTFLOW 0x10
376#define CT_STOPFLOW 0x20
377#define CT_SENDCHR 0x40
378
379/*
380 * Define the stats structure kept for each port. This is a useful set
381 * of data collected for each port on the slave. The A_GETSTATS command
382 * is used to retrieve this data from the slave.
383 */
384typedef struct asystats {
385 unsigned long opens;
386 unsigned long txchars;
387 unsigned long rxchars;
388 unsigned long txringq;
389 unsigned long rxringq;
390 unsigned long txmsgs;
391 unsigned long rxmsgs;
392 unsigned long txflushes;
393 unsigned long rxflushes;
394 unsigned long overruns;
395 unsigned long framing;
396 unsigned long parity;
397 unsigned long ringover;
398 unsigned long lost;
399 unsigned long rxstart;
400 unsigned long rxstop;
401 unsigned long txstart;
402 unsigned long txstop;
403 unsigned long dcdcnt;
404 unsigned long dtrcnt;
405 unsigned long ctscnt;
406 unsigned long rtscnt;
407 unsigned long dsrcnt;
408 unsigned long ricnt;
409 unsigned long txbreaks;
410 unsigned long rxbreaks;
411 unsigned long signals;
412 unsigned long state;
413 unsigned long hwid;
414} asystats_t;
415
416/*****************************************************************************/
417
418/*
419 * All command and control communication with a device on the slave is
420 * via a control block in shared memory. Each device has its own control
421 * block, defined by the following structure. The control block allows
422 * the host to open, close and control the device on the slave.
423 */
424typedef struct cdkctrl {
425 unsigned char open;
426 unsigned char close;
427 unsigned long openarg;
428 unsigned long closearg;
429 unsigned long cmd;
430 unsigned long status;
431 unsigned long args[32];
432} cdkctrl_t;
433
434/*
435 * Each device on the slave passes data to and from the host via a ring
436 * queue in shared memory. Define a ring queue structure to hold the
437 * vital information about each ring queue. Two ring queues will be
438 * allocated for each port, one for receive data and one for transmit
439 * data.
440 */
441typedef struct cdkasyrq {
442 unsigned long offset;
443 unsigned short size;
444 unsigned short head;
445 unsigned short tail;
446} cdkasyrq_t;
447
448/*
449 * Each asynchronous port is defined in shared memory by the following
450 * structure. It contains a control block to command a device, and also
451 * the necessary data channel information as well.
452 */
453typedef struct cdkasy {
454 cdkctrl_t ctrl;
455 unsigned short notify;
456 asynotify_t changed;
457 unsigned short receive;
458 cdkasyrq_t rxq;
459 unsigned short transmit;
460 cdkasyrq_t txq;
461} cdkasy_t;
462
463#pragma pack()
464
465/*****************************************************************************/
466
467/*
468 * Define the set of ioctls used by the driver to do special things
469 * to the board. These include interrupting it, and initializing
470 * the driver after board startup and shutdown.
471 */
472#include <linux/ioctl.h>
473
474#define STL_BINTR _IO('s',20)
475#define STL_BSTART _IO('s',21)
476#define STL_BSTOP _IO('s',22)
477#define STL_BRESET _IO('s',23)
478
479/*
480 * Define a set of ioctl extensions, used to get at special stuff.
481 */
482#define STL_GETPFLAG _IO('s',80)
483#define STL_SETPFLAG _IO('s',81)
484
485/*****************************************************************************/
486#endif
diff --git a/include/linux/comstats.h b/include/linux/comstats.h
deleted file mode 100644
index 3f5ea8e8026d..000000000000
--- a/include/linux/comstats.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * comstats.h -- Serial Port Stats.
5 *
6 * Copyright (C) 1996-1998 Stallion Technologies
7 * Copyright (C) 1994-1996 Greg Ungerer.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24/*****************************************************************************/
25#ifndef _COMSTATS_H
26#define _COMSTATS_H
27/*****************************************************************************/
28
29/*
30 * Serial port stats structure. The structure itself is UART
31 * independent, but some fields may be UART/driver specific (for
32 * example state).
33 */
34
35typedef struct {
36 unsigned long brd;
37 unsigned long panel;
38 unsigned long port;
39 unsigned long hwid;
40 unsigned long type;
41 unsigned long txtotal;
42 unsigned long rxtotal;
43 unsigned long txbuffered;
44 unsigned long rxbuffered;
45 unsigned long rxoverrun;
46 unsigned long rxparity;
47 unsigned long rxframing;
48 unsigned long rxlost;
49 unsigned long txbreaks;
50 unsigned long rxbreaks;
51 unsigned long txxon;
52 unsigned long txxoff;
53 unsigned long rxxon;
54 unsigned long rxxoff;
55 unsigned long txctson;
56 unsigned long txctsoff;
57 unsigned long rxrtson;
58 unsigned long rxrtsoff;
59 unsigned long modem;
60 unsigned long state;
61 unsigned long flags;
62 unsigned long ttystate;
63 unsigned long cflags;
64 unsigned long iflags;
65 unsigned long oflags;
66 unsigned long lflags;
67 unsigned long signals;
68} comstats_t;
69
70
71/*
72 * Board stats structure. Returns useful info about the board.
73 */
74
75#define COM_MAXPANELS 8
76
77typedef struct {
78 unsigned long panel;
79 unsigned long type;
80 unsigned long hwid;
81 unsigned long nrports;
82} companel_t;
83
84typedef struct {
85 unsigned long brd;
86 unsigned long type;
87 unsigned long hwid;
88 unsigned long state;
89 unsigned long ioaddr;
90 unsigned long ioaddr2;
91 unsigned long memaddr;
92 unsigned long irq;
93 unsigned long nrpanels;
94 unsigned long nrports;
95 companel_t panels[COM_MAXPANELS];
96} combrd_t;
97
98
99/*
100 * Define the ioctl operations for stats stuff.
101 */
102#include <linux/ioctl.h>
103
104#define COM_GETPORTSTATS _IO('c',30)
105#define COM_CLRPORTSTATS _IO('c',31)
106#define COM_GETBRDSTATS _IO('c',32)
107
108
109/*
110 * Define the set of ioctls that give user level access to the
111 * private port, panel and board structures. The argument required
112 * will be driver dependent!
113 */
114#define COM_READPORT _IO('c',40)
115#define COM_READBOARD _IO('c',41)
116#define COM_READPANEL _IO('c',42)
117
118/*****************************************************************************/
119#endif
diff --git a/include/linux/istallion.h b/include/linux/istallion.h
deleted file mode 100644
index ad700a60c158..000000000000
--- a/include/linux/istallion.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * istallion.h -- stallion intelligent multiport serial driver.
5 *
6 * Copyright (C) 1996-1998 Stallion Technologies
7 * Copyright (C) 1994-1996 Greg Ungerer.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24/*****************************************************************************/
25#ifndef _ISTALLION_H
26#define _ISTALLION_H
27/*****************************************************************************/
28
29/*
30 * Define important driver constants here.
31 */
32#define STL_MAXBRDS 4
33#define STL_MAXPANELS 4
34#define STL_MAXPORTS 64
35#define STL_MAXCHANS (STL_MAXPORTS + 1)
36#define STL_MAXDEVS (STL_MAXBRDS * STL_MAXPORTS)
37
38
39/*
40 * Define a set of structures to hold all the board/panel/port info
41 * for our ports. These will be dynamically allocated as required at
42 * driver initialization time.
43 */
44
45/*
46 * Port and board structures to hold status info about each object.
47 * The board structure contains pointers to structures for each port
48 * connected to it. Panels are not distinguished here, since
49 * communication with the slave board will always be on a per port
50 * basis.
51 */
52struct stliport {
53 unsigned long magic;
54 struct tty_port port;
55 unsigned int portnr;
56 unsigned int panelnr;
57 unsigned int brdnr;
58 unsigned long state;
59 unsigned int devnr;
60 int baud_base;
61 int custom_divisor;
62 int closing_wait;
63 int rc;
64 int argsize;
65 void *argp;
66 unsigned int rxmarkmsk;
67 wait_queue_head_t raw_wait;
68 struct asysigs asig;
69 unsigned long addr;
70 unsigned long rxoffset;
71 unsigned long txoffset;
72 unsigned long sigs;
73 unsigned long pflag;
74 unsigned int rxsize;
75 unsigned int txsize;
76 unsigned char reqbit;
77 unsigned char portidx;
78 unsigned char portbit;
79};
80
81/*
82 * Use a structure of function pointers to do board level operations.
83 * These include, enable/disable, paging shared memory, interrupting, etc.
84 */
85struct stlibrd {
86 unsigned long magic;
87 unsigned int brdnr;
88 unsigned int brdtype;
89 unsigned long state;
90 unsigned int nrpanels;
91 unsigned int nrports;
92 unsigned int nrdevs;
93 unsigned int iobase;
94 int iosize;
95 unsigned long memaddr;
96 void __iomem *membase;
97 unsigned long memsize;
98 int pagesize;
99 int hostoffset;
100 int slaveoffset;
101 int bitsize;
102 int enabval;
103 unsigned int panels[STL_MAXPANELS];
104 int panelids[STL_MAXPANELS];
105 void (*init)(struct stlibrd *brdp);
106 void (*enable)(struct stlibrd *brdp);
107 void (*reenable)(struct stlibrd *brdp);
108 void (*disable)(struct stlibrd *brdp);
109 void __iomem *(*getmemptr)(struct stlibrd *brdp, unsigned long offset, int line);
110 void (*intr)(struct stlibrd *brdp);
111 void (*reset)(struct stlibrd *brdp);
112 struct stliport *ports[STL_MAXPORTS];
113};
114
115
116/*
117 * Define MAGIC numbers used for above structures.
118 */
119#define STLI_PORTMAGIC 0xe671c7a1
120#define STLI_BOARDMAGIC 0x4bc6c825
121
122/*****************************************************************************/
123#endif
diff --git a/include/linux/sc26198.h b/include/linux/sc26198.h
deleted file mode 100644
index 7ca35abad387..000000000000
--- a/include/linux/sc26198.h
+++ /dev/null
@@ -1,533 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * sc26198.h -- SC26198 UART hardware info.
5 *
6 * Copyright (C) 1995-1998 Stallion Technologies
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*****************************************************************************/
24#ifndef _SC26198_H
25#define _SC26198_H
26/*****************************************************************************/
27
28/*
29 * Define the number of async ports per sc26198 uart device.
30 */
31#define SC26198_PORTS 8
32
33/*
34 * Baud rate timing clocks. All derived from a master 14.7456 MHz clock.
35 */
36#define SC26198_MASTERCLOCK 14745600L
37#define SC26198_DCLK (SC26198_MASTERCLOCK)
38#define SC26198_CCLK (SC26198_MASTERCLOCK / 2)
39#define SC26198_BCLK (SC26198_MASTERCLOCK / 4)
40
41/*
42 * Define internal FIFO sizes for the 26198 ports.
43 */
44#define SC26198_TXFIFOSIZE 16
45#define SC26198_RXFIFOSIZE 16
46
47/*****************************************************************************/
48
49/*
50 * Global register definitions. These registers are global to each 26198
51 * device, not specific ports on it.
52 */
53#define TSTR 0x0d
54#define GCCR 0x0f
55#define ICR 0x1b
56#define WDTRCR 0x1d
57#define IVR 0x1f
58#define BRGTRUA 0x84
59#define GPOSR 0x87
60#define GPOC 0x8b
61#define UCIR 0x8c
62#define CIR 0x8c
63#define BRGTRUB 0x8d
64#define GRXFIFO 0x8e
65#define GTXFIFO 0x8e
66#define GCCR2 0x8f
67#define BRGTRLA 0x94
68#define GPOR 0x97
69#define GPOD 0x9b
70#define BRGTCR 0x9c
71#define GICR 0x9c
72#define BRGTRLB 0x9d
73#define GIBCR 0x9d
74#define GITR 0x9f
75
76/*
77 * Per port channel registers. These are the register offsets within
78 * the port address space, so need to have the port address (0 to 7)
79 * inserted in bit positions 4:6.
80 */
81#define MR0 0x00
82#define MR1 0x01
83#define IOPCR 0x02
84#define BCRBRK 0x03
85#define BCRCOS 0x04
86#define BCRX 0x06
87#define BCRA 0x07
88#define XONCR 0x08
89#define XOFFCR 0x09
90#define ARCR 0x0a
91#define RXCSR 0x0c
92#define TXCSR 0x0e
93#define MR2 0x80
94#define SR 0x81
95#define SCCR 0x81
96#define ISR 0x82
97#define IMR 0x82
98#define TXFIFO 0x83
99#define RXFIFO 0x83
100#define IPR 0x84
101#define IOPIOR 0x85
102#define XISR 0x86
103
104/*
105 * For any given port calculate the address to use to access a specified
106 * register. This is only used for unusual access, mostly this is done
107 * through the assembler access routines.
108 */
109#define SC26198_PORTREG(port,reg) ((((port) & 0x07) << 4) | (reg))
110
111/*****************************************************************************/
112
113/*
114 * Global configuration control register bit definitions.
115 */
116#define GCCR_NOACK 0x00
117#define GCCR_IVRACK 0x02
118#define GCCR_IVRCHANACK 0x04
119#define GCCR_IVRTYPCHANACK 0x06
120#define GCCR_ASYNCCYCLE 0x00
121#define GCCR_SYNCCYCLE 0x40
122
123/*****************************************************************************/
124
125/*
126 * Mode register 0 bit definitions.
127 */
128#define MR0_ADDRNONE 0x00
129#define MR0_AUTOWAKE 0x01
130#define MR0_AUTODOZE 0x02
131#define MR0_AUTOWAKEDOZE 0x03
132#define MR0_SWFNONE 0x00
133#define MR0_SWFTX 0x04
134#define MR0_SWFRX 0x08
135#define MR0_SWFRXTX 0x0c
136#define MR0_TXMASK 0x30
137#define MR0_TXEMPTY 0x00
138#define MR0_TXHIGH 0x10
139#define MR0_TXHALF 0x20
140#define MR0_TXRDY 0x00
141#define MR0_ADDRNT 0x00
142#define MR0_ADDRT 0x40
143#define MR0_SWFNT 0x00
144#define MR0_SWFT 0x80
145
146/*
147 * Mode register 1 bit definitions.
148 */
149#define MR1_CS5 0x00
150#define MR1_CS6 0x01
151#define MR1_CS7 0x02
152#define MR1_CS8 0x03
153#define MR1_PAREVEN 0x00
154#define MR1_PARODD 0x04
155#define MR1_PARENB 0x00
156#define MR1_PARFORCE 0x08
157#define MR1_PARNONE 0x10
158#define MR1_PARSPECIAL 0x18
159#define MR1_ERRCHAR 0x00
160#define MR1_ERRBLOCK 0x20
161#define MR1_ISRUNMASKED 0x00
162#define MR1_ISRMASKED 0x40
163#define MR1_AUTORTS 0x80
164
165/*
166 * Mode register 2 bit definitions.
167 */
168#define MR2_STOP1 0x00
169#define MR2_STOP15 0x01
170#define MR2_STOP2 0x02
171#define MR2_STOP916 0x03
172#define MR2_RXFIFORDY 0x00
173#define MR2_RXFIFOHALF 0x04
174#define MR2_RXFIFOHIGH 0x08
175#define MR2_RXFIFOFULL 0x0c
176#define MR2_AUTOCTS 0x10
177#define MR2_TXRTS 0x20
178#define MR2_MODENORM 0x00
179#define MR2_MODEAUTOECHO 0x40
180#define MR2_MODELOOP 0x80
181#define MR2_MODEREMECHO 0xc0
182
183/*****************************************************************************/
184
185/*
186 * Baud Rate Generator (BRG) selector values.
187 */
188#define BRG_50 0x00
189#define BRG_75 0x01
190#define BRG_150 0x02
191#define BRG_200 0x03
192#define BRG_300 0x04
193#define BRG_450 0x05
194#define BRG_600 0x06
195#define BRG_900 0x07
196#define BRG_1200 0x08
197#define BRG_1800 0x09
198#define BRG_2400 0x0a
199#define BRG_3600 0x0b
200#define BRG_4800 0x0c
201#define BRG_7200 0x0d
202#define BRG_9600 0x0e
203#define BRG_14400 0x0f
204#define BRG_19200 0x10
205#define BRG_28200 0x11
206#define BRG_38400 0x12
207#define BRG_57600 0x13
208#define BRG_115200 0x14
209#define BRG_230400 0x15
210#define BRG_GIN0 0x16
211#define BRG_GIN1 0x17
212#define BRG_CT0 0x18
213#define BRG_CT1 0x19
214#define BRG_RX2TX316 0x1b
215#define BRG_RX2TX31 0x1c
216
217#define SC26198_MAXBAUD 921600
218
219/*****************************************************************************/
220
221/*
222 * Command register command definitions.
223 */
224#define CR_NULL 0x04
225#define CR_ADDRNORMAL 0x0c
226#define CR_RXRESET 0x14
227#define CR_TXRESET 0x1c
228#define CR_CLEARRXERR 0x24
229#define CR_BREAKRESET 0x2c
230#define CR_TXSTARTBREAK 0x34
231#define CR_TXSTOPBREAK 0x3c
232#define CR_RTSON 0x44
233#define CR_RTSOFF 0x4c
234#define CR_ADDRINIT 0x5c
235#define CR_RXERRBLOCK 0x6c
236#define CR_TXSENDXON 0x84
237#define CR_TXSENDXOFF 0x8c
238#define CR_GANGXONSET 0x94
239#define CR_GANGXOFFSET 0x9c
240#define CR_GANGXONINIT 0xa4
241#define CR_GANGXOFFINIT 0xac
242#define CR_HOSTXON 0xb4
243#define CR_HOSTXOFF 0xbc
244#define CR_CANCELXOFF 0xc4
245#define CR_ADDRRESET 0xdc
246#define CR_RESETALLPORTS 0xf4
247#define CR_RESETALL 0xfc
248
249#define CR_RXENABLE 0x01
250#define CR_TXENABLE 0x02
251
252/*****************************************************************************/
253
254/*
255 * Channel status register.
256 */
257#define SR_RXRDY 0x01
258#define SR_RXFULL 0x02
259#define SR_TXRDY 0x04
260#define SR_TXEMPTY 0x08
261#define SR_RXOVERRUN 0x10
262#define SR_RXPARITY 0x20
263#define SR_RXFRAMING 0x40
264#define SR_RXBREAK 0x80
265
266#define SR_RXERRS (SR_RXPARITY | SR_RXFRAMING | SR_RXOVERRUN)
267
268/*****************************************************************************/
269
270/*
271 * Interrupt status register and interrupt mask register bit definitions.
272 */
273#define IR_TXRDY 0x01
274#define IR_RXRDY 0x02
275#define IR_RXBREAK 0x04
276#define IR_XONXOFF 0x10
277#define IR_ADDRRECOG 0x20
278#define IR_RXWATCHDOG 0x40
279#define IR_IOPORT 0x80
280
281/*****************************************************************************/
282
283/*
284 * Interrupt vector register field definitions.
285 */
286#define IVR_CHANMASK 0x07
287#define IVR_TYPEMASK 0x18
288#define IVR_CONSTMASK 0xc0
289
290#define IVR_RXDATA 0x10
291#define IVR_RXBADDATA 0x18
292#define IVR_TXDATA 0x08
293#define IVR_OTHER 0x00
294
295/*****************************************************************************/
296
297/*
298 * BRG timer control register bit definitions.
299 */
300#define BRGCTCR_DISABCLK0 0x00
301#define BRGCTCR_ENABCLK0 0x08
302#define BRGCTCR_DISABCLK1 0x00
303#define BRGCTCR_ENABCLK1 0x80
304
305#define BRGCTCR_0SCLK16 0x00
306#define BRGCTCR_0SCLK32 0x01
307#define BRGCTCR_0SCLK64 0x02
308#define BRGCTCR_0SCLK128 0x03
309#define BRGCTCR_0X1 0x04
310#define BRGCTCR_0X12 0x05
311#define BRGCTCR_0IO1A 0x06
312#define BRGCTCR_0GIN0 0x07
313
314#define BRGCTCR_1SCLK16 0x00
315#define BRGCTCR_1SCLK32 0x10
316#define BRGCTCR_1SCLK64 0x20
317#define BRGCTCR_1SCLK128 0x30
318#define BRGCTCR_1X1 0x40
319#define BRGCTCR_1X12 0x50
320#define BRGCTCR_1IO1B 0x60
321#define BRGCTCR_1GIN1 0x70
322
323/*****************************************************************************/
324
325/*
326 * Watch dog timer enable register.
327 */
328#define WDTRCR_ENABALL 0xff
329
330/*****************************************************************************/
331
332/*
333 * XON/XOFF interrupt status register.
334 */
335#define XISR_TXCHARMASK 0x03
336#define XISR_TXCHARNORMAL 0x00
337#define XISR_TXWAIT 0x01
338#define XISR_TXXOFFPEND 0x02
339#define XISR_TXXONPEND 0x03
340
341#define XISR_TXFLOWMASK 0x0c
342#define XISR_TXNORMAL 0x00
343#define XISR_TXSTOPPEND 0x04
344#define XISR_TXSTARTED 0x08
345#define XISR_TXSTOPPED 0x0c
346
347#define XISR_RXFLOWMASK 0x30
348#define XISR_RXFLOWNONE 0x00
349#define XISR_RXXONSENT 0x10
350#define XISR_RXXOFFSENT 0x20
351
352#define XISR_RXXONGOT 0x40
353#define XISR_RXXOFFGOT 0x80
354
355/*****************************************************************************/
356
357/*
358 * Current interrupt register.
359 */
360#define CIR_TYPEMASK 0xc0
361#define CIR_TYPEOTHER 0x00
362#define CIR_TYPETX 0x40
363#define CIR_TYPERXGOOD 0x80
364#define CIR_TYPERXBAD 0xc0
365
366#define CIR_RXDATA 0x80
367#define CIR_RXBADDATA 0x40
368#define CIR_TXDATA 0x40
369
370#define CIR_CHANMASK 0x07
371#define CIR_CNTMASK 0x38
372
373#define CIR_SUBTYPEMASK 0x38
374#define CIR_SUBNONE 0x00
375#define CIR_SUBCOS 0x08
376#define CIR_SUBADDR 0x10
377#define CIR_SUBXONXOFF 0x18
378#define CIR_SUBBREAK 0x28
379
380/*****************************************************************************/
381
382/*
383 * Global interrupting channel register.
384 */
385#define GICR_CHANMASK 0x07
386
387/*****************************************************************************/
388
389/*
390 * Global interrupting byte count register.
391 */
392#define GICR_COUNTMASK 0x0f
393
394/*****************************************************************************/
395
396/*
397 * Global interrupting type register.
398 */
399#define GITR_RXMASK 0xc0
400#define GITR_RXNONE 0x00
401#define GITR_RXBADDATA 0x80
402#define GITR_RXGOODDATA 0xc0
403#define GITR_TXDATA 0x20
404
405#define GITR_SUBTYPEMASK 0x07
406#define GITR_SUBNONE 0x00
407#define GITR_SUBCOS 0x01
408#define GITR_SUBADDR 0x02
409#define GITR_SUBXONXOFF 0x03
410#define GITR_SUBBREAK 0x05
411
412/*****************************************************************************/
413
414/*
415 * Input port change register.
416 */
417#define IPR_CTS 0x01
418#define IPR_DTR 0x02
419#define IPR_RTS 0x04
420#define IPR_DCD 0x08
421#define IPR_CTSCHANGE 0x10
422#define IPR_DTRCHANGE 0x20
423#define IPR_RTSCHANGE 0x40
424#define IPR_DCDCHANGE 0x80
425
426#define IPR_CHANGEMASK 0xf0
427
428/*****************************************************************************/
429
430/*
431 * IO port interrupt and output register.
432 */
433#define IOPR_CTS 0x01
434#define IOPR_DTR 0x02
435#define IOPR_RTS 0x04
436#define IOPR_DCD 0x08
437#define IOPR_CTSCOS 0x10
438#define IOPR_DTRCOS 0x20
439#define IOPR_RTSCOS 0x40
440#define IOPR_DCDCOS 0x80
441
442/*****************************************************************************/
443
444/*
445 * IO port configuration register.
446 */
447#define IOPCR_SETCTS 0x00
448#define IOPCR_SETDTR 0x04
449#define IOPCR_SETRTS 0x10
450#define IOPCR_SETDCD 0x00
451
452#define IOPCR_SETSIGS (IOPCR_SETRTS | IOPCR_SETRTS | IOPCR_SETDTR | IOPCR_SETDCD)
453
454/*****************************************************************************/
455
456/*
457 * General purpose output select register.
458 */
459#define GPORS_TXC1XA 0x08
460#define GPORS_TXC16XA 0x09
461#define GPORS_RXC16XA 0x0a
462#define GPORS_TXC16XB 0x0b
463#define GPORS_GPOR3 0x0c
464#define GPORS_GPOR2 0x0d
465#define GPORS_GPOR1 0x0e
466#define GPORS_GPOR0 0x0f
467
468/*****************************************************************************/
469
470/*
471 * General purpose output register.
472 */
473#define GPOR_0 0x01
474#define GPOR_1 0x02
475#define GPOR_2 0x04
476#define GPOR_3 0x08
477
478/*****************************************************************************/
479
480/*
481 * General purpose output clock register.
482 */
483#define GPORC_0NONE 0x00
484#define GPORC_0GIN0 0x01
485#define GPORC_0GIN1 0x02
486#define GPORC_0IO3A 0x02
487
488#define GPORC_1NONE 0x00
489#define GPORC_1GIN0 0x04
490#define GPORC_1GIN1 0x08
491#define GPORC_1IO3C 0x0c
492
493#define GPORC_2NONE 0x00
494#define GPORC_2GIN0 0x10
495#define GPORC_2GIN1 0x20
496#define GPORC_2IO3E 0x20
497
498#define GPORC_3NONE 0x00
499#define GPORC_3GIN0 0x40
500#define GPORC_3GIN1 0x80
501#define GPORC_3IO3G 0xc0
502
503/*****************************************************************************/
504
505/*
506 * General purpose output data register.
507 */
508#define GPOD_0MASK 0x03
509#define GPOD_0SET1 0x00
510#define GPOD_0SET0 0x01
511#define GPOD_0SETR0 0x02
512#define GPOD_0SETIO3B 0x03
513
514#define GPOD_1MASK 0x0c
515#define GPOD_1SET1 0x00
516#define GPOD_1SET0 0x04
517#define GPOD_1SETR0 0x08
518#define GPOD_1SETIO3D 0x0c
519
520#define GPOD_2MASK 0x30
521#define GPOD_2SET1 0x00
522#define GPOD_2SET0 0x10
523#define GPOD_2SETR0 0x20
524#define GPOD_2SETIO3F 0x30
525
526#define GPOD_3MASK 0xc0
527#define GPOD_3SET1 0x00
528#define GPOD_3SET0 0x40
529#define GPOD_3SETR0 0x80
530#define GPOD_3SETIO3H 0xc0
531
532/*****************************************************************************/
533#endif
diff --git a/include/linux/serial167.h b/include/linux/serial167.h
deleted file mode 100644
index 59c81b708562..000000000000
--- a/include/linux/serial167.h
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * serial167.h
3 *
4 * Richard Hirst [richard@sleepie.demon.co.uk]
5 *
6 * Based on cyclades.h
7 */
8
9struct cyclades_monitor {
10 unsigned long int_count;
11 unsigned long char_count;
12 unsigned long char_max;
13 unsigned long char_last;
14};
15
16/*
17 * This is our internal structure for each serial port's state.
18 *
19 * Many fields are paralleled by the structure used by the serial_struct
20 * structure.
21 *
22 * For definitions of the flags field, see tty.h
23 */
24
25struct cyclades_port {
26 int magic;
27 int type;
28 int card;
29 int line;
30 int flags; /* defined in tty.h */
31 struct tty_struct *tty;
32 int read_status_mask;
33 int timeout;
34 int xmit_fifo_size;
35 int cor1,cor2,cor3,cor4,cor5,cor6,cor7;
36 int tbpr,tco,rbpr,rco;
37 int ignore_status_mask;
38 int close_delay;
39 int IER; /* Interrupt Enable Register */
40 unsigned long last_active;
41 int count; /* # of fd on device */
42 int x_char; /* to be pushed out ASAP */
43 int x_break;
44 int blocked_open; /* # of blocked opens */
45 unsigned char *xmit_buf;
46 int xmit_head;
47 int xmit_tail;
48 int xmit_cnt;
49 int default_threshold;
50 int default_timeout;
51 wait_queue_head_t open_wait;
52 wait_queue_head_t close_wait;
53 struct cyclades_monitor mon;
54};
55
56#define CYCLADES_MAGIC 0x4359
57
58#define CYGETMON 0x435901
59#define CYGETTHRESH 0x435902
60#define CYSETTHRESH 0x435903
61#define CYGETDEFTHRESH 0x435904
62#define CYSETDEFTHRESH 0x435905
63#define CYGETTIMEOUT 0x435906
64#define CYSETTIMEOUT 0x435907
65#define CYGETDEFTIMEOUT 0x435908
66#define CYSETDEFTIMEOUT 0x435909
67
68#define CyMaxChipsPerCard 1
69
70/**** cd2401 registers ****/
71
72#define CyGFRCR (0x81)
73#define CyCCR (0x13)
74#define CyCLR_CHAN (0x40)
75#define CyINIT_CHAN (0x20)
76#define CyCHIP_RESET (0x10)
77#define CyENB_XMTR (0x08)
78#define CyDIS_XMTR (0x04)
79#define CyENB_RCVR (0x02)
80#define CyDIS_RCVR (0x01)
81#define CyCAR (0xee)
82#define CyIER (0x11)
83#define CyMdmCh (0x80)
84#define CyRxExc (0x20)
85#define CyRxData (0x08)
86#define CyTxMpty (0x02)
87#define CyTxRdy (0x01)
88#define CyLICR (0x26)
89#define CyRISR (0x89)
90#define CyTIMEOUT (0x80)
91#define CySPECHAR (0x70)
92#define CyOVERRUN (0x08)
93#define CyPARITY (0x04)
94#define CyFRAME (0x02)
95#define CyBREAK (0x01)
96#define CyREOIR (0x84)
97#define CyTEOIR (0x85)
98#define CyMEOIR (0x86)
99#define CyNOTRANS (0x08)
100#define CyRFOC (0x30)
101#define CyRDR (0xf8)
102#define CyTDR (0xf8)
103#define CyMISR (0x8b)
104#define CyRISR (0x89)
105#define CyTISR (0x8a)
106#define CyMSVR1 (0xde)
107#define CyMSVR2 (0xdf)
108#define CyDSR (0x80)
109#define CyDCD (0x40)
110#define CyCTS (0x20)
111#define CyDTR (0x02)
112#define CyRTS (0x01)
113#define CyRTPRL (0x25)
114#define CyRTPRH (0x24)
115#define CyCOR1 (0x10)
116#define CyPARITY_NONE (0x00)
117#define CyPARITY_E (0x40)
118#define CyPARITY_O (0xC0)
119#define Cy_5_BITS (0x04)
120#define Cy_6_BITS (0x05)
121#define Cy_7_BITS (0x06)
122#define Cy_8_BITS (0x07)
123#define CyCOR2 (0x17)
124#define CyETC (0x20)
125#define CyCtsAE (0x02)
126#define CyCOR3 (0x16)
127#define Cy_1_STOP (0x02)
128#define Cy_2_STOP (0x04)
129#define CyCOR4 (0x15)
130#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
131#define CyCOR5 (0x14)
132#define CyCOR6 (0x18)
133#define CyCOR7 (0x07)
134#define CyRBPR (0xcb)
135#define CyRCOR (0xc8)
136#define CyTBPR (0xc3)
137#define CyTCOR (0xc0)
138#define CySCHR1 (0x1f)
139#define CySCHR2 (0x1e)
140#define CyTPR (0xda)
141#define CyPILR1 (0xe3)
142#define CyPILR2 (0xe0)
143#define CyPILR3 (0xe1)
144#define CyCMR (0x1b)
145#define CyASYNC (0x02)
146#define CyLICR (0x26)
147#define CyLIVR (0x09)
148#define CySCRL (0x23)
149#define CySCRH (0x22)
150#define CyTFTC (0x80)
151
152
153/* max number of chars in the FIFO */
154
155#define CyMAX_CHAR_FIFO 12
156
157/***************************************************************************/
diff --git a/include/linux/stallion.h b/include/linux/stallion.h
deleted file mode 100644
index 336af33c6ea4..000000000000
--- a/include/linux/stallion.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * stallion.h -- stallion multiport serial driver.
5 *
6 * Copyright (C) 1996-1998 Stallion Technologies
7 * Copyright (C) 1994-1996 Greg Ungerer.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24/*****************************************************************************/
25#ifndef _STALLION_H
26#define _STALLION_H
27/*****************************************************************************/
28
29/*
30 * Define important driver constants here.
31 */
32#define STL_MAXBRDS 4
33#define STL_MAXPANELS 4
34#define STL_MAXBANKS 8
35#define STL_PORTSPERPANEL 16
36#define STL_MAXPORTS 64
37#define STL_MAXDEVS (STL_MAXBRDS * STL_MAXPORTS)
38
39
40/*
41 * Define a set of structures to hold all the board/panel/port info
42 * for our ports. These will be dynamically allocated as required.
43 */
44
45/*
46 * Define a ring queue structure for each port. This will hold the
47 * TX data waiting to be output. Characters are fed into this buffer
48 * from the line discipline (or even direct from user space!) and
49 * then fed into the UARTs during interrupts. Will use a classic ring
50 * queue here for this. The good thing about this type of ring queue
51 * is that the head and tail pointers can be updated without interrupt
52 * protection - since "write" code only needs to change the head, and
53 * interrupt code only needs to change the tail.
54 */
55struct stlrq {
56 char *buf;
57 char *head;
58 char *tail;
59};
60
61/*
62 * Port, panel and board structures to hold status info about each.
63 * The board structure contains pointers to structures for each panel
64 * connected to it, and in turn each panel structure contains pointers
65 * for each port structure for each port on that panel. Note that
66 * the port structure also contains the board and panel number that it
67 * is associated with, this makes it (fairly) easy to get back to the
68 * board/panel info for a port.
69 */
70struct stlport {
71 unsigned long magic;
72 struct tty_port port;
73 unsigned int portnr;
74 unsigned int panelnr;
75 unsigned int brdnr;
76 int ioaddr;
77 int uartaddr;
78 unsigned int pagenr;
79 unsigned long istate;
80 int baud_base;
81 int custom_divisor;
82 int close_delay;
83 int closing_wait;
84 int openwaitcnt;
85 int brklen;
86 unsigned int sigs;
87 unsigned int rxignoremsk;
88 unsigned int rxmarkmsk;
89 unsigned int imr;
90 unsigned int crenable;
91 unsigned long clk;
92 unsigned long hwid;
93 void *uartp;
94 comstats_t stats;
95 struct stlrq tx;
96};
97
98struct stlpanel {
99 unsigned long magic;
100 unsigned int panelnr;
101 unsigned int brdnr;
102 unsigned int pagenr;
103 unsigned int nrports;
104 int iobase;
105 void *uartp;
106 void (*isr)(struct stlpanel *panelp, unsigned int iobase);
107 unsigned int hwid;
108 unsigned int ackmask;
109 struct stlport *ports[STL_PORTSPERPANEL];
110};
111
112struct stlbrd {
113 unsigned long magic;
114 unsigned int brdnr;
115 unsigned int brdtype;
116 unsigned int state;
117 unsigned int nrpanels;
118 unsigned int nrports;
119 unsigned int nrbnks;
120 int irq;
121 int irqtype;
122 int (*isr)(struct stlbrd *brdp);
123 unsigned int ioaddr1;
124 unsigned int ioaddr2;
125 unsigned int iosize1;
126 unsigned int iosize2;
127 unsigned int iostatus;
128 unsigned int ioctrl;
129 unsigned int ioctrlval;
130 unsigned int hwid;
131 unsigned long clk;
132 unsigned int bnkpageaddr[STL_MAXBANKS];
133 unsigned int bnkstataddr[STL_MAXBANKS];
134 struct stlpanel *bnk2panel[STL_MAXBANKS];
135 struct stlpanel *panels[STL_MAXPANELS];
136};
137
138
139/*
140 * Define MAGIC numbers used for above structures.
141 */
142#define STL_PORTMAGIC 0x5a7182c9
143#define STL_PANELMAGIC 0x7ef621a1
144#define STL_BOARDMAGIC 0xa2267f52
145
146/*****************************************************************************/
147#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 10:32:48 -0500