diff options
-rw-r--r-- | arch/mips/ath79/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index b91ad3efe29e..d2728573e9fc 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c | |||
@@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(void) | |||
189 | AR934X_PLL_CPU_CONFIG_NFRAC_MASK; | 189 | AR934X_PLL_CPU_CONFIG_NFRAC_MASK; |
190 | 190 | ||
191 | cpu_pll = nint * ath79_ref_clk.rate / ref_div; | 191 | cpu_pll = nint * ath79_ref_clk.rate / ref_div; |
192 | cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); | 192 | cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); |
193 | cpu_pll /= (1 << out_div); | 193 | cpu_pll /= (1 << out_div); |
194 | 194 | ||
195 | pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); | 195 | pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); |
@@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(void) | |||
203 | AR934X_PLL_DDR_CONFIG_NFRAC_MASK; | 203 | AR934X_PLL_DDR_CONFIG_NFRAC_MASK; |
204 | 204 | ||
205 | ddr_pll = nint * ath79_ref_clk.rate / ref_div; | 205 | ddr_pll = nint * ath79_ref_clk.rate / ref_div; |
206 | ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); | 206 | ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); |
207 | ddr_pll /= (1 << out_div); | 207 | ddr_pll /= (1 << out_div); |
208 | 208 | ||
209 | clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); | 209 | clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); |